sta-constraints.md

STA Timing Constraints

The industry-standard method of specifying STA timing constraints is the Synopsys Design Constraints (SDC) format. This is a text file that specifies the timing requirements for the design. The constraints are used by the synthesis and place-and-route tools to optimize the design for the desired performance. This is used in tools like Design Compiler, ICC, and PrimeTime as well as OpenROAD and OpenLane.

Input constraints

Output constraints

Clocks

Timing Exceptions

set_false_path set_multi_cycle_path

Ideal vs propagated clocks

set_propagated_clock

License

Copyright 2024 VLSI-DA (see LICENSE for use)