Fall 2022, EE231001 Logic Design Laboratory, 李濬屹(LEE, CHUN-YI)
Introduction to the basic concepts in logic design that form the basis of computation and communication circuits. Verilog and FPGA implementations. Logic gates and memory elements. Timing methodologies. Finite state systems. Programmable logic. Basic computer organization.
Dmux_1x4_4bit: PASS
Crossbar_2x2_4bit: PASS
Crossbar_4x4_4bit: PASS
Toggle_Flip_Flop: PASS
Ripple_Carry_Adder: PASS
Decode_And_Execute: FAIL
Carry_Look_Ahead_Adder_8bit: PASS
Multiplier_4bit: PASS
Exhausted_Testing: FAIL
Ping_Pong_Counter: PASS
FIFO_8: FAIL
Multi_Bank_Memory: SYN_ERROR
Round_Robin_FIFO_Arbiter: SYN_ERROR
Parameterized_Ping_Pong_Counter: PASS
Content_Addressable_Memory: PASS
Scan_Chain_Design: PASS
Built_In_Self_Test: PASS
Mealy_Sequence_Detector: PASS
Sliding_Window_Sequence_Detector: PASS
Traffic_Light_Controller: FAIL
Greatest_Common_Divisor: TIMEOUT
Booth_Multiplier_4bit: FILE_DNE
Lab 1: Gate-level modeling
Lab 2: Data-flow modeling and Behavioral modeling
Lab 3: Sequential circuits & FPGA board
Lab 4: Finite State Machines & FPGA board
Lab 5: Advanced circuit implementation, Finite State Machine, and FPGA board
Lab 6: Short-term project
Final Project: The students will submit a proposal, then exercise their creativity to build a small course project.
There is no required textbook