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py/tt/placer: Use non-assigned analog slots for digital modules formal #120: Commit 21c67d0 pushed by smunaut
March 16, 2024 12:17 29s dev
dev
March 16, 2024 12:17 29s
py/placer: Don't place modules on non-existent mux formal #119: Commit 167d965 pushed by smunaut
March 15, 2024 22:17 28s dev
dev
March 15, 2024 22:17 28s
[of] ol2/tt_top: Use GPIO local tie-off points instead of global k01 formal #118: Commit d3f5d73 pushed by smunaut
March 14, 2024 09:32 5m 35s dev
dev
March 14, 2024 09:32 5m 35s
pg: Add basic modeling of the power gate behavior formal #117: Commit 6efa0f9 pushed by smunaut
March 13, 2024 22:35 5m 46s dev
dev
March 13, 2024 22:35 5m 46s
[of] formal/py: Update the modules.yaml generation script for OF formal #116: Commit 76803d3 pushed by smunaut
March 13, 2024 20:34 5m 40s dev
dev
March 13, 2024 20:34 5m 40s
py/tt: Enable power gate by default if not specified formal #115: Commit 44b469a pushed by smunaut
March 13, 2024 20:05 2m 11s dev
dev
March 13, 2024 20:05 2m 11s
[of] formal: Update the tt_formal.v with new pin mapping formal #114: Commit c4eff98 pushed by smunaut
March 13, 2024 16:03 4m 27s dev
dev
March 13, 2024 16:03 4m 27s
docs: update pinout for TT06 formal #113: Commit 8801767 pushed by smunaut
March 13, 2024 14:24 2m 49s dev
dev
March 13, 2024 14:24 2m 49s
docs: update pinout for TT06 formal #112: Commit 76844e1 pushed by urish
January 2, 2024 09:10 4m 10s tt06-staging
tt06-staging
January 2, 2024 09:10 4m 10s
docs: explain mux addressing scheme formal #111: Commit bb1b9a2 pushed by urish
November 28, 2023 09:37 4m 2s main
main
November 28, 2023 09:37 4m 2s
ol2: update config for latest OpenLane 2 formal #110: Commit ec51999 pushed by urish
November 18, 2023 22:02 4m 3s tt06-staging
tt06-staging
November 18, 2023 22:02 4m 3s
[openframe] 32 mux rows (512 tiles) formal #109: Commit b15952b pushed by urish
November 17, 2023 23:52 3m 55s tt06-staging
tt06-staging
November 17, 2023 23:52 3m 55s
fix: workaround routing issues formal #108: Commit 303e85f pushed by urish
November 6, 2023 19:31 6m 42s gf180mcu
gf180mcu
November 6, 2023 19:31 6m 42s
fix: wrong pin positions formal #107: Commit 09f00b1 pushed by urish
November 6, 2023 18:49 4m 20s gf180mcu
gf180mcu
November 6, 2023 18:49 4m 20s
WiP experimental gf180 support formal #106: Commit c3df9d2 pushed by urish
November 6, 2023 16:45 12s gf180mcu
gf180mcu
November 6, 2023 16:45 12s
ol2/tt_top: mask_rev support formal #105: Commit 8201885 pushed by urish
November 6, 2023 12:09 7m 8s tt05-openframe
tt05-openframe
November 6, 2023 12:09 7m 8s
ol2/tt_autosel: add tt_autosel macro formal #104: Commit 84922e8 pushed by urish
November 6, 2023 10:43 6m 5s tt05-openframe
tt05-openframe
November 6, 2023 10:43 6m 5s
WiP experimental gf180 support formal #103: Commit a48d226 pushed by urish
November 5, 2023 22:31 5m 37s gf180mcu
gf180mcu
November 5, 2023 22:31 5m 37s
[tt05] Set pin 33/35 as input for the analog test formal #102: Commit d19a01d pushed by urish
November 4, 2023 22:29 4m 57s tt05-release
tt05-release
November 4, 2023 22:29 4m 57s
[openframe] initial openframe support WiP formal #101: Commit a4053e7 pushed by urish
November 3, 2023 16:41 5m 31s tt05-openframe
tt05-openframe
November 3, 2023 16:41 5m 31s
[openframe] initial openframe support WiP formal #100: Commit 8c9bc07 pushed by urish
November 2, 2023 22:42 5m 5s tt05-openframe
tt05-openframe
November 2, 2023 22:42 5m 5s
[opnframe] initial openframe support WiP formal #99: Commit 1d81bf3 pushed by urish
November 2, 2023 18:42 4m 6s tt05-openframe
tt05-openframe
November 2, 2023 18:42 4m 6s
[opnframe] initial openframe support WiP formal #98: Commit 0aecf82 pushed by urish
November 2, 2023 18:29 6m 41s tt05-openframe
tt05-openframe
November 2, 2023 18:29 6m 41s
[opnframe] initial openframe support WiP formal #97: Commit fd23b0e pushed by urish
November 2, 2023 17:53 5m 31s tt05-openframe
tt05-openframe
November 2, 2023 17:53 5m 31s
[opnframe] initial openframe support WiP formal #96: Commit fe0e41e pushed by urish
November 2, 2023 14:54 6m 16s tt05-openframe
tt05-openframe
November 2, 2023 14:54 6m 16s