sim: Hack for sg13g2 #182
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| name: formal | |
| # either manually started, or on a schedule | |
| on: [ push, workflow_dispatch, pull_request ] | |
| jobs: | |
| formal: | |
| # ubuntu | |
| runs-on: ubuntu-latest | |
| steps: | |
| # need the repo checked out | |
| - name: checkout repo | |
| uses: actions/checkout@v3 | |
| # install oss fpga tools for cocotb and iverilog | |
| - name: install oss-cad-suite | |
| uses: YosysHQ/setup-oss-cad-suite@v2 | |
| with: | |
| github-token: ${{ secrets.GITHUB_TOKEN }} | |
| - run: | | |
| yosys --version | |
| - name: python requirements | |
| run: pip3 install -r py/requirements.txt | |
| # formal | |
| - name: formal tristate | |
| run: | | |
| make formal_tristate | |
| - name: formal tristate | |
| run: | | |
| make formal_connectivity |