feat: update project tt_um_ancho from LuisVazpez12/PWM_configurable

Commit: a5eb66c983b6e4d0f352cbe65a5b952ce056e324
Workflow: https://github.com/LuisVazpez12/PWM_configurable/actions/runs/8757612449

projects/tt_um_ancho/LICENSE

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projects/tt_um_ancho/commit_id.json

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+{
+  "app": "Tiny Tapeout tt06 7f56a586",
+  "repo": "https://github.com/LuisVazpez12/PWM_configurable",
+  "commit": "a5eb66c983b6e4d0f352cbe65a5b952ce056e324",
+  "workflow_url": "https://github.com/LuisVazpez12/PWM_configurable/actions/runs/8757612449",
+  "sort_id": 1713549494318,
+  "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
+}

projects/tt_um_ancho/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## How it works
+El PWM configurable de ciclo de trabajo incrementales un dispositivo diseñado para generar señales PWM (Modulación por Ancho de Pulso) con ciclos de trabajo incrementales basados en tres señales de entrada digitales. Este dispositivo permite una fácil configuración del ciclo de trabajo para adaptarse a una variedad de aplicaciones. El ciclo de trabajo será incremental con valor de 12.5% para cada combinación de entrada.
+
+## How to test
+Usando los puertos de entrada en combinacion de estados logicos y con un uno logico en enable, puede visualizarse en la salida como la señal de ancho de pulso varia de acuerdo a las siguientes combinaciones:
+000=12.5%
+001=25%
+010=37.5%
+011=50%
+100=62.5%
+101=75%
+110=87.5%
+111=100%
+
+## External hardware
+Generador de señales para generar la señal de reloj de 10MHz, osciloscopio para poder visualizar el ancho del pulso.

projects/tt_um_ancho/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "Circuito PWM con ciclo de trabajo configurable"      # Project title
+  author:       "Maria Fernanda Tovany Salvador, Javier Trucios Alonso & Luis David Vazquez Perez"      # Your name
+  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  " A partir de tres senales de entrada digitales selecciona el ciclo de trabajo de salida (PWM)."      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_ancho"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "tt_um_ancho.v"
+    - "ancho.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "no use"
+  ui[1]: "no use"
+  ui[2]: "no use"
+  ui[3]: "speed[0]"
+  ui[4]: "speed[1]"
+  ui[5]: "speed[3]"
+  ui[6]: "enable"
+  ui[7]: "clock"
+
+  # Outputs
+  uo[0]: "PWM"
+  uo[1]: "no use"
+  uo[2]: "no use"
+  uo[3]: "no use"
+  uo[4]: "no use"
+  uo[5]: "no use"
+  uo[6]: "no use"
+  uo[7]: "no use"
+
+  # Bidirectional pins
+  uio[0]: "no use"
+  uio[1]: "no use"
+  uio[2]: "no use"
+  uio[3]: "no use"
+  uio[4]: "no use"
+  uio[5]: "no use"
+  uio[6]: "no use"
+  uio[7]: "no use"
+
+# Do not change!
+yaml_version: 6

projects/tt_um_ancho/stats/metrics.csv

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+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_ancho,wokwi,flow completed,0h0m49s0ms,0h0m33s0ms,6572.08800805582,0.01795472,3286.04400402791,2.57,4.16477,484.49,54,0,0,0,0,0,0,0,0,0,0,-1,-1,465,302,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,399575.0,0.0,0.91,0.6,0.04,0.0,-1,45,90,15,60,0,0,0,36,2,6,2,2,2,4,3,0,9,12,3,1220,225,0,249,59,1753,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_ancho/stats/synthesis-stats.txt

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+
+64. Printing statistics.
+
+=== tt_um_ancho ===
+
+   Number of wires:                 38
+   Number of wire bits:             73
+   Number of public wires:          14
+   Number of public wire bits:      49
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 54
+     sky130_fd_sc_hd__a21oi_2        3
+     sky130_fd_sc_hd__a22o_2         2
+     sky130_fd_sc_hd__and3_2         1
+     sky130_fd_sc_hd__and4_2         1
+     sky130_fd_sc_hd__buf_1          1
+     sky130_fd_sc_hd__buf_2          1
+     sky130_fd_sc_hd__conb_1        23
+     sky130_fd_sc_hd__dfrtp_2        6
+     sky130_fd_sc_hd__inv_2          9
+     sky130_fd_sc_hd__nor2_2         2
+     sky130_fd_sc_hd__nor3_2         1
+     sky130_fd_sc_hd__o21a_2         3
+     sky130_fd_sc_hd__o22a_2         1
+
+   Chip area for module '\tt_um_ancho': 409.142400
+