feat: update project tt_um_nurirfansyah_alits01 from nurirfansyah/tt0…

…6-analog-its_ip_alits01

Commit: fe4a3a7b39162c78a9923e87c3e209f877ff1329
Workflow: https://github.com/nurirfansyah/tt06-analog-its_ip_alits01/actions/runs/8757979613

projects/tt_um_nurirfansyah_alits01/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "custom_gds action",
   "repo": "https://github.com/nurirfansyah/tt06-analog-its_ip_alits01",
-  "commit": "576c80e7c1f61fb211267bd656d286da66ce9bc1",
-  "workflow_url": "https://github.com/nurirfansyah/tt06-analog-its_ip_alits01/actions/runs/8755842436",
+  "commit": "fe4a3a7b39162c78a9923e87c3e209f877ff1329",
+  "workflow_url": "https://github.com/nurirfansyah/tt06-analog-its_ip_alits01/actions/runs/8757979613",
   "sort_id": 1713517171709,
   "analog": true
 }

projects/tt_um_nurirfansyah_alits01/info.yaml

@@ -3,7 +3,7 @@ project:
   title:        "Analog Test Circuit ITS: VCO"      # Project title
   author:       "Astria Nur Irfansyah"      # Your name
   discord:      "irfansyah_99806"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "A voltage controlled ring oscillator. "      # One line description of what your project does
+  description:  "Voltage controlled ring oscillator. "      # One line description of what your project does
   language:     "Analog" # other examples include Verilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -30,12 +30,12 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
+  uo[0]: "out5"
+  uo[1]: "out4"
+  uo[2]: "out3"
+  uo[3]: "out2"
+  uo[4]: "out1"
+  uo[5]: "out0"
   uo[6]: ""
   uo[7]: ""