feat: update project tt_um_factory_test from TinyTapeout/tt06-factory…

…-test

Commit: a83879c6a55b3b8236d6ff47ac36b3b18488a727
Workflow: https://github.com/TinyTapeout/tt06-factory-test/actions/runs/7426309667

projects/tt_um_factory_test/commit_id.json

@@ -1,9 +1,9 @@
 {
-  "app": "Tiny Tapeout tt05 562ebd4f",
-  "repo": "https://github.com/TinyTapeout/tt05-factory-test",
-  "commit": "901461a50ef7aeda53262e030f4511c072ff5bf8",
-  "workflow_url": "https://github.com/TinyTapeout/tt05-factory-test/actions/runs/6500162402",
-  "sort_id": 1700321067877,
-  "openlane_version": "OpenLane 7e5a2e9fb274c0a100b4859a927adce7089455ff",
-  "power_gate": false
+  "app": "Tiny Tapeout tt06 66e1fc3f",
+  "repo": "https://github.com/TinyTapeout/tt06-factory-test",
+  "commit": "a83879c6a55b3b8236d6ff47ac36b3b18488a727",
+  "workflow_url": "https://github.com/TinyTapeout/tt06-factory-test/actions/runs/7426309667",
+  "sort_id": 1706521817227,
+  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
+  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
 }

projects/tt_um_factory_test/info.yaml

@@ -1,53 +1,53 @@
 # Tiny Tapeout project information
 project:
-  title:        "TinyTapeout 05 Factory Test"      # Project title
+  title:        "TinyTapeout 06 Factory Test"      # Project title
   author:       "Sylvain Munaut"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Factory test module"      # One line description of what your project does
-  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_factory_test"
-
+  
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
-  source_files:
+  source_files:        
     - "tt_um_factory_test.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "sel / data_i[0]"
-  ui[1]: "data_i[1]"
-  ui[2]: "data_i[2]"
-  ui[3]: "data_i[3]"
-  ui[4]: "data_i[4]"
-  ui[5]: "data_i[5]"
-  ui[6]: "data_i[6]"
-  ui[7]: "data_i[7]"
+  ui[0]: "sel"
+  ui[1]: ""
+  ui[2]: ""
+  ui[3]: ""
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
 
   # Outputs
-  uo[0]: "data_o[0] (when sel=0) / counter_o[0] (when sel=1)"
-  uo[1]: "data_o[1] (when sel=0) / counter_o[1] (when sel=1)"
-  uo[2]: "data_o[2] (when sel=0) / counter_o[2] (when sel=1)"
-  uo[3]: "data_o[3] (when sel=0) / counter_o[3] (when sel=1)"
-  uo[4]: "data_o[4] (when sel=0) / counter_o[4] (when sel=1)"
-  uo[5]: "data_o[5] (when sel=0) / counter_o[5] (when sel=1)"
-  uo[6]: "data_o[6] (when sel=0) / counter_o[6] (when sel=1)"
-  uo[7]: "data_o[7] (when sel=0) / counter_o[7] (when sel=1)"
+  uo[0]: "data_o[0]"
+  uo[1]: "data_o[1]"
+  uo[2]: "data_o[2]"
+  uo[3]: "data_o[3]"
+  uo[4]: "data_o[4]"
+  uo[5]: "data_o[5]"
+  uo[6]: "data_o[6]"
+  uo[7]: "data_o[7]"
 
   # Bidirectional pins
-  uio[0]: "counter_o[0]"
-  uio[1]: "counter_o[1]"
-  uio[2]: "counter_o[2]"
-  uio[3]: "counter_o[3]"
-  uio[4]: "counter_o[4]"
-  uio[5]: "counter_o[5]"
-  uio[6]: "counter_o[6]"
-  uio[7]: "counter_o[7]"
+  uio[0]: "data_i[0] / counter_o[0]"
+  uio[1]: "data_i[1] / counter_o[1]"
+  uio[2]: "data_i[2] / counter_o[2]"
+  uio[3]: "data_i[3] / counter_o[3]"
+  uio[4]: "data_i[4] / counter_o[4]"
+  uio[5]: "data_i[5] / counter_o[5]"
+  uio[6]: "data_i[6] / counter_o[6]"
+  uio[7]: "data_i[7] / counter_o[7]"
 
 # Do not change!
 yaml_version: 6

projects/tt_um_factory_test/stats/metrics.csv

@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_factory_test,wokwi,flow completed,0h1m15s0ms,0h0m59s0ms,10248.001639680262,0.01795472,5124.000819840131,4.06,86.2312,477.32,69,0,0,0,0,0,0,0,0,0,0,-1,-1,1803,540,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1256569.0,0.0,4.44,1.18,1.19,1.74,-1,20,76,10,52,0,0,0,41,8,9,3,0,2,4,3,8,17,24,4,1190,225,0,242,92,1749,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_factory_test/stats/synthesis-stats.txt

@@ -0,0 +1,33 @@
+
+62. Printing statistics.
+
+=== tt_um_factory_test ===
+
+   Number of wires:                 53
+   Number of wire bits:             88
+   Number of public wires:          17
+   Number of public wire bits:      52
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 69
+     sky130_fd_sc_hd__a21oi_2        1
+     sky130_fd_sc_hd__a31o_2         1
+     sky130_fd_sc_hd__and2_2         9
+     sky130_fd_sc_hd__and2b_2        1
+     sky130_fd_sc_hd__and3_2         1
+     sky130_fd_sc_hd__and4_2         2
+     sky130_fd_sc_hd__buf_1         19
+     sky130_fd_sc_hd__buf_2          8
+     sky130_fd_sc_hd__conb_1         1
+     sky130_fd_sc_hd__dfrtp_2        9
+     sky130_fd_sc_hd__inv_2          1
+     sky130_fd_sc_hd__mux2_2         8
+     sky130_fd_sc_hd__nand2_2        1
+     sky130_fd_sc_hd__nor2_2         3
+     sky130_fd_sc_hd__or2_2          1
+     sky130_fd_sc_hd__xnor2_2        1
+     sky130_fd_sc_hd__xor2_2         2
+
+   Chip area for module '\tt_um_factory_test': 646.870400
+