diff --git a/configs/AM62AX/AM62AX_linux_toc.txt b/configs/AM62AX/AM62AX_linux_toc.txt index a0ac20965..1b4f090b1 100644 --- a/configs/AM62AX/AM62AX_linux_toc.txt +++ b/configs/AM62AX/AM62AX_linux_toc.txt @@ -110,6 +110,7 @@ linux/How_to_Guides/Host/K3_Resource_Partitioning_Tool #linux/How_to_Guides/Host/How_to_Setup_and_Debug_using_Lauterbach linux/How_to_Guides/Host/SYSFW_Trace_Parser linux/How_to_Guides/Target/Processor_SDK_Linux_File_System_Optimization_Customization +linux/How_to_Guides/Target/How_to_boot_quickly linux/How_to_Guides/Target/How_to_test_MCAN_on_AM62x linux/How_to_Guides/Target/How_to_enable_DT_overlays_in_linux linux/How_to_Guides/Target/How_to_playback_audio_over_HDMI diff --git a/configs/AM62PX/AM62PX_linux_toc.txt b/configs/AM62PX/AM62PX_linux_toc.txt index 06dfdfd7d..d9f650f62 100644 --- a/configs/AM62PX/AM62PX_linux_toc.txt +++ b/configs/AM62PX/AM62PX_linux_toc.txt @@ -132,6 +132,7 @@ linux/How_to_Guides/Target/How_to_test_MCAN_on_AM62x linux/How_to_Guides/Target/How_to_enable_DT_overlays_in_linux linux/How_to_Guides/Target/How_to_playback_audio_over_HDMI linux/How_to_Guides/Target/How_to_enable_display_sharing_between_remotecore_and_Linux +linux/How_to_Guides/Target/How_to_boot_quickly linux/How_to_Guides/Target/How_to_enable_Microtips_LVDS_Panel linux/How_to_Guides/Target/How_to_Use_K3Conf_Tool linux/How_to_Guides/Target/Runtime_debug_unlock_on_secure_device diff --git a/configs/AM62X/AM62X_linux_toc.txt b/configs/AM62X/AM62X_linux_toc.txt index 09282210b..174678d95 100644 --- a/configs/AM62X/AM62X_linux_toc.txt +++ b/configs/AM62X/AM62X_linux_toc.txt @@ -132,6 +132,7 @@ linux/How_to_Guides/Host/K3_Resource_Partitioning_Tool linux/How_to_Guides/Host/How_to_Setup_and_Debug_using_Lauterbach linux/How_to_Guides/Host/SYSFW_Trace_Parser linux/How_to_Guides/Target/Processor_SDK_Linux_File_System_Optimization_Customization +linux/How_to_Guides/Target/How_to_boot_quickly #linux/How_to_Guides/Target/How_to_flash_emmc_device # We do not support this for now linux/How_to_Guides/Target/How_to_suspend_to_ram_on_AM62x linux/How_to_Guides/Target/How_to_test_MCAN_on_AM62x diff --git a/source/files/AM62P-Change-DMA-allocation.patch b/source/files/AM62P-Change-DMA-allocation.patch new file mode 100644 index 000000000..98d2d55ac --- /dev/null +++ b/source/files/AM62P-Change-DMA-allocation.patch @@ -0,0 +1,107 @@ +From 17508b3e3a8991ecc0cf767ad2302d34141b8616 Mon Sep 17 00:00:00 2001 +From: Aashvij Shenai +Date: Fri, 29 Mar 2024 15:40:53 +0530 +Subject: [PATCH] am62px: Change DMA allocation + +This patch removes the DMA channel allocations fo A53 and MCU cores so +that the first channels are allocated to DM R5. This will be used to +demonstrate the use of High Capacity BCDMA channels. In Am62Px, there +are 4 HC channels +--- + .../am62px/sciclient_defaultBoardcfg_rm.c | 42 ++++--------------- + 1 file changed, 9 insertions(+), 33 deletions(-) + +diff --git a/source/drivers/sciclient/sciclient_default_boardcfg/am62px/sciclient_defaultBoardcfg_rm.c b/source/drivers/sciclient/sciclient_default_boardcfg/am62px/sciclient_defaultBoardcfg_rm.c +index a22e6f6b4459..05d228843932 100644 +--- a/source/drivers/sciclient/sciclient_default_boardcfg/am62px/sciclient_defaultBoardcfg_rm.c ++++ b/source/drivers/sciclient/sciclient_default_boardcfg/am62px/sciclient_defaultBoardcfg_rm.c +@@ -96,7 +96,7 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) = + .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM, + .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg), + }, +- .resasg_entries_size = 123 * sizeof(struct tisci_boardcfg_rm_resasg_entry), ++ .resasg_entries_size = 119 * sizeof(struct tisci_boardcfg_rm_resasg_entry), + }, + }, + .resasg_entries = { +@@ -154,34 +154,22 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) = + .start_resource = 0, + .host_id = TISCI_HOST_ID_ALL, + }, +- { +- .num_resource = 18, +- .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN), +- .start_resource = 0, +- .host_id = TISCI_HOST_ID_A53_2, +- }, + { + .num_resource = 6, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN), +- .start_resource = 18, ++ .start_resource = 0, + .host_id = TISCI_HOST_ID_WKUP_0_R5_0, + }, + { + .num_resource = 6, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN), +- .start_resource = 18, ++ .start_resource = 0, + .host_id = TISCI_HOST_ID_WKUP_0_R5_1, + }, + { +- .num_resource = 2, +- .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN), +- .start_resource = 24, +- .host_id = TISCI_HOST_ID_MCU_0_R5_0, +- }, +- { +- .num_resource = 6, ++ .num_resource = 26, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN), +- .start_resource = 26, ++ .start_resource = 6, + .host_id = TISCI_HOST_ID_ALL, + }, + { +@@ -238,34 +226,22 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) = + .start_resource = 52, + .host_id = TISCI_HOST_ID_ALL, + }, +- { +- .num_resource = 18, +- .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN), +- .start_resource = 0, +- .host_id = TISCI_HOST_ID_A53_2, +- }, + { + .num_resource = 6, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN), +- .start_resource = 18, ++ .start_resource = 0, + .host_id = TISCI_HOST_ID_WKUP_0_R5_0, + }, + { + .num_resource = 6, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN), +- .start_resource = 18, ++ .start_resource = 0, + .host_id = TISCI_HOST_ID_WKUP_0_R5_1, + }, + { +- .num_resource = 2, +- .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN), +- .start_resource = 24, +- .host_id = TISCI_HOST_ID_MCU_0_R5_0, +- }, +- { +- .num_resource = 6, ++ .num_resource = 26, + .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN), +- .start_resource = 26, ++ .start_resource = 6, + .host_id = TISCI_HOST_ID_ALL, + }, + { +-- +2.34.1 + diff --git a/source/files/am62ax_nor.patch b/source/files/am62ax_nor.patch new file mode 100644 index 000000000..91ced8043 --- /dev/null +++ b/source/files/am62ax_nor.patch @@ -0,0 +1,165 @@ +From 46fc19268d993d410607c5a99b9d9a6f21dff812 Mon Sep 17 00:00:00 2001 +From: Aashvij Shenai +Date: Wed, 27 Mar 2024 16:01:57 +0530 +Subject: [PATCH] am62ax: Use NOR + +Signed-off-by: Aashvij Shenai +--- + arch/arm/dts/k3-am62a-main.dtsi | 3 +-- + arch/arm/dts/k3-am62a7-sk-u-boot.dtsi | 4 ++++ + arch/arm/dts/k3-am62a7-sk.dts | 10 +++++----- + configs/am62ax_evm_a53_defconfig | 11 +++++++++-- + configs/am62ax_evm_r5_defconfig | 19 +++++++++++++++++-- + 5 files changed, 36 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi +index 41aec3a82e86..63f33a71101f 100644 +--- a/arch/arm/dts/k3-am62a-main.dtsi ++++ b/arch/arm/dts/k3-am62a-main.dtsi +@@ -553,7 +553,6 @@ + #address-cells = <2>; + #size-cells = <2>; + ranges; +- status = "disabled"; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; +@@ -566,7 +565,7 @@ + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; +- assigned-clock-rates = <166666666>; ++ assigned-clock-rates = <25000000>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +index 090520500570..8de960facff5 100644 +--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi ++++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +@@ -215,6 +215,10 @@ + + partitions { + bootph-pre-ram; ++ ++ partition@3fc0000 { ++ u-boot,dm-spl; ++ }; + }; + }; + }; +diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts +index f727b5f82580..6898b412e9d0 100644 +--- a/arch/arm/dts/k3-am62a7-sk.dts ++++ b/arch/arm/dts/k3-am62a7-sk.dts +@@ -409,7 +409,7 @@ + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ +- compatible = "spi-nand"; ++ compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; +@@ -451,14 +451,14 @@ + reg = <0x6c0000 0x40000>; + }; + +- partition@2000000 { ++ partition@800000 { + label = "ospi_nand.rootfs"; +- reg = <0x2000000 0x5fc0000>; ++ reg = <0x800000 0x37c0000>; + }; + +- partition@7fc0000 { ++ partition@3fc0000 { + label = "ospi_nand.phypattern"; +- reg = <0x7fc0000 0x40000>; ++ reg = <0x3fc0000 0x40000>; + }; + }; + }; +diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig +index 5442796a82e7..bbb1c01d71f4 100644 +--- a/configs/am62ax_evm_a53_defconfig ++++ b/configs/am62ax_evm_a53_defconfig +@@ -48,8 +48,9 @@ CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_MTD_SUPPORT=y + CONFIG_SPL_MTD_LOAD=y + CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000 +-CONFIG_SPL_NAND_SPI_SUPPORT=y + CONFIG_SPL_DM_SPI_FLASH=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUPPORT=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_USB_GADGET=y +@@ -117,8 +118,14 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y + CONFIG_MMC_SDHCI_AM654=y + CONFIG_MTD=y + CONFIG_DM_MTD=y +-CONFIG_MTD_SPI_NAND=y + CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_SOFT_RESET=y ++CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_S28HX_T=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_MT35XU=y + CONFIG_PHY_TI_DP83867=y + CONFIG_TI_AM65_CPSW_NUSS=y + CONFIG_PINCTRL=y +diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig +index 156d5a188096..7ee8724b672a 100644 +--- a/configs/am62ax_evm_r5_defconfig ++++ b/configs/am62ax_evm_r5_defconfig +@@ -12,6 +12,10 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 + CONFIG_SPL_DM_SPI=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_CADENCE_QSPI=y ++CONFIG_CADENCE_QSPI_PHY=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" + CONFIG_SPL_TEXT_BASE=0x43c00000 + CONFIG_DM_RESET=y +@@ -50,8 +54,12 @@ CONFIG_SPL_DMA=y + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_MTD_SUPPORT=y + CONFIG_SPL_MTD_LOAD=y +-CONFIG_SPL_NAND_SPI_SUPPORT=y ++# CONFIG_SPL_NAND_SPI_SUPPORT=y + CONFIG_SPL_DM_SPI_FLASH=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y + CONFIG_SPL_DM_RESET=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y +@@ -103,8 +111,15 @@ CONFIG_MMC_SDHCI_ADMA=y + CONFIG_MMC_SDHCI_AM654=y + CONFIG_MTD=y + CONFIG_DM_MTD=y +-CONFIG_MTD_SPI_NAND=y + CONFIG_DM_SPI_FLASH=y ++CONFIG_SF_DEFAULT_MODE=0 ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_SOFT_RESET=y ++CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_S28HX_T=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_MT35XU=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_SPL_PINCTRL=y + +base-commit: 7d050099177240f6cdf8992310f2cf4941e954af +prerequisite-patch-id: 26f3054c6516aae6a335c354a876ab1690a42de1 +-- +2.34.1 + diff --git a/source/files/ddr_1600_singlerank_am62p.h b/source/files/ddr_1600_singlerank_am62p.h new file mode 100644 index 000000000..f72bc859a --- /dev/null +++ b/source/files/ddr_1600_singlerank_am62p.h @@ -0,0 +1,3451 @@ +/* Copyright (c) 2022, Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#define DDR_TYPE LPDDR4 + +#ifndef BOARD_DDRREGINIT_H_ +#define BOARD_DDRREGINIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file was generated with the + * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.01 + * Tue Jan 02 2024 15:29:26 GMT-0600 (Central Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1600MHz + * Density (per channel): 16Gb + * Number of Ranks: 1 +*/ + + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 +#define DDRSS_SDRAM_IDX 16 + +#define DDRSS_CTL_REG_INIT_COUNT (435U) +#define DDRSS_PHY_INDEP_REG_INIT_COUNT (424U) +#define DDRSS_PHY_REG_INIT_COUNT (827U) + +uint32_t DDRSS_ctlReg[] = { + 0x00000B00U, // DDRSS_CTL_0_VAL + 0x00000000U, // DDRSS_CTL_1_VAL + 0x00000000U, // DDRSS_CTL_2_VAL + 0x00000000U, // DDRSS_CTL_3_VAL + 0x00000000U, // DDRSS_CTL_4_VAL + 0x00000000U, // DDRSS_CTL_5_VAL + 0x00000000U, // DDRSS_CTL_6_VAL + 0x00002710U, // DDRSS_CTL_7_VAL + 0x000186A0U, // DDRSS_CTL_8_VAL + 0x00000005U, // DDRSS_CTL_9_VAL + 0x00000064U, // DDRSS_CTL_10_VAL + 0x0004E200U, // DDRSS_CTL_11_VAL + 0x0030D400U, // DDRSS_CTL_12_VAL + 0x00000005U, // DDRSS_CTL_13_VAL + 0x00000C80U, // DDRSS_CTL_14_VAL + 0x0004E200U, // DDRSS_CTL_15_VAL + 0x0030D400U, // DDRSS_CTL_16_VAL + 0x00000005U, // DDRSS_CTL_17_VAL + 0x00000C80U, // DDRSS_CTL_18_VAL + 0x01010100U, // DDRSS_CTL_19_VAL + 0x01010100U, // DDRSS_CTL_20_VAL + 0x01000110U, // DDRSS_CTL_21_VAL + 0x02010002U, // DDRSS_CTL_22_VAL + 0x0000000AU, // DDRSS_CTL_23_VAL + 0x000186A0U, // DDRSS_CTL_24_VAL + 0x00000000U, // DDRSS_CTL_25_VAL + 0x00000000U, // DDRSS_CTL_26_VAL + 0x00000000U, // DDRSS_CTL_27_VAL + 0x00000000U, // DDRSS_CTL_28_VAL + 0x00020200U, // DDRSS_CTL_29_VAL + 0x00000000U, // DDRSS_CTL_30_VAL + 0x00000000U, // DDRSS_CTL_31_VAL + 0x00000000U, // DDRSS_CTL_32_VAL + 0x00000000U, // DDRSS_CTL_33_VAL + 0x08000010U, // DDRSS_CTL_34_VAL + 0x00004040U, // DDRSS_CTL_35_VAL + 0x00000000U, // DDRSS_CTL_36_VAL + 0x00000000U, // DDRSS_CTL_37_VAL + 0x00000000U, // DDRSS_CTL_38_VAL + 0x00000000U, // DDRSS_CTL_39_VAL + 0x0000040CU, // DDRSS_CTL_40_VAL + 0x00000000U, // DDRSS_CTL_41_VAL + 0x00000E38U, // DDRSS_CTL_42_VAL + 0x00000000U, // DDRSS_CTL_43_VAL + 0x00000E38U, // DDRSS_CTL_44_VAL + 0x00000000U, // DDRSS_CTL_45_VAL + 0x05000804U, // DDRSS_CTL_46_VAL + 0x00000700U, // DDRSS_CTL_47_VAL + 0x09090004U, // DDRSS_CTL_48_VAL + 0x00000303U, // DDRSS_CTL_49_VAL + 0x00620011U, // DDRSS_CTL_50_VAL + 0x09110045U, // DDRSS_CTL_51_VAL + 0x0000421DU, // DDRSS_CTL_52_VAL + 0x00620011U, // DDRSS_CTL_53_VAL + 0x09110045U, // DDRSS_CTL_54_VAL + 0x0900421DU, // DDRSS_CTL_55_VAL + 0x000A0A09U, // DDRSS_CTL_56_VAL + 0x040006DBU, // DDRSS_CTL_57_VAL + 0x090D2005U, // DDRSS_CTL_58_VAL + 0x00001710U, // DDRSS_CTL_59_VAL + 0x0C00DB60U, // DDRSS_CTL_60_VAL + 0x090D200DU, // DDRSS_CTL_61_VAL + 0x00001710U, // DDRSS_CTL_62_VAL + 0x0C00DB60U, // DDRSS_CTL_63_VAL + 0x0304200DU, // DDRSS_CTL_64_VAL + 0x04050002U, // DDRSS_CTL_65_VAL + 0x1F1E1F1EU, // DDRSS_CTL_66_VAL + 0x01010008U, // DDRSS_CTL_67_VAL + 0x043C3C07U, // DDRSS_CTL_68_VAL + 0x03222203U, // DDRSS_CTL_69_VAL + 0x00002222U, // DDRSS_CTL_70_VAL + 0x00000101U, // DDRSS_CTL_71_VAL + 0x00000000U, // DDRSS_CTL_72_VAL + 0x01000000U, // DDRSS_CTL_73_VAL + 0x00130803U, // DDRSS_CTL_74_VAL + 0x000000BBU, // DDRSS_CTL_75_VAL + 0x00000260U, // DDRSS_CTL_76_VAL + 0x00001858U, // DDRSS_CTL_77_VAL + 0x00000260U, // DDRSS_CTL_78_VAL + 0x00001858U, // DDRSS_CTL_79_VAL + 0x00000005U, // DDRSS_CTL_80_VAL + 0x0000000AU, // DDRSS_CTL_81_VAL + 0x00000010U, // DDRSS_CTL_82_VAL + 0x00000130U, // DDRSS_CTL_83_VAL + 0x00000304U, // DDRSS_CTL_84_VAL + 0x00000130U, // DDRSS_CTL_85_VAL + 0x00000304U, // DDRSS_CTL_86_VAL + 0x03004000U, // DDRSS_CTL_87_VAL + 0x00001201U, // DDRSS_CTL_88_VAL + 0x000C0005U, // DDRSS_CTL_89_VAL + 0x2108000CU, // DDRSS_CTL_90_VAL + 0x0A050521U, // DDRSS_CTL_91_VAL + 0x170C0803U, // DDRSS_CTL_92_VAL + 0x170C0803U, // DDRSS_CTL_93_VAL + 0x03010103U, // DDRSS_CTL_94_VAL + 0x00010301U, // DDRSS_CTL_95_VAL + 0x00140014U, // DDRSS_CTL_96_VAL + 0x026C026CU, // DDRSS_CTL_97_VAL + 0x026C026CU, // DDRSS_CTL_98_VAL + 0x00000000U, // DDRSS_CTL_99_VAL + 0x03030000U, // DDRSS_CTL_100_VAL + 0x05050501U, // DDRSS_CTL_101_VAL + 0x03031804U, // DDRSS_CTL_102_VAL + 0x0C080C08U, // DDRSS_CTL_103_VAL + 0x08030318U, // DDRSS_CTL_104_VAL + 0x030C080CU, // DDRSS_CTL_105_VAL + 0x00000303U, // DDRSS_CTL_106_VAL + 0x00000301U, // DDRSS_CTL_107_VAL + 0x00000001U, // DDRSS_CTL_108_VAL + 0x00000000U, // DDRSS_CTL_109_VAL + 0x40020100U, // DDRSS_CTL_110_VAL + 0x00038010U, // DDRSS_CTL_111_VAL + 0x00050004U, // DDRSS_CTL_112_VAL + 0x00000004U, // DDRSS_CTL_113_VAL + 0x00040003U, // DDRSS_CTL_114_VAL + 0x00040005U, // DDRSS_CTL_115_VAL + 0x00030000U, // DDRSS_CTL_116_VAL + 0x00050004U, // DDRSS_CTL_117_VAL + 0x00000004U, // DDRSS_CTL_118_VAL + 0x00002EC0U, // DDRSS_CTL_119_VAL + 0x00002EC0U, // DDRSS_CTL_120_VAL + 0x00002EC0U, // DDRSS_CTL_121_VAL + 0x00002EC0U, // DDRSS_CTL_122_VAL + 0x00002EC0U, // DDRSS_CTL_123_VAL + 0x00000000U, // DDRSS_CTL_124_VAL + 0x0000051DU, // DDRSS_CTL_125_VAL + 0x00061600U, // DDRSS_CTL_126_VAL + 0x00061600U, // DDRSS_CTL_127_VAL + 0x00061600U, // DDRSS_CTL_128_VAL + 0x00061600U, // DDRSS_CTL_129_VAL + 0x00061600U, // DDRSS_CTL_130_VAL + 0x00000000U, // DDRSS_CTL_131_VAL + 0x0000AA68U, // DDRSS_CTL_132_VAL + 0x00061600U, // DDRSS_CTL_133_VAL + 0x00061600U, // DDRSS_CTL_134_VAL + 0x00061600U, // DDRSS_CTL_135_VAL + 0x00061600U, // DDRSS_CTL_136_VAL + 0x00061600U, // DDRSS_CTL_137_VAL + 0x00000000U, // DDRSS_CTL_138_VAL + 0x0000AA68U, // DDRSS_CTL_139_VAL + 0x00000000U, // DDRSS_CTL_140_VAL + 0x00000000U, // DDRSS_CTL_141_VAL + 0x00000000U, // DDRSS_CTL_142_VAL + 0x00000000U, // DDRSS_CTL_143_VAL + 0x00000000U, // DDRSS_CTL_144_VAL + 0x00000000U, // DDRSS_CTL_145_VAL + 0x00000000U, // DDRSS_CTL_146_VAL + 0x00000000U, // DDRSS_CTL_147_VAL + 0x00000000U, // DDRSS_CTL_148_VAL + 0x00000000U, // DDRSS_CTL_149_VAL + 0x00000000U, // DDRSS_CTL_150_VAL + 0x00000000U, // DDRSS_CTL_151_VAL + 0x00000000U, // DDRSS_CTL_152_VAL + 0x00000000U, // DDRSS_CTL_153_VAL + 0x00000000U, // DDRSS_CTL_154_VAL + 0x00000000U, // DDRSS_CTL_155_VAL + 0x00000000U, // DDRSS_CTL_156_VAL + 0x00000000U, // DDRSS_CTL_157_VAL + 0x03050000U, // DDRSS_CTL_158_VAL + 0x03080308U, // DDRSS_CTL_159_VAL + 0x00000000U, // DDRSS_CTL_160_VAL + 0x08010000U, // DDRSS_CTL_161_VAL + 0x000E0808U, // DDRSS_CTL_162_VAL + 0x01000000U, // DDRSS_CTL_163_VAL + 0x0E080808U, // DDRSS_CTL_164_VAL + 0x00000000U, // DDRSS_CTL_165_VAL + 0x08080801U, // DDRSS_CTL_166_VAL + 0x0000080EU, // DDRSS_CTL_167_VAL + 0x00040003U, // DDRSS_CTL_168_VAL + 0x00000007U, // DDRSS_CTL_169_VAL + 0x00000000U, // DDRSS_CTL_170_VAL + 0x00000000U, // DDRSS_CTL_171_VAL + 0x00000000U, // DDRSS_CTL_172_VAL + 0x00000000U, // DDRSS_CTL_173_VAL + 0x00000000U, // DDRSS_CTL_174_VAL + 0x00000000U, // DDRSS_CTL_175_VAL + 0x01000000U, // DDRSS_CTL_176_VAL + 0x00000000U, // DDRSS_CTL_177_VAL + 0x00001700U, // DDRSS_CTL_178_VAL + 0x0000100EU, // DDRSS_CTL_179_VAL + 0x00000002U, // DDRSS_CTL_180_VAL + 0x00000000U, // DDRSS_CTL_181_VAL + 0x00000001U, // DDRSS_CTL_182_VAL + 0x00000002U, // DDRSS_CTL_183_VAL + 0x00000C00U, // DDRSS_CTL_184_VAL + 0x00008000U, // DDRSS_CTL_185_VAL + 0x00000C00U, // DDRSS_CTL_186_VAL + 0x00008000U, // DDRSS_CTL_187_VAL + 0x00000C00U, // DDRSS_CTL_188_VAL + 0x00008000U, // DDRSS_CTL_189_VAL + 0x00000000U, // DDRSS_CTL_190_VAL + 0x00000000U, // DDRSS_CTL_191_VAL + 0x00000000U, // DDRSS_CTL_192_VAL + 0x00000000U, // DDRSS_CTL_193_VAL + 0x00000000U, // DDRSS_CTL_194_VAL + 0x0005000AU, // DDRSS_CTL_195_VAL + 0x0404000DU, // DDRSS_CTL_196_VAL + 0x0000000DU, // DDRSS_CTL_197_VAL + 0x00A00140U, // DDRSS_CTL_198_VAL + 0x0C0C0190U, // DDRSS_CTL_199_VAL + 0x00000190U, // DDRSS_CTL_200_VAL + 0x00A00140U, // DDRSS_CTL_201_VAL + 0x0C0C0190U, // DDRSS_CTL_202_VAL + 0x00000190U, // DDRSS_CTL_203_VAL + 0x00000000U, // DDRSS_CTL_204_VAL + 0x00000000U, // DDRSS_CTL_205_VAL + 0x00000000U, // DDRSS_CTL_206_VAL + 0x00000000U, // DDRSS_CTL_207_VAL + 0x00000004U, // DDRSS_CTL_208_VAL + 0x00000000U, // DDRSS_CTL_209_VAL + 0x00000000U, // DDRSS_CTL_210_VAL + 0x00000054U, // DDRSS_CTL_211_VAL + 0x0000002DU, // DDRSS_CTL_212_VAL + 0x00000000U, // DDRSS_CTL_213_VAL + 0x00000054U, // DDRSS_CTL_214_VAL + 0x0000002DU, // DDRSS_CTL_215_VAL + 0x00000000U, // DDRSS_CTL_216_VAL + 0x00000004U, // DDRSS_CTL_217_VAL + 0x00000000U, // DDRSS_CTL_218_VAL + 0x00000000U, // DDRSS_CTL_219_VAL + 0x00000054U, // DDRSS_CTL_220_VAL + 0x0000002DU, // DDRSS_CTL_221_VAL + 0x00000000U, // DDRSS_CTL_222_VAL + 0x00000054U, // DDRSS_CTL_223_VAL + 0x0000002DU, // DDRSS_CTL_224_VAL + 0x00000000U, // DDRSS_CTL_225_VAL + 0x00000000U, // DDRSS_CTL_226_VAL + 0x00000029U, // DDRSS_CTL_227_VAL + 0x000000A9U, // DDRSS_CTL_228_VAL + 0x000000A9U, // DDRSS_CTL_229_VAL + 0x00000029U, // DDRSS_CTL_230_VAL + 0x000000A9U, // DDRSS_CTL_231_VAL + 0x000000A9U, // DDRSS_CTL_232_VAL + 0x00000000U, // DDRSS_CTL_233_VAL + 0x00000000U, // DDRSS_CTL_234_VAL + 0x00000000U, // DDRSS_CTL_235_VAL + 0x00000000U, // DDRSS_CTL_236_VAL + 0x00000000U, // DDRSS_CTL_237_VAL + 0x00000000U, // DDRSS_CTL_238_VAL + 0x00000000U, // DDRSS_CTL_239_VAL + 0x00000000U, // DDRSS_CTL_240_VAL + 0x00000000U, // DDRSS_CTL_241_VAL + 0x00000000U, // DDRSS_CTL_242_VAL + 0x00000000U, // DDRSS_CTL_243_VAL + 0x00000000U, // DDRSS_CTL_244_VAL + 0x00000000U, // DDRSS_CTL_245_VAL + 0x00000000U, // DDRSS_CTL_246_VAL + 0x00000000U, // DDRSS_CTL_247_VAL + 0x00000000U, // DDRSS_CTL_248_VAL + 0x00000000U, // DDRSS_CTL_249_VAL + 0x00000000U, // DDRSS_CTL_250_VAL + 0x00000000U, // DDRSS_CTL_251_VAL + 0x00000000U, // DDRSS_CTL_252_VAL + 0x00000000U, // DDRSS_CTL_253_VAL + 0x00000000U, // DDRSS_CTL_254_VAL + 0x00000000U, // DDRSS_CTL_255_VAL + 0x00000000U, // DDRSS_CTL_256_VAL + 0x35003535U, // DDRSS_CTL_257_VAL + 0x00002735U, // DDRSS_CTL_258_VAL + 0x00000027U, // DDRSS_CTL_259_VAL + 0x00000027U, // DDRSS_CTL_260_VAL + 0x00000027U, // DDRSS_CTL_261_VAL + 0x00000027U, // DDRSS_CTL_262_VAL + 0x00000027U, // DDRSS_CTL_263_VAL + 0x00000000U, // DDRSS_CTL_264_VAL + 0x00000000U, // DDRSS_CTL_265_VAL + 0x0000002BU, // DDRSS_CTL_266_VAL + 0x0000002BU, // DDRSS_CTL_267_VAL + 0x0000002BU, // DDRSS_CTL_268_VAL + 0x0000002BU, // DDRSS_CTL_269_VAL + 0x0000002BU, // DDRSS_CTL_270_VAL + 0x0000002BU, // DDRSS_CTL_271_VAL + 0x00000000U, // DDRSS_CTL_272_VAL + 0x00000000U, // DDRSS_CTL_273_VAL + 0x00000015U, // DDRSS_CTL_274_VAL + 0x00000015U, // DDRSS_CTL_275_VAL + 0x00000000U, // DDRSS_CTL_276_VAL + 0x00000015U, // DDRSS_CTL_277_VAL + 0x00000015U, // DDRSS_CTL_278_VAL + 0x00000020U, // DDRSS_CTL_279_VAL + 0x00010000U, // DDRSS_CTL_280_VAL + 0x00000100U, // DDRSS_CTL_281_VAL + 0x00000000U, // DDRSS_CTL_282_VAL + 0x00000000U, // DDRSS_CTL_283_VAL + 0x00000101U, // DDRSS_CTL_284_VAL + 0x00000000U, // DDRSS_CTL_285_VAL + 0x00000000U, // DDRSS_CTL_286_VAL + 0x00000000U, // DDRSS_CTL_287_VAL + 0x00000000U, // DDRSS_CTL_288_VAL + 0x00000000U, // DDRSS_CTL_289_VAL + 0x00000000U, // DDRSS_CTL_290_VAL + 0x00000000U, // DDRSS_CTL_291_VAL + 0x00000000U, // DDRSS_CTL_292_VAL + 0x00000000U, // DDRSS_CTL_293_VAL + 0x00000000U, // DDRSS_CTL_294_VAL + 0x00000000U, // DDRSS_CTL_295_VAL + 0x0C181511U, // DDRSS_CTL_296_VAL + 0x00000304U, // DDRSS_CTL_297_VAL + 0x00000000U, // DDRSS_CTL_298_VAL + 0x00000000U, // DDRSS_CTL_299_VAL + 0x00000000U, // DDRSS_CTL_300_VAL + 0x00000000U, // DDRSS_CTL_301_VAL + 0x00000000U, // DDRSS_CTL_302_VAL + 0x00000000U, // DDRSS_CTL_303_VAL + 0x00000000U, // DDRSS_CTL_304_VAL + 0x00000000U, // DDRSS_CTL_305_VAL + 0x00000000U, // DDRSS_CTL_306_VAL + 0x00000000U, // DDRSS_CTL_307_VAL + 0x00000000U, // DDRSS_CTL_308_VAL + 0x00000000U, // DDRSS_CTL_309_VAL + 0x00000000U, // DDRSS_CTL_310_VAL + 0x00020000U, // DDRSS_CTL_311_VAL + 0x00400100U, // DDRSS_CTL_312_VAL + 0x00080032U, // DDRSS_CTL_313_VAL + 0x01000200U, // DDRSS_CTL_314_VAL + 0x06400040U, // DDRSS_CTL_315_VAL + 0x00020030U, // DDRSS_CTL_316_VAL + 0x00400100U, // DDRSS_CTL_317_VAL + 0x00300640U, // DDRSS_CTL_318_VAL + 0x00030000U, // DDRSS_CTL_319_VAL + 0x00500050U, // DDRSS_CTL_320_VAL + 0x00000100U, // DDRSS_CTL_321_VAL + 0x01010000U, // DDRSS_CTL_322_VAL + 0x00000000U, // DDRSS_CTL_323_VAL + 0x3FFF0000U, // DDRSS_CTL_324_VAL + 0x000FFF00U, // DDRSS_CTL_325_VAL + 0xFFFFFFFFU, // DDRSS_CTL_326_VAL + 0x00FFFF00U, // DDRSS_CTL_327_VAL + 0x0B000000U, // DDRSS_CTL_328_VAL + 0x0001FFFFU, // DDRSS_CTL_329_VAL + 0x01010101U, // DDRSS_CTL_330_VAL + 0x01010101U, // DDRSS_CTL_331_VAL + 0x00000118U, // DDRSS_CTL_332_VAL + 0x00000C01U, // DDRSS_CTL_333_VAL + 0x00040100U, // DDRSS_CTL_334_VAL + 0x00040100U, // DDRSS_CTL_335_VAL + 0x00000000U, // DDRSS_CTL_336_VAL + 0x00000000U, // DDRSS_CTL_337_VAL + 0x01030303U, // DDRSS_CTL_338_VAL + 0x00000001U, // DDRSS_CTL_339_VAL + 0x00000000U, // DDRSS_CTL_340_VAL + 0x00000000U, // DDRSS_CTL_341_VAL + 0x00000000U, // DDRSS_CTL_342_VAL + 0x00000000U, // DDRSS_CTL_343_VAL + 0x00000000U, // DDRSS_CTL_344_VAL + 0x00000000U, // DDRSS_CTL_345_VAL + 0x00000000U, // DDRSS_CTL_346_VAL + 0x00000000U, // DDRSS_CTL_347_VAL + 0x00000000U, // DDRSS_CTL_348_VAL + 0x00000000U, // DDRSS_CTL_349_VAL + 0x00000000U, // DDRSS_CTL_350_VAL + 0x00000000U, // DDRSS_CTL_351_VAL + 0x00000000U, // DDRSS_CTL_352_VAL + 0x00000000U, // DDRSS_CTL_353_VAL + 0x00000000U, // DDRSS_CTL_354_VAL + 0x00000000U, // DDRSS_CTL_355_VAL + 0x00000000U, // DDRSS_CTL_356_VAL + 0x00000000U, // DDRSS_CTL_357_VAL + 0x00000000U, // DDRSS_CTL_358_VAL + 0x00000000U, // DDRSS_CTL_359_VAL + 0x00000000U, // DDRSS_CTL_360_VAL + 0x00000000U, // DDRSS_CTL_361_VAL + 0x00000000U, // DDRSS_CTL_362_VAL + 0x00000000U, // DDRSS_CTL_363_VAL + 0x00000000U, // DDRSS_CTL_364_VAL + 0x00000000U, // DDRSS_CTL_365_VAL + 0x00000000U, // DDRSS_CTL_366_VAL + 0x00000000U, // DDRSS_CTL_367_VAL + 0x00000000U, // DDRSS_CTL_368_VAL + 0x00000000U, // DDRSS_CTL_369_VAL + 0x00000000U, // DDRSS_CTL_370_VAL + 0x00000000U, // DDRSS_CTL_371_VAL + 0x00000000U, // DDRSS_CTL_372_VAL + 0x00000000U, // DDRSS_CTL_373_VAL + 0x00000000U, // DDRSS_CTL_374_VAL + 0x00000000U, // DDRSS_CTL_375_VAL + 0x00000000U, // DDRSS_CTL_376_VAL + 0x00000000U, // DDRSS_CTL_377_VAL + 0x00000000U, // DDRSS_CTL_378_VAL + 0x00000000U, // DDRSS_CTL_379_VAL + 0x00000000U, // DDRSS_CTL_380_VAL + 0x00000000U, // DDRSS_CTL_381_VAL + 0x00000000U, // DDRSS_CTL_382_VAL + 0x01000101U, // DDRSS_CTL_383_VAL + 0x01010001U, // DDRSS_CTL_384_VAL + 0x00010101U, // DDRSS_CTL_385_VAL + 0x01080803U, // DDRSS_CTL_386_VAL + 0x05020201U, // DDRSS_CTL_387_VAL + 0x0C081818U, // DDRSS_CTL_388_VAL + 0x0008040CU, // DDRSS_CTL_389_VAL + 0x0B100406U, // DDRSS_CTL_390_VAL + 0x0B100406U, // DDRSS_CTL_391_VAL + 0x10100806U, // DDRSS_CTL_392_VAL + 0x01000000U, // DDRSS_CTL_393_VAL + 0x06030601U, // DDRSS_CTL_394_VAL + 0x04000103U, // DDRSS_CTL_395_VAL + 0x1B000004U, // DDRSS_CTL_396_VAL + 0x00000176U, // DDRSS_CTL_397_VAL + 0x00000200U, // DDRSS_CTL_398_VAL + 0x00000200U, // DDRSS_CTL_399_VAL + 0x00000200U, // DDRSS_CTL_400_VAL + 0x00000200U, // DDRSS_CTL_401_VAL + 0x00000693U, // DDRSS_CTL_402_VAL + 0x00000E9CU, // DDRSS_CTL_403_VAL + 0x03000202U, // DDRSS_CTL_404_VAL + 0x32200404U, // DDRSS_CTL_405_VAL + 0x000030B0U, // DDRSS_CTL_406_VAL + 0x00000200U, // DDRSS_CTL_407_VAL + 0x00000200U, // DDRSS_CTL_408_VAL + 0x00000200U, // DDRSS_CTL_409_VAL + 0x00000200U, // DDRSS_CTL_410_VAL + 0x0000DB18U, // DDRSS_CTL_411_VAL + 0x0001E6E0U, // DDRSS_CTL_412_VAL + 0x0F160402U, // DDRSS_CTL_413_VAL + 0x32200A07U, // DDRSS_CTL_414_VAL + 0x000030B0U, // DDRSS_CTL_415_VAL + 0x00000200U, // DDRSS_CTL_416_VAL + 0x00000200U, // DDRSS_CTL_417_VAL + 0x00000200U, // DDRSS_CTL_418_VAL + 0x00000200U, // DDRSS_CTL_419_VAL + 0x0000DB18U, // DDRSS_CTL_420_VAL + 0x0001E6E0U, // DDRSS_CTL_421_VAL + 0x0F160402U, // DDRSS_CTL_422_VAL + 0x00200A07U, // DDRSS_CTL_423_VAL + 0x00000000U, // DDRSS_CTL_424_VAL + 0x02000A00U, // DDRSS_CTL_425_VAL + 0x00050003U, // DDRSS_CTL_426_VAL + 0x00010101U, // DDRSS_CTL_427_VAL + 0x00010101U, // DDRSS_CTL_428_VAL + 0x00010001U, // DDRSS_CTL_429_VAL + 0x00000101U, // DDRSS_CTL_430_VAL + 0x02000201U, // DDRSS_CTL_431_VAL + 0x02010000U, // DDRSS_CTL_432_VAL + 0x06000200U, // DDRSS_CTL_433_VAL + 0x00001E1EU, // DDRSS_CTL_434_VAL +}; + +uint32_t DDRSS_phyIndepReg[] = { + 0x00000B00U, // DDRSS_PI_0_VAL + 0x00000000U, // DDRSS_PI_1_VAL + 0x00000000U, // DDRSS_PI_2_VAL + 0x01000000U, // DDRSS_PI_3_VAL + 0x00000001U, // DDRSS_PI_4_VAL + 0x00010064U, // DDRSS_PI_5_VAL + 0x00000000U, // DDRSS_PI_6_VAL + 0x00000000U, // DDRSS_PI_7_VAL + 0x00000000U, // DDRSS_PI_8_VAL + 0x00000000U, // DDRSS_PI_9_VAL + 0x00000000U, // DDRSS_PI_10_VAL + 0x00000002U, // DDRSS_PI_11_VAL + 0x00000005U, // DDRSS_PI_12_VAL + 0x00050001U, // DDRSS_PI_13_VAL + 0x08000000U, // DDRSS_PI_14_VAL + 0x00010300U, // DDRSS_PI_15_VAL + 0x00000005U, // DDRSS_PI_16_VAL + 0x00000000U, // DDRSS_PI_17_VAL + 0x00000000U, // DDRSS_PI_18_VAL + 0x00000000U, // DDRSS_PI_19_VAL + 0x00000000U, // DDRSS_PI_20_VAL + 0x00000000U, // DDRSS_PI_21_VAL + 0x00000000U, // DDRSS_PI_22_VAL + 0x00000000U, // DDRSS_PI_23_VAL + 0x00000000U, // DDRSS_PI_24_VAL + 0x00000000U, // DDRSS_PI_25_VAL + 0x01010000U, // DDRSS_PI_26_VAL + 0x0A000100U, // DDRSS_PI_27_VAL + 0x00000028U, // DDRSS_PI_28_VAL + 0x05000000U, // DDRSS_PI_29_VAL + 0x00320000U, // DDRSS_PI_30_VAL + 0x00000000U, // DDRSS_PI_31_VAL + 0x00000000U, // DDRSS_PI_32_VAL + 0x01010102U, // DDRSS_PI_33_VAL + 0x00000000U, // DDRSS_PI_34_VAL + 0x00000000U, // DDRSS_PI_35_VAL + 0x00000000U, // DDRSS_PI_36_VAL + 0x00000001U, // DDRSS_PI_37_VAL + 0x000000AAU, // DDRSS_PI_38_VAL + 0x00000055U, // DDRSS_PI_39_VAL + 0x000000B5U, // DDRSS_PI_40_VAL + 0x0000004AU, // DDRSS_PI_41_VAL + 0x00000056U, // DDRSS_PI_42_VAL + 0x000000A9U, // DDRSS_PI_43_VAL + 0x000000A9U, // DDRSS_PI_44_VAL + 0x000000B5U, // DDRSS_PI_45_VAL + 0x00000000U, // DDRSS_PI_46_VAL + 0x00000000U, // DDRSS_PI_47_VAL + 0x00050500U, // DDRSS_PI_48_VAL + 0x00000019U, // DDRSS_PI_49_VAL + 0x000007D0U, // DDRSS_PI_50_VAL + 0x00000300U, // DDRSS_PI_51_VAL + 0x00000000U, // DDRSS_PI_52_VAL + 0x00000000U, // DDRSS_PI_53_VAL + 0x01000000U, // DDRSS_PI_54_VAL + 0x00010101U, // DDRSS_PI_55_VAL + 0x01000000U, // DDRSS_PI_56_VAL + 0x03000000U, // DDRSS_PI_57_VAL + 0x00000000U, // DDRSS_PI_58_VAL + 0x00001705U, // DDRSS_PI_59_VAL + 0x00000000U, // DDRSS_PI_60_VAL + 0x00000000U, // DDRSS_PI_61_VAL + 0x00000000U, // DDRSS_PI_62_VAL + 0x0A0A140AU, // DDRSS_PI_63_VAL + 0x10020101U, // DDRSS_PI_64_VAL + 0x01000210U, // DDRSS_PI_65_VAL + 0x05000404U, // DDRSS_PI_66_VAL + 0x00010001U, // DDRSS_PI_67_VAL + 0x0001000EU, // DDRSS_PI_68_VAL + 0x01010500U, // DDRSS_PI_69_VAL + 0x00010000U, // DDRSS_PI_70_VAL + 0x00000034U, // DDRSS_PI_71_VAL + 0x00000000U, // DDRSS_PI_72_VAL + 0x00000000U, // DDRSS_PI_73_VAL + 0x0000FFFFU, // DDRSS_PI_74_VAL + 0x00000000U, // DDRSS_PI_75_VAL + 0x00000000U, // DDRSS_PI_76_VAL + 0x00000000U, // DDRSS_PI_77_VAL + 0x00000000U, // DDRSS_PI_78_VAL + 0x01000000U, // DDRSS_PI_79_VAL + 0x00010001U, // DDRSS_PI_80_VAL + 0x02000008U, // DDRSS_PI_81_VAL + 0x01000200U, // DDRSS_PI_82_VAL + 0x00000100U, // DDRSS_PI_83_VAL + 0x02000100U, // DDRSS_PI_84_VAL + 0x02000200U, // DDRSS_PI_85_VAL + 0x00000000U, // DDRSS_PI_86_VAL + 0x00000000U, // DDRSS_PI_87_VAL + 0x00000000U, // DDRSS_PI_88_VAL + 0x00000000U, // DDRSS_PI_89_VAL + 0x00000000U, // DDRSS_PI_90_VAL + 0x00000000U, // DDRSS_PI_91_VAL + 0x00000000U, // DDRSS_PI_92_VAL + 0x00000000U, // DDRSS_PI_93_VAL + 0x00000000U, // DDRSS_PI_94_VAL + 0x00000000U, // DDRSS_PI_95_VAL + 0x00000000U, // DDRSS_PI_96_VAL + 0x00000000U, // DDRSS_PI_97_VAL + 0x00000000U, // DDRSS_PI_98_VAL + 0x01000400U, // DDRSS_PI_99_VAL + 0x0E0D0F10U, // DDRSS_PI_100_VAL + 0x080A1413U, // DDRSS_PI_101_VAL + 0x01000009U, // DDRSS_PI_102_VAL + 0x00000302U, // DDRSS_PI_103_VAL + 0x00000008U, // DDRSS_PI_104_VAL + 0x08000000U, // DDRSS_PI_105_VAL + 0x00000100U, // DDRSS_PI_106_VAL + 0x00000000U, // DDRSS_PI_107_VAL + 0x0000AA00U, // DDRSS_PI_108_VAL + 0x00000000U, // DDRSS_PI_109_VAL + 0x00000000U, // DDRSS_PI_110_VAL + 0x00010000U, // DDRSS_PI_111_VAL + 0x00000000U, // DDRSS_PI_112_VAL + 0x00000000U, // DDRSS_PI_113_VAL + 0x00000000U, // DDRSS_PI_114_VAL + 0x00000000U, // DDRSS_PI_115_VAL + 0x00000000U, // DDRSS_PI_116_VAL + 0x00000000U, // DDRSS_PI_117_VAL + 0x00000000U, // DDRSS_PI_118_VAL + 0x00000000U, // DDRSS_PI_119_VAL + 0x00000000U, // DDRSS_PI_120_VAL + 0x00000000U, // DDRSS_PI_121_VAL + 0x00000000U, // DDRSS_PI_122_VAL + 0x00000000U, // DDRSS_PI_123_VAL + 0x00000000U, // DDRSS_PI_124_VAL + 0x00000000U, // DDRSS_PI_125_VAL + 0x00000000U, // DDRSS_PI_126_VAL + 0x00000000U, // DDRSS_PI_127_VAL + 0x00000000U, // DDRSS_PI_128_VAL + 0x00000000U, // DDRSS_PI_129_VAL + 0x00000000U, // DDRSS_PI_130_VAL + 0x00000000U, // DDRSS_PI_131_VAL + 0x00000000U, // DDRSS_PI_132_VAL + 0x00000000U, // DDRSS_PI_133_VAL + 0x00000000U, // DDRSS_PI_134_VAL + 0x00000000U, // DDRSS_PI_135_VAL + 0x00000008U, // DDRSS_PI_136_VAL + 0x00000000U, // DDRSS_PI_137_VAL + 0x00000000U, // DDRSS_PI_138_VAL + 0x00000000U, // DDRSS_PI_139_VAL + 0x00000000U, // DDRSS_PI_140_VAL + 0x00000000U, // DDRSS_PI_141_VAL + 0x00000000U, // DDRSS_PI_142_VAL + 0x00000000U, // DDRSS_PI_143_VAL + 0x00000000U, // DDRSS_PI_144_VAL + 0x00010000U, // DDRSS_PI_145_VAL + 0x00000000U, // DDRSS_PI_146_VAL + 0x00000000U, // DDRSS_PI_147_VAL + 0x0000000AU, // DDRSS_PI_148_VAL + 0x000186A0U, // DDRSS_PI_149_VAL + 0x00000100U, // DDRSS_PI_150_VAL + 0x00000000U, // DDRSS_PI_151_VAL + 0x00000000U, // DDRSS_PI_152_VAL + 0x00000000U, // DDRSS_PI_153_VAL + 0x00000000U, // DDRSS_PI_154_VAL + 0x00000000U, // DDRSS_PI_155_VAL + 0x01000000U, // DDRSS_PI_156_VAL + 0x00010003U, // DDRSS_PI_157_VAL + 0x02000101U, // DDRSS_PI_158_VAL + 0x01030001U, // DDRSS_PI_159_VAL + 0x00010400U, // DDRSS_PI_160_VAL + 0x06000105U, // DDRSS_PI_161_VAL + 0x01070001U, // DDRSS_PI_162_VAL + 0x00000000U, // DDRSS_PI_163_VAL + 0x00000000U, // DDRSS_PI_164_VAL + 0x00000000U, // DDRSS_PI_165_VAL + 0x00010001U, // DDRSS_PI_166_VAL + 0x00000000U, // DDRSS_PI_167_VAL + 0x00000000U, // DDRSS_PI_168_VAL + 0x00000000U, // DDRSS_PI_169_VAL + 0x00000000U, // DDRSS_PI_170_VAL + 0x00010000U, // DDRSS_PI_171_VAL + 0x00000004U, // DDRSS_PI_172_VAL + 0x00000000U, // DDRSS_PI_173_VAL + 0x00010000U, // DDRSS_PI_174_VAL + 0x00000000U, // DDRSS_PI_175_VAL + 0x00080000U, // DDRSS_PI_176_VAL + 0x00F000F0U, // DDRSS_PI_177_VAL + 0x00202001U, // DDRSS_PI_178_VAL + 0x00000034U, // DDRSS_PI_179_VAL + 0x00000057U, // DDRSS_PI_180_VAL + 0x00020057U, // DDRSS_PI_181_VAL + 0x02000200U, // DDRSS_PI_182_VAL + 0x00000004U, // DDRSS_PI_183_VAL + 0x00000E0CU, // DDRSS_PI_184_VAL + 0x000E3800U, // DDRSS_PI_185_VAL + 0x00380000U, // DDRSS_PI_186_VAL + 0x00000013U, // DDRSS_PI_187_VAL + 0x000000BBU, // DDRSS_PI_188_VAL + 0x00000260U, // DDRSS_PI_189_VAL + 0x00001858U, // DDRSS_PI_190_VAL + 0x00000260U, // DDRSS_PI_191_VAL + 0x04001858U, // DDRSS_PI_192_VAL + 0x01010404U, // DDRSS_PI_193_VAL + 0x00001501U, // DDRSS_PI_194_VAL + 0x00250025U, // DDRSS_PI_195_VAL + 0x01000100U, // DDRSS_PI_196_VAL + 0x00000100U, // DDRSS_PI_197_VAL + 0x00000000U, // DDRSS_PI_198_VAL + 0x05080803U, // DDRSS_PI_199_VAL + 0x01011818U, // DDRSS_PI_200_VAL + 0x01010101U, // DDRSS_PI_201_VAL + 0x000C0C0AU, // DDRSS_PI_202_VAL + 0x00000000U, // DDRSS_PI_203_VAL + 0x00000000U, // DDRSS_PI_204_VAL + 0x04000000U, // DDRSS_PI_205_VAL + 0x0A021010U, // DDRSS_PI_206_VAL + 0x0404020AU, // DDRSS_PI_207_VAL + 0x00090031U, // DDRSS_PI_208_VAL + 0x00190041U, // DDRSS_PI_209_VAL + 0x00190041U, // DDRSS_PI_210_VAL + 0x01010101U, // DDRSS_PI_211_VAL + 0x0003000DU, // DDRSS_PI_212_VAL + 0x00030190U, // DDRSS_PI_213_VAL + 0x01000190U, // DDRSS_PI_214_VAL + 0x000E000EU, // DDRSS_PI_215_VAL + 0x01910100U, // DDRSS_PI_216_VAL + 0x01000191U, // DDRSS_PI_217_VAL + 0x01910191U, // DDRSS_PI_218_VAL + 0x32103200U, // DDRSS_PI_219_VAL + 0x01013210U, // DDRSS_PI_220_VAL + 0x0A070601U, // DDRSS_PI_221_VAL + 0x180F090DU, // DDRSS_PI_222_VAL + 0x180F0911U, // DDRSS_PI_223_VAL + 0x000C0011U, // DDRSS_PI_224_VAL + 0x00001000U, // DDRSS_PI_225_VAL + 0x00000C00U, // DDRSS_PI_226_VAL + 0x00001000U, // DDRSS_PI_227_VAL + 0x00000C00U, // DDRSS_PI_228_VAL + 0x02001000U, // DDRSS_PI_229_VAL + 0x001E000DU, // DDRSS_PI_230_VAL + 0x001E0190U, // DDRSS_PI_231_VAL + 0x00000190U, // DDRSS_PI_232_VAL + 0x00001900U, // DDRSS_PI_233_VAL + 0x32000056U, // DDRSS_PI_234_VAL + 0x06000101U, // DDRSS_PI_235_VAL + 0x00230204U, // DDRSS_PI_236_VAL + 0x3212005AU, // DDRSS_PI_237_VAL + 0x13000101U, // DDRSS_PI_238_VAL + 0x00230A10U, // DDRSS_PI_239_VAL + 0x3212005AU, // DDRSS_PI_240_VAL + 0x13000101U, // DDRSS_PI_241_VAL + 0x00000A10U, // DDRSS_PI_242_VAL + 0x05030900U, // DDRSS_PI_243_VAL + 0x00040900U, // DDRSS_PI_244_VAL + 0x0000062BU, // DDRSS_PI_245_VAL + 0x20010004U, // DDRSS_PI_246_VAL + 0x0A0A0A03U, // DDRSS_PI_247_VAL + 0x220D0000U, // DDRSS_PI_248_VAL + 0x1F09001EU, // DDRSS_PI_249_VAL + 0x0000C570U, // DDRSS_PI_250_VAL + 0x20060045U, // DDRSS_PI_251_VAL + 0x17101718U, // DDRSS_PI_252_VAL + 0x220D0000U, // DDRSS_PI_253_VAL + 0x1F09001EU, // DDRSS_PI_254_VAL + 0x0000C570U, // DDRSS_PI_255_VAL + 0x20060045U, // DDRSS_PI_256_VAL + 0x17101718U, // DDRSS_PI_257_VAL + 0x00000000U, // DDRSS_PI_258_VAL + 0x00000176U, // DDRSS_PI_259_VAL + 0x00000E9CU, // DDRSS_PI_260_VAL + 0x000030B0U, // DDRSS_PI_261_VAL + 0x0001E6E0U, // DDRSS_PI_262_VAL + 0x000030B0U, // DDRSS_PI_263_VAL + 0x0001E6E0U, // DDRSS_PI_264_VAL + 0x026C0014U, // DDRSS_PI_265_VAL + 0x0303026CU, // DDRSS_PI_266_VAL + 0x00000003U, // DDRSS_PI_267_VAL + 0x00000000U, // DDRSS_PI_268_VAL + 0x08030503U, // DDRSS_PI_269_VAL + 0x00000803U, // DDRSS_PI_270_VAL + 0x00002710U, // DDRSS_PI_271_VAL + 0x000186A0U, // DDRSS_PI_272_VAL + 0x00000005U, // DDRSS_PI_273_VAL + 0x00000064U, // DDRSS_PI_274_VAL + 0x00000014U, // DDRSS_PI_275_VAL + 0x0004E200U, // DDRSS_PI_276_VAL + 0x000186A0U, // DDRSS_PI_277_VAL + 0x00000005U, // DDRSS_PI_278_VAL + 0x00000C80U, // DDRSS_PI_279_VAL + 0x0000026CU, // DDRSS_PI_280_VAL + 0x0004E200U, // DDRSS_PI_281_VAL + 0x000186A0U, // DDRSS_PI_282_VAL + 0x00000005U, // DDRSS_PI_283_VAL + 0x00000C80U, // DDRSS_PI_284_VAL + 0x0100026CU, // DDRSS_PI_285_VAL + 0x00320040U, // DDRSS_PI_286_VAL + 0x00010008U, // DDRSS_PI_287_VAL + 0x06400040U, // DDRSS_PI_288_VAL + 0x00010030U, // DDRSS_PI_289_VAL + 0x06400040U, // DDRSS_PI_290_VAL + 0x00000330U, // DDRSS_PI_291_VAL + 0x00280050U, // DDRSS_PI_292_VAL + 0x03040404U, // DDRSS_PI_293_VAL + 0x00000303U, // DDRSS_PI_294_VAL + 0x01010000U, // DDRSS_PI_295_VAL + 0x04040202U, // DDRSS_PI_296_VAL + 0x67670808U, // DDRSS_PI_297_VAL + 0x67676767U, // DDRSS_PI_298_VAL + 0x67676767U, // DDRSS_PI_299_VAL + 0x67676767U, // DDRSS_PI_300_VAL + 0x00006767U, // DDRSS_PI_301_VAL + 0x00000000U, // DDRSS_PI_302_VAL + 0x00000000U, // DDRSS_PI_303_VAL + 0x00000000U, // DDRSS_PI_304_VAL + 0x00000000U, // DDRSS_PI_305_VAL + 0x55000000U, // DDRSS_PI_306_VAL + 0x00000000U, // DDRSS_PI_307_VAL + 0x3C00005AU, // DDRSS_PI_308_VAL + 0x00005500U, // DDRSS_PI_309_VAL + 0x00005A00U, // DDRSS_PI_310_VAL + 0x0055003CU, // DDRSS_PI_311_VAL + 0x00000000U, // DDRSS_PI_312_VAL + 0x3C00005AU, // DDRSS_PI_313_VAL + 0x00005500U, // DDRSS_PI_314_VAL + 0x00005A00U, // DDRSS_PI_315_VAL + 0x1716153CU, // DDRSS_PI_316_VAL + 0x13121118U, // DDRSS_PI_317_VAL + 0x06050414U, // DDRSS_PI_318_VAL + 0x02010007U, // DDRSS_PI_319_VAL + 0x00000003U, // DDRSS_PI_320_VAL + 0x00000000U, // DDRSS_PI_321_VAL + 0x00000000U, // DDRSS_PI_322_VAL + 0x01000000U, // DDRSS_PI_323_VAL + 0x04020201U, // DDRSS_PI_324_VAL + 0x00080804U, // DDRSS_PI_325_VAL + 0x00000000U, // DDRSS_PI_326_VAL + 0x00000000U, // DDRSS_PI_327_VAL + 0x00000000U, // DDRSS_PI_328_VAL + 0x00000004U, // DDRSS_PI_329_VAL + 0x00000000U, // DDRSS_PI_330_VAL + 0x00000029U, // DDRSS_PI_331_VAL + 0x00000000U, // DDRSS_PI_332_VAL + 0x00000000U, // DDRSS_PI_333_VAL + 0x00000000U, // DDRSS_PI_334_VAL + 0x20002B27U, // DDRSS_PI_335_VAL + 0x00000000U, // DDRSS_PI_336_VAL + 0x00000054U, // DDRSS_PI_337_VAL + 0x0000002DU, // DDRSS_PI_338_VAL + 0x000000A9U, // DDRSS_PI_339_VAL + 0x00000000U, // DDRSS_PI_340_VAL + 0x00000000U, // DDRSS_PI_341_VAL + 0x35000000U, // DDRSS_PI_342_VAL + 0x20152B27U, // DDRSS_PI_343_VAL + 0x00000000U, // DDRSS_PI_344_VAL + 0x00000054U, // DDRSS_PI_345_VAL + 0x0000002DU, // DDRSS_PI_346_VAL + 0x000000A9U, // DDRSS_PI_347_VAL + 0x00000000U, // DDRSS_PI_348_VAL + 0x00000000U, // DDRSS_PI_349_VAL + 0x35000000U, // DDRSS_PI_350_VAL + 0x20152B27U, // DDRSS_PI_351_VAL + 0x00000000U, // DDRSS_PI_352_VAL + 0x00000004U, // DDRSS_PI_353_VAL + 0x00000000U, // DDRSS_PI_354_VAL + 0x00000029U, // DDRSS_PI_355_VAL + 0x00000000U, // DDRSS_PI_356_VAL + 0x00000000U, // DDRSS_PI_357_VAL + 0x00000000U, // DDRSS_PI_358_VAL + 0x20002B27U, // DDRSS_PI_359_VAL + 0x00000000U, // DDRSS_PI_360_VAL + 0x00000054U, // DDRSS_PI_361_VAL + 0x0000002DU, // DDRSS_PI_362_VAL + 0x000000A9U, // DDRSS_PI_363_VAL + 0x00000000U, // DDRSS_PI_364_VAL + 0x00000000U, // DDRSS_PI_365_VAL + 0x35000000U, // DDRSS_PI_366_VAL + 0x20152B27U, // DDRSS_PI_367_VAL + 0x00000000U, // DDRSS_PI_368_VAL + 0x00000054U, // DDRSS_PI_369_VAL + 0x0000002DU, // DDRSS_PI_370_VAL + 0x000000A9U, // DDRSS_PI_371_VAL + 0x00000000U, // DDRSS_PI_372_VAL + 0x00000000U, // DDRSS_PI_373_VAL + 0x35000000U, // DDRSS_PI_374_VAL + 0x20152B27U, // DDRSS_PI_375_VAL + 0x00000000U, // DDRSS_PI_376_VAL + 0x00000004U, // DDRSS_PI_377_VAL + 0x00000000U, // DDRSS_PI_378_VAL + 0x00000029U, // DDRSS_PI_379_VAL + 0x00000000U, // DDRSS_PI_380_VAL + 0x00000000U, // DDRSS_PI_381_VAL + 0x00000000U, // DDRSS_PI_382_VAL + 0x20002B27U, // DDRSS_PI_383_VAL + 0x00000000U, // DDRSS_PI_384_VAL + 0x00000054U, // DDRSS_PI_385_VAL + 0x0000002DU, // DDRSS_PI_386_VAL + 0x000000A9U, // DDRSS_PI_387_VAL + 0x00000000U, // DDRSS_PI_388_VAL + 0x00000000U, // DDRSS_PI_389_VAL + 0x35000000U, // DDRSS_PI_390_VAL + 0x20152B27U, // DDRSS_PI_391_VAL + 0x00000000U, // DDRSS_PI_392_VAL + 0x00000054U, // DDRSS_PI_393_VAL + 0x0000002DU, // DDRSS_PI_394_VAL + 0x000000A9U, // DDRSS_PI_395_VAL + 0x00000000U, // DDRSS_PI_396_VAL + 0x00000000U, // DDRSS_PI_397_VAL + 0x35000000U, // DDRSS_PI_398_VAL + 0x20152B27U, // DDRSS_PI_399_VAL + 0x00000000U, // DDRSS_PI_400_VAL + 0x00000004U, // DDRSS_PI_401_VAL + 0x00000000U, // DDRSS_PI_402_VAL + 0x00000029U, // DDRSS_PI_403_VAL + 0x00000000U, // DDRSS_PI_404_VAL + 0x00000000U, // DDRSS_PI_405_VAL + 0x00000000U, // DDRSS_PI_406_VAL + 0x20002B27U, // DDRSS_PI_407_VAL + 0x00000000U, // DDRSS_PI_408_VAL + 0x00000054U, // DDRSS_PI_409_VAL + 0x0000002DU, // DDRSS_PI_410_VAL + 0x000000A9U, // DDRSS_PI_411_VAL + 0x00000000U, // DDRSS_PI_412_VAL + 0x00000000U, // DDRSS_PI_413_VAL + 0x35000000U, // DDRSS_PI_414_VAL + 0x20152B27U, // DDRSS_PI_415_VAL + 0x00000000U, // DDRSS_PI_416_VAL + 0x00000054U, // DDRSS_PI_417_VAL + 0x0000002DU, // DDRSS_PI_418_VAL + 0x000000A9U, // DDRSS_PI_419_VAL + 0x00000000U, // DDRSS_PI_420_VAL + 0x00000000U, // DDRSS_PI_421_VAL + 0x35000000U, // DDRSS_PI_422_VAL + 0x20152B27U, // DDRSS_PI_423_VAL +}; + +uint32_t DDRSS_phyReg[] = { + 0x04F00000U, // DDRSS_PHY_0_VAL + 0x00000000U, // DDRSS_PHY_1_VAL + 0x00030200U, // DDRSS_PHY_2_VAL + 0x00000000U, // DDRSS_PHY_3_VAL + 0x00000000U, // DDRSS_PHY_4_VAL + 0x01030000U, // DDRSS_PHY_5_VAL + 0x00010000U, // DDRSS_PHY_6_VAL + 0x01030004U, // DDRSS_PHY_7_VAL + 0x01000000U, // DDRSS_PHY_8_VAL + 0x00000000U, // DDRSS_PHY_9_VAL + 0x00000000U, // DDRSS_PHY_10_VAL + 0x00000000U, // DDRSS_PHY_11_VAL + 0x01010000U, // DDRSS_PHY_12_VAL + 0x00010000U, // DDRSS_PHY_13_VAL + 0x00C00001U, // DDRSS_PHY_14_VAL + 0x00CC0008U, // DDRSS_PHY_15_VAL + 0x00660601U, // DDRSS_PHY_16_VAL + 0x00000003U, // DDRSS_PHY_17_VAL + 0x00000000U, // DDRSS_PHY_18_VAL + 0x00000001U, // DDRSS_PHY_19_VAL + 0x0000AAAAU, // DDRSS_PHY_20_VAL + 0x00005555U, // DDRSS_PHY_21_VAL + 0x0000B5B5U, // DDRSS_PHY_22_VAL + 0x00004A4AU, // DDRSS_PHY_23_VAL + 0x00005656U, // DDRSS_PHY_24_VAL + 0x0000A9A9U, // DDRSS_PHY_25_VAL + 0x0000B7B7U, // DDRSS_PHY_26_VAL + 0x00004848U, // DDRSS_PHY_27_VAL + 0x00000000U, // DDRSS_PHY_28_VAL + 0x00000000U, // DDRSS_PHY_29_VAL + 0x08000000U, // DDRSS_PHY_30_VAL + 0x0F000008U, // DDRSS_PHY_31_VAL + 0x00000F0FU, // DDRSS_PHY_32_VAL + 0x00E4E400U, // DDRSS_PHY_33_VAL + 0x00071020U, // DDRSS_PHY_34_VAL + 0x000C0020U, // DDRSS_PHY_35_VAL + 0x00062000U, // DDRSS_PHY_36_VAL + 0x00000000U, // DDRSS_PHY_37_VAL + 0x55555555U, // DDRSS_PHY_38_VAL + 0xAAAAAAAAU, // DDRSS_PHY_39_VAL + 0x55555555U, // DDRSS_PHY_40_VAL + 0xAAAAAAAAU, // DDRSS_PHY_41_VAL + 0x00005555U, // DDRSS_PHY_42_VAL + 0x01000100U, // DDRSS_PHY_43_VAL + 0x00800180U, // DDRSS_PHY_44_VAL + 0x00000001U, // DDRSS_PHY_45_VAL + 0x00000000U, // DDRSS_PHY_46_VAL + 0x00000000U, // DDRSS_PHY_47_VAL + 0x00000000U, // DDRSS_PHY_48_VAL + 0x00000000U, // DDRSS_PHY_49_VAL + 0x00000000U, // DDRSS_PHY_50_VAL + 0x00000000U, // DDRSS_PHY_51_VAL + 0x00000000U, // DDRSS_PHY_52_VAL + 0x00000000U, // DDRSS_PHY_53_VAL + 0x00000000U, // DDRSS_PHY_54_VAL + 0x00000000U, // DDRSS_PHY_55_VAL + 0x00000000U, // DDRSS_PHY_56_VAL + 0x00000000U, // DDRSS_PHY_57_VAL + 0x00000000U, // DDRSS_PHY_58_VAL + 0x00000000U, // DDRSS_PHY_59_VAL + 0x00000000U, // DDRSS_PHY_60_VAL + 0x00000000U, // DDRSS_PHY_61_VAL + 0x00000000U, // DDRSS_PHY_62_VAL + 0x00000000U, // DDRSS_PHY_63_VAL + 0x00000000U, // DDRSS_PHY_64_VAL + 0x00000000U, // DDRSS_PHY_65_VAL + 0x00000000U, // DDRSS_PHY_66_VAL + 0x00000004U, // DDRSS_PHY_67_VAL + 0x00000000U, // DDRSS_PHY_68_VAL + 0x00000000U, // DDRSS_PHY_69_VAL + 0x00000000U, // DDRSS_PHY_70_VAL + 0x00000000U, // DDRSS_PHY_71_VAL + 0x00000000U, // DDRSS_PHY_72_VAL + 0x00000000U, // DDRSS_PHY_73_VAL + 0x081F07FFU, // DDRSS_PHY_74_VAL + 0x10200080U, // DDRSS_PHY_75_VAL + 0x00000008U, // DDRSS_PHY_76_VAL + 0x00000401U, // DDRSS_PHY_77_VAL + 0x00000000U, // DDRSS_PHY_78_VAL + 0x01CC0B01U, // DDRSS_PHY_79_VAL + 0x1003CC0BU, // DDRSS_PHY_80_VAL + 0x20000140U, // DDRSS_PHY_81_VAL + 0x07FF0200U, // DDRSS_PHY_82_VAL + 0x0000DD01U, // DDRSS_PHY_83_VAL + 0x00100303U, // DDRSS_PHY_84_VAL + 0x00000000U, // DDRSS_PHY_85_VAL + 0x00000000U, // DDRSS_PHY_86_VAL + 0x00031000U, // DDRSS_PHY_87_VAL + 0x00100010U, // DDRSS_PHY_88_VAL + 0x00100010U, // DDRSS_PHY_89_VAL + 0x00100010U, // DDRSS_PHY_90_VAL + 0x00100010U, // DDRSS_PHY_91_VAL + 0x02000010U, // DDRSS_PHY_92_VAL + 0x00000004U, // DDRSS_PHY_93_VAL + 0x51516042U, // DDRSS_PHY_94_VAL + 0x31C06000U, // DDRSS_PHY_95_VAL + 0x07AB0340U, // DDRSS_PHY_96_VAL + 0x00C0C001U, // DDRSS_PHY_97_VAL + 0x0B000000U, // DDRSS_PHY_98_VAL + 0x000B0A0AU, // DDRSS_PHY_99_VAL + 0x42100010U, // DDRSS_PHY_100_VAL + 0x010C073EU, // DDRSS_PHY_101_VAL + 0x000F0C2DU, // DDRSS_PHY_102_VAL + 0x01000140U, // DDRSS_PHY_103_VAL + 0x00F50120U, // DDRSS_PHY_104_VAL + 0x00000C00U, // DDRSS_PHY_105_VAL + 0x00000299U, // DDRSS_PHY_106_VAL + 0x00030200U, // DDRSS_PHY_107_VAL + 0x02800000U, // DDRSS_PHY_108_VAL + 0x80800000U, // DDRSS_PHY_109_VAL + 0x000B2010U, // DDRSS_PHY_110_VAL + 0x32570186U, // DDRSS_PHY_111_VAL + 0x00000004U, // DDRSS_PHY_112_VAL + 0x04190419U, // DDRSS_PHY_113_VAL + 0x04190419U, // DDRSS_PHY_114_VAL + 0x04190419U, // DDRSS_PHY_115_VAL + 0x04190419U, // DDRSS_PHY_116_VAL + 0x00000419U, // DDRSS_PHY_117_VAL + 0x0000A000U, // DDRSS_PHY_118_VAL + 0x00A000A0U, // DDRSS_PHY_119_VAL + 0x00A000A0U, // DDRSS_PHY_120_VAL + 0x00A000A0U, // DDRSS_PHY_121_VAL + 0x00A000A0U, // DDRSS_PHY_122_VAL + 0x00A000A0U, // DDRSS_PHY_123_VAL + 0x00A000A0U, // DDRSS_PHY_124_VAL + 0x00A000A0U, // DDRSS_PHY_125_VAL + 0x00A000A0U, // DDRSS_PHY_126_VAL + 0x01E600A0U, // DDRSS_PHY_127_VAL + 0x01000000U, // DDRSS_PHY_128_VAL + 0x00000000U, // DDRSS_PHY_129_VAL + 0x00000000U, // DDRSS_PHY_130_VAL + 0x00080200U, // DDRSS_PHY_131_VAL + 0x00000000U, // DDRSS_PHY_132_VAL + 0x20202020U, // DDRSS_PHY_133_VAL + 0x20202020U, // DDRSS_PHY_134_VAL + 0xF0F02020U, // DDRSS_PHY_135_VAL + 0x00000000U, // DDRSS_PHY_136_VAL + 0x04F00000U, // DDRSS_PHY_256_VAL + 0x00000000U, // DDRSS_PHY_257_VAL + 0x00030200U, // DDRSS_PHY_258_VAL + 0x00000000U, // DDRSS_PHY_259_VAL + 0x00000000U, // DDRSS_PHY_260_VAL + 0x01030000U, // DDRSS_PHY_261_VAL + 0x00010000U, // DDRSS_PHY_262_VAL + 0x01030004U, // DDRSS_PHY_263_VAL + 0x01000000U, // DDRSS_PHY_264_VAL + 0x00000000U, // DDRSS_PHY_265_VAL + 0x00000000U, // DDRSS_PHY_266_VAL + 0x00000000U, // DDRSS_PHY_267_VAL + 0x01010000U, // DDRSS_PHY_268_VAL + 0x00010000U, // DDRSS_PHY_269_VAL + 0x00C00001U, // DDRSS_PHY_270_VAL + 0x00CC0008U, // DDRSS_PHY_271_VAL + 0x00660601U, // DDRSS_PHY_272_VAL + 0x00000003U, // DDRSS_PHY_273_VAL + 0x00000000U, // DDRSS_PHY_274_VAL + 0x00000001U, // DDRSS_PHY_275_VAL + 0x0000AAAAU, // DDRSS_PHY_276_VAL + 0x00005555U, // DDRSS_PHY_277_VAL + 0x0000B5B5U, // DDRSS_PHY_278_VAL + 0x00004A4AU, // DDRSS_PHY_279_VAL + 0x00005656U, // DDRSS_PHY_280_VAL + 0x0000A9A9U, // DDRSS_PHY_281_VAL + 0x0000B7B7U, // DDRSS_PHY_282_VAL + 0x00004848U, // DDRSS_PHY_283_VAL + 0x00000000U, // DDRSS_PHY_284_VAL + 0x00000000U, // DDRSS_PHY_285_VAL + 0x08000000U, // DDRSS_PHY_286_VAL + 0x0F000008U, // DDRSS_PHY_287_VAL + 0x00000F0FU, // DDRSS_PHY_288_VAL + 0x00E4E400U, // DDRSS_PHY_289_VAL + 0x00071020U, // DDRSS_PHY_290_VAL + 0x000C0020U, // DDRSS_PHY_291_VAL + 0x00062000U, // DDRSS_PHY_292_VAL + 0x00000000U, // DDRSS_PHY_293_VAL + 0x55555555U, // DDRSS_PHY_294_VAL + 0xAAAAAAAAU, // DDRSS_PHY_295_VAL + 0x55555555U, // DDRSS_PHY_296_VAL + 0xAAAAAAAAU, // DDRSS_PHY_297_VAL + 0x00005555U, // DDRSS_PHY_298_VAL + 0x01000100U, // DDRSS_PHY_299_VAL + 0x00800180U, // DDRSS_PHY_300_VAL + 0x00000000U, // DDRSS_PHY_301_VAL + 0x00000000U, // DDRSS_PHY_302_VAL + 0x00000000U, // DDRSS_PHY_303_VAL + 0x00000000U, // DDRSS_PHY_304_VAL + 0x00000000U, // DDRSS_PHY_305_VAL + 0x00000000U, // DDRSS_PHY_306_VAL + 0x00000000U, // DDRSS_PHY_307_VAL + 0x00000000U, // DDRSS_PHY_308_VAL + 0x00000000U, // DDRSS_PHY_309_VAL + 0x00000000U, // DDRSS_PHY_310_VAL + 0x00000000U, // DDRSS_PHY_311_VAL + 0x00000000U, // DDRSS_PHY_312_VAL + 0x00000000U, // DDRSS_PHY_313_VAL + 0x00000000U, // DDRSS_PHY_314_VAL + 0x00000000U, // DDRSS_PHY_315_VAL + 0x00000000U, // DDRSS_PHY_316_VAL + 0x00000000U, // DDRSS_PHY_317_VAL + 0x00000000U, // DDRSS_PHY_318_VAL + 0x00000000U, // DDRSS_PHY_319_VAL + 0x00000000U, // DDRSS_PHY_320_VAL + 0x00000000U, // DDRSS_PHY_321_VAL + 0x00000000U, // DDRSS_PHY_322_VAL + 0x00000004U, // DDRSS_PHY_323_VAL + 0x00000000U, // DDRSS_PHY_324_VAL + 0x00000000U, // DDRSS_PHY_325_VAL + 0x00000000U, // DDRSS_PHY_326_VAL + 0x00000000U, // DDRSS_PHY_327_VAL + 0x00000000U, // DDRSS_PHY_328_VAL + 0x00000000U, // DDRSS_PHY_329_VAL + 0x081F07FFU, // DDRSS_PHY_330_VAL + 0x10200080U, // DDRSS_PHY_331_VAL + 0x00000008U, // DDRSS_PHY_332_VAL + 0x00000401U, // DDRSS_PHY_333_VAL + 0x00000000U, // DDRSS_PHY_334_VAL + 0x01CC0B01U, // DDRSS_PHY_335_VAL + 0x1003CC0BU, // DDRSS_PHY_336_VAL + 0x20000140U, // DDRSS_PHY_337_VAL + 0x07FF0200U, // DDRSS_PHY_338_VAL + 0x0000DD01U, // DDRSS_PHY_339_VAL + 0x00100303U, // DDRSS_PHY_340_VAL + 0x00000000U, // DDRSS_PHY_341_VAL + 0x00000000U, // DDRSS_PHY_342_VAL + 0x00031000U, // DDRSS_PHY_343_VAL + 0x00100010U, // DDRSS_PHY_344_VAL + 0x00100010U, // DDRSS_PHY_345_VAL + 0x00100010U, // DDRSS_PHY_346_VAL + 0x00100010U, // DDRSS_PHY_347_VAL + 0x02000010U, // DDRSS_PHY_348_VAL + 0x00000004U, // DDRSS_PHY_349_VAL + 0x51516042U, // DDRSS_PHY_350_VAL + 0x31C06000U, // DDRSS_PHY_351_VAL + 0x07AB0340U, // DDRSS_PHY_352_VAL + 0x00C0C001U, // DDRSS_PHY_353_VAL + 0x0B000000U, // DDRSS_PHY_354_VAL + 0x000B0A0AU, // DDRSS_PHY_355_VAL + 0x42100010U, // DDRSS_PHY_356_VAL + 0x010C073EU, // DDRSS_PHY_357_VAL + 0x000F0C2DU, // DDRSS_PHY_358_VAL + 0x01000140U, // DDRSS_PHY_359_VAL + 0x00F50120U, // DDRSS_PHY_360_VAL + 0x00000C00U, // DDRSS_PHY_361_VAL + 0x00000299U, // DDRSS_PHY_362_VAL + 0x00030200U, // DDRSS_PHY_363_VAL + 0x02800000U, // DDRSS_PHY_364_VAL + 0x80800000U, // DDRSS_PHY_365_VAL + 0x000B2010U, // DDRSS_PHY_366_VAL + 0x17520684U, // DDRSS_PHY_367_VAL + 0x00000003U, // DDRSS_PHY_368_VAL + 0x04190419U, // DDRSS_PHY_369_VAL + 0x04190419U, // DDRSS_PHY_370_VAL + 0x04190419U, // DDRSS_PHY_371_VAL + 0x04190419U, // DDRSS_PHY_372_VAL + 0x00000419U, // DDRSS_PHY_373_VAL + 0x0000A000U, // DDRSS_PHY_374_VAL + 0x00A000A0U, // DDRSS_PHY_375_VAL + 0x00A000A0U, // DDRSS_PHY_376_VAL + 0x00A000A0U, // DDRSS_PHY_377_VAL + 0x00A000A0U, // DDRSS_PHY_378_VAL + 0x00A000A0U, // DDRSS_PHY_379_VAL + 0x00A000A0U, // DDRSS_PHY_380_VAL + 0x00A000A0U, // DDRSS_PHY_381_VAL + 0x00A000A0U, // DDRSS_PHY_382_VAL + 0x01E600A0U, // DDRSS_PHY_383_VAL + 0x01000000U, // DDRSS_PHY_384_VAL + 0x00000000U, // DDRSS_PHY_385_VAL + 0x00000000U, // DDRSS_PHY_386_VAL + 0x00080200U, // DDRSS_PHY_387_VAL + 0x00000000U, // DDRSS_PHY_388_VAL + 0x20202020U, // DDRSS_PHY_389_VAL + 0x20202020U, // DDRSS_PHY_390_VAL + 0xF0F02020U, // DDRSS_PHY_391_VAL + 0x00000000U, // DDRSS_PHY_392_VAL + 0x04F00000U, // DDRSS_PHY_512_VAL + 0x00000000U, // DDRSS_PHY_513_VAL + 0x00030200U, // DDRSS_PHY_514_VAL + 0x00000000U, // DDRSS_PHY_515_VAL + 0x00000000U, // DDRSS_PHY_516_VAL + 0x01030000U, // DDRSS_PHY_517_VAL + 0x00010000U, // DDRSS_PHY_518_VAL + 0x01030004U, // DDRSS_PHY_519_VAL + 0x01000000U, // DDRSS_PHY_520_VAL + 0x00000000U, // DDRSS_PHY_521_VAL + 0x00000000U, // DDRSS_PHY_522_VAL + 0x00000000U, // DDRSS_PHY_523_VAL + 0x01010000U, // DDRSS_PHY_524_VAL + 0x00010000U, // DDRSS_PHY_525_VAL + 0x00C00001U, // DDRSS_PHY_526_VAL + 0x00CC0008U, // DDRSS_PHY_527_VAL + 0x00660601U, // DDRSS_PHY_528_VAL + 0x00000003U, // DDRSS_PHY_529_VAL + 0x00000000U, // DDRSS_PHY_530_VAL + 0x00000001U, // DDRSS_PHY_531_VAL + 0x0000AAAAU, // DDRSS_PHY_532_VAL + 0x00005555U, // DDRSS_PHY_533_VAL + 0x0000B5B5U, // DDRSS_PHY_534_VAL + 0x00004A4AU, // DDRSS_PHY_535_VAL + 0x00005656U, // DDRSS_PHY_536_VAL + 0x0000A9A9U, // DDRSS_PHY_537_VAL + 0x0000B7B7U, // DDRSS_PHY_538_VAL + 0x00004848U, // DDRSS_PHY_539_VAL + 0x00000000U, // DDRSS_PHY_540_VAL + 0x00000000U, // DDRSS_PHY_541_VAL + 0x08000000U, // DDRSS_PHY_542_VAL + 0x0F000008U, // DDRSS_PHY_543_VAL + 0x00000F0FU, // DDRSS_PHY_544_VAL + 0x00E4E400U, // DDRSS_PHY_545_VAL + 0x00071020U, // DDRSS_PHY_546_VAL + 0x000C0020U, // DDRSS_PHY_547_VAL + 0x00062000U, // DDRSS_PHY_548_VAL + 0x00000000U, // DDRSS_PHY_549_VAL + 0x55555555U, // DDRSS_PHY_550_VAL + 0xAAAAAAAAU, // DDRSS_PHY_551_VAL + 0x55555555U, // DDRSS_PHY_552_VAL + 0xAAAAAAAAU, // DDRSS_PHY_553_VAL + 0x00005555U, // DDRSS_PHY_554_VAL + 0x01000100U, // DDRSS_PHY_555_VAL + 0x00800180U, // DDRSS_PHY_556_VAL + 0x00000001U, // DDRSS_PHY_557_VAL + 0x00000000U, // DDRSS_PHY_558_VAL + 0x00000000U, // DDRSS_PHY_559_VAL + 0x00000000U, // DDRSS_PHY_560_VAL + 0x00000000U, // DDRSS_PHY_561_VAL + 0x00000000U, // DDRSS_PHY_562_VAL + 0x00000000U, // DDRSS_PHY_563_VAL + 0x00000000U, // DDRSS_PHY_564_VAL + 0x00000000U, // DDRSS_PHY_565_VAL + 0x00000000U, // DDRSS_PHY_566_VAL + 0x00000000U, // DDRSS_PHY_567_VAL + 0x00000000U, // DDRSS_PHY_568_VAL + 0x00000000U, // DDRSS_PHY_569_VAL + 0x00000000U, // DDRSS_PHY_570_VAL + 0x00000000U, // DDRSS_PHY_571_VAL + 0x00000000U, // DDRSS_PHY_572_VAL + 0x00000000U, // DDRSS_PHY_573_VAL + 0x00000000U, // DDRSS_PHY_574_VAL + 0x00000000U, // DDRSS_PHY_575_VAL + 0x00000000U, // DDRSS_PHY_576_VAL + 0x00000000U, // DDRSS_PHY_577_VAL + 0x00000000U, // DDRSS_PHY_578_VAL + 0x00000004U, // DDRSS_PHY_579_VAL + 0x00000000U, // DDRSS_PHY_580_VAL + 0x00000000U, // DDRSS_PHY_581_VAL + 0x00000000U, // DDRSS_PHY_582_VAL + 0x00000000U, // DDRSS_PHY_583_VAL + 0x00000000U, // DDRSS_PHY_584_VAL + 0x00000000U, // DDRSS_PHY_585_VAL + 0x081F07FFU, // DDRSS_PHY_586_VAL + 0x10200080U, // DDRSS_PHY_587_VAL + 0x00000008U, // DDRSS_PHY_588_VAL + 0x00000401U, // DDRSS_PHY_589_VAL + 0x00000000U, // DDRSS_PHY_590_VAL + 0x01CC0B01U, // DDRSS_PHY_591_VAL + 0x1003CC0BU, // DDRSS_PHY_592_VAL + 0x20000140U, // DDRSS_PHY_593_VAL + 0x07FF0200U, // DDRSS_PHY_594_VAL + 0x0000DD01U, // DDRSS_PHY_595_VAL + 0x00100303U, // DDRSS_PHY_596_VAL + 0x00000000U, // DDRSS_PHY_597_VAL + 0x00000000U, // DDRSS_PHY_598_VAL + 0x00031000U, // DDRSS_PHY_599_VAL + 0x00100010U, // DDRSS_PHY_600_VAL + 0x00100010U, // DDRSS_PHY_601_VAL + 0x00100010U, // DDRSS_PHY_602_VAL + 0x00100010U, // DDRSS_PHY_603_VAL + 0x02000010U, // DDRSS_PHY_604_VAL + 0x00000004U, // DDRSS_PHY_605_VAL + 0x51516042U, // DDRSS_PHY_606_VAL + 0x31C06000U, // DDRSS_PHY_607_VAL + 0x07AB0340U, // DDRSS_PHY_608_VAL + 0x00C0C001U, // DDRSS_PHY_609_VAL + 0x0B000000U, // DDRSS_PHY_610_VAL + 0x000B0A0AU, // DDRSS_PHY_611_VAL + 0x42100010U, // DDRSS_PHY_612_VAL + 0x010C073EU, // DDRSS_PHY_613_VAL + 0x000F0C2DU, // DDRSS_PHY_614_VAL + 0x01000140U, // DDRSS_PHY_615_VAL + 0x00F50120U, // DDRSS_PHY_616_VAL + 0x00000C00U, // DDRSS_PHY_617_VAL + 0x00000299U, // DDRSS_PHY_618_VAL + 0x00030200U, // DDRSS_PHY_619_VAL + 0x02800000U, // DDRSS_PHY_620_VAL + 0x80800000U, // DDRSS_PHY_621_VAL + 0x000B2010U, // DDRSS_PHY_622_VAL + 0x07684523U, // DDRSS_PHY_623_VAL + 0x00000001U, // DDRSS_PHY_624_VAL + 0x04190419U, // DDRSS_PHY_625_VAL + 0x04190419U, // DDRSS_PHY_626_VAL + 0x04190419U, // DDRSS_PHY_627_VAL + 0x04190419U, // DDRSS_PHY_628_VAL + 0x00000419U, // DDRSS_PHY_629_VAL + 0x0000A000U, // DDRSS_PHY_630_VAL + 0x00A000A0U, // DDRSS_PHY_631_VAL + 0x00A000A0U, // DDRSS_PHY_632_VAL + 0x00A000A0U, // DDRSS_PHY_633_VAL + 0x00A000A0U, // DDRSS_PHY_634_VAL + 0x00A000A0U, // DDRSS_PHY_635_VAL + 0x00A000A0U, // DDRSS_PHY_636_VAL + 0x00A000A0U, // DDRSS_PHY_637_VAL + 0x00A000A0U, // DDRSS_PHY_638_VAL + 0x01E600A0U, // DDRSS_PHY_639_VAL + 0x01000000U, // DDRSS_PHY_640_VAL + 0x00000000U, // DDRSS_PHY_641_VAL + 0x00000000U, // DDRSS_PHY_642_VAL + 0x00080200U, // DDRSS_PHY_643_VAL + 0x00000000U, // DDRSS_PHY_644_VAL + 0x20202020U, // DDRSS_PHY_645_VAL + 0x20202020U, // DDRSS_PHY_646_VAL + 0xF0F02020U, // DDRSS_PHY_647_VAL + 0x00000000U, // DDRSS_PHY_648_VAL + 0x04F00000U, // DDRSS_PHY_768_VAL + 0x00000000U, // DDRSS_PHY_769_VAL + 0x00030200U, // DDRSS_PHY_770_VAL + 0x00000000U, // DDRSS_PHY_771_VAL + 0x00000000U, // DDRSS_PHY_772_VAL + 0x01030000U, // DDRSS_PHY_773_VAL + 0x00010000U, // DDRSS_PHY_774_VAL + 0x01030004U, // DDRSS_PHY_775_VAL + 0x01000000U, // DDRSS_PHY_776_VAL + 0x00000000U, // DDRSS_PHY_777_VAL + 0x00000000U, // DDRSS_PHY_778_VAL + 0x00000000U, // DDRSS_PHY_779_VAL + 0x01010000U, // DDRSS_PHY_780_VAL + 0x00010000U, // DDRSS_PHY_781_VAL + 0x00C00001U, // DDRSS_PHY_782_VAL + 0x00CC0008U, // DDRSS_PHY_783_VAL + 0x00660601U, // DDRSS_PHY_784_VAL + 0x00000003U, // DDRSS_PHY_785_VAL + 0x00000000U, // DDRSS_PHY_786_VAL + 0x00000001U, // DDRSS_PHY_787_VAL + 0x0000AAAAU, // DDRSS_PHY_788_VAL + 0x00005555U, // DDRSS_PHY_789_VAL + 0x0000B5B5U, // DDRSS_PHY_790_VAL + 0x00004A4AU, // DDRSS_PHY_791_VAL + 0x00005656U, // DDRSS_PHY_792_VAL + 0x0000A9A9U, // DDRSS_PHY_793_VAL + 0x0000B7B7U, // DDRSS_PHY_794_VAL + 0x00004848U, // DDRSS_PHY_795_VAL + 0x00000000U, // DDRSS_PHY_796_VAL + 0x00000000U, // DDRSS_PHY_797_VAL + 0x08000000U, // DDRSS_PHY_798_VAL + 0x0F000008U, // DDRSS_PHY_799_VAL + 0x00000F0FU, // DDRSS_PHY_800_VAL + 0x00E4E400U, // DDRSS_PHY_801_VAL + 0x00071020U, // DDRSS_PHY_802_VAL + 0x000C0020U, // DDRSS_PHY_803_VAL + 0x00062000U, // DDRSS_PHY_804_VAL + 0x00000000U, // DDRSS_PHY_805_VAL + 0x55555555U, // DDRSS_PHY_806_VAL + 0xAAAAAAAAU, // DDRSS_PHY_807_VAL + 0x55555555U, // DDRSS_PHY_808_VAL + 0xAAAAAAAAU, // DDRSS_PHY_809_VAL + 0x00005555U, // DDRSS_PHY_810_VAL + 0x01000100U, // DDRSS_PHY_811_VAL + 0x00800180U, // DDRSS_PHY_812_VAL + 0x00000000U, // DDRSS_PHY_813_VAL + 0x00000000U, // DDRSS_PHY_814_VAL + 0x00000000U, // DDRSS_PHY_815_VAL + 0x00000000U, // DDRSS_PHY_816_VAL + 0x00000000U, // DDRSS_PHY_817_VAL + 0x00000000U, // DDRSS_PHY_818_VAL + 0x00000000U, // DDRSS_PHY_819_VAL + 0x00000000U, // DDRSS_PHY_820_VAL + 0x00000000U, // DDRSS_PHY_821_VAL + 0x00000000U, // DDRSS_PHY_822_VAL + 0x00000000U, // DDRSS_PHY_823_VAL + 0x00000000U, // DDRSS_PHY_824_VAL + 0x00000000U, // DDRSS_PHY_825_VAL + 0x00000000U, // DDRSS_PHY_826_VAL + 0x00000000U, // DDRSS_PHY_827_VAL + 0x00000000U, // DDRSS_PHY_828_VAL + 0x00000000U, // DDRSS_PHY_829_VAL + 0x00000000U, // DDRSS_PHY_830_VAL + 0x00000000U, // DDRSS_PHY_831_VAL + 0x00000000U, // DDRSS_PHY_832_VAL + 0x00000000U, // DDRSS_PHY_833_VAL + 0x00000000U, // DDRSS_PHY_834_VAL + 0x00000004U, // DDRSS_PHY_835_VAL + 0x00000000U, // DDRSS_PHY_836_VAL + 0x00000000U, // DDRSS_PHY_837_VAL + 0x00000000U, // DDRSS_PHY_838_VAL + 0x00000000U, // DDRSS_PHY_839_VAL + 0x00000000U, // DDRSS_PHY_840_VAL + 0x00000000U, // DDRSS_PHY_841_VAL + 0x081F07FFU, // DDRSS_PHY_842_VAL + 0x10200080U, // DDRSS_PHY_843_VAL + 0x00000008U, // DDRSS_PHY_844_VAL + 0x00000401U, // DDRSS_PHY_845_VAL + 0x00000000U, // DDRSS_PHY_846_VAL + 0x01CC0B01U, // DDRSS_PHY_847_VAL + 0x1003CC0BU, // DDRSS_PHY_848_VAL + 0x20000140U, // DDRSS_PHY_849_VAL + 0x07FF0200U, // DDRSS_PHY_850_VAL + 0x0000DD01U, // DDRSS_PHY_851_VAL + 0x00100303U, // DDRSS_PHY_852_VAL + 0x00000000U, // DDRSS_PHY_853_VAL + 0x00000000U, // DDRSS_PHY_854_VAL + 0x00031000U, // DDRSS_PHY_855_VAL + 0x00100010U, // DDRSS_PHY_856_VAL + 0x00100010U, // DDRSS_PHY_857_VAL + 0x00100010U, // DDRSS_PHY_858_VAL + 0x00100010U, // DDRSS_PHY_859_VAL + 0x02000010U, // DDRSS_PHY_860_VAL + 0x00000004U, // DDRSS_PHY_861_VAL + 0x51516042U, // DDRSS_PHY_862_VAL + 0x31C06000U, // DDRSS_PHY_863_VAL + 0x07AB0340U, // DDRSS_PHY_864_VAL + 0x00C0C001U, // DDRSS_PHY_865_VAL + 0x0B000000U, // DDRSS_PHY_866_VAL + 0x000B0A0AU, // DDRSS_PHY_867_VAL + 0x42100010U, // DDRSS_PHY_868_VAL + 0x010C073EU, // DDRSS_PHY_869_VAL + 0x000F0C2DU, // DDRSS_PHY_870_VAL + 0x01000140U, // DDRSS_PHY_871_VAL + 0x00F50120U, // DDRSS_PHY_872_VAL + 0x00000C00U, // DDRSS_PHY_873_VAL + 0x00000299U, // DDRSS_PHY_874_VAL + 0x00030200U, // DDRSS_PHY_875_VAL + 0x02800000U, // DDRSS_PHY_876_VAL + 0x80800000U, // DDRSS_PHY_877_VAL + 0x000B2010U, // DDRSS_PHY_878_VAL + 0x76158234U, // DDRSS_PHY_879_VAL + 0x00000000U, // DDRSS_PHY_880_VAL + 0x04190419U, // DDRSS_PHY_881_VAL + 0x04190419U, // DDRSS_PHY_882_VAL + 0x04190419U, // DDRSS_PHY_883_VAL + 0x04190419U, // DDRSS_PHY_884_VAL + 0x00000419U, // DDRSS_PHY_885_VAL + 0x0000A000U, // DDRSS_PHY_886_VAL + 0x00A000A0U, // DDRSS_PHY_887_VAL + 0x00A000A0U, // DDRSS_PHY_888_VAL + 0x00A000A0U, // DDRSS_PHY_889_VAL + 0x00A000A0U, // DDRSS_PHY_890_VAL + 0x00A000A0U, // DDRSS_PHY_891_VAL + 0x00A000A0U, // DDRSS_PHY_892_VAL + 0x00A000A0U, // DDRSS_PHY_893_VAL + 0x00A000A0U, // DDRSS_PHY_894_VAL + 0x01E600A0U, // DDRSS_PHY_895_VAL + 0x01000000U, // DDRSS_PHY_896_VAL + 0x00000000U, // DDRSS_PHY_897_VAL + 0x00000000U, // DDRSS_PHY_898_VAL + 0x00080200U, // DDRSS_PHY_899_VAL + 0x00000000U, // DDRSS_PHY_900_VAL + 0x20202020U, // DDRSS_PHY_901_VAL + 0x20202020U, // DDRSS_PHY_902_VAL + 0xF0F02020U, // DDRSS_PHY_903_VAL + 0x00000000U, // DDRSS_PHY_904_VAL + 0x00000000U, // DDRSS_PHY_1024_VAL + 0x00000000U, // DDRSS_PHY_1025_VAL + 0x00000000U, // DDRSS_PHY_1026_VAL + 0x00000000U, // DDRSS_PHY_1027_VAL + 0x00000000U, // DDRSS_PHY_1028_VAL + 0x00000100U, // DDRSS_PHY_1029_VAL + 0x00000200U, // DDRSS_PHY_1030_VAL + 0x00000000U, // DDRSS_PHY_1031_VAL + 0x00000000U, // DDRSS_PHY_1032_VAL + 0x00000000U, // DDRSS_PHY_1033_VAL + 0x00000000U, // DDRSS_PHY_1034_VAL + 0x00400000U, // DDRSS_PHY_1035_VAL + 0x00000080U, // DDRSS_PHY_1036_VAL + 0x00DCBA98U, // DDRSS_PHY_1037_VAL + 0x03000000U, // DDRSS_PHY_1038_VAL + 0x00200000U, // DDRSS_PHY_1039_VAL + 0x00000000U, // DDRSS_PHY_1040_VAL + 0x00000000U, // DDRSS_PHY_1041_VAL + 0x00000000U, // DDRSS_PHY_1042_VAL + 0x00000000U, // DDRSS_PHY_1043_VAL + 0x00000000U, // DDRSS_PHY_1044_VAL + 0x0000002AU, // DDRSS_PHY_1045_VAL + 0x00000015U, // DDRSS_PHY_1046_VAL + 0x00000015U, // DDRSS_PHY_1047_VAL + 0x0000002AU, // DDRSS_PHY_1048_VAL + 0x00000033U, // DDRSS_PHY_1049_VAL + 0x0000000CU, // DDRSS_PHY_1050_VAL + 0x0000000CU, // DDRSS_PHY_1051_VAL + 0x00000033U, // DDRSS_PHY_1052_VAL + 0x0A418820U, // DDRSS_PHY_1053_VAL + 0x003F0000U, // DDRSS_PHY_1054_VAL + 0x000F013FU, // DDRSS_PHY_1055_VAL + 0x20202003U, // DDRSS_PHY_1056_VAL + 0x00202020U, // DDRSS_PHY_1057_VAL + 0x20008008U, // DDRSS_PHY_1058_VAL + 0x00000810U, // DDRSS_PHY_1059_VAL + 0x00000F00U, // DDRSS_PHY_1060_VAL + 0x000304CCU, // DDRSS_PHY_1061_VAL + 0x03000003U, // DDRSS_PHY_1062_VAL + 0x00030000U, // DDRSS_PHY_1063_VAL + 0x00000300U, // DDRSS_PHY_1064_VAL + 0x00000300U, // DDRSS_PHY_1065_VAL + 0x00000300U, // DDRSS_PHY_1066_VAL + 0x00000300U, // DDRSS_PHY_1067_VAL + 0x42080010U, // DDRSS_PHY_1068_VAL + 0x0000803EU, // DDRSS_PHY_1069_VAL + 0x00000001U, // DDRSS_PHY_1070_VAL + 0x01000002U, // DDRSS_PHY_1071_VAL + 0x00008000U, // DDRSS_PHY_1072_VAL + 0x00000000U, // DDRSS_PHY_1280_VAL + 0x00000000U, // DDRSS_PHY_1281_VAL + 0x00000000U, // DDRSS_PHY_1282_VAL + 0x00000000U, // DDRSS_PHY_1283_VAL + 0x00000000U, // DDRSS_PHY_1284_VAL + 0x00000100U, // DDRSS_PHY_1285_VAL + 0x00000200U, // DDRSS_PHY_1286_VAL + 0x00000000U, // DDRSS_PHY_1287_VAL + 0x00000000U, // DDRSS_PHY_1288_VAL + 0x00000000U, // DDRSS_PHY_1289_VAL + 0x00000000U, // DDRSS_PHY_1290_VAL + 0x00400000U, // DDRSS_PHY_1291_VAL + 0x00000080U, // DDRSS_PHY_1292_VAL + 0x00DCBA98U, // DDRSS_PHY_1293_VAL + 0x03000000U, // DDRSS_PHY_1294_VAL + 0x00200000U, // DDRSS_PHY_1295_VAL + 0x00000000U, // DDRSS_PHY_1296_VAL + 0x00000000U, // DDRSS_PHY_1297_VAL + 0x00000000U, // DDRSS_PHY_1298_VAL + 0x00000000U, // DDRSS_PHY_1299_VAL + 0x00000000U, // DDRSS_PHY_1300_VAL + 0x0000002AU, // DDRSS_PHY_1301_VAL + 0x00000015U, // DDRSS_PHY_1302_VAL + 0x00000015U, // DDRSS_PHY_1303_VAL + 0x0000002AU, // DDRSS_PHY_1304_VAL + 0x00000033U, // DDRSS_PHY_1305_VAL + 0x0000000CU, // DDRSS_PHY_1306_VAL + 0x0000000CU, // DDRSS_PHY_1307_VAL + 0x00000033U, // DDRSS_PHY_1308_VAL + 0x0A418820U, // DDRSS_PHY_1309_VAL + 0x00000000U, // DDRSS_PHY_1310_VAL + 0x000F0000U, // DDRSS_PHY_1311_VAL + 0x20202003U, // DDRSS_PHY_1312_VAL + 0x00202020U, // DDRSS_PHY_1313_VAL + 0x20008008U, // DDRSS_PHY_1314_VAL + 0x00000810U, // DDRSS_PHY_1315_VAL + 0x00000F00U, // DDRSS_PHY_1316_VAL + 0x000304CCU, // DDRSS_PHY_1317_VAL + 0x03000003U, // DDRSS_PHY_1318_VAL + 0x00030000U, // DDRSS_PHY_1319_VAL + 0x00000300U, // DDRSS_PHY_1320_VAL + 0x00000300U, // DDRSS_PHY_1321_VAL + 0x00000300U, // DDRSS_PHY_1322_VAL + 0x00000300U, // DDRSS_PHY_1323_VAL + 0x42080010U, // DDRSS_PHY_1324_VAL + 0x0000803EU, // DDRSS_PHY_1325_VAL + 0x00000001U, // DDRSS_PHY_1326_VAL + 0x01000002U, // DDRSS_PHY_1327_VAL + 0x00008000U, // DDRSS_PHY_1328_VAL + 0x00000000U, // DDRSS_PHY_1536_VAL + 0x00000000U, // DDRSS_PHY_1537_VAL + 0x00000000U, // DDRSS_PHY_1538_VAL + 0x00000000U, // DDRSS_PHY_1539_VAL + 0x00000000U, // DDRSS_PHY_1540_VAL + 0x00000100U, // DDRSS_PHY_1541_VAL + 0x00000200U, // DDRSS_PHY_1542_VAL + 0x00000000U, // DDRSS_PHY_1543_VAL + 0x00000000U, // DDRSS_PHY_1544_VAL + 0x00000000U, // DDRSS_PHY_1545_VAL + 0x00000000U, // DDRSS_PHY_1546_VAL + 0x00400000U, // DDRSS_PHY_1547_VAL + 0x00000080U, // DDRSS_PHY_1548_VAL + 0x00DCBA98U, // DDRSS_PHY_1549_VAL + 0x03000000U, // DDRSS_PHY_1550_VAL + 0x00200000U, // DDRSS_PHY_1551_VAL + 0x00000000U, // DDRSS_PHY_1552_VAL + 0x00000000U, // DDRSS_PHY_1553_VAL + 0x00000000U, // DDRSS_PHY_1554_VAL + 0x00000000U, // DDRSS_PHY_1555_VAL + 0x00000000U, // DDRSS_PHY_1556_VAL + 0x0000002AU, // DDRSS_PHY_1557_VAL + 0x00000015U, // DDRSS_PHY_1558_VAL + 0x00000015U, // DDRSS_PHY_1559_VAL + 0x0000002AU, // DDRSS_PHY_1560_VAL + 0x00000033U, // DDRSS_PHY_1561_VAL + 0x0000000CU, // DDRSS_PHY_1562_VAL + 0x0000000CU, // DDRSS_PHY_1563_VAL + 0x00000033U, // DDRSS_PHY_1564_VAL + 0x0A418820U, // DDRSS_PHY_1565_VAL + 0x10000000U, // DDRSS_PHY_1566_VAL + 0x000F0000U, // DDRSS_PHY_1567_VAL + 0x20202003U, // DDRSS_PHY_1568_VAL + 0x00202020U, // DDRSS_PHY_1569_VAL + 0x20008008U, // DDRSS_PHY_1570_VAL + 0x00000810U, // DDRSS_PHY_1571_VAL + 0x00000F00U, // DDRSS_PHY_1572_VAL + 0x000304CCU, // DDRSS_PHY_1573_VAL + 0x03000003U, // DDRSS_PHY_1574_VAL + 0x00030000U, // DDRSS_PHY_1575_VAL + 0x00000300U, // DDRSS_PHY_1576_VAL + 0x00000300U, // DDRSS_PHY_1577_VAL + 0x00000300U, // DDRSS_PHY_1578_VAL + 0x00000300U, // DDRSS_PHY_1579_VAL + 0x42080010U, // DDRSS_PHY_1580_VAL + 0x0000803EU, // DDRSS_PHY_1581_VAL + 0x00000001U, // DDRSS_PHY_1582_VAL + 0x01000002U, // DDRSS_PHY_1583_VAL + 0x00008000U, // DDRSS_PHY_1584_VAL + 0x00000000U, // DDRSS_PHY_1792_VAL + 0x00010100U, // DDRSS_PHY_1793_VAL + 0x00000000U, // DDRSS_PHY_1794_VAL + 0x00000000U, // DDRSS_PHY_1795_VAL + 0x00000000U, // DDRSS_PHY_1796_VAL + 0x00000000U, // DDRSS_PHY_1797_VAL + 0x00050000U, // DDRSS_PHY_1798_VAL + 0x04000000U, // DDRSS_PHY_1799_VAL + 0x00000055U, // DDRSS_PHY_1800_VAL + 0x00000000U, // DDRSS_PHY_1801_VAL + 0x00000000U, // DDRSS_PHY_1802_VAL + 0x00000000U, // DDRSS_PHY_1803_VAL + 0x00000000U, // DDRSS_PHY_1804_VAL + 0x00002001U, // DDRSS_PHY_1805_VAL + 0x00004003U, // DDRSS_PHY_1806_VAL + 0x50020028U, // DDRSS_PHY_1807_VAL + 0x01010000U, // DDRSS_PHY_1808_VAL + 0x80080001U, // DDRSS_PHY_1809_VAL + 0x10200000U, // DDRSS_PHY_1810_VAL + 0x00000008U, // DDRSS_PHY_1811_VAL + 0x00000000U, // DDRSS_PHY_1812_VAL + 0x06000000U, // DDRSS_PHY_1813_VAL + 0x010F0F0EU, // DDRSS_PHY_1814_VAL + 0x00040101U, // DDRSS_PHY_1815_VAL + 0x0000010FU, // DDRSS_PHY_1816_VAL + 0x00000000U, // DDRSS_PHY_1817_VAL + 0x00000064U, // DDRSS_PHY_1818_VAL + 0x00000000U, // DDRSS_PHY_1819_VAL + 0x00000000U, // DDRSS_PHY_1820_VAL + 0x0F0F0F01U, // DDRSS_PHY_1821_VAL + 0x0F0F0F02U, // DDRSS_PHY_1822_VAL + 0x0F0F0F0FU, // DDRSS_PHY_1823_VAL + 0x0F0F0804U, // DDRSS_PHY_1824_VAL + 0x00800120U, // DDRSS_PHY_1825_VAL + 0x00041B42U, // DDRSS_PHY_1826_VAL + 0x00004201U, // DDRSS_PHY_1827_VAL + 0x00000000U, // DDRSS_PHY_1828_VAL + 0x00000000U, // DDRSS_PHY_1829_VAL + 0x00000000U, // DDRSS_PHY_1830_VAL + 0x00000000U, // DDRSS_PHY_1831_VAL + 0x00000000U, // DDRSS_PHY_1832_VAL + 0x00000000U, // DDRSS_PHY_1833_VAL + 0x03010100U, // DDRSS_PHY_1834_VAL + 0x00540007U, // DDRSS_PHY_1835_VAL + 0x000040A2U, // DDRSS_PHY_1836_VAL + 0x00024410U, // DDRSS_PHY_1837_VAL + 0x00004410U, // DDRSS_PHY_1838_VAL + 0x00004410U, // DDRSS_PHY_1839_VAL + 0x00004410U, // DDRSS_PHY_1840_VAL + 0x00004410U, // DDRSS_PHY_1841_VAL + 0x00004410U, // DDRSS_PHY_1842_VAL + 0x00004410U, // DDRSS_PHY_1843_VAL + 0x00004410U, // DDRSS_PHY_1844_VAL + 0x00004410U, // DDRSS_PHY_1845_VAL + 0x00004410U, // DDRSS_PHY_1846_VAL + 0x00000000U, // DDRSS_PHY_1847_VAL + 0x00000076U, // DDRSS_PHY_1848_VAL + 0x00000400U, // DDRSS_PHY_1849_VAL + 0x00000008U, // DDRSS_PHY_1850_VAL + 0x00000000U, // DDRSS_PHY_1851_VAL + 0x00000000U, // DDRSS_PHY_1852_VAL + 0x00000000U, // DDRSS_PHY_1853_VAL + 0x00000000U, // DDRSS_PHY_1854_VAL + 0x00000000U, // DDRSS_PHY_1855_VAL + 0x03000000U, // DDRSS_PHY_1856_VAL + 0x00000000U, // DDRSS_PHY_1857_VAL + 0x00000000U, // DDRSS_PHY_1858_VAL + 0x00000000U, // DDRSS_PHY_1859_VAL + 0x04102006U, // DDRSS_PHY_1860_VAL + 0x00041020U, // DDRSS_PHY_1861_VAL + 0x01C98C98U, // DDRSS_PHY_1862_VAL + 0x3F400000U, // DDRSS_PHY_1863_VAL + 0x3F3F1F3FU, // DDRSS_PHY_1864_VAL + 0x0000001FU, // DDRSS_PHY_1865_VAL + 0x00000000U, // DDRSS_PHY_1866_VAL + 0x00000000U, // DDRSS_PHY_1867_VAL + 0x00000000U, // DDRSS_PHY_1868_VAL + 0x00000001U, // DDRSS_PHY_1869_VAL + 0x00000000U, // DDRSS_PHY_1870_VAL + 0x00000000U, // DDRSS_PHY_1871_VAL + 0x00000000U, // DDRSS_PHY_1872_VAL + 0x00000000U, // DDRSS_PHY_1873_VAL + 0x76543210U, // DDRSS_PHY_1874_VAL + 0x06010198U, // DDRSS_PHY_1875_VAL + 0x00000000U, // DDRSS_PHY_1876_VAL + 0x00000000U, // DDRSS_PHY_1877_VAL + 0x00000000U, // DDRSS_PHY_1878_VAL + 0x00040700U, // DDRSS_PHY_1879_VAL + 0x00000000U, // DDRSS_PHY_1880_VAL + 0x00000000U, // DDRSS_PHY_1881_VAL + 0x00000000U, // DDRSS_PHY_1882_VAL + 0x00000000U, // DDRSS_PHY_1883_VAL + 0x00000000U, // DDRSS_PHY_1884_VAL + 0x00000002U, // DDRSS_PHY_1885_VAL + 0x00000000U, // DDRSS_PHY_1886_VAL + 0x00000000U, // DDRSS_PHY_1887_VAL + 0x0001F7C3U, // DDRSS_PHY_1888_VAL + 0x03000003U, // DDRSS_PHY_1889_VAL + 0x00000000U, // DDRSS_PHY_1890_VAL + 0x00001142U, // DDRSS_PHY_1891_VAL + 0x01020000U, // DDRSS_PHY_1892_VAL + 0x00000080U, // DDRSS_PHY_1893_VAL + 0x03900390U, // DDRSS_PHY_1894_VAL + 0x03900390U, // DDRSS_PHY_1895_VAL + 0x03900390U, // DDRSS_PHY_1896_VAL + 0x03900390U, // DDRSS_PHY_1897_VAL + 0x03000300U, // DDRSS_PHY_1898_VAL + 0x03000300U, // DDRSS_PHY_1899_VAL + 0x00000300U, // DDRSS_PHY_1900_VAL + 0x00000300U, // DDRSS_PHY_1901_VAL + 0x00000300U, // DDRSS_PHY_1902_VAL + 0x00000300U, // DDRSS_PHY_1903_VAL + 0x00000004U, // DDRSS_PHY_1904_VAL + 0x3183BF77U, // DDRSS_PHY_1905_VAL + 0x00000000U, // DDRSS_PHY_1906_VAL + 0x0C000DFFU, // DDRSS_PHY_1907_VAL + 0x30000DFFU, // DDRSS_PHY_1908_VAL + 0x3F0DFF11U, // DDRSS_PHY_1909_VAL + 0x00EF0000U, // DDRSS_PHY_1910_VAL + 0x780DFFCCU, // DDRSS_PHY_1911_VAL + 0x00000C11U, // DDRSS_PHY_1912_VAL + 0x00018011U, // DDRSS_PHY_1913_VAL + 0x0089FF00U, // DDRSS_PHY_1914_VAL + 0x000C3F11U, // DDRSS_PHY_1915_VAL + 0x01990000U, // DDRSS_PHY_1916_VAL + 0x000C3F91U, // DDRSS_PHY_1917_VAL + 0x01990000U, // DDRSS_PHY_1918_VAL + 0x3F0DFF11U, // DDRSS_PHY_1919_VAL + 0x00EF0000U, // DDRSS_PHY_1920_VAL + 0x00018011U, // DDRSS_PHY_1921_VAL + 0x0089FF00U, // DDRSS_PHY_1922_VAL + 0x20040005U, // DDRSS_PHY_1923_VAL +}; + +uint16_t DDRSS_ctlRegNum[] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127, + 128, + 129, + 130, + 131, + 132, + 133, + 134, + 135, + 136, + 137, + 138, + 139, + 140, + 141, + 142, + 143, + 144, + 145, + 146, + 147, + 148, + 149, + 150, + 151, + 152, + 153, + 154, + 155, + 156, + 157, + 158, + 159, + 160, + 161, + 162, + 163, + 164, + 165, + 166, + 167, + 168, + 169, + 170, + 171, + 172, + 173, + 174, + 175, + 176, + 177, + 178, + 179, + 180, + 181, + 182, + 183, + 184, + 185, + 186, + 187, + 188, + 189, + 190, + 191, + 192, + 193, + 194, + 195, + 196, + 197, + 198, + 199, + 200, + 201, + 202, + 203, + 204, + 205, + 206, + 207, + 208, + 209, + 210, + 211, + 212, + 213, + 214, + 215, + 216, + 217, + 218, + 219, + 220, + 221, + 222, + 223, + 224, + 225, + 226, + 227, + 228, + 229, + 230, + 231, + 232, + 233, + 234, + 235, + 236, + 237, + 238, + 239, + 240, + 241, + 242, + 243, + 244, + 245, + 246, + 247, + 248, + 249, + 250, + 251, + 252, + 253, + 254, + 255, + 256, + 257, + 258, + 259, + 260, + 261, + 262, + 263, + 264, + 265, + 266, + 267, + 268, + 269, + 270, + 271, + 272, + 273, + 274, + 275, + 276, + 277, + 278, + 279, + 280, + 281, + 282, + 283, + 284, + 285, + 286, + 287, + 288, + 289, + 290, + 291, + 292, + 293, + 294, + 295, + 296, + 297, + 298, + 299, + 300, + 301, + 302, + 303, + 304, + 305, + 306, + 307, + 308, + 309, + 310, + 311, + 312, + 313, + 314, + 315, + 316, + 317, + 318, + 319, + 320, + 321, + 322, + 323, + 324, + 325, + 326, + 327, + 328, + 329, + 330, + 331, + 332, + 333, + 334, + 335, + 336, + 337, + 338, + 339, + 340, + 341, + 342, + 343, + 344, + 345, + 346, + 347, + 348, + 349, + 350, + 351, + 352, + 353, + 354, + 355, + 356, + 357, + 358, + 359, + 360, + 361, + 362, + 363, + 364, + 365, + 366, + 367, + 368, + 369, + 370, + 371, + 372, + 373, + 374, + 375, + 376, + 377, + 378, + 379, + 380, + 381, + 382, + 383, + 384, + 385, + 386, + 387, + 388, + 389, + 390, + 391, + 392, + 393, + 394, + 395, + 396, + 397, + 398, + 399, + 400, + 401, + 402, + 403, + 404, + 405, + 406, + 407, + 408, + 409, + 410, + 411, + 412, + 413, + 414, + 415, + 416, + 417, + 418, + 419, + 420, + 421, + 422, + 423, + 424, + 425, + 426, + 427, + 428, + 429, + 430, + 431, + 432, + 433, + 434, +}; + +uint16_t DDRSS_phyIndepRegNum[] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127, + 128, + 129, + 130, + 131, + 132, + 133, + 134, + 135, + 136, + 137, + 138, + 139, + 140, + 141, + 142, + 143, + 144, + 145, + 146, + 147, + 148, + 149, + 150, + 151, + 152, + 153, + 154, + 155, + 156, + 157, + 158, + 159, + 160, + 161, + 162, + 163, + 164, + 165, + 166, + 167, + 168, + 169, + 170, + 171, + 172, + 173, + 174, + 175, + 176, + 177, + 178, + 179, + 180, + 181, + 182, + 183, + 184, + 185, + 186, + 187, + 188, + 189, + 190, + 191, + 192, + 193, + 194, + 195, + 196, + 197, + 198, + 199, + 200, + 201, + 202, + 203, + 204, + 205, + 206, + 207, + 208, + 209, + 210, + 211, + 212, + 213, + 214, + 215, + 216, + 217, + 218, + 219, + 220, + 221, + 222, + 223, + 224, + 225, + 226, + 227, + 228, + 229, + 230, + 231, + 232, + 233, + 234, + 235, + 236, + 237, + 238, + 239, + 240, + 241, + 242, + 243, + 244, + 245, + 246, + 247, + 248, + 249, + 250, + 251, + 252, + 253, + 254, + 255, + 256, + 257, + 258, + 259, + 260, + 261, + 262, + 263, + 264, + 265, + 266, + 267, + 268, + 269, + 270, + 271, + 272, + 273, + 274, + 275, + 276, + 277, + 278, + 279, + 280, + 281, + 282, + 283, + 284, + 285, + 286, + 287, + 288, + 289, + 290, + 291, + 292, + 293, + 294, + 295, + 296, + 297, + 298, + 299, + 300, + 301, + 302, + 303, + 304, + 305, + 306, + 307, + 308, + 309, + 310, + 311, + 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1826, + 1827, + 1828, + 1829, + 1830, + 1831, + 1832, + 1833, + 1834, + 1835, + 1836, + 1837, + 1838, + 1839, + 1840, + 1841, + 1842, + 1843, + 1844, + 1845, + 1846, + 1847, + 1848, + 1849, + 1850, + 1851, + 1852, + 1853, + 1854, + 1855, + 1856, + 1857, + 1858, + 1859, + 1860, + 1861, + 1862, + 1863, + 1864, + 1865, + 1866, + 1867, + 1868, + 1869, + 1870, + 1871, + 1872, + 1873, + 1874, + 1875, + 1876, + 1877, + 1878, + 1879, + 1880, + 1881, + 1882, + 1883, + 1884, + 1885, + 1886, + 1887, + 1888, + 1889, + 1890, + 1891, + 1892, + 1893, + 1894, + 1895, + 1896, + 1897, + 1898, + 1899, + 1900, + 1901, + 1902, + 1903, + 1904, + 1905, + 1906, + 1907, + 1908, + 1909, + 1910, + 1911, + 1912, + 1913, + 1914, + 1915, + 1916, + 1917, + 1918, + 1919, + 1920, + 1921, + 1922, + 1923, +}; +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/source/files/fastxspi_pattern_am62a_100MHz.bin b/source/files/fastxspi_pattern_am62a_100MHz.bin new file mode 100644 index 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b/source/images/optimized_bootflow_sbl_mpu.png differ diff --git a/source/images/typical_bootflow_spl_mpu.png b/source/images/typical_bootflow_spl_mpu.png new file mode 100644 index 000000000..7beab7d0f Binary files /dev/null and b/source/images/typical_bootflow_spl_mpu.png differ diff --git a/source/linux/How_to_Guides/Target/How_to_boot_quickly.rst b/source/linux/How_to_Guides/Target/How_to_boot_quickly.rst new file mode 100644 index 000000000..20837e8f0 --- /dev/null +++ b/source/linux/How_to_Guides/Target/How_to_boot_quickly.rst @@ -0,0 +1,537 @@ +.. include:: /_replacevars.rst + +Boot Time Optimizations +======================= + +Introduction +------------ +This guide explains how to reduce the time taken to boot from power on to userspace for |__PRODUCT_LINE_NAME__| |__PART_FAMILY_DEVICE_NAMES__| devices. +In the fast-evolving landscape of automotive technology, quick processor boot times are paramount for delivering a seamless, responsive user experience and sets the stage for faster access to critical systems. + +.. note:: + The same workflow is applied to the entire Sitara MPU family, but for each SoC, specific steps will differ and will be highlighted + +The objectives of this document are as follows: + +- Explain various techniques to reduce boot time + +- Highlight the tradeoffs to reach the milestone + +- Measurement and breakdown of default boot time + +- Measurements after optimizations + +Software environment +^^^^^^^^^^^^^^^^^^^^ +This guide uses 9.2 Processor SDK as reference. + +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + - `Processor-SDK-Linux `_ + + - `MCU+ SDK `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - `Processor-SDK-Linux `_ + + - `MCU+ SDK `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - `Processor-SDK-Linux `_ + + - `MCU+ SDK `_ + +Hardware setup and equipment +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +- Development kit used for testing + + .. ifconfig:: CONFIG_part_variant in ('AM62X') + + - AM62 (https://www.ti.com/tool/SK-AM62) + + .. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - AM62A (https://www.ti.com/tool/SK-AM62A-LP) + + .. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - AM62P (https://www.ti.com/tool/SK-AM62P-LP) + +- Micro-USB cables for UART connection + +- Logic Analyzer with at least 4 channels and a sample rate of 10MS/s + +Typical boot flow +^^^^^^^^^^^^^^^^^ +This section details the Out-Of-Box boot sequence: + +.. Image:: /images/typical_bootflow_spl_mpu.png + :align: center + + +**PMIC** or Power Management IC controls the power supply to the SoC. As a unit, it consists of diode controllers, DC-DC conversion and voltage regulation. TI's Fulton PMIC needs about 30ms to supply power while Burton PMIC requires 18ms. + +**BootROM** (Primary Program Loader) is executed first from ROM and performs basic initializations such PLLs and SRAM configuration. It then loads a bootloader image in the boot device specified by the boot switches. This entity takes about 12ms to complete. + +**SPL** (Secondary Program Loader) is the first stage of the bootloader. It consists of code that fits into the SRAM and is run by the Main R5. R5 SPL initializes some peripherals and, most importantly, DDR. Subsequently, it loads TF-A, OPTEE and A53 SPL into DDR and then jumps to TF-A. A53 SPL is an intermediate Linux friendly bootloader stage used to jump to U-boot. + +**TF-A** (Trusted Firmware - Arm) provides a reference trusted code base for the Armv8 architecture. It implements various ARM interface standards. The binary is typically included in the bootloader binary. It starts in the early stages of U-Boot. Without ATF, the kernel cannot setup the services which need to be executed in the Secure World environment + +**OPTEE** (Trusted Execution Environment) is designed as a companion to a non-secure Linux kernel running on Arm; Cortex-A cores using the TrustZone technology. + +**U-boot** proper is the second stage bootloader. It offers a flexible way to load and start the Linux Kernel and provides a minimal set of tools to interact with the board’s hardware via a command line interface. It runs from DRAM, initializing additional hardware devices (network, USB, DSI/CSI, etc.). Then, it loads and prepares the device tree (FDT). The main task handled by the U-Boot is the loading and starting of the kernel image itself. + +**Kernel** runs from DDR and takes over the system completely. + +**Userspace** process is executed by a user in the operating system, rather than being part of the operating system itself. It might also be executed by an init system (e.g. systemd), but it isn't part of the kernel. User space is the area of memory that non-kernel applications run in non-privileged execution mode. + +Optimized bootflow +^^^^^^^^^^^^^^^^^^ +This section describes an overview of the modifications that can be done to achieve shorter boot times. The succeeding sections will detail how to achieve these sequences. + +.. Image:: /images/optimized_bootflow_sbl_mpu.png + :align: center + +Reducing bootloader time +------------------------ + +- Falcon Mode: + + This is a feature that allows us to skip **A53 SPL** and **U-boot proper** and jump to TF-A and then the kernel directly saving ~5s in our boot time. It is implemented differently depending on the bootloader. + +- Choosing the right bootmedia: + + +------------------+--------------+--------------------+----------------------------------+ + | Part | Bootmedia | Theoretical Read | Default offering | + | | | performance (MBps) | | + +------------------+--------------+--------------------+----------+-----------+-----------+ + | | | | AM62 EVM | AM62A EVM | AM62P EVM | + +==================+==============+====================+==========+===========+===========+ + | S28HS512T | OSPI-NOR | 330 | YES | NO | YES | + +------------------+--------------+--------------------+----------+-----------+-----------+ + | W35N01JWTBAG | OSPI-NAND | 50 | NO | YES | NO | + +------------------+--------------+--------------------+----------+-----------+-----------+ + | MTFC16GAPALBH-IT | eMMC (HS200) | 200 | YES | YES | NO | + +------------------+--------------+--------------------+----------+-----------+-----------+ + | MTFC32GAZAQHD-IT | eMMC (HS400) | 400 | NO | NO | YES | + +------------------+--------------+--------------------+----------+-----------+-----------+ + +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + You can track current performance numbers here: `AM62X `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + You can track current performance numbers here: `AM62AX `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + You can track current performance numbers here: `AM62PX `_ + + .. note:: + If links are broken at a later stage, navigate to the Getting started page of MCU+ documentation -> Datasheet -> Performance numbers + +- Flashing binaries: + + .. ifconfig:: CONFIG_part_variant in ('AM62X') + + - `UART flashing tool `_ + + - `U-Boot eMMC flashing tool `_ + + - `U-Boot SPI flashing tool `_ + + .. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - `UART flashing tool `_ + + - `U-Boot eMMC flashing tool `_ + + - `U-Boot SPI flashing tool `_ + + .. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - `UART flashing tool `_ + + - `U-Boot eMMC flashing tool `_ + + - `U-Boot SPI flashing tool `_ + +Secondary Boot Loader (SBL) +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + The following section will be in reference to `MCU+ SDK's SBL examples `_. + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + The following section will be in reference to `MCU+ SDK's SBL examples `_. + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + The following section will be in reference to `MCU+ SDK's SBL examples `_. + +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + - `AM62X Falcon Mode `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - `AM62AX Falcon Mode `_ + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - `AM62PX Falcon Mode `_ + +- Removing unnecessary prints + + The default examples contain a large number of prints that impact boot time and need to be removed. + + - Navigate to the main.c of your example and remove calls to `Bootloader_profileAddCore`, `Bootloader_profileAddProfilePoint`, `Bootloader_profileUpdateAppimageSize`, `Bootloader_profileUpdateMediaAndClk` and `Bootloader_profilePrintProfileLog`. + + - Navigate to /source/drivers/device_manager/sciclient_direct/sciclient_direct_wrapper.c and remove the `DebugP_log` from `Sciclient_getVersionCheck` function. + + .. note:: + If an RTOS example is being used, remove prints in additional files in `/examples/drivers/boot/common/` + +- Skipping OSPI PHY tuning (in case of OSPI bootmedia) + + PHY calibration allows the flash to function at maximum performance and this consumes some time that is dependent on the current algorithm implementation. By default, only stage 2 examples will skip tuning. + + To validate this, do not remove the log prints from the previous subsection and observe the `SBL Board_driversOpen` parameter. Currently, the tuning algorithm takes 22ms to complete. If skipping is successful, it should drop down to ~150us. + + Open the relevant example's syscfg by navigating into `/examples/drivers/boot/sbl_ospi_linux_multistage/sbl_ospi_linux_stage1///ti-arm-clang/` and running :literal:`make syscfg-gui`. Navigate to the `OSPI` section and enable **OSPI skip Tuning option**. Ensure that **Enable PHY** is checked as well. + + .. Image:: /images/SBL_enable_ospi_phy_skip.png + :align: center + +- Enabling DMA in the bootloader + + Open the relevant example's syscfg and navigate to the `Bootloader` section and click on **Enable DMA** if not enabled by default. + + .. Image:: /images/SBL_enable_dma.png + :align: center + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - Enable High Capacity(HC) channel DMA + + This upgrades the DMA channel's FIFO depth from 128 to 192 and has been shown to have more than 200% increase in DMA transfer performance. In AM62P, the first four channels are high capacity. By default, these channels have been assigned to the A53 core by order of core priority which A53 has the first 18 channels, DM R5 has the next 6 and lastly, MCU R5 has 2. + + - :download:`This patch ` removes the DMA allocation of A53 and MCU cores to showcase the use of High capacity channels + + .. note:: + It is not possible to assign the first 2 channels to DM R5, the next 2 to A53, next 4 again to DM R5 and so on. + + - Rebuild the boardcfg : `BOARCFG_GEN `_ + + - Flash the binaries + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - FastXSPI + + This is a special OSPI-NOR boot mode where ROM tunes OSPI when provided with the right parameters. If successful, OSPI PHY tuning need not be done by the bootloader at SBL-stage1 otherwise it will switch to the regular OSPI-NOR mode where tuning has to be done by a subsequent stage. + + Flash the relevant binary at :literal:`0x3fc0000`: + + .. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - :download:`OSPI-NOR @100MHz ` + + - :download:`OSPI-NOR @133MHz ` + + - :download:`OSPI-NOR @166MHz ` + + .. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - :download:`OSPI-NOR @100MHz ` + + - :download:`OSPI-NOR @133MHz ` + + - :download:`OSPI-NOR @166MHz ` + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + - Use DDR in single rank configuration + + The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM. Dual rank gives us access to a bigger memory bank but consumes twice the tuning time. By default, DDR is in dual rank configuration and takes ~35ms that is visible in `System_init` in the SBL logs. + + Navigate to the DDR section in SBL-stage1 syscfg and update it to the single rank file given below to reduce the time to ~20ms. + + :download:`ddr_1600_singlerank_am62p.h ` + + .. Image:: /images/SBL_singlerank_ddr.png + :align: center + +Reducing Linux kernel boot time +------------------------------- + +- Adding :literal:`quiet` + + - To save 8+ seconds, add "quiet" argument in the Kernel "bootargs". It suppresses most messages during the Linux start-up sequence. To access the logs after login, you can run :code:`dmesg` for the logs to be printed. By default, quiet is at a loglevel of 4 and should be adequate to suppress the majority of logs but if finer control is required :litera:`quiet` can be replaced with :literal:`loglevel=x` where x can be 1-14. + + - The kernel looks for bootargs in 3 places: U-Boot environment variable, the device tree and the kernel config. You can add the following in any of the 3 locations. + + U-Boot console: + + .. code-block:: console + + U-Boot=> setenv bootargs 'console=ttyS2,115200n8 fsck.mode=skip sysrq_always_enabled quiet' + + Device Tree: + + .. code-block:: dts + + chosen { + ... + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 quiet"; + ... + }; + + Kernel config: + + .. code-block:: kconfig + + CONFIG_CMDLINE="console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 quiet" + +- Using a smaller kernel system + + - By default, the kernel image contains a lot of drivers and filesystems to enable the functionality supported for the board but are not necessary for early boot. Trim kernel capabilities by using + + - `ti_arm64_prune.config` - removes irrelevant platform drivers + - `ti_early_display.config` - converts the majority of functionality into loadable modules + + Usage: + + .. code-block:: console + + kernel$ make ARCH=arm64 CROSS_COMPILE=/aarch64-none-linux-gnu- defconfig ti_arm64_prune.config ti_early_display.config + + *Note: You can access /kernel/configs/ti_early_display.config and see the breakdown of how much time is saved by disabling each module and take a call on whether the functionality is required and its effect on boot time* + +- Disabling nodes in DT + + Unnecessary nodes can be disabled by adding :literal:`status = "disabled"` to the nodes. While this will not directly affect boot time, the minimal kernel will not throw probe errors during boot. + +Reducing userspace boot time +---------------------------- + +It is recommended to use a tiny intermediate filesystem that can be used to run applications early with minimal configuration and then mount into a filesystem with full functionality. For this purpose, the installer packages a `tisdk-tiny-initramfs-am62xx-evm.cpio` under filesystem/ that can be used as an initramfs. + +In order to package the filesystem as initramfs into the kernel, follow these steps: + +1. Extract the cpio archive to a preferred location via GUI or + + .. code-block:: console + + $ mkdir output + $ cd output + $ cpio -idv < tisdk-tiny-initramfs-am62xx-evm.cpio + + +2. Edit the kernel config: + + .config: + + .. code-block:: kconfig + + CONFIG_INITRAMFS_SOURCE="/path/to/filesystem" + + or using :literal:`menuconfig`: + + .. code-block:: kconfig + + kernel$ make ARCH=arm64 CROSS_COMPILE=/aarch64-none-linux-gnu- menuconfig + + General setup -> + Initial RAM filesystem and RAM disk (initramfs/initrd) support -> + Initramfs source file(s) + /path/to/filesystem + +3. Rebuild the kernel + + .. code-block:: console + + kernel$ make ARCH=arm64 CROSS_COMPILE=/aarch64-none-linux-gnu- Image -j64 + +The time taken to boot filesystem is measured from Process ID 1(PID1) to login prompt which is 1.98s with the initramfs filesystem. In order to further drop this time, you can: + +.. note:: + Please ensure that you do not mistakenly affect the host computer while making the below changes + +- Remove startup scripts from the tiny filesystem + + .. code-block:: console + + host$ rm /etc/rc5.d/* + host$ cd /etc/rcS.d + host$ rm S02banner.sh S04udev S05checkroot.sh S06modutils.sh S07bootlogd S29read-only-rootfs-hook.sh S36bootmisc.sh S37populate-volatile.sh S38dmesg.sh S38urandom + + This shaves off 1.536s from filesystem boot time. udev alone takes up 1.152s. + +- Remove package manager, console logo and add /dev/null in the filesystem + + .. code-block:: console + + host$ rm /usr/lib/opkg + host$ rm /etc/issue + host$ cd /dev + host$ mknod -m 0600 null c 1 3 + + This removes 52ms from the boot up time. + +Measurements +------------ + +The following section displays the time taken by each stage to start and end. Four profile points were used: + + - MCU_PORz (White) - MCU Power-On-Reset + + - SBL_start (Brown) - GPIO is set to LOW as soon as SBL stage 1 is started (Before System_init) + + - SBL_end (Red) - GPIO is set to LOW as soon as SBL stage 2 completes (After App_driversClose) + + - Kernel_end (Gold) - GPIO is set to HIGH when kernel is about to jump to ramdisk (init/main.c: kernel_init) + +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + .. Image:: /images/am62x_ospi_boot_analyser.png + :align: center + + ROM time : SBL_start - MCU_PORz = 33ms + + SBL time : SBL_end - SBL_start = 240ms + + TF-A + OPTEE + Kernel time: Kernel_end - SBL_end = 415ms + + .. code-block:: console + + [2024-03-29 11:52:40.318] NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty + [2024-03-29 11:52:40.318] NOTICE: BL31: Built : 16:09:05, Feb 9 2024 + [2024-03-29 11:52:41.098] + [2024-03-29 11:52:41.098] am62xx-evm login: + + To calculate userspace, we use console logs to take timestamps from TF-A to login prompt and subtract kernel time = + + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + .. Image:: /images/am62ax_ospi_boot_analyser.png + :align: center + + ROM time : SBL_start - MCU_PORz = 48ms + + SBL time til Linux CPU is started: SBL_end - SBL_start = 624ms + + SBL C7X load + DriversClose + TF-A + OPTEE + Kernel time: Kernel_end - SBL_end = 679ms (~450ms for Kernel) + + .. code-block:: console + + [2024-03-29 13:02:19.196] NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty + [2024-03-29 13:02:19.196] NOTICE: BL31: Built : 16:09:05, Feb 9 2024 + [2024-03-29 13:02:19.991] + [2024-03-29 13:02:19.991] am62xx-evm login: + + To calculate userspace, we use console logs to take timestamps from TF-A to login prompt and subtract kernel time = 345ms + +.. ifconfig:: CONFIG_part_variant in ('AM62PX') + + .. Image:: /images/am62px_ospi_boot_analyser.png + :align: center + + ROM time : SBL_start - MCU_PORz = 30.79ms + + SBL time : SBL_end - SBL_start = 186.42ms + + TF-A + OPTEE + Kernel time: Kernel_end - SBL_end = 497.67ms + + .. code-block:: console + + [2024-03-29 14:31:25.265] NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty + [2024-03-29 14:31:25.265] NOTICE: BL31: Built : 16:09:05, Feb 9 2024 + [2024-03-29 14:31:26.117] + [2024-03-29 14:31:26.117] am62xx-evm login: + + To calculate userspace, we use console logs to take timestamps from TF-A to login prompt and subtract kernel time = 355ms + +Additional notes +---------------- + +.. ifconfig:: CONFIG_part_variant in ('AM62X', 'AM62PX') + + .. note:: + Ensure that you are not affecting your host computer when making the changes deailed below + + - This statically compiled :download:`modetest ` can be added to the filesystem to test out display at boot on an OLDI panel. + + - `init` is a symbolic link to /sbin/init. Remove the file sbin/init + + .. code-block:: console + + rm /sbin/init + + - Create a new sbin/init and add the following. + + .. code-block:: sh + + #!/bin/sh + + mount -t proc none /proc + mount -t sysfs none /sys + mount -t devtmpfs dev /dev + + # Run modetest in the background + # 40 - connector ID + # 38 - CRTC ID + # 1920x1200 - resolution of panel + modetest -M tidss -s 40@38:1920x1200 & + + exec /sbin/init.sysvinit $* + + You can get the connector ID and CRTC ID of your OLDI panel by running :literal:`kmsprint` or :literal:`modetest -M tidss` + + - Make it executable + + .. code-block:: console + + chmod +x /sbin/init + + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - While AM62A ships with OSPI-NAND, it can be replaced with the OSPI-NOR flash with ease. It is not recommended to resolder used flashes onto a board. NAND flash support needs to be replaced with NOR flash support + + - SPL: + + Apply this :download:`patch ` and rebuild `U-Boot `_. + + - SBL: + + Update the Flash type in Flash section in syscfg to reflect NOR. Save and build SBL. + +Troubleshooting +--------------- + +- If the following logs are noticed and kernel does not come up, it suggests that TF-A is not receiving data from DM which probably hasn't had enough time to run completely + + .. code-block:: console + + ERROR: Timeout waiting for thread SP_RESPONSE to fill + ERROR: Thread SP_RESPONSE verification failed (-60) + ERROR: Message receive failed (-60) + ERROR: Failed to get response (-60) + ERROR: Transfer send failed (-60) + +Known issues +------------ + +.. ifconfig:: CONFIG_part_variant in ('AM62AX') + + - Due to the implementation of OSPI-NAND software layer in MCU+ SDK, it has been observed that the read performance drops when tuning is skipped. This fix will be incoporated for 10.0 SDK release. + +.. ifconfig:: CONFIG_part_variant in ('AM62X') + + - OSPI stage 2 will not skip tuning by default on AM62X \ No newline at end of file diff --git a/source/linux/How_to_Guides_Developer_Notes.rst b/source/linux/How_to_Guides_Developer_Notes.rst index 99e75ddcb..cc9c18acb 100644 --- a/source/linux/How_to_Guides_Developer_Notes.rst +++ b/source/linux/How_to_Guides_Developer_Notes.rst @@ -33,6 +33,7 @@ Developer Notes How_to_Guides/Target/How_to_Use_K3Conf_Tool How_to_Guides/Target/How_to_Tune_Real_Time_Linux How_to_Guides/Target/How_to_enable_display_sharing_between_remotecore_and_Linux + How_to_Guides/Target/How_to_boot_quickly How_to_Guides/Target/Runtime_debug_unlock_on_secure_device How_to_Guides/FAQ/How_to_Verify_Ipc_Linux_R5 How_to_Guides/FAQ/How_to_Configure_MSMC_memory