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Right now we have the tests SRAM and SRAM_MULTI, but they are block-level tests. We need a system-level test to show that we can read out some data from the ADC in the right order. We implemented part of this for ButterPHY in the test LOOPBACK_JTAG, but the test was never passing, so it needs to be updated for DragonPHY and debugged.
The text was updated successfully, but these errors were encountered:
It looks like this was addressed in cpu_system_tests/loopback_sram, but there is still some leftover code from the old approach. I think we should revisit this to make sure we're checking what we think we're checking.
Right now we have the tests SRAM and SRAM_MULTI, but they are block-level tests. We need a system-level test to show that we can read out some data from the ADC in the right order. We implemented part of this for ButterPHY in the test
LOOPBACK_JTAG
, but the test was never passing, so it needs to be updated for DragonPHY and debugged.The text was updated successfully, but these errors were encountered: