diff --git a/_pages/group-photos.md b/_pages/group-photos.md index 7c8ec60..99110b9 100644 --- a/_pages/group-photos.md +++ b/_pages/group-photos.md @@ -7,6 +7,10 @@ hide_hero: true + + + + diff --git a/assets/images/group_photo_apr_14_2024.jpg b/assets/images/group_photo_apr_14_2024.jpg new file mode 100644 index 0000000..25f1acb Binary files /dev/null and b/assets/images/group_photo_apr_14_2024.jpg differ diff --git a/assets/images/jeffrey.jpg b/assets/images/jeffrey.jpg index 71e897f..a44c415 100644 Binary files a/assets/images/jeffrey.jpg and b/assets/images/jeffrey.jpg differ diff --git a/assets/images/yuchen.jpg b/assets/images/yuchen.jpg index de027b0..67f1c0f 100644 Binary files a/assets/images/yuchen.jpg and b/assets/images/yuchen.jpg differ diff --git a/index.md b/index.md index 0045205..2d7b43d 100644 --- a/index.md +++ b/index.md @@ -79,6 +79,24 @@ Stanford accelerate group works on creating high performance and energy-efficien Research: I am generally interested in designing hardware accelerators. Most of my previous works were related to computational photography algorithms such as digital refocusing. Currently, I am focusing on analyzing and designing architecture of CGRAs to create high-performance, energy-efficient, and reconfigurable computing platforms. + + + + + + + +
Group photo from INDO Restaurant & Lounge on April 14, 2024. From left to right: Sai Gautham Ravipati, Po-Han Chen, Yuchen Mei, Kai Bartolone, Suresh Nambi, Jeffrey Yu, Zhouhua Xie, Kathleen Feng, Kartik Prabhu, Kalhan Koul, Michael Oduoza, Bo Wun Cheng, Jackson Melchert, and Priyanka Raina.
Group photo from Alpine Inn on October 8, 2023. From left to right: Jackson Melchert, Kalhan Koul, Kathleen Feng, Kai Bartolone, Bo Wun Cheng, Jeffery Yu, Po-Han Chen, Kartik Prabhu, Michael Oduoza, Yuchen Mei, Priyanka Raina, and Calib Terrill.
+ Jeffrey Yu
+ Email: jeffreyy AT stanford DOT edu
+ About: Jeffrey is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. degree in Computer Engineering from UC San Diego in 2021.
+ Research: His research focuses on edge device training, efficient ML algorithms, and deep neural network quantization. In particular, he is working on low-precision multi-modal AI and building an hardware accelerator for mix-reality workloads.
+
+ Yuchen Mei
+ Email: yuchenm AT stanford DOT edu, Webpage
+ About: Yuchen Mei is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. degree in Electronic Information Science and Technology from Nanjing University (China) in 2021 and M.S. in Electrical Engineering from Stanford University in 2023.
+ Research: His current research focuses on application mapping and optimization for domain-specific accelerators, with a particular interest in auto-scheduling for compute-intensive applications, such as image processing and deep learning. Before joining Stanford, he worked on 3D-CNN optimization and hardware security. +
@@ -103,24 +121,6 @@ Stanford accelerate group works on creating high performance and energy-efficien ## Masters Students - - - - - - - -
- Jeffrey Yu
- Email: jeffreyy AT stanford DOT edu
- About: Jeffrey is an EE Master student at Stanford University working in Prof. Priyanka Raina’s research group. He received his B.S. degree in Computer Engineering from UC San Diego in 2021.
- Research: My research focuses on efficient DNN inference and training using quantization and new number systems. I also work on the mapping DNN operations to the accelerator and verification of RTL and SoC.
-
- Yuchen Mei
- Email: yuchenm AT stanford DOT edu, Webpage
- About: Yuchen Mei is an EE M.S. student at Stanford University supervised by Prof. Priyanka Raina. He received a B.S. degree in Electronic Information Science and Technology from Nanjing University (China) in 2021. Before joining Stanford, he was a research assistant at Nanjing University where he worked on 3D-CNN optimization and hardware security.
- Research: Currently, my research focuses on how to improve the frequency of image processing and machine learning applications running on CGRAs. I am involved in the development of software pipelining techniques and the design space exploration of the CGRA array and interconnection system. I am generally interested in chip design, domain-specific accelerators, and design automation. -