From 05ed94c61b7042b7e5e5f8798a9b9e85f6d4d8c2 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 21 Jun 2024 10:10:27 +0200
Subject: [PATCH] fix #16 add --pyhsical-width xyz

---
 src/main/scala/vexiiriscv/Param.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
index c9f447bd..98845f5e 100644
--- a/src/main/scala/vexiiriscv/Param.scala
+++ b/src/main/scala/vexiiriscv/Param.scala
@@ -62,6 +62,7 @@ class ParamSimple(){
   var withDispatcherBuffer = false
   var hartCount = 1
   var withMmu = false
+  var physicalWidth = 32
   var resetVector = 0x80000000l
   var decoders = 1
   var lanes = 1
@@ -323,6 +324,7 @@ class ParamSimple(){
     opt[Unit]("debug-triggers-lsu") action { (v, c) => privParam.debugTriggersLsu = true }
     opt[Unit]("debug-jtag-tap") action { (v, c) => embeddedJtagTap = true }
     opt[Unit]("with-boot-mem-init") action { (v, c) => bootMemClear = true }
+    opt[Int]("physical-width") action {(v, c) => physicalWidth = v}
   }
 
   def plugins(hartId : Int = 0) = pluginsArea(hartId).plugins
@@ -334,10 +336,10 @@ class ParamSimple(){
 
     plugins += new riscv.RiscvPlugin(xlen, hartCount, rvf = withRvf, rvd = withRvd, rvc = withRvc)
     withMmu match {
-      case false => plugins += new memory.StaticTranslationPlugin(32)
+      case false => plugins += new memory.StaticTranslationPlugin(physicalWidth)
       case true => plugins += new memory.MmuPlugin(
         spec = if (xlen == 32) MmuSpec.sv32 else MmuSpec.sv39,
-        physicalWidth = 32
+        physicalWidth = physicalWidth
       )
     }