diff --git a/.github/workflows/push-doc.yml b/.github/workflows/push-doc.yml
index 10829b03818..d6096e8bc7d 100644
--- a/.github/workflows/push-doc.yml
+++ b/.github/workflows/push-doc.yml
@@ -18,6 +18,8 @@ jobs:
       sphinx_html_baseurl: 'https://spinalhdl.github.io/SpinalDoc-RTD/master/'
       sphinx_github_url: 'https://github.com/SpinalHDL/SpinalDoc-RTD'
       sphinx_extra_version: 'master'
+
+    if: github.event.head_commit.author.email != 'action.github.com'
     steps:
     - uses: actions/checkout@v3
       with:
@@ -36,6 +38,8 @@ jobs:
         file: pdf.Dockerfile
     - name: Check links
       run: docker run --rm -u $(id -u $USER):$(id -g $USER) -v $PWD:/docs -e sphinx_html_baseurl -e sphinx_github_url spinaldoc-pdf make linkcheck
+    - name: Build zh-cn translated doc
+      run: docker run --rm -u $(id -u $USER):$(id -g $USER) -v $PWD:/docs -e sphinx_html_baseurl -e sphinx_github_url spinaldoc-pdf sphinx-build -b html -D language=zh_CN ./source/ docs/html/zh_CN
     - name: Build multiversioned doc
       run: docker run --rm -u $(id -u $USER):$(id -g $USER) -v $PWD:/docs -e sphinx_html_baseurl -e sphinx_github_url spinaldoc-pdf sphinx-multiversion source docs/html
     - name: Add .nojekill
diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml
index bb113fa962e..28aa9e1ae7a 100644
--- a/.github/workflows/test-build.yml
+++ b/.github/workflows/test-build.yml
@@ -27,3 +27,7 @@ jobs:
       run: |
         source bin/setup_env.sh
         make html
+    - name: "Test zh-CN doc building"
+      run: |
+        source bin/setup_env.sh
+        make -e SPHINXOPTS="-D language='zh_CN'" html
diff --git a/.github/workflows/update-pot.yml b/.github/workflows/update-pot.yml
new file mode 100644
index 00000000000..17cec535480
--- /dev/null
+++ b/.github/workflows/update-pot.yml
@@ -0,0 +1,50 @@
+name: "Update translation template pot files."
+
+on:
+  push:
+    branches:
+      - master
+      - dev
+  schedule:
+    # * is a special character in YAML
+    # setup monthly background build
+    - cron: '45 4 20 * *'
+    # gh-pages have a lifetime ?  90 days ? so we do this once a month to refresh
+
+jobs:
+  pots:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v3
+      with:
+        fetch-depth: 0
+    - name: "setup python"
+      uses: actions/setup-python@v4
+      with:
+        python-version: 3.9
+    - name: "install dependencies"
+      run: |
+        apt-get update -y && apt-get install -y git gettext sphinx-intl
+        pip install -r requirements.txt
+    - uses: ammaraskar/sphinx-problem-matcher@master
+    - name: "update pot"
+      run: |
+        source bin/setup_env.sh
+        make gettext -e BUILDDIR=source/locale/
+    - name: "update po files"
+      run: |
+        source bin/setup_env.sh
+        sphinx-intl update -p source/locale/gettext/ -l zh_CN
+    - name: Commit changes
+      uses: stefanzweifel/git-auto-commit-action@v5
+      with: 
+        commit_message: update .pot files
+        commit_user_email: action@github.com
+        commit_user_name: GiHub Action Bot
+        commit_author: GiHub Action Bot <action@github.com>
+        file_pattern: 'source/locale/*.pot source/locale/*.po'
+    - name: Push changes
+      uses: ad-m/github-push-action@master
+      with:
+        github_token: ${{ secrets.GITHUB_TOKEN }}
+        branch: ${{ github.ref }}
diff --git a/.gitignore b/.gitignore
index 50e0bc75092..032f1f1ccf5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,9 +8,11 @@ docs/*
 *.bin
 .cache/
 .venv*/
+*.mo
 
 # artifacts from compiling the examples
 examples/project
 .metals
 .scala-build
-.bsp
\ No newline at end of file
+.bsp
+.sphinx_matcher.json
\ No newline at end of file
diff --git a/README.rst b/README.rst
index 72d6fb3f98c..fcc1b01f6f9 100644
--- a/README.rst
+++ b/README.rst
@@ -51,6 +51,12 @@ and then you can use ``make`` the usual way
 
 all the outputs will be in docs folder (for html: docs/html)
 
+The Chinese version can be built by
+
+.. code:: shell
+
+   make -e SPHINXOPTS="-D language='zh_CN'" html # for html in Chinese
+
 
 With Docker
 -----------
diff --git a/requirements.txt b/requirements.txt
index 6e281fda0d4..3f7b2ce5688 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -3,3 +3,4 @@ sphinx-rtd-theme==1.2.1
 sphinxcontrib-wavedrom==3.0.4
 sphinx-multiversion @ git+https://github.com/samuel-emrys/sphinx-multiversion.git@cd723351f687c98d32834226ae7b3ec9e63bcba5
 sphinx-copybutton==0.5.2
+sphinx-intl==2.1.0
diff --git a/source/_templates/versions.html b/source/_templates/versions.html
index 691699f807c..f2fd2e86fac 100644
--- a/source/_templates/versions.html
+++ b/source/_templates/versions.html
@@ -12,9 +12,9 @@
        <dd class="rtd-current-item">
          <a href="#">en</a>
        </dd>
-       <dd>
-         <a href="https://thucgra.github.io/SpinalHDL_Chinese_Doc/">zh_CN</a>
-      </dd>
+       {% for the_language, url in languages %}
+       <dd><a href="{{ url }}/index.html">{{ the_language }}</a></dd>
+       {% endfor %}
     </dl>
     {%- endif %}
     {%- if versions.tags %}
diff --git a/source/conf.py b/source/conf.py
index dd1aaf76255..1c1399c1445 100644
--- a/source/conf.py
+++ b/source/conf.py
@@ -223,6 +223,8 @@
     'github_version': os.getenv('GITHUB_REF_NAME', 'master'), # Version
     'conf_py_path': '/source/', # Path in the checkout to the docs root
 
+    'current_language': 'en',
+    'languages': [["zh_CN", "/SpinalDoc-RTD/zh_CN"]],
     'sphinx_latest_version': os.getenv('sphinx_latest_version', None)
 }
 
@@ -366,3 +368,5 @@ def html_context_add_git(attr):
 
 
 html_context = html_context_add_git(html_context)
+locale_dirs = ['locale/']   # path is example but recommended.
+gettext_compact = False     # optional.
diff --git a/source/locale/gettext/SpinalHDL/Data types/AFix.pot b/source/locale/gettext/SpinalHDL/Data types/AFix.pot
new file mode 100644
index 00000000000..111090ba7bd
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/AFix.pot	
@@ -0,0 +1,193 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/AFix.rst:5
+msgid "AFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:8
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:10
+msgid "Auto-ranging Fixed-Point, ``AFix``, is a fixed-point class which tracks the representable range of values while preforming fixed-point operations."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:12
+msgid "**Warning: Much of this code is still under development. API and function calls may change.**"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:14
+msgid "User feedback is appreciated!"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:18
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:20
+msgid "AFix can be created using bit sizes or exponents:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:36
+msgid "These will have representable ranges for all bits."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:38
+msgid "For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:40
+msgid "``AFix.U(12 bits)`` will have a range of 0 to 4095."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:42
+msgid "``AFix.SQ(8 bits, 4 bits)`` will have a range of -4096 (-256) to 4095 (255.9375)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:44
+msgid "``AFix.U(8 exp, 4 exp)`` will have a range of 0 to 256"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:47
+msgid "Custom range ``AFix`` values can be created be directly instantiating the class."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:58
+msgid "The ``maxValue`` and ``minValue`` stores what backing integer values are representable. These values represent the true fixed-point value after multiplying by ``2^exp``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:61
+msgid "``AFix.U(2 exp, -1 exp)`` can represent: ``0, 0.5, 1.0, 1.5, 2, 2.5, 3, 3.5``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:64
+msgid "``AFix.S(2 exp, -2 exp)`` can represent: ``-2.0, -1.75, -1.5, -1.25, -1, -0.75, -0.5, -0.25, 0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:67
+msgid "Exponent values greater 0 are allowed and represent values which are larger than 1."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:69
+msgid "``AFix.S(2 exp, 1 exp)`` can represent: ``-4, 2, 0, 2``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:72
+msgid "``AFix(8, 16, 2 exp)`` can represent: ``32, 36, 40, 44, 48, 52, 56, 60, 64``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:75
+msgid "Note: ``AFix`` will use 5 bits to save this type as that can store ``16``, its ``maxValue``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:79
+msgid "Mathematical Operations"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:81
+msgid "``AFix`` supports Addition (``+``), Subtraction (``-``), and Multiplication (``*``) at the hardware level. Division (``\\``) and Modulo (``%``) operators are provided but are not recommended for hardware elaboration."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:85
+msgid "Operations are preformed as if the ``AFix`` value is a regular ``Int`` number. Signed and unsigned numbers are interoperable. There are no type differences between signed or unsigned values."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:103
+msgid "``AFix`` supports operations without without range expansion. It does this by selecting the aligned maximum and minimum ranges from each of the inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:106
+msgid "``+|`` Add without expansion. ``-|`` Subtract without expansion."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:111
+msgid "Inequality Operations"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:113
+msgid "``AFix`` supports standard inequality operations."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:124
+msgid "Warning: Operations which are out of range at compile time will be optimized out!"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:128
+msgid "Bitshifting"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:130
+msgid "``AFix`` supports decimal and bit shifting"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:132
+msgid "``<<`` Shifts the decimal to the left. Adds to the exponent. ``>>`` Shifts the decimal to the right. Subtracts from the exponent. ``<<|`` Shifts the bits to the left. Adds fractional zeros. ``>>|`` Shifts the bits to the right. Removes fractional bits."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:139
+msgid "Saturation and Rounding"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:141
+msgid "``AFix`` implements saturation and all common rounding methods."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:143
+msgid "Saturation works by saturating the backing value range of an ``AFix`` value. There are multiple helper functions which consider the exponent."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:153
+msgid "``AFix`` rounding modes:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:170
+msgid "A mathematical example of these rounding modes is better explained here: `Rounding - Wikipedia <https://en.wikipedia.org/wiki/Rounding>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:172
+msgid "All of these modes will result in an ``AFix`` value with 0 exponent. If rounding to a different exponent is required consider shifting or use an assignment with the ``truncated`` tag."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:177
+msgid "Assignment"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:179
+msgid "``AFix`` will automatically check and expand range and precision during assignment. By default, it is an error to assign an ``AFix`` value to another ``AFix`` value with smaller range or precision."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:182
+msgid "The ``.truncated`` function is used to control how assignments to smaller types."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:192
+msgid "``RoundType``:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:207
+msgid "The ``saturation`` flag will add logic to saturate to the assigned datatype range."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:209
+msgid "The ``overflow`` flag will allow assignment directly after rounding without range checking."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/AFix.rst:211
+msgid "Rounding is always required when assigning a value with more precision to one with lower precision."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/Fix.pot b/source/locale/gettext/SpinalHDL/Data types/Fix.pot
new file mode 100644
index 00000000000..ebeeaf1a28b
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/Fix.pot	
@@ -0,0 +1,521 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/Fix.rst:2
+msgid "SpinalHDL fixed-point support is only partially used/tested, if you find any bugs with it, or you think that some functionality is missing, please create a `Github issue <https://github.com/SpinalHDL/SpinalHDL/issues>`_. Also, please do not use undocumented features in your code."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:7
+msgid "UFix/SFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:10
+#: ../../SpinalHDL/Data types/Fix.rst:169
+#: ../../SpinalHDL/Data types/Fix.rst:208
+#: ../../SpinalHDL/Data types/Fix.rst:237
+#: ../../SpinalHDL/Data types/Fix.rst:273
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:12
+msgid "The ``UFix`` and ``SFix`` types correspond to a vector of bits that can be used for fixed-point arithmetic."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:15
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:17
+msgid "The syntax to declare a fixed-point number is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:20
+msgid "Unsigned Fixed-Point"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:26
+#: ../../SpinalHDL/Data types/Fix.rst:49
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:27
+#: ../../SpinalHDL/Data types/Fix.rst:50
+msgid "bit width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:28
+#: ../../SpinalHDL/Data types/Fix.rst:51
+msgid "resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:29
+#: ../../SpinalHDL/Data types/Fix.rst:52
+msgid "max"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:30
+#: ../../SpinalHDL/Data types/Fix.rst:53
+msgid "min"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:31
+msgid "UFix(peak: ExpNumber, resolution: ExpNumber)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:32
+msgid "peak-resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:33
+#: ../../SpinalHDL/Data types/Fix.rst:56
+msgid "2^resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:34
+#: ../../SpinalHDL/Data types/Fix.rst:57
+msgid "2^peak-2^resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:35
+#: ../../SpinalHDL/Data types/Fix.rst:40
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:36
+msgid "UFix(peak: ExpNumber, width: BitCount)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:37
+#: ../../SpinalHDL/Data types/Fix.rst:60
+msgid "width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:38
+msgid "2^(peak-width)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:39
+msgid "2^peak-2^(peak-width)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:43
+msgid "Signed Fixed-Point"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:54
+msgid "SFix(peak: ExpNumber, resolution: ExpNumber)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:55
+msgid "peak-resolution+1"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:58
+#: ../../SpinalHDL/Data types/Fix.rst:63
+msgid "-(2^peak)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:59
+msgid "SFix(peak: ExpNumber, width: BitCount)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:61
+msgid "2^(peak-width-1)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:62
+msgid "2^peak-2^(peak-width-1)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:66
+msgid "Format"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:68
+msgid "The chosen format follows the usual way of defining fixed-point number format using Q notation. More information can be found on the `Wikipedia page about the Q number format <https://en.wikipedia.org/wiki/Q_(number_format)>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:70
+msgid "For example Q8.2 will mean a fixed-point number of 8+2 bits, where 8 bits are used for the natural part and 2 bits for the fractional part. If the fixed-point number is signed, one more bit is used for the sign."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:73
+msgid "The resolution is defined as being the smallest power of two that can be represented in this number."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:76
+msgid "To make representing power-of-two numbers less error prone, there is a numeric type in ``spinal.core`` called ``ExpNumber``, which is used for the fixed-point type constructors. A convenience wrapper exists for this type, in the form of the ``exp`` function (used in the code samples on this page)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:80
+msgid "Examples"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:99
+msgid "Assignments"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:102
+msgid "Valid Assignments"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:104
+msgid "An assignment to a fixed-point value is valid when there is no bit loss. Any bit loss will result in an error."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:106
+msgid "If the source fixed-point value is too big, the ``truncated`` function will allow you to resize the source number to match the destination size."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:109
+#: ../../SpinalHDL/Data types/Fix.rst:134
+#: ../../SpinalHDL/Data types/Fix.rst:148
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:129
+msgid "From a Scala constant"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:131
+msgid "Scala ``BigInt`` or ``Double`` types can be used as constants when assigning to ``UFix`` or ``SFix`` signals."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:143
+msgid "Raw value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:145
+msgid "The integer representation of the fixed-point number can be read or written by using the ``raw`` property."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:157
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:159
+msgid "The following operators are available for the ``UFix`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:162
+msgid "Arithmetic"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:168
+#: ../../SpinalHDL/Data types/Fix.rst:207
+#: ../../SpinalHDL/Data types/Fix.rst:236
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:170
+msgid "Returned resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:171
+msgid "Returned amplitude"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:172
+msgid "x + y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:173
+msgid "Addition"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:174
+#: ../../SpinalHDL/Data types/Fix.rst:178
+msgid "Min(x.resolution, y.resolution)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:175
+#: ../../SpinalHDL/Data types/Fix.rst:179
+msgid "Max(x.amplitude, y.amplitude)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:176
+msgid "x - y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:177
+msgid "Subtraction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:180
+msgid "x * y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:181
+msgid "Multiplication"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:182
+msgid "x.resolution * y.resolution)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:183
+#: ../../SpinalHDL/Data types/Fix.rst:281
+msgid "x.amplitude * y.amplitude"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:184
+msgid "x >> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:185
+#: ../../SpinalHDL/Data types/Fix.rst:193
+msgid "Arithmetic shift right, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:186
+#: ../../SpinalHDL/Data types/Fix.rst:194
+msgid "x.amplitude >> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:187
+msgid "x.resolution >> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:188
+msgid "x << y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:189
+#: ../../SpinalHDL/Data types/Fix.rst:197
+msgid "Arithmetic shift left, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:190
+#: ../../SpinalHDL/Data types/Fix.rst:198
+msgid "x.amplitude << y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:191
+msgid "x.resolution << y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:192
+msgid "x >>| y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:195
+#: ../../SpinalHDL/Data types/Fix.rst:199
+#: ../../SpinalHDL/Data types/Fix.rst:280
+msgid "x.resolution"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:196
+msgid "x <<| y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:202
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:209
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:210
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:211
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:212
+#: ../../SpinalHDL/Data types/Fix.rst:215
+#: ../../SpinalHDL/Data types/Fix.rst:218
+#: ../../SpinalHDL/Data types/Fix.rst:221
+#: ../../SpinalHDL/Data types/Fix.rst:224
+#: ../../SpinalHDL/Data types/Fix.rst:227
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:213
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:214
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:216
+msgid "x > y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:217
+msgid "Greater than"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:219
+#: ../../SpinalHDL/Data types/Fix.rst:225
+msgid "x >= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:220
+msgid "Greater than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:222
+msgid "x < y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:223
+msgid "Less than"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:226
+msgid "Less than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:230
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:238
+#: ../../SpinalHDL/Data types/Fix.rst:272
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:239
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:240
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:241
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:242
+msgid "x.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:243
+msgid "Binary cast to UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:244
+msgid "UInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:245
+msgid "x.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:246
+msgid "Binary cast to SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:247
+msgid "SInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:248
+msgid "x.asBools"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:249
+msgid "Cast into a array of Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:250
+msgid "Vec(Bool(),width(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:251
+msgid "x.toUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:252
+msgid "Return the corresponding UInt (with truncation)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:253
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:254
+msgid "x.toSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:255
+msgid "Return the corresponding SInt (with truncation)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:256
+msgid "SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:257
+msgid "x.toUFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:258
+msgid "Return the corresponding UFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:259
+msgid "UFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:260
+msgid "x.toSFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:261
+msgid "Return the corresponding SFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:262
+msgid "SFix"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:265
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:271
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:274
+msgid "x.maxValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:275
+msgid "Return the maximum value storable"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:276
+#: ../../SpinalHDL/Data types/Fix.rst:279
+#: ../../SpinalHDL/Data types/Fix.rst:282
+msgid "Double"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:277
+msgid "x.minValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Fix.rst:278
+msgid "Return the minimum value storable"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/Floating.pot b/source/locale/gettext/SpinalHDL/Data types/Floating.pot
new file mode 100644
index 00000000000..f7e4f50e50f
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/Floating.pot	
@@ -0,0 +1,300 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/Floating.rst:2
+msgid "SpinalHDL floating-point support is under development and only partially used/tested, if you have any bugs with it, or you think that some functionality is missing, please create a `Github issue <https://github.com/SpinalHDL/SpinalHDL/issues>`_. Also, please do not use undocumented features in your code."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:7
+msgid "Floating"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:10
+#: ../../SpinalHDL/Data types/Floating.rst:78
+#: ../../SpinalHDL/Data types/Floating.rst:97
+#: ../../SpinalHDL/Data types/Floating.rst:122
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:12
+msgid "The ``Floating`` type corresponds to IEEE-754 encoded numbers. A second type called ``RecFloating`` helps in simplifying your design by recoding the floating-point value simplify some edge cases in IEEE-754 floating-point."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:14
+msgid "It's composed of a sign bit, an exponent field and a mantissa field. The widths of the different fields are defined in the IEEE-754 or de-facto standards."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:16
+msgid "This type can be used with the following import:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:23
+msgid "IEEE-754 floating format"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:25
+msgid "The numbers are encoded into IEEE-754 `floating-point format <https://en.wikipedia.org/wiki/IEEE_floating_point>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:28
+msgid "Recoded floating format"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:30
+msgid "Since IEEE-754 has some quirks about denormalized numbers and special values, Berkeley proposed another way of recoding floating-point values."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:32
+msgid "The mantissa is modified so that denormalized values can be treated the same as the normalized ones."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:34
+msgid "The exponent field is one bit larger that one of the IEEE-754 number."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:36
+msgid "The sign bit is kept unchanged between the two encodings."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:38
+msgid "Examples can be found `here <https://github.com/ucb-bar/berkeley-hardfloat/blob/master/README.md>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:41
+msgid "Zero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:43
+msgid "The zero is encoded with the three leading zeros of the exponent field being set to zero."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:46
+msgid "Denormalized values"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:48
+msgid "Denormalized values are encoded in the same way as a normal floating-point number. The mantissa is shifted so that the first one becomes implicit. The exponent is encoded as 107 (decimal) plus the index of the highest bit set to 1."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:52
+msgid "Normalized values"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:54
+msgid "The recoded mantissa for normalized values is exactly the same as the original IEEE-754 mantissa. The recoded exponent is encoded as 130 (decimal) plus the original exponent value."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:57
+msgid "Infinity"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:59
+msgid "The recoded mantissa value is treated as don't care. The recoded exponent three highest bits is 6 (decimal), the rest of the exponent can be treated as don't care."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:62
+msgid "NaN"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:64
+msgid "The recoded mantissa for normalized values is exactly the same as the original IEEE-754 mantissa. The recoded exponent three highest bits is 7 (decimal), the rest of the exponent can be treated as don't care."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:67
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:69
+msgid "The syntax to declare a floating-point number is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:72
+msgid "IEEE-754 Number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:77
+#: ../../SpinalHDL/Data types/Floating.rst:96
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:79
+msgid "Floating(exponentSize: Int, mantissaSize: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:80
+msgid "IEEE-754 Floating-point value with a custom exponent and mantissa size"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:81
+msgid "Floating16()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:82
+msgid "IEEE-754 Half precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:83
+msgid "Floating32()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:84
+msgid "IEEE-754 Single precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:85
+msgid "Floating64()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:86
+msgid "IEEE-754 Double precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:87
+msgid "Floating128()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:88
+msgid "IEEE-754 Quad precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:91
+msgid "Recoded floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:98
+msgid "RecFloating(exponentSize: Int, mantissaSize: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:99
+msgid "Recoded Floating-point value with a custom exponent and mantissa size"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:100
+msgid "RecFloating16()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:101
+msgid "Recoded Half precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:102
+msgid "RecFloating32()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:103
+msgid "Recoded Single precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:104
+msgid "RecFloating64()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:105
+msgid "Recoded Double precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:106
+msgid "RecFloating128()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:107
+msgid "Recoded Quad precision floating-point number"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:110
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:112
+msgid "The following operators are available for the ``Floating`` and ``RecFloating`` types:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:115
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:121
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:123
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:124
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:125
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:126
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:127
+msgid "x.asBools"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:128
+msgid "Cast into a array of Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:129
+msgid "Vec(Bool(),width(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:130
+msgid "x.toUInt(size: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:131
+msgid "Return the corresponding UInt (with truncation)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:132
+#: ../../SpinalHDL/Data types/Floating.rst:138
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:133
+msgid "x.toSInt(size: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:134
+msgid "Return the corresponding SInt (with truncation)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:135
+#: ../../SpinalHDL/Data types/Floating.rst:141
+msgid "SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:136
+msgid "x.fromUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:137
+#: ../../SpinalHDL/Data types/Floating.rst:140
+msgid "Return the corresponding Floating (with truncation)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Floating.rst:139
+msgid "x.fromSInt"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/Int.pot b/source/locale/gettext/SpinalHDL/Data types/Int.pot
new file mode 100644
index 00000000000..f2267f36496
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/Int.pot	
@@ -0,0 +1,1474 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/Int.rst:4
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "UInt/SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:6
+msgid "The ``UInt``/``SInt`` types are vectors of bits interpreted as two's complement unsigned/signed integers. They can do what ``Bits`` can do, with the addition of unsigned/signed integer arithmetic and comparisons."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:10
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:12
+msgid "The syntax to declare an integer is as follows:  (everything between [] is optional)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:18
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:19
+#: ../../SpinalHDL/Data types/Int.rst:78
+#: ../../SpinalHDL/Data types/Int.rst:179
+#: ../../SpinalHDL/Data types/Int.rst:243
+#: ../../SpinalHDL/Data types/Int.rst:292
+#: ../../SpinalHDL/Data types/Int.rst:378
+#: ../../SpinalHDL/Data types/Int.rst:480
+#: ../../SpinalHDL/Data types/Int.rst:674
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "UInt[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "SInt[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:22
+msgid "Create an unsigned/signed integer, bits count is inferred"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "UInt(x bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "SInt(x bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:25
+msgid "Create an unsigned/signed integer with x bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "U(value: Int[,x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "U(value: BigInt[,x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "S(value: Int[,x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "S(value: BigInt[,x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+#: ../../SpinalHDL/Data types/Int.rst:30
+msgid "Create an unsigned/signed integer assigned with 'value'"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "U\"[[size']base]value\""
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "S\"[[size']base]value\""
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "(base: 'h', 'd', 'o', 'b')"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "U([x bits,] elements: Element*)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "S([x bits,] elements: Element*)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:37
+msgid "Create an unsigned integer assigned with the value specified by :ref:`elements <element>`"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:66
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:68
+msgid "The following operators are available for the ``UInt`` and ``SInt`` types:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:71
+msgid "Logic"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:77
+#: ../../SpinalHDL/Data types/Int.rst:178
+#: ../../SpinalHDL/Data types/Int.rst:242
+#: ../../SpinalHDL/Data types/Int.rst:291
+#: ../../SpinalHDL/Data types/Int.rst:377
+#: ../../SpinalHDL/Data types/Int.rst:479
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:79
+#: ../../SpinalHDL/Data types/Int.rst:244
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:80
+#: ../../SpinalHDL/Data types/Int.rst:208
+msgid "~x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:81
+msgid "Bitwise NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:82
+#: ../../SpinalHDL/Data types/Int.rst:106
+#: ../../SpinalHDL/Data types/Int.rst:115
+#: ../../SpinalHDL/Data types/Int.rst:118
+#: ../../SpinalHDL/Data types/Int.rst:122
+#: ../../SpinalHDL/Data types/Int.rst:126
+#: ../../SpinalHDL/Data types/Int.rst:204
+#: ../../SpinalHDL/Data types/Int.rst:210
+#: ../../SpinalHDL/Data types/Int.rst:516
+msgid "T(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:83
+msgid "x & y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:84
+msgid "Bitwise AND"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:85
+#: ../../SpinalHDL/Data types/Int.rst:88
+#: ../../SpinalHDL/Data types/Int.rst:91
+#: ../../SpinalHDL/Data types/Int.rst:183
+#: ../../SpinalHDL/Data types/Int.rst:189
+#: ../../SpinalHDL/Data types/Int.rst:192
+#: ../../SpinalHDL/Data types/Int.rst:198
+msgid "T(max(w(x), w(y)) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:86
+msgid "x | y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:87
+msgid "Bitwise OR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:89
+msgid "x ^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:90
+msgid "Bitwise XOR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:92
+msgid "x.xorR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:93
+msgid "XOR all bits of x (reduction operator)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:94
+#: ../../SpinalHDL/Data types/Int.rst:97
+#: ../../SpinalHDL/Data types/Int.rst:100
+#: ../../SpinalHDL/Data types/Int.rst:247
+#: ../../SpinalHDL/Data types/Int.rst:250
+#: ../../SpinalHDL/Data types/Int.rst:253
+#: ../../SpinalHDL/Data types/Int.rst:256
+#: ../../SpinalHDL/Data types/Int.rst:259
+#: ../../SpinalHDL/Data types/Int.rst:262
+#: ../../SpinalHDL/Data types/Int.rst:382
+#: ../../SpinalHDL/Data types/Int.rst:385
+#: ../../SpinalHDL/Data types/Int.rst:403
+#: ../../SpinalHDL/Data types/Int.rst:406
+#: ../../SpinalHDL/Data types/Int.rst:409
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:95
+msgid "x.orR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:96
+msgid "OR all bits of x (reduction operator)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:98
+msgid "x.andR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:99
+msgid "AND all bits of x (reduction operator)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:101
+#: ../../SpinalHDL/Data types/Int.rst:104
+msgid "x \\>\\> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:102
+msgid "Arithmetic shift right, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:103
+msgid "T(w(x) - y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:105
+msgid "Arithmetic shift right, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:107
+#: ../../SpinalHDL/Data types/Int.rst:110
+msgid "x \\<\\< y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:108
+msgid "Arithmetic shift left, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:109
+msgid "T(w(x) + y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:111
+msgid "Arithmetic shift left, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:112
+msgid "T(w(x) + max(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:113
+msgid "x \\|\\>\\> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:114
+msgid "Logical shift right, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:116
+msgid "x \\|\\<\\< y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:117
+msgid "Logical shift left, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:119
+msgid "x.rotateLeft(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "Logical left rotation, y : UInt/Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "The width of y is constrained to the width of log2Up(x) or less"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:123
+msgid "x.rotateRight(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "Logical right rotation, y : UInt/Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:127
+msgid "x.clearAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:128
+msgid "Clear all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:129
+#: ../../SpinalHDL/Data types/Int.rst:132
+#: ../../SpinalHDL/Data types/Int.rst:135
+#: ../../SpinalHDL/Data types/Int.rst:138
+msgid "*modifies x*"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:130
+msgid "x.setAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:131
+msgid "Set all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:133
+msgid "x.setAllTo(value : Boolean)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:134
+msgid "Set all bits to the given Boolean value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:136
+msgid "x.setAllTo(value : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:137
+msgid "Set all bits to the given Bool value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:142
+msgid "Notice the difference in behaviour between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type of :code:`y`."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:145
+msgid "In the first case \"2\" is an ``Int`` (which can be seen as an \"elaboration integer constant\"), and in the second case it is a hardware signal (type ``UInt``) that may or may not be a constant."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:173
+msgid "Arithmetic"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:180
+#: ../../SpinalHDL/Data types/Int.rst:293
+#: ../../SpinalHDL/Data types/Int.rst:379
+#: ../../SpinalHDL/Data types/Int.rst:481
+#: ../../SpinalHDL/Data types/Int.rst:674
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:181
+msgid "x + y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:182
+msgid "Addition"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:184
+msgid "x +^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:185
+msgid "Addition with carry"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:186
+#: ../../SpinalHDL/Data types/Int.rst:195
+msgid "T(max(w(x), w(y)) + 1 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:187
+msgid "x +| y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:188
+msgid "Addition of addend with `saturation`_ (see also `T.maxValue` and `T.minValue`)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:190
+msgid "x - y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:191
+msgid "Subtraction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:193
+msgid "x -^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:194
+msgid "Subtraction with carry"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:196
+msgid "x -| y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:197
+msgid "Subtraction of subtrahend with `saturation`_ (see also `T.minValue` and `T.maxValue`)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:199
+msgid "x * y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:200
+msgid "Multiplication"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:201
+msgid "T(w(x) + w(y)) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:202
+msgid "x / y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:203
+msgid "Division"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:205
+msgid "x % y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:206
+msgid "Modulo"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:207
+msgid "T(min(w(x), w(y)) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:209
+msgid "Unary One's compliment, Bitwise NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:211
+msgid "-x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:212
+msgid "Unary Two's compliment of SInt type.  Not available for UInt."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:213
+#: ../../SpinalHDL/Data types/Int.rst:302
+#: ../../SpinalHDL/Data types/Int.rst:311
+msgid "SInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:233
+msgid "Notice how simulation assertions are made here (with ``===``), as opposed to elaboration assertions in the previous example (with ``==``)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:237
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:245
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:246
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:248
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:249
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:251
+msgid "x > y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:252
+msgid "Greater than"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:254
+msgid "x >= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:255
+msgid "Greater than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:257
+msgid "x < y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:258
+msgid "Less than"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:260
+msgid "x <= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:261
+msgid "Less than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:282
+msgid "When comparing ``UInt`` values in a way that allows for \"wraparound\" behavior, meaning that the values will \"wrap around\" to the minimum value when they exceed the maximum value. The ``wrap`` method of ``UInt`` can be used as ``x.wrap < y`` for ``UInt`` variables ``x, y``, the result will be true if ``x`` is less than ``y`` in the wraparound sense."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:286
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:294
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:295
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:296
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:297
+msgid "x.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:298
+msgid "Binary cast to UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:299
+#: ../../SpinalHDL/Data types/Int.rst:314
+msgid "UInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:300
+msgid "x.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:301
+msgid "Binary cast to SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:303
+msgid "x.asBools"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:304
+msgid "Cast into a array of Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:305
+msgid "Vec(Bool(), w(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:306
+msgid "x.asBool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:307
+msgid "Extract LSB of :code:`x`"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:308
+msgid "Bool(x.lsb)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:309
+msgid "S(x: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:310
+msgid "Cast a Data into a SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:312
+msgid "U(x: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:313
+msgid "Cast a Data into an UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:315
+msgid "x.intoSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:316
+msgid "Convert to SInt expanding sign bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:317
+msgid "SInt(w(x) + 1 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:318
+msgid "myUInt.twoComplement(en: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:319
+msgid "Generate two's complement of number if ``en`` is ``True``, unchanged otherwise. (``en`` makes result negative)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:320
+msgid "SInt(w(myUInt) + 1, bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:321
+msgid "mySInt.abs"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:322
+msgid "Return the absolute value as a UInt value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:323
+#: ../../SpinalHDL/Data types/Int.rst:326
+msgid "UInt(w(mySInt) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:324
+msgid "mySInt.abs(en: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:325
+msgid "Return the absolute value as a UInt value when ``en`` is ``True``, otherwise just reinterpret bits as unsigned"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:327
+msgid "mySInt.absWithSym"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:328
+msgid "Return the absolute value of the UInt value with symmetric, shrink 1 bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:329
+msgid "UInt(w(mySInt) - 1 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:332
+msgid "To cast a ``Bool``, a ``Bits``, or an ``SInt`` into a ``UInt``, you can use ``U(something)``. To cast things into an ``SInt``, you can use ``S(something)``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:368
+msgid "Bit extraction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:370
+msgid "All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs the extraction operators can also be used to assign a part of a ``UInt`` / ``SInt`` ."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:380
+msgid "x(y: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:381
+msgid "Static bit access of y-th bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:383
+msgid "x(x: UInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:384
+msgid "Variable bit access of y-th bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:386
+msgid "x(offset: Int, width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:387
+msgid "Fixed part select of fixed width, offset is LSB index"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:388
+#: ../../SpinalHDL/Data types/Int.rst:391
+msgid "Bits(width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:389
+msgid "x(offset: UInt, width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:390
+msgid "Variable part-select of fixed width, offset is LSB index"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:392
+msgid "x(range: Range)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:393
+msgid "Access a :ref:`range <range>` of bits. Ex : myBits(4 downto 2)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:394
+msgid "Bits(range.size bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:395
+msgid "x.subdivideIn(y slices, [strict: Boolean])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:396
+msgid "Subdivide x into y slices, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:397
+msgid "Vec(Bits(...), y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:398
+msgid "x.subdivideIn(y bits, [strict: Boolean])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:399
+msgid "Subdivide x in multiple slices of y bits, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:400
+msgid "Vec(Bits(y bit), ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:401
+msgid "x.msb"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:402
+msgid "Access most significant bit of x (highest index, sign bit for SInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:404
+msgid "x.lsb"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:405
+msgid "Access lowest significant bit of x (index 0)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:407
+msgid "mySInt.sign"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:408
+msgid "Access most sign bit, only SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:413
+msgid "Some basic examples:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:442
+msgid "Subdivide details"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:444
+msgid "Both overloads of ``subdivideIn`` have an optional parameter ``strict`` (i.e. ``subdivideIn(slices: SlicesCount, strict: Boolean = true)``). If ``strict`` is ``true`` an error will be raised if the input could not be divided into equal parts. If set to ``false`` the last element may be smaller than the other (equal sized) elements."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:470
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:472
+msgid "In contrast to the bit extraction operations listed above it's not possible to use the return values to assign to the original signal."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:482
+msgid "x.getWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:483
+msgid "Return bitcount"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:484
+#: ../../SpinalHDL/Data types/Int.rst:487
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:485
+msgid "x.high"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:486
+msgid "Return the index of the MSB (highest allowed index for Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:488
+msgid "x.bitsRange"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:489
+msgid "Return the range (0 to x.high)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:490
+#: ../../SpinalHDL/Data types/Int.rst:499
+msgid "Range"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:491
+msgid "x.minValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:492
+msgid "Lowest possible value of x (e.g. 0 for UInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:493
+#: ../../SpinalHDL/Data types/Int.rst:496
+msgid "BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:494
+msgid "x.maxValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:495
+msgid "Highest possible value of x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:497
+msgid "x.valueRange"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:498
+msgid "Return the range from minimum to maximum possible value of x (x.minValue to x.maxValue)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:500
+msgid "x ## y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:501
+msgid "Concatenate, x->high, y->low"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:502
+msgid "Bits(w(x) + w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:503
+msgid "x #* n"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:504
+msgid "Repeat x n-times"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:505
+msgid "Bits(w(x) * n bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:506
+msgid "x @@ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:507
+msgid "Concatenate x:T with y:Bool/SInt/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:508
+msgid "T(w(x) + w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:509
+msgid "x.resize(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "Return a resized copy of x, if enlarged, it is filled with zero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "for UInt or filled with the sign for SInt, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:512
+msgid "T(y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:513
+msgid "x.resized"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "Return a version of x which is allowed to be automatically"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:0
+msgid "resized where needed"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:517
+msgid "x.expand"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:518
+msgid "Return x with 1 bit expand"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:519
+msgid "T(w(x)+1 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:520
+msgid "x.getZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:521
+msgid "Return a new instance of type T that is assigned a constant value of zeros the same width as x."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:522
+msgid "T(0, w(x) bits).clearAll()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:523
+msgid "x.getAllTrue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:524
+msgid "Return a new instance of type T that is assigned a constant value of ones the same width as x."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:525
+msgid "T(w(x) bits).setAll()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:528
+msgid "`validRange` can only be used for types where the minimum and maximum values fit into a signed 32-bit integer. (This is a limitation given by the Scala ``scala.collection.immutable.Range`` type which uses `Int`)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:547
+msgid "FixPoint operations"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:549
+msgid "For fixpoint, we can divide it into two parts:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:551
+msgid "Lower bit operations (rounding methods)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:552
+msgid "High bit operations (saturation operations)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:555
+msgid "Lower bit operations"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:559
+msgid "About Rounding: https://en.wikipedia.org/wiki/Rounding"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "SpinalHDL-Name"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Wikipedia-Name"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "API"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Mathematic Algorithm"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "return(align=false)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Supported"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "FLOOR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "RoundDown"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+#: ../../SpinalHDL/Data types/Int.rst:622
+msgid "floor"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "floor(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+#: ../../SpinalHDL/Data types/Int.rst:565
+#: ../../SpinalHDL/Data types/Int.rst:622
+#: ../../SpinalHDL/Data types/Int.rst:623
+msgid "w(x)-n   bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+#: ../../SpinalHDL/Data types/Int.rst:565
+#: ../../SpinalHDL/Data types/Int.rst:566
+#: ../../SpinalHDL/Data types/Int.rst:567
+#: ../../SpinalHDL/Data types/Int.rst:568
+#: ../../SpinalHDL/Data types/Int.rst:569
+#: ../../SpinalHDL/Data types/Int.rst:570
+#: ../../SpinalHDL/Data types/Int.rst:571
+msgid "Yes"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "FLOORTOZERO"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "RoundToZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+#: ../../SpinalHDL/Data types/Int.rst:623
+msgid "floorToZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "sign*floor(abs(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "CEIL"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "RoundUp"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+#: ../../SpinalHDL/Data types/Int.rst:624
+msgid "ceil"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "ceil(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+#: ../../SpinalHDL/Data types/Int.rst:567
+#: ../../SpinalHDL/Data types/Int.rst:568
+#: ../../SpinalHDL/Data types/Int.rst:569
+#: ../../SpinalHDL/Data types/Int.rst:570
+#: ../../SpinalHDL/Data types/Int.rst:571
+#: ../../SpinalHDL/Data types/Int.rst:624
+#: ../../SpinalHDL/Data types/Int.rst:625
+#: ../../SpinalHDL/Data types/Int.rst:626
+#: ../../SpinalHDL/Data types/Int.rst:627
+#: ../../SpinalHDL/Data types/Int.rst:628
+#: ../../SpinalHDL/Data types/Int.rst:629
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "w(x)-n+1 bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "CEILTOINF"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "RoundToInf"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+#: ../../SpinalHDL/Data types/Int.rst:625
+msgid "ceilToInf"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "sign*ceil(abs(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "ROUNDUP"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "RoundHalfUp"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+#: ../../SpinalHDL/Data types/Int.rst:626
+msgid "roundUp"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "floor(x+0.5)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "ROUNDDOWN"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "RoundHalfDown"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+#: ../../SpinalHDL/Data types/Int.rst:627
+msgid "roundDown"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "ceil(x-0.5)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "ROUNDTOZERO"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "RoundHalfToZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+#: ../../SpinalHDL/Data types/Int.rst:629
+msgid "roundToZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "sign*ceil(abs(x)-0.5)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+#: ../../SpinalHDL/Data types/Int.rst:584
+#: ../../SpinalHDL/Data types/Int.rst:585
+#: ../../SpinalHDL/Data types/Int.rst:588
+msgid "ROUNDTOINF"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+msgid "RoundHalfToInf"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+#: ../../SpinalHDL/Data types/Int.rst:628
+msgid "roundToInf"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+msgid "sign*floor(abs(x)+0.5)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "ROUNDTOEVEN"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+msgid "RoundHalfToEven"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+msgid "roundToEven"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "No"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "ROUNDTOODD"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "RoundHalfToOdd"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "roundToOdd"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:577
+msgid "The **RoundToEven** and **RoundToOdd** modes are very special, and are used in some big data statistical fields with high accuracy concerns, SpinalHDL doesn't support them yet."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:579
+msgid "You will find `ROUNDUP`, `ROUNDDOWN`, `ROUNDTOZERO`, `ROUNDTOINF`, `ROUNDTOEVEN`, `ROUNTOODD` are very close in behavior, `ROUNDTOINF` is the most common. The behavior of rounding in different programming languages may be different."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "Programming language"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "default-RoundType"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "comments"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:584
+msgid "Matlab"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:584
+#: ../../SpinalHDL/Data types/Int.rst:585
+#: ../../SpinalHDL/Data types/Int.rst:588
+msgid "round(1.5)=2,round(2.5)=3;round(-1.5)=-2,round(-2.5)=-3"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:584
+#: ../../SpinalHDL/Data types/Int.rst:585
+#: ../../SpinalHDL/Data types/Int.rst:588
+msgid "round to ±Infinity"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:585
+msgid "python2"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "python3"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "round(1.5)=round(2.5)=2;  round(-1.5)=round(-2.5)=-2"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "close to Even"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "Scala.math"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "ROUNDTOUP"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "round(1.5)=2,round(2.5)=3;round(-1.5)=-1,round(-2.5)=-2"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "always to +Infinity"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:588
+msgid "SpinalHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:592
+msgid "In SpinalHDL `ROUNDTOINF` is the default RoundType (``round = roundToInf``)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:615
+msgid "Only ``floor`` and ``floorToZero`` work without the ``align`` option; they do not need a carry bit. Other rounding operations default to using a carry bit."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:617
+msgid "**round Api**"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "Return(align=false)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "Return(align=true)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:622
+#: ../../SpinalHDL/Data types/Int.rst:624
+#: ../../SpinalHDL/Data types/Int.rst:626
+#: ../../SpinalHDL/Data types/Int.rst:627
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "Both"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:622
+#: ../../SpinalHDL/Data types/Int.rst:623
+#: ../../SpinalHDL/Data types/Int.rst:624
+#: ../../SpinalHDL/Data types/Int.rst:625
+#: ../../SpinalHDL/Data types/Int.rst:626
+#: ../../SpinalHDL/Data types/Int.rst:627
+#: ../../SpinalHDL/Data types/Int.rst:628
+#: ../../SpinalHDL/Data types/Int.rst:629
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "w(x)-n bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:623
+#: ../../SpinalHDL/Data types/Int.rst:625
+#: ../../SpinalHDL/Data types/Int.rst:628
+#: ../../SpinalHDL/Data types/Int.rst:629
+msgid "SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:623
+msgid "equal to floor in UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:625
+msgid "equal to ceil in UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:626
+msgid "simple for HW"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:628
+msgid "most Common"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:629
+msgid "equal to roundDown in UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "round"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "SpinalHDL chose roundToInf"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:634
+msgid "Although ``roundToInf`` is very common, ``roundUp`` has the least cost and good timing, with almost no performance loss. As a result, ``roundUp`` is strongly recommended for production use."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:638
+msgid "High bit operations"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "function"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Operation"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Positive-Op"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Negative-Op"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "sat"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "Saturation"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "when(Top[w-1, w-n].orR) set maxValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "When(Top[w-1, w-n].andR) set minValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:646
+msgid "trim"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:646
+msgid "Discard"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:646
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "N/A"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "symmetry"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "Symmetric"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "minValue = -maxValue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:650
+msgid "Symmetric is only valid for ``SInt``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:663
+msgid "fixTo function"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:665
+msgid "Two ways are provided in ``UInt``/``SInt`` to do fixpoint:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:669
+msgid "``fixTo`` is strongly recommended in your RTL work, you don't need to handle carry bit alignment and bit width calculations manually like **Way1** in the above diagram."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:671
+msgid "Factory Fix function with Auto Saturation:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:674
+msgid "Function"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "fixTo(section, roundType, symmetric)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "Factory FixFunction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "section.size bits"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/Vec.pot b/source/locale/gettext/SpinalHDL/Data types/Vec.pot
new file mode 100644
index 00000000000..f7dfbb7c195
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/Vec.pot	
@@ -0,0 +1,237 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/Vec.rst:7
+msgid "Vec"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:10
+#: ../../SpinalHDL/Data types/Vec.rst:24
+#: ../../SpinalHDL/Data types/Vec.rst:72
+#: ../../SpinalHDL/Data types/Vec.rst:99
+#: ../../SpinalHDL/Data types/Vec.rst:121
+#: ../../SpinalHDL/Data types/Vec.rst:147
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:12
+msgid "A ``Vec`` is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:15
+#: ../../SpinalHDL/Data types/Vec.rst:23
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:17
+msgid "The syntax to declare a vector is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:25
+msgid "Vec.fill(size: Int)(type: Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:26
+msgid "Create a vector of ``size`` elements of type ``Data``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:27
+msgid "Vec(x, y, ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:0
+msgid "Create a vector where indexes point to the provided elements."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:0
+msgid "Does not create new hardware signals."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:0
+msgid "This constructor supports mixed element width."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:34
+msgid "Examples"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:61
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:63
+msgid "The following operators are available for the ``Vec`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:66
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:71
+#: ../../SpinalHDL/Data types/Vec.rst:98
+#: ../../SpinalHDL/Data types/Vec.rst:120
+#: ../../SpinalHDL/Data types/Vec.rst:146
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:73
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:74
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:75
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:76
+#: ../../SpinalHDL/Data types/Vec.rst:79
+#: ../../SpinalHDL/Data types/Vec.rst:157
+#: ../../SpinalHDL/Data types/Vec.rst:160
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:77
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:78
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:93
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:100
+#: ../../SpinalHDL/Data types/Vec.rst:122
+#: ../../SpinalHDL/Data types/Vec.rst:148
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:101
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:102
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:103
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:114
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:123
+msgid "x.getBitsWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:124
+msgid "Return the full size of the Vec"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:125
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:137
+msgid "Lib helper functions"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:140
+msgid "You need to import ``import spinal.lib._`` to put these functions in scope."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:149
+msgid "x.sCount(condition: T => Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:150
+msgid "Count the number of occurence matching a given condition in the Vec."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:151
+#: ../../SpinalHDL/Data types/Vec.rst:154
+#: ../../SpinalHDL/Data types/Vec.rst:163
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:152
+msgid "x.sCount(value: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:153
+msgid "Count the number of occurence of a value in the Vec."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:155
+msgid "x.sExists(condition: T => Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:156
+msgid "Check if there is a matching condition in the Vec."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:158
+msgid "x.sContains(value: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:159
+msgid "Check if there is an element with a given value present in the Vec."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:161
+msgid "x.sFindFirst(condition: T => Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:162
+msgid "Find the first element matching the given condition in the Vec, return the index of that element."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:164
+msgid "x.reduceBalancedTree(op: (T, T) => T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:165
+msgid "Balanced reduce function, to try to minimize the depth of the resulting circuit. ``op`` should be commutative and associative."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:166
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:167
+msgid "x.shuffle(indexMapping: Int => Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:168
+msgid "Shuffle the Vec using a function that maps the old indexes to new ones."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:169
+msgid "Vec[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/Vec.rst:191
+msgid "The sXXX prefix is used to disambiguate with respect to identically named Scala functions that accept a lambda function as argument."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/bits.pot b/source/locale/gettext/SpinalHDL/Data types/bits.pot
new file mode 100644
index 00000000000..4e813e2d31e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/bits.pot	
@@ -0,0 +1,691 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/bits.rst:4
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:6
+msgid "The ``Bits`` type is a vector of bits without conveying any arithmetic meaning."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:9
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:11
+msgid "The syntax to declare a bit vector is as follows (everything between [] is optional):"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:17
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:18
+#: ../../SpinalHDL/Data types/bits.rst:82
+#: ../../SpinalHDL/Data types/bits.rst:182
+#: ../../SpinalHDL/Data types/bits.rst:207
+#: ../../SpinalHDL/Data types/bits.rst:260
+#: ../../SpinalHDL/Data types/bits.rst:358
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:19
+msgid "Bits [()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:20
+msgid "Create Bits, bit count is inferred from the widest assignment statement after construction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:22
+#: ../../SpinalHDL/Data types/bits.rst:393
+msgid "Bits(x bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:23
+msgid "Create Bits with x bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "B(value: Int[, x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "B(value: BigInt[, x bits])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:26
+msgid "Create Bits with x bits assigned with 'value'"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:27
+msgid "B\"[[size']base]value\""
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:28
+msgid "Create Bits assigned with 'value' (base: 'h', 'd', 'o', 'b')"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:29
+msgid "B([x bits,] elements: Element*)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:30
+msgid "Create Bits assigned with the value specified by :ref:`elements <element>`"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:53
+msgid "When inferring the width of a ``Bits`` the sizes of assigned values still have to match the final size of the signal:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:70
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:72
+msgid "The following operators are available for the ``Bits`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:75
+msgid "Logic"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:81
+#: ../../SpinalHDL/Data types/bits.rst:181
+#: ../../SpinalHDL/Data types/bits.rst:206
+#: ../../SpinalHDL/Data types/bits.rst:259
+#: ../../SpinalHDL/Data types/bits.rst:357
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:83
+#: ../../SpinalHDL/Data types/bits.rst:183
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:84
+msgid "~x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:85
+msgid "Bitwise NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:86
+#: ../../SpinalHDL/Data types/bits.rst:114
+#: ../../SpinalHDL/Data types/bits.rst:128
+#: ../../SpinalHDL/Data types/bits.rst:132
+#: ../../SpinalHDL/Data types/bits.rst:136
+#: ../../SpinalHDL/Data types/bits.rst:140
+#: ../../SpinalHDL/Data types/bits.rst:211
+#: ../../SpinalHDL/Data types/bits.rst:226
+#: ../../SpinalHDL/Data types/bits.rst:374
+#: ../../SpinalHDL/Data types/bits.rst:389
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:87
+msgid "x & y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:88
+msgid "Bitwise AND"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:89
+#: ../../SpinalHDL/Data types/bits.rst:92
+#: ../../SpinalHDL/Data types/bits.rst:95
+msgid "Bits(w(xy) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:90
+msgid "x | y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:91
+msgid "Bitwise OR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:93
+msgid "x ^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:94
+msgid "Bitwise XOR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:96
+msgid "x.xorR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:97
+msgid "XOR all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:98
+#: ../../SpinalHDL/Data types/bits.rst:101
+#: ../../SpinalHDL/Data types/bits.rst:104
+#: ../../SpinalHDL/Data types/bits.rst:186
+#: ../../SpinalHDL/Data types/bits.rst:189
+#: ../../SpinalHDL/Data types/bits.rst:264
+#: ../../SpinalHDL/Data types/bits.rst:267
+#: ../../SpinalHDL/Data types/bits.rst:285
+#: ../../SpinalHDL/Data types/bits.rst:288
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:99
+msgid "x.orR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:100
+msgid "OR all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:102
+msgid "x.andR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:103
+msgid "AND all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "y = 1 // Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "x \\>\\> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift right, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Result may reduce width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:109
+msgid "Bits(w(x) - y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "y = U(1) // UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift right, y: UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Result is same width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "x \\<\\< y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift left, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Result may increase width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:119
+msgid "Bits(w(x) + y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift left, y: UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:124
+msgid "Bits(w(x) + max(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:125
+msgid "x \\|\\>\\> y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift right, y: Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:129
+msgid "x \\|\\<\\< y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical shift left, y: Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:133
+msgid "x.rotateLeft(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical left rotation, y: UInt/Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:137
+msgid "x.rotateRight(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:0
+msgid "Logical right rotation, y: UInt/Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:141
+msgid "x.clearAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:142
+msgid "Clear all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:143
+#: ../../SpinalHDL/Data types/bits.rst:146
+#: ../../SpinalHDL/Data types/bits.rst:149
+#: ../../SpinalHDL/Data types/bits.rst:152
+msgid "*modifies x*"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:144
+msgid "x.setAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:145
+msgid "Set all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:147
+msgid "x.setAllTo(value: Boolean)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:148
+msgid "Set all bits to the given Boolean value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:150
+msgid "x.setAllTo(value: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:151
+msgid "Set all bits to the given Bool value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:176
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:184
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:185
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:187
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:188
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:201
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:208
+#: ../../SpinalHDL/Data types/bits.rst:261
+#: ../../SpinalHDL/Data types/bits.rst:359
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:209
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:210
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:212
+msgid "x.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:213
+msgid "Binary cast to UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:214
+msgid "UInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:215
+msgid "x.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:216
+msgid "Binary cast to SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:217
+msgid "SInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:218
+msgid "x.asBools"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:219
+msgid "Cast to an array of Bools"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:220
+msgid "Vec(Bool(), w(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:221
+msgid "x.asBool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:222
+msgid "Extract LSB of :code:`x`"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:223
+msgid "Bool(x.lsb)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:224
+msgid "B(x: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:225
+msgid "Cast Data to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:229
+msgid "To cast a ``Bool``, ``UInt`` or an ``SInt`` into a ``Bits``, you can use ``B(something)`` or ``B(something[, x bits])``:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:247
+msgid "Bit extraction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:249
+msgid "All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs the extraction operators can also be used to assign a part of a ``Bits``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:252
+msgid "All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs They can also be used to select a range of bits to be written."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:262
+msgid "x(y: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:263
+msgid "Static bit access of y-th bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:265
+msgid "x(x: UInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:266
+msgid "Variable bit access of y-th bit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:268
+msgid "x(offset: Int, width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:269
+msgid "Fixed part select of fixed width, offset is LSB index"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:270
+#: ../../SpinalHDL/Data types/bits.rst:273
+msgid "Bits(width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:271
+msgid "x(offset: UInt, width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:272
+msgid "Variable part-select of fixed width, offset is LSB index"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:274
+msgid "x(range: Range)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:275
+msgid "Access a :ref:`range <range>` of bits. Ex : myBits(4 downto 2)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:276
+msgid "Bits(range.size bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:277
+msgid "x.subdivideIn(y slices, [strict: Boolean])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:278
+msgid "Subdivide x into y slices, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:279
+msgid "Vec(Bits(...), y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:280
+msgid "x.subdivideIn(y bits, [strict: Boolean])"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:281
+msgid "Subdivide x in multiple slices of y bits, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:282
+msgid "Vec(Bits(y bit), ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:283
+msgid "x.msb"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:284
+msgid "Access most significant bit of x (highest index)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:286
+msgid "x.lsb"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:287
+msgid "Access lowest significant bit of x (index 0)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:291
+msgid "Some basic examples:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:320
+msgid "Subdivide details"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:322
+msgid "Both overloads of ``subdivideIn`` have an optional parameter ``strict`` (i.e. ``subdivideIn(slices: SlicesCount, strict: Boolean = true)``). If ``strict`` is ``true`` an error will be raised if the input could not be divided into equal parts. If set to ``false`` the last element may be smaller than the other (equal sized) elements."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:348
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:350
+msgid "In contrast to the bit extraction operations listed above it's not possible to use the return values to assign to the original signal."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:360
+msgid "x.getWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:361
+msgid "Return bitcount"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:362
+#: ../../SpinalHDL/Data types/bits.rst:371
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:363
+msgid "x.bitsRange"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:364
+msgid "Return the range (0 to x.high)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:365
+#: ../../SpinalHDL/Data types/bits.rst:368
+msgid "Range"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:366
+msgid "x.valueRange"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:367
+msgid "Return the range of minimum to maximum x values, interpreted as an unsigned integer (0 to 2 \\*\\* width - 1)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:369
+msgid "x.high"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:370
+msgid "Return the index of the MSB (highest allowed zero-based index for x)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:372
+msgid "x.reversed"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:373
+msgid "Return a copy of x with reverse bit order, MSB<>LSB are mirrored."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:375
+msgid "x ## y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:376
+msgid "Concatenate, x->high, y->low"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:377
+msgid "Bits(w(x) + w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:378
+msgid "x #* n"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:379
+msgid "Repeat x n-times"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:380
+msgid "Bits(w(x) * n bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:381
+msgid "x.resize(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:382
+msgid "Return a resized representation of x, if enlarged, it is extended with zero padding at MSB as necessary, y: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:384
+msgid "Bits(y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:385
+msgid "x.resized"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:386
+msgid "Return a version of x which is allowed to be automatically resized were needed.  The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:390
+msgid "x.resizeLeft(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:391
+msgid "Resize by keeping MSB at the same place, x:Int The resize may widen or truncate, retaining the MSB."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:394
+msgid "x.getZero"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:395
+msgid "Return a new instance of Bits that is assigned a constant value of zeros the same width as x."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:396
+msgid "Bits(0, w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:397
+msgid "x.getAllTrue"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:398
+msgid "Return a new instance of Bits that is assigned a constant value of ones the same width as x."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:399
+msgid "Bits(w(x) bits).setAll()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:402
+msgid "`validRange` can only be used for types where the minimum and maximum values fit into a signed 32-bit integer. (This is a limitation given by the Scala ``scala.collection.immutable.Range`` type which uses `Int`)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:424
+msgid "MaskedLiteral"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bits.rst:426
+msgid "MaskedLiteral values are bit vectors with don't care values denoted with ``-``. They can be used for direct comparison or for ``switch`` statements and ``mux`` es."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/bool.pot b/source/locale/gettext/SpinalHDL/Data types/bool.pot
new file mode 100644
index 00000000000..e2663ca7620
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/bool.pot	
@@ -0,0 +1,472 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/bool.rst:4
+#: ../../SpinalHDL/Data types/bool.rst:70
+#: ../../SpinalHDL/Data types/bool.rst:73
+#: ../../SpinalHDL/Data types/bool.rst:76
+#: ../../SpinalHDL/Data types/bool.rst:80
+#: ../../SpinalHDL/Data types/bool.rst:112
+#: ../../SpinalHDL/Data types/bool.rst:116
+#: ../../SpinalHDL/Data types/bool.rst:120
+#: ../../SpinalHDL/Data types/bool.rst:123
+#: ../../SpinalHDL/Data types/bool.rst:126
+#: ../../SpinalHDL/Data types/bool.rst:135
+#: ../../SpinalHDL/Data types/bool.rst:138
+#: ../../SpinalHDL/Data types/bool.rst:141
+#: ../../SpinalHDL/Data types/bool.rst:144
+#: ../../SpinalHDL/Data types/bool.rst:192
+#: ../../SpinalHDL/Data types/bool.rst:195
+#: ../../SpinalHDL/Data types/bool.rst:198
+#: ../../SpinalHDL/Data types/bool.rst:201
+#: ../../SpinalHDL/Data types/bool.rst:204
+#: ../../SpinalHDL/Data types/bool.rst:207
+#: ../../SpinalHDL/Data types/bool.rst:216
+#: ../../SpinalHDL/Data types/bool.rst:248
+#: ../../SpinalHDL/Data types/bool.rst:251
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:7
+#: ../../SpinalHDL/Data types/bool.rst:66
+#: ../../SpinalHDL/Data types/bool.rst:108
+#: ../../SpinalHDL/Data types/bool.rst:188
+#: ../../SpinalHDL/Data types/bool.rst:244
+#: ../../SpinalHDL/Data types/bool.rst:271
+#: ../../SpinalHDL/Data types/bool.rst:305
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:9
+msgid "The ``Bool`` type corresponds to a boolean value (True or False) or a single bit/wire used in a hardware design.  While named similarly it should not be confused with Scala `Boolean` type which does not describe hardware but truth values in the Scala generator code."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:14
+msgid "An important concept and rule-of-thumb to understand is that the Scala `Boolean` type is used in places where elaboration-time HDL code-generation decision making is occuring in Scala code.  Like any regular program it affects execution of the Scala program that is SpinalHDL at the time the program is being run to perform HDL code generation."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:20
+msgid "Therefore the value of a Scala `Boolean` can not be observed from hardware, because it only exists ahead-of-time in the SpinalHDL program at the time of HDL code-gen."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:24
+msgid "In scenarios where you might need this for your design, for example to pass a value (that maybe acting as a parameterized constant input) from Scala into your hardware design, you can type convert it to Bool with the constructor `Bool(value: Boolean)`."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:28
+msgid "Similarly the value of a SpinalHDL `Bool` can not be seen at code-generation, all that can be seen and manipulated is the HDL construct concerning a `wire` and how it is routed (through modules/Components), driven (sourced) and connected (sunk)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:32
+msgid "The signal direction of assignment operators `:=` is managed by SpinalHDL. The use of the Bool instance on the left-hand-side or the right-hand-side of the assignment operator `:=` dictates if it is a source (provides state) or sink (captures state) for a given assignment."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:37
+msgid "Multiple uses of the assignment operator are allowed, such that it is normal for a signal wire to act as a source (provides a value to drive HDL state) to be able to connect and drive multiple inputs of other HDL constructs.  When a Bool instance used as a source the order the assignment statements appear or are executed in Scala does not matter, unlike when it is used as a sink (captures state)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:44
+msgid "When multiple assignment operators drive the Bool (the Bool is on the left-hand-side of the assignment expression), the last assignment statement wins rule; take effect.  The last would be the last to execute in Scala code.  This matter can affect the layout and ordering of your SpinalHDL Scala code to ensure the correct precedence order is archived in the hardware design for assigning a new state to the Bool in hardware."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:51
+msgid "It may help to understand the concept with relating the Scala/SpinalHDL `Bool` instance as a reference to a HDL `net` in the net-list.  Which the assignment `:=` operator is attaching HDL constructs into the same net."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:57
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:59
+msgid "The syntax to declare a boolean value is as follows: (everything between [] is optional)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:65
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:67
+#: ../../SpinalHDL/Data types/bool.rst:272
+#: ../../SpinalHDL/Data types/bool.rst:306
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:68
+msgid "Bool()"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:69
+msgid "Create a Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:71
+msgid "True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:72
+msgid "Create a Bool assigned with ``true``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:74
+msgid "False"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:75
+msgid "Create a Bool assigned with ``false``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:77
+msgid "Bool(value: Boolean)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:78
+msgid "Create a Bool assigned with a value from a Scala Boolean type (true, false). This explicitly converts to ``True`` or ``False``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:93
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:95
+msgid "The following operators are available for the ``Bool`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:102
+msgid "Logic"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:107
+#: ../../SpinalHDL/Data types/bool.rst:187
+#: ../../SpinalHDL/Data types/bool.rst:243
+#: ../../SpinalHDL/Data types/bool.rst:270
+#: ../../SpinalHDL/Data types/bool.rst:304
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:109
+#: ../../SpinalHDL/Data types/bool.rst:189
+#: ../../SpinalHDL/Data types/bool.rst:245
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:110
+msgid "!x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:111
+#: ../../SpinalHDL/Data types/bool.rst:125
+msgid "Logical NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:0
+msgid "x && y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:0
+msgid "x & y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:115
+msgid "Logical AND"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:0
+msgid "x || y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:0
+msgid "x | y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:119
+msgid "Logical OR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:121
+msgid "x ^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:122
+msgid "Logical XOR"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:124
+msgid "~x"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:127
+msgid "x.set[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:128
+msgid "Set x to True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:129
+#: ../../SpinalHDL/Data types/bool.rst:132
+msgid "Unit (none)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:130
+msgid "x.clear[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:131
+msgid "Set x to False"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:133
+msgid "x.setWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:134
+msgid "Set x when cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:136
+msgid "x.clearWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:137
+msgid "Clear x when cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:139
+msgid "x.riseWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:140
+msgid "Set x when x is False and cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:142
+msgid "x.fallWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:143
+msgid "Clear x when x is True and cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:173
+msgid "Edge detection"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:175
+msgid "All edge detection functions will instantiate an additional register via :ref:`RegNext <regnext>` to get a delayed value of the ``Bool`` in question."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:178
+msgid "This feature does not reconfigure a D-type Flip-Flop to use an alternative CLK source, it uses two D-type Flip-Flop in series chain (with both CLK pins inheriting the default ClockDomain).  It has combinational logic to perform edge detection based on the output Q states."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:190
+msgid "x.edge[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:191
+msgid "Return True when x changes state"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:193
+msgid "x.edge(initAt: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:194
+msgid "Same as x.edge but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:196
+msgid "x.rise[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:197
+msgid "Return True when x was low at the last cycle and is now high"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:199
+msgid "x.rise(initAt: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:200
+msgid "Same as x.rise but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:202
+msgid "x.fall[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:203
+msgid "Return True when x was high at the last cycle and is now low"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:205
+msgid "x.fall(initAt: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:206
+msgid "Same as x.fall but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:208
+msgid "x.edges[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:209
+msgid "Return a bundle (rise, fall, toggle)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:210
+#: ../../SpinalHDL/Data types/bool.rst:213
+msgid "BoolEdges"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:211
+msgid "x.edges(initAt: Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:212
+msgid "Same as x.edges but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:214
+msgid "x.toggle[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:215
+msgid "Return True at every edge"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:238
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:246
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:247
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:249
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:250
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:265
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:273
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:274
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:275
+msgid "Bits(1 bit)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:276
+msgid "x.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:277
+msgid "Binary cast to UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:278
+msgid "UInt(1 bit)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:279
+msgid "x.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:280
+msgid "Binary cast to SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:281
+msgid "SInt(1 bit)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:282
+msgid "x.asUInt(bitCount)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:283
+msgid "Binary cast to UInt and resize, putting Bool value in LSB and padding with zeros."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:285
+msgid "UInt(bitCount bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:286
+msgid "x.asBits(bitCount)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:287
+msgid "Binary cast to Bits and resize, putting Bool value in LSB and padding with zeros."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:289
+msgid "Bits(bitCount bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:299
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:307
+msgid "x ## y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:308
+msgid "Concatenate, x->high, y->low"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:309
+msgid "Bits(w(x) + w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:310
+msgid "x #* n"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:311
+msgid "Repeat x n-times"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:312
+msgid "Bits(n bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:324
+msgid "MaskedBoolean"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bool.rst:326
+msgid "A masked boolean allows don’t care values. They are usually not used on their own but through :ref:`MaskedLiteral <maskedliteral>`."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/bundle.pot b/source/locale/gettext/SpinalHDL/Data types/bundle.pot
new file mode 100644
index 00000000000..ad2161a378e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/bundle.pot	
@@ -0,0 +1,198 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/bundle.rst:5
+msgid "Bundle"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:8
+#: ../../SpinalHDL/Data types/bundle.rst:64
+#: ../../SpinalHDL/Data types/bundle.rst:97
+#: ../../SpinalHDL/Data types/bundle.rst:121
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:10
+msgid "The ``Bundle`` is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:12
+msgid "A ``Bundle`` can be used to model data structures, buses, and interfaces."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:15
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:17
+msgid "The syntax to declare a bundle is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:27
+msgid "For example, a bundle holding a color could be defined as:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:35
+msgid "You can find an :ref:`APB3 definition <example_apb3>` among the :ref:`Spinal HDL examples <example_list>`."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:38
+msgid "Conditional signals"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:39
+msgid "The signals in the ``Bundle`` can be defined conditionally. Unless ``dataWidth`` is greater than 0, there will be no ``data`` signal in elaborated ``myBundle``, as demonstrated in the example below."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:50
+msgid "See also :ref:`generate <generate>` for information about this SpinalHDL method."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:53
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:55
+msgid "The following operators are available for the ``Bundle`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:58
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:63
+#: ../../SpinalHDL/Data types/bundle.rst:96
+#: ../../SpinalHDL/Data types/bundle.rst:120
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:65
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:66
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:67
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:68
+#: ../../SpinalHDL/Data types/bundle.rst:71
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:69
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:70
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:91
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:98
+#: ../../SpinalHDL/Data types/bundle.rst:122
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:99
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:100
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:101
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:108
+msgid "The elements of the bundle will be mapped into place in the order in which they are defined, LSB first. Thus, ``r`` in ``color1`` will occupy bits 0 to 8 of ``myBits`` (LSB), followed by ``g`` and ``b`` in that order, with ``b.msb`` also being the MSB of the resulting Bits type."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:113
+msgid "Convert Bits back to Bundle"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:114
+msgid "The ``.assignFromBits`` operator can be viewed as the reverse of ``.asBits``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:123
+msgid "x.assignFromBits(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:124
+msgid "Convert Bits (y) to Bundle(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:125
+#: ../../SpinalHDL/Data types/bundle.rst:128
+msgid "Unit"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:126
+msgid "x.assignFromBits(y, hi, lo)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:127
+msgid "Convert Bits (y) to Bundle(x) with high/low boundary"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:130
+msgid "The following example saves a Bundle called CommonDataBus into a circular buffer (3rd party memory), reads the Bits out later and converts them back to CommonDataBus format."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:162
+msgid "IO Element direction"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:164
+msgid "When you define a ``Bundle`` inside the IO definition of your component, you need to specify its direction."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:167
+msgid "in/out"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:169
+msgid "If all elements of your bundle go in the same direction you can use ``in(MyBundle())`` or ``out(MyBundle())``."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:171
+#: ../../SpinalHDL/Data types/bundle.rst:190
+msgid "For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:181
+msgid "master/slave"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:183
+msgid "If your interface obeys to a master/slave topology, you can use the ``IMasterSlave`` trait. Then you have to implement the function ``def asMaster(): Unit`` to set the direction of each element from the master's perspective. Then you can use the ``master(MyBundle())`` and ``slave(MyBundle())`` syntax in the IO definition."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/bundle.rst:185
+msgid "There are functions defined as toXXX, such as the ``toStream`` method of the ``Flow`` class. These functions can usually be called by the master side. In addition, the fromXXX functions are designed for the slave side. It is common that there are more functions available for the master side than for the slave side."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/enum.pot b/source/locale/gettext/SpinalHDL/Data types/enum.pot
new file mode 100644
index 00000000000..771f7a0233f
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/enum.pot	
@@ -0,0 +1,237 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/enum.rst:5
+msgid "SpinalEnum"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:8
+#: ../../SpinalHDL/Data types/enum.rst:48
+#: ../../SpinalHDL/Data types/enum.rst:122
+#: ../../SpinalHDL/Data types/enum.rst:189
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:10
+msgid "The ``Enumeration`` type corresponds to a list of named values."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:13
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:15
+msgid "The declaration of an enumerated data type is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:23
+msgid "For the example above, the default encoding is used. The native enumeration type is used for VHDL and a binary encoding is used for Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:26
+msgid "The enumeration encoding can be forced by defining the enumeration as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:35
+msgid "If you want to define an enumeration as in/out for a given component, you have to do as following: ``in(MyEnum())`` or ``out(MyEnum())``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:38
+#: ../../SpinalHDL/Data types/enum.rst:46
+msgid "Encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:40
+msgid "The following enumeration encodings are supported:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:47
+msgid "Bit width"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:49
+msgid "``native``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:51
+msgid "Use the VHDL enumeration system, this is the default encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:52
+msgid "``binarySequential``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:53
+#: ../../SpinalHDL/Data types/enum.rst:60
+msgid "``log2Up(stateCount)``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:54
+msgid "Use Bits to store states in declaration order (value from 0 to n-1)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:55
+msgid "``binaryOneHot``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:56
+msgid "stateCount"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:57
+msgid "Use Bits to store state. Each bit corresponds to one state, only one bit is set at a time in the hardware encoded state representation."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:59
+msgid "``graySequential``"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:61
+msgid "Encode index (numbers as if using ``binarySequential``) as binary gray code."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:63
+msgid "Custom encodings can be performed in two different ways: static or dynamic."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:93
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:95
+msgid "Instantiate an enumerated signal and assign a value to it:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:111
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:113
+msgid "The following operators are available for the ``Enumeration`` type:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:116
+msgid "Comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:121
+#: ../../SpinalHDL/Data types/enum.rst:188
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:123
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:124
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:125
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:126
+#: ../../SpinalHDL/Data types/enum.rst:129
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:127
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:128
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:154
+msgid "Types"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:156
+msgid "In order to use your enums, for example in a function, you may need its type."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:158
+msgid "The value type (e.g. sIdle’s type) is"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:164
+#: ../../SpinalHDL/Data types/enum.rst:176
+msgid "or equivalently"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:170
+msgid "The bundle type (e.g. stateNext’s type) is"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:183
+msgid "Type cast"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:190
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:191
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:192
+msgid "Binary cast to Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:193
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:194
+msgid "x.asBits.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:195
+msgid "Binary cast to UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:196
+msgid "UInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:197
+msgid "x.asBits.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:198
+msgid "Binary cast to SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:199
+msgid "SInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:200
+msgid "e.assignFromBits(bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:201
+msgid "Bits cast to enum"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/enum.rst:202
+msgid "MyEnum()"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Data types/index.pot b/source/locale/gettext/SpinalHDL/Data types/index.pot
new file mode 100644
index 00000000000..0121efbf261
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Data types/index.pot	
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Data types/index.rst:5
+msgid "Data types"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:7
+msgid "The language provides 5 base types, and 2 composite types that can be used."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:9
+msgid "Base types: :ref:`Bool <Bool>` , :ref:`Bits <Bits>` , :ref:`UInt <Int>` for unsigned integers, :ref:`SInt <Int>` for signed integers and :ref:`Enum <Enum>`."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:10
+msgid "Composite types: :ref:`Bundle <Bundle>` and :ref:`Vec <Vec>`."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:15
+msgid "In addition to the base types, Spinal has support under development for:"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:17
+msgid ":ref:`Fixed-point <fixed>` numbers (partial support)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:18
+msgid ":ref:`Auto-range Fixed-point <afix>` numbers (add,sub,mul support)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:19
+msgid ":ref:`Floating-point <Floating>` numbers (experimental support)"
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:22
+msgid "Additionaly, if you want to assign a don't care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:31
+msgid "Finally, a special type is available for checking equality between a BitVector and a bit constant pattern that contains holes defined like a bitmask (bit positions not to be compared by the equality expression)."
+msgstr ""
+
+#: ../../SpinalHDL/Data types/index.rst:34
+msgid "Here is an example to show how you can achieve this (note the use of 'M' prefix) :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/assignment_overlap.pot b/source/locale/gettext/SpinalHDL/Design errors/assignment_overlap.pot
new file mode 100644
index 00000000000..7664698a348
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/assignment_overlap.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:3
+msgid "Assignment overlap"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:8
+msgid "SpinalHDL will check that no signal assignment completely erases a previous one."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:13
+msgid "The following code"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:23
+msgid "will throw the following error:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:32
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/assignment_overlap.rst:44
+msgid "But in the case when you really want to override the previous assignment (as there are times when overriding makes sense), you can do the following:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/clock_crossing_violation.pot b/source/locale/gettext/SpinalHDL/Design errors/clock_crossing_violation.pot
new file mode 100644
index 00000000000..f34dbaa7de7
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/clock_crossing_violation.pot	
@@ -0,0 +1,85 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:3
+msgid "Clock crossing violation"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:8
+msgid "SpinalHDL will check that every register of your design only depends (through combinational logic paths) on registers which use the same or a synchronous clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:13
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:28
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:42
+msgid "There are multiple possible fixes, listed below:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:44
+msgid ":ref:`crossClockDomain tags <crossclockdomain-tag>`"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:45
+msgid ":ref:`setSynchronousWith method <setsynchronouswith>`"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:46
+msgid ":ref:`BufferCC type <buffercc>`"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:51
+msgid "crossClockDomain tag"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:53
+msgid "The ``crossClockDomain`` tag can be used to communicate \"It's alright, don't panic about this specific clock crossing\" to the SpinalHDL compiler."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:72
+msgid "setSynchronousWith"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:74
+msgid "You can also specify that two clock domains are synchronous together by using the ``setSynchronousWith`` method of one of the ``ClockDomain`` objects."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:94
+msgid "BufferCC"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:96
+msgid "When exchanging single-bit signals (such as ``Bool`` types), or Gray-coded values, you can use ``BufferCC`` to safely cross different ``ClockDomain`` regions."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:99
+msgid "Do not use ``BufferCC`` with multi-bit signals, as there is a risk of corrupted reads on the receiving side if the clocks are asynchronous. See the :ref:`Clock Domains <clock_domain>` page for more details."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/combinatorial_loop.pot b/source/locale/gettext/SpinalHDL/Design errors/combinatorial_loop.pot
new file mode 100644
index 00000000000..d2fcea48158
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/combinatorial_loop.pot	
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:3
+msgid "Combinatorial loop"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:8
+msgid "SpinalHDL will check that there are no combinatorial loops in the design."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:13
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:29
+msgid "will throw :"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:47
+msgid "A possible fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:64
+msgid "False-positives"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:66
+msgid "It should be said that SpinalHDL's algorithm to detect combinatorial loops can be pessimistic, and it may give false positives. If it is giving a false positive, you can manually disable loop checking on one signal of the loop like so:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:77
+msgid "could be fixed by :"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/combinatorial_loop.rst:87
+msgid "It should also be said that assignments such as ``(a(1) := a(0))`` can make some tools like `Verilator <https://www.veripool.org/wiki/verilator>`_ unhappy. It may be better to use a ``Vec(Bool(), 8)`` in this case."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/hierarchy_violation.pot b/source/locale/gettext/SpinalHDL/Design errors/hierarchy_violation.pot
new file mode 100644
index 00000000000..bd06551792a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/hierarchy_violation.pot	
@@ -0,0 +1,78 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:3
+msgid "Hierarchy violation"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:8
+msgid "SpinalHDL will check that signals are never accessed outside of the current component's scope."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:10
+msgid "The following signals can be read inside a component:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:12
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:18
+msgid "All directionless signals defined in the current component"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:13
+msgid "All in/out/inout signals of the current component"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:14
+msgid "All in/out/inout signals of child components"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:16
+msgid "In addition, the following signals can be assigned to inside of a component:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:19
+msgid "All out/inout signals of the current component"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:20
+msgid "All in/inout signals of child components"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:22
+msgid "If a ``HIERARCHY VIOLATION`` error appears, it means that one of the above rules was violated."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:25
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:27
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:40
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/hierarchy_violation.rst:49
+msgid "A fix could be :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/index.pot b/source/locale/gettext/SpinalHDL/Design errors/index.pot
new file mode 100644
index 00000000000..575ba1b7a3a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/index.pot	
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/index.rst:3
+msgid "Design errors"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:5
+msgid "The SpinalHDL compiler will perform many checks on your design to be sure that the generated VHDL/Verilog will be safe for simulation and synthesis. Basically, it should not be possible to generate a broken VHDL/Verilog design. Below is a non-exhaustive list of SpinalHDL checks:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:9
+msgid "Assignment overlapping"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:10
+msgid "Clock crossing"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:11
+msgid "Hierarchy violation"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:12
+msgid "Combinatorial loops"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:13
+msgid "Latches"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:14
+msgid "Undriven signals"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:15
+msgid "Width mismatch"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:16
+msgid "Unreachable switch statements"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/index.rst:18
+msgid "On each SpinalHDL error report, you will find a stack trace, which can be useful to accurately find out where the design error is. These design checks may look like overkill at first glance, but they becomes invaluable as soon as you start to move away from the traditional way of doing hardware description."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/iobundle.pot b/source/locale/gettext/SpinalHDL/Design errors/iobundle.pot
new file mode 100644
index 00000000000..d807ac709b2
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/iobundle.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:3
+msgid "IO bundle"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:8
+msgid "SpinalHDL will check that each ``io`` bundle contains only in/out/inout signals. Other kinds of signals are called directionless signals."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:12
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:14
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:24
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:33
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:43
+msgid "But if for meta hardware description reasons you really want ``io.a`` to be directionless, you can do:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/latch_detected.pot b/source/locale/gettext/SpinalHDL/Design errors/latch_detected.pot
new file mode 100644
index 00000000000..0b299037ace
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/latch_detected.pot	
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:3
+msgid "Latch detected"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:8
+msgid "SpinalHDL will check that no combinational signals will infer a latch during synthesis. In other words, this is a check that no combinational signals are partially assigned."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:12
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:14
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:27
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:36
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:51
+msgid "Due to mux"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:53
+msgid "Another reason for a latch being detected is often a non-exhaustive ``mux``/``muxList`` statement with a missing default:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:64
+msgid "which can be fixed by adding the missing case (or a default case):"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/latch_detected.rst:74
+msgid "In e.g. width generic code it is often a better solution to use ``muxListDc`` as this will not generate an error for those cases were a default is not needed:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/no_driver_on.pot b/source/locale/gettext/SpinalHDL/Design errors/no_driver_on.pot
new file mode 100644
index 00000000000..de37d9eb67c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/no_driver_on.pot	
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:3
+msgid "No driver on"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:8
+msgid "SpinalHDL will check that all combinational signals which have an impact on the design are assigned by something."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:13
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:23
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/no_driver_on.rst:32
+msgid "A fix could be:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/nullpointerexception.pot b/source/locale/gettext/SpinalHDL/Design errors/nullpointerexception.pot
new file mode 100644
index 00000000000..5d27c6236c5
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/nullpointerexception.pot	
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:5
+msgid "NullPointerException"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:8
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:10
+msgid "``NullPointerException`` is a Scala runtime reported error which can happen when a variable is accessed before it has been initialized."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:13
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:15
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:24
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:33
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:43
+msgid "Issue explanation"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:45
+msgid "SpinalHDL is not a language, it is a Scala library, which means that it obeys the same rules as the Scala general purpose programming language."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/nullpointerexception.rst:47
+msgid "When running the above SpinalHDL hardware description to generate the corresponding VHDL/Verilog RTL, the SpinalHDL hardware description will be executed as a Scala program, and ``a`` will be a null reference until the program executes ``val a = UInt(8 bits)``, so trying to assign to it before then will result in a ``NullPointerException``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/out_of_range_constant.pot b/source/locale/gettext/SpinalHDL/Design errors/out_of_range_constant.pot
new file mode 100644
index 00000000000..08b71326565
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/out_of_range_constant.pot	
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:3
+msgid "Out of Range Constant"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:8
+msgid "SpinalHDL checks that in comparisons with literals the literal is not wider than the value compared to."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:13
+msgid "For example the following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:20
+msgid "Will result in the following error:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:30
+msgid "Specifying exceptions"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:32
+msgid "In some cases, because of the design parametrization, it can make sense to compare a value to a larger constant and get a statically known ``True/False`` result."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:34
+msgid "You have the option to specifically whitelist one instance of a comparison with an out of range constant."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/out_of_range_constant.rst:42
+msgid "Alternatively, you can allow comparisons to out of range constants for the whole design."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/register_defined_as_component_input.pot b/source/locale/gettext/SpinalHDL/Design errors/register_defined_as_component_input.pot
new file mode 100644
index 00000000000..193d241f2c2
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/register_defined_as_component_input.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:3
+msgid "Register defined as component input"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:8
+msgid "In SpinalHDL, you are not allowed to define a component that has a register as an input. The reasoning behind this is to prevent surprises when the user tries to drive the inputs of child components with the registered signal. If a registered input is desired, you will need to declare the unregistered input in the ``io`` bundle, and register the signal in the body of the component."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:13
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:15
+msgid "The following code :"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:25
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:34
+msgid "A fix could be :"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/register_defined_as_component_input.rst:44
+msgid "If a registered ``a`` is required, it can be done like so:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/scope_violation.pot b/source/locale/gettext/SpinalHDL/Design errors/scope_violation.pot
new file mode 100644
index 00000000000..85b79f497f9
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/scope_violation.pot	
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:3
+msgid "Scope violation"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:8
+msgid "SpinalHDL will check that there are no signals assigned outside the scope they are defined in. This error isn't easy to trigger as it requires some specific meta hardware description tricks."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:12
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:14
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:28
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/scope_violation.rst:37
+msgid "A fix could be:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/spinal_cant_clone.pot b/source/locale/gettext/SpinalHDL/Design errors/spinal_cant_clone.pot
new file mode 100644
index 00000000000..2599b630554
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/spinal_cant_clone.pot	
@@ -0,0 +1,66 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:3
+msgid "Spinal can't clone class"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:8
+msgid "This error happens when SpinalHDL wants to create a new datatype instance via the ``cloneOf`` function but isn't able to do it. The reason for this is nearly always because it can't retrieve the construction parameters of a ``Bundle``."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:12
+msgid "Example 1"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:14
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:54
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:27
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:39
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:52
+msgid "Example 2"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:72
+msgid "raises an exeption:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:78
+msgid "In this case, a solution is to override the clone function to propagate the implicit parameter."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:90
+msgid "We need to clone the hardware element, not the eventually assigned value in it."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:94
+msgid "An alternative is to used :ref:`ScopeProperty <scopeproperty>`."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/unassigned_register.pot b/source/locale/gettext/SpinalHDL/Design errors/unassigned_register.pot
new file mode 100644
index 00000000000..bf6f8ad4160
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/unassigned_register.pot	
@@ -0,0 +1,58 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:3
+msgid "Unassigned register"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:8
+msgid "SpinalHDL will check that all registers which impact the design have been assigned somewhere."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:13
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:23
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:59
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:32
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:44
+msgid "Register with only init"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:46
+msgid "In some cases, because of the design parameterization, it could make sense to generate a register which has no assignment but only an ``init`` statement."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unassigned_register.rst:68
+msgid "To fix it, you can ask SpinalHDL to transform the register into a combinational one if no assignment is present but it has an ``init`` statement:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/unreachable_is_statement.pot b/source/locale/gettext/SpinalHDL/Design errors/unreachable_is_statement.pot
new file mode 100644
index 00000000000..7a941b21c77
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/unreachable_is_statement.pot	
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:3
+msgid "Unreachable is statement"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:8
+msgid "SpinalHDL will check to ensure that all ``is`` statements in a ``switch`` are reachable."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:11
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:13
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:29
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/unreachable_is_statement.rst:38
+msgid "A fix could be:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Design errors/width_mismatch.pot b/source/locale/gettext/SpinalHDL/Design errors/width_mismatch.pot
new file mode 100644
index 00000000000..655501e965d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Design errors/width_mismatch.pot	
@@ -0,0 +1,52 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:3
+msgid "Width mismatch"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:8
+msgid "SpinalHDL will check that operators and signals on the left and right side of assignments have the same widths."
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:11
+msgid "Assignment example"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:13
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:45
+msgid "The following code:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:23
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:55
+msgid "will throw:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:32
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:67
+msgid "A fix could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Design errors/width_mismatch.rst:43
+msgid "Operator example"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/bus_slave_factory_impl.pot b/source/locale/gettext/SpinalHDL/Developers area/bus_slave_factory_impl.pot
new file mode 100644
index 00000000000..661ce457565
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/bus_slave_factory_impl.pot	
@@ -0,0 +1,356 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:7
+msgid "Bus Slave Factory Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:12
+msgid "This page will document the implementation of the BusSlaveFactory tool and one of those variant. You can get more information about the functionality of that tool :ref:`here <bus_slave_factory>`."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:15
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:17
+msgid "The class diagram is the following :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:23
+msgid "The ``BusSlaveFactory`` abstract class define minimum requirements that each implementation of it should provide :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:29
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:52
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:30
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:54
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:340
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:31
+msgid "busDataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:32
+msgid "Return the data width of the bus"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:33
+msgid "read(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:34
+msgid "When the bus read the ``address``\\ , fill the response with ``that`` at ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:35
+msgid "write(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:36
+msgid "When the bus write the ``address``\\ , assign ``that`` with bus's data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:37
+msgid "onWrite(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:38
+msgid "Call ``doThat`` when a write transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:39
+msgid "onRead(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:40
+msgid "Call ``doThat`` when a read transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:41
+msgid "nonStopWrite(that,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:42
+msgid "Permanently assign ``that`` by the bus write data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:45
+msgid "By using them the ``BusSlaveFactory`` should also be able to provide many utilities :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:53
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:55
+msgid "readAndWrite(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:57
+msgid "Make ``that`` readable and writable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:58
+msgid "readMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "Create the memory mapping to read ``that`` from 'address'. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "If ``that`` is bigger than one word it extends the register on followings addresses"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:62
+msgid "writeMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "Create the memory mapping to write ``that`` at 'address'. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:66
+msgid "createWriteOnly(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:67
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:70
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:68
+msgid "Create a write only register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:69
+msgid "createReadWrite(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:71
+msgid "Create a read write register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:72
+msgid "createAndDriveFlow(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:73
+msgid "Flow[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:74
+msgid "Create a writable Flow register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:75
+msgid "drive(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:77
+msgid "Drive ``that`` with a register writable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:78
+msgid "driveAndRead(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:80
+msgid "Drive ``that`` with a register writable and readable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:81
+msgid "driveFlow(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:83
+msgid "Emit on ``that`` a transaction when a write happen at ``address`` by using data placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "readStreamNonBlocking(that,address,"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "validBitOffset,payloadBitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "Read ``that`` and consume the transaction when a read happen at ``address``."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "valid <= validBitOffset bit"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "doBitsAccumulationAndClearOnRead"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "Instantiate an internal register which at each cycle do :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "reg := reg | that"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:0
+msgid "Then when a read occur, the register is cleared. This register is readable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:98
+msgid "About ``BusSlaveFactoryDelayed``, it's still an abstract class, but it capture each primitives (BusSlaveFactoryElement) calls into a data-model. This datamodel is one list that contain all primitives, but also a HashMap that link each address used to a list of primitives that are using it. Then when they all are collected (at the end of the current component), it do a callback that should be implemented by classes that extends it. The implementation of this callback should implement the hardware corresponding to all primitives collected."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:101
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:104
+msgid "BusSlaveFactory"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:106
+msgid "Let's describe primitives abstract function :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:133
+msgid "Then let's operate the magic to implement all utile based on them :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:246
+msgid "BusSlaveFactoryDelayed"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:248
+msgid "Let's implement classes that will be used to store primitives :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:279
+msgid "Then let's implement the ``BusSlaveFactoryDelayed`` itself :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:330
+msgid "AvalonMMSlaveFactory"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:332
+msgid "First let's implement the companion object that provide the compatible AvalonMM configuration object that correspond to the following table :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:338
+msgid "Pin name"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:339
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:341
+msgid "read"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:342
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:345
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:354
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:343
+msgid "High one cycle to produce a read request"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:344
+msgid "write"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:346
+msgid "High one cycle to produce a write request"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:347
+msgid "address"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:348
+msgid "UInt(addressWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:349
+msgid "Byte granularity but word aligned"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:350
+msgid "writeData"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:351
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:357
+msgid "Bits(dataWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:353
+msgid "readDataValid"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:355
+msgid "High to respond a read command"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:356
+msgid "readData"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:358
+msgid "Valid when readDataValid is high"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:378
+msgid "Then, let's implement the AvalonMMSlaveFactory itself."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:429
+msgid "Conclusion"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:431
+msgid "That's all, you can check one example that use this ``Apb3SlaveFactory`` to create an Apb3UartCtrl :ref:`here <memory_mapped_uart>`."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:433
+msgid "If you want to add the support of a new memory bus, it's very simple you just need to implement another variation of the ``BusSlaveFactoryDelayed`` trait. The ``Apb3SlaveFactory`` is probably a good starting point :D"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/howtodocument.pot b/source/locale/gettext/SpinalHDL/Developers area/howtodocument.pot
new file mode 100644
index 00000000000..48026a82eb9
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/howtodocument.pot	
@@ -0,0 +1,117 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:2
+msgid "How to HACK this documentation"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:3
+msgid "If you want to add your page to this documentation you need to add your source file in the appropriate section. I opted to create a structure that resample the various section of the documentation, this is not strictly necessary, but for clarity sake, highly encourage."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:8
+msgid "This documentation uses a recursive index tree: every folder have a special ``index.rst`` files that tell sphinx which file, and in what order to put it in the documentation tree."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:12
+msgid "Title convention"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:13
+msgid "Sphinx is very smart, the document structure is deduced from how you use non alphanumerical characters (like:  ``= - ` : ' \" ~ ^ _ * + # < >``), you only need to be consistent. Still, for consistency sakes we use this progression:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:17
+msgid "``=`` over and underline for section titles"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:18
+msgid "``=`` underline for titles"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:19
+msgid "``-`` underline for paragraph"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:20
+msgid "``^`` for subparagraph"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:23
+msgid "Wavedrom integration"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:24
+msgid "This documentation makes use of the ``sphinxcontrib-wavedrom`` plugin, So you can specify a timing diagram, or a register description with the WaveJSON_ syntax like so:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:44
+msgid "and you get:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:62
+msgid "if you want the Wavedrom diagram to be present in the pdf export, you need to use the \"non relaxed\" JSON dialect. long story short, no javascript code and use ``\"`` around key value (Eg. ``\"name\"``)."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:65
+msgid "you can describe register mapping with the same syntax:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:88
+msgid "New section"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:89
+msgid "if you want to add a new  section you need to specify in the top index, the index file of the new section. I suggest to name the folder like the section name, but is not required; Sphinx will take the name of the section from the title of the index file."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:94
+msgid "example"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:95
+msgid "I want to document the new feature in SpinalHDL, and I want to create a section for it; let's call it ``Cheese``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:97
+msgid "So I need to create a folder named ``Cheese`` (name is not important), and in it create a index file like:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:112
+msgid "The ``.. toctree::`` directive accept some parameters, in this case ``:glob:`` makes so you can use the ``*`` to include all the remaining files."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:116
+msgid "The file path is relative to the index file, if you want to specify the absolute path, you need to prepend ``/``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:119
+msgid "``introduction.rst`` will be always the first on the list because it's specified in the index file. Other files will be included in alphabetical order."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:122
+msgid "Now I can add the ``introduction.rst`` and other files like ``cheddar.rst``, ``stilton.rst``, etc."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:124
+msgid "The only thing remaining to do is to add cheese to the top index file like so:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:151
+msgid "that's it, now you can add all you want in cheese and all pages will show up in the documentation."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/index.pot b/source/locale/gettext/SpinalHDL/Developers area/index.pot
new file mode 100644
index 00000000000..f982c6b950d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/index.rst:3
+msgid "Developers area"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/mill support.pot b/source/locale/gettext/SpinalHDL/Developers area/mill support.pot
new file mode 100644
index 00000000000..b2e036284b8
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/mill support.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:2
+msgid "Build through Mill"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:4
+msgid "SpinalHDL itself can be built with Mill.  This is an alternative to the Sbt build tool that can be found at Introduction_to_Mill_. It can compile/test/publishLocal the existing modules. Build through mill can be much faster than Sbt, which is useful while debugging."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:10
+msgid "Compile the library"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:18
+msgid "Run all test suites"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:26
+msgid "Run a specified test suite"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:34
+msgid "Run a specified App"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:42
+msgid "Publish locally"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/mill support.rst:44
+msgid "Mill can also publish the library to the local ivy2 repository as a ``dev`` version."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot b/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot
new file mode 100644
index 00000000000..70788c52252
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot	
@@ -0,0 +1,193 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:3
+msgid "SpinalHDL internal datamodel"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:12
+msgid "This page provides documentation on the internal data structure utilized by SpinalHDL for storing and modifying the netlist described by users via the SpinalHDL API."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:15
+msgid "General structure"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:17
+msgid "The following diagrams follow the UML nomenclature :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:19
+msgid "A link with a white arrow mean \"base extend target\""
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:20
+msgid "A link with a black diamond mean \"base contains target\""
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:21
+msgid "A link with a white diamond mean \"base has a reference to target\""
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:22
+msgid "The * symbol mean \"multiple\""
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:24
+msgid "The majority of the data structures are stored using double-linked lists, which facilitate the insertion and removal of elements."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:26
+msgid "There is a diagram of the global data structure :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:31
+msgid "And here more details about the `Statement` class :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:36
+msgid "In general, when an element within the data model utilizes other expressions or statements, that element typically includes functions for iterating over these usages. For example, each Expression is equipped with a *foreachExpression* function."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:38
+msgid "When using these iteration functions, you have the option to remove the current element from the tree."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:40
+msgid "Additionally, as a side note, while the *foreachXXX* functions iterate only one level deep, there are often corresponding *walkXXX* functions that perform recursive iteration. For instance, using *myExpression.walkExpression* on *((a+b)+c)+d* will traverse the entire tree of addition operations."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:42
+msgid "There are also utilities like *myExpression.remapExpressions(Expression => Expression),* which iterate through all the expressions used within *myExpression* and replace them with the one you provide."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44
+msgid "More generaly, most of the graph checks and transformations done by SpinalHDL are located in <https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala>"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47
+msgid "Exploring the datamodel"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:49
+msgid "Here is an example that identifies all adders within the netlist without utilizing shortcuts. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:109
+msgid "Which will produces :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:127
+msgid "Please note that in many cases, shortcuts are available. All the recursive processes mentioned earlier could have been replaced by a single one. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:141
+msgid "Compilation Phases"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:143
+msgid "Here is the complete list of default phases, arranged in order, that are employed to modify, check, and generate Verilog code from a top-level component. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:145
+msgid "<https://github.com/SpinalHDL/SpinalHDL/blob/ec8cd9f513566b43cbbdb08d0df4dee1f0fee655/core/src/main/scala/spinal/core/internals/Phase.scala#L2487>"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:147
+msgid "If you, as a user, add a new compilation phase by using *SpinalConfig.addTransformationPhase(new MyPhase())*, this phase will be inserted immediately after the user component elaboration process, which is relatively early in the compilation sequence. During this phase, you can still make use of the complete SpinalHDL user API to introduce elements into the netlist."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:149
+msgid "If you choose to use the SpinalConfig.phasesInserters API, it's essential to exercise caution and ensure that any modifications made to the netlist align with the phases that have already been executed. For instance, if you insert your phase after the *PhaseInferWidth*, you must specify the width of each node you introduce."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:152
+msgid "Modifying a netlist as a user without plugins"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:154
+msgid "There are several user APIs that enable you to make modifications during the user elaboration phase. :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:156
+msgid "mySignal.removeAssignments : Will remove all previous `:=` affecting the given signal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:157
+msgid "mySignal.removeStatement : Will void the existance of the signal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:158
+msgid "mySignal.setAsDirectionLess : Will turn a in / out signal into a internal signal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:159
+msgid "mySignal.setName : Enforce a given name on a signal (there is many other variants)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:160
+msgid "mySubComponent.mySignal.pull() : Will provide a readable copy of the given signal, even if that signal is somewhere else in the hierarchy"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:161
+msgid "myComponent.rework\\{ myCode \\} : Execute `myCode` in the context of `myComponent`, allowing modifying it with the user API"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:163
+msgid "For example, the following code can be used to modify a top-level component by adding a three-stage shift register to each input and output of the component. This is particularly useful for synthesis testing."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:187
+msgid "You can use the code in the following manner: :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:193
+msgid "Here is a function that enables you to execute the body code as if the current component's context did not exist. This can be particularly useful for defining new signals without the influence of the current conditional scope (such as when or switch)."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:223
+msgid "This kind of functionality is, for instance, employed in the VexRiscv pipeline to dynamically create components or elements as needed."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:226
+msgid "User space netlist analysis"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:228
+msgid "The SpinalHDL data model is also accessible and can be read during user-time elaboration. Here's an example that can help find the shortest logical path (in terms of clock cycles) to traverse a list of signals. In this specific case, it is being used to analyze the latency of the VexRiscv FPU design."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:242
+msgid "Here you can find the implementation of that LatencyAnalysis tool : <https://github.com/SpinalHDL/SpinalHDL/blob/3b87c898cb94dc08456b4fe2b1e8b145e6c86f63/lib/src/main/scala/spinal/lib/Utils.scala#L620>"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:247
+msgid "Enumerating every ClockDomain in use"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:249
+msgid "In this case, this is accomplished after the elaboration process by utilizing the SpinalHDL report."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:285
+msgid "Will print out"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Developers area/types.pot b/source/locale/gettext/SpinalHDL/Developers area/types.pot
new file mode 100644
index 00000000000..b0dbb3c4eef
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Developers area/types.pot	
@@ -0,0 +1,1191 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Developers area/types.rst:3
+msgid "Types"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:12
+msgid "The language provides 5 base types and 2 composite types that can be used."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:15
+msgid "Base types : ``Bool``, ``Bits``, ``UInt`` for unsigned integers, ``SInt`` for signed integers, ``Enum``."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:16
+msgid "Composite types : Bundle, Vec."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:22
+msgid "Those types and their usage (with examples) are explained hereafter."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:24
+msgid "Fixed point support is documented :ref:`Fixed-Point <fixed>`"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:27
+#: ../../SpinalHDL/Developers area/types.rst:45
+#: ../../SpinalHDL/Developers area/types.rst:48
+#: ../../SpinalHDL/Developers area/types.rst:51
+#: ../../SpinalHDL/Developers area/types.rst:54
+#: ../../SpinalHDL/Developers area/types.rst:79
+#: ../../SpinalHDL/Developers area/types.rst:83
+#: ../../SpinalHDL/Developers area/types.rst:87
+#: ../../SpinalHDL/Developers area/types.rst:90
+#: ../../SpinalHDL/Developers area/types.rst:99
+#: ../../SpinalHDL/Developers area/types.rst:102
+#: ../../SpinalHDL/Developers area/types.rst:105
+#: ../../SpinalHDL/Developers area/types.rst:108
+#: ../../SpinalHDL/Developers area/types.rst:111
+#: ../../SpinalHDL/Developers area/types.rst:114
+#: ../../SpinalHDL/Developers area/types.rst:240
+#: ../../SpinalHDL/Developers area/types.rst:249
+#: ../../SpinalHDL/Developers area/types.rst:258
+#: ../../SpinalHDL/Developers area/types.rst:261
+#: ../../SpinalHDL/Developers area/types.rst:270
+#: ../../SpinalHDL/Developers area/types.rst:273
+#: ../../SpinalHDL/Developers area/types.rst:276
+#: ../../SpinalHDL/Developers area/types.rst:363
+#: ../../SpinalHDL/Developers area/types.rst:366
+#: ../../SpinalHDL/Developers area/types.rst:369
+#: ../../SpinalHDL/Developers area/types.rst:372
+#: ../../SpinalHDL/Developers area/types.rst:709
+#: ../../SpinalHDL/Developers area/types.rst:712
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:29
+msgid "This is the standard *boolean* type that corresponds to a single bit."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:32
+#: ../../SpinalHDL/Developers area/types.rst:420
+msgid "Declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:34
+msgid "The syntax to declare such as value is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:40
+#: ../../SpinalHDL/Developers area/types.rst:130
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:41
+#: ../../SpinalHDL/Developers area/types.rst:75
+#: ../../SpinalHDL/Developers area/types.rst:131
+#: ../../SpinalHDL/Developers area/types.rst:157
+#: ../../SpinalHDL/Developers area/types.rst:180
+#: ../../SpinalHDL/Developers area/types.rst:224
+#: ../../SpinalHDL/Developers area/types.rst:315
+#: ../../SpinalHDL/Developers area/types.rst:350
+#: ../../SpinalHDL/Developers area/types.rst:397
+#: ../../SpinalHDL/Developers area/types.rst:421
+#: ../../SpinalHDL/Developers area/types.rst:434
+#: ../../SpinalHDL/Developers area/types.rst:664
+#: ../../SpinalHDL/Developers area/types.rst:705
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:42
+#: ../../SpinalHDL/Developers area/types.rst:132
+#: ../../SpinalHDL/Developers area/types.rst:225
+#: ../../SpinalHDL/Developers area/types.rst:316
+#: ../../SpinalHDL/Developers area/types.rst:351
+#: ../../SpinalHDL/Developers area/types.rst:398
+#: ../../SpinalHDL/Developers area/types.rst:435
+#: ../../SpinalHDL/Developers area/types.rst:706
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:43
+msgid "Bool()"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:44
+msgid "Create a Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:46
+msgid "True"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:47
+msgid "Create a Bool assigned with ``true``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:49
+msgid "False"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:50
+msgid "Create a Bool assigned with ``false``"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:52
+msgid "Bool(value : Boolean)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:53
+msgid "Create a Bool assigned with a Scala Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:57
+msgid "Using this type into SpinalHDL yields:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:66
+#: ../../SpinalHDL/Developers area/types.rst:217
+msgid "Operators"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:68
+msgid "The following operators are available for the ``Bool`` type"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:74
+#: ../../SpinalHDL/Developers area/types.rst:223
+#: ../../SpinalHDL/Developers area/types.rst:314
+#: ../../SpinalHDL/Developers area/types.rst:349
+#: ../../SpinalHDL/Developers area/types.rst:396
+#: ../../SpinalHDL/Developers area/types.rst:433
+#: ../../SpinalHDL/Developers area/types.rst:704
+msgid "Operator"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:76
+msgid "Return type"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:77
+msgid "!x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:78
+msgid "Logical NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "x && y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+#: ../../SpinalHDL/Developers area/types.rst:229
+msgid "x & y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:82
+msgid "Logical AND"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "x || y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+#: ../../SpinalHDL/Developers area/types.rst:232
+msgid "x | y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:86
+msgid "Logical OR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:88
+#: ../../SpinalHDL/Developers area/types.rst:235
+msgid "x ^ y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:89
+msgid "Logical XOR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:91
+msgid "x.set[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:92
+msgid "Set x to True"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:94
+msgid "x.clear[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:95
+msgid "Set x to False"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:97
+msgid "x.rise[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:98
+msgid "Return True when x was low at the last cycle and is now high"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:100
+msgid "x.rise(initAt : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:101
+msgid "Same as x.rise but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:103
+msgid "x.fall[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:104
+msgid "Return True when x was high at the last cycle and is now low"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:106
+msgid "x.fall(initAt : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:107
+msgid "Same as x.fall but with a reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:109
+msgid "x.setWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:110
+msgid "Set x when cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:112
+msgid "x.clearWhen(cond)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:113
+msgid "Clear x when cond is True"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:118
+msgid "The BitVector family - (``Bits``, ``UInt``, ``SInt``)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:120
+msgid "``BitVector`` is a family of types for storing multiple bits of information in a single value. This type has three subtypes that can be used to model different behaviours:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:121
+msgid "``Bits`` do not convey any sign information whereas the ``UInt`` (unsigned integer) and ``SInt`` (signed integer) provide the required operations to compute correct results if signed / unsigned arithmetic is used."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:124
+msgid "Declaration syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:133
+msgid "Bits/UInt/SInt [()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:134
+msgid "Create a BitVector, bits count is inferred"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:135
+#: ../../SpinalHDL/Developers area/types.rst:138
+#: ../../SpinalHDL/Developers area/types.rst:141
+#: ../../SpinalHDL/Developers area/types.rst:144
+#: ../../SpinalHDL/Developers area/types.rst:147
+msgid "Bits/UInt/SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:136
+msgid "Bits/UInt/SInt(x bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:137
+msgid "Create a BitVector with x bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:139
+msgid "B/U/S(value : Int[,width : BitCount])"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:140
+#: ../../SpinalHDL/Developers area/types.rst:143
+msgid "Create a BitVector assigned with 'value'"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:142
+msgid "B/U/S\"[[size']base]value\""
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:145
+msgid "B/U/S([x bits], element, ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:146
+msgid "Create a BitVector assigned with the value specified by elements (see the table below)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:150
+msgid "Elements could be defined as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:156
+msgid "Element syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:158
+msgid "x : Int -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:159
+msgid "Set bit x with y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:160
+msgid "x : Range -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:161
+msgid "Set each bits in range x with y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:162
+#: ../../SpinalHDL/Developers area/types.rst:167
+msgid "x : Range -> y : T"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+#: ../../SpinalHDL/Developers area/types.rst:163
+#: ../../SpinalHDL/Developers area/types.rst:168
+msgid "Set bits in range x with y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:164
+msgid "x : Range -> y : String"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "The string format follows the same rules as B/U/S\"xyz\" one"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:169
+msgid "default -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "Set all unconnected bits with the y value."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "This feature can only be used to do assignments without the U/B/S prefix"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:174
+msgid "You can define a Range values"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:179
+msgid "Range syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:181
+msgid "Width"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:182
+msgid "(x downto y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:183
+msgid "[x:y] x >= y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:184
+msgid "x-y+1"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:185
+msgid "(x to y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:186
+msgid "[x:y] x <= y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:187
+msgid "y-x+1"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:188
+msgid "(x until y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:189
+msgid "[x:y[ x < y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:190
+msgid "y-x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:226
+msgid "~x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:227
+msgid "Bitwise NOT"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:228
+#: ../../SpinalHDL/Developers area/types.rst:322
+#: ../../SpinalHDL/Developers area/types.rst:378
+msgid "T(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:230
+msgid "Bitwise AND"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:231
+#: ../../SpinalHDL/Developers area/types.rst:234
+#: ../../SpinalHDL/Developers area/types.rst:237
+#: ../../SpinalHDL/Developers area/types.rst:354
+#: ../../SpinalHDL/Developers area/types.rst:357
+#: ../../SpinalHDL/Developers area/types.rst:724
+msgid "T(max(w(x), w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:233
+msgid "Bitwise OR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:236
+msgid "Bitwise XOR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:238
+#: ../../SpinalHDL/Developers area/types.rst:436
+msgid "x(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:239
+msgid "Read bitfield, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:241
+msgid "x(hi,lo)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:242
+msgid "Read bitfield, hi : Int, lo : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:243
+#: ../../SpinalHDL/Developers area/types.rst:252
+#: ../../SpinalHDL/Developers area/types.rst:733
+msgid "T(hi-lo+1 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:244
+msgid "x(offset,width)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:245
+msgid "Read bitfield, offset: UInt, width: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:246
+#: ../../SpinalHDL/Developers area/types.rst:255
+#: ../../SpinalHDL/Developers area/types.rst:736
+msgid "T(width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:247
+#: ../../SpinalHDL/Developers area/types.rst:439
+msgid "x(y) := z"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:248
+msgid "Assign bits, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:250
+msgid "x(hi,lo) := z"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:251
+#: ../../SpinalHDL/Developers area/types.rst:732
+msgid "Assign bitfield, hi : Int, lo : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:253
+msgid "x(offset,width) := z"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:254
+#: ../../SpinalHDL/Developers area/types.rst:735
+msgid "Assign bitfield, offset: UInt, width: Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:256
+msgid "x.msb"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:257
+msgid "Return the most significant bit"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:259
+msgid "x.lsb"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:260
+msgid "Return the least significant bit"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:262
+msgid "x.range"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:263
+msgid "Return the range (x.high downto 0)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:264
+msgid "Range"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:265
+msgid "x.high"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:266
+msgid "Return the upper bound of the type x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:267
+#: ../../SpinalHDL/Developers area/types.rst:715
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:268
+msgid "x.xorR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:269
+msgid "XOR all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:271
+msgid "x.orR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:272
+msgid "OR all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:274
+msgid "x.andR"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:275
+msgid "AND all bits of x"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:277
+msgid "x.clearAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:278
+msgid "Clear all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:279
+#: ../../SpinalHDL/Developers area/types.rst:282
+#: ../../SpinalHDL/Developers area/types.rst:438
+#: ../../SpinalHDL/Developers area/types.rst:739
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:280
+msgid "x.setAll[()]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:281
+msgid "Set all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:283
+msgid "x.setAllTo(value : Boolean)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:284
+msgid "Set all bits to the given Boolean value"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:286
+msgid "x.setAllTo(value : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:287
+msgid "Set all bits to the given Bool value"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:289
+msgid "x.asBools"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:290
+msgid "Cast into an array of Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:291
+msgid "Vec(Bool(),width(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:295
+msgid "Masked comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:297
+msgid "Sometimes you need to check equality between a ``BitVector`` and a bits constant that contain holes defined as a bitmask (bit positions not to be compared by the equality expression)."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:300
+msgid "An example demonstrating how to do that (note the use of 'M' prefix) :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:308
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:317
+#: ../../SpinalHDL/Developers area/types.rst:320
+#: ../../SpinalHDL/Developers area/types.rst:373
+#: ../../SpinalHDL/Developers area/types.rst:376
+msgid "x >> y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:318
+msgid "Logical shift right, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:319
+#: ../../SpinalHDL/Developers area/types.rst:375
+msgid "T(w(x) - y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:321
+msgid "Logical shift right, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:323
+#: ../../SpinalHDL/Developers area/types.rst:326
+#: ../../SpinalHDL/Developers area/types.rst:379
+#: ../../SpinalHDL/Developers area/types.rst:382
+msgid "x << y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:324
+msgid "Logical shift left, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:325
+#: ../../SpinalHDL/Developers area/types.rst:381
+msgid "T(w(x) + y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:327
+msgid "Logical shift left, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:328
+#: ../../SpinalHDL/Developers area/types.rst:384
+msgid "T(w(x) + max(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:329
+msgid "x.rotateLeft(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:330
+msgid "Logical left rotation, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:331
+msgid "T(w(x))"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:332
+#: ../../SpinalHDL/Developers area/types.rst:385
+msgid "x.resize(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:333
+msgid "Return a resized copy of x, filled with zero bits as necessary at the MSB to widen, may also truncate width retaining at the LSB side, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:335
+#: ../../SpinalHDL/Developers area/types.rst:339
+#: ../../SpinalHDL/Developers area/types.rst:387
+msgid "T(y bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:336
+msgid "x.resizeLeft(y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:337
+msgid "Return a resized copy of x, filled with zero bits as necessary at the LSB to widen, may also truncate width retraining at the MSB side, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:343
+msgid "UInt, SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:352
+msgid "x + y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:353
+msgid "Addition"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:355
+msgid "x - y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:356
+msgid "Subtraction"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:358
+msgid "x * y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:359
+msgid "Multiplication"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:360
+msgid "T(w(x) + w(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:361
+msgid "x > y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:362
+msgid "Greater than"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:364
+msgid "x >= y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:365
+msgid "Greater than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:367
+msgid "x < y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:368
+msgid "Less than"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:370
+msgid "x <= y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:371
+msgid "Less than or equal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:374
+msgid "Arithmetic shift right, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:377
+msgid "Arithmetic shift right, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:380
+msgid "Arithmetic shift left, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:383
+msgid "Arithmetic shift left, y : UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:386
+msgid "Return an arithmetic resized copy of x, y : Int"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:391
+msgid "Bool, Bits, UInt, SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:399
+#: ../../SpinalHDL/Developers area/types.rst:725
+msgid "x.asBits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:400
+msgid "Binary cast in Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:401
+msgid "Bits(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:402
+msgid "x.asUInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:403
+msgid "Binary cast in UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:404
+msgid "UInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:405
+msgid "x.asSInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:406
+msgid "Binary cast in SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:407
+msgid "SInt(w(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:408
+msgid "x.asBool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:409
+msgid "Binary cast in Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:410
+msgid "Bool(x.lsb)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:414
+msgid "Vec"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:422
+msgid "Vec(type : Data, size : Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:423
+msgid "Create a vector of size time the given type"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:424
+msgid "Vec(x,y,..)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "Create a vector where indexes point to given elements."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:0
+msgid "this construct supports mixed element width"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:437
+msgid "Read element y, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:440
+msgid "Assign element y with z, y : Int/UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:460
+msgid "Bundle"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:462
+msgid "Bundles could be used to model data structure line buses and interfaces."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:463
+msgid "All attributes that extends Data (Bool, Bits, UInt, ...) that are defined inside the bundle are considered as part of the bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:466
+msgid "Simple example (RGB/VGA)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:468
+msgid "The following example show an RGB bundle definition with some internal function."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:484
+msgid "Then you can also incorporate a Bundle inside Bundle as deeply as you want:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:494
+msgid "And finaly instantiate your Bundles inside the hardware :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:504
+msgid "If you want to specify your bundle as an input or an output of a Component, you have to do it by the following way :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:518
+msgid "Interface example (APB)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:520
+msgid "If you want to define an interface, let's imagine an APB interface, you can also use bundles :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:546
+msgid "One good practice is to group all construction parameters inside a configuration class. This could make the parametrization much easier later in your components, especially if you have to reuse the same configuration at multiple places. Also if one time you need to add another construction parameter, you will only have to add it into the configuration class and everywhere this one is instantiated:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:573
+msgid "Then at some points, you will probably need to use the APB bus as master or as slave interface of some components. To do that you can define some functions :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:611
+msgid "Then to make that better, the spinal.lib integrates a small master slave utility named IMasterSlave. When a bundle extends IMasterSlave, it should implement/override the asMaster function. It give you the ability to setup a master or a slave interface in a smoother way :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:622
+msgid "An example of an APB bus that implement this IMasterSlave :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:654
+msgid "Enum"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:656
+msgid "SpinalHDL supports enumeration with some encodings :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:662
+msgid "Encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:663
+msgid "Bit width"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:665
+msgid "native"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:667
+msgid "Use the VHDL enumeration system, this is the default encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:668
+msgid "binarySequancial"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:669
+msgid "log2Up(stateCount)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:670
+msgid "Use Bits to store states in declaration order (value from 0 to n-1)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:671
+msgid "binaryOneHot"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:672
+msgid "stateCount"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:673
+msgid "Use Bits to store state. Each bit position corresponds to one state, only one bit is active at a time when encoded."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:677
+msgid "Define an enumeration type:"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:685
+msgid "Instantiate a signal to store the enumeration encoded value and assign it a value :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:697
+msgid "Data (Bool, Bits, UInt, SInt, Enum, Bundle, Vec)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:699
+msgid "All hardware types extends the Data class, which mean that all of them provide following operators :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:707
+msgid "x === y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:708
+msgid "Equality"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:710
+msgid "x =/= y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:711
+msgid "Inequality"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:713
+msgid "x.getWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:714
+msgid "Return bitcount"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:716
+msgid "x ## y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:717
+msgid "Concatenate, x->high, y->low"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:718
+msgid "Bits(width(x) + width(y) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:719
+msgid "Cat(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:720
+msgid "Concatenate list, first element on lsb, x : Array[Data]"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:721
+msgid "Bits(sumOfWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:722
+msgid "Mux(cond,x,y)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:723
+msgid "if cond ? x : y"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:726
+msgid "Cast in Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:727
+msgid "Bits(width(x) bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:728
+msgid "x.assignFromBits(bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:729
+msgid "Assign from Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:731
+msgid "x.assignFromBits(bits,hi,lo)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:734
+msgid "x.assignFromBits(bits,offset,width)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:737
+msgid "x.getZero"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:738
+msgid "Get equivalent type assigned with zero"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:743
+msgid "Literals as signal declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:745
+msgid "Literals are generally use as a constant value. But you can also use them to do two things in a single one :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:748
+msgid "Define a wire which is assigned with a constant value"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:749
+msgid "Setup inferred type: UInt(4 bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:750
+msgid "Clock cycles where `cond =/= True` will result in the constant being reinstated"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:751
+msgid "Clock cycles where `cond === True` will result in the signal having the value of `red` due to the last statement wins rule."
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:754
+msgid "An example :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:770
+msgid "Continuous Assignment Literals as signal declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:772
+msgid "You can also use them in expressions to do three things at once :"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:774
+msgid "Define a wire"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:775
+msgid "Maintain the result of an equality operation in the hardware logic implementation with the constant value and another signal"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:777
+msgid "Setup inferred type: Bool due to use of === equality operator having a result of type Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Developers area/types.rst:780
+msgid "There is an example :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/index.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/index.pot
new file mode 100644
index 00000000000..73e4fd5b47f
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/index.rst:3
+msgid "Advanced ones"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/jtag.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/jtag.pot
new file mode 100644
index 00000000000..05201ddb2e1
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/jtag.pot	
@@ -0,0 +1,182 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:3
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:60
+msgid "JTAG TAP"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:9
+msgid "The goal of this page is to show the implementation of a JTAG TAP (a slave) by a non-conventional way."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:0
+msgid "This implementation is not a simple one, it mix object oriented programming, abstract interfaces decoupling, hardware generation and hardware description."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:0
+msgid "Of course a simple JTAG TAP implementation could be done only with a simple hardware description, but the goal here is really to going forward and creating an very reusable and extensible JTAG TAP generator"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:16
+msgid "This page will not explain how JTAG works. A good tutorial can be found `there <https://www.fpga4fun.com/JTAG.html>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:18
+msgid "One big difference between commonly used HDL and Spinal, is the fact that SpinalHDL allow you to define hardware generators/builders. It's very different than describing hardware. Let's take a look into the example bellow because the difference between generate/build/describing could seem \"playing with word\" or could be interpreted differently."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:21
+msgid "The example bellow is a JTAG TAP which allow the JTAG master to read ``switchs``\\ /\\ ``keys`` inputs and write ``leds`` outputs. This TAP could also be recognized by a master by using the UID 0x87654321."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:28
+msgid "As you can see, a JtagTap is created but then some Generator/Builder functions (idcode,read,write) are called to create each JTAG instruction. This is what i call \"Hardware generator/builder\", then these Generator/Builder are used by the user to describing an hardware. And there is the point, in commonly HDL you can only describe your hardware, which imply many donkey job."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:30
+msgid "This JTAG TAP tutorial is based on `this <https://github.com/SpinalHDL/SpinalHDL/tree/master/lib/src/main/scala/spinal/lib/com/jtag>`_ implementation."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:35
+msgid "JTAG bus"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:37
+msgid "First we need to define a JTAG bus bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:44
+msgid "As you can see this bus don't contain the TCK pin because it will be provided by the clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:47
+msgid "JTAG state machine"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:49
+msgid "Let's define the JTAG state machine as explained `here <https://www.fpga4fun.com/JTAG2.html>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:57
+msgid "The ``randBoot()`` on ``state`` make it initialized with a random state. It's only for simulation purpose."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:62
+msgid "Let's implement the core of the JTAG TAP, without any instruction, just the base manage the instruction register (IR) and the bypass."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:71
+msgid "Ignore the reference to `with JTagTapAccess` for now, it will be explained further down."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:74
+msgid "Jtag instructions"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:76
+msgid "Now that the JTAG TAP core is done, we can think about how to implement JTAG instructions by an reusable way."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:79
+msgid "JTAG TAP class interface"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:81
+msgid "First we need to define how an instruction could interact with the JTAG TAP core. We could of course directly take the JtagTap area, but it's not very nice because is some situation the JTAG TAP core is provided by another IP (Altera virtual JTAG for example)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:83
+msgid "So let's define a simple and abstract interface between the JTAG TAP core and instructions :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:91
+msgid "Then let the ``JtagTap`` implement this abstract interface:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:93
+msgid "Additions to ``class JtagTap``"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:102
+msgid "Base class"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:104
+msgid "Let's define a useful base class for JTAG instruction that provide some callback (doCapture/doShift/doUpdate/doReset) depending the selected instruction and the state of the JTAG TAP :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:0
+msgid "About the Component.current.addPrePopTask(...) :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:0
+msgid "This allows you to call the given code at the end of the current component construction. Because of object oriented nature of JtagInstruction, doCapture, doShift, doUpdate and doReset should not be called before children classes construction (because children classes will use it as a callback to do some logic)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:116
+msgid "Read instruction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:118
+msgid "Let's implement an instruction that allow the JTAG to read a signal."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:126
+msgid "Write instruction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:128
+msgid "Let's implement an instruction that allow the JTAG to write a register (and also read its current value)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:136
+msgid "Idcode instruction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:138
+msgid "Let's implement the instruction that return a idcode to the JTAG and also, when a reset occur, set the instruction register (IR) to it own instructionId."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:146
+msgid "User friendly wrapper"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:148
+msgid "Let's add some user friendly function to the JtagTapAccess to make instructions instantiation easier ."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:150
+msgid "Additions to ``trait JtagTapAccess``"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:159
+msgid "Usage demonstration"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:161
+msgid "And there we are, we can now very easily create an application specific JTAG TAP without having to write any logic or any interconnections."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/jtag.rst:168
+msgid "This way of doing things (Generating hardware) could also be applied to, for example, generating an APB/AHB/AXI bus slave."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.pot
new file mode 100644
index 00000000000..1e8ee9f163b
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.pot	
@@ -0,0 +1,180 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:4
+msgid "Memory mapped UART"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:9
+msgid "This example will take the ``UartCtrl`` component implemented in the previous :ref:`example <example_uart>` to create a memory mapped UART controller."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:12
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:14
+msgid "The implementation will be based on the APB3 bus with a RX FIFO."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:16
+msgid "Here is the register mapping table:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:22
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:23
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:24
+msgid "Access"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:25
+msgid "Address"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:26
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:27
+msgid "clockDivider"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:28
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:29
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:34
+msgid "RW"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:30
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:31
+msgid "Set the UartCtrl clock divider"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:32
+msgid "frame"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:33
+msgid "UartCtrlFrameConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:35
+msgid "4"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:36
+msgid "Set the dataLength, the parity and the stop bit configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:37
+msgid "writeCmd"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:38
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:39
+msgid "W"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:40
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:45
+msgid "8"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:41
+msgid "Send a write command to UartCtrl"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:42
+msgid "writeBusy"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:43
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:44
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:49
+msgid "R"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:46
+msgid "Bit 0 => zero when a new writeCmd can be sent"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:47
+msgid "read"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:48
+msgid "Bool / Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:50
+msgid "12"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:0
+msgid "Bits 7 downto 0 => rx payload"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:0
+msgid "Bit 31 => rx payload valid"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:56
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:58
+msgid "For this implementation, the Apb3SlaveFactory tool will be used. It allows you to define a APB3 slave with a nice syntax. You can find the documentation of this tool :ref:`there <bus_slave_factory>`."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:60
+msgid "First, we just need to define the ``Apb3Config`` that will be used for the controller. It is defined in a Scala object as a function to be able to get it from everywhere."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:67
+msgid "Then we can define a ``Apb3UartCtrl`` component which instantiates a ``UartCtrl`` and creates the memory mapping logic between it and the APB3 bus:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:0
+msgid "Yes, that's all it takes. It's also synthesizable."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:0
+msgid "The Apb3SlaveFactory tool is not something hard-coded into the SpinalHDL compiler. It's something implemented with SpinalHDL regular hardware description syntax."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/pinesec.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/pinesec.pot
new file mode 100644
index 00000000000..71d54c24ec0
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/pinesec.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/pinesec.rst:2
+msgid "Pinesec"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/pinesec.rst:4
+msgid "Remember to add it"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot
new file mode 100644
index 00000000000..fffd21cc8b9
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot	
@@ -0,0 +1,65 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:4
+msgid "Slots"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:9
+msgid "Let's say you have some hardware which has to keep track of multiple similar ongoing activities, you may want to implement an array of \"slots\" to do so. This example show how to do it using Area, OHMasking.first, onMask and reader."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:13
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:15
+msgid "This implementation avoid the use of Vec. Instead, it use Area which allow to mix signal, registers and logic definitions in each slot."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17
+msgid "Note that the `reader` API is for SpinalHDL version comming after 1.9.1"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24
+msgid "In practice"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:26
+msgid "For instance, this kind of slot pattern is used in Tilelink coherency hub to keep track of all ongoing memory probes in flight:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:28
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30
+msgid "As well in the DRAM / SDR / DDR memory controller to implement the handeling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:34
+msgid "As well in the NaxRiscv (out of order CPU) load-store-unit to handle the store-queue / load-queue hardware (a bit too scary to show here in the doc XD)"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot
new file mode 100644
index 00000000000..4ded58d7a91
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot	
@@ -0,0 +1,349 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:4
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:12
+msgid "Timer"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:9
+msgid "A timer module is probably one of the most basic pieces of hardware. But even for a timer, there are some interesting things that you can do with SpinalHDL. This example will define a simple timer component which integrates a bus bridging utile."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:14
+msgid "So let's start with the ``Timer`` component."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:17
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:84
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:19
+msgid "The ``Timer`` component will have a single construction parameter:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:25
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:92
+msgid "Parameter Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:26
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:41
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:93
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:27
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:42
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:94
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:120
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:28
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:135
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:142
+msgid "width"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:29
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:30
+msgid "Specify the bit width of the timer counter"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:33
+msgid "And also some inputs/outputs:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:39
+msgid "IO Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:40
+msgid "Direction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:43
+msgid "tick"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:44
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:48
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:52
+msgid "in"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:45
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:49
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:57
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:46
+msgid "When ``tick`` is True, the timer count up until ``limit``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:47
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:146
+msgid "clear"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:50
+msgid "When ``tick`` is True, the timer is set to zero. ``clear`` has priority over ``tick``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:51
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:133
+msgid "limit"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:53
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:61
+msgid "UInt(width bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:54
+msgid "When the timer value is equal to ``limit``\\ , the ``tick`` input is inhibited."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:55
+msgid "full"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:56
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:60
+msgid "out"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:58
+msgid "``full`` is high when the timer value is equal to ``limit`` and ``tick`` is high."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:59
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:140
+msgid "value"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:62
+msgid "Wire out the timer counter value."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:66
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:155
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:75
+msgid "Bridging function"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:77
+msgid "Now we can start with the main purpose of this example: defining a bus bridging function. To do that we will use two techniques:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:80
+msgid "Using the ``BusSlaveFactory`` tool documented :ref:`here <bus_slave_factory>`"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:81
+msgid "Defining a function inside the ``Timer`` component which can be called from the parent component to drive the ``Timer``\\ 's IO in an abstract way."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:86
+msgid "This bridging function will take the following parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:95
+msgid "busCtrl"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:96
+msgid "BusSlaveFactory"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:97
+msgid "The ``BusSlaveFactory`` instance that will be used by the function to create the bridging logic."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:98
+msgid "baseAddress"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:99
+msgid "BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:100
+msgid "The base address where the bridging logic should be mapped."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:101
+msgid "ticks"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:102
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:105
+msgid "Seq[Bool]"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:103
+msgid "A list of Bool sources that can be used as a tick signal."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:104
+msgid "clears"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:106
+msgid "A list of Bool sources that can be used as a clear signal."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:109
+msgid "The register mapping assumes that the bus system is 32 bits wide:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:115
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:116
+msgid "Access"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:117
+msgid "Width"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:118
+msgid "Address offset"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:119
+msgid "Bit offset"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:121
+msgid "ticksEnable"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:122
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:128
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:134
+msgid "RW"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:123
+msgid "len(ticks)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:124
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:125
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:130
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:137
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:144
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:126
+msgid "Each ``ticks`` bool can be actived if the corresponding ``ticksEnable`` bit is high."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:127
+msgid "clearsEnable"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:129
+msgid "len(clears)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:131
+msgid "16"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:132
+msgid "Each ``clears`` bool can be actived if the corresponding ``clearsEnable`` bit is high."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:136
+msgid "4"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:0
+msgid "Access the limit value of the timer component."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:0
+msgid "When this register is written to, the timer is cleared."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:141
+msgid "R"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:143
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:149
+msgid "8"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:145
+msgid "Access the value of the timer."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:147
+msgid "W"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:151
+msgid "When this register is written to, it clears the timer."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:157
+msgid "Let's add this bridging function inside the ``Timer`` component."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:167
+msgid "Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:169
+msgid "Here is some demonstration code which is very close to the one used in the Pinsec SoC timer module. Basically it instantiates following elements:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:171
+msgid "One 16 bit prescaler"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:172
+msgid "One 32 bit timer"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:173
+msgid "Three 16 bit timers"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:175
+msgid "Then by using an ``Apb3SlaveFactory`` and functions defined inside the ``Timer``\\ s, it creates bridging logic between the APB3 bus and all instantiated components."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/fractal.pot b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/fractal.pot
new file mode 100644
index 00000000000..4d47b7cbfd1
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/fractal.pot	
@@ -0,0 +1,160 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:2
+msgid "Fractal calculator"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:5
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:7
+msgid "This example will show a simple implementation (without optimization) of a Mandelbrot fractal calculator by using data streams and fixed point calculations."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:10
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:12
+msgid "The component will receive one ``Stream`` of pixel tasks (which contain the XY coordinates in the Mandelbrot space) and will produce one ``Stream`` of pixel results (which contain the number of iterations done for the corresponding task)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:14
+msgid "Let's specify the IO of our component:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:20
+msgid "IO Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:21
+msgid "Direction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:22
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:41
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:58
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:23
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:42
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:59
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:24
+msgid "cmd"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:25
+msgid "slave"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:26
+msgid "Stream[PixelTask]"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:27
+msgid "Provide XY coordinates to process"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:28
+msgid "rsp"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:29
+msgid "master"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:30
+msgid "Stream[PixelResult]"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:31
+msgid "Return iteration count needed for the corresponding cmd transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:34
+msgid "Let's specify the PixelTask ``Bundle``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:40
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:57
+msgid "Element Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:43
+msgid "x"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:44
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:47
+msgid "SFix"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:45
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:48
+msgid "Coordinate in the Mandelbrot space"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:46
+msgid "y"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:51
+msgid "Let's specify the PixelResult ``Bundle``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:60
+msgid "iteration"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:61
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:62
+msgid "Number of iterations required to solve the Mandelbrot coordinates"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:66
+msgid "Elaboration parameters (Generics)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:68
+msgid "Let's define the class that will provide construction parameters of our system:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:76
+msgid "iterationType and fixType are functions that you can call to instantiate new signals. It's like a typedef in C."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:79
+msgid "Bundle definition"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:87
+msgid "Component implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/fractal.rst:89
+msgid "And now the implementation. The one below is a very simple one without pipelining / multi-threading."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/index.pot b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/index.pot
new file mode 100644
index 00000000000..c6d7d4dd901
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/index.rst:3
+msgid "Intermediates ones"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/uart.pot b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/uart.pot
new file mode 100644
index 00000000000..bc2e47ae478
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/uart.pot	
@@ -0,0 +1,388 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:4
+msgid "UART"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:7
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:9
+msgid "This UART controller tutorial is based on `this <https://github.com/SpinalHDL/SpinalHDL/tree/master/lib/src/main/scala/spinal/lib/com/uart>`_ implementation."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:11
+msgid "This implementation is characterized by:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:14
+msgid "ClockDivider/Parity/StopBit/DataLength configs are set by the component inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:15
+msgid "RXD input is filtered by using a sampling window of N samples and a majority vote."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:18
+msgid "Interfaces of this UartCtrl are:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:24
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:53
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:133
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:218
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:25
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:54
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:134
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:219
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:26
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:55
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:135
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:220
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:27
+msgid "config"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:28
+msgid "UartCtrlConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:29
+msgid "Give all configurations to the controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:30
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:142
+msgid "write"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:31
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:143
+msgid "Stream[Bits]"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:32
+msgid "Port used by the system to give transmission order to the controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:33
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:227
+msgid "read"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:34
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:228
+msgid "Flow[Bits]"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:35
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:229
+msgid "Port used by the controller to notify the system about a successfully received frame"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:36
+msgid "uart"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:37
+msgid "Uart"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:38
+msgid "Uart interface with rxd / txd"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:42
+msgid "Data structures"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:44
+msgid "Before implementing the controller itself we need to define some data structures."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:47
+msgid "Controller construction parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:56
+msgid "dataWidthMax"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:57
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:60
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:63
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:66
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:69
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:58
+msgid "Maximum number of data bits that could be sent using a single UART frame"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:59
+msgid "clockDividerWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:61
+msgid "Number of bits that the clock divider has"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:62
+msgid "preSamplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:64
+msgid "Number of samples to drop at the beginning of the sampling window"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:65
+msgid "samplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:67
+msgid "Number of samples use at the middle of the window to get the filtered RXD value"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:68
+msgid "postSamplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:70
+msgid "Number of samples to drop at the end of the sampling window"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:73
+msgid "To make the implementation easier let's assume that ``preSamplingSize + samplingSize + postSamplingSize`` is always a power of two. If so we can skip resetting counters in a few places."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:76
+msgid "Instead of adding each construction parameters (generics) to ``UartCtrl`` one by one, we can group them inside a class that will be used as single parameter of ``UartCtrl``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:84
+msgid "UART interface"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:86
+msgid "Let's define a UART interface bundle without flow control."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:95
+msgid "UART configuration enums"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:97
+msgid "Let's define parity and stop bit enumerations."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:105
+msgid "UartCtrl configuration Bundles"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:107
+msgid "Let's define bundles that will be used as IO elements to setup ``UartCtrl``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:115
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:117
+msgid "In ``UartCtrl``\\ , 3 things will be instantiated:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:120
+msgid "One clock divider that generates a tick pulse at the UART RX sampling rate."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:121
+msgid "One ``UartCtrlTx`` component"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:122
+msgid "One ``UartCtrlRx`` component"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:125
+msgid "UartCtrlTx"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:127
+msgid "The interfaces of this ``Component`` are the following :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:136
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:221
+msgid "configFrame"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:137
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:222
+msgid "UartCtrlFrameConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:138
+msgid "Contains data bit width count and party/stop bits configurations"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:139
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:224
+msgid "samplingTick"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:140
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:146
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:225
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:231
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:141
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:226
+msgid "Time reference that pulses ``rxSamplePerBit`` times per UART baud"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:144
+msgid "Port used by the system to give transmission orders to the controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:145
+msgid "txd"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:147
+msgid "UART txd pin"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:150
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:235
+msgid "Let's define the enumeration that will be used to store the state of ``UartCtrlTx``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:158
+msgid "Let's define the skeleton of ``UartCtrlTx``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:202
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:296
+msgid "And here is the complete implementation:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:210
+msgid "UartCtrlRx"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:212
+msgid "The interfaces of this ``Component`` are the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:223
+msgid "Contains data bit width and party/stop bits configurations"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:230
+msgid "rxd"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:232
+msgid "UART rxd pin, not synchronized with the current clock domain"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:244
+msgid "Let's define the skeleton of the UartCtrlRx :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:304
+msgid "UartCtrl"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:306
+msgid "Let's write ``UartCtrl`` that instantiates the ``UartCtrlRx`` and ``UartCtrlTx`` parts, generate the clock divider logic, and connect them to each other."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:313
+msgid "To make it easier to use the UART with fixed settings, we introduce an companion object for ``UartCtrl``. It allows us to provide additional ways of instantiating a UartCtrl component with different sets of parameters. Here we define a ``UartCtrlInitConfig`` holding the settings for a component that is not runtime configurable. Note that it is still possible to instantiate the UartCtrl manually like all other components, which one would do if a runtime-configurable UART is needed (via ``val uart = new UartCtrl()``)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:325
+msgid "Simple usage"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:327
+msgid "To synthesize a ``UartCtrl`` as ``115200-N-8-1``:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:334
+msgid "If you are using ``txd`` pin only, add:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:341
+msgid "On the contrary, if you are using ``rxd`` pin only:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:349
+msgid "Example with test bench"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:351
+msgid "Here is a top level example that does the followings things:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:354
+msgid "Instantiate ``UartCtrl`` and set its configuration to 921600 baud/s, no parity, 1 stop bit."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:355
+msgid "Each time a byte is received from the UART, it writes it on the leds output."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:356
+msgid "Every 2000 cycles, it sends the switches input value to the UART."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:363
+msgid "`Here <https://github.com/SpinalHDL/SpinalHDL/blob/master/tester/src/test/resources/UartCtrlUsageExample_tb.vhd>`_ you can get a simple VHDL testbench for this small ``UartCtrlUsageExample``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:366
+msgid "Bonus: Having fun with Stream"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:368
+msgid "If you want to queue data received from the UART:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:375
+msgid "If you want to add a queue on the write interface and do some flow control:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:382
+msgid "If you want to send a 0x55 header before sending the value of switches, you can replace the write generator of the preceding example by:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot
new file mode 100644
index 00000000000..4556ebeb570
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot	
@@ -0,0 +1,261 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:2
+msgid "VGA"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:5
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:7
+msgid "VGA interfaces are becoming an endangered species, but implementing a VGA controller is still a good exercise."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:9
+msgid "An explanation about the VGA protocol can be found `here <https://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:11
+msgid "This VGA controller tutorial is based on `this <https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/graphic/vga/VgaCtrl.scala>`_ implementation."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:14
+msgid "Data structures"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:16
+msgid "Before implementing the controller itself we need to define some data structures."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:19
+msgid "RGB color"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:21
+msgid "First, we need a three channel color structure (Red, Green, Blue). This data structure will be used to feed the controller with pixels and also will be used by the VGA bus."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:29
+msgid "VGA bus"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:35
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:109
+msgid "io name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:36
+msgid "Driver"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:37
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:111
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:38
+msgid "vSync"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:39
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:42
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:45
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:48
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:128
+msgid "master"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:40
+msgid "Vertical synchronization, indicate the beginning of a new frame"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:41
+msgid "hSync"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:43
+msgid "Horizontal synchronization, indicate the beginning of a new line"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:44
+msgid "colorEn"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:46
+msgid "High when the interface is in the visible part"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:47
+msgid "color"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:49
+msgid "Carry the color, don't care when colorEn is low"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:57
+msgid "This Vga ``Bundle`` uses the ``IMasterSlave`` trait, which allows you to create master/slave VGA interfaces using the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:65
+msgid "VGA timings"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:67
+msgid "The VGA interface is driven by using 8 different timings. Here is one simple example of a ``Bundle`` that is able to carry them."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:82
+msgid "But this not a very good way to specify it because it is redundant for vertical and horizontal timings."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:84
+msgid "Let's write it in a clearer way:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:92
+msgid "Then we can add some some functions to set these timings for specific resolutions and frame rates:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:100
+msgid "VGA Controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:103
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:110
+msgid "Direction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:112
+msgid "softReset"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:113
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:116
+msgid "in"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:114
+msgid "Reset internal counters and keep the VGA interface inactive"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:115
+msgid "timings"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:117
+msgid "Specify VGA horizontal and vertical timings"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:118
+msgid "pixels"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:119
+msgid "slave"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:120
+msgid "Stream of RGB colors that feeds the VGA controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:121
+msgid "error"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:122
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:125
+msgid "out"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:123
+msgid "High when the pixels stream is too slow"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:124
+msgid "frameStart"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:126
+msgid "High when a new frame starts"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:127
+msgid "vga"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:129
+msgid "VGA interface"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:132
+msgid "The controller does not integrate any pixel buffering. It directly takes them from the ``pixels`` ``Stream`` and puts them on the ``vga.color`` out at the right time. If ``pixels`` is not valid then ``error`` becomes high for one cycle."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:135
+msgid "Component and io definition"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:137
+msgid "Let's define a new VgaCtrl ``Component``\\ , which takes as ``RgbConfig`` and ``timingsWidth`` as parameters. Let's give the bit width a default value of 12."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:146
+msgid "Horizontal and vertical logic"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148
+msgid "The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal syncronization signal as to increment."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150
+msgid "Let's define ``HVArea``\\ , which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical syncronization."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160
+msgid "As you can see, it's done by using ``Area``. This is to avoid the creation of a new ``Component`` which would have been much more verbose."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:163
+msgid "Interconnections"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:165
+msgid "Now that we have timing generators for horizontal and vertical synchronization, we need to drive the outputs."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:176
+msgid "Bonus"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:178
+msgid "The VgaCtrl that was defined above is generic (not application specific). We can imagine a case where the system provides a ``Stream`` of ``Fragment`` of RGB, which means the system transmits pixels between start/end of picture indications."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:181
+msgid "In this case we can automatically manage the ``softReset`` input by asserting it when an ``error`` occurs, then wait for the end of the current ``pixels`` picture to deassert ``error``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:183
+msgid "Let's add a function to ``VgaCtrl`` that can be called from the parent component to feed ``VgaCtrl`` by using this ``Stream`` of ``Fragment`` of RGB."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/apb3.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/apb3.pot
new file mode 100644
index 00000000000..28a575c53da
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/apb3.pot	
@@ -0,0 +1,151 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:4
+msgid "APB3 definition"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:9
+msgid "This example will show the syntax to define an APB3 ``Bundle``."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:12
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:14
+msgid "The specification from ARM could be interpreted as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:20
+msgid "Signal Name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:21
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:22
+msgid "Driver side"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:23
+msgid "Comment"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:24
+msgid "PADDR"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:25
+msgid "UInt(addressWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:26
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:30
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:34
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:38
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:42
+msgid "Master"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:27
+msgid "Address in byte"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:28
+msgid "PSEL"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:29
+msgid "Bits(selWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:31
+msgid "One bit per slave"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:32
+msgid "PENABLE"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:33
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:37
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:45
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:53
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:36
+msgid "PWRITE"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:40
+msgid "PWDATA"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:41
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:49
+msgid "Bits(dataWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:44
+msgid "PREADY"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:46
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:50
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:54
+msgid "Slave"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:48
+msgid "PRDATA"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:52
+msgid "PSLVERROR"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:55
+msgid "Optional"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:59
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:61
+msgid "This specification shows that the APB3 bus has multiple possible configurations. To represent that, we can define a configuration class in Scala:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:68
+msgid "Then we can define the APB3 ``Bundle`` which will be used to represent the bus in hardware:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:76
+msgid "Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/apb3.rst:78
+msgid "Here is a usage example of this definition:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/carry_adder.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/carry_adder.pot
new file mode 100644
index 00000000000..b9b8f181c41
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/carry_adder.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/carry_adder.rst:2
+msgid "Carry adder"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/carry_adder.rst:4
+msgid "This example defines a component with inputs ``a`` and ``b``\\ , and a ``result`` output. At any time, ``result`` will be the sum of ``a`` and ``b`` (combinatorial). This sum is manually done by a carry adder logic."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/color_summing.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/color_summing.pot
new file mode 100644
index 00000000000..43ce6a57b18
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/color_summing.pot	
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/color_summing.rst:2
+msgid "Color summing"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/color_summing.rst:4
+msgid "First let's define a Color ``Bundle`` with an addition operator."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/color_summing.rst:11
+msgid "Then let's define a component with a ``sources`` input which is a vector of colors, and a ``result`` output which is the sum of the ``sources`` input."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/counter_with_clear.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/counter_with_clear.pot
new file mode 100644
index 00000000000..25b33c10ef0
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/counter_with_clear.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/counter_with_clear.rst:2
+msgid "Counter with clear"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/counter_with_clear.rst:4
+msgid "This example defines a component with a ``clear`` input and a ``value`` output. Each clock cycle, the ``value`` output is incrementing, but when ``clear`` is high, ``value`` is cleared."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/index.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/index.pot
new file mode 100644
index 00000000000..e16d66eff4f
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/index.rst:3
+msgid "Simple ones"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/pll_resetctrl.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/pll_resetctrl.pot
new file mode 100644
index 00000000000..0b8156fd3c3
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/pll_resetctrl.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:2
+msgid "PLL BlackBox and reset controller"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:4
+msgid "Let's imagine you want to define a ``TopLevel`` component which instantiates a PLL ``BlackBox``\\ , and create a new clock domain from it which will be used by your core logic. Let's also imagine that you want to adapt an external asynchronous reset into this core clock domain to a synchronous reset source."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:6
+msgid "The following imports will be used in code examples on this page:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:14
+msgid "The PLL BlackBox definition"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:16
+msgid "This is how to define the PLL ``BlackBox``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:23
+msgid "This will correspond to the following VHDL component:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:36
+msgid "TopLevel definition"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:38
+msgid "This is how to define your ``TopLevel`` which instantiates the PLL, creates the new ``ClockDomain``\\ , and also adapts the asynchronous reset input to a synchronous reset:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/rgb_to_gray.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/rgb_to_gray.pot
new file mode 100644
index 00000000000..4ec2762993d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/rgb_to_gray.pot	
@@ -0,0 +1,88 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:2
+msgid "RGB to gray"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:4
+msgid "Let's imagine a component that converts an RGB color into a gray one, and then writes it into external memory."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:10
+msgid "io name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:11
+msgid "Direction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:12
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:13
+msgid "clear"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:14
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:17
+msgid "in"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:15
+msgid "Clear all internal registers"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:16
+msgid "r,g,b"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:18
+msgid "Color inputs"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:19
+msgid "wr"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:20
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:23
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:26
+msgid "out"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:21
+msgid "Memory write"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:22
+msgid "address"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:24
+msgid "Memory address, incrementing each cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:25
+msgid "data"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:27
+msgid "Memory data, gray level"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/Simple ones/sinus_rom.pot b/source/locale/gettext/SpinalHDL/Examples/Simple ones/sinus_rom.pot
new file mode 100644
index 00000000000..4c98dc11deb
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/Simple ones/sinus_rom.pot	
@@ -0,0 +1,110 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:4
+msgid "Sinus rom"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:6
+msgid "Let's imagine that you want to generate a sine wave and also have a filtered version of it (which is completely useless in practical, but let's do it as an example)."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:12
+msgid "Parameters name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:13
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:29
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:14
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:30
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:15
+msgid "resolutionWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:16
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:19
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:17
+msgid "Number of bits used to represent numbers"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:18
+msgid "sampleCount"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:20
+msgid "Number of samples in a sine period"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:27
+msgid "IO name"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:28
+msgid "Direction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:31
+msgid "sin"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:32
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:36
+msgid "out"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:33
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:37
+msgid "SInt(resolutionWidth bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:34
+msgid "Output which plays the sine wave"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:35
+msgid "sinFiltered"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:38
+msgid "Output which plays the filtered version of the sine"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:41
+msgid "So let's define the ``Component``\\ :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:49
+msgid "To play the sine wave on the ``sin`` output, you can define a ROM which contain all samples of a sine period (it could be just a quarter, but let's do things the most simple way). Then you can read that ROM with an phase counter and this will generate your sine wave."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:57
+msgid "Then to generate ``sinFiltered``\\ , you can for example use a first order low pass filter implementation:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Simple ones/sinus_rom.rst:64
+msgid "Here is the complete code:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Examples/index.pot b/source/locale/gettext/SpinalHDL/Examples/index.pot
new file mode 100644
index 00000000000..fb6ecf98a10
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Examples/index.pot
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/index.rst:3
+msgid "Examples"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:18
+msgid "Examples are split into three kinds:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:20
+msgid "Simple examples that could be used to get used to the basics of SpinalHDL."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:21
+msgid "Intermediate examples which implement components by using a traditional approach."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:22
+msgid "Advanced examples which go further than traditional HDL by using object-oriented programming, functional programming, and meta-hardware description."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:24
+msgid "They are all accessible in the sidebar under the corresponding sections."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:27
+msgid "The SpinalHDL workshop contains many labs with their solutions. See `here <https://github.com/SpinalHDL/SpinalWorkshop>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:30
+msgid "You can also find a list of repositories using SpinalHDL :ref:`there <users_repositories>`"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:34
+msgid "Getting started"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:35
+msgid "All examples assume that you have the following imports on the top of your scala file:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/index.rst:42
+msgid "To generate VHDL for a given component, you can place the following at the bottom of your scala file:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Foreword/index.pot b/source/locale/gettext/SpinalHDL/Foreword/index.pot
new file mode 100644
index 00000000000..3a663fc820b
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Foreword/index.pot
@@ -0,0 +1,169 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Foreword/index.rst:4
+msgid "Foreword"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:6
+msgid "Preliminary notes:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:8
+msgid "All the following statements will be about describing digital hardware. Verification is another tasty topic."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:10
+msgid "For conciseness, let's assume that SystemVerilog is a recent revision of Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:12
+msgid "When reading this, we should not underestimate how much our attachment for our favourite HDL will bias our judgement."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:17
+msgid "Why moving away from traditional HDL"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:20
+msgid "VHDL/Verilog aren't Hardware Description Languages"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:22
+msgid "Those languages are event driven languages created initially for simulation/documentation purposes. Only in a second time they were used as inputs languages for synthesis tools. Which explain the roots of a lot of the following points."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:29
+msgid "Event driven paradigm doesn't make any sense for RTL"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:31
+msgid "When you think about it, describing digital hardware (RTL) by using process/always blocks doesn't make any practical senses. Why do we have to worry about a sensitivity list? Why do we have to split our design between processes/always blocks of different natures (combinatorial logic / register without reset / register with async reset)?"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:37
+msgid "For instance, to implement this:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:42
+msgid "Using VHDL processes you write this:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:78
+msgid "Using SpinalHDL you write this:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:93
+msgid "As for everything, you can get used to this event driven semantic, until you taste something better."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:98
+msgid "Recent revisions of VHDL and Verilog aren't usable"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:100
+msgid "The EDA industry is really slow to implement VHDL 2008 and SystemVerilog synthesis capabilities in their tools. Additionally, when it's done, it appear that only a constraining subset of the language is implemented (not talking about simulation features). It result that using any interesting feature of those language revision isn't safe as:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:106
+msgid "It will probably make your code incompatible with many EDA tools."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:107
+msgid "Other companies will likely not accept your IP as their flow isn't ready for it."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:110
+msgid "Anyway, those revisions don't change the heart of those HDL issues: they are based on a event driven paradigm which doesn't make sense to describe digital hardware."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:116
+msgid "VHDL records, Verilog struct are broken (SystemVerilog is good on this, if you can use it)"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:118
+msgid "You can't use them to define an interface, because you can't define their internal signal directions. Even worst, you can't give them construction parameters! So, define your RGB record/struct once, and hope you never have to use it with bigger/smaller color channels..."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:123
+msgid "Also a fancy thing with VHDL is the fact that if you want to add an array of something into a component entity, you have to define the type of this array into a package... Which can't be parameterized..."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:127
+msgid "For instance, below is a SpinalHDL APB3 bus definition:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:159
+msgid "Then about the VHDL 2008 partial solution and the SystemVerilog interface/modport, lucky you are if your EDA tools / company flow / company policy allow you to use them."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:165
+msgid "VHDL and Verilog are so verbose"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:167
+msgid "Really, with VHDL and Verilog, when it starts to be about component instantiation interconnection, the copy-paste god has to be invoked."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:170
+msgid "To understand it more deeply, below is a SpinalHDL example performing some peripherals instantiation and adding the APB3 decoder required to access them."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:203
+msgid "Done. That's all. You don't have to bind each signal one by one when you instantiate a module/component because you can access their interfaces in a object-oriented manner."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:207
+msgid "Also about VHDL/Verilog struct/records, we can say that they are really dirty tricks, without true parameterization and reusability capabilities, trying to hide the fact that those languages were poorly designed."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:213
+msgid "Meta Hardware Description capabilities"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:215
+msgid "Basically VHDL and Verilog provide some elaboration tools which aren't directly mapped into hardware as loops / generate statements / macro / function / procedure / task. But that's all."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:219
+msgid "And even then, they are really limited. For instance, one can't define process/always/component/module blocks into a task/procedure. It is really a bottleneck for many fancy things."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:223
+msgid "With SpinalHDL you can call a user-defined task/procedure on a bus like that: ``myHandshakeBus.queue(depth=64)``. Below is some code including the definition."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:249
+msgid "Let's see further, imagine you want to define a state machine. With VHDL/Verilog you have to write a lot of raw code with some switch statements to do it. You can't define the notion of \"StateMachine\", which would give you a nice syntax to define each state. Else you can use a third-party tool to draw your state machine and then generate your VHDL/Verilog equivalent code..."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:255
+msgid "Meta-hardware description capabilities of SpinalHDL enable you to define your own tools which then allow you to define things in abstracts ways, as for state machines."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:259
+msgid "Below is an simple example of the usage of a state machine abstraction defined on the top of SpinalHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:290
+msgid "Imagine you want to generate the instruction decoding of your CPU. It could require some fancy elaboration time algorithms to generate the less logic possible. But in VHDL/Verilog, your only option to do these kind of things is to write a script which generates the ``.vhd`` and ``.v`` that you want."
+msgstr ""
+
+#: ../../SpinalHDL/Foreword/index.rst:295
+msgid "There is really much to say about meta-hardware description, but the only true way to understand it and get its real taste is to experiment it. The goal with it is to stop playing with wires and gates, to start taking some distance with that low level stuff, to think reusable."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Formal verification/index.pot b/source/locale/gettext/SpinalHDL/Formal verification/index.pot
new file mode 100644
index 00000000000..fd5c57033ab
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Formal verification/index.pot	
@@ -0,0 +1,311 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Formal verification/index.rst:3
+msgid "Formal verification"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:7
+msgid "General"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:9
+msgid "SpinalHDL allows to generate a subset of the SystemVerilog Assertions (SVA). Mostly assert, assume, cover and a few others."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:11
+msgid "In addition it provide a formal verification backend which allows to directly run the formal verification in the open-source Symbi-Yosys toolchain."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:16
+msgid "Formal backend"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:18
+msgid "You can run the formal verification of a component via:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:28
+msgid "Currently, 3 modes are supported :"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:30
+msgid "withBMC(depth)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:31
+msgid "withProve(depth)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:32
+msgid "withCover(depth)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:35
+msgid "Installing requirements"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:37
+msgid "To install the Symbi-Yosys, you have a few options. You can fetch a precompiled package at:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:39
+msgid "https://github.com/YosysHQ/oss-cad-suite-build/releases"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:40
+msgid "https://github.com/YosysHQ/fpga-toolchain/releases (EOL - superseded by oss-cad-suite)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:42
+msgid "Or you can compile things from scratch :"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:44
+msgid "https://symbiyosys.readthedocs.io/en/latest/install.html"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:48
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:52
+msgid "External assertions"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:54
+msgid "Here is an example of a simple counter and the corresponding formal testbench."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:91
+msgid "Internal assertions"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:93
+msgid "If you want you can embed formal statements directly into the DUT:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:120
+msgid "External stimulus"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:122
+msgid "If your DUT has inputs, you need to drive them from the testbench. You can use all the regular hardware statements to do it, but you can also use the formal `anyseq`, `anyconst`, `allseq`, `allconst` statement:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:151
+msgid "More assertions / past"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:153
+msgid "For instance we can check that the value is counting up (if not already at 10):"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:169
+msgid "Assuming memory content"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:171
+msgid "Here is an example where we want to prevent the value ``1`` from ever being present in a memory :"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:207
+msgid "Utilities and primitives"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:210
+msgid "Assertions / clock / reset"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:212
+msgid "Assertions are always clocked and disabled during resets. This also apply for assumes and covers."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:214
+msgid "If you want to keep your assertion enabled during reset you can do:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:224
+msgid "Specifying the initial value of a signal"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:226
+msgid "For instance, for the reset signal of the current clockdomain (usefull at the top)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:233
+msgid "Specifying a initial assumption"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:240
+msgid "Memory content (Mem)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:242
+msgid "If you have a Mem in your design, and you want to check its content, you can do it the following ways :"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:257
+msgid "Specifying assertion in the reset scope"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:267
+msgid "Formal primitives"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:273
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:274
+msgid "Returns"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:275
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:276
+msgid "``assert(Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:279
+msgid "``assume(Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:282
+msgid "``cover(Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:0
+msgid "``past(that : T, delay : Int)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:0
+msgid "``past(that : T)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:287
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:288
+msgid "Return ``that`` delayed by ``delay`` cycles. (default 1 cycle)"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:289
+msgid "``rose(that : Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:290
+#: ../../SpinalHDL/Formal verification/index.rst:293
+#: ../../SpinalHDL/Formal verification/index.rst:296
+#: ../../SpinalHDL/Formal verification/index.rst:299
+#: ../../SpinalHDL/Formal verification/index.rst:302
+#: ../../SpinalHDL/Formal verification/index.rst:305
+#: ../../SpinalHDL/Formal verification/index.rst:308
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:291
+msgid "Return True when ``that`` transitioned from False to True"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:292
+msgid "``fell(that : Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:294
+msgid "Return True when ``that`` transitioned from True to False"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:295
+msgid "``changed(that : Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:297
+msgid "Return True when ``that`` current value changed between compared to the last cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:298
+msgid "``stable(that : Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:300
+msgid "Return True when ``that`` current value didn't changed between compared to the last cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:301
+msgid "``initstate()``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:303
+msgid "Return True the first cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:304
+msgid "``pastValid()``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:306
+msgid "Returns True when the past value is valid (False on the first cycle). Recommended to be used with each application of ``past``, ``rose``, ``fell``, ``changed`` and ``stable``."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:307
+msgid "``pastValidAfterReset()``"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:309
+msgid "Simliar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:311
+msgid "Note that you can use the init statement on past:"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:320
+msgid "Limitations"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:322
+msgid "There is no support for unclocked assertions. But their usage in third party formal verification examples seems mostly code style related."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:326
+msgid "Naming polices"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:328
+msgid "All formal validation related functions return Area or Composite (preferred), and naming as formalXXXX. ``formalContext`` can be used to create formal related logic, there could be ``formalAsserts``, ``formalAssumes`` and ``formalCovers`` in it."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:332
+msgid "For Component"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:333
+msgid "The minimum required assertions internally in a ``Component`` for \"prove\" can be named as ``formalAsserts``."
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:336
+msgid "For interfaces implement IMasterSlave"
+msgstr ""
+
+#: ../../SpinalHDL/Formal verification/index.rst:337
+msgid "There could be functions in name ``formalAssertsMaster``, ``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers``. Master/Slave are target interface type, so that ``formalAssertsMaster`` can be understand as \"formal verfication assertions for master interface\"."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/core.pot b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/core.pot
new file mode 100644
index 00000000000..43241b9199a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/core.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/core.rst:2
+msgid "Core"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/core.rst:3
+msgid "Redirection to https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_core_oo.pdf"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/index.pot b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/index.pot
new file mode 100644
index 00000000000..c482090cc02
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/index.rst:3
+msgid "Cheatsheets"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/lib.pot b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/lib.pot
new file mode 100644
index 00000000000..2112b57d16f
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/lib.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/lib.rst:2
+msgid "Lib"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/lib.rst:4
+msgid "Redirection to https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_lib_oo.pdf"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/symbolic.pot b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/symbolic.pot
new file mode 100644
index 00000000000..0c15bc1ccee
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Cheatsheets/symbolic.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/symbolic.rst:2
+msgid "Symbolic"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Cheatsheets/symbolic.rst:4
+msgid "Redirection to https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_symbolic.pdf"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/index.pot b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/index.pot
new file mode 100644
index 00000000000..1d8cf812c65
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/index.rst:3
+msgid "Help for VHDL people"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.pot b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.pot
new file mode 100644
index 00000000000..a71af538055
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.pot	
@@ -0,0 +1,277 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:5
+msgid "VHDL comparison"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:8
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:10
+msgid "This page will show the main differences between VHDL and SpinalHDL. Things will not be explained in depth."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:13
+msgid "Process"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:15
+msgid "Processes are often needed when you write RTL, however, their semantics can be clunky to work with. Due to how they work in VHDL, they can force you to split your code and duplicate things."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:17
+msgid "To produce the following RTL:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:21
+msgid "You will have to write the following VHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:57
+msgid "While in SpinalHDL, it's:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:73
+msgid "Implicit vs explicit definitions"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:75
+msgid "In VHDL, when you declare a signal, you don't specify if it is a combinatorial signal or a register. Where and how you assign to it decides whether it is combinatorial or registered."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:77
+msgid "In SpinalHDL these kinds of things are explicit. Registers are defined as registers directly in their declaration."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:80
+msgid "Clock domains"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:82
+msgid "In VHDL, every time you want to define a bunch of registers, you need the carry the clock and the reset wire to them. In addition, you have to hardcode everywhere how those clock and reset signals should be used (clock edge, reset polarity, reset nature (async, sync))."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:84
+msgid "In SpinalHDL you can define a ``ClockDomain``, and then define the area of your hardware that uses it."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:86
+msgid "For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:107
+msgid "Component's internal organization"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:109
+msgid "In VHDL, there is a ``block`` feature that allows you to define sub-areas of logic inside your component. However, almost no one uses this feature, because most people don't know about them, and also because all signals defined inside these regions are not readable from the outside."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:111
+msgid "In SpinalHDL you have an ``Area`` feature that does this concept much more nicely:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:131
+msgid "Variables and signals defined inside of an ``Area`` are accessible elsewhere in the component, including in other ``Area`` regions."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:134
+msgid "Safety"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:136
+msgid "In VHDL as in SpinalHDL, it's easy to write combinatorial loops, or to infer a latch by forgetting to drive a signal in the path of a process."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:138
+msgid "Then, to detect those issues, you can use some ``lint`` tools that will analyze your VHDL, but those tools aren't free. In SpinalHDL the ``lint`` process in integrated inside the compiler, and it won't generate the RTL code until everything is fine. It also checks clock domain crossing."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:141
+msgid "Functions and procedures"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:143
+msgid "Functions and procedures are not used very often in VHDL, probably because they are very limited:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:145
+msgid "You can only define a chunk of combinational hardware, or only a chunk of registers (if you call the function/procedure inside a clocked process)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:146
+msgid "You can't define a process inside them."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:147
+msgid "You can't instantiate a component inside them."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:148
+msgid "The scope of what you can read/write inside them is limited."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:150
+msgid "In SpinalHDL, all those limitations are removed."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:152
+msgid "An example that mixes combinational logic and a register in a single function:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:168
+msgid "An example with the queue function inside the Stream Bundle (handshake). This function instantiates a FIFO component:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:184
+msgid "An example where a function assigns a signal defined outside of itself:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:200
+msgid "Buses and Interfaces"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:202
+msgid "VHDL is very boring when it comes to buses and interfaces. You have two options:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:204
+msgid "Define buses and interfaces wire-by-wire, each time and everywhere:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:216
+msgid "Use records but lose parameterization (statically fixed in the package), and you have to define one for each directions:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:223
+msgid "SpinalHDL has very strong support for bus and interface declarations with limitless parameterizations:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:229
+msgid "You can also use object oriented programming to define configuration objects:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:273
+msgid "Signal declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:275
+msgid "VHDL forces you to define all signals at the top of your architecture description, which is annoying."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:295
+msgid "SpinalHDL is flexible when it comes to signal declarations."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:302
+msgid "It also allows you to define and assign signals in a single line."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:309
+msgid "Component instantiation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:311
+msgid "VHDL is very verbose about this, as you have to redefine all signals of your sub-component entity, and then bind them one-by-one when you instantiate your component."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:338
+msgid "SpinalHDL removes that, and allows you to access the IO of sub-components in an object-oriented way."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:349
+msgid "Casting"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:351
+msgid "There are two annoying casting methods in VHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:353
+msgid "boolean <> std_logic (ex: To assign a signal using a condition such as ``mySignal <= myValue < 10`` is not legal)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:354
+msgid "unsigned <> integer  (ex: To access an array)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:356
+msgid "SpinalHDL removes these casts by unifying things."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:358
+msgid "boolean/std_logic:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:366
+msgid "unsigned/integer:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:375
+msgid "Resizing"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:377
+msgid "The fact that VHDL is strict about bit size is probably a good thing."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:383
+msgid "In SpinalHDL you have two ways to do the same:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:394
+msgid "Parameterization"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:396
+msgid "VHDL prior to the 2008 revision has many issues with generics. For example, you can't parameterize records, you can't parameterize arrays in the entity, and you can't have type parameters."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:397
+msgid "Then VHDL 2008 came and fixed those issues. But RTL tool support for VHDL 2008 is really weak depending on the vendor."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:399
+msgid "SpinalHDL has full support for generics integrated natively in its compiler, and it doesn't rely on VHDL generics."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:401
+msgid "Here is an example of parameterized data structures:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:409
+msgid "Here is an example of a parameterized component:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:422
+msgid "Meta hardware description"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:424
+msgid "VHDL has kind of a closed syntax. You can't add abstraction layers on top of it."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:426
+msgid "SpinalHDL, because it's built on top of Scala, is very flexible, and allows you to define new abstraction layers very easily."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:428
+msgid "Some examples of this flexibility are the :ref:`FSM <state_machine>` library, the :ref:`BusSlaveFactory <bus_slave_factory>` library, and also the :ref:`JTAG <jtag>` library."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.pot b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.pot
new file mode 100644
index 00000000000..00dd3c7317b
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.pot	
@@ -0,0 +1,171 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:5
+msgid "VHDL equivalences"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:8
+msgid "Entity and architecture"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:10
+msgid "In SpinalHDL, a VHDL entity and architecture are both defined inside a ``Component``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:12
+msgid "Here is an example of a component which has 3 inputs (``a``, ``b``, ``c``) and an output (``result``). This component also has an ``offset`` construction parameter (like a VHDL generic)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:24
+msgid "Then to instantiate that component, you don't need to bind it:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:43
+msgid "Data types"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:45
+msgid "SpinalHDL data types are similar to the VHDL ones:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:50
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:68
+msgid "VHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:51
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:69
+msgid "SpinalHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:52
+msgid "std_logic"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:53
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:54
+msgid "std_logic_vector"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:55
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:56
+msgid "unsigned"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:57
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:58
+msgid "signed"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:59
+msgid "SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:62
+msgid "In VHDL, to define an 8 bit ``unsigned`` you have to give the range of bits ``unsigned(7 downto 0)``,"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:63
+msgid "whereas in SpinalHDL you simply supply the number of bits ``UInt(8 bits)``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:70
+msgid "records"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:71
+msgid "Bundle"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:72
+msgid "array"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:73
+msgid "Vec"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:74
+msgid "enum"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:75
+msgid "SpinalEnum"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:77
+msgid "Here is an example of the SpinalHDL ``Bundle`` definition. ``channelWidth`` is a construction parameter, like VHDL generics, but for data structures:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:85
+msgid "Then for example, to instantiate a ``Bundle``, you need to write ``val myColor = RGB(channelWidth=8)``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:88
+msgid "Signal"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:90
+msgid "Here is an example about signal instantiations:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:107
+msgid "Assignments"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:109
+msgid "In SpinalHDL, the ``:=`` assignment operator is equivalent to the VHDL signal assignment (``<=``):"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:116
+msgid "Conditional assignments are done like in VHDL by using ``if``/``case`` statements:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:141
+msgid "Literals"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:143
+msgid "Literals are a little bit different than in VHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:163
+msgid "Registers"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:165
+msgid "In SpinalHDL, registers are explicitly specified while in VHDL registers are inferred. Here is an example of SpinalHDL registers:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:175
+msgid "Process blocks"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.rst:177
+msgid "Process blocks are a simulation feature that is unnecessary to design RTL. It's why SpinalHDL doesn't contain any feature analogous to process blocks, and you can assign what you want, where you want."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot b/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot
new file mode 100644
index 00000000000..bd711eb8328
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot	
@@ -0,0 +1,405 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-27 15:39+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:4
+msgid "Install and setup"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:6
+msgid "Spinal is a Scala library (a programming language using the Java VM) so it requires setting up a Scala environment; there are many ways to do so. Also, it generates VHDL, Verilog or SystemVerilog, which can be used by many different tools. This section describes the supported way to install a *SpinalHDL description to Simulation* flow, but there can be many variations."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:13
+msgid "Required/Recommended tools"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:15
+msgid "Before you download the SpinalHDL tools, you need to install a Scala environment:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:17
+msgid "`Java JDK <https://www.oracle.com/java/technologies/downloads/>`_, a Java environment"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:19
+msgid "`Scala 2 <https://www.scala-lang.org/>`_, compiler and library"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:20
+msgid "`SBT <https://www.scala-sbt.org/download/>`_, a Scala build tool"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:22
+msgid "These tools enable to use Spinal; but without any other tools, it is limited to HDL code generation."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:25
+msgid "To enable more features we recommend:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:27
+msgid "An IDE (for instance the currently recommended `IntelliJ <https://www.jetbrains.com/idea/>`_ with its Scala plugin or `VSCodium <https://vscodium.com/>`_ with Metals extension) to get features such as:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:31
+msgid "Code suggestions / completion"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:32
+msgid "Automatic build with syntax errors right in the code"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:33
+msgid "Generate code with a single click"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:34
+msgid "Run simulation / tests with a single click (if a supported simulator is set up)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:37
+msgid "A supported simulator like `Verilator <https://www.veripool.org/verilator/>`_ to test the design right from SpinalHDL."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:39
+msgid "`Gtkwave <https://gtkwave.sourceforge.net/>`_ to view the waves generated by Verilator during simulation."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:41
+msgid "`Git <https://git-scm.com/>`_ for version control system"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:42
+msgid "A C++ toolchain, needed for simulating with Verilator"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:43
+msgid "A linux shell, needed for simulating with Verilator"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:46
+msgid "Linux Installation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:48
+msgid "At time of writing the recommended way of installing Scala and SBT is via `Coursier <https://get-coursier.io/docs/cli-installation>`_. Coursier is able to in addition to the scala tools install a Java JDK to use, in the example below we install Java from the package manager. We recommend to install JDK 17 (LTS) because of compatibility with the used Scala version."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:53
+msgid "For Debian or Ubuntu we run:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:65
+msgid "If you want to install the tools for simulation and/or formal proofs, we recommend `oss-cad-suite <https://github.com/YosysHQ/oss-cad-suite-build>`_. It contains a waveform viewer (gtkWave), verilog simulators (verilator and iverilog), VHDL simulator (GHDL) and other tools. In case you want to build the tools yourself have a look at the legacy simulation tool :ref:`installation instructions <sim backend install>`."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:69
+msgid "We first install the needed C++ toolchain and download oss-cad-suite. To use it we must load the oss-cad-suite environment for each shell we want to use it in. Note that oss-cad-suite contains a Python 3 interpreter that may interfere with the system Python installation if loaded permanently."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:73
+msgid "Go to the oss-cad-suite `release page <https://github.com/YosysHQ/oss-cad-suite-build/releases/latest>`_ to get the download link for the latest version. You can download/extract oss-cad-suite to a folder of your choice. (last tested version of oss-cad-suite is `2023-10-22`, but more recent ones will most likely also work)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:83
+msgid "To use oss-cad-suite in a shell you need to load it's environment, e.g. via ``souce <path to oss-cad-suite>/environment``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:87
+msgid "Mac OS X Installation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:88
+msgid "You can use homebrew to install on Mac OS X.  By default homebrew installs Java 21, but the  SpinalHDL tutorial SpinalTemplateSbt uses Scala version 2.12.16, which is not supported by Java 21 (17 is still the recommended LTS version, https://whichjdk.com/). So to install Java version 1.7 do:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:96
+msgid "And then add this to your path."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:102
+msgid "To manage multiple versions of Java it is also essential to have jenv installed."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:108
+msgid "Jenv added these lines to my .bash_profile"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:115
+msgid "Next you have to install scala's interactive build tool sbt."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:121
+msgid "If this works for you, please let us know.  If this does not work for you, you can read the github issue about Mac o SX installation here. https://github.com/SpinalHDL/SpinalHDL/issues/1216"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:124
+msgid "If you want to install the tools for simulation and/or formal proofs, we recommend `oss-cad-suite <https://github.com/YosysHQ/oss-cad-suite-build>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:127
+msgid "Windows installation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:130
+msgid "While a native installation is possible the simpler and currently recommended way is to use WSL on Windows. If you want to use WSL, install `it <https://learn.microsoft.com/en-us/windows/wsl/install>`_, a distribution of your choice and follow the Linux installation instructions. Data in your WSL instance can be accessed from windows under ``\\\\wsl$``. In case you want to use IntelliJ you'll have to download the Linux version to WSL, if you want to use VSCode then the Windows version can be used to remotely edit in WSL."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:136
+msgid "At time of writing the recommended way of installing Scala and SBT is via `Coursier <https://get-coursier.io/docs/cli-installation>`_. Coursier is able to in addition to the scala tools install a Java JDK to use, in the example below we install Java manually. We recommend to install JDK 17 (LTS) because of compatibility with Scala."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:141
+msgid "First download and install `Adoptium JDK 17 <https://adoptium.net/temurin/releases/?os=windows&version=17>`_. Download, unzip and run the `Coursier installer <https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-win32.zip>`_, when asked agree to an update of your ``PATH`` variable. Reboot to force an update of ``PATH``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:145
+msgid "This is sufficient for generating hardware. For simulation continue with either choice below. In case you want to build the tools yourself have a look at the legacy simulation tool :ref:`installation instructions <sim backend install>`."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:149
+msgid "An All-in-One solution offered by SpinalHDL maintainer `Readon <https://github.com/Readon>` is available to install and run SpinalHDL with Verilator simulation and formal verification via SymbiYosys. Download `it <https://github.com/Readon/msys2-installer/releases>`_ and install the environment anywhere on your disk. Start the build environment by clicking on the MSYS2-MINGW64 icon in the Start menu and use the MSYS2 default console. An alternative is to use the Windows Terminal or a Tabby-like application and use the startup command ``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``, where the ``%MSYS2_ROOT%`` is the location of the msys2 installation. It is worth noting that if you want to use it offline, you should carefully select the libraries that the project depends on, otherwise you will need to download the packages manually. See the README for the repos for more details."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:158
+msgid "MSYS2 verilator for simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:160
+msgid "We recommend to install compiler/verilator through `MSYS2 <https://www.msys2.org>`. Other methods of installing gcc/make/shell (e.g. chocolatey, scoop, etc.) may also work but are untested."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:163
+msgid "SpinalHDL maintainer `Readon <https://github.com/Readon>` is maintaining a MSYS2 fork that default installs all needed officially available and custom built packages (also maintained by Readon `here <https://github.com/Readon/MINGW-SpinalHDL>`) for simulation and formal verification. It can be found `here <https://github.com/Readon/msys2-installer>`. If used then the packages installed below via ``pacman`` are already installed and those installation steps can be skipped."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:169
+msgid "Currently verilator 4.228 is latest available version known to work."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:171
+msgid "Download the latest installer and install MSYS2 with default settings. You should get a MSYS2 terminal at the end of the installation, there run:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:184
+msgid "In a MSYS2 MINGW64 terminal we need to set some environment variables to make Java/sbt available (you can make these settings persistent by adding them to ``~/.bashrc`` in MSYS2):"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:193
+msgid "With this you should be able to run sbt/verilator simulations from MSYS2 terminals (sbt via calling ``sbt.bat``)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:196
+msgid "MSYS2 for formal verification"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:198
+msgid "In addition to the steps above we also need to install yosys, sby, z3 and yices. Both yosys(yosys-smtbmc workable) and sby are not available as official MSYS2 packages, but packages are provided by `Readon <https://github.com/Readon>`. If you used their installer then these steps are not needed (you should check if there are newer packages available)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:212
+msgid "OCI Container"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:214
+msgid "A container for SpinalHDL development is available as well. The container is hosted at ``ghcr.io/spinalhdl/docker:master`` and can be used with Docker/Podman/Github Codespaces. It is used for the SpinalHDL CI regression and can therefore be an easy way to run the CI commands locally."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:218
+msgid "To run the container run e.g. ``podman run -v .:/workspace -it ghcr.io/spinalhdl/docker:master`` in a SpinalHDL project root directory, making the project directory available in ``/workspace``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:221
+msgid "Please consult the documentation of you Distribution (Linux, WSL) or Docker (Windows) on how to install the container runtime you want to use. Multiple editors/IDEs (e.g. VSCode, IntelliJ, Neovide) allow for remote development in a container. Please consult the documentation of the editor on how to do remote development."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:226
+msgid "Installing SBT in an internet-free Linux environment"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:229
+msgid "If you are not using an air-gapped environment we recommend to go with the normal linux installation. (which is a subset of the installation for an air-gapped environment)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:233
+msgid "Normally, SBT uses online repositories to download and cache your projects dependencies. This cache is located in several folders:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:236
+msgid "``~/.sbt``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:237
+msgid "``~/.cache/JNA``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:238
+msgid "``~/.cache/coursier``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:240
+msgid "To set up an internet-free environment, you can:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:242
+msgid "Set up an environment with internet (see above)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:243
+msgid "Launch a Spinal command (see :ref:`Using SBT`) to fetch dependencies (for instance using the `getting started <https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:246
+msgid "Copy the caches to the internet-free environment."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:251
+msgid "Create a first SpinalHDL project"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:253
+msgid "We have prepared a ready-to-go project for you the: `getting started <https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:255
+msgid "You can `download <https://codeload.github.com/SpinalHDL/SpinalTemplateSbt/zip/master>`_ it, or clone it."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:257
+msgid "The following commands clone the project into a new directory named ``MySpinalProject`` and initialize a fresh ``git`` history:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:271
+msgid "The directory structure of a project"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:275
+msgid "The structure described here is the default structure, but it can be easily modified."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:278
+msgid "In the root of the project are the following files:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:281
+msgid "File"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:281
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:283
+msgid "``build.sbt``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:283
+msgid "Scala configuration for ``sbt``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:284
+msgid "``build.sc``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:284
+msgid "Scala configuration for ``mill``, an alternative to ``sbt``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:285
+msgid "``hw/``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:285
+msgid "The folder containing hardware descriptions"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:286
+msgid "``project/``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:286
+msgid "More Scala configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:287
+msgid "``README.md``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:287
+msgid "A ``text/markdown`` file describing your project"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:288
+msgid "``.gitignore``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:288
+msgid "List of files to ignore in versioning"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:289
+msgid "``.mill-version``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:289
+msgid "More configuration for ``mill``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:290
+msgid "``.scalafmt.conf``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:290
+msgid "Configuration of rules to auto-format the code"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:293
+msgid "As you probably guessed it, the interesting thing here is ``hw/``. It contains four folders: ``spinal/``, ``verilog/`` and ``vhdl/`` for your IPs and ``gen/`` for IPs generated with Spinal."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:297
+msgid "``hw/spinal/`` contains a folder named after your project name. This name must be set in ``build.sbt`` (along with the company name) and in ``build.sc``; and it must be the one in ``package yourprojectname`` at the beginning of ``.scala`` files."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:302
+msgid "In ``hw/spinal/yourprojectname/``, are the descriptions of your IPs, simulation tests, formal tests; and there is ``Config.scala``, which contains the configuration of ``Spinal``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:308
+msgid "``sbt`` must be used **only** at the root of the project, in the folder containing ``build.sbt``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:313
+msgid "Using Spinal on SpinalHDL code"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:315
+msgid "Now the tutorial shows how to use Spinal on SpinalHDL code depending on your development environment:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:318
+msgid ":ref:`Using SBT`"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:319
+msgid ":ref:`Using VSCodium`"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:320
+msgid ":ref:`Using IntelliJ`"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/IntelliJ.pot b/source/locale/gettext/SpinalHDL/Getting Started/IntelliJ.pot
new file mode 100644
index 00000000000..211cdc02557
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/IntelliJ.pot	
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:4
+msgid "Using Spinal from IntelliJ IDEA"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:6
+msgid "In addition to the aforementioned requirements, you also need to download the IntelliJ IDEA (the free *Community edition* is enough). When you have installed IntelliJ, also check that you have enabled its Scala plugin (\\ `install information <https://www.jetbrains.com/help/idea/2016.1/enabling-and-disabling-plugins.html?origin=old_help>`_ can be found here)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:8
+msgid "And do the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:10
+msgid "In *Intellij IDEA*\\ , \"import project\" with the root of this repository, the choose the *Import project from external model SBT* and be sure to check all boxes."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:11
+msgid "In addition, you might need to specify some path like where you installed the JDK to *IntelliJ*."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:12
+msgid "In the project (Intellij project GUI), right click on ``src/main/scala/mylib/MyTopLevel.scala`` and select \"Run MyTopLevel\"."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:14
+msgid "This should generate the output file ``MyTopLevel.vhd`` in the project directory, which implements a simple 8-bit counter."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/IntelliJ.rst:16
+msgid "Now you can use your environment, let's explore the code: :ref:`Simple example`."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/SBT.pot b/source/locale/gettext/SpinalHDL/Getting Started/SBT.pot
new file mode 100644
index 00000000000..790f09eae5c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/SBT.pot	
@@ -0,0 +1,77 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:4
+msgid "Using Spinal from CLI with SBT"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:6
+msgid "First, open a terminal in the root of the template you have downloaded earlier in :ref:`template`."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:9
+msgid "Commands can be executed right from the terminal:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:15
+msgid "But ``sbt`` has a quite long boot time so the we recommend to use its interactive mode:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:22
+msgid "Now ``sbt`` shows a prompt. Let's start by doing Scala compilation. It will fetch dependencies so it can take time the first time:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:29
+msgid "Actually you never need to just ``compile`` as it is done automatically when needed. The first build time will take a few moments longer compared to future builds as the sbt tool builds the entire project from a cold start and then uses incremental building where possible from that point on.  ``sbt`` supports autocompletion inside the interactive shell to assist discovery and usage of the available commands. You can start the interactive shell with ``sbt shell`` or running ``sbt`` with no arguments from the command line."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:37
+msgid "To run a specific HDL code-generation or simulation, the command is ``runMain``. So if you type ``runMain``, space, and tab, you should get this:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:47
+msgid "The autocompletion suggests all things that can be run. Let's run the Verilog generation for instance:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:54
+msgid "Look at the directory ./hw/gen/: there is a new ``MyTopLevel.v`` file!"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:56
+msgid "Now add a ``~`` at the beginning of the command:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:62
+msgid "It prints this:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:83
+msgid "So now, each time you save a source file, it will re-generate ``MyTopLevel.v``. To do this, it automatically compiles the source files and it performs lint checks. This way you can get errors printed on the terminal almost in real-time while you are editing the source files."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:88
+msgid "You can press Enter to stop automatic generation, then Ctrl-D to exit ``sbt``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:90
+msgid "It is also possible to start it right from the terminal, without using ``sbt``'s interactive prompt:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:97
+msgid "Now you can use your environment, let's explore the code: :ref:`Simple example`."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/basics.pot b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/basics.pot
new file mode 100644
index 00000000000..f90d0316600
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/basics.pot	
@@ -0,0 +1,273 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:3
+msgid "Variables and functions should be defined into ``object``\\ , ``class``\\ , ``function``. You can't define them on the root of a Scala file."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:6
+msgid "Basics"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:9
+msgid "Types"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:11
+msgid "In Scala, there are 5 major types:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:17
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:18
+msgid "Literal"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:19
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:20
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:21
+msgid "true, false"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:23
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:24
+msgid "3, 0x32"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:25
+msgid "32 bits integer"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:26
+msgid "Float"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:27
+msgid "3.14f"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:28
+msgid "32 bits floating point"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:29
+msgid "Double"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:30
+msgid "3.14"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:31
+msgid "64 bits floating point"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:32
+msgid "String"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:33
+msgid "\"Hello world\""
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:34
+msgid "UTF-16 string"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:38
+msgid "Variables"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:40
+msgid "In Scala, you can define a variable by using the ``var`` keyword:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:49
+msgid "Scala is able to infer the type automatically. You don't need to specify it if the variable is assigned at declaration:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:55
+msgid "However, it's not very common to use ``var`` in Scala. Instead, constant values defined by ``val`` are often used:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:64
+msgid "Functions"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:66
+msgid "For example, if you want to define a function which returns ``true`` if the sum of its two arguments is bigger than zero, you can do as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:74
+msgid "Then, to call this function, you can write:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:80
+msgid "You can also specify arguments by name, which is useful if you have many arguments:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:90
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:92
+msgid "The ``return`` keyword is not necessary. In absence of it, Scala takes the last statement of your function as the returned value."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:101
+msgid "Return type inferation"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:103
+msgid "Scala is able to automatically infer the return type. You don't need to specify it:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:112
+msgid "Curly braces"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:114
+msgid "Scala functions don't require curly braces if your function contains only one statement:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:121
+msgid "Function that returns nothing"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:123
+msgid "If you want a function to return nothing, the return type should be set to ``Unit``. It's equivalent to the C/C++ ``void`` type."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:133
+msgid "Argument default values"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:135
+msgid "You can specify a default value for each argument of a function:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:144
+msgid "Apply"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:146
+msgid "Functions named ``apply`` are special because you can call them without having to type their name:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:157
+msgid "This concept is also applicable for Scala ``object`` (static)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:168
+msgid "Object"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:170
+msgid "In Scala, there is no ``static`` keyword. In place of that, there is ``object``. Everything defined inside an ``object`` definition is static."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:172
+msgid "The following example defines a static function named ``pow2`` which takes a floating point value as parameter and returns a floating point value as well."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:180
+msgid "Then you can call it by writing:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:187
+msgid "Entry point (main)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:189
+msgid "The entry point of a Scala program (the main function) should be defined inside an object as a function named ``main``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:200
+msgid "Class"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:202
+msgid "The class syntax is very similar to Java. Imagine that you want to define a ``Color`` class which takes as construction parameters three Float values (r,g,b) :"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:210
+msgid "Then, to instantiate the class from the previous example and use its ``getGrayLevel`` function:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:217
+msgid "Be careful, if you want to access a construction parameter of the class from the outside, this construction parameter should be defined as a ``val``:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:227
+msgid "Inheritance"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:229
+msgid "As an example, suppose that you want to define two classes, ``Rectangle`` and ``Square``, which extend the class ``Shape``:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:246
+msgid "Case class"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:248
+msgid "Case class is an alternative way of declaring classes."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:256
+msgid "Then there are some differences between ``case class`` and ``class`` :"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:258
+msgid "case classes don't need the ``new`` keyword to be instantiated."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:259
+msgid "construction parameters are accessible from outside; you don't need to define them as ``val``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:261
+msgid "In SpinalHDL, this explains the reasoning behind the coding conventions: it's in general recommended to use ``case class`` instead of ``class`` in order to have less typing and more coherency."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:264
+msgid "Templates / Type parameterization"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:266
+msgid "Imagine you want to design a class which is a queue of a given datatype, in that case you need to provide a type parameter to the class:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:275
+msgid "If you want to restrict the ``T`` type to be a sub class of a given type (for example ``Shape``), you can use the ``<: Shape`` syntax :"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/basics.rst:289
+msgid "The same is possible for functions:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/coding_conventions.pot b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/coding_conventions.pot
new file mode 100644
index 00000000000..61337f94fac
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/coding_conventions.pot	
@@ -0,0 +1,145 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:3
+msgid "Coding conventions"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:8
+msgid "The coding conventions used in SpinalHDL are the same as the ones documented in the `Scala Style Guide <https://docs.scala-lang.org/style/>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:10
+msgid "Some additional practical details and cases are explained in next pages."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:13
+msgid "class vs case class"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:15
+msgid "When you define a ``Bundle`` or a ``Component``, it is preferable to declare it as a case class."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:17
+msgid "The reasons are:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:19
+msgid "It avoids the use of ``new`` keywords. Never having to use it is better than sometimes, under some conditions."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:20
+msgid "A ``case class`` provides a ``clone`` function. This is useful in SpinalHDL when there is a need to clone a ``Bundle``, for example, when you define a new ``Reg`` or a new ``Stream`` of some kind."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:21
+msgid "Construction parameters are directly visible from outside."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:24
+msgid "[case] class"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:26
+msgid "All classes names should start with a uppercase letter"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:43
+msgid "companion object"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:45
+msgid "A `companion object <https://docs.scala-lang.org/overviews/scala-book/companion-objects.html>`_ should start with an uppercase letter."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:57
+msgid "An exception to this rule is when the companion object is used as a function (only ``apply`` inside), and these ``apply`` functions don't generate hardware:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:66
+msgid "function"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:68
+msgid "A function should always start with a lowercase letter:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:80
+msgid "instances"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:82
+msgid "Instances of classes should always start with a lowercase letter:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:90
+msgid "if / when"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:92
+msgid "Scala ``if`` and SpinalHDL ``when`` should normally be written in the following way:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:112
+msgid "Exceptions could be:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:114
+msgid "It's fine to include a dot before the keyword like methods ``.elsewhen`` and ``.otherwise``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:115
+msgid "It's fine to compress an ``if``\\ /\\ ``when`` statement onto a single line if it makes the code more readable."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:118
+msgid "switch"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:120
+msgid "SpinalHDL ``switch`` should normally be written in the following way:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:136
+msgid "It's fine to compress an ``is``\\ /\\ ``default`` statement onto a single line if it makes the code more readable."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:139
+msgid "Parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:141
+msgid "Grouping parameters of a ``Component``/``Bundle`` inside a case class is generally welcome because:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:143
+msgid "Easier to carry/manipulate to configure the design"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:144
+msgid "Better maintainability"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/coding_conventions.rst:158
+msgid "But this should not be applied in all cases. For example: in a FIFO, it doesn't make sense to group the ``dataType`` parameter with the ``depth`` parameter of the fifo because, in general, the ``dataType`` is something related to the design, while the ``depth`` is something related to the configuration of the design."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/index.pot b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/index.pot
new file mode 100644
index 00000000000..d01dc73ed13
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/index.pot	
@@ -0,0 +1,37 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/index.rst:3
+msgid "Scala Guide"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/index.rst:14
+msgid "Scala guide"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/index.rst:17
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/index.rst:18
+msgid "Scala is a very capable programming language that was influenced by a unique set of languages, but often, this set of languages doesn't cross the ones that most programmers use. That can hinder newcomers' understanding of the concepts and design choices behind Scala."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/index.rst:20
+msgid "The following pages will present Scala, and try to provide enough information about it for newcomers to be comfortable with SpinalHDL."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/interaction.pot b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/interaction.pot
new file mode 100644
index 00000000000..e10b589243d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/Scala Guide/interaction.pot	
@@ -0,0 +1,137 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:3
+msgid "Interaction"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:8
+msgid "SpinalHDL is, in fact, not an language: it's a regular Scala library. This could seem strange at first glance, but it is a very powerful combination."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:10
+msgid "You can use the whole Scala world to help you in the description of your hardware via the SpinalHDL library, but to do that properly, it's important to understand how SpinalHDL interacts with Scala."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:13
+msgid "How SpinalHDL works behind the API"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:15
+msgid "When you execute your SpinalHDL hardware description, each time you use SpinalHDL functions, operators, or classes, it will build an in-memory graph that represents the netlist of your design."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:17
+msgid "Then, when the elaboration is done (instantiation of your top-level ``Component`` classes), SpinalHDL will do some passes on the graph that was constructed, and if everything is fine, it will flush that graph into a VHDL or Verilog file."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:20
+msgid "Everything is a reference"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:22
+msgid "For example, if you define a Scala function which takes a parameter of type ``Bits``, when you call it, it will be passed as a reference. As consequence of that, if you assign that argument inside the function, it has the same effect on the underlying ``Bits`` object as if you had assigned to it outside the function."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:27
+msgid "Hardware types"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:29
+msgid "Hardware data types in SpinalHDL are the combination of two things:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:32
+msgid "An instance of a given Scala type"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:33
+msgid "The configuration of that instance"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:35
+msgid "For example ``Bits(8 bits)`` is the combination of the Scala type ``Bits`` and its ``8 bits`` configuration (as a construction parameter)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:45
+msgid "RGB example"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:47
+msgid "Let's take an Rgb bundle class as example:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:57
+msgid "The hardware data type here is the combination of the Scala ``Rgb`` class and its ``rWidth``, ``gWidth``, and ``bWidth`` parameterization."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:59
+msgid "Here is an example of usage:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:69
+msgid "You can also use functions to define various kinds of type factories (typedef):"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:80
+msgid "Names of signals in the generated RTL"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:82
+msgid "To name signals in the generated RTL, SpinalHDL uses Java reflections to walk through your entire component hierarchy, collecting all references stored inside the class attributes, and naming them with their attribute name."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:84
+msgid "This is why the names of every signal defined inside a function are lost:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:95
+msgid "One solution if you want preserve the names of the internal variables in the generated RTL, is to use ``Area``:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:107
+msgid "Scala is for elaboration, SpinalHDL for hardware description"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:109
+msgid "For example, if you write a Scala for loop to generate some hardware, it will generate the unrolled result in VHDL/Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:111
+msgid "Also, if you want a constant, you should not use SpinalHDL hardware literals but the Scala ones. For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:126
+msgid "Scala elaboration capabilities (if, for, functional programming)"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:128
+msgid "All of Scala's syntax can be used to elaborate hardware designs, for instance, a Scala ``if`` statement could be used to enable or disable the generation of hardware:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:140
+msgid "The same is true for Scala ``for`` loops:"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/Scala Guide/interaction.rst:152
+msgid "Also, functional programming techniques can be used with many SpinalHDL types:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/VSCodium.pot b/source/locale/gettext/SpinalHDL/Getting Started/VSCodium.pot
new file mode 100644
index 00000000000..9296e13291d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/VSCodium.pot	
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:4
+msgid "Using Spinal from VSCodium"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:7
+msgid "`VSCodium <https://vscodium.com/>`_ is the open source build of Visual Studio Code, but without the telemetry included in Microsoft's downloadable version."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:9
+msgid "As a one-time setup task, go to view->extensions search for \"Scala\" and install the \"Scala (Metals)\" `extension <https://marketplace.visualstudio.com/items?itemName=scalameta.metals>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:11
+msgid "Open the workspace: ``File`` > ``Open Folder...`` and open the folder you have downloaded earlier in :ref:`template`."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:13
+msgid "The other way to start it, is to cd into the appropriate directory and type ``codium .``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:15
+msgid "Wait a little bit, a notification pop-up should appear on the bottom-right corner: \"Multiple build definitions found. Which would you like to use?\". Click ``sbt``, then another pop-up appears, click ``Import build``."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:19
+msgid "Wait while running ``sbt bloopInstall``. Then a warning pop-up appears, you can ignore it (don't show again)."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:22
+msgid "Find and open ``hw/spinal/projectname/MyTopLevel.scala``.  Wait a little bit, and see the ``run | debug`` line that is displayed by Metals, before each ``App``. For instance, click on ``run`` just above ``object MyTopLevelVerilog``. Alternatively, you can select Menu Bar -> Run -> Run Without Debugging.  Either approach performs design checks and, as the checks pass, generates the Verilog file ``./hw/gen/MyTopLevel.v``"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:25
+msgid "This is all you need to do to use SpinalHDL from VSCodium.  You now have the design-rule-checked Verilog and/or VHDL which you can use as input to your favorite synthesis tool."
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:27
+msgid "Now that you know how to use the VSCodium development environment, let's explore the code: :ref:`Simple example`."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Getting Started/index.pot b/source/locale/gettext/SpinalHDL/Getting Started/index.pot
new file mode 100644
index 00000000000..d627698d725
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Getting Started/index.pot	
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Getting Started/index.rst:3
+msgid "Getting Started"
+msgstr ""
+
+#: ../../SpinalHDL/Getting Started/index.rst:5
+msgid "Let's start learning SpinalHDL! In this chapter, we will install and setup an environment, taste the language and learn how to generate VHDL and Verilog, and perform lints on the fly."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/A simple example.pot b/source/locale/gettext/SpinalHDL/Introduction/A simple example.pot
new file mode 100644
index 00000000000..e6a8dc92795
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/A simple example.pot	
@@ -0,0 +1,129 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:4
+msgid "A simple example"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:6
+msgid "Below is a simple hardware description from the `getting started <https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:29
+msgid "It is split into chunks and explained in this section."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:33
+msgid "Component"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:35
+msgid "First, there is the structure of a SpinalHDL ``Component``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:37
+msgid "A component is a piece of logic which can be instantiated (pasted) as many times as needed, and where the only accessible signals are its inputs and outputs."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:50
+msgid "``MyTopLevel`` is the name of the component."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:52
+msgid "In SpinalHDL, components use ``UpperCamelCase``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:56
+msgid "See also :ref:`Component` for more information."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:60
+msgid "Ports"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:62
+msgid "Then, the ports are defined."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:71
+msgid "Directions:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:73
+msgid "``cond0`` and ``cond1`` are inputs ports"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:74
+msgid "``flag`` and ``state`` are outputs ports"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:76
+msgid "Types:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:78
+msgid "``cond0``, ``cond1`` and ``flag`` are 1 bit each (as 3 individual wires)"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:79
+msgid "``state`` is an 8-bit unsigned integer (a bus of 8 wires representing an unsigned integer)"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:84
+msgid "This syntax is only available since SpinalHDL 1.8, see :ref:`io` for legacy syntax and more information."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:89
+msgid "Internal logic"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:91
+msgid "Finally, there is the component logic:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:104
+msgid "``counter`` is a register containing an 8-bits unsigned integer, with the initial value 0. Assignments to change the state of a register are available for read-back only after the next clock sampling."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:110
+msgid "Because of the presence of a register, two implicit signals are added to the component for the clock and the reset. See :ref:`Reg` and :ref:`clock_domain` for more information."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:114
+msgid "Then a conditional rule is described: when the input ``cond0`` (which is in the ``io`` bundle) is set, the ``counter`` is incremented by one, else ``counter`` keeps its value set in the last rule. But, there is no previous rule, you would say. With a simple signal it would be a latch, and trigger an error. But here ``counter`` is a register, so it has a default case: it just keeps the same value."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:121
+msgid "This creates a multiplexer: the input of the ``counter`` register can be its output or its output plus one depending on ``io.cond0``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:124
+msgid "Then unconditional rules (assignments) are described:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:126
+msgid "The output ``state`` is connected to the output of the register ``counter``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:127
+msgid "The output ``flag`` is the output of an ``or`` gate between a signal which is true when the output of \"``counter`` equals 0\", and the input ``cond1``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/A simple example.rst:132
+msgid "See also :ref:`semantics` for more information."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/Contributing.pot b/source/locale/gettext/SpinalHDL/Introduction/Contributing.pot
new file mode 100644
index 00000000000..f86fd9bd4ec
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/Contributing.pot
@@ -0,0 +1,37 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/Contributing.rst:2
+msgid "Contributing"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Contributing.rst:4
+msgid "`Repository of the language <https://github.com/SpinalHDL/SpinalHDL>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Contributing.rst:5
+msgid "`Contributor guide <https://github.com/SpinalHDL/SpinalHDL/blob/dev/CONTRIBUTING.md>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Contributing.rst:6
+msgid "`Repository of this documentation <https://github.com/SpinalHDL/SpinalDoc-RTD>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Contributing.rst:7
+msgid "`Donation channel <https://opencollective.com/spinalhdl>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/Getting in touch.pot b/source/locale/gettext/SpinalHDL/Introduction/Getting in touch.pot
new file mode 100644
index 00000000000..a87f1213dc5
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/Getting in touch.pot	
@@ -0,0 +1,53 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:2
+msgid "Getting in touch"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:4
+msgid "For questions about SpinalHDL syntax and live talks:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:6
+msgid "`English Matrix channel <https://gitter.im/SpinalHDL/SpinalHDL>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:7
+msgid "`Chinese Matrix channel <https://gitter.im/SpinalHDL-CN/Community>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:8
+msgid "`Google group <https://groups.google.com/forum/#!forum/spinalhdl-hardware-description-language>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:10
+msgid "For bug reports, feature requests and questions:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:12
+msgid "`Open a ticket <https://github.com/SpinalHDL/SpinalHDL/issues/new>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:14
+msgid "If you are interested in a presentation, a workshop, or consulting:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Getting in touch.rst:16
+msgid "`Contact us by email: spinalhdl@gmail.com <mailto:spinalhdl@gmail.com>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/License.pot b/source/locale/gettext/SpinalHDL/Introduction/License.pot
new file mode 100644
index 00000000000..b7584d5c9f3
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/License.pot
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/License.rst:2
+msgid "License"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:4
+msgid "SpinalHDL uses two licenses, one for ``spinal.core`` and one for ``spinal.lib`` and everything else in the repository."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:7
+msgid "``spinal.core`` (the compiler) is under the LGPL license, which can be summarized as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:10
+msgid "You can make money with your SpinalHDL description and its generated RTL."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:11
+msgid "You don't have to share your SpinalHDL description and its generated RTL."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:12
+msgid "There are no fees and no royalties."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:13
+msgid "If your make improvements to the SpinalHDL core, and you wish to redistribute those modifications, you have to share those modifications to make the tool better for everybody."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/License.rst:17
+msgid "``spinal.lib`` (a general purpose library of components/tools/interfaces) is under the permissive MIT license so you do not have to share it, even if contributions are really appreciated."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/Other learning materials.pot b/source/locale/gettext/SpinalHDL/Introduction/Other learning materials.pot
new file mode 100644
index 00000000000..01407493d3c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/Other learning materials.pot	
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:2
+msgid "Other learning materials"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:4
+msgid "`A short show case (PDF slideshow) <https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/motivation.pdf>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:5
+msgid "`Presentation of the language (PDF slideshow) <https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/presentation.pdf>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:6
+msgid "`Jupyter bootcamp <https://github.com/SpinalHDL/Spinal-bootcamp>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:7
+msgid "`Workshop <https://github.com/SpinalHDL/SpinalWorkshop>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:9
+msgid "There is also a few more specific videos online :"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:11
+msgid "`On youtube <https://www.youtube.com/results?search_query=SpinalHDL>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:12
+msgid "`On f-si's peertube <https://peertube.f-si.org/search?search=SpinalHDL>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:14
+msgid "A few SpinalHDL webinar were made and are recorded here :"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:16
+msgid "`Datenlord's youtube channel <https://www.youtube.com/@datenlord>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:21
+msgid "Some of those tutorials are not using the latest version of SpinalHDL, so they may lack some recent SpinalHDL features."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot b/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot
new file mode 100644
index 00000000000..47baccfcf69
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot	
@@ -0,0 +1,123 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:2
+msgid "Projects using SpinalHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:4
+msgid "Note that the following lists are very incompletes."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:9
+msgid "Repositories"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:11
+msgid "`J1Sc Stack CPU <https://github.com/SteffenReith/J1Sc>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:12
+msgid "`VexRiscv CPU and SoC <https://github.com/SpinalHDL/VexRiscv>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:13
+msgid "`NaxRiscv CPU <https://github.com/SpinalHDL/NaxRiscv>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:14
+msgid "`SaxonSoc <https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:15
+msgid "`open-rdma <https://github.com/datenlord/open-rdma>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:16
+msgid "`MicroRV32 SoC <https://github.com/agra-uni-bremen/microrv32>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:17
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:46
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:63
+msgid "\\.\\.\\."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:21
+msgid "Companies"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:23
+msgid "`DatenLord, China <https://datenlord.github.io/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:25
+msgid "`RoCE v2 hardware implementation <https://github.com/datenlord/open-rdma>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:26
+msgid "`WaveBPF <https://github.com/datenlord/wavebpf>`_ (wBPF): a \"tightly-coupled multi-core\" eBPF CPU, designed to be a high-throughput coprocessor for processing in-memory data (e.g. network packets)."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:30
+msgid "`Elitestek (FPGA Vendor), China <https://elitestek.com/product/RISC_V/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:32
+msgid "\"Elitestek has used the VexRISC-V core in FPGAs and applied in multi applications in worldwide customers.\""
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:35
+msgid "`LeafLabs, Massachusetts, USA <https://www.leaflabs.com>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:37
+msgid "`SpinalHDL To Accelerate Neuroscience (PDF slideshow) <https://github.com/SpinalHDL/SpinalHDL/files/10219043/SpinalHDL.To.Accelerate.Neuro.pdf>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:40
+msgid "QsPin, Belgium"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:42
+msgid "`Tiempo Secure, France <https://www.tiempo-secure.com/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:44
+msgid "`SpinalHDL for ASIC (PDF slideshow) <https://github.com/SpinalHDL/SpinalHDL/files/10239051/SpinalHDL.for.ASIC.pdf>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:49
+msgid "Universities"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:51
+msgid "`Universität Bremen - Fachbereich 3 - Informatik, Germany <http://www.informatik.uni-bremen.de/agra/ger/index.php>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:54
+msgid "`SpinalHDL in Computer Architecture Research and Education (PDF slideshow) <https://github.com/SpinalHDL/SpinalHDL/files/10244833/20221216_summit_saahm.pdf>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:57
+msgid "`Universität Potsdam - Embedded Systems Architectures for Signalprocessing, Germany <https://www.uni-potsdam.de/en/aess/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:60
+msgid "`A Network Attached Deep Learning Accelerator for FPGA Clusters (PDF slideshow) <https://github.com/SpinalHDL/SpinalHDL/files/10238707/A_Network_Attached_Deep_Learning_Accelerator_for_FPGA_Clusters.pdf>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/SpinalHDL.pot b/source/locale/gettext/SpinalHDL/Introduction/SpinalHDL.pot
new file mode 100644
index 00000000000..605bf96ebc6
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/SpinalHDL.pot
@@ -0,0 +1,141 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:4
+msgid "About SpinalHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:7
+msgid "What is SpinalHDL?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:9
+msgid "SpinalHDL is an open source high-level hardware description language with associated tools. Its development started in December 2014."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:12
+msgid "SpinalHDL makes it possible to efficiently describe hardware, giving names to digital hardware notions; the most obvious examples are ``Reg`` and ``Latch``. In event-driven languages such as VHDL and Verilog, to use these two common elements, the user has to describe how to simulate them with a process, so that the synthesis tool can infer what cell it is. With SpinalHDL, you just have to declare a ``Reg`` or a ``Latch``."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:19
+msgid "SpinalHDL is a *domain-specific language* based on Scala a general-purpose language. It brings several benefits:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:22
+msgid "There are free integrated development environments supporting it, providing many features that simple text editors don't have:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:25
+msgid "syntax and type errors are highlighted right in the code"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:26
+msgid "correct renaming, even across files"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:27
+msgid "smart auto completion / suggestions"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:28
+msgid "navigation tools (go to definition, show all references, etc.)"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:30
+msgid "It allows to implement simple to complex hardware generators (meta-hardware description) with no need to deal with several languages."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:35
+msgid "`Scala <https://scala-lang.org/>`_ is a statically-typed, functional and object-oriented language using the Java virtual machine (JVM)."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:40
+msgid "What SpinalHDL is not"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:42
+msgid "SpinalHDL is not an HLS tool: its goal is not to automagically transform an abstract algorithm into a digital circuit. Its goal is to create a new abstraction level by naming things, to help the designer reuse their code and not write the same thing over and over again."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:47
+msgid "SpinalHDL is not an analog modeling language. VHDL and Verilog make it possible for analog designers to provide a model of their IP to digital designers. SpinalHDL does not address this case, and is for digital designers to describe their own digital designs."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:54
+msgid "The Spinal development flow"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:56
+msgid "Once code is written in *SpinalHDL*, the tool can:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:58
+msgid "Generate VHDL, Verilog or SystemVerilog, to instantiate it in one of these languages or give it to any simulator or synthesis tool. There is no logic overhead, hierarchy and names are preserved, and it runs design checks during generation."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:62
+msgid "Boot a simulation using Verilator or another supported simulator."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:68
+msgid "As SpinalHDL is interoperable with VHDL and (System)Verilog, you can both instantiate SpinalHDL IPs in these language (using generated code) and instantiate IPs in these languages in SpinalHDL (using ``BlackBox``)."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:74
+msgid "SpinalHDL is *fully interoperable* with standard VHDL/Verilog-based EDA tools (simulators and synthesizers) as the output generated by the toolchain can be VHDL or Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:80
+msgid "Advantages of using SpinalHDL over VHDL / Verilog"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:82
+msgid "As SpinalHDL is based on a high-level language, it provides several advantages to improve your hardware coding:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:84
+msgid "**No more endless wiring** - Create and connect complex buses like AXI in one single line."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:85
+msgid "**Evolving capabilities** - Create your own bus definitions and abstraction layers."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:86
+msgid "**Reduce code size** - By a high factor, especially for wiring. This enables you to have a better overview of your code base, increase your productivity and create fewer headaches."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:87
+msgid "**Free and user friendly IDE** - Thanks to Scala tools for auto-completion, error highlighting, navigation shortcuts, and many others."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:88
+msgid "**Powerful and easy type conversions** - Bidirectional translation between any data type and bits. Useful when loading a complex data structure from a CPU interface."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:89
+msgid "**Design checks** - Early stage lints to check that there are eg no combinatorial loops / latches."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:90
+msgid "**Clock domain safety** - Early stage lints to inform you that there are no unintentional clock domain crossings."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:91
+msgid "**Generic design** - There are no restrictions to the genericity of your hardware description by using Scala constructs."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/faq.pot b/source/locale/gettext/SpinalHDL/Introduction/faq.pot
new file mode 100644
index 00000000000..df15af6e3c8
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/faq.pot
@@ -0,0 +1,117 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/faq.rst:2
+msgid "FAQ"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:5
+msgid "What is the overhead of SpinalHDL generated RTL compared to human written VHDL/Verilog?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:7
+msgid "The overhead is nil.  SpinalHDL generates the same HDL constructs found in human written VHDL/Verilog with no additional instantiated artifacts present in the resulting implementation due to its use.  This makes the overhead zero when comparing the generated HDL against handwritten HDL."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:12
+msgid "Due to the powerful expressive nature of the Scala/SpinalHDL languages, the design is more concise for a given complex hardware design and has strong type safety, strong HDL safety paradigms that result in fewer lines of code, able to achieve more functionality with fewer bugs."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:17
+msgid "SpinalHDL does not take a HLS approach and is not itself a HLS solution. Its goal is not to translate any arbitrary code into RTL, but to provide a powerful language to describe RTL and raise the abstraction level and increase code reuse at the level the designer is working."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:22
+msgid "What if SpinalHDL becomes unsupported in the future?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:24
+msgid "This question has two sides:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:26
+msgid "SpinalHDL generates VHDL/Verilog files, which means that SpinalHDL will be supported by all EDA tools for many decades."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:27
+msgid "If there is a bug in SpinalHDL and there is no longer support to fix it, it's not a deadly situation, because the SpinalHDL compiler is fully open source.  For simple issues, you may be able to fix the issue yourself within a few hours."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:30
+msgid "Consider how much time it takes for a commercial EDA vendor to fix issues or to add new features in their closed tools. Consider also your cost and time savings achieved when using SpinalHDL and the potential for your own entity to give back to the community some of this as engineering time, open-source contribution time or donations to the project to improve its future."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:36
+msgid "Does SpinalHDL keep comments in generated VHDL/verilog?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:38
+msgid "No, it doesn't. Generated files should be considered as a netlist. For example, when you compile C code, do you care about your comments in the generated assembly code?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:42
+msgid "Could SpinalHDL scale up to big projects?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:44
+msgid "Yes, some experiments were done, and it appears that generating hundreds of 3KLUT CPUs with caches takes around 12 seconds, which is a ridiculously short time compared to the time required to simulate or synthesize this kind of design."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:48
+msgid "How SpinalHDL came to be"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:50
+msgid "Between December 2014 and April 2016, it was as a personal hobby project.  But since April 2016 one person is working full time on it. Some people are also regularly contributing to the project."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:54
+msgid "Why develop a new language when there is VHDL/Verilog/SystemVerilog?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:56
+msgid "The :ref:`Foreword` is dedicated to this topic."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:59
+msgid "How to use an unreleased version of SpinalHDL (but committed on git)?"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:61
+msgid "First, you need to get the repository, if you haven't cloned it yet:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:68
+msgid "In the command above you can replace ``dev`` by the name of the branch you want to checkout. ``--depth 1`` prevents from downloading the repository history."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:71
+msgid "Then publish the code as it is in the directory fetched:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:77
+msgid "Here ``2.12.13`` is the Scala version used. The first two numbers must match the ones of the version used in your project. You can find it in your ``build.sbt`` and/or ``build.sc``:"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:87
+msgid "Then in your project, update the SpinalHDL version specified in your ``build.sbt`` or ``build.sc``: it should be set to ``dev`` instead of a version number."
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/faq.rst:99
+msgid "Here it is always ``dev`` no matter the branch you have checked out earlier."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Introduction/index.pot b/source/locale/gettext/SpinalHDL/Introduction/index.pot
new file mode 100644
index 00000000000..a736e9b61ef
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Introduction/index.pot
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Introduction/index.rst:2
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Introduction/index.rst:4
+msgid "This section introduces the SpinalHDL project: the language, and everything around it."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/index.pot b/source/locale/gettext/SpinalHDL/Legacy/index.pot
new file mode 100644
index 00000000000..1e4501aa3bc
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/index.rst:3
+msgid "Legacy"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware.pot
new file mode 100644
index 00000000000..38fb47766ce
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware.pot
@@ -0,0 +1,154 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:5
+msgid "Hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:8
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:10
+msgid "There is the Pinsec toplevel hardware diagram :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:16
+msgid "RISCV"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:18
+msgid "The RISCV is a 5 stage pipelined CPU with following features :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:21
+msgid "Instruction cache"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:22
+msgid "Single cycle Barrel shifter"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:23
+msgid "Single cycle MUL, 34 cycle DIV"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:24
+msgid "Interruption support"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:25
+msgid "Dynamic branch prediction"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:26
+msgid "Debug port"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:29
+msgid "AXI4"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:31
+msgid "As previously said, Pinsec integrates an AXI4 bus fabric. AXI4 is not the easiest bus to work with but has many advantages like:"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:34
+msgid "A flexible topology"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:35
+msgid "High bandwidth potential"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:36
+msgid "Potential out of order request completion"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:37
+msgid "Easy methods to meets clocks timings"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:38
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:59
+msgid "Standard used by many IP cores"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:39
+msgid "A handshake methodology that fits with SpinalHDL Stream."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:41
+msgid "From an Area utilization perspective, AXI4 is for sure not the lightest solution, but some techniques could dramatically reduce that concern :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:44
+msgid "Using Read-Only/Write-Only AXI4 variations where that is possible"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:45
+msgid "Introducing an Axi4-Shared variation where a new ARW channel is introduced to replace and combine AR and AW channels. This solution reduces resource usage by a factor of two for the address decoding and the address arbitration."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:46
+msgid "Timing relaxation is possible depending upon the interconnect implementation, and if all masters never stall the R/B channel (RREADY and BREADY are strapped to 1). Both xREADY signals can be removed by synthesis in this case, relaxing timings."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:47
+msgid "As the AXI4 spec suggests, the interconnect can expand the transactions ID by aggregating the corresponding input port ID. This allows the interconnect to have an infinite number of pending requests and also to support out of order completion with a negligible area cost (transaction ID expand)."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:49
+msgid "The Pinsec interconnect doesn't introduce latency cycles."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:52
+msgid "APB3"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:54
+msgid "In Pinsec, all peripherals implement an APB3 bus to be interfaced. The APB3 choice was motivated by following reasons :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:57
+msgid "Very simple bus (no burst)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:58
+msgid "Use very few resources"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:62
+msgid "Generate the RTL"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:64
+msgid "To generate the RTL, you have multiple solutions :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:66
+msgid "You can download the SpinalHDL source code, and then run :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:72
+msgid "Or you can create your own main into your own SBT project and then run it :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:86
+msgid "Currently, only the verilog version was tested in simulation and in FPGA because the last release of GHDL is not compatible with cocotb."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot
new file mode 100644
index 00000000000..ef4eef3fa4a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot
@@ -0,0 +1,359 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:7
+msgid "SoC toplevel (Pinsec)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:12
+msgid "``Pinsec`` is a little SoC designed for FPGA. It is available in the SpinalHDL library and some documentation could be find :ref:`there <pinsec_introduction>`"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:14
+msgid "Its toplevel implementation is an interesting example, because it is a mix some design patterns that make it very easy to modify. Adding a new master or a new peripheral to the bus fabric could be done with little effort."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:16
+msgid "The toplevel implementation could be consulted at the links here : `https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala <https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:19
+msgid "This is the Pinsec toplevel hardware diagram :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:25
+msgid "Defining all IO"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:47
+msgid "Clock and resets"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:49
+msgid "Pinsec has three clocks inputs :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:52
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:70
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:73
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:76
+msgid "axiClock"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:53
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:79
+msgid "vgaClock"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:54
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:82
+msgid "jtag.tck"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:56
+msgid "And one reset input :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:59
+msgid "asyncReset"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:61
+msgid "Which will finally give 5 ClockDomain (clock/reset couple) :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:66
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:67
+msgid "Clock"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:68
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:69
+msgid "resetCtrlClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:71
+msgid "Used by the reset controller, Flops of this clock domain are initialized by the FPGA bitstream"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:72
+msgid "axiClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:74
+msgid "Used by all component connected to the AXI and the APB interconnect"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:75
+msgid "coreClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:77
+msgid "The only difference with the axiClockDomain, is the fact that the reset could also be asserted by the debug module"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:78
+msgid "vgaClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:80
+msgid "Used by the VGA controller backend as a pixel clock"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:81
+msgid "jtagClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:83
+msgid "Used to clock the frontend of the JTAG controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:87
+msgid "Reset controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:89
+msgid "First we need to define the reset controller clock domain, which has no reset wire, but use the FPGA bitstream loading to setup flipflops."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:100
+msgid "Then we can define a simple reset controller under this clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:131
+msgid "Clock domain setup for each system"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:133
+msgid "Now that the reset controller is implemented, we can define clock domain for all sub-systems of Pinsec :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:157
+msgid "Also all the core system of Pinsec will be defined into a ``axi`` clocked area :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:166
+msgid "Main components"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:168
+msgid "Pinsec is constituted mainly by 4 main components :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:171
+msgid "One RISCV CPU"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:172
+msgid "One SDRAM controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:173
+msgid "One on chip memory"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:174
+msgid "One JTAG controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:177
+msgid "RISCV CPU"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:179
+msgid "The RISCV CPU used in Pinsec as many parametrization possibilities :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:226
+msgid "On chip RAM"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:228
+msgid "The instantiation of the AXI4 on chip RAM is very simple."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:230
+msgid "In fact it's not an AXI4 but an Axi4Shared, which mean that a ARW channel replace the AR and AW ones. This solution uses less area while being fully interoperable with full AXI4."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:242
+msgid "SDRAM controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:244
+msgid "First you need to define the layout and timings of your SDRAM device. On the DE1-SOC, the SDRAM device is an IS42x320D one."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:271
+msgid "Then you can used those definition to parametrize the SDRAM controller instantiation."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:284
+msgid "JTAG controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:286
+msgid "The JTAG controller could be used to access memories and debug the CPU from an PC."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:298
+msgid "Peripherals"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:300
+msgid "Pinsec has some integrated peripherals :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:303
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:309
+msgid "GPIO"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:304
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:322
+msgid "Timer"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:305
+msgid "UART"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:306
+msgid "VGA"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:324
+msgid "The Pinsec timer module consists of :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:327
+msgid "One prescaler"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:328
+msgid "One 32 bits timer"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:329
+msgid "Three 16 bits timers"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:331
+msgid "All of them are packed into the PinsecTimerCtrl component."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:338
+msgid "UART controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:340
+msgid "First we need to define a configuration for our UART controller :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:356
+msgid "Then we can use it to instantiate the UART controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:363
+msgid "VGA controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:365
+msgid "First we need to define a configuration for our VGA controller :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:379
+msgid "Then we can use it to instantiate the VGA controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:386
+msgid "Bus interconnects"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:388
+msgid "There is three interconnections components :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:391
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:409
+msgid "AXI4 crossbar"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:392
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:396
+msgid "AXI4 to APB3 bridge"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:393
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:471
+msgid "APB3 decoder"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:398
+msgid "This bridge will be used to connect low bandwidth peripherals to the AXI crossbar."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411
+msgid "The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. The concept of this factory is to create it, then call many function on it to configure it, and finaly call the ``build`` function to ask the factory to generate the corresponding hardware :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421
+msgid "First you need to populate slaves interfaces :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:433
+msgid "Then you need to populate a matrix of interconnections between slaves and masters (this sets up visibility) :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:446
+msgid "Then to reduce combinatorial path length and have a good design FMax, you can ask the factory to insert pipelining stages between itself a given master or slave :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:0
+msgid "``halfPipe`` / >> / << / >/->  in the following code are provided by the Stream bus library."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:0
+msgid "Some documentation could be find :ref:`there <stream>`. In short, it's just some pipelining and interconnection stuff."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:473
+msgid "The interconnection between the APB3 bridge and all peripherals is done via an APB3Decoder :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:490
+msgid "Misc"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:492
+msgid "To connect all toplevel IO to components, the following code is required :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:503
+msgid "And finally some connections between components are required like interrupts and core debug module resets"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/index.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/index.pot
new file mode 100644
index 00000000000..ce0756e9904
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/index.rst:3
+msgid "pinsec"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot
new file mode 100644
index 00000000000..5c6e43f8c78
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot
@@ -0,0 +1,98 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:7
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:15
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10
+msgid "This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available `here <https://github.com/SpinalHDL/VexRiscv>`__ and offers better perforance/area/features."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17
+msgid "Pinsec is the name of a little FPGA SoC fully written in SpinalHDL. Goals of this project are multiple :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:20
+msgid "Prove that SpinalHDL is a viable HDL alternative in non-trivial projects."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:21
+msgid "Show advantage of SpinalHDL meta-hardware description capabilities in a concrete project."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:22
+msgid "Provide a fully open source SoC."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:25
+msgid "Pinsec has followings hardware features:"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:28
+msgid "AXI4 interconnect for high speed busses"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:29
+msgid "APB3 interconnect for peripherals"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:30
+msgid "RISCV CPU with instruction cache, MUL/DIV extension and interrupt controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:31
+msgid "JTAG bridge to load binaries and debug the CPU"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:32
+msgid "SDRAM SDR controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:33
+msgid "On chip ram"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:34
+msgid "One UART controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:35
+msgid "One VGA controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:36
+msgid "Some timer module"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:37
+msgid "Some GPIO"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:39
+msgid "The toplevel code explanation could be find :ref:`there <pinsec_hardware_toplevel>`"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:42
+msgid "Board support"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:44
+msgid "A DE1-SOC FPGA project can be find `here <https://drive.google.com/drive/folders/0B-CqLXDTaMbKOGhIU0JGdHVVSk0?usp=sharing>`__ with some demo binaries."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/software.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/software.pot
new file mode 100644
index 00000000000..9472b0727f4
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/software.pot
@@ -0,0 +1,65 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:5
+msgid "Software"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:8
+msgid "RISCV tool-chain"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:10
+msgid "Binaries executed by the CPU can be defined in ASM/C/C++ and compiled by the GCC RISCV fork. Also, to load binaries and debug the CPU, an OpenOCD fork and RISCV GDB can be used."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:12
+msgid "RISCV tools : `https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status <https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:13
+msgid "OpenOCD fork : `https://github.com/Dolu1990/openocd_riscv <https://github.com/Dolu1990/openocd_riscv>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:14
+msgid "Software examples : `https://github.com/Dolu1990/pinsecSoftware <https://github.com/Dolu1990/pinsecSoftware>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:17
+msgid "OpenOCD/GDB/Eclipse  configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:19
+msgid "About the OpenOCD fork, there is the configuration file that could be used to connect the Pinsec SoC : `https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg <https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:21
+msgid "There is an example of arguments used to run the OpenOCD tool :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:27
+msgid "To debug with eclipse, you will need the Zylin plugin and then create an \"Zynlin embedded debug (native)\"."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:29
+msgid "Initialize commands :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/pinsec/software.rst:37
+msgid "Run commands :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Legacy/riscv.pot b/source/locale/gettext/SpinalHDL/Legacy/riscv.pot
new file mode 100644
index 00000000000..c14cd2ca0e1
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Legacy/riscv.pot
@@ -0,0 +1,165 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:3
+msgid "RiscV"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:6
+msgid "This page only documents the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this CPU and is available `here <https://github.com/SpinalHDL/VexRiscv>`_ and offers better performance/area/features."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:11
+msgid "Features"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:13
+msgid "RISC-V CPU"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:16
+msgid "Pipelined on 5 stages (Fetch Decode Execute0 Execute1 WriteBack)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:17
+msgid "Multiple branch prediction modes : (disable, static or dynamic)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:18
+msgid "Data path parameterizable between fully bypassed to fully interlocked"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:20
+msgid "Extensions"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:23
+msgid "One cycle multiplication"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:24
+msgid "34 cycle division"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:25
+msgid "Iterative shifter (N shift -> N cycles)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:26
+msgid "Single cycle shifter"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:27
+msgid "Interruption controller"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:28
+msgid "Debugging module (with JTAG bridge, openOCD port and GDB)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:29
+msgid "Instruction cache with wrapped burst memory interface, one way"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:30
+msgid "Data cache with instructions to evict/flush the whole cache or a given address, one way"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:32
+msgid "Performance/Area (on cyclone II)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:35
+msgid "small core -> 846 LE, 0.6 DMIPS/Mhz"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:36
+msgid "debug module (without JTAG) -> 240 LE"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:37
+msgid "JTAG Avalon master -> 238 LE"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:38
+msgid "big core with MUL/DIV/Full shifter/I$/Interrupt/Debug -> 2200 LE, 1.15 DMIPS/Mhz, at least 100 Mhz (with default synthesis option)"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:41
+msgid "Base FPGA project"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:43
+msgid "You can find a DE1-SOC project which integrate two instance of the CPU with MUL/DIV/Full shifter/I$/Interrupt/Debug there :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:45
+msgid "https://drive.google.com/drive/folders/0B-CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:47
+msgid "CPU/JTAG/VGA IP are pre-generated. Quartus Prime : 15.1."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:51
+msgid "How to generate the CPU VHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:54
+msgid "This avalon version of the CPU isn't present in recent releases of SpinalHDL. Please consider the `VexRiscv <https://github.com/SpinalHDL/VexRiscv>`_ instead."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:63
+msgid "How to debug"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:65
+msgid "You can find the openOCD fork here :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:67
+msgid "https://github.com/Dolu1990/openocd_riscv"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:69
+msgid "An example target configuration file could be find here :"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:71
+msgid "https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:73
+msgid "Then you can use the RISCV GDB."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:76
+msgid "Todo"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:79
+msgid "Documentation"
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:80
+msgid "Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths."
+msgstr ""
+
+#: ../../SpinalHDL/Legacy/riscv.rst:82
+msgid "Contact spinalhdl@gmail.com for more information"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot
new file mode 100644
index 00000000000..348220f4bc5
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot
@@ -0,0 +1,82 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:3
+msgid "AHB-Lite3"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6
+msgid "Configuration and instanciation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8
+msgid "First each time you want to create a AHB-Lite3 bus, you will need a configuration object. This configuration object is an ``AhbLite3Config`` and has following arguments :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:14
+msgid "Parameter name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:15
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:16
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:17
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:18
+msgid "addressWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:19
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:23
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:21
+msgid "Width of HADDR (byte granularity)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:22
+msgid "dataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:25
+msgid "Width of HWDATA and HRDATA"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:28
+msgid "There is in short how the AHB-Lite3 bus is defined in the SpinalHDL library :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:58
+msgid "There is a short example of usage :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:74
+msgid "Variations"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:76
+msgid "There is an AhbLite3Master variation. The only difference is the absence of the ``HREADYOUT`` signal. This variation should only be used by masters while the interconnect and slaves use ``AhbLite3``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot
new file mode 100644
index 00000000000..e994607388a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot
@@ -0,0 +1,136 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:3
+msgid "Apb3"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:5
+msgid "The AMBA3-APB bus is commonly used to interface low bandwidth peripherals."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8
+msgid "Configuration and instanciation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:10
+msgid "First each time you want to create a APB3 bus, you will need a configuration object. This configuration object is an ``Apb3Config`` and has following arguments :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:16
+msgid "Parameter name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:17
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:18
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:19
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:78
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:20
+msgid "addressWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:21
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:25
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:29
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:23
+msgid "Width of PADDR (byte granularity)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:24
+msgid "dataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:27
+msgid "Width of PWDATA and PRDATA"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:28
+msgid "selWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:30
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:31
+msgid "With of PSEL"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:32
+msgid "useSlaveError"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:33
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:34
+msgid "false"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:35
+msgid "Specify the presence of PSLVERROR"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:38
+msgid "There is in short how the APB3 bus is defined in the SpinalHDL library :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:54
+msgid "There is a short example of usage :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:70
+msgid "Functions and operators"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:76
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:77
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:79
+msgid "X >> Y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:81
+msgid "Connect X to Y. Address of Y could be smaller than the one of X"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:82
+msgid "X << Y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:84
+msgid "Do the reverse of the >> operator"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot
new file mode 100644
index 00000000000..1bdc04de4d3
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot
@@ -0,0 +1,263 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:2
+msgid "Axi4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:4
+msgid "The AXI4 is a high bandwidth bus defined by ARM."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7
+msgid "Configuration and instanciation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:9
+msgid "First each time you want to create a AXI4 bus, you will need a configuration object. This configuration object is an ``Axi4Config`` and has following arguments :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:11
+msgid "Note : useXXX specify if the bus has XXX signal present."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:16
+msgid "Parameter name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:17
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:114
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:18
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:19
+msgid "addressWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:20
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:23
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:26
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:29
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:22
+msgid "dataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:25
+msgid "idWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:28
+msgid "userWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:31
+msgid "useId"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:32
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:35
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:38
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:41
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:44
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:47
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:50
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:53
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:56
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:59
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:62
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:65
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:68
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:33
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:36
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:39
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:42
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:45
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:48
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:51
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:54
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:57
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:60
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:63
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:66
+msgid "true"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:34
+msgid "useRegion"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:37
+msgid "useBurst"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:40
+msgid "useLock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:43
+msgid "useCache"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:46
+msgid "useSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:49
+msgid "useQos"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:52
+msgid "useLen"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:55
+msgid "useLast"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:58
+msgid "useResp"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:61
+msgid "useProt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:64
+msgid "useStrb"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:67
+msgid "useUser"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:69
+msgid "false"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:72
+msgid "There is in short how the AXI4 bus is defined in the SpinalHDL library :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:89
+msgid "There is a short example of usage :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:106
+msgid "Variations"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:108
+msgid "There is 3 other variation of the Axi4 bus :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:115
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:136
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:116
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:147
+msgid "Axi4ReadOnly"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:117
+msgid "Only AR and R channels are present"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:118
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:144
+msgid "Axi4WriteOnly"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:119
+msgid "Only AW, W and B channels are present"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:120
+msgid "Axi4Shared"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:0
+msgid "This variation is a library initiative."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:0
+msgid "It use 4 channels, W, B ,R and also a new one which is named AWR."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:0
+msgid "The AWR channel can be used to transmit AR and AW transactions. To dissociate them, a signal ``write`` is present."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:0
+msgid "The advantage of this Axi4Shared variation is to use less area, especially in the interconnect."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:128
+msgid "Functions and operators"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:134
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:135
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:137
+msgid "X >> Y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:139
+msgid "Connect X to Y. Able infer default values as specified in the AXI4 specification, and also to adapt some width in a safe manner."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:140
+msgid "X << Y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:142
+msgid "Do the reverse of the >> operator"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:143
+msgid "X.toWriteOnly"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:145
+msgid "Return an Axi4WriteOnly bus drive by X"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:146
+msgid "X.toReadOnly"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:148
+msgid "Return an Axi4ReadOnly bus drive by X"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot
new file mode 100644
index 00000000000..f88023131c7
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot
@@ -0,0 +1,116 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:3
+msgid "AvalonMM"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:5
+msgid "The AvalonMM bus fit very well in FPGA. It is very flexible :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:7
+msgid "Able of the same simplicity than APB"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:8
+msgid "Better for than AHB in many application that need bandwidth because AvalonMM has a mode that decouple read response from commands (reduce latency read latency impact)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:9
+msgid "Less performance than AXI but use much less area (Read and write command use the same handshake channel. The master don't need to store address of pending request to avoid Read/Write hazard)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:12
+msgid "Configuration and instanciation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:14
+msgid "The ``AvalonMM`` Bundle has a construction argument ``AvalonMMConfig``. Because of the flexible nature of the Avalon bus, the ``AvalonMMConfig`` as many configuration elements. For more information the Avalon spec could be find on the intel website."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:46
+msgid "This configuration class has also some functions :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:52
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:69
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:53
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:70
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:54
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:71
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:55
+msgid "getReadOnlyConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:56
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:59
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:73
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:76
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:79
+msgid "AvalonMMConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:57
+msgid "Return a similar configuration but with all write feature disabled"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:58
+msgid "getWriteOnlyConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:60
+msgid "Return a similar configuration but with all read feature disabled"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:63
+msgid "This configuration companion object has also some functions to provide some ``AvalonMMConfig`` templates :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:72
+msgid "fixed(addressWidth,dataWidth,readLatency)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:74
+msgid "Return a simple configuration with fixed read timings"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:75
+msgid "pipelined(addressWidth,dataWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:77
+msgid "Return a configuration with variable latency read (readDataValid)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:78
+msgid "bursted(addressWidth,dataWidth,burstCountWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:80
+msgid "Return a configuration with variable latency read and burst capabilities"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/index.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/index.pot
new file mode 100644
index 00000000000..0a47c40c11e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/index.rst:3
+msgid "Bus"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot
new file mode 100644
index 00000000000..ce2f14f4571
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot
@@ -0,0 +1,37 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:3
+msgid "Tilelink"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:6
+msgid "Configuration and instanciation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:8
+msgid "There is a short example to define two non coherent tilelink bus instance and connect them:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:22
+msgid "Here is the same as above, but with coherency channels"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:43
+msgid "Those above where for the hardware instanciation, the thing is that it is the simple / easy part. When things goes into SoC / memory coherency, you kind of need an additional layer to negociate / propagate parameters all around. That's what tilelink.fabric.Node is about."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot
new file mode 100644
index 00000000000..8d4bfb8a9ab
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot
@@ -0,0 +1,169 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:3
+msgid "tilelink.fabric.Node"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:5
+msgid "tilelink.fabric.Node is an additional layer over the regular tilelink hardware instanciation which handle negociation and parameters propagation at a SoC level."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:7
+msgid "It is mostly based on the Fiber API, which allows to create elaboration time fibers (user-space threads), allowing to schedule future parameter propagation / negociation and hardware elaboration."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:9
+msgid "A Node can be created in 3 ways :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:11
+msgid "tilelink.fabric.Node.down() : To create a node which can connect downward (toward slaves), so it would be used in a CPU / DMA / bridges agents"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:12
+msgid "tilelink.fabric.Node() : To create an intermediate nodes"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:13
+msgid "tilelink.fabric.Node.up() : To create a node which can connect upward (toward masters), so it would be used in peripherals / memories / bridges agents"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:15
+msgid "Nodes mostly have the following attributes :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:17
+msgid "bus : Handle[tilelink.Bus]; the hardware instance of the bus"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:18
+msgid "m2s.proposed : Handle[tilelink.M2sSupport]; The set of features which is proposed by the upward connections"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:19
+msgid "m2s.supported : Handle[tilelink.M2sSupport] : The set of feature supported by the downward connections"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:20
+msgid "m2s.parameter : Handle[tilelink.M2sParameter] : The final bus parameter"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:22
+msgid "You can note that they all are Handles. Handle is a way in SpinalHDL to have share a value between fibers. If a fiber read a Handle while this one has no value yet, it will block the execution of that fiber until another fiber provide a value to the Handle."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:24
+msgid "There is also a set of attribues like m2s, but reversed (named s2m) which specify the parameters for the transactions initiated by the slave side of the interconnect (ex memory coherency)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:26
+msgid "There is two talks which where introducing the tilelink.fabric.Node. Those talk may not exactly follow the actual syntax, they are still follow the concepts :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:28
+msgid "Introduction : https://youtu.be/hVi9xOGuuek"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:29
+msgid "In depth : https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-96d7eb89e907"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:32
+msgid "Example Toplevel"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:34
+msgid "Here is an example of a simple fictive SoC toplevel :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:46
+msgid "You can also define intermediate nodes in the interconnect as following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:70
+msgid "Example GpioFiber"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:72
+msgid "GpioFiber is a simple tilelink peripheral which can read / drive a 32 bits tristate array."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:116
+msgid "Example RamFiber"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:118
+msgid "RamFiber is the integration layer of a regular tilelink Ram component."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:146
+msgid "Example CpuFiber"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:148
+msgid "CpuFiber is an fictive example of a master integration."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:195
+msgid "One particularity of Tilelink, is that it assumes a master will not emit requests to a unmapped memory space. To allow a master to identify what memory access it is allowed to do, you can use the spinal.lib.system.tag.MemoryConnection.getMemoryTransfers tool as following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:206
+msgid "If you run this in the Cpu's fiber, in the following soc :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:228
+msgid "You will get :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:236
+msgid "\"through=\" specify the chain of address transformations done to reach the target."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:237
+msgid "\"SM\" means SizeMapping(address, size)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:238
+msgid "\"OT\" means OffsetTransformer(offset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:240
+msgid "Note that you can also add PMA (Physical Memory Attributes) to nodes and retreives them via this getMemoryTransfers utilities."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:242
+msgid "The currently defined PMA are :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:258
+msgid "The getMemoryTransfers utility rely on a dedicated SpinalTag :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:270
+msgid "That SpinalTag can be used applied to both ends of a given memory bus connection to keep this connection discoverable at elaboration time, creating a graph of MemoryConnection. One good thing about it is that is is bus agnostic, meaning it isn't tilelink specific."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:274
+msgid "Example WidthAdapter"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:276
+msgid "The width adapter is a simple example of bridge."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/index.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/index.pot
new file mode 100644
index 00000000000..903e09ae862
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Com/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Com/index.rst:3
+msgid "Com"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/spiXdr.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/spiXdr.pot
new file mode 100644
index 00000000000..c52d8623bcb
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Com/spiXdr.pot
@@ -0,0 +1,65 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:3
+msgid "SPI XDR"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:5
+msgid "There is a SPI controller which support :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:7
+msgid "half/full duplex"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:8
+msgid "single/dual/quad SPI"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:9
+msgid "SDR/DDR/.. data rate"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:12
+msgid "You can find its APB3 implementation here :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:14
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/68b6158700fc2440ea7980406f927262c004faca/lib/src/main/scala/spinal/lib/com/spi/xdr/Apb3SpiXdrMasterCtrl.scala#L43"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:17
+msgid "Configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:19
+msgid "Here is an example."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:50
+msgid "Software Driver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:52
+msgid "See :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:54
+msgid "https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/spi.h https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/spiDemo/src/main.c"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/uart.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/uart.pot
new file mode 100644
index 00000000000..8ca2c00a0c1
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Com/uart.pot
@@ -0,0 +1,176 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:3
+msgid "UART"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:5
+msgid "The UART protocol could be used, for instance, to emit and receive RS232 / RS485 frames."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:7
+msgid "There is an example of an 8 bits frame, with no parity and one stop bit :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:12
+msgid "Bus definition"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:27
+msgid "UartCtrl"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:29
+msgid "An Uart controller is implemented in the library. This controller has the specificity to use a sampling window to read the ``rxd`` pin and then to using an majority vote to filter its value."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:35
+msgid "IO name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:36
+msgid "direction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:37
+#: ../../SpinalHDL/Libraries/Com/uart.rst:64
+msgid "type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:38
+#: ../../SpinalHDL/Libraries/Com/uart.rst:65
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:39
+msgid "config"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:40
+msgid "in"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:41
+msgid "UartCtrlConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:42
+msgid "Used to set the clock divider/parity/stop/data length of the controller"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:43
+msgid "write"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:44
+msgid "slave"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:45
+msgid "Stream[Bits]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:46
+msgid "Stream port used to request a frame transmission"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:47
+msgid "read"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:48
+#: ../../SpinalHDL/Libraries/Com/uart.rst:52
+msgid "master"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:49
+msgid "Flow[Bits]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:50
+msgid "Flow port used to receive decoded frames"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:51
+msgid "uart"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:53
+msgid "Uart"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:54
+msgid "Interface to the real world"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:57
+msgid "The controller could be instantiated via an ``UartCtrlGenerics`` configuration object :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:63
+msgid "Attribute"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:66
+msgid "dataWidthMax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:67
+#: ../../SpinalHDL/Libraries/Com/uart.rst:70
+#: ../../SpinalHDL/Libraries/Com/uart.rst:73
+#: ../../SpinalHDL/Libraries/Com/uart.rst:76
+#: ../../SpinalHDL/Libraries/Com/uart.rst:79
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:68
+msgid "Maximal number of bit inside a frame"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:69
+msgid "clockDividerWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:71
+msgid "Width of the internal clock divider"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:72
+msgid "preSamplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:74
+msgid "Specify how many samplingTick are drop at the beginning of a UART baud"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:75
+msgid "samplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:77
+msgid "Specify how many samplingTick are used to sample ``rxd`` values in the middle of the UART baud"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:78
+msgid "postSamplingSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:80
+msgid "Specify how many samplingTick are drop at the end of a UART baud"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot
new file mode 100644
index 00000000000..4fa7916d43e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot
@@ -0,0 +1,662 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:3
+msgid "USB device"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:5
+msgid "Here exists a USB device controller in the SpinalHDL library."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:7
+msgid "A few bullet points to summarise support:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:9
+msgid "Implemented to allow a CPU to configure and manage the endpoints"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:10
+msgid "A internal ram which store the endpoints states and transactions descriptors"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:11
+msgid "Up to 16 endpoints (for virtualy no price)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:12
+msgid "Support USB host full speed (12Mbps)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:13
+msgid "Test on linux using its own driver (https://github.com/SpinalHDL/linux/blob/dev/drivers/usb/gadget/udc/spinal_udc.c)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:14
+msgid "Bmb memory interace for the configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:15
+msgid "Require a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:16
+msgid "The controller frequency is not restricted"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:17
+msgid "No external phy required"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:19
+msgid "Linux gadget tested and functional :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:21
+msgid "Serial connection"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:22
+msgid "Ethernet connection"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:23
+msgid "Mass storage (~8 Mbps on ArtyA7 linux)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:25
+msgid "Deployments :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:27
+msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:28
+msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:32
+msgid "Architecture"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:34
+msgid "The controller is composed of :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:36
+msgid "A few control registers"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:37
+msgid "A internal ram used to store the endpoint status, the transfer descriptors and the endpoint 0 SETUP data."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:39
+msgid "A linked list of descriptors for each endpoint in order to handle the USB IN/OUT transactions and data."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:41
+msgid "The endpoint 0 manage the IN/OUT transactions like all the other endpoints but has some additional hardware to manage the SETUP transactions :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:43
+msgid "Its linked list is cleared on each setup transactions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:44
+msgid "The data from the SETUP transaction is stored in a fixed location (SETUP_DATA)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:45
+msgid "It has a specific interrupt flag for SETUP transactions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:48
+msgid "Registers"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:50
+msgid "Note that all registers and memories of the controller are only accessible in 32 bits word access, bytes access isn't supported."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:53
+msgid "FRAME (0xFF00)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "usbFrameId"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "RO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "31-0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "Current usb frame id"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:63
+msgid "ADDRESS (0xFF04)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid "address"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "WO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid "6-0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid "The device will only listen at tokens with the specified address This field is automaticaly cleared on usb reset events"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+msgid "enable"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+msgid "8"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+msgid "Enable the USB address filtering if set"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid "trigger"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid "9"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid "Set the enable (see above) on the next EP0 IN tocken completion Cleared by the hardware after any EP0 completion"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:77
+msgid "The idea here is to keep the whole register cleared until a USB SET_ADDRESS setup packet is received on EP0. At that moment, you can set the address and the trigger field, then provide the IN zero length descriptor to EP0 to finalise the SET_ADDRESS sequance. The controller will then automaticaly turn on the address filtering at the completion of that descriptor."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:82
+msgid "INTERRUPT (0xFF08)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:84
+msgid "Individual bits of this register can be cleared by writing '1' in them. Reading this register returns the current interrupt status."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+msgid "endpoints"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "W1C"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "15-0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+msgid "Raised when an endpoint generates an interrupt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+msgid "reset"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "16"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+msgid "Raised when a USB reset occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+msgid "ep0Setup"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "17"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+msgid "Raised when endpoint 0 receives a setup transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+msgid "suspend"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid "18"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+msgid "Raised when a USB suspend occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+msgid "resume"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "19"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+msgid "Raised when a USB resume occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "disconnect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "20"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "Raised when a USB disconnect occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:104
+msgid "HALT (0xFF0C)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:106
+msgid "This register allows placement of a single endpoint into a dormant state in order to ensure atomicity of CPU operations, allowing to do things as read/modify/write on the endpoint registers and descriptors. The peripheral will return NAK if the given endpoint is addressed by the usb host while halt is enabled and the endpoint is enabled."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+msgid "endpointId"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "3-0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+msgid "The endpoint you want to put in sleep"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "When set halt is active, when clear endpoint is unhalted."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid "effective enable"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid "5"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid "After setting the enable, you need to wait for this bit to be set by the hardware itself to ensure atomicity"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:121
+msgid "CONFIG (0xFF10)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+msgid "pullupSet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+msgid "SO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+msgid "Write '1' to enable the USB device pullup on the dp pin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+msgid "pullupClear"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+msgid "interruptEnableSet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "2"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+msgid "Write '1' to let the present and future interrupt happening"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+msgid "interruptEnableClear"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid "3"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:136
+msgid "INFO (0xFF20)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "ramSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "The internal ram will have (1 << this) bytes"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:145
+msgid "ENDPOINTS (0x0000 - 0x003F)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:147
+msgid "The endpoints status are stored at the begining of the internal ram over one 32 bits word each."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "RW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+msgid "If not set, the endpoint will ignore all the trafic"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+msgid "stall"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+msgid "If set, the endpoint will always return STALL status"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+msgid "nack"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+msgid "If set, the endpoint will always return NACK status"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid "dataPhase"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid "Specify the IN/OUT data PID used. '0' => DATA0. This field is also updated by the controller."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+msgid "head"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "15-4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+msgid "Specify the current descriptor head (linked list). 0 => empty list, byte address = this << 4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+msgid "isochronous"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "maxPacketSize"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "31-22"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:169
+msgid "To get a endpoint responsive you need :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:171
+msgid "Set its enable flag to 1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:173
+msgid "Then the there is a few cases : - Either you have the stall or nack flag set, and so, the controller will always respond with the corresponding responses - Either, for EP0 setup request, the controller will not use descriptors, but will instead write the data into the SETUP_DATA register, and ACK - Either you have a empty linked list (head==0) in which case it will answer NACK - Either you have at least one descriptor pointed by head, in which case it will execute it and ACK if all was going smooth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:180
+msgid "SETUP_DATA (0x0040 - 0x0047)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:182
+msgid "When endpoint 0 receives a SETUP transaction, the data of the transaction will be stored in this location."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:185
+msgid "Descriptors"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:187
+msgid "Descriptors allows to specify how an endpoint needs to handle the data phase of IN/OUT transactions. They are stored in the internal ram, can be linked together via their linked lists and need to be aligned on 16 bytes boundaries"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "offset"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "Specify the current progress in the transfer (in byte)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "code"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "19-16"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "0xF => in progress, 0x0 => success"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "next"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "Pointer to the next descriptor 0 => nothing, byte address = this << 4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "length"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "31-16"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "Number of bytes allocated for the data field"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "direction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "'0' => OUT, '1' => IN"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "interrupt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "If set, the completion of the descriptor will generate an interrupt."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid "completionOnFull"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid "Normally, a descriptor completion only occurs when a USB transfer is smaller than the maxPacketSize. But if this field is set, then when the descriptor become full is also a considered as a completion event. (offset == length)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "data1OnCompletion"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "force the endpoint dataPhase to DATA1 on the completion of the descriptor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:215
+msgid "data"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:215
+msgid "..."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:218
+msgid "Note, if the controller receives a frame where the IN/OUT does not match the descriptor IN/OUT, the frame will be ignored."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:220
+msgid "Also, to initialise a descriptor, the CPU should set the code field to 0xF"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:223
+msgid "Usage"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot
new file mode 100644
index 00000000000..68e329026df
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot
@@ -0,0 +1,121 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:3
+msgid "USB OHCI"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:5
+msgid "Here exists a USB OHCi controller (host) in the SpinalHDL library."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:7
+msgid "A few bullet points to summarise support:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:9
+msgid "It follow the `OpenHCI Open Host Controller Interface Specification for USB` specification (OHCI)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:10
+msgid "It is compatible with the upstream linux / uboot OHCI drivers already. (there is also an OHCI driver on tinyUSB)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:11
+msgid "This provides USB host full speed and low speed capabilities (12Mbps and 1.5Mbps)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:12
+msgid "Tested on linux and uboot"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:13
+msgid "One controller can host multiple ports (up to 16)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:14
+msgid "Bmb memory interface for DMA accesses"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:15
+msgid "Bmb memory interace for the configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:16
+msgid "Requires a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:17
+msgid "The controller frequency is not restricted"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:18
+msgid "No external phy required"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:20
+msgid "Devices tested and functional :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:22
+msgid "Mass storage (~8 Mbps on ArtyA7 linux)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:23
+msgid "Keyboard / Mouse"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:24
+msgid "Audio output"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:25
+msgid "Hub"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:27
+msgid "Limitations :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:29
+msgid "Some USB hub (had one so far) do not like having a full speed host with low speed devices attached."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:30
+msgid "Some modern devices will not work on USB full speed (ex :  Gbps ethernet adapter)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:31
+msgid "Require memory coherency with the CPU (or the cpu need to be able to flush its data cache in the driver)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:33
+msgid "Deployments :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:35
+msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:36
+msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:39
+msgid "Usage"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot
new file mode 100644
index 00000000000..ab0357ab5f5
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot
@@ -0,0 +1,87 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:3
+msgid "QSysify"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:5
+msgid "QSysify is a tool which is able to generate a QSys IP (tcl script) from a SpinalHDL component by analysing its IO definition. It currently implement the following interfaces features :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:7
+msgid "Master/Slave AvalonMM"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:8
+msgid "Master/Slave APB3"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:9
+msgid "Clock domain input"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:10
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:67
+msgid "Reset output"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:11
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:60
+msgid "Interrupt input"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:12
+msgid "Conduit (Used in last resort)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:15
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:17
+msgid "In the case of a UART controller :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:30
+msgid "The following  ``main`` will generate the Verilog and the QSys TCL script with io.bus as an AvalonMM and io.uart as a conduit :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:48
+msgid "tags"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:50
+msgid "Because QSys require some information that are not specified in the SpinalHDL hardware specification, some tags should be added to interface:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:53
+msgid "AvalonMM / APB3"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:74
+msgid "Adding new interface support"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:76
+msgid "Basically, the QSysify tool can be setup with a list of interface ``emitter`` `(as you can see here) <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L12>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:78
+msgid "You can create your own emitter by creating a new class extending `QSysifyInterfaceEmiter <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L24>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/quartus_flow.pot b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/quartus_flow.pot
new file mode 100644
index 00000000000..226250cc3d0
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/quartus_flow.pot
@@ -0,0 +1,78 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:3
+msgid "QuartusFlow"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:5
+msgid "A compilation flow is an Altera-defined sequence of commands that use a combination of command-line executables. A full compilation flow launches all Compiler modules in sequence to synthesize, fit, analyze final timing, and generate a device programming file."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:8
+msgid "Tools in `this file <https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/eda/altera/QuartusFlow.scala>`__ help you get rid of redundant Quartus GUI."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:11
+msgid "For a single rtl file"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:13
+msgid "The object ``spinal.lib.eda.altera.QuartusFlow`` can automatically report the used area and maximum frequency of a single rtl file."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:16
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:54
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:30
+msgid "The code above will create a new Quartus project with ``TopLevel.vhd``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:33
+msgid "This operation will remove the folder ``workspacePath``!"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:36
+msgid "The ``family`` and ``device`` values are passed straight to the Quartus CLI as parameters. Please check the Quartus documentation for the correct value to use in your project."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:39
+msgid "Tip"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:41
+msgid "To test a component that has too many pins, set them as ``VIRTUAL_PIN``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:49
+msgid "For an existing project"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:51
+msgid "The class ``spinal.lib.eda.altera.QuartusProject`` can automatically find configuration files in an existing project. Those are used for compilation and programming the device."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:56
+msgid "Specify the path that contains your project files like ``.qpf`` and ``.cdf``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:68
+msgid "Remember to save the ``.cdf`` of your project before calling ``prj.program()``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/EDA/index.pot b/source/locale/gettext/SpinalHDL/Libraries/EDA/index.pot
new file mode 100644
index 00000000000..6db9fded61e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/EDA/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/EDA/index.rst:3
+msgid "EDA"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Graphics/colors.pot b/source/locale/gettext/SpinalHDL/Libraries/Graphics/colors.pot
new file mode 100644
index 00000000000..3ec7ab6a4bc
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Graphics/colors.pot
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Graphics/colors.rst:3
+msgid "Colors"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/colors.rst:6
+msgid "RGB"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/colors.rst:8
+msgid "You can use an Rgb bundle to model colors in hardware. This Rgb bundle take as parameter an RgbConfig classes which specify the number of bits for each channels :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/colors.rst:22
+msgid "Those classes could be used as following :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Graphics/index.pot b/source/locale/gettext/SpinalHDL/Libraries/Graphics/index.pot
new file mode 100644
index 00000000000..621ce8b8bd0
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Graphics/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Graphics/index.rst:3
+msgid "Graphics"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Graphics/vga.pot b/source/locale/gettext/SpinalHDL/Libraries/Graphics/vga.pot
new file mode 100644
index 00000000000..4e7c0b27880
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Graphics/vga.pot
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:5
+msgid "VGA"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:8
+msgid "VGA bus"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:10
+msgid "An VGA bus definition is available via the Vga bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:25
+msgid "VGA timings"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:27
+msgid "VGA timings could be modeled in hardware by using an VgaTimings bundle :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:47
+msgid "VGA controller"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:49
+msgid "An VGA controller is available. Its definition is the following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:67
+msgid "``frameStart`` is a signals that pulse one cycle at the beginning of each new frame."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:68
+msgid "``pixels`` is a stream of color used to feed the VGA interface when needed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:69
+msgid "``error`` is high when a transaction on the pixels is needed, but nothing is present."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/IO/index.pot b/source/locale/gettext/SpinalHDL/Libraries/IO/index.pot
new file mode 100644
index 00000000000..28c0729c673
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/IO/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/IO/index.rst:3
+msgid "IO"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/IO/readableOpenDrain.pot b/source/locale/gettext/SpinalHDL/Libraries/IO/readableOpenDrain.pot
new file mode 100644
index 00000000000..3696abd522e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/IO/readableOpenDrain.pot
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/IO/readableOpenDrain.rst:3
+msgid "ReadableOpenDrain"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/readableOpenDrain.rst:5
+msgid "The ReadableOpenDrain bundle is defined as following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/readableOpenDrain.rst:18
+msgid "Then, as a master, you can use the ``read`` signal to read the outside value and use the ``write`` to set the value that you want to drive on the output."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/readableOpenDrain.rst:20
+msgid "There is an example of usage :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/IO/tristate.pot b/source/locale/gettext/SpinalHDL/Libraries/IO/tristate.pot
new file mode 100644
index 00000000000..4c871dc821c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/IO/tristate.pot
@@ -0,0 +1,86 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:4
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:22
+msgid "TriState"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:6
+msgid "Tri-state signals are difficult to handle in many cases:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:8
+msgid "They are not really kind of digital things"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:9
+msgid "And except for IO, they aren't used for digital design"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:10
+msgid "The tristate concept doesn't fit naturally in the SpinalHDL internal graph."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:12
+msgid "SpinalHDL provides two different abstractions for tristate signals. The ``TriState`` bundle and :ref:`section-analog_and_inout` signals. Both serve different purposes:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:15
+msgid "TriState should be used for most purposes, especially within a design. The bundle contains an additional signal to carry the current direction."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:16
+msgid "``Analog`` and ``inout`` should be used for drivers on the device boundary and in some other special cases. See the referenced documentation page for more details."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:18
+msgid "As stated above, the recommended approach is to use ``TriState`` within a design. On the top-level the ``TriState`` bundle is then assigned to an analog inout to get the synthesis tools to infer the correct I/O driver. This can be done automatically done via the :ref:`InOutWrapper <section-analog_and_inout>` or manually if needed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:24
+msgid "The TriState bundle is defined as following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:38
+msgid "A master can use the ``read`` signal to read the outside value, the ``writeEnable`` to enable the output, and finally use ``write`` to set the value that is driven on the output."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:41
+msgid "There is an example of usage:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:56
+msgid "TriStateArray"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:58
+msgid "In some case, you need to have the control over the output enable of each individual pin (Like for GPIO). In this range of cases, you can use the TriStateArray bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:60
+msgid "It is defined as following :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:73
+msgid "It is the same than the TriState bundle, except that the ``writeEnable`` is an Bits to control each output buffer."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:75
+msgid "There is an example of usage :"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot b/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot
new file mode 100644
index 00000000000..34156f1642e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot
@@ -0,0 +1,93 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:7
+msgid "Plic Mapper"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:9
+msgid "The PLIC Mapper defines the register generation and access for a PLIC (Platform Level Interrupt Controller."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:12
+msgid "``PlicMapper.apply``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:14
+msgid "``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : Seq[PlicGateway], targets : Seq[PlicTarget])``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:16
+msgid "args for PlicMapper:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:18
+msgid "**bus**: bus to which this ctrl is attached"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:19
+msgid "**mapping**: a mapping configuration (see above)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:20
+msgid "**gateways**: a sequence of PlicGateway (interrupt sources) to generate the bus access control"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:21
+msgid "**targets**: the sequence of PlicTarget (eg. multiple cores) to generate the bus access control"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:24
+msgid "It follows the interface given by riscv: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:26
+msgid "As of now, two memory mappings are available :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:29
+msgid "``PlicMapping.sifive``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:30
+msgid "Follows the SiFive PLIC mapping (eg. `E31 core complex Manual <https://sifive.cdn.prismic.io/sifive/9169d157-0d50-4005-a289-36c684de671b_e31_core_complex_manual_21G1.pdf>`_ ), basically a full fledged PLIC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:33
+msgid "``PlicMapping.light``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:34
+msgid "This mapping generates a lighter PLIC, at the cost of some missing optional features:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36
+msgid "no reading the intrerrupt's priority"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37
+msgid "no reading the interrupts's pending bit (must use the claim/complete mechanism)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38
+msgid "no reading the target's threshold"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:40
+msgid "The rest of the registers & logic is generated."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Misc/index.pot b/source/locale/gettext/SpinalHDL/Libraries/Misc/index.pot
new file mode 100644
index 00000000000..e176d910195
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Misc/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Misc/index.rst:3
+msgid "Misc"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot b/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot
new file mode 100644
index 00000000000..fc9582d3dae
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot
@@ -0,0 +1,149 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:5
+msgid "Plugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:8
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:10
+msgid "For some design, instead of implementing your Component's hardware directly in it, you may instead want to compose its hardware by using some sorts of Plugins. This can provide a few key features :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:13
+msgid "You can extend the features of your component by adding new plugins in its parameters. For instance adding Floating point support in a CPU."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:14
+msgid "You can swap various implementations of the same functionality just by using another set of plugins. For instance one implementation of a CPU multiplier may fit well on some FPGA, while others may fit well on ASIC."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:15
+msgid "It avoid the very very very large hand written toplevel syndrom where everything has to be connected manualy. Instead plugins can discover their neighborhood by looking/using the software interface of other plugins."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:17
+msgid "VexRiscv and NaxRiscv projects are an example of this. Their are CPUs which have a mostly empty toplevel, and their hardware parts are injected using plugins. For instance :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:20
+msgid "PcPlugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:21
+msgid "FetchPlugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:22
+msgid "DecoderPlugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:23
+msgid "RegFilePlugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:24
+msgid "IntAluPlugin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:25
+msgid "..."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:27
+msgid "And those plugins will then negociate/propagate/interconnect to each others via their pool of services."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:29
+msgid "While VexRiscv use a strict synchronous 2 phase system (setup/build callback), NaxRiscv uses a more flexible approach which uses the spinal.core.fiber API to fork elaboration threads which can interlock each others in order to ensure a workable elaboration ordering."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:31
+msgid "The Plugin API provide a NaxRiscv like system to define composable components using plugins."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:34
+msgid "Execution order"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:36
+msgid "The main idea is that you have multiple 2 executions phases :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:38
+msgid "Setup phase, in which plugins can lock/retain each others. The idea is not to start negociation / elaboration yet."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:39
+msgid "Build phase, in which plugins can negociation / elaboration hardware."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:41
+msgid "The build phase will not start before all FiberPlugin are done with their setup phase."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:61
+msgid "Simple example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:63
+msgid "Here is a simple dummy example with a SubComponent which will be composed using 2 plugins :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:102
+msgid "Such TopLevel would generate the following Verilog code :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:131
+msgid "Note each \"during build\" fork an elaboration thread, the DriverPlugin.logic thread execution will be blocked on the \"sp\" evaluation until the StatePlugin.logic execution is done."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:135
+msgid "Interlocking / Ordering"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:137
+msgid "Plugins can interlock each others using Retainer instances. Each plugin instance has a built in lock which can be controlled using retain/release functions."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:140
+msgid "Here is an example based on the above `Simple example` but that time, the DriverPlugin will increment the StatePlugin.logic.signal by an amount set by other plugins (SetupPlugin in our case). And to ensure that the DriverPlugin doesn't generate the hardware too early, the SetupPlugin uses the DriverPlugin.retain/release functions."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:207
+msgid "Here is the generated verilog"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:236
+msgid "Clearly, those examples are overkilled for what they do, the idea in general is more about :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:238
+msgid "Negociate / create interfaces between plugins (ex jump / flush ports)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:239
+msgid "Schedule the elaboration (ex decode / dispatch specification)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:240
+msgid "Provide a distributed framework which can scale up (minimal hardcoding)"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Pipeline/index.pot b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/index.pot
new file mode 100644
index 00000000000..d4f97f75dd2
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Pipeline/index.rst:3
+msgid "Pipeline"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot
new file mode 100644
index 00000000000..338439d40b1
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot
@@ -0,0 +1,668 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:3
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:5
+msgid "spinal.lib.misc.pipeline provides a pipelining API. The main advantages over manual pipelining are :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:7
+msgid "You don't have to predefine all the signal elements needed for the entire staged system upfront. You can create and consume stagable signals in a more ad hoc fashion as your design requires - without needing to refactor all the intervening stages to know about the signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:8
+msgid "Signals of the pipeline can utilize the powerful parametrization capabilities of SpinalHDL and be subject to optimization/removal if a specific design build does not require a particular parametrized feature, without any need to modify the staging system design or project code base in a significant way."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:9
+msgid "Manual retiming is much easier, as you don't have to handle the registers / arbitration manualy"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10
+msgid "Manage the arbitration by itself"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:12
+msgid "The API is composed of 4 main things :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:14
+msgid "Node : which represents a layer in the pipeline"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:15
+msgid "Link : which allows to connect nodes to each other"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:16
+msgid "Builder : which will generate the hardware required for a whole pipeline"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:17
+msgid "Payload : which are used to retrieve hardware signals on nodes along the pipeline"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:19
+msgid "It is important to understand that Payload isn't a hardware data/signal instance, but a key to retrieve a data/signal on nodes along the pipeline, and that the pipeline builder will then automatically interconnect/pipeline every occurrence of a given Payload between nodes."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:21
+msgid "Here is an example to illustrate :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:27
+msgid "Here is a video about this API :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:29
+msgid "https://www.youtube.com/watch?v=74h_-FMWWIM"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:32
+msgid "Simple example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:34
+msgid "Here is a simple example which only uses the basics of the API :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:78
+msgid "This will produce the following hardware :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:83
+msgid "Here is a simulation wave :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:105
+msgid "Here is the same example but using more of the API :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:148
+msgid "Payload"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:150
+msgid "Payload objects are used to refer to data which can go through the pipeline. Technicaly speaking, Payload is a HardType which has a name and is used as a \"key\" to retrieve the signals in a certain pipeline stage."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:163
+msgid "Note that I got used to name the Payload instances using uppercase. This is to make it very explicit that the thing isn't a hardware signal, but are more like a \"key/type\" to access things."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:166
+msgid "Node"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:168
+msgid "Node mostly hosts the valid/ready arbitration signals, and the hardware signals required for all the Payload values going through it."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:170
+msgid "You can access its arbitration via :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:177
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:238
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:268
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:390
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:427
+msgid "API"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:178
+msgid "Access"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:179
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:239
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:269
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:391
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:428
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:180
+msgid "node.valid"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:181
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:184
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:187
+msgid "RW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:182
+msgid "Is the signal which specifies if a transaction is present on the node. It is driven by the upstream. Once asserted, it must only be de-asserted the cycle after which either both valid and ready or node.cancel are high. valid must not depend on ready."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:183
+msgid "node.ready"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:185
+msgid "Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpresure. The signal has no meaning when there is no transaction (node.valid being deasserted)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:186
+msgid "node.cancel"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:188
+msgid "Is the signal which specifies if the node's transaction in being canceled from the pipeline. It is driven by the downstream. The signal has no meaning when there is no transaction (node.valid being deasserted)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:189
+msgid "node.isValid"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:190
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:193
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:196
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:199
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:202
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:207
+msgid "RO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:191
+msgid "node.valid's read only accessor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:192
+msgid "node.isReady"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:194
+msgid "node.ready's read only accessor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:195
+msgid "node.isCancel"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:197
+msgid "node.cancel's read only accessor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:198
+msgid "node.isFiring"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200
+msgid "True when the node transaction is successfuly moving futher (valid && ready && !cancel). Useful to commit state changes."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201
+msgid "node.isMoving"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:203
+msgid "True when the node transaction will not be present anymore on the node (starting from the next cycle), either because downstream is ready to take the transaction, or because the transaction is canceled from the pipeline. (valid && (ready || cancel)). Useful to \"reset\" states."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:206
+msgid "node.isCanceling"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:208
+msgid "True when the node transaction is being canceled. Meaning that it will not appear anywhere in the pipeline in future cycles."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:210
+msgid "Note that the node.valid/node.ready signals follows the same conventions than the :doc:`../stream`'s ones ."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:212
+msgid "The Node controls (valid/ready/cancel) and status (isValid, isReady, isCancel, isFiring, ...) signals are created on demande. So for instance you can create pipeline with no backpresure by never refering to the ready signal. That's why it is important to use status signals when you want to read the status of something and only use control signals when you to drive something."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215
+msgid "Here is a list of arbitration cases you can have on a node. valid/ready/cancel define the state we are in, while isFiring/isMoving result of those :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "valid"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "ready"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "cancel"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "isFiring"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "isMoving"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "X"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+msgid "No transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+msgid "Going through"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+msgid "Blocked"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "Canceled"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:230
+msgid "Note that if you want to model things like for instance a CPU stage which can block and flush stuff, take a look a the CtrlLink, as it provides the API to do such things."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:232
+msgid "You can access signals referenced by a Payload via:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:240
+msgid "node(Payload)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:241
+msgid "Return the corresponding hardware signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:242
+msgid "node(Payload, Any)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:243
+msgid "Same as above, but include a second argument which is used as a \"secondary key\". This eases the construction of multi-lane hardware. For instance, when you have a multi issue CPU pipeline, you can use the lane Int id as secondary key"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:244
+msgid "node.insert(Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:245
+msgid "Return a new Payload instance which is connected to the given Data hardware signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:261
+msgid "While you can manualy drive/read the arbitration/data of the first/last stage of your pipeline, there is a few utilities to connect its boundaries."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:270
+msgid "node.arbitrateFrom(Stream[T]])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:271
+msgid "Drive a node arbitration from a stream."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:272
+msgid "node.arbitrateFrom(Flow[T]])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:273
+msgid "Drive a node arbitration from the Flow."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:274
+msgid "node.arbitrateTo(Stream[T]])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:275
+msgid "Drive a stream arbitration from the node."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:276
+msgid "node.arbitrateTo(Flow[T]])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:277
+msgid "Drive a Flow arbitration from the node."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:278
+msgid "node.driveFrom(Stream[T]])((Node, T) => Unit)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:279
+msgid "Drive a node from a stream. The provided lambda function can be use to connect the data"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:280
+msgid "node.driveFrom(Flow[T]])((Node, T) => Unit)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:281
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:285
+msgid "Same as above but for Flow"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:282
+msgid "node.driveTo(Stream[T]])((T, Node) => Unit)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:283
+msgid "Drive a stream from the node. The provided lambda function can be use to connect the data"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:284
+msgid "node.driveTo(Flow[T]])((T, Node) => Unit)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:305
+msgid "In order to reduce verbosity, there is a set of implicit conversions between Payload toward their data representation which can be used when you are in the context of a Node :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:314
+msgid "You can also use those implicit conversions by importing them :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:327
+msgid "There is also an API which alows you to create new Area which provide the whole API of a given node instance (including implicit convertion) without import :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:338
+msgid "Such feature is very useful when you have parametrizable pipeline locations for your hardware (see retiming example)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:342
+msgid "Links"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:344
+msgid "There is few different Links already implemented (but you could also create your own custom one). The idea of Links is to connect two nodes together in various ways. They generally have a `up` Node and a `down` Node."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:349
+msgid "DirectLink"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:351
+msgid "Very simple, it connect two nodes with wires only. Here is an example :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:361
+msgid "StageLink"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:363
+msgid "This connect two nodes using registers on the data / valid signals and some arbitration on the ready."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:371
+msgid "S2mLink"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:373
+msgid "This connect two nodes using registers on the ready signal, which can be useful to improve backpresure combinatorial timings."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:380
+msgid "CtrlLink"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:382
+msgid "This is kind of a special Link, as connect two nodes with optional flow control / bypass logic. Its API should be flexible enough to implement a CPU stage with it."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:384
+msgid "Here is its flow control API (The Bool arguments enable the features) :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:392
+msgid "haltWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:393
+msgid "Allows to block the current transaction (clear up.ready down.valid)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:394
+msgid "throwWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:395
+msgid "Allows to cancel the current transaction from the pipeline (clear down.valid and make the transaction driver forget its current state)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:396
+msgid "forgetOneWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:397
+msgid "Allows to request the upstream to forget its current transaction  (but doesn't clear the down.valid)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:398
+msgid "ignoreReadyWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:399
+msgid "Allows to ignore the downstream ready (set up.ready)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:400
+msgid "duplicateWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:401
+msgid "Allows to duplicate the current transaction (clear up.ready)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:402
+msgid "terminateWhen(Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:403
+msgid "Allows to hide the current transaction from downstream (clear down.valid)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:405
+msgid "Also note that if you want to do flow control in a conditional scope (ex in a when statement), you can call the following functions :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:407
+msgid "haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), throwIt()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:419
+msgid "You can retrieve which nodes are connected to the Link using node.up / node.down."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:421
+msgid "The CtrlLink also provide an API to access Payload :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:429
+msgid "link(Payload)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:430
+msgid "Same as Link.down(Payload)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:431
+msgid "link(Payload, Any)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:432
+msgid "Same as Link.down(Payload, Any)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:433
+msgid "link.insert(Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:434
+msgid "Same as Link.down.insert(Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:435
+msgid "link.bypass(Payload)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436
+msgid "Allows to conditionaly override a Payload value between link.up -> link.down. This can be used to fix data hazard in CPU pipelines for instance."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:455
+msgid "Note that if you create a CtrlLink without node arguments, it will create its own nodes internally."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:466
+msgid "Other Links"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:468
+msgid "There is also a JoinLink / ForkLink implemented."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:471
+msgid "Your custom Link"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:473
+msgid "You can implement your custom links by implementing the Link base class."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:486
+msgid "But that API may change a bit, as it is still fresh."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:489
+msgid "Builder"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:491
+msgid "To generate the hardware of your pipeline, you need to give a list of all the Links used in your pipeline."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:506
+msgid "There is also a set of \"all in one\" builders that you can instanciate to help yourself."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:508
+msgid "For instance there is the NodesBuilder class which can be used to create sequentially staged pipelines :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:521
+msgid "Composability"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:523
+msgid "One good thing about the API is that it easily allows to compose a pipeline with multiple parallel things. What i mean by \"compose\" is that sometime the pipeline you need to design has parallel processing to do."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:525
+msgid "Imagine you need to do floating point multiplication on 4 pairs of numbers (to later sum them). If those 4 pairs a provided at the same time by a single stream of data, then you don't want 4 different pipelines to multiply them, instead you want to process them all in parallel in the same pipeline."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:527
+msgid "The example below show a pattern which composes a pipeline with multiple lanes to process them in parallel."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:571
+msgid "This will produce the following data path (assuming lanesCount = 2), abitration not being shown :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:578
+msgid "Retiming / Variable lenth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:580
+msgid "Sometime you want to design a pipeline, but you don't really know where the critical paths will be and what the right balance between stages is. And often you can't rely on the synthesis tool doing a good job with automatic retiming."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:582
+msgid "So, you kind of need a easy way to move the logic of your pipeline around."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:584
+msgid "Here is how it can be done with this pipelining API :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:646
+msgid "If then you generate this component like this :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:659
+msgid "You will get a 4 stages separated by 3 layer of flip flop doing your processing :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:664
+msgid "Note the generated hardware verilog is kinda clean (by my standards at least :P) :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:779
+msgid "Also, you can easily tweak how many stages and where you want the processing to be done, for instance you may want to move the inversion hardware in the same stage as the adder. This can be done the following way :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:793
+msgid "Then you may want to remove the output register stage :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:809
+msgid "Simple CPU example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:811
+msgid "Here is a simple/stupid 8 bits CPU example with :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:813
+msgid "3 stages (fetch, decode, execute)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:814
+msgid "embedded fetch memory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:815
+msgid "add / jump / led /delay instructions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:886
+msgid "Here is a simple testbench which implement a loop which will make the led counting up."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/binarySystem.pot b/source/locale/gettext/SpinalHDL/Libraries/binarySystem.pot
new file mode 100644
index 00000000000..f1b1dc57211
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/binarySystem.pot
@@ -0,0 +1,332 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:3
+msgid "BinarySystem"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:6
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:8
+msgid "Here things have nothing to do with HDL, but they are very common in digital systems, In particular, the algorithm reference model is widely used. In addition, it is also used in build testbench."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:16
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:17
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:18
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:20
+msgid "**String**.asHex"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:21
+msgid "HexString to BigInt == BigInt(string, 16)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:22
+#: ../../SpinalHDL/Libraries/binarySystem.rst:25
+#: ../../SpinalHDL/Libraries/binarySystem.rst:28
+#: ../../SpinalHDL/Libraries/binarySystem.rst:31
+#: ../../SpinalHDL/Libraries/binarySystem.rst:103
+#: ../../SpinalHDL/Libraries/binarySystem.rst:109
+#: ../../SpinalHDL/Libraries/binarySystem.rst:112
+#: ../../SpinalHDL/Libraries/binarySystem.rst:115
+msgid "BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:23
+msgid "**String**.asDec"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:24
+msgid "Decimal String to BigInt == BigInt(string, 10)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:26
+msgid "**String**.asOct"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:27
+msgid "Octal String to BigInt == BigInt(string, 8)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:29
+msgid "**String**.asBin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:30
+msgid "Binary String to BigInt == BigInt(string, 2)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:35
+msgid "**Byte|Int|Long|BigInt**.hexString()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:36
+msgid "to HEX String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:37
+#: ../../SpinalHDL/Libraries/binarySystem.rst:40
+#: ../../SpinalHDL/Libraries/binarySystem.rst:43
+#: ../../SpinalHDL/Libraries/binarySystem.rst:46
+#: ../../SpinalHDL/Libraries/binarySystem.rst:49
+#: ../../SpinalHDL/Libraries/binarySystem.rst:52
+#: ../../SpinalHDL/Libraries/binarySystem.rst:85
+#: ../../SpinalHDL/Libraries/binarySystem.rst:88
+#: ../../SpinalHDL/Libraries/binarySystem.rst:91
+#: ../../SpinalHDL/Libraries/binarySystem.rst:94
+msgid "String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:38
+msgid "**Byte|Int|Long|BigInt**.octString()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:39
+msgid "to Oct String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:41
+msgid "**Byte|Int|Long|BigInt**.binString()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:42
+msgid "to Bin String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:44
+msgid "**Byte|Int|Long|BigInt**.hexString(bitSize)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:45
+msgid "first align to bit Size, then to HEX String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:47
+msgid "**Byte|Int|Long|BigInt**.octString(bitSize)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:48
+msgid "first align to bit Size, then to Oct String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:50
+msgid "**Byte|Int|Long|BigInt**.binString(bitSize)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:51
+msgid "first align to bit Size, then to Bin String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:56
+msgid "**Byte|Int|Long|BigInt**.toBinInts()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:57
+msgid "to BinaryList"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:58
+#: ../../SpinalHDL/Libraries/binarySystem.rst:61
+#: ../../SpinalHDL/Libraries/binarySystem.rst:64
+#: ../../SpinalHDL/Libraries/binarySystem.rst:67
+#: ../../SpinalHDL/Libraries/binarySystem.rst:70
+#: ../../SpinalHDL/Libraries/binarySystem.rst:73
+#: ../../SpinalHDL/Libraries/binarySystem.rst:76
+#: ../../SpinalHDL/Libraries/binarySystem.rst:79
+msgid "List[Int]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:59
+msgid "**Byte|Int|Long|BigInt**.toDecInts()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:60
+msgid "to DecimalList"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:62
+msgid "**Byte|Int|Long|BigInt**.toOctInts()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:63
+msgid "to OctalList"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:65
+msgid "**Byte|Int|Long|BigInt**.toBinInts(num)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:66
+msgid "to BinaryList, align to num size and fill 0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:68
+msgid "**Byte|Int|Long|BigInt**.toDecInts(num)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:69
+msgid "to DecimalList, align to num size and fill 0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:71
+msgid "**Byte|Int|Long|BigInt**.toOctInts(num)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:72
+msgid "to OctalList, align to num size and fill 0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:74
+msgid "**\"3F2A\"**.hexToBinInts"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:75
+msgid "Hex String to BinaryList"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:77
+msgid "**\"3F2A\"**.hexToBinIntsAlign"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:78
+msgid "Hex String to BinaryList Align to times of 4"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:83
+msgid "**List(1,0,1,0,...)**.binIntsToHex"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:84
+msgid "BinaryList to HexString"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:86
+msgid "**List(1,0,1,0,...)**.binIntsToOct"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:87
+msgid "BinaryList to OctString"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:89
+msgid "**List(1,0,1,0,...)**.binIntsToHexAlignHigh"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:90
+msgid "BinaryList size align to times of 4 (fill 0) then to HexString"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:92
+msgid "**List(1,0,1,0,...)**.binIntsToOctAlignHigh"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:93
+msgid "BinaryList size align to times of 3 (fill 0) then to HexString"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:95
+msgid "**List(1,0,1,0,...)**.binIntsToInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:96
+msgid "BinaryList (maxSize 32) to Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:97
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:98
+msgid "**List(1,0,1,0,...)**.binIntsToLong"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:99
+msgid "BinaryList (maxSIZE 64) to Long"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:100
+msgid "Long"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:101
+msgid "**List(1,0,1,0,...)**.binIntsToBigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:102
+msgid "BinaryList (size no restrictions) to BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:107
+msgid "**Int**.toBigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:108
+msgid "32.toBigInt == BigInt(32)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:110
+msgid "**Long**.toBigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:111
+msgid "3233113232L.toBigInt == BigInt(3233113232L)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:113
+msgid "**Byte**.toBigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:114
+msgid "8.toByte.toBigInt == BigInt(8.toByte)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:118
+msgid "String to Int/Long/BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:134
+msgid "Int/Long/BigInt to String"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:155
+msgid "Int/Long/BigInt to Binary-List"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:174
+msgid "align to a fixed width"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:187
+msgid "Binary-List to Int/Long/BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:215
+msgid "BigInt enricher"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/bus_slave_factory.pot b/source/locale/gettext/SpinalHDL/Libraries/bus_slave_factory.pot
new file mode 100644
index 00000000000..2c5f8d0b059
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/bus_slave_factory.pot
@@ -0,0 +1,246 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:7
+msgid "Bus Slave Factory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:12
+msgid "In many situation it's needed to implement a bus register bank. The ``BusSlaveFactory`` is a tool that provide an abstract and smooth way to define them."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:14
+msgid "To see capabilities of the tool, an simple example use the Apb3SlaveFactory variation to implement an :ref:`memory mapped UART <memory_mapped_uart>`. There is also another example with an :ref:`Timer <timer>` which contain a memory mapping function."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:16
+msgid "You can find more documentation about the internal implementation of the ``BusSlaveFactory`` tool :ref:`there <bus_slave_factory_implementation>`"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:19
+msgid "Functionality"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:21
+msgid "There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:22
+msgid "Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:28
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:29
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:30
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:31
+msgid "busDataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:32
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:33
+msgid "Return the data width of the bus"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:34
+msgid "read(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:36
+msgid "When the bus read the ``address``\\ , fill the response with ``that`` at ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:37
+msgid "write(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:39
+msgid "When the bus write the ``address``\\ , assign ``that`` with bus's data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:40
+msgid "onWrite(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:42
+msgid "Call ``doThat`` when a write transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:43
+msgid "onRead(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:45
+msgid "Call ``doThat`` when a read transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:46
+msgid "nonStopWrite(that,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:48
+msgid "Permanently assign ``that`` by the bus write data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:49
+msgid "readAndWrite(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:51
+msgid "Make ``that`` readable and writable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:52
+msgid "readMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Create the memory mapping to read ``that`` from 'address'."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "If ``that`` is bigger than one word it extends the register on followings addresses"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:56
+msgid "writeMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Create the memory mapping to write ``that`` at 'address'."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:60
+msgid "createWriteOnly(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:61
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:64
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:62
+msgid "Create a write only register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:63
+msgid "createReadWrite(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:65
+msgid "Create a read write register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:66
+msgid "createAndDriveFlow(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:67
+msgid "Flow[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:68
+msgid "Create a writable Flow register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:69
+msgid "drive(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:71
+msgid "Drive ``that`` with a register writable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:72
+msgid "driveAndRead(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:74
+msgid "Drive ``that`` with a register writable and readable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:75
+msgid "driveFlow(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:77
+msgid "Emit on ``that`` a transaction when a write happen at ``address`` by using data placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "readStreamNonBlocking(that,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "address,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "validBitOffset,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "payloadBitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Read ``that`` and consume the transaction when a read happen at ``address``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "valid <= validBitOffset bit"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "doBitsAccumulationAndClearOnRead(that,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Instantiate an internal register which at each cycle do :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "reg := reg | that"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Then when a read occur, the register is cleared. This register is readable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/fiber.pot b/source/locale/gettext/SpinalHDL/Libraries/fiber.pot
new file mode 100644
index 00000000000..2befcd4098c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/fiber.pot
@@ -0,0 +1,133 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:7
+msgid "Fiber framework"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:10
+msgid "This framework is not expected to be used for general RTL generation and targets large system design management and code generation. It is currently used as toplevel integration tool in SaxonSoC."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:13
+msgid "Currently in developpement."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:15
+msgid "The Fiber to run the hardware elaboration in a out of order manner, a bit similarly to Makefile, where you can define rules and dependencies which will then be solved when you run a make command. It is very similar to the Scala Future feature."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:17
+msgid "Using this framework can complicate simple things but provide some strong features for complex cases :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:19
+msgid "You can define things before even knowing all their requirements, ex : instantiating a interruption controller, before knowing how many interrupt signal lines you need"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:21
+msgid "Abstract/lazy/partial SoC architecture definition allowing the creation of SoC template for further specialisations"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:22
+msgid "Automatic requirement negotiation between multiple agents in a decentralized way, ex : between masters and slaves of a memory bus"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:24
+msgid "The framework is mainly composed of :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:26
+msgid "``Handle[T]``, which can be used later to store a value of type ``T``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:27
+msgid "``handle.load`` which allow to set the value of a handle (will reschedule all tasks waiting on it)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:28
+msgid "``handle.get``, which return the value of the given handle. Will block the task execution if that handle isn't loaded yet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:29
+msgid "``Handle{ /*code*/ }``, which fork a new task which will execute the given code. The result of that code will be loaded into the Handle"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:30
+msgid "``soon(handle)``, which allows the current task to announce that it will load ``handle`` with a value (used for scheduling)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:34
+msgid "Simple dummy example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:36
+msgid "There is a simple example :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:59
+msgid "Its runtime will be :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:61
+msgid "create a and b"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:62
+msgid "fork the calculator task, but is blocked when executing a.get"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:63
+msgid "fork the printer task, but is blocked when executing calculator.get"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:64
+msgid "load a and b, which reschedule the calculator task (as it was waiting on a)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:65
+msgid "calculator do its a + b sum, and load its Handle with that result, which reschedule the printer task"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:66
+msgid "printer task print its stuff"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:67
+msgid "everything done"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:70
+msgid "So, the main point of that example is to show that we kind of overcome the sequential execution of things, as a and b are loaded after the definition of the calculator."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:74
+msgid "Handle[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:76
+msgid "Handle[T] are a bit like scala's Future[T], they allow to talk about something before it is even existing, and wait on it."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:87
+msgid "soon(handle)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fiber.rst:89
+msgid "In order to maintain a proper graph of dependencies between tasks and Handle, a task can specify in advance that it will load a given handle. This is very usefull in case of a generation starvation/deadlock for SpinalHDL to report accuratly where is the issue."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/flow.pot b/source/locale/gettext/SpinalHDL/Libraries/flow.pot
new file mode 100644
index 00000000000..749c33cf463
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/flow.pot
@@ -0,0 +1,246 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/flow.rst:3
+msgid "Flow"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:6
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:8
+msgid "The Flow interface is a simple valid/payload protocol which means the slave can't halt the bus. It could be used to represent data coming from an UART controller, requests to write an on-chip memory, etc."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:15
+msgid "Signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:16
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:17
+msgid "Driver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:18
+#: ../../SpinalHDL/Libraries/flow.rst:40
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:19
+msgid "Don't care when"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:20
+msgid "valid"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:21
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:22
+#: ../../SpinalHDL/Libraries/flow.rst:27
+msgid "Master"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:23
+msgid "When high => payload present on the interface"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:25
+msgid "payload"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:26
+#: ../../SpinalHDL/Libraries/flow.rst:74
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:28
+msgid "Content of the transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:29
+msgid "valid is low"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:33
+msgid "Functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:39
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:41
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:42
+msgid "Latency"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:43
+msgid "Flow(type : Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+#: ../../SpinalHDL/Libraries/flow.rst:44
+msgid "Create a Flow of a given type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:45
+#: ../../SpinalHDL/Libraries/flow.rst:50
+#: ../../SpinalHDL/Libraries/flow.rst:55
+#: ../../SpinalHDL/Libraries/flow.rst:70
+msgid "Flow[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:47
+msgid "master/slave Flow(type : Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "Initialized with corresponding in/out setup"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:52
+msgid "x.m2sPipe()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "Return a Flow drived by x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "through a register stage that cut valid/payload paths"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:56
+#: ../../SpinalHDL/Libraries/flow.rst:66
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "x << y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "y >> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:59
+msgid "Connect y to x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:61
+#: ../../SpinalHDL/Libraries/flow.rst:71
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "x <-< y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "y >-> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:64
+msgid "Connect y to x through a m2sPipe"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:67
+msgid "x.throwWhen(cond : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "Return a Flow connected to x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:0
+msgid "When cond is high, transaction are dropped"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:72
+msgid "x.toReg()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:73
+msgid "Return a register which is loaded with ``payload`` when valid is high"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:76
+msgid "x.setIdle()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:77
+msgid "Set the Flow in an Idle state: ``valid`` is ``False`` and don't care about ``payload``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:80
+msgid "x.push(newPayload: T)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:81
+msgid "Assign a new valid payload to the Flow. ``valid`` is set to ``True``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:86
+msgid "Code example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:94
+msgid "Simulation Support"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:100
+msgid "Class"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:101
+msgid "Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:102
+msgid "FlowMonitor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:103
+msgid "Used for both master and slave sides, calls function with payload if Flow transmits data."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:104
+msgid "FlowDriver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:105
+msgid "Testbench master side, drives values by calling function to apply value (if available). Function must return if value was available. Supports random delays."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:106
+msgid "ScoreboardInOrder"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/flow.rst:107
+msgid "Often used to compare reference/dut data"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/fragment.pot b/source/locale/gettext/SpinalHDL/Libraries/fragment.pot
new file mode 100644
index 00000000000..16d3a4dea40
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/fragment.pot
@@ -0,0 +1,179 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/fragment.rst:3
+msgid "Fragment"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:6
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:8
+msgid "The ``Fragment`` bundle is the concept of transmitting a \"big\" thing by using multiple \"small\" fragments. For examples :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:11
+msgid "A picture transmitted with width*height transaction on a ``Stream[Fragment[Pixel]]``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:12
+msgid "An UART packet received from an controller without flow control could be transmitted on a ``Flow[Fragment[Bits]]``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:13
+msgid "An AXI read burst could be carried by an ``Stream[Fragment[AxiReadResponse]]``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:15
+msgid "Signals defined by the ``Fragment`` bundle are :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:21
+msgid "Signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:22
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:23
+msgid "Driver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:24
+#: ../../SpinalHDL/Libraries/fragment.rst:51
+#: ../../SpinalHDL/Libraries/fragment.rst:77
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:25
+msgid "fragment"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:26
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:27
+#: ../../SpinalHDL/Libraries/fragment.rst:31
+msgid "Master"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:28
+msgid "The \"payload\" of the current transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:29
+msgid "last"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:30
+#: ../../SpinalHDL/Libraries/fragment.rst:53
+#: ../../SpinalHDL/Libraries/fragment.rst:56
+#: ../../SpinalHDL/Libraries/fragment.rst:59
+#: ../../SpinalHDL/Libraries/fragment.rst:62
+#: ../../SpinalHDL/Libraries/fragment.rst:65
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:32
+msgid "High when the fragment is the last of the current packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:35
+msgid "As you can see with this specification and precedent example, the ``Fragment`` concept doesn't specify how transaction are transmitted (You can use Stream,Flow or any other communication protocol). It only add enough information (\\ ``last``\\ ) to know if the current transaction is the first one, the last one or one in the middle of a given packet."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:38
+msgid "The protocol didn't carry a \\'first\\' bit because it can be generated at any place by doing \\'RegNextWhen(bus.last, bus.fire) init(True)\\'"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:41
+msgid "Functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:43
+msgid "For ``Stream[Fragment[T]]`` and ``Flow[Fragment[T]]``\\ , following function are presents :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:49
+#: ../../SpinalHDL/Libraries/fragment.rst:75
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:50
+#: ../../SpinalHDL/Libraries/fragment.rst:76
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:52
+msgid "x.first"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:54
+msgid "Return True when the next or the current transaction is/would be the first of a packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:55
+msgid "x.tail"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:57
+msgid "Return True when the next or the current transaction is/would be not the first of a packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:58
+msgid "x.isFirst"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:60
+msgid "Return True when an transaction is present and is the first of a packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:61
+msgid "x.isTail"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:63
+msgid "Return True when an transaction is present and is the not the first/last of a packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:64
+msgid "x.isLast"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:66
+msgid "Return True when an transaction is present and is the last of a packet"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:69
+msgid "For ``Stream[Fragment[T]]``\\ , following function are also accessible :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:78
+msgid "x.insertHeader(header : T)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:79
+msgid "Stream[Fragment[T]]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fragment.rst:80
+msgid "Add the ``header`` to each packet on ``x`` and return the resulting bus"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/fsm.pot b/source/locale/gettext/SpinalHDL/Libraries/fsm.pot
new file mode 100644
index 00000000000..f840ba1a2fd
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/fsm.pot
@@ -0,0 +1,249 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:7
+msgid "State machine"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:12
+msgid "In SpinalHDL you can define your state machine like in VHDL/Verilog, by using enumerations and switch/case statements. But in SpinalHDL you can also use a dedicated syntax."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:14
+msgid "The state machine below is implemented in the following examples:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:20
+msgid "Style A:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:54
+msgid "Style B:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:92
+msgid "StateMachine"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:94
+msgid "``StateMachine`` is the base class. It manages the logic of the FSM."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:102
+msgid "``StateMachine`` also provides some accessors:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:108
+#: ../../SpinalHDL/Libraries/fsm.rst:189
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:109
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:110
+#: ../../SpinalHDL/Libraries/fsm.rst:190
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:111
+msgid "``isActive(state)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:112
+#: ../../SpinalHDL/Libraries/fsm.rst:115
+msgid "``Bool``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:113
+msgid "Returns ``True`` when the state machine is in the given state"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:114
+msgid "``isEntering(state)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:116
+msgid "Returns ``True`` when the state machine is entering the given state"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:119
+msgid "Entry point"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:121
+msgid "A state can be defined as the entry point of the state machine by extending the EntryPoint trait:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:127
+msgid "Or by using ``setEntry(state)``:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:135
+msgid "Transitions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:137
+msgid "Transitions are represented by ``goto(nextState)``, which schedules the state machine to be in ``nextState`` the next cycle."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:138
+msgid "``exit()`` schedules the state machine to be in the boot state the next cycle (or, in ``StateFsm``, to exit the current nested state machine)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:140
+msgid "These two functions can be used inside state definitions (see below) or using ``always { yourStatements }``, which always applies ``yourStatements``, with a priority over states."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:144
+msgid "State encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:146
+msgid "By default the FSM state vector will be encoded using the native encoding of the language/tools the RTL is generated for (Verilog or VHDL). This default can be overriden by using the ``setEncoding(...)`` method which either takes a ``SpinalEnumEncoding`` or varargs of type ``(State, BigInt)`` for a custom encoding."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:150
+msgid "Using a ``SpinalEnumEncoding``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:159
+msgid "Using a custom encoding"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:169
+msgid "When using the ``graySequential`` enum encoding, no check is done to verify that the FSM transitions only produce single-bit changes in the state vector. The encoding is done according to the order of state definitions and the designer must ensure that only valid transitions are done if needed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:174
+msgid "States"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:176
+msgid "Multiple kinds of states can be used:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:178
+msgid "``State`` (the base one)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:179
+msgid "``StateDelay``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:180
+msgid "``StateFsm``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:181
+msgid "``StateParallelFsm``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:183
+msgid "Each of them provides the following functions to define the logic associated to them:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:196
+msgid "``yourStatements`` is applied when the state machine is not in ``state`` and will be in ``state`` the next cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:202
+msgid "``yourStatements`` is applied when the state machine is in ``state`` and will be in another state the next cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:208
+msgid "``yourStatements`` is applied when the state machine is in ``state``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:214
+msgid "``yourStatements`` is executed when the state machine will be in ``state`` the next cycle (even if it is already in it)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:216
+msgid "``state.`` is implicit in a ``new State`` block:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:236
+msgid "StateDelay"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:238
+msgid "``StateDelay`` allows you to create a state which waits for a fixed number of cycles before executing statements in ``whenCompleted {...}``. The preferred way to use it is:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:248
+msgid "It can also be written in one line:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:255
+msgid "StateFsm"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:257
+msgid "``StateFsm`` allows you to describe a state containing a nested state machine. When the nested state machine is done (exited), statements in ``whenCompleted { ... }`` are executed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:259
+msgid "There is an example of StateFsm definition :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:290
+msgid "In the example above, ``exit()`` makes the state machine jump to the boot state (a internal hidden state). This notifies ``StateFsm`` about the completion of the inner state machine."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:293
+msgid "StateParallelFsm"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:295
+msgid "``StateParallelFsm`` allows you to handle multiple nested state machines. When all nested state machine are done, statements in ``whenCompleted { ... }`` are executed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:297
+#: ../../SpinalHDL/Libraries/fsm.rst:322
+msgid "Example:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:308
+msgid "Notes about the entry state"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:310
+msgid "The way the entry state has been defined above makes it so that between the reset and the first clock sampling, the state machine is in a boot state. It is only after the first clock sampling that the defined entry state becomes active. This allows to properly enter the entry state (applying statements in ``onEntry``), and allows nested state machines."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:312
+msgid "While it is usefull, it is also possible to bypass that feature and directly having a state machine booting into a user state."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:314
+msgid "To do so, use `makeInstantEntry()` instead of defining a ``new State``. This function returns the boot state, active directly after reset."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:317
+msgid "The ``onEntry`` of that state will only be called when it transitions from another state to this state and not during boot."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/fsm.rst:320
+msgid "During simulation, the boot state is always named ``BOOT``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/index.pot b/source/locale/gettext/SpinalHDL/Libraries/index.pot
new file mode 100644
index 00000000000..e81561f594d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/index.pot
@@ -0,0 +1,61 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/index.rst:5
+msgid "Libraries"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:7
+msgid "The spinal.lib package goals are :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:9
+msgid "Provide things that are commonly used in hardware design (FIFO, clock crossing bridges, useful functions)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:10
+msgid "Provide simple peripherals (UART, JTAG, VGA, ..)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:11
+msgid "Provide some bus definition (Avalon, AMBA, ..)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:12
+msgid "Provide some methodology (Stream, Flow, Fragment)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:13
+msgid "Provide some example to get the spirit of spinal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:14
+msgid "Provide some tools and facilities (latency analyser, QSys converter, ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:16
+msgid "To use features introduced in followings chapter you need, in most of cases, to ``import spinal.lib._`` in your sources."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:0
+msgid "This package is currently under construction. Documented features could be considered as stable."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/index.rst:0
+msgid "Do not hesitate to use github for suggestions/bug/fixes/enhancements"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot
new file mode 100644
index 00000000000..57f6c13dabe
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot
@@ -0,0 +1,687 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:3
+msgid "RegIf"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:5
+msgid "Register Interface Builder"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:7
+msgid "Automatic address, fields allocation and conflict detection"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:8
+msgid "28 Register Access types (Covering the 25 types defined by the UVM standard)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:9
+#: ../../SpinalHDL/Libraries/regIf.rst:112
+msgid "Automatic documentation generation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:12
+msgid "Automatic allocation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:14
+msgid "Automatic address allocation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:39
+msgid "Automatic fileds allocation"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:54
+msgid "conflict detection"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:70
+msgid "28 Access Types"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:72
+msgid "Most of these come from UVM specification"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+msgid "AccessType"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+#: ../../SpinalHDL/Libraries/regIf.rst:436
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+msgid "From"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "RO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+msgid "w: no effect, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid "UVM"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "RW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+msgid "w: as-is, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+msgid "RC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+msgid "w: no effect, r: clears all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+msgid "RS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+msgid "w: no effect, r: sets all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+msgid "WRC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+msgid "w: as-is, r: clears all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+msgid "WRS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+msgid "w: as-is, r: sets all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+msgid "WC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+msgid "w: clears all bits, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+msgid "WS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+msgid "w: sets all bits, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+msgid "WSRC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+msgid "w: sets all bits, r: clears all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+msgid "WCRS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+msgid "w: clears all bits, r: sets all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "W1C"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+msgid "w: 1/0 clears/no effect on matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+msgid "W1S"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+msgid "w: 1/0 sets/no effect on matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+msgid "W1T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+msgid "w: 1/0 toggles/no effect on matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+msgid "W0C"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+msgid "w: 1/0 no effect on/clears matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+msgid "W0S"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+msgid "w: 1/0 no effect on/sets matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+msgid "W0T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+msgid "w: 1/0 no effect on/toggles matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+msgid "W1SRC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+msgid "w: 1/0 sets/no effect on matching bit, r: clears all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+msgid "W1CRS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+msgid "w: 1/0 clears/no effect on matching bit, r: sets all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+msgid "W0SRC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+msgid "w: 1/0 no effect on/sets matching bit, r: clears all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+msgid "W0CRS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+msgid "w: 1/0 no effect on/clears matching bit, r: sets all bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+msgid "WO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+msgid "w: as-is, r: error"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+msgid "WOC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+msgid "w: clears all bits, r: error"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+msgid "WOS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+msgid "w: sets all bits, r: error"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+msgid "W1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+msgid "w: first one after hard reset is as-is, other w have no effects, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid "WO1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid "w: first one after hard reset is as-is, other w have no effects, r: error"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+msgid "NA"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+msgid "w: reserved, r: reserved"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "New"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+msgid "W1P"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+msgid "w: 1/0 pulse/no effect on matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+msgid "W0P"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+msgid "w: 0/1 pulse/no effect on matching bit, r: no effect"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+msgid "HSRW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+msgid "w: Hardware Set, SoftWare RW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+msgid "RWHS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+msgid "w: SoftWare RW, Hardware Set"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+msgid "ROV"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+msgid "w: ReadOnly Value, used for hardware version"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "CSTM"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "w: user custom Type, used for document"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:114
+msgid "Document Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Document"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Status"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+msgid "HTML"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+msgid "``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid "Y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+msgid "CHeader"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+msgid "``busif.accept(CHeaderGenerator(\"header\", \"AP\"))``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+msgid "JSON"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+msgid "``busif.accept(JsonGenerator(\"regif\"))``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+msgid "RALF(UVM)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+msgid "``busif.accept(RalfGenerator(\"header\"))``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid "SystemRDL"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid "``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", Some(\"name\"), Some(\"desc\")))``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:124
+msgid "Latex(pdf)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:124
+#: ../../SpinalHDL/Libraries/regIf.rst:125
+msgid "N"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:125
+msgid "docx"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:128
+msgid "HTML auto-doc is now complete, Example source Code:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:133
+msgid "generated HTML document:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:139
+msgid "Special Access Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:141
+msgid "**CASE1:** ``RO`` usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:143
+msgid "``RO`` is different from other types. It does not create registers and requires an external signal to drive it, Attention, please don't forget to drive it."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:175
+msgid "**CASE2:** ``ROV`` usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:177
+msgid "ASIC design often requires some solidified version information. Unlike RO, it is not expected to generate wire signals"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:179
+msgid "old way:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:186
+msgid "new way:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:194
+msgid "**CASE3:** ``HSRW/RWHS`` hardware set type In some cases, such registers are not only configured by software, but also set by hardware signals"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:231
+msgid "**CASE4:** ``CSTM`` Although SpinalHDL includes 25 register types and 6 extension types, there are still various demands for private register types in practical application. Therefore, we reserve CSTM types for scalability. CSTM is only used to generate software interfaces, and does not generate actual circuits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:246
+msgid "**CASE5:** ``parasiteField``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:248
+msgid "This is used for software to share the same register on multiple address instead of generating multiple register entities"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:250
+msgid "example1: clock gate software enable"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:262
+msgid "example2: interrupt raw reg with foce interface for software"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:273
+msgid "Byte Mask"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:275
+msgid "withStrb"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:279
+msgid "Typical Example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:281
+msgid "Batch create REG-Address and fields register"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:321
+msgid "Interrupt Factory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:323
+msgid "Manual writing interruption"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:366
+msgid "this is a very tedious and repetitive work, a better way is to use the \"factory\" paradigm to auto-generate the documentation for each signal."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:368
+msgid "now the InterruptFactory can do that."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:370
+msgid "Easy Way create interruption:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:394
+msgid "IP level interrupt Factory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+msgid "Register"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "RAW"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "int raw register, set by int event, clear when bus write 1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+msgid "FORCE"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+msgid "int force register, for SW debug use"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "MASK"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "int mask register, 1: off; 0: open; defualt 1 int off"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "STATUS"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+msgid "int status, Read Only, ``status = raw && ! mask``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:408
+#: ../../SpinalHDL/Libraries/regIf.rst:426
+msgid "SpinalUsage:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:415
+msgid "SYS level interrupt merge"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "int status, RO, ``status = int_level && ! mask``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:433
+msgid "Spinal Factory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:436
+msgid "BusInterface method"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:438
+#: ../../SpinalHDL/Libraries/regIf.rst:440
+msgid "``InterruptFactory(regNamePre: String, triggers: Bool*)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:438
+msgid "create RAW/FORCE/MASK/STATUS for pulse event"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:439
+msgid "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:439
+msgid "create RAW/MASK/STATUS for pulse event"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:440
+msgid "create MASK/STATUS for level_int merge"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:441
+#: ../../SpinalHDL/Libraries/regIf.rst:443
+msgid "``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:441
+msgid "create RAW/FORCE/MASK/STATUS for pulse event at addrOffset"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:442
+msgid "``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:442
+msgid "create RAW/MASK/STATUS for pulse event at addrOffset"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:443
+msgid "create MASK/STATUS for level_int merge at addrOffset"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:447
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:479
+msgid "DefaultReadValue"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:481
+msgid "When the software reads a reserved address, the current policy is to return normally, readerror=0. In order to facilitate software debugging, the read back value can be configured, which is 0 by default"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:499
+msgid "Developers Area"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:501
+msgid "You can add your document Type by extending the `BusIfVistor` Trait"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:503
+msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:505
+msgid "BusIfVistor give access BusIf.RegInsts to do what you want"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/stream.pot b/source/locale/gettext/SpinalHDL/Libraries/stream.pot
new file mode 100644
index 00000000000..bbf3f88e797
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/stream.pot
@@ -0,0 +1,781 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/stream.rst:7
+msgid "Stream"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:10
+msgid "Specification"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:12
+msgid "The Stream interface is a simple handshake protocol to carry payload."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:13
+msgid "It could be used for example to push and pop elements into a FIFO, send requests to a UART controller, etc."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:19
+msgid "Signal"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:20
+#: ../../SpinalHDL/Libraries/stream.rst:217
+#: ../../SpinalHDL/Libraries/stream.rst:232
+#: ../../SpinalHDL/Libraries/stream.rst:273
+#: ../../SpinalHDL/Libraries/stream.rst:294
+#: ../../SpinalHDL/Libraries/stream.rst:335
+#: ../../SpinalHDL/Libraries/stream.rst:353
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:21
+msgid "Driver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:22
+#: ../../SpinalHDL/Libraries/stream.rst:96
+#: ../../SpinalHDL/Libraries/stream.rst:218
+#: ../../SpinalHDL/Libraries/stream.rst:233
+#: ../../SpinalHDL/Libraries/stream.rst:274
+#: ../../SpinalHDL/Libraries/stream.rst:295
+#: ../../SpinalHDL/Libraries/stream.rst:336
+#: ../../SpinalHDL/Libraries/stream.rst:354
+#: ../../SpinalHDL/Libraries/stream.rst:423
+#: ../../SpinalHDL/Libraries/stream.rst:438
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:23
+msgid "Don't care when"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:24
+msgid "valid"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:25
+#: ../../SpinalHDL/Libraries/stream.rst:30
+#: ../../SpinalHDL/Libraries/stream.rst:110
+#: ../../SpinalHDL/Libraries/stream.rst:114
+#: ../../SpinalHDL/Libraries/stream.rst:241
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:26
+#: ../../SpinalHDL/Libraries/stream.rst:36
+msgid "Master"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:27
+msgid "When high => payload present on the interface"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:29
+msgid "ready"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:31
+msgid "Slave"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:32
+msgid "When low => transaction are not consumed by the slave"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:33
+#: ../../SpinalHDL/Libraries/stream.rst:38
+msgid "valid is low"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:34
+msgid "payload"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:35
+#: ../../SpinalHDL/Libraries/stream.rst:220
+#: ../../SpinalHDL/Libraries/stream.rst:276
+#: ../../SpinalHDL/Libraries/stream.rst:338
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:37
+msgid "Content of the transaction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:49
+msgid "There is some examples of usage in SpinalHDL :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:70
+msgid "Each slave can or can't allow the payload to change when valid is high and ready is low. For examples:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:73
+msgid "An priority arbiter without lock logic can switch from one input to the other (which will change the payload)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:74
+msgid "An UART controller could directly use the write port to drive UART pins and only consume the transaction at the end of the transmission. Be careful with that."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:78
+msgid "Semantics"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:80
+msgid "When manually reading/driving the signals of a Stream keep in mind that:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:82
+msgid "After being asserted, ``valid`` may only be deasserted once the current payload was acknowleged. This means ``valid`` can only toggle to 0 the cycle after a the slave did a read by asserting ``ready``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:83
+msgid "In contrast to that ``ready`` may change at any time."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:84
+msgid "A transfer is only done on cycles where both ``valid`` and ``ready`` are asserted."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:85
+msgid "``valid`` of a Stream must not depend on ``ready`` in a combinatorial way and any path between the two must be registered."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:86
+msgid "It is recommended that ``valid`` does not depend on ``ready`` at all."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:89
+msgid "Functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:95
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:97
+#: ../../SpinalHDL/Libraries/stream.rst:453
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:98
+msgid "Latency"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:99
+msgid "Stream(type : Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+#: ../../SpinalHDL/Libraries/stream.rst:100
+msgid "Create a Stream of a given type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:101
+#: ../../SpinalHDL/Libraries/stream.rst:106
+#: ../../SpinalHDL/Libraries/stream.rst:118
+#: ../../SpinalHDL/Libraries/stream.rst:125
+#: ../../SpinalHDL/Libraries/stream.rst:131
+#: ../../SpinalHDL/Libraries/stream.rst:137
+#: ../../SpinalHDL/Libraries/stream.rst:163
+#: ../../SpinalHDL/Libraries/stream.rst:168
+#: ../../SpinalHDL/Libraries/stream.rst:235
+#: ../../SpinalHDL/Libraries/stream.rst:238
+#: ../../SpinalHDL/Libraries/stream.rst:297
+#: ../../SpinalHDL/Libraries/stream.rst:300
+#: ../../SpinalHDL/Libraries/stream.rst:356
+#: ../../SpinalHDL/Libraries/stream.rst:359
+#: ../../SpinalHDL/Libraries/stream.rst:455
+#: ../../SpinalHDL/Libraries/stream.rst:457
+msgid "Stream[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:103
+msgid "master/slave Stream(type : Data)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Initialized with corresponding in/out setup"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:108
+msgid "x.fire"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:109
+msgid "Return True when a transaction is consumed on the bus (valid && ready)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:112
+msgid "x.isStall"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:113
+msgid "Return True when a transaction is stall on the bus (valid && ! ready)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:116
+msgid "x.queue(size:Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:117
+msgid "Return a Stream connected to x through a FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:119
+msgid "2"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x.m2sPipe()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x.stage()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Return a Stream drived by x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "through a register stage that cut valid/payload paths"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Cost = (payload width + 1) flop flop"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:126
+#: ../../SpinalHDL/Libraries/stream.rst:138
+#: ../../SpinalHDL/Libraries/stream.rst:148
+#: ../../SpinalHDL/Libraries/stream.rst:159
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:127
+msgid "x.s2mPipe()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "ready paths is cut by a register stage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Cost = payload width * (mux2 + 1 flip flop)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:132
+#: ../../SpinalHDL/Libraries/stream.rst:143
+#: ../../SpinalHDL/Libraries/stream.rst:153
+#: ../../SpinalHDL/Libraries/stream.rst:164
+#: ../../SpinalHDL/Libraries/stream.rst:169
+msgid "0"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:133
+msgid "x.halfPipe()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "valid/ready/payload paths are cut by some register"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Cost = (payload width + 2) flip flop, bandwidth divided by two"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x << y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "y >> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:141
+msgid "Connect y to x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x <-< y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "y >-> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:146
+msgid "Connect y to x through a m2sPipe"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x </< y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "y >/> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:151
+msgid "Connect y to x through a s2mPipe"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "x <-/< y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "y >/-> x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Connect y to x through s2mPipe().m2sPipe()"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Which imply no combinatorial path between x and y"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:160
+msgid "x.haltWhen(cond : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Return a Stream connected to x"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Halted when cond is true"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:165
+msgid "x.throwWhen(cond : Bool)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "When cond is true, transaction are dropped"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:172
+msgid "The following code will create this logic :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:192
+msgid "Utils"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:194
+msgid "There is many utils that you can use in your design in conjunction with the Stream bus, this chapter will document them."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:197
+msgid "StreamFifo"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:199
+msgid "On each stream you can call the .queue(size) to get a buffered stream. But you can also instantiate the FIFO component itself :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:216
+#: ../../SpinalHDL/Libraries/stream.rst:272
+#: ../../SpinalHDL/Libraries/stream.rst:334
+msgid "parameter name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:219
+#: ../../SpinalHDL/Libraries/stream.rst:275
+#: ../../SpinalHDL/Libraries/stream.rst:337
+msgid "dataType"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:221
+#: ../../SpinalHDL/Libraries/stream.rst:277
+#: ../../SpinalHDL/Libraries/stream.rst:339
+msgid "Payload data type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:222
+#: ../../SpinalHDL/Libraries/stream.rst:278
+msgid "depth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:223
+#: ../../SpinalHDL/Libraries/stream.rst:279
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:224
+#: ../../SpinalHDL/Libraries/stream.rst:280
+msgid "Size of the memory used to store elements"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:231
+#: ../../SpinalHDL/Libraries/stream.rst:293
+#: ../../SpinalHDL/Libraries/stream.rst:352
+msgid "io name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:234
+#: ../../SpinalHDL/Libraries/stream.rst:296
+msgid "push"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:236
+#: ../../SpinalHDL/Libraries/stream.rst:298
+#: ../../SpinalHDL/Libraries/stream.rst:357
+msgid "Used to push elements"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:237
+#: ../../SpinalHDL/Libraries/stream.rst:299
+msgid "pop"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:239
+#: ../../SpinalHDL/Libraries/stream.rst:301
+#: ../../SpinalHDL/Libraries/stream.rst:360
+msgid "Used to pop elements"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:240
+msgid "flush"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:242
+msgid "Used to remove all elements inside the FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:243
+msgid "occupancy"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:244
+#: ../../SpinalHDL/Libraries/stream.rst:303
+#: ../../SpinalHDL/Libraries/stream.rst:306
+msgid "UInt of log2Up(depth + 1) bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:245
+msgid "Indicate the internal memory occupancy"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:249
+msgid "StreamFifoCC"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:251
+msgid "You can instantiate the dual clock domain version of the fifo the following way :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:281
+msgid "pushClock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:282
+#: ../../SpinalHDL/Libraries/stream.rst:285
+#: ../../SpinalHDL/Libraries/stream.rst:341
+#: ../../SpinalHDL/Libraries/stream.rst:344
+msgid "ClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:283
+#: ../../SpinalHDL/Libraries/stream.rst:342
+msgid "Clock domain used by the push side"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:284
+msgid "popClock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:286
+#: ../../SpinalHDL/Libraries/stream.rst:345
+msgid "Clock domain used by the pop side"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:302
+msgid "pushOccupancy"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:304
+msgid "Indicate the internal memory occupancy (from the push side perspective)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:305
+msgid "popOccupancy"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:307
+msgid "Indicate the internal memory occupancy  (from the pop side perspective)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:311
+msgid "StreamCCByToggle"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:313
+msgid "Component that connects Streams across clock domains based on toggling signals."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:314
+msgid "This way of implementing a cross clock domain bridge is characterized by a small area usage but also a low bandwidth."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:340
+msgid "inputClock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:343
+msgid "outputClock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:355
+msgid "input"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:358
+msgid "output"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:363
+msgid "Alternatively you can also use a this shorter syntax which directly return you the cross clocked stream:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:377
+msgid "StreamWidthAdapter"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:379
+msgid "This component adapts the width of the input stream to the output stream. When the width of the ``outStream`` payload is greater than the ``inStream``, by combining the payloads of several input transactions into one; conversely, if the payload width of the ``outStream`` is less than the ``inStream``, one input transaction will be split into several output transactions."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:382
+msgid "In the best case, the width of the payload of the ``inStream`` should be an integer multiple of the ``outStream`` as shown below."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:390
+msgid "As in the example above, the two ``inStream`` transactions will be merged into one ``outStream`` transaction, and the payload of the first input transaction will be placed on the lower bits of the output payload by default."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:392
+msgid "If the expected order of input transaction payload placement is different from the default setting, here is an example."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:400
+msgid "There is also a traditional parameter called ``endianness``, which has the same effect as ``ORDER``. The value of ``endianness`` is the same as ``LOWER_FIRST`` of ``order`` when it is ``LITTLE``, and the same as ``HIGHER_FIRST`` when it is ``BIG``. The ``padding`` parameter is an optional boolean value to determine whether the adapter accepts non-integer multiples of the input and output payload width."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:406
+msgid "StreamArbiter"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:408
+msgid "When you have multiple Streams and you want to arbitrate them to drive a single one, you can use the StreamArbiterFactory."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:422
+msgid "Arbitration functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:424
+msgid "lowerFirst"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:425
+msgid "Lower port have priority over higher port"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:426
+msgid "roundRobin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:427
+msgid "Fair round robin arbitration"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:428
+msgid "sequentialOrder"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Could be used to retrieve transaction in a sequancial order"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "First transaction should come from port zero, then from port one, ..."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:437
+msgid "Lock functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:439
+msgid "noLock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:440
+msgid "The port selection could change every cycle, even if the transaction on the selected port is not consumed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:441
+msgid "transactionLock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:442
+msgid "The port selection is locked until the transaction on the selected port is consumed."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:443
+msgid "fragmentLock"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "Could be used to arbitrate Stream[Flow[T]]."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:0
+msgid "In this mode, the port selection is locked until the selected port finish is burst (last=True)."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:452
+msgid "Generation functions"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:454
+msgid "on(inputs : Seq[Stream[T]])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:456
+msgid "onArgs(inputs : Stream[T]*)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:460
+msgid "StreamJoin"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:462
+msgid "This utility takes multiple input streams and waits until all of them fire `valid` before letting all of them through by providing `ready`."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:471
+msgid "StreamFork"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:473
+msgid "A StreamFork will clone each incoming data to all its output streams. If synchronous is true, all output streams will always fire together, which means that the stream will halt until all output streams are ready. If synchronous is false, output streams may be ready one at a time, at the cost of an additional flip flop (1 bit per output). The input stream will block until all output streams have processed each item regardlessly."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:485
+msgid "or"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:493
+msgid "StreamMux"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:495
+msgid "A mux implementation for ``Stream``. It takes a ``select`` signal and streams in ``inputs``, and returns a ``Stream`` which is connected to one of the input streams specified by ``select``. ``StreamArbiter`` is a facility works similar to this but is more powerful."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:507
+msgid "The ``UInt`` type of ``select`` signal could not be changed while output stream is stalled, or it might break the transaction on the fly. Use ``Stream`` typed ``select`` can generate a stream interface which only fire and change the routing when it is safe."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:512
+msgid "StreamDemux"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:514
+msgid "A demux implementation for ``Stream``. It takes a ``input``, a ``select`` and a ``portCount`` and returns a ``Vec(Stream)`` where the output stream specified by ``select`` is connected to ``input``, the other output streams are inactive. For safe transaction, refer the notes above."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:525
+msgid "StreamDispatcherSequencial"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:527
+msgid "This util take its input stream and routes it to ``outputCount`` stream in a sequential order."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:538
+msgid "StreamTransactionExtender"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:540
+msgid "This utility will take one input transfer and generate several output transfers, it provides the facility to repeat the payload value ``count+1`` times into output transfers. The ``count`` is captured and registered each time inputStream fires for an individual payload."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:555
+msgid "This ``extender`` provides several status signals, such as ``working``, ``last``, ``done`` where ``working`` means there is one input transfer accepted and in-progress, ``last`` indicates the last output transfer is prepared and waiting to complete, ``done`` become valid represents the last output transfer is fireing and making the current input transaction process complete and ready to start another transaction."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:572
+msgid "If only count for output stream is required then use ``StreamTransactionCounter`` instead."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:575
+msgid "Simulation support"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:577
+msgid "For simulation master and slave implementations are available:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:583
+msgid "Class"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:584
+msgid "Usage"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:585
+msgid "StreamMonitor"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:586
+msgid "Used for both master and slave sides, calls function with payload if Stream fires."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:587
+msgid "StreamDriver"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:588
+msgid "Testbench master side, drives values by calling function to apply value (if available). Function must return if value was available. Supports random delays."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:589
+msgid "StreamReadyRandmizer"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:590
+msgid "Randomizes ``ready`` for reception of data, testbench is the slave side."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:591
+msgid "ScoreboardInOrder"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/stream.rst:592
+msgid "Often used to compare reference/dut data"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/utils.pot b/source/locale/gettext/SpinalHDL/Libraries/utils.pot
new file mode 100644
index 00000000000..94a456916cc
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/utils.pot
@@ -0,0 +1,468 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/utils.rst:5
+msgid "Utils"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:7
+msgid "Some utils are also present in :ref:`spinal.core <utils>`"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:10
+msgid "State less utilities"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:16
+#: ../../SpinalHDL/Libraries/utils.rst:83
+#: ../../SpinalHDL/Libraries/utils.rst:216
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:17
+#: ../../SpinalHDL/Libraries/utils.rst:84
+#: ../../SpinalHDL/Libraries/utils.rst:217
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:18
+#: ../../SpinalHDL/Libraries/utils.rst:85
+#: ../../SpinalHDL/Libraries/utils.rst:189
+#: ../../SpinalHDL/Libraries/utils.rst:218
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:19
+msgid "toGray(x : UInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:20
+#: ../../SpinalHDL/Libraries/utils.rst:44
+#: ../../SpinalHDL/Libraries/utils.rst:47
+#: ../../SpinalHDL/Libraries/utils.rst:53
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:21
+msgid "Return the gray value converted from ``x`` (UInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:22
+msgid "fromGray(x : Bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:23
+#: ../../SpinalHDL/Libraries/utils.rst:30
+#: ../../SpinalHDL/Libraries/utils.rst:34
+msgid "UInt"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:24
+msgid "Return the UInt value converted value from ``x`` (gray)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:25
+msgid "Reverse(x : T)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:26
+#: ../../SpinalHDL/Libraries/utils.rst:41
+#: ../../SpinalHDL/Libraries/utils.rst:61
+#: ../../SpinalHDL/Libraries/utils.rst:67
+#: ../../SpinalHDL/Libraries/utils.rst:72
+#: ../../SpinalHDL/Libraries/utils.rst:87
+#: ../../SpinalHDL/Libraries/utils.rst:95
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:27
+msgid "Flip all bits (lsb + n -> msb - n)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "OHToUInt(x : Seq[Bool])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "OHToUInt(x : BitVector)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:31
+msgid "Return the index of the single bit set (one hot) in ``x``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "CountOne(x : Seq[Bool])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "CountOne(x : BitVector)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:35
+msgid "Return the number of bit set in ``x``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "MajorityVote(x : Seq[Bool])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "MajorityVote(x : BitVector)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:38
+#: ../../SpinalHDL/Libraries/utils.rst:191
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:39
+msgid "Return True if the number of bit set is > x.size / 2"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:40
+msgid "EndiannessSwap(that: T[, base:BitCount])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:42
+msgid "Big-Endian <-> Little-Endian"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:43
+msgid "OHMasking.first(x : Bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:45
+msgid "Apply a mask on x to only keep the first bit set"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:46
+msgid "OHMasking.last(x : Bits)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:48
+msgid "Apply a mask on x to only keep the last bit set"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "OHMasking.roundRobin("
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "requests : Bits,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "ohPriority : Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid ")"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "Apply a mask on x to only keep the bit set from ``requests``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "it start looking in ``requests`` from the ``ohPriority`` position."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "For example if ``requests`` is \"1001\" and ``ohPriority`` is \"0010\", the ``roundRobin`` function will start looking in `requests` from its second bit and will return \"1000\"."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "MuxOH ("
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "oneHot : IndexedSeq[Bool],"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "inputs : Iterable[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:62
+msgid "Returns the muxed ``T`` from the ``inputs`` based on the ``oneHot`` vector."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "PriorityMux ("
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "sel: Seq[Bool],"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "in:  Seq[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:68
+#: ../../SpinalHDL/Libraries/utils.rst:73
+msgid "Return the first ``in`` element whose ``sel`` is ``True``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "in:  Seq[(Bool, T)]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:77
+msgid "State full utilities"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:86
+msgid "Delay(that: T, cycleCount: Int)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:88
+msgid "Return ``that`` delayed by ``cycleCount`` cycles"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:89
+msgid "History(that: T, length: Int[,when : Bool])"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:90
+msgid "List[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "Return a Vec of ``length`` elements"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "The first element is ``that``\\ , the last one is ``that`` delayed by ``length``\\ -1\\"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "The internal shift register sample when ``when`` is asserted"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:94
+msgid "BufferCC(input : T)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:96
+msgid "Return the input signal synchronized with the current clock domain by using 2 flip flop"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:100
+msgid "Counter"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:102
+msgid "The Counter tool can be used to easily instantiate a hardware counter."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:108
+msgid "Instantiation syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:109
+#: ../../SpinalHDL/Libraries/utils.rst:152
+msgid "Notes"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:110
+msgid "``Counter(start: BigInt, end: BigInt[, inc : Bool])``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:112
+msgid "``Counter(range : Range[, inc : Bool])``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:113
+msgid "Compatible with the  ``x to y`` ``x until y`` syntaxes"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:114
+msgid "``Counter(stateCount: BigInt[, inc : Bool])``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:115
+msgid "Starts at zero and ends at ``stateCount - 1``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:116
+msgid "``Counter(bitCount: BitCount[, inc : Bool])``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:117
+msgid "Starts at zero and ends at ``(1 << bitCount) - 1``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:119
+msgid "A counter can be controlled by methods, and wires can be read:"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:135
+msgid "When a ``Counter`` overflows (reached end value), it restarts the next cycle to its start value."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:138
+msgid "Currently, only up counter are supported."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:140
+msgid "``CounterFreeRun`` builds an always running counter: ``CounterFreeRun(stateCount: BigInt)``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:143
+msgid "Timeout"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:145
+msgid "The Timeout tool can be used to easily instantiate an hardware timeout."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:151
+msgid "Instanciation syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:153
+msgid "Timeout(cycles : BigInt)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:154
+msgid "Tick after ``cycles`` clocks"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:155
+msgid "Timeout(time : TimeNumber)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:156
+msgid "Tick after a ``time`` duration"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:157
+msgid "Timeout(frequency : HertzNumber)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:158
+msgid "Tick at an ``frequency`` rate"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:161
+msgid "There is an example of different syntaxes which could be used with the Counter tool"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:171
+msgid "If you instantiate an ``Timeout`` with an time or frequency setup, the implicit ``ClockDomain`` should have an frequency setting."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:174
+msgid "ResetCtrl"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:176
+msgid "The ResetCtrl provide some utilities to manage resets."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:179
+msgid "asyncAssertSyncDeassert"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:181
+msgid "You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the filtered value."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:187
+msgid "Argument name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:188
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:190
+msgid "input"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:192
+msgid "Signal that should be filtered"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:193
+msgid "clockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:194
+msgid "ClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:195
+msgid "ClockDomain which will use the filtered value"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:196
+msgid "inputPolarity"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:197
+#: ../../SpinalHDL/Libraries/utils.rst:200
+msgid "Polarity"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:198
+msgid "HIGH/LOW (default=HIGH)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:199
+msgid "outputPolarity"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:201
+msgid "HIGH/LOW (default=clockDomain.config.resetActiveLevel)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:202
+msgid "bufferDepth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:203
+#: ../../SpinalHDL/Libraries/utils.rst:220
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:204
+msgid "Number of register stages used to avoid metastability (default=2)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:207
+msgid "There is also an ``ResetCtrl.asyncAssertSyncDeassertDrive`` version of tool which directly assign the ``clockDomain`` reset with the filtered value."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:210
+msgid "Special utilities"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:219
+msgid "LatencyAnalysis(paths : Node*)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "Return the shortest path, in terms of cycles, that travel through all nodes,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/utils.rst:0
+msgid "from the first one to the last one"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Libraries/vexriscv.pot b/source/locale/gettext/SpinalHDL/Libraries/vexriscv.pot
new file mode 100644
index 00000000000..2a4564c60a7
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Libraries/vexriscv.pot
@@ -0,0 +1,77 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:3
+msgid "VexRiscv (RV32IM CPU)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:5
+msgid "VexRiscv is an fpga friendly RISC-V ISA CPU implementation with following features :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:8
+msgid "RV32IM instruction set"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:9
+msgid "Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:10
+msgid "1.44 DMIPS/Mhz when all features are enabled"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:11
+msgid "Optimized for FPGA"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:12
+msgid "Optional MUL/DIV extension"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:13
+msgid "Optional instruction and data caches"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:14
+msgid "Optional MMU"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:15
+msgid "Optional debug extension allowing eclipse debugging via an GDB >> openOCD >> JTAG connection"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:16
+msgid "Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:17
+msgid "Two implementation of shift instructions, Single cycle / shiftNumber cycles"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:18
+msgid "Each stage could have bypass or interlock hazard logic"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:19
+msgid "FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/vexriscv.rst:21
+msgid "Much more information there : `https://github.com/SpinalHDL/VexRiscv <https://github.com/SpinalHDL/VexRiscv>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/analog_inout.pot b/source/locale/gettext/SpinalHDL/Other language features/analog_inout.pot
new file mode 100644
index 00000000000..e072110015e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/analog_inout.pot	
@@ -0,0 +1,99 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:5
+msgid "Analog and inout"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:8
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:10
+msgid "You can define native tristate signals by using the ``Analog``/``inout`` features. These features were added for the following reasons:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:13
+msgid "Being able to add native tristate signals to the toplevel (it avoids having to manually wrap them with some hand-written VHDL/Verilog)."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:14
+msgid "Allowing the definition of blackboxes which contain ``inout`` pins."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:15
+msgid "Being able to connect a blackbox's ``inout`` pin through the hierarchy to a toplevel ``inout`` pin."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:17
+msgid "As those features were only added for convenience, please do not try other fancy stuff with tristate logic just yet."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:19
+msgid "If you want to model a component like a memory-mapped GPIO peripheral, please use the :ref:`TriState/TriStateArray <section-tristate>` bundles from the Spinal standard library, which abstract over the true nature of tristate drivers."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:22
+msgid "Analog"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:24
+msgid "``Analog`` is the keyword which allows a signal to be defined as something analog, which in the digital world could mean ``0``, ``1``, or ``Z`` (the disconnected, high-impedance state)."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:26
+#: ../../SpinalHDL/Other language features/analog_inout.rst:43
+#: ../../SpinalHDL/Other language features/analog_inout.rst:66
+msgid "For instance:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:39
+msgid "inout"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:41
+msgid "``inout`` is the keyword which allows you to set an ``Analog`` signal as a bidirectional (both \"in\" and \"out\") signal."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:61
+msgid "InOutWrapper"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:63
+msgid "``InOutWrapper`` is a tool which allows you to transform all ``master`` ``TriState``/``TriStateArray``/``ReadableOpenDrain`` bundles of a component into native ``inout(Analog(...))`` signals. It allows you to keep your hardware description free of any ``Analog``/``inout`` things, and then transform the toplevel to make it synthesis ready."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:80
+msgid "Will generate:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:100
+msgid "Instead of:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:123
+msgid "Manually driving Analog bundles"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:125
+msgid "If an ``Analog`` bundle is not driven, it will default to being high-Z. Therefore to manually implement a tristate driver (in case the ``InOutWrapper`` type can't be used for some reason) you have to conditionally drive the signal."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/analog_inout.rst:128
+msgid "To manually connect a ``TriState`` signal to an ``Analog`` bundle:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/assertion.pot b/source/locale/gettext/SpinalHDL/Other language features/assertion.pot
new file mode 100644
index 00000000000..aea4e897df8
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/assertion.pot	
@@ -0,0 +1,77 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/assertion.rst:3
+msgid "Assertions"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:5
+msgid "In addition to Scala run-time assertions, you can add hardware assertions using the following syntax:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:7
+msgid "``assert(assertion : Bool, message : String = null, severity: AssertNodeSeverity = Error)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:9
+msgid "Severity levels are:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:15
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:16
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:17
+msgid "NOTE"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:18
+msgid "Used to report an informative message"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:19
+msgid "WARNING"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:20
+msgid "Used to report an unusual case"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:21
+msgid "ERROR"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:22
+msgid "Used to report an situation that should not happen"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:23
+msgid "FAILURE"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:24
+msgid "Used to report a fatal situation and close the simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/assertion.rst:27
+msgid "One practical example could be to check that the ``valid`` signal of a handshake protocol never drops when ``ready`` is low:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/index.pot b/source/locale/gettext/SpinalHDL/Other language features/index.pot
new file mode 100644
index 00000000000..b3b94e66459
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/index.pot	
@@ -0,0 +1,65 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/index.rst:3
+msgid "Other language features"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:5
+msgid "The core of the language defines the syntax for many features:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:7
+msgid "Types / Literals"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:8
+msgid "Register / Clock domains"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:9
+msgid "Component / Area"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:10
+msgid "RAM / ROM"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:11
+msgid "When / Switch / Mux"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:12
+msgid "BlackBox (to integrate VHDL or Verilog IPs inside Spinal)"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:13
+msgid "SpinalHDL to VHDL converter"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:15
+msgid "Then, by using these features, you can define digital hardware, and also build powerful libraries and abstractions. It's one of the major advantages of SpinalHDL over other commonly used HDLs, because you can extend the language without having knowledge about the compiler."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:18
+msgid "One good example of this is the :ref:`SpinalHDL lib <lib_introduction>` which adds many utilities, tools, buses, and methodologies."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/index.rst:20
+msgid "To use features introduced in the following chapter you need to ``import spinal.core._`` in your sources."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/report.pot b/source/locale/gettext/SpinalHDL/Other language features/report.pot
new file mode 100644
index 00000000000..96e96760a11
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/report.pot	
@@ -0,0 +1,41 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/report.rst:3
+msgid "Report"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/report.rst:5
+msgid "You can add debugging in RTL for simulation, using the following syntax:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/report.rst:21
+msgid "It will generate the following Verilog code for example:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/report.rst:27
+msgid "Since SpinalHDL 1.4.4, the following syntax is also supported:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/report.rst:33
+msgid "You can display the current simulation time using the REPORT_TIME object"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/report.rst:39
+msgid "will result in:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot b/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot
new file mode 100644
index 00000000000..91c531a03d7
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot	
@@ -0,0 +1,41 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:4
+msgid "ScopeProperty"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:6
+msgid "A scope property is a thing which can store values locally to the current thread. Its API can be used to set/get that value, but also to apply modification to the value for a portion of the execution in a stack manner."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:8
+msgid "In other words it is a alternative to global variable, scala implicit, ThreadLocal."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:10
+msgid "To compare with global variable, It allow to run multiple thread running the same code indepedently"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:11
+msgid "To compare with scala implicit, it is less intrusive in the code base"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/scope_property.rst:12
+msgid "To compare with ThreadLocal, it has some API to collect all ScopeProperty and restore them in the same state later on"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/stub.pot b/source/locale/gettext/SpinalHDL/Other language features/stub.pot
new file mode 100644
index 00000000000..f2283b9be49
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/stub.pot	
@@ -0,0 +1,53 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/stub.rst:3
+msgid "Stub"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:5
+msgid "You can empty an Component Hierarchy as stub:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:20
+msgid "It will generate the following Verilog code for example:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:43
+msgid "You can also empty the top Component"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:49
+msgid "What does `stub` do ?"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:51
+msgid "first walk all the components and find out clock, then keep clock"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:52
+msgid "then remove all children component"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:53
+msgid "then remove all assignment and logic we dont want"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/stub.rst:54
+msgid "tile 0 to output port"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/utils.pot b/source/locale/gettext/SpinalHDL/Other language features/utils.pot
new file mode 100644
index 00000000000..b35ce50e2bc
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/utils.pot	
@@ -0,0 +1,319 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/utils.rst:4
+msgid "Utils"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:7
+msgid "General"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:9
+msgid "Many tools and utilities are present in :ref:`spinal.lib <lib_introduction>` but some are already present in the SpinalHDL Core."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:15
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:16
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:17
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:18
+msgid "``widthOf(x : BitVector)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:19
+#: ../../SpinalHDL/Other language features/utils.rst:22
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:20
+msgid "Return the width of a Bits/UInt/SInt signal"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:21
+msgid "``log2Up(x : BigInt)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:23
+msgid "Return the number of bits needed to represent ``x`` states"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:24
+msgid "``isPow2(x : BigInt)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:25
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:26
+msgid "Return true if ``x`` is a power of two"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:27
+msgid "``roundUp(that : BigInt, by : BigInt)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:28
+msgid "BigInt"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:29
+msgid "Return the first ``by`` multiply from ``that`` (included)"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:30
+msgid "``Cat(x: Data*)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:31
+#: ../../SpinalHDL/Other language features/utils.rst:34
+msgid "Bits"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:32
+msgid "Concatenate all arguments, from MSB to LSB, see `Cat`_"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:33
+msgid "``Cat(x: Iterable[Data])``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:35
+msgid "Conactenate arguments, from LSB to MSB, see `Cat`_"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:40
+msgid "Cat"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:42
+msgid "As listed above, there are two version of ``Cat``. Both versions concatenate the signals they contain, with a subtle difference:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:44
+msgid "``Cat(x: Data*)`` takes an arbitrary number of hardware signals as parameters. It mimics other HDLs and the leftmost parameter becomes the MSB of the resulting ``Bits``, the rightmost the LSB side. Said differently: the input is concatenated in the order as written."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:47
+msgid "``Cat(x: Iterable[Data])`` which takes a single Scala iterable collection (Seq / Set / List / ...) containing hardware signals. This version places the first element of the list into the LSB, and the last into the MSB."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:50
+msgid "This seeming difference comes mostly from the convention that ``Bits`` are written from the hightest index to the lowest index, while Lists are written down starting from index 0 to the highest index. ``Cat`` places index 0 of both conventions at the LSB."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:65
+msgid "Cloning hardware datatypes"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:67
+msgid "You can clone a given hardware data type by using the ``cloneOf(x)`` function. It will return a new instance of the same Scala type and parameters."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:70
+msgid "For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:84
+msgid "You can get more information about how hardware data types are managed on the :ref:`Hardware types page <hardware_type>`."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:87
+msgid "If you use the ``cloneOf`` function on a ``Bundle``, this ``Bundle`` should be a ``case class`` or should override the clone function internally."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:105
+msgid "Passing a datatype as construction parameter"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:107
+msgid "Many pieces of reusable hardware need to be parameterized by some data type. For example if you want to define a FIFO or a shift register, you need a parameter to specify which kind of payload you want for the component."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:110
+msgid "There are two similar ways to do this."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:113
+msgid "The old way"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:115
+msgid "A good example of the old way to do this is in this definition of a ``ShiftRegister`` component:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:127
+msgid "And here is how you can instantiate the component:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:133
+msgid "As you can see, the raw hardware type is directly passed as a construction parameter. Then each time you want to create an new instance of that kind of hardware data type, you need to use the ``cloneOf(...)`` function. Doing things this way is not super safe as it's easy to forget to use ``cloneOf``."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:138
+msgid "The safe way"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:140
+msgid "An example of the safe way to pass a data type parameter is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:152
+msgid "And here is how you instantiate the component (exactly the same as before):"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:158
+msgid "Notice how the example above uses a ``HardType`` wrapper around the raw data type ``T``, which is a \"blueprint\" definition of a hardware data type. This way of doing things is easier to use than the \"old way\", because to create a new instance of the hardware data type you only need to call the ``apply`` function of that ``HardType`` (or in other words, just add parentheses after the parameter)."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:161
+msgid "Additionally, this mechanism is completely transparent from the point of view of the user, as a hardware data type can be implicitly converted into a ``HardType``."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:164
+msgid "Frequency and time"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:166
+msgid "SpinalHDL has a dedicated syntax to define frequency and time values:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:177
+msgid "For time definitions you can use following postfixes to get a ``TimeNumber``:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:178
+msgid "``fs``, ``ps``, ``ns``, ``us``, ``ms``, ``sec``, ``mn``, ``hr``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:180
+msgid "For time definitions you can use following postfixes to get a ``HertzNumber``:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:181
+msgid "``Hz``, ``KHz``, ``MHz``, ``GHz``, ``THz``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:183
+msgid "``TimeNumber`` and ``HertzNumber`` are based on the ``PhysicalNumber`` class which use  scala ``BigDecimal`` to store numbers."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:186
+msgid "Binary prefix"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:188
+msgid "SpinalHDL allows the definition of integer numbers using binary prefix notation according to IEC."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:195
+msgid "The following binary prefix notations are available:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:201
+msgid "Binary Prefix"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:202
+msgid "Value"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:203
+msgid "Byte, Bytes"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:204
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:205
+msgid "KiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:206
+msgid "1024 == 1 << 10"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:207
+msgid "MiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:208
+msgid "1024\\ :sup:`2` == 1 << 20"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:209
+msgid "GiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:210
+msgid "1024\\ :sup:`3` == 1 << 30"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:211
+msgid "TiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:212
+msgid "1024\\ :sup:`4` == 1 << 40"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:213
+msgid "PiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:214
+msgid "1024\\ :sup:`5` == 1 << 50"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:215
+msgid "EiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:216
+msgid "1024\\ :sup:`6` == 1 << 60"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:217
+msgid "ZiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:218
+msgid "1024\\ :sup:`7` == 1 << 70"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:219
+msgid "YiB"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:220
+msgid "1024\\ :sup:`8` == 1 << 80"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/utils.rst:223
+msgid "Of course, BigInt can also be printed as a string in bytes unit. ``BigInt(1024).byteUnit``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Other language features/vhdl_generation.pot b/source/locale/gettext/SpinalHDL/Other language features/vhdl_generation.pot
new file mode 100644
index 00000000000..8096479ee88
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Other language features/vhdl_generation.pot	
@@ -0,0 +1,296 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:5
+msgid "VHDL and Verilog generation"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:8
+msgid "Generate VHDL and Verilog from a SpinalHDL Component"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:10
+msgid "To generate the VHDL from a SpinalHDL component you just need to call ``SpinalVhdl(new YourComponent)`` in a Scala ``main``."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:12
+msgid "Generating Verilog is exactly the same, but with ``SpinalVerilog`` in place of ``SpinalVHDL``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:40
+msgid "``SpinalVhdl`` and ``SpinalVerilog`` may need to create multiple instances of your component class, therefore the first argument is not a ``Component`` reference, but a function that returns a new component."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:43
+msgid "The ``SpinalVerilog`` implementation began the 5th of June, 2016. This backend successfully passes the same regression tests as the VHDL one (RISCV CPU, Multicore and pipelined mandelbrot, UART RX/TX, Single clock fifo, Dual clock fifo, Gray counter, ...)."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:46
+msgid "If you have any issues with this new backend, please make a `Github issue <https://github.com/SpinalHDL/SpinalHDL/issues>`_ describing the problem."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:49
+msgid "Parametrization from Scala"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:55
+msgid "Argument name"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:56
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:57
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:58
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:294
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:59
+msgid "``mode``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:60
+msgid "SpinalMode"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:61
+msgid "null"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "Set the SpinalHDL hdl generation mode."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "Can be set to ``VHDL`` or ``Verilog``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:64
+msgid "``defaultConfigForClockDomains``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:65
+msgid "ClockDomainConfig"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "RisingEdgeClock"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "AsynchronousReset"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "ResetActiveHigh"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:0
+msgid "ClockEnableActiveHigh"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:70
+msgid "Set the clock configuration that will be used as the default value for all new ``ClockDomain``."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:71
+msgid "``onlyStdLogicVectorAtTopLevelIo``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:72
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:73
+msgid "false"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:74
+msgid "Change all unsigned/signed toplevel io into std_logic_vector."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:75
+msgid "``defaultClockDomainFrequency``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:76
+msgid "IClockDomainFrequency"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:77
+msgid "UnknownFrequency"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:78
+msgid "Default clock frequency."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:79
+msgid "``targetDirectory``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:80
+msgid "String"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:81
+msgid "Current directory"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:82
+msgid "Directory where files are generated."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:85
+msgid "And this is the syntax to specify them:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:98
+msgid "Parametrization from shell"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:100
+msgid "You can also specify generation parameters by using command line arguments."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:108
+msgid "The syntax for command line arguments is:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:124
+msgid "Generated VHDL and Verilog"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:126
+msgid "How a SpinalHDL RTL description is translated into VHDL and Verilog is important:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:128
+msgid "Names in Scala are preserved in VHDL and Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:129
+msgid "``Component`` hierarchy in Scala is preserved in VHDL and Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:130
+msgid "``when`` statements in Scala are emitted as if statements in VHDL and Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:131
+msgid "``switch`` statements in Scala are emitted as case statements in VHDL and Verilog in all standard cases."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:134
+msgid "Organization"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:136
+msgid "When you use the VHDL generator, all modules are generated into a single file which contain three sections:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:138
+msgid "A package that contains the definition of all Enums"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:139
+msgid "A package that contains functions used by the architectural elements"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:140
+msgid "All components needed by your design"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:142
+msgid "When you use the Verilog generation, all modules are generated into a single file which contains two sections:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:144
+msgid "All enumeration definitions used"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:145
+msgid "All modules needed by your design"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:148
+msgid "Combinational logic"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:150
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:213
+msgid "Scala:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:178
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:238
+msgid "VHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:211
+msgid "Sequential logic"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:283
+msgid "VHDL and Verilog attributes"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:285
+msgid "In some situations, it is useful to give attributes for some signals in a design to modify how they are synthesized."
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:287
+msgid "To do that, you can call the following functions on any signals or memories in the design:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:293
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:295
+msgid "``addAttribute(name)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:296
+msgid "Add a boolean attribute with the given ``name`` set to true"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:297
+msgid "``addAttribute(name, value)``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:298
+msgid "Add a string attribute with the given ``name`` set to ``value``"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:301
+msgid "Example:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:308
+msgid "Produced declaration in VHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Other language features/vhdl_generation.rst:316
+msgid "Produced declaration in Verilog:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Semantic/assignments.pot b/source/locale/gettext/SpinalHDL/Semantic/assignments.pot
new file mode 100644
index 00000000000..47f94f092b9
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Semantic/assignments.pot
@@ -0,0 +1,154 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:2
+msgid "Assignments"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:4
+msgid "There are multiple assignment operators:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:10
+msgid "Symbol"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:11
+#: ../../SpinalHDL/Semantic/assignments.rst:82
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:12
+msgid "``:=``"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:13
+msgid "Standard assignment, equivalent to ``<=`` in VHDL/Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:14
+msgid "``\\=``"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:15
+msgid "Equivalent to ``:=`` in VHDL and ``=`` in Verilog. The value is updated instantly in-place. Only works with combinational signals, does not work with registers."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:16
+msgid "``<>``"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:17
+msgid "Automatic connection between 2 signals or two bundles of the same type. Direction is inferred by using signal direction (in/out). (Similar behavior to ``:=``\\ )"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:19
+msgid "When muxing (for instance using ``when``, see :doc:`when_switch`.), the last valid standard assignment ``:=`` wins. Else, assigning twice to the same assignee from the same scope results in an assignment overlap.  SpinalHDL will assume this is a unintentional design error by default and halt elaboration with error. For special use-cases assignment overlap can be programatically permitted on a case by case basis. (see :doc:`../Design errors/assignment_overlap`)."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:45
+msgid "It also supports Bundle assignment (convert all bit signals into a single bit-bus of suitable width of type Bits, to then use that wider form in an assignment expression).  Bundle multiple signals together using ``()`` (Scala Tuple syntax) on both the left hand side and right hand side of an assignment expression."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:62
+msgid "It is important to understand that in SpinalHDL, the nature of a signal (combinational/sequential) is defined in its declaration, not by the way it is assigned. All datatype instances will define a combinational signal, while a datatype instance wrapped with ``Reg(...)`` will define a sequential (registered) signal."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:73
+msgid "Width checking"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:75
+msgid "SpinalHDL checks that the bit count of the left side and the right side of an assignment matches. There are multiple ways to adapt the width of a given BitVector (``Bits``, ``UInt``, ``SInt``):"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:81
+msgid "Resizing techniques"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:83
+msgid "x := y.resized"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:84
+msgid "Assign x with a resized copy of y, size inferred from x."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:85
+msgid "x := y.resize(newWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:86
+msgid "Assign x with a resized copy of y :code:`newWidth` bits wide."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:87
+msgid "x := y.resizeLeft(newWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:88
+msgid "Assign x with a resized copy of y :code:`newWidth` bits wide. Pads at the LSB if needed."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:91
+msgid "All resize methods may cause the resulting width to be wider or narrower than the original width of :code:`y`. When widening occurs the extra bits are padded with zeros."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:95
+msgid "The inferred conversion with ``x.resized`` is based on the target width on the left hand side of the assignment expression being resolved and obeys the same semantics as ``y.resize(someWidth)``. The expression ``x := y.resized`` is equivalent to ``x := y.resize(x.getBitsWidth bits)``."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:99
+msgid "While the example code snippets show the use of an assignment statement, the resize family of methods can be chained like any ordinary Scala method."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:102
+msgid "There is one case where Spinal automatically resizes a value:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:109
+msgid "Because ``U(3)`` is a \"weak\" bit count inferred signal, SpinalHDL widens it automatically. This can be considered to be functionally equivalent to ``U(3, 2 bits).resized`` However rest reassured SpinalHDL will do the correct thing and continue to flag an error if the scenario would require narrowing. An error is reported if the literal required 9 bits (e.g. ``U(0x100)``) when trying to assign into ``myUIntOf_8bits``."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:117
+msgid "Combinatorial loops"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:119
+msgid "SpinalHDL checks that there are no combinatorial loops (latches) in your design. If one is detected, it raises an error and SpinalHDL will print the path of the loop."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:123
+msgid "CombInit"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:125
+msgid "``CombInit`` can be used to copy a signal and its current combinatorial assignments. The main use-case is to be able to overwrite the copied later, without impacting the original signal."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:149
+msgid "If we look at the resulting Verilog, ``b`` is not present. Since it is a copy of ``a`` by reference, these variables designate the same Verilog wire."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:168
+msgid "``CombInit`` is particularly helpful in helper functions to ensure that the returned value is not referencing an input."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/assignments.rst:181
+msgid "Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` and ``a2`` reference the same signal and the zero assignment is also applied to ``a1``. With ``CombInit`` we have a coherent behaviour whatever the ``c`` value."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Semantic/index.pot b/source/locale/gettext/SpinalHDL/Semantic/index.pot
new file mode 100644
index 00000000000..277a04ca09a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Semantic/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Semantic/index.rst:5
+msgid "Semantic"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Semantic/rules.pot b/source/locale/gettext/SpinalHDL/Semantic/rules.pot
new file mode 100644
index 00000000000..d090beb885a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Semantic/rules.pot
@@ -0,0 +1,172 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Semantic/rules.rst:2
+msgid "Rules"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:4
+msgid "The semantics behind SpinalHDL are important to learn, so that you understand what is really happening behind the scenes, and how to control it."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:6
+msgid "These semantics are defined by multiple rules:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:8
+msgid "Signals and registers are operating concurrently with each other (parallel behavioral, as in VHDL and Verilog)"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:9
+msgid "An assignment to a combinational signal is like expressing a rule which is always true"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:10
+msgid "An assignment to a register is like expressing a rule which is applied on each cycle of its clock domain"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:11
+msgid "For each signal, the last valid assignment wins"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:12
+msgid "Each signal and register can be manipulated as an object during hardware elaboration in a `OOP <https://en.wikipedia.org/wiki/Object-oriented_programming>`_ manner"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:15
+msgid "Concurrency"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:17
+msgid "The order in which you assign each combinational or registered signal has no behavioral impact."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:19
+msgid "For example, both of the following pieces of code are equivalent:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:28
+msgid "This is equivalent to:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:37
+msgid "More generally, when you use the ``:=`` assignment operator, it's like specifying an additional new rule for the left side signal/register."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:40
+msgid "Last valid assignment wins"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:42
+msgid "If a combinational signal or register is assigned multiple times through the use of the SpinalHDL ``:=`` operator, the last assignment that may execute wins (and so gets to set the value as a result for this state)."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:46
+msgid "It could be said that top to bottom evaluation occurs based on the state that exists at that time.  If your upstream signal inputs are driven from registers and so have synchronous behaviour, then it could be said that at each clock cycle the assignments are re-evaluated based on the new state at the time."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:51
+msgid "Some reasons why an assignment statement may not get to execute in hardware this clock cycle, maybe due to it being wrapped in a ``when(cond)`` clause."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:54
+msgid "Another reason maybe that the SpinalHDL code never made it through elaboration because the feature was paramaterized and disabled during HDL code-generation, see ``paramIsFalse`` use below."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:58
+msgid "As an example:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:78
+msgid "This will produce the following truth table:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:83
+msgid "x"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:84
+msgid "y"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:85
+msgid "=>"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:86
+msgid "result"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:87
+#: ../../SpinalHDL/Semantic/rules.rst:88
+#: ../../SpinalHDL/Semantic/rules.rst:91
+#: ../../SpinalHDL/Semantic/rules.rst:96
+msgid "False"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:90
+#: ../../SpinalHDL/Semantic/rules.rst:94
+msgid "1"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:92
+#: ../../SpinalHDL/Semantic/rules.rst:95
+#: ../../SpinalHDL/Semantic/rules.rst:99
+#: ../../SpinalHDL/Semantic/rules.rst:100
+msgid "True"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:98
+msgid "2"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:102
+msgid "3"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:106
+msgid "Signal and register interactions with Scala (OOP reference + Functions)"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:108
+msgid "In SpinalHDL, each hardware element is modeled by a class instance. This means you can manipulate instances by using their references, such as passing them as arguments to a function."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:110
+msgid "As an example, the following code implements a register which is incremented when ``inc`` is True and cleared when ``clear`` is True (``clear`` has priority over ``inc``) :"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:124
+msgid "You can implement exactly the same functionality by mixing the previous example with a function that assigns to ``counter``:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:142
+msgid "You can also integrate the conditional check inside the function:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:158
+msgid "And also specify what should be assigned to the function:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:174
+msgid "All of the previous examples are strictly equivalent both in their generated RTL and also in the SpinalHDL compiler's perspective. This is because SpinalHDL only cares about the Scala runtime and the objects instantiated there, it doesn't care about the Scala syntax itself."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/rules.rst:177
+msgid "In other words, from a generated RTL generation / SpinalHDL perspective, when you use functions in Scala which generate hardware, it is like the function was inlined. This is also true case for Scala loops, as they will appear in unrolled form in the generated RTL."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Semantic/when_switch.pot b/source/locale/gettext/SpinalHDL/Semantic/when_switch.pot
new file mode 100644
index 00000000000..1d8c3c88f08
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Semantic/when_switch.pot
@@ -0,0 +1,156 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:2
+msgid "When/Switch/Mux"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:5
+msgid "When"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:7
+msgid "As in VHDL and Verilog, signals can be conditionally assigned when a specified condition is met:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:21
+msgid "If the keyword ``otherwise`` is on the same line as the closing bracket ``}`` of the ``when`` condition, no dot is needed."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:31
+msgid "But if ``.otherwise`` is on another line, a dot is **required**:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:43
+msgid "Switch"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:45
+msgid "As in VHDL and Verilog, signals can be conditionally assigned when a signal has a defined value:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:61
+msgid "``is`` clauses can be factorized (logical OR) by separating them with a comma ``is(value1, value2)``."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:64
+#: ../../SpinalHDL/Semantic/when_switch.rst:186
+msgid "Example"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:86
+msgid "is equivalent to"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:101
+msgid "Additional options"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:103
+msgid "By default, SpinalHDL will generate an \"UNREACHABLE DEFAULT STATEMENT\" error if a ``switch`` contains a ``default`` statement while all the possible logical values of the ``switch`` are already covered by the ``is`` statements. You can drop this error reporting by specifying `` switch(myValue, coverUnreachable = true) { ... }``."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:117
+msgid "This check is done on the logical values, not on the physical values. For instance, if you have a SpinalEnum(A,B,C) encoded in a one-hot manner, SpinalHDL will only care about the A,B,C values (\"001\" \"010\" \"100\"). Physical values as \"000\" \"011\" \"101\" \"110\" \"111\" will not be taken in account."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:120
+msgid "By default, SpinalHDL will generate a \"DUPLICATED ELEMENTS IN SWITCH IS(...) STATEMENT\" error if a given ``is`` statement provides multiple times the same value. For instance ``is(42,42) { ... }`` You can drop this error reporting by specifying ``switch(myValue, strict = true){ ... }``. SpinalHDL will then take care of removing duplicated values."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:133
+msgid "Local declaration"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:135
+msgid "It is possible to define new signals inside a when/switch statement:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:152
+msgid "SpinalHDL checks that signals defined inside a scope are only assigned inside that scope."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:155
+msgid "Mux"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:157
+msgid "If you just need a ``Mux`` with a ``Bool`` selection signal, there are two equivalent syntaxes:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:163
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:164
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:165
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:166
+msgid "Mux(cond, whenTrue, whenFalse)"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:167
+#: ../../SpinalHDL/Semantic/when_switch.rst:170
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:168
+#: ../../SpinalHDL/Semantic/when_switch.rst:171
+msgid "Return ``whenTrue`` when ``cond`` is True, ``whenFalse`` otherwise"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:169
+msgid "cond ? whenTrue | whenFalse"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:181
+msgid "Bitwise selection"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:183
+msgid "A bitwise selection looks like the VHDL ``when`` syntax."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:198
+msgid "``mux`` checks that all possible values are covered to prevent generation of latches. If all possible values are covered, the default statement must not be added:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:211
+msgid "``muxList(...)`` and ``muxListDc(...)`` are alternatives bitwise selectors that take a sequence of tuples or mappings as input."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:213
+msgid "``muxList`` can be used as a direct replacement for ``mux``, providing a easier to use interface in code that generates the cases. It has the same checking behavior as ``mux`` does, requiring full coverage and prohibiting listing a default if it is not needed."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:216
+msgid "``muxtListDc`` can be used if the uncovered values are not important, they can be left unassigned by using ``muxListDc``. This will add a default case if needed. This default case will generate X's during the simulation if ever encountered. ``muxListDc(...)`` is often a good alternative in generic code."
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:220
+msgid "Below is an example of dividing a ``Bits`` of 128 bits into 32 bits:"
+msgstr ""
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:238
+msgid "Example for ``muxListDc`` selecting bits from a configurable width vector:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Sequential logic/index.pot b/source/locale/gettext/SpinalHDL/Sequential logic/index.pot
new file mode 100644
index 00000000000..bb3258eb1ce
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Sequential logic/index.pot	
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Sequential logic/index.rst:3
+msgid "Sequential logic"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Sequential logic/memory.pot b/source/locale/gettext/SpinalHDL/Sequential logic/memory.pot
new file mode 100644
index 00000000000..4f4623c8bbe
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Sequential logic/memory.pot	
@@ -0,0 +1,411 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:2
+msgid "RAM/ROM Memory"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:4
+msgid "To create a memory in SpinalHDL, the ``Mem`` class should be used. It allows you to define a memory and add read and write ports to it."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:7
+msgid "The following table shows how to instantiate a memory:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:13
+#: ../../SpinalHDL/Sequential logic/memory.rst:40
+#: ../../SpinalHDL/Sequential logic/memory.rst:161
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:14
+#: ../../SpinalHDL/Sequential logic/memory.rst:41
+#: ../../SpinalHDL/Sequential logic/memory.rst:140
+#: ../../SpinalHDL/Sequential logic/memory.rst:162
+#: ../../SpinalHDL/Sequential logic/memory.rst:227
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:15
+msgid "``Mem(type : Data, size : Int)``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:16
+msgid "Create a RAM"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:17
+msgid "``Mem(type : Data, initialContent : Array[Data])``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:18
+msgid "Create a ROM. If your target is an FPGA, because the memory can be inferred as a block ram, you can still create write ports on it."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:22
+msgid "If you want to define a ROM, elements of the ``initialContent`` array should only be literal values (no operator, no resize functions). There is an example :ref:`here <sinus_rom>`."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:25
+msgid "To give a RAM initial values, you can also use the ``init`` function."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:28
+msgid "Write mask width is flexible, and subdivide the memory word in as many slices of equal width as the width of the mask. For instance if you have a 32 bits memory word and provide a 4 bits mask then it will be a byte mask. If you provide a as many mask bits than you have word bits, then it is a bit mask."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:32
+msgid "Manipulation of ``Mem`` is possible in simulation, see section :ref:`Load and Store of Memory in Simulation <simulation_of_memory>`."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:34
+msgid "The following table show how to add access ports on a memory :"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:42
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:43
+msgid "mem(address) := data"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:44
+msgid "Synchronous write"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:46
+msgid "mem(x)"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:47
+msgid "Asynchronous read"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:48
+#: ../../SpinalHDL/Sequential logic/memory.rst:63
+#: ../../SpinalHDL/Sequential logic/memory.rst:71
+#: ../../SpinalHDL/Sequential logic/memory.rst:84
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.write("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "address"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "data"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "[enable]"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "[mask]"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid ")"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Synchronous write with an optional mask."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "If no enable is specified, it's automatically inferred from the conditional scope where this function is called"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readAsync("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "[readUnderWrite]"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:62
+msgid "Asynchronous read with an optional read-under-write policy"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readSync("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "[clockCrossing]"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:70
+msgid "Synchronous read with an optional enable, read-under-write policy, and ``clockCrossing`` mode"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readWriteSync("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "enable"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "write"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Infer a read/write port."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "``data`` is written when ``enable && write``."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Return the read data, the read occurs when ``enable`` is true"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:88
+msgid "If for some reason you need a specific memory port which is not implemented in Spinal, you can always abstract over your memory by specifying a BlackBox for it."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:91
+msgid "Memory ports in SpinalHDL are not inferred, but are explicitly defined. You should not use coding templates like in VHDL/Verilog to help the synthesis tool to infer memory."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:93
+msgid "Here is a example which infers a simple dual port ram (32 bits * 256):"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:111
+msgid "Synchronous enable quirk"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:113
+msgid "When enable signals are used in a block guarded by a conditional block like `when`, only the enable signal will be generated as the access condition: the `when` condition is ignored."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:123
+msgid "In the example above the condition `cond` will not be elaborated. Prefer to include the condition `cond` in the enable signal directly as below."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:131
+msgid "Read-under-write policy"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:133
+msgid "This policy specifies how a read is affected when a write occurs in the same cycle to the same address."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:139
+#: ../../SpinalHDL/Sequential logic/memory.rst:226
+msgid "Kinds"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:141
+msgid "``dontCare``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:142
+msgid "Don't care about the read value when the case occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:143
+msgid "``readFirst``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:144
+msgid "The read will get the old value (before the write)"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:145
+msgid "``writeFirst``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:146
+msgid "The read will get the new value (provided by the write)"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:150
+msgid "The generated VHDL/Verilog is always in the ``readFirst`` mode, which is compatible with ``dontCare`` but not with ``writeFirst``. To generate a design that contains this kind of feature, you need to enable :ref:`automatic memory blackboxing <automatic_memory_blackboxing>`."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:153
+msgid "Mixed-width ram"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:155
+msgid "You can specify ports that access the memory with a width that is a power of two fraction of the memory width using these functions:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.writeMixedWidth("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:168
+msgid "Similar to ``mem.write``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readAsyncMixedWidth("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:174
+msgid "Similar to ``mem.readAsync``, but in place of returning the read value, it drives the signal/object given as the ``data`` argument"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readSyncMixedWidth("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:182
+msgid "Similar to ``mem.readSync``, but in place of returning the read value, it drives the signal/object given as the ``data`` argument"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "mem.readWriteSyncMixedWidth("
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:192
+msgid "Equivalent to ``mem.readWriteSync``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:196
+msgid "As for read-under-write policy, to use this feature you need to enable :ref:`automatic memory blackboxing <automatic_memory_blackboxing>`, because there is no universal VHDL/Verilog language template to infer mixed-width ram."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:201
+msgid "Automatic blackboxing"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:203
+msgid "Because it's impossible to infer all ram kinds by using regular VHDL/Verilog, SpinalHDL integrates an optional automatic blackboxing system. This system looks at all memories present in your RTL netlist and replaces them with blackboxes. Then the generated code will rely on third party IP to provide the memory features, such as the read-during-write policy and mixed-width ports."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:205
+msgid "Here is an example of how to enable blackboxing of memories by default:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:215
+msgid "If the standard blackboxing tools don't do enough for your design, do not hesitate to create a `Github issue <https://github.com/SpinalHDL/SpinalHDL/issues>`_. There is also a way to create your own blackboxing tool."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:218
+msgid "Blackboxing policy"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:220
+msgid "There are multiple policies that you can use to select which memory you want to blackbox and also what to do when the blackboxing is not feasible:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:228
+msgid "``blackboxAll``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Blackbox all memory."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Throw an error on unblackboxable memory"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:231
+msgid "``blackboxAllWhatsYouCan``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:232
+msgid "Blackbox all memory that is blackboxable"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:233
+msgid "``blackboxRequestedAndUninferable``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Blackbox memory specified by the user and memory that is known to be uninferable (mixed-width, ...)."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:236
+msgid "``blackboxOnlyIfRequested``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:0
+msgid "Blackbox memory specified by the user"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:241
+msgid "To explicitly set a memory to be blackboxed, you can use its ``generateAsBlackBox`` function."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:248
+msgid "You can also define your own blackboxing policy by extending the ``MemBlackboxingPolicy`` class."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:251
+msgid "Standard memory blackboxes"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:253
+msgid "Shown below are the VHDL definitions of the standard blackboxes used in SpinalHDL:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:365
+msgid "As you can see, blackboxes have a technology parameter. To set it, you can use the ``setTechnology`` function on the corresponding memory. There are currently 4 kinds of technologies possible:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:368
+msgid "``auto``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:369
+msgid "``ramBlock``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:370
+msgid "``distributedLut``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:371
+msgid "``registerFile``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:373
+msgid "Blackboxing can insert HDL attributes if ``SpinalConfig#setDevice(Device)`` has been configured for your device-vendor."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:376
+msgid "The resulting HDL attributes might look like:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:383
+msgid "SpinalHDL tries to support many common memory types provided by well known vendors and devices, however this is an ever moving landscape and project requirements can be very specific in this area."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:387
+msgid "If this is important to your design flow then check the output HDL for the expected attributes/generic insertion, while consulting your vendor's platform documentation."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:391
+msgid "HDL attributes can also be added manually using the `addAttribute()` :ref:`addAttribute <vhdl-and-verilog-attributes>` mechanism."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Sequential logic/registers.pot b/source/locale/gettext/SpinalHDL/Sequential logic/registers.pot
new file mode 100644
index 00000000000..f1f5e5876ba
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Sequential logic/registers.pot	
@@ -0,0 +1,165 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:4
+msgid "Registers"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:6
+msgid "Creating registers in SpinalHDL is very different than in VHDL or Verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:8
+msgid "In Spinal, there are no process/always blocks. Registers are explicitly defined at declaration. This difference from traditional event-driven HDL has a big impact:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:11
+msgid "You can assign registers and wires in the same scope, meaning the code doesn't need to be split between process/always blocks"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:12
+msgid "It make things much more flexible (see :ref:`Functions <function>`)"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:14
+msgid "Clocks and resets are handled separately, see the :ref:`Clock domain <clock_domain>` chapter for details."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:17
+msgid "Instantiation"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:19
+msgid "There are 4 ways to instantiate a register:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:25
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:26
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:27
+msgid "``Reg(type : Data)``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:28
+msgid "Register of the given type"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:29
+msgid "``RegInit(resetValue : Data)``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:30
+msgid "Register loaded with the given ``resetValue`` when a reset occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:31
+msgid "``RegNext(nextValue : Data)``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:32
+msgid "Register that samples the given ``nextValue`` each cycle"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:33
+msgid "``RegNextWhen(nextValue : Data, cond : Bool)``"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:34
+msgid "Register that samples the given ``nextValue`` when a condition occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:36
+msgid "Here is an example declaring some registers:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:56
+msgid "The code above will infer the following logic:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:62
+msgid "The ``reg3`` example above shows how you can assign the value of a ``RegInit`` register. It's possible to use the same syntax to assign to the other register types as well (``Reg``, ``RegNext``, ``RegNextWhen``). Just like in combinational assignments, the rule is 'Last assignment wins', but if no assignment is done, the register keeps its value. If the Reg is declared in a design and does not have suitable assignment and consumption it is likely to be pruned (removed from design) at some point by EDA flows after being deemed unnecessary."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:70
+msgid "Also, ``RegNext`` is an abstraction which is built over the ``Reg`` syntax. The two following sequences of code are strictly equivalent:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:84
+msgid "It is possible to have multiple options at the same time in other ways and so slightly more advanced compositions built on top of the basic understand of the above:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:125
+msgid "Reset value"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:127
+msgid "In addition to the ``RegInit(value : Data)`` syntax which directly creates the register with a reset value, you can also set the reset value by calling the ``init(value : Data)`` function on the register."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:135
+msgid "If you have a register containing a Bundle, you can use the ``init`` function on each element of the Bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:148
+msgid "Initialization value for simulation purposes"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:150
+msgid "For registers that don't need a reset value in RTL, but need an initialization value for simulation (to avoid x-propagation), you can ask for a random initialization value by calling the ``randBoot()`` function."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:158
+msgid "Register vectors"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:160
+msgid "As for wires, it is possible to define a vector of registers with ``Vec``."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:167
+msgid "Initialization can be done with the ``init`` method as usual, which can be combined with the ``foreach`` iteration on the registers."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:175
+msgid "In case where the initialization must be deferred since the init value is not known, use a function as in the example below."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:208
+msgid "Transforming a wire into a register"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:210
+msgid "Sometimes it is useful to transform an existing wire into a register. For instance, when you are using a Bundle, if you want some outputs of the bundle to be registers, you might prefer to write ``io.myBundle.PORT := newValue`` without declaring registers with ``val PORT = Reg(...)`` and connecting their output to the port with ``io.myBundle.PORT := PORT``. To do this, you just need to use ``.setAsReg()`` on the ports you want to control as registers:"
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:230
+msgid "Notice in the code above that you can also specify an initialization value."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:234
+msgid "The register is created in the clock domain of the wire, and does not depend on the place where ``.setAsReg()`` is used."
+msgstr ""
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:237
+msgid "In the example above, the wire is defined in the ``io`` Bundle, in the same clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` was written in a ``ClockingArea`` with a different clock domain, the register would use the clock domain of the component and not the one of the ``ClockingArea``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot b/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot
new file mode 100644
index 00000000000..ecb38b1171d
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot
@@ -0,0 +1,237 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:3
+msgid "Boot a simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:6
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:8
+msgid "Below is an example hardware definition + testbench:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:46
+msgid "Configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:48
+msgid "``SimConfig`` will return a default simulation configuration instance on which you can call multiple functions to configure your simulation:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:54
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:55
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:56
+msgid "``withWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:57
+msgid "Enable simulation wave capture (default format)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:58
+msgid "``withVcdWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:59
+msgid "Enable simulation wave capture (VCD text format)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:60
+msgid "``withFstWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:61
+msgid "Enable simulation wave capture (FST binary format)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:62
+msgid "``withConfig(SpinalConfig)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:63
+msgid "Specify the ``SpinalConfig`` that should be use to generate the hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:64
+msgid "``allOptimisation``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:65
+msgid "Enable all the RTL compilation optimizations to reduce simulation time (will increase compilation time)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:66
+msgid "``workspacePath(path)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:67
+msgid "Change the folder where the sim files are generated"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:68
+msgid "``withVerilator``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:69
+msgid "Use Verilator as simulation backend (default)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:70
+msgid "``withGhdl``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:71
+msgid "Use GHDL as simulation backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:72
+msgid "``withIVerilog``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:73
+msgid "Use Icarus Verilog as simulation backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:74
+msgid "``withVCS``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:75
+msgid "Use Synopsys VCS as simulation backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:77
+msgid "Then you can call the ``compile(rtl)`` function to compile the hardware and warm up the simulator. This function will return a ``SimCompiled`` instance."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:80
+msgid "On this ``SimCompiled`` instance you can run your simulation with the following functions:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:86
+msgid "``doSim[(simName[, seed])]{dut => /* main stimulus code */}``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:83
+msgid "Run the simulation until the main thread runs to completion and exits/returns. It will detect and report an error if the simulation gets fully stuck. As long as e.g. a clock is running the simulation can continue forever, it is therefore recommended to use ``SimTimeout(cycles)`` to limit the possible runtime."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:91
+msgid "``doSimUntilVoid[(simName[, seed])]{dut => ...}``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:89
+msgid "Run the simulation until it is ended by calling either ``simSuccess()`` or ``simFailure()``. The main stimulus thread can continue or exit early. As long as there are events to process, the simulation will continue. The simulation will report an error if it gets fully stuck."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:93
+msgid "The following testbench template will use the following toplevel :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:102
+msgid "Here is a template with many simulation configurations:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:119
+msgid "Here is a template where the simulation ends by completing the simulation main thread execution:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:130
+msgid "Here is a template where the simulation ends by explicitly calling `simSuccess()`:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:144
+msgid "Note is it equivalent to:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:161
+msgid "Note that by default, the simulation files will be placed into the ``simWorkspace/xxx`` folders. You can override the simWorkspace location by setting the ``SPINALSIM_WORKSPACE`` environment variable."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:164
+msgid "Running multiple tests on the same hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:179
+msgid "Throw Success or Failure of the simulation from a thread"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:181
+msgid "At any moment during a simulation you can call ``simSuccess`` or ``simFailure`` to end it."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:183
+msgid "It is possible to make a simulation fail when it is too long, for instance because the test-bench is waiting for a condition which never occurs. To do so, call ``SimTimeout(maxDuration)`` where ``maxDuration`` is the time (in simulation units of time) after the which the simulation should be considered to have failed."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:185
+msgid "For instance, to make the simulation fail after 1000 times the duration of a clock cycle:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:194
+msgid "Capturing wave for a given window before failure"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:196
+msgid "In the case you have a very long simulation, and you don't want to capture the wave on all of it (too bug, too slow), you have mostly 2 ways to do it."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:198
+msgid "Either you know already at which ``simTime`` the simulation failed, in which case you can do the following in your testbench :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:205
+msgid "Or you can run a dual lock-step simulation, with one running a bit delayed from the the other one, and which will start recording the wave once the leading simulation had a failure."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:207
+msgid "To do this, you can use the DualSimTracer utility, with parameters for the compiled hardware, the window of time you want to capture before failure, and a seed."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:209
+msgid "Here is an example :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:214
+msgid "This will generate the following file structure :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:216
+msgid "simWorkspace/Toplevel/explorer/stdout.log : stdout of the simulation which is ahead"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:217
+msgid "simWorkspace/Toplevel/tracer/stdout.log : stdout of the simulation doing the wave tracing"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:218
+msgid "simWorkspace/Toplevel/tracer.fst : Waveform of the failure"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:220
+msgid "The scala terminal will show the explorer simulation stdout."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/clock.pot b/source/locale/gettext/SpinalHDL/Simulation/clock.pot
new file mode 100644
index 00000000000..8c0b46f0c63
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/clock.pot
@@ -0,0 +1,298 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/clock.rst:2
+msgid "Clock domains"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:5
+msgid "Stimulus API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:7
+msgid "Below is a list of ``ClockDomain`` stimulation functions:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:13
+msgid "ClockDomain stimulus functions"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:14
+#: ../../SpinalHDL/Simulation/clock.rst:48
+#: ../../SpinalHDL/Simulation/clock.rst:84
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:15
+msgid "``forkStimulus(period)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:16
+msgid "Fork a simulation process to generate the ClockDomain stimulus (clock, reset, softReset, clockEnable signals)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:17
+msgid "``forkSimSpeedPrinter(printPeriod)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:18
+msgid "Fork a simulation process which will periodically print the simulation speed in kilo-cycles per real time second. ``printPeriod`` is in realtime seconds"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:19
+msgid "``clockToggle()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:20
+msgid "Toggle the clock signal"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:21
+msgid "``fallingEdge()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:22
+msgid "Clear the clock signal"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:23
+msgid "``risingEdge()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:24
+msgid "Set the clock signal"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:25
+msgid "``assertReset()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:26
+msgid "Set the reset signal to its active level"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:27
+msgid "``deassertReset()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:28
+msgid "Set the reset signal to its inactive level"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:29
+msgid "``assertClockEnable()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:30
+#: ../../SpinalHDL/Simulation/clock.rst:32
+msgid "Set the clockEnable signal to its active level"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:31
+msgid "``deassertClockEnable()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:33
+msgid "``assertSoftReset()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:34
+#: ../../SpinalHDL/Simulation/clock.rst:36
+msgid "Set the softReset signal to its active level"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:35
+msgid "``deassertSoftReset()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:39
+msgid "Wait API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:41
+#: ../../SpinalHDL/Simulation/clock.rst:77
+msgid "Below is a list of ``ClockDomain`` utilities that you can use to wait for a given event from the domain:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:47
+msgid "ClockDomain wait functions"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:49
+msgid "``waitSampling([cyclesCount])``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:50
+msgid "Wait until the ``ClockDomain`` makes a sampling, (active clock edge && deassertReset && assertClockEnable)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:51
+msgid "``waitRisingEdge([cyclesCount])``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:52
+msgid "Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 cycle if not otherwise specified. Note, cyclesCount = 0 is legal, and the function is not sensitive to reset/softReset/clockEnable"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:53
+msgid "``waitFallingEdge([cyclesCount])``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:54
+msgid "Same as ``waitRisingEdge`` but for the falling edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:55
+msgid "``waitActiveEdge([cyclesCount])``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:56
+msgid "Same as ``waitRisingEdge`` but for the edge level specified by the ``ClockDomainConfig``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:57
+msgid "``waitRisingEdgeWhere(condition)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:58
+msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:59
+msgid "``waitFallingEdgeWhere(condition)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:60
+msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:61
+msgid "``waitActiveEdgeWhere(condition)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:62
+msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:63
+msgid "``waitSamplingWhere(condition) : Boolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:64
+msgid "Wait until a clockdomain sampled and the given condition is true"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:65
+msgid "``waitSamplingWhere(timeout)(condition) : Boolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:66
+msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:70
+msgid "All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:75
+msgid "Callback API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:83
+msgid "ClockDomain callback functions"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:85
+msgid "``onNextSampling { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:86
+msgid "Execute the callback code only once on the next ``ClockDomain`` sample (active edge + reset off + clock enable on)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:87
+msgid "``onSamplings { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:88
+msgid "Execute the callback code each time the ``ClockDomain`` sample (active edge + reset off + clock enable on)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:89
+msgid "``onActiveEdges { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:90
+msgid "Execute the callback code each time the ``ClockDomain`` clock generates its configured edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:91
+msgid "``onEdges { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:92
+msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising or falling edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:93
+msgid "``onRisingEdges { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:94
+msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:95
+msgid "``onFallingEdges { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:96
+msgid "Execute the callback code each time the ``ClockDomain`` clock generates a falling edge"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:97
+msgid "``onSamplingWhile { callback : Boolean }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:98
+msgid "Same as onSampling, but you can stop it (forever) by letting the callback returning false"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:103
+msgid "Default ClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:105
+msgid "You can access the default ``ClockDomain`` of your toplevel as shown below:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:121
+msgid "Note that you can also directly fork a standard reset/clock process:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:127
+msgid "An example of how to wait for a rising edge on the clock:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:135
+msgid "New ClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:137
+msgid "If your toplevel defines some clock and reset inputs which aren't directly integrated into their ``ClockDomain``, you can define their corresponding ``ClockDomain`` directly in the testbench:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/engine.pot b/source/locale/gettext/SpinalHDL/Simulation/engine.pot
new file mode 100644
index 00000000000..27e9f996c62
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/engine.pot
@@ -0,0 +1,73 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/engine.rst:5
+msgid "Simulation engine"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:7
+msgid "This page explains the internals of the simulation engine."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:9
+msgid "The simulation engine emulates an event-driven simulator (VHDL/Verilog like) by applying the following simulation loop on the top of the Verilator C++ simulation model:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:14
+msgid "At a low level, the simulation engine manages the following primitives:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:16
+msgid "*Sensitive callbacks*, which allow users to call a function on each simulation delta cycle."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:17
+msgid "*Delayed callbacks*, which allow users to call a function at a future simulation time."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:18
+msgid "*Simulation threads*, which allow users to describe concurrent processes."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:19
+msgid "*Command buffer*, which allows users to delay write access to the :abbr:`DUT (Device Under Test)` until the end of the current delta cycle."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:21
+msgid "There are some practical uses of those primitives:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:23
+msgid "Sensitive callbacks can be used to wake up a simulation thread when a given condition happens, like a rising edge on a clock."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:24
+msgid "Delayed callbacks can be used to schedule stimuli, such as deasserting a reset after a given time, or toggling the clock."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:25
+msgid "Both sensitive and delayed callbacks can be used to resume a simulation thread."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:26
+msgid "A simulation thread can be used (for instance) to produce stimulus and check the DUT's output values."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/engine.rst:27
+msgid "The command buffer's purpose is mainly to avoid all concurrency issues between the DUT and the testbench."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/asynchronous.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/asynchronous.pot
new file mode 100644
index 00000000000..a158e71b3fb
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/asynchronous.pot
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:4
+msgid "Asynchronous adder"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:6
+msgid "This example creates a ``Component`` out of combinational logic that does some simple arithmetic on 3 operands."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:8
+msgid "The test bench performs the following steps 100 times:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:10
+msgid "Initialize ``a``, ``b``, and ``c`` to random integers in the 0..255 range."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:11
+msgid "Stimulate the :abbr:`DUT (Device Under Test)`'s matching ``a``, ``b``, ``c`` inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:12
+msgid "Wait 1 simulation timestep (to allow the inputs to propagate)."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/asynchronous.rst:13
+msgid "Check for correct output."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/dual_clock_fifo.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/dual_clock_fifo.pot
new file mode 100644
index 00000000000..d5ac110c427
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/dual_clock_fifo.pot
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:4
+msgid "Dual clock fifo"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:6
+msgid "This example creates a ``StreamFifoCC``, which is designed for crossing clock domains, along with 3 simulation threads."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:8
+msgid "The threads handle:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:10
+msgid "Management of the two clocks"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:11
+msgid "Pushing to the FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:12
+msgid "Popping from the FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:14
+msgid "The FIFO push thread randomizes the inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/dual_clock_fifo.rst:16
+msgid "The FIFO pop thread handles checking the the :abbr:`DUT (Device Under Test)`'s outputs against the reference model (an ordinary ``scala.collection.mutable.Queue`` instance)."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/index.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/index.pot
new file mode 100644
index 00000000000..af6522ef09a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/index.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/index.rst:3
+msgid "Examples"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/single_clock_fifo.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/single_clock_fifo.pot
new file mode 100644
index 00000000000..a5ddf73355e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/single_clock_fifo.pot
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:4
+msgid "Single clock fifo"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:6
+msgid "This example creates a ``StreamFifo``, and spawns 3 simulation threads. Unlike the :ref:`Dual clock fifo <sim_example_dual_clock_fifo>` example, this FIFO does not need complex clock management."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:9
+msgid "The 3 simulation threads handle:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:11
+msgid "Managing the clock/reset"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:12
+msgid "Pushing to the FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:13
+msgid "Popping from the FIFO"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:15
+msgid "The FIFO push thread randomizes the inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/single_clock_fifo.rst:17
+msgid "The FIFO pop thread handles checking the the :abbr:`DUT (Device Under Test)`'s outputs against the reference model (an ordinary ``scala.collection.mutable.Queue`` instance)."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/synchronous.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/synchronous.pot
new file mode 100644
index 00000000000..c378c4cadd6
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/synchronous.pot
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:4
+msgid "Synchronous adder"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:6
+msgid "This example creates a ``Component`` out of sequential logic that does some simple arithmetic on 3 operands."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:8
+msgid "The test bench performs the following steps 100 times:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:10
+msgid "Initialize ``a``, ``b``, and ``c`` to random integers in the 0..255 range."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:11
+msgid "Stimulate the :abbr:`DUT (Device Under Test)`'s matching ``a``, ``b``, ``c`` inputs."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:12
+msgid "Wait until the simulation samples the DUT's signals again."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:13
+msgid "Check for correct output."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/examples/synchronous.rst:15
+msgid "The main difference between this example and the :ref:`Asynchronous adder <sim_example_asynchronous_adder>` example is that this ``Component`` has to use ``forkStimulus`` to generate a clock signal, since it is using sequential logic internally."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/uart_decoder.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/uart_decoder.pot
new file mode 100644
index 00000000000..f867904a140
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/uart_decoder.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/uart_decoder.rst:3
+msgid "Uart decoder"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/examples/uart_encoder.pot b/source/locale/gettext/SpinalHDL/Simulation/examples/uart_encoder.pot
new file mode 100644
index 00000000000..17b78cfbd4a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/examples/uart_encoder.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/examples/uart_encoder.rst:3
+msgid "Uart encoder"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/index.pot b/source/locale/gettext/SpinalHDL/Simulation/index.pot
new file mode 100644
index 00000000000..863d62d524e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/index.pot
@@ -0,0 +1,53 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/index.rst:3
+msgid "Simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:5
+msgid "As always, you can use your standard simulation tools to simulate the VHDL/Verilog generated by SpinalHDL. However, since SpinalHDL 1.0.0, the language integrates an API to write testbenches and test your hardware directly in Scala. This API provides the capabilities to read and write the DUT signals, fork and join simulation processes, sleep and wait until a given condition is reached. Therefore, using SpinalHDL's simulation API, it is easy to integrate testbenches with the most common Scala unit-test frameworks."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:11
+msgid "To be able to simulate user-defined components, SpinalHDL uses external HDL simulators as backend. Currently, four simulators are supported:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:13
+msgid "`Verilator <https://www.veripool.org/verilator/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:14
+msgid "`GHDL <http://ghdl.free.fr/>`_ **(experimental, since SpinalHDL 1.4.1)**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:15
+msgid "`Icarus Verilog <https://steveicarus.github.io/iverilog/>`_ **(experimental, since SpinalHDL 1.4.1)**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:16
+msgid "`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`_ **(experimental, since SpinalHDL 1.7.0)**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:17
+msgid "`XSim <https://www.google.com/search?q=site%3Axilinx.com+xsim>`_ **(experimental, since SpinalHDL 1.7.0)**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/index.rst:19
+msgid "With external HDL simulators it is possible to directly test the generated HDL sources without increasing the SpinalHDL codebase complexity."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/GHDL.pot b/source/locale/gettext/SpinalHDL/Simulation/install/GHDL.pot
new file mode 100644
index 00000000000..60afae4932a
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/install/GHDL.pot
@@ -0,0 +1,41 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:3
+msgid "Setup and installation of GHDL"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:6
+msgid "If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup <Install>` you can skip the instructions below - but you need to activate the oss-cad-suite environment."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:9
+msgid "Even though GHDL is generally available in linux distributions package system, SpinalHDL depends on bugfixes of GHDL codebase that were added after the release of GHDL v0.37. Therefore it is reccomended to install GHDL from source. The C++ library boost-interprocess, which is contained in the libboost-dev package in debian-like distributions, has to be installed too. boost-interprocess is required to generate the shared memory communication interface."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:13
+msgid "Linux"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:29
+msgid "Also the openjdk package that corresponds to your Java version has to be installed."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:31
+msgid "For more configuration options and Windows installation see `<https://ghdl.github.io/ghdl/getting.html>`_"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot b/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot
new file mode 100644
index 00000000000..d844d4cad62
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot	
@@ -0,0 +1,37 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:3
+msgid "Setup and installation of Icarus Verilog"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:6
+msgid "If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup <Install>` you can skip the instructions below - but you need to activate the oss-cad-suite environment."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:9
+msgid "In most recent linux distributions, a recent version of Icarus Verilog is generally available through the package system. The C++ library boost-interprocess, which is contained in the libboost-dev package in debian-like distributions, has to be installed too. boost-interprocess is required to generate the shared memory communication interface."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:13
+msgid "Linux"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:20
+msgid "Also the openjdk package that corresponds to your Java version has to be installed. Refer to `<https://iverilog.fandom.com/wiki/Installation_Guide>`_ for more informations about Windows and installation from source."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot b/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot
new file mode 100644
index 00000000000..36756691648
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot
@@ -0,0 +1,196 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:3
+msgid "VCS Simulation Configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:8
+msgid "Environment variable"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:10
+msgid "You should have several environment variables defined before:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:12
+msgid "``VCS_HOME``: The home path to your VCS installation."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:13
+msgid "``VERDI_HOME``: The home path to your Verdi installation."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:14
+msgid "Add ``$VCS_HOME/bin`` and ``$VERDI_HOME/bin`` to your ``PATH``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:16
+msgid "Prepend the following paths to your ``LD_LIBRARY_PATH`` to enable PLI features."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:26
+msgid "If you encounter the ``Compilation of SharedMemIface.cpp failed`` error, make sure that you have installed C++ boost library correctly. The header and library files path should be added to ``CPLUS_INCLUDE_PATH``, ``LIBRARY_PATH`` and ``LD_LIBRARY_PATH`` respectively."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:30
+msgid "User defined environment setup"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:32
+msgid "Sometimes a VCS environment setup file `synopsys_sim.setup` is required to run VCS simulation. Also you may want to run some scripts or code to setup the environment just before VCS starting compilation. You can do this by `withVCSSimSetup`."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:47
+msgid "This method will copy your own `synopsys_sim.setup` file to the VCS work directory under the `workspacePath` (default as `simWorkspace`) directory, and run your scripts."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:51
+msgid "VCS Flags"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:53
+msgid "The VCS backend follows the three step compilation flow:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:55
+msgid "Analysis step: analysis the HDL model using ``vlogan`` and ``vhdlan``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:57
+msgid "Elaborate step: elaborate the model using ``vcs`` and generate the executable hardware model."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:59
+msgid "Simulation step: run the simulation."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:61
+msgid "In each step, user can pass some specific flags through ``VCSFlags`` to enable some features like SDF back-annotation or multi-threads."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:63
+msgid "``VCSFlags`` takes three parameters,"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:69
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:70
+msgid "Type"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:71
+#: ../../SpinalHDL/Simulation/install/VCS.rst:112
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:72
+msgid "``compileFlags``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:73
+#: ../../SpinalHDL/Simulation/install/VCS.rst:76
+#: ../../SpinalHDL/Simulation/install/VCS.rst:79
+msgid "``List[String]``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:74
+msgid "Flags pass to ``vlogan`` or ``vhdlan``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:75
+msgid "``elaborateFlags``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:77
+msgid "Flags pass to ``vcs``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:78
+msgid "``runFlags``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:80
+msgid "Flags pass to executable hardware model."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:82
+msgid "For example, you pass the ``-kdb`` flags to both compilation step and elaboration step, for Verdi debugging,"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:101
+msgid "Waveform generation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:103
+msgid "VCS backend can generate three waveform format: ``VCD``, ``VPD`` and ``FSDB`` (Verdi required)."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:105
+msgid "You can enable them by the following methods of ``SpinalSimConfig``,"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:111
+msgid "Method"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:113
+msgid "``withWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:114
+msgid "Enable ``VCD`` waveform."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:115
+msgid "``withVPDWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:116
+msgid "Enable ``VPD`` waveform."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:117
+msgid "``withFSDBWave``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:118
+msgid "Enable ``FSDB`` waveform."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:120
+msgid "Also, you can control the wave trace depth by using ``withWaveDepth(depth: Int)``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:123
+msgid "Simulation with ``Blackbox``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:125
+msgid "Sometimes, IP vendors will provide you with some design entites in Verilog/VHDL format and you want to integrate them into your SpinalHDL design. The integration can done by following two ways:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:128
+msgid "In a ``Blackbox`` definition, use ``addRTLPath(path: String)`` to assign a external Verilog/VHDL file to this blackbox."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:129
+msgid "Use the method ``mergeRTLSource(fileName: String=null)`` of ``SpinalReport``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot b/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot
new file mode 100644
index 00000000000..86743d09720
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot
@@ -0,0 +1,105 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:3
+msgid "Setup and installation of Verilator"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:6
+msgid "If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup <Install>` you can skip the instructions below - but you need to activate the oss-cad-suite environment."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:9
+msgid "SpinalSim + Verilator is supported on both Linux and Windows platforms."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:11
+msgid "It is recommended that v4.218 is the oldest Verilator version to use.  While it maybe possible to use older verilator versions, some optional and Scala source dependent features that SpinalHDL can use (such as Verilog ``$urandom`` support) may not be supported by older Verilator versions and will cause an error when trying to simulate."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:16
+msgid "Ideally the latest v4.xxx and v5.xxx is well supported and bug reports should be opened with any issues you have."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:20
+msgid "Scala"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:22
+msgid "Don't forget to add the following in your ``build.sbt`` file:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:28
+msgid "And you will always need the following imports in your Scala testbench:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:36
+msgid "Linux"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:38
+msgid "You will also need a recent version of Verilator installed :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:56
+msgid "Windows"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:58
+msgid "In order to get SpinalSim + Verilator working on Windows, you have to do the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:60
+msgid "Install `MSYS2 <https://www.msys2.org/>`_"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:61
+msgid "Via MSYS2 get gcc/g++/verilator (for Verilator you can compile it from the sources)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:62
+msgid "Add ``bin`` and ``usr\\bin`` of MSYS2 into your windows ``PATH`` (ie : ``C:\\msys64\\usr\\bin;C:\\msys64\\mingw64\\bin``)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:63
+msgid "Check that the JAVA_HOME environment variable points to the JDK installation folder (i.e.: ``C:\\Program Files\\Java\\jdk-13.0.2``)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:65
+msgid "Then you should be able to run SpinalSim + Verilator from your Scala project without having to use MSYS2 anymore."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:67
+msgid "From a fresh install of MSYS2 MinGW 64-bit, you will have to run the following commands inside the MSYS2 MinGW 64-bits shell (enter commands one by one):"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:70
+msgid "From the MinGW package manager"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:86
+msgid "From source"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:114
+msgid "Be sure that your ``PATH`` environnement variable is pointing to the JDK 1.8 and doesn't contain a JRE installation."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:117
+msgid "Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could potentialy have some side effects. This is why it is safer to add them as the last elements of the ``PATH`` to reduce their priority."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/index.pot b/source/locale/gettext/SpinalHDL/Simulation/install/index.pot
new file mode 100644
index 00000000000..5862895d9cf
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/install/index.pot
@@ -0,0 +1,37 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/install/index.rst:2
+msgid "SBT setup for simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/index.rst:4
+msgid "To enable SpinalSim, the following lines have to be added in your build.sbt file :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/index.rst:10
+msgid "Also the following imports have to be added in testbenches sources :"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/index.rst:19
+msgid "Also, if you need to use gmake instead of make (ex OpenBSD) you can set the SPINAL_MAKE_CMD environnement variable to \"gmake\""
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/install/index.rst:22
+msgid "Backend-dependent installation instructions"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/sensitive.pot b/source/locale/gettext/SpinalHDL/Simulation/sensitive.pot
new file mode 100644
index 00000000000..10bb59e953c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/sensitive.pot
@@ -0,0 +1,49 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:4
+msgid "Sensitive API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:6
+msgid "You can register callback functions to be called on each delta-cycle of the simulation:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:12
+msgid "Sensitive functions"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:13
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:14
+msgid "``forkSensitive { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:15
+msgid "Register the callback code to be called at each delta-cycle of the simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:16
+msgid "``forkSensitiveWhile { callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/sensitive.rst:17
+msgid "Register the callback code to be called at each delta-cycle of the simulation, while the callback return value is true (meaning it should be rescheduled for the next delta-cycle)"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/signal.pot b/source/locale/gettext/SpinalHDL/Simulation/signal.pot
new file mode 100644
index 00000000000..effe2797e75
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/signal.pot
@@ -0,0 +1,195 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/signal.rst:2
+msgid "Accessing signals of the simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:5
+msgid "Read and write signals"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:7
+msgid "Each interface signal of the toplevel can be read and written from Scala:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:13
+#: ../../SpinalHDL/Simulation/signal.rst:124
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:14
+#: ../../SpinalHDL/Simulation/signal.rst:125
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:15
+msgid "``Bool.toBoolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:16
+msgid "Read a hardware ``Bool`` as a Scala ``Boolean`` value"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:17
+msgid "``Bits``/``UInt``/``SInt.toInt``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:18
+msgid "Read a hardware ``BitVector`` as a Scala ``Int`` value"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:19
+msgid "``Bits``/``UInt``/``SInt.toLong``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:20
+msgid "Read a hardware ``BitVector`` as a Scala ``Long`` value"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:21
+msgid "``Bits``/``UInt``/``SInt.toBigInt``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:22
+msgid "Read a hardware ``BitVector`` as a Scala ``BigInt`` value"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:23
+msgid "``SpinalEnumCraft.toEnum``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:24
+msgid "Read a hardware ``SpinalEnumCraft`` as a Scala ``SpinalEnumElement`` value"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:25
+msgid "``Bool #= Boolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:26
+msgid "Assign a hardware ``Bool`` from an Scala ``Boolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:27
+msgid "``Bits``/``UInt``/``SInt #= Int``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:28
+msgid "Assign a hardware ``BitVector`` from a Scala ``Int``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:29
+msgid "``Bits``/``UInt``/``SInt #= Long``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:30
+msgid "Assign a hardware ``BitVector`` from a Scala ``Long``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:31
+msgid "``Bits``/``UInt``/``SInt #= BigInt``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:32
+msgid "Assign a hardware ``BitVector`` from a Scala ``BigInt``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:33
+msgid "``SpinalEnumCraft #= SpinalEnumElement``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:34
+msgid "Assign a hardware ``SpinalEnumCraft`` from a Scala ``SpinalEnumElement``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:35
+msgid "``Data.randomize()``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:36
+msgid "Assign a random value to a SpinalHDL value."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:48
+msgid "Accessing signals inside the component's hierarchy"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:50
+msgid "To access signals which are inside the component's hierarchy, you have first to set the given signal as ``simPublic``."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:52
+msgid "You can add this ``simPublic`` tag directly in the hardware description:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:76
+msgid "Or you can add it later, after having instantiated your toplevel for the simulation:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:108
+msgid "Load and Store of Memory in Simulation"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:110
+msgid "It is possible to modify the contents of ``Mem`` hardware interface components in simulation.  The `data` argument should be a word-width value with the `address` being the word-address within."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:114
+msgid "There is no API to convert address and/or individual data bits into units other than the natural word size."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:117
+msgid "There is no API to mark any memory location with simulation `X` (undefined) state."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:126
+msgid "``Mem.getBigInt(address: Long): BigInt``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:127
+msgid "Read a word from simulator at the word-address."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:128
+msgid "``Mem.setBigInt(address: Long, data: BigInt)``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:129
+msgid "Write a word to simulator at the word-address."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:131
+msgid "Using this simple example using a memory:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:138
+msgid "Setting up the simulation we make the memory accessible:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:145
+msgid "We can read data during simulation, but have to take care that the data is already available (might be a cycle late due to simulation event ordering):"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:153
+msgid "And can write to memory like so:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/signal.rst:160
+msgid "Care has to be taken that due to event ordering in simulation e.g. the read depicted above has to be delayed to when the value is actually available in the memory."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/simulator_specifics.pot b/source/locale/gettext/SpinalHDL/Simulation/simulator_specifics.pot
new file mode 100644
index 00000000000..1afcf291246
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/simulator_specifics.pot
@@ -0,0 +1,175 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:3
+msgid "Simulator specific details"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:6
+msgid "How SpinalHDL simulates the hardware with Verilator backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:8
+msgid "Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model of the DUT and then uses Verilator to convert it to a C++ cycle-accurate model."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:9
+msgid "The C++ model is compiled into a shared object (.so), which is bound to Scala via JNI-FFI."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:10
+msgid "The native Verilator API is abstracted by providing a simulation multi-threaded API."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:12
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:29
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:49
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:69
+msgid "**Advantages:**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:14
+msgid "Since the Verilator backend uses a compiled C++ simulation model, the simulation speed is fast compared to most of the other commercial and free simulators."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:16
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:34
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:56
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:73
+msgid "**Limitations:**"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:18
+msgid "Verilator accepts only synthesizable Verilog/System Verilog code. Therefore special care has to be taken when simulating Verilog blackbox components that may have non-synthesizable statements."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:19
+msgid "VHDL blackboxes cannot be simulated."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:20
+msgid "The simulation boot process is slow due to the necessity to compile and link the generated C++ model.  Some support to incrementally compile and link exists which can provide speedups for subsequent simulations after building the first."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:23
+msgid "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:25
+msgid "Depending on the chosen simulator, SpinalHDL generates a Verilog or VHDL hardware model of the DUT."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:26
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:46
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:66
+msgid "The HDL model is loaded in the simulator."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:27
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:47
+msgid "The communication between the simulation and the JVM is established through shared memory. The commands are issued to the simulator using `VPI <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:31
+msgid "Both GHDL and Icarus Verilog can accept non-synthesizable HDL code."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:32
+msgid "The simulation boot process is quite faster compared to Verilator."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:36
+msgid "GHDL accepts VHDL code only. Therefore only VHDL blackboxes can be used with this simulator."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:37
+msgid "Icarus Verilog accepts Verilog code only. Therefore only Verilog blackboxes can be used with this simulator."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:38
+msgid "The simulation speed is around one order of magnitude slower compared to Verilator."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:40
+msgid "Finally, as the native Verilator API is rather crude, SpinalHDL abstracts over it by providing both single and multi-threaded simulation APIs to help the user construct testbench implementations."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:43
+msgid "How SpinalHDL simulates the hardware with Synopsys VCS backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:45
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:65
+msgid "SpinalHDL generates a Verilog/VHDL (depended on your choice) hardware model of the DUT."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:51
+msgid "Support all language features of SystemVerilog/Verilog/VHDL."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:52
+msgid "Support encrypted IP."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:53
+msgid "Support FSDB wave format dump."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:54
+msgid "High Performance of both compilation and simulation."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:58
+msgid "Synopsys VCS is a **commercial** simulation tool. It is close source and not free. You have to own the licenses to **legally** use it."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:60
+msgid "Before using VCS as the simulation backend, make sure that you have checked your system environment as :ref:`VCS environment<vcs_env>`."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:63
+msgid "How SpinalHDL simulates the hardware with Xilinx XSim backend"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:67
+msgid "The communication between the simulation and the JVM is established through shared memory. The commands are issued to the simulator using XSI."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:71
+msgid "Support Xilinx built-in primitives and cores."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:75
+msgid "Xilinx XSim is a **commercial** tool installed with Vivado. It is closed source and subject to licensing terms to use. You have to own the licenses to **legally** use it."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:76
+msgid "Vivado versions prior to 2019.1 do not work properly."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:78
+msgid "Before using XSim as the simulation backend, make sure that you have done following steps. 1. Define VIVADO_HOME environment variable to specify where your vivado located. ex `export VIVADO_HOME=/d/Xilinx/Vivado/2022.1` (under MSYS2). 2. Make sure two vivado path is inside the PATH. For Windows MSYS2 user, run shell command like `export PATH=$PATH:$VIVADO_HOME/bin:$VIVADO_HOME/lib/win64.o`. For Linux user just source the Vivado's settings64.sh file located at `VIVADO_HOME`."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:83
+msgid "Performance"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:85
+msgid "When a high-performance simulation is required, Verilator should be used as a backend. On a little SoC like `Murax <https://github.com/SpinalHDL/VexRiscv>`_, an Intel® Core™ i7-4720HQ is capable of simulating 1.2 million clock cycles per second. However, when the DUT is simple and a maximum of few thousands clock cycles have to be simulated, using GHDL or Icarus Verilog could yield a better result, due to their lower simulation loading overhead."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/threadFull.pot b/source/locale/gettext/SpinalHDL/Simulation/threadFull.pot
new file mode 100644
index 00000000000..8ccb56ac373
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/threadFull.pot
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/threadFull.rst:2
+msgid "Thread-full API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadFull.rst:4
+msgid "In SpinalSim, you can write your testbench by using multiple threads in a similar way to SystemVerilog, and a bit like VHDL/Verilog process/always blocks. This allows you to write concurrent tasks and control the simulation time using a fluent API."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadFull.rst:9
+msgid "Fork and join simulation threads"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadFull.rst:22
+msgid "Sleep and waitUntil"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Simulation/threadLess.pot b/source/locale/gettext/SpinalHDL/Simulation/threadLess.pot
new file mode 100644
index 00000000000..b586245d920
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Simulation/threadLess.pot
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:2
+msgid "Thread-less API"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:4
+msgid "There are some functions that you can use to avoid the need for threading, but which still allow you to control the flow of simulation time."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:10
+msgid "Threadless functions"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:11
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:12
+msgid "``delayed(delay){ callback }``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:13
+msgid "Register the callback code to be called at a simulation time ``delay`` steps after the current timestep."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:15
+msgid "The advantages of the ``delayed`` function over using a regular simulation thread + sleep are:"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:17
+msgid "Performance (no context switching)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:18
+msgid "Memory usage (no native JVM thread memory allocation)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/threadLess.rst:20
+msgid "Some other thread-less functions related to ``ClockDomain`` objects are documented as part of the :ref:`Callback API <sim_clock_threadless>`, and some others related with the delta-cycle execution process are documented as part of the :ref:`Sensitive API <sim_sensitive_api>`"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/area.pot b/source/locale/gettext/SpinalHDL/Structuring/area.pot
new file mode 100644
index 00000000000..80570410d3e
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/area.pot
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/area.rst:2
+msgid "Area"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:4
+msgid "Sometimes, creating a ``Component`` to define some logic is overkill because you:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:6
+msgid "Need to define all construction parameters and IO (verbosity, duplication)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:7
+msgid "Split your code (more than needed)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:9
+msgid "For this kind of case you can use an ``Area`` to define a group of signals/logic:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:0
+msgid "In VHDL and Verilog, sometimes prefixes are used to separate variables into logical sections. It is suggested that you use ``Area`` instead  of this in SpinalHDL."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/area.rst:44
+msgid "\\ :ref:`ClockingArea <clock_domain>` is a special kind of ``Area`` that allows you to define chunks of hardware which use a given ``ClockDomain``\\"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/blackbox.pot b/source/locale/gettext/SpinalHDL/Structuring/blackbox.pot
new file mode 100644
index 00000000000..0038667d8e7
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/blackbox.pot
@@ -0,0 +1,181 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:4
+msgid "Instantiate VHDL and Verilog IP"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:7
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:9
+msgid "A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying its interfaces. It's up to the simulator or synthesizer to do the elaboration correctly."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:13
+msgid "Defining an blackbox"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:15
+msgid "An example of how to define a blackbox is shown below:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:46
+msgid "In VHDL, signals of type ``Bool`` will be translated into ``std_logic`` and ``Bits`` into ``std_logic_vector``. If you want to get ``std_ulogic``, you have to use a ``BlackBoxULogic`` instead of ``BlackBox``."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:47
+msgid "In Verilog, ``BlackBoxUlogic`` does not change the generated verilog."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:56
+msgid "Generics"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:58
+msgid "There are two different ways to declare generics:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:75
+msgid "Instantiating a blackbox"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:77
+msgid "Instantiating a ``BlackBox`` is just like instantiating a ``Component``:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:115
+msgid "Clock and reset mapping"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:117
+msgid "In your blackbox definition you have to explicitly define clock and reset wires. To map signals of a ``ClockDomain`` to corresponding inputs of the blackbox you can use the ``mapClockDomain`` or ``mapCurrentClockDomain`` function. ``mapClockDomain`` has the following parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:123
+msgid "name"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:124
+msgid "type"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:125
+msgid "default"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:126
+msgid "description"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:127
+msgid "clockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:128
+msgid "ClockDomain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:129
+msgid "ClockDomain.current"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:130
+msgid "Specify the clockDomain which provides the signals"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:131
+msgid "clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:132
+#: ../../SpinalHDL/Structuring/blackbox.rst:136
+#: ../../SpinalHDL/Structuring/blackbox.rst:140
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:133
+#: ../../SpinalHDL/Structuring/blackbox.rst:137
+#: ../../SpinalHDL/Structuring/blackbox.rst:141
+msgid "Nothing"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:134
+msgid "Blackbox input which should be connected to the clockDomain clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:135
+msgid "reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:138
+msgid "Blackbox input which should be connected to the clockDomain reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:139
+msgid "enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:142
+msgid "Blackbox input which should be connected to the clockDomain enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:145
+msgid "``mapCurrentClockDomain`` has almost the same parameters as ``mapClockDomain`` but without the clockDomain."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:147
+msgid "For example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:167
+msgid "io prefix"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:169
+msgid "In order to avoid the prefix \"io\\_\" on each of the IOs of the blackbox, you can use the function ``noIoPrefix()`` as shown below :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:202
+msgid "Rename all io of a blackbox"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:204
+msgid "IOs of a ``BlackBox`` or ``Component`` can be renamed at compile-time using the ``addPrePopTask`` function. This function takes a no-argument function to be applied during compilation, and is useful for adding renaming passes, as shown in the following example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:251
+msgid "Add RTL source"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:253
+msgid "With the function ``addRTLPath()`` you can associate your RTL sources with the blackbox. After the generation of your SpinalHDL code you can call the function ``mergeRTLSource`` to merge all of the sources together."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:291
+msgid "VHDL - No numeric type"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:293
+msgid "If you want to use only ``std_logic_vector`` in your blackbox component, you can add the tag ``noNumericType`` to the blackbox."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:312
+msgid "The code above will generate the following VHDL:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot b/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot
new file mode 100644
index 00000000000..c65fc2eefa3
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot
@@ -0,0 +1,510 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:4
+msgid "Clock domains"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:9
+msgid "In SpinalHDL, clock and reset signals can be combined to create a **clock domain**. Clock domains can be applied to some areas of the design and then all synchronous elements instantiated into those areas will then **implicitly** use this clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:11
+msgid "Clock domain application works like a stack, which means that if you are in a given clock domain you can still apply another clock domain locally."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:13
+msgid "Please note that a register captures its clock domain when the register is created, not when it is assigned. So please make sure to create them inside the desired ``ClockingArea``."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:18
+msgid "Instantiation"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:20
+msgid "The syntax to define a clock domain is as follows (using EBNF syntax):"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:33
+msgid "This definition takes five parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:39
+#: ../../SpinalHDL/Structuring/clock_domain.rst:196
+msgid "Argument"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:40
+#: ../../SpinalHDL/Structuring/clock_domain.rst:197
+#: ../../SpinalHDL/Structuring/clock_domain.rst:338
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:41
+#: ../../SpinalHDL/Structuring/clock_domain.rst:198
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:42
+msgid "``clock``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:43
+msgid "Clock signal that defines the domain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:45
+msgid "``reset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:46
+msgid "Reset signal. If a register exists which needs a reset and the clock domain doesn't provide one, an error message will be displayed"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:47
+#: ../../SpinalHDL/Structuring/clock_domain.rst:50
+#: ../../SpinalHDL/Structuring/clock_domain.rst:53
+msgid "null"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:48
+msgid "``softReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:49
+msgid "Reset which infers an additional synchronous reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:51
+msgid "``clockEnable``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:52
+msgid "The goal of this signal is to disable the clock on the whole clock domain without having to manually implement that on each synchronous element"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:54
+#: ../../SpinalHDL/Structuring/clock_domain.rst:214
+msgid "``frequency``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:55
+msgid "Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate and PLL or other hardware to control the frequency"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:57
+#: ../../SpinalHDL/Structuring/clock_domain.rst:216
+msgid "UnknownFrequency"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:58
+#: ../../SpinalHDL/Structuring/clock_domain.rst:202
+msgid "``config``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:59
+msgid "Specify the polarity of signals and the nature of the reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:60
+#: ../../SpinalHDL/Structuring/clock_domain.rst:204
+msgid "Current config"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:63
+msgid "An applied example to define a specific clock domain within the design is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:78
+msgid "When an `Area` is not needed, it is also possible to apply the clock domain directly. Two syntaxes exist:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:105
+msgid "Configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:107
+msgid "In addition to :ref:`constructor parameters <clock_domain_instantiation>`\\ , the following elements of each clock domain are configurable via a ``ClockDomainConfig``\\ class:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:113
+msgid "Property"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:114
+msgid "Valid values"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:115
+msgid "``clockEdge``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:116
+msgid "``RISING``\\ , ``FALLING``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:117
+msgid "``resetKind``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:118
+msgid "``ASYNC``\\ , ``SYNC``\\ , and ``BOOT`` which is supported by some FPGAs (where FF values are loaded by the bitstream)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:119
+msgid "``resetActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:120
+#: ../../SpinalHDL/Structuring/clock_domain.rst:122
+#: ../../SpinalHDL/Structuring/clock_domain.rst:124
+msgid "``HIGH``\\ , ``LOW``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:121
+msgid "``softResetActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:123
+msgid "``clockEnableActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:157
+msgid "By default, a ``ClockDomain`` is applied to the whole design. The configuration of this default domain is:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:160
+msgid "Clock : rising edge"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:161
+msgid "Reset : asynchronous, active high"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:162
+msgid "No clock enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:164
+msgid "This corresponds to the following ``ClockDomainConfig``:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:175
+msgid "Internal clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:177
+msgid "An alternative syntax to create a clock domain is the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:190
+msgid "This definition takes six parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:199
+msgid "``name``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:200
+msgid "Name of `clk` and `reset` signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:203
+msgid "Specify polarity of signals and the nature of the reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:205
+msgid "``withReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:206
+msgid "Add a reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:207
+msgid "true"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:208
+msgid "``withSoftReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:209
+msgid "Add a soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:210
+#: ../../SpinalHDL/Structuring/clock_domain.rst:213
+msgid "false"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:211
+msgid "``withClockEnable``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:212
+msgid "Add a clock enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:215
+msgid "Frequency of the clock domain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:219
+msgid "The advantage of this approach is to create clock and reset signals with a known/specified name instead of an inherited one."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:221
+msgid "Once created, you have to assign the ``ClockDomain``'s signals, as shown in the example below:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:253
+msgid "In other components then the one you created the ClockDomain in, you must not use ``.clock`` and ``.reset``, but ``.readClockWire`` and ``.readResetWire`` as listed below. For the global ClockDomain you must always use those ``.readXXX`` functions."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:259
+msgid "External clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:261
+msgid "You can define a clock domain which is driven by the outside anywhere in your source. It will then automatically add clock and reset wires from the top level inputs to all synchronous elements."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:274
+msgid "The arguments to the ``ClockDomain.external`` function are exactly the same as in the ``ClockDomain.internal`` function. Below is an example of a design using ``ClockDomain.external``:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:296
+msgid "Signal priorities in HDL generation"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:298
+msgid "In the current version, reset and clock enable signals have different priorities. Their order is : ``asyncReset``, ``clockEnable``, ``syncReset`` and ``softReset``."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:300
+msgid "Please be careful that clockEnable has a higher priority than syncReset. If you do a sync reset when the clockEnable is disabled (especially at the beginning of a simulation), the gated registers will not be reseted."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:302
+msgid "Here is an example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:310
+msgid "It will generate VerilogHDL codes like:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:324
+msgid "If that behaviour is problematic, one workaround is to use a when statement as a clock enable instead of using the ClockDomain.enable feature. This is open for future improvements."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:327
+msgid "Context"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:329
+msgid "You can retrieve in which clock domain you are by calling ``ClockDomain.current`` anywhere."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:331
+msgid "The returned ``ClockDomain`` instance has the following functions that can be called:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:337
+msgid "name"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:339
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:340
+msgid "frequency.getValue"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:0
+msgid "Return the frequency of the clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:0
+msgid "This being the arbitrary value you configured the domain with."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:343
+msgid "Double"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:344
+msgid "hasReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:345
+msgid "Return if the clock domain has a reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:346
+#: ../../SpinalHDL/Structuring/clock_domain.rst:349
+#: ../../SpinalHDL/Structuring/clock_domain.rst:352
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:347
+msgid "hasSoftReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:348
+msgid "Return if the clock domain has a soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:350
+msgid "hasClockEnable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:351
+msgid "Return if the clock domain has a clock enable signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:353
+msgid "readClockWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:354
+msgid "Return a signal derived from the clock signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:355
+#: ../../SpinalHDL/Structuring/clock_domain.rst:358
+#: ../../SpinalHDL/Structuring/clock_domain.rst:361
+#: ../../SpinalHDL/Structuring/clock_domain.rst:364
+#: ../../SpinalHDL/Structuring/clock_domain.rst:367
+#: ../../SpinalHDL/Structuring/clock_domain.rst:370
+#: ../../SpinalHDL/Structuring/clock_domain.rst:373
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:356
+msgid "readResetWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:357
+msgid "Return a signal derived from the reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:359
+msgid "readSoftResetWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:360
+msgid "Return a signal derived from the soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:362
+msgid "readClockEnableWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:363
+msgid "Return a signal derived from the clock enable signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:365
+msgid "isResetActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:366
+msgid "Return True when the reset is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:368
+msgid "isSoftResetActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:369
+msgid "Return True when the soft reset is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:371
+msgid "isClockEnableActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:372
+msgid "Return True when the clock enable is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:375
+msgid "An example is included below where a UART controller uses the frequency specification to set its clock divider:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:387
+msgid "Clock domain crossing"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:389
+msgid "SpinalHDL checks at compile time that there are no unwanted/unspecified cross clock domain signal reads. If you want to read a signal that is emitted by another ``ClockDomain`` area, you should add the ``crossClockDomain`` tag to the destination signal as depicted in the following example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:451
+msgid "In general, you can use 2 or more flip-flop driven by the destination clock domain to prevent metastability. The ``BufferCC(input: T, init: T = null, bufferDepth: Int = 2)`` function provided in ``spinal.lib._`` will instantiate the necessary flip-flops (the number of flip-flops will depends on the ``bufferDepth`` parameter) to mitigate the phenomena."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:475
+msgid "The ``BufferCC`` function is only for signals of type ``Bit``, or ``Bits`` operating as Gray-coded counters (only 1 bit-flip per clock cycle), and can not used for multi-bit cross-domain processes. For multi-bit cases, it is recommended to use ``StreamFifoCC`` for high bandwidth requirements, or use ``StreamCCByToggle`` to reduce resource usage in cases where bandwidth is not critical."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:478
+msgid "Special clocking Areas"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:481
+msgid "Slow Area"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:483
+msgid "A ``SlowArea`` is used to create a new clock domain area which is slower than the current one:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:512
+msgid "The clock signal used in a SlowArea is the same as the parent one. The SlowArea add instead a clock-enable signal that will slow down the sampling rate inside it. In other words, ``ClockDomain.current.readClockWire`` will return the fast (parent domain) clock. To obtain the clock enable, use ``ClockDomain.current.readClockEnableWire``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:517
+msgid "BootReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:519
+msgid "`clockDomain.withBootReset()` could specify register's resetKind as BOOT. `clockDomain.withSyncReset()` could specify register's resetKind as SYNC (sync-reset)."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:537
+msgid "ResetArea"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:539
+msgid "A ``ResetArea`` is used to create a new clock domain area where a special reset signal is combined with the current clock domain reset:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:559
+msgid "ClockEnableArea"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:561
+msgid "A ``ClockEnableArea`` is used to add an additional clock enable in the current clock domain:"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot b/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot
new file mode 100644
index 00000000000..eda685d7c48
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot
@@ -0,0 +1,194 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:4
+msgid "Components and hierarchy"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:6
+msgid "Like in VHDL and Verilog, you can define components that can be used to build a design hierarchy. However, in SpinalHDL, you don't need to bind their ports at instantiation:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``val io = new Bundle { ... }``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "Declaring external ports in a ``Bundle`` called ``io`` is recommended. If you name your bundle ``io``, SpinalHDL will check that all of its elements are defined as inputs or outputs."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:41
+msgid "If it is better to your taste, you can use the ``Module`` syntax instead of ``Component`` (they are the same thing)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:47
+msgid "Input / output definition"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:49
+msgid "The syntax to define inputs and outputs is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:55
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:56
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:57
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``in port Bool()``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``out port Bool()``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:60
+msgid "Create an input Bool/output Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:61
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``in Bits/UInt/SInt[(x bits)]``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``out Bits/UInt/SInt[(x bits)]``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``in Bits(3 bits)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:65
+msgid "Create an input/output of the corresponding type"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:66
+msgid "Bits/UInt/SInt"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``in(T)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``out(T)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``out UInt(7 bits)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:70
+msgid "For all other data types, you may have to add some brackets around it. Sorry, this is a Scala limitation."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:71
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:77
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``master(T)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``slave(T)``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:0
+msgid "``master(Bool())``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:75
+msgid "This syntax is provided by the ``spinal.lib`` library (If you annotate your object with the ``slave`` syntax, then import ``spinal.lib.slave`` instead). T must extend ``IMasterSlave``. Some documentation is available :ref:`here <interface_example_apb>`. You may not actually need the brackets, so ``master T`` is fine as well."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:80
+msgid "There are some rules to follow with component interconnection:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:83
+msgid "Components can only **read** output and input signals of child components."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:84
+msgid "Components can read their own output port values (unlike in VHDL)."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:87
+msgid "If for some reason you need to read signals from far away in the hierarchy (such as for debugging or temporal patches), you can do it by using the value returned by ``some.where.else.theSignal.pull()``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:91
+msgid "Pruned signals"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:93
+msgid "SpinalHDL will generate all the named signals and their depedencies, while all the useless anonymous / zero width ones are removed from the RTL generation."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:96
+msgid "You can collect the list of all the removed ans useless signals via the ``printPruned`` and the ``printPrunedIo`` functions on the generated ``SpinalReport`` object:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:126
+msgid "Parametrized Hardware (\"Generic\" in VHDL, \"Parameter\" in Verilog)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:128
+msgid "If you want to parameterize your component, you can give parameters to the constructor of the component as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:146
+msgid "If you have several parameters, it is a good practice to give a specific configuration class as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:159
+msgid "You can add functions inside the config, along with requirements on the config attributes:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:173
+msgid "This parametrization occurs entirely within the SpinalHDL code-generation during elaboration.  This generates non-generic HDL code. The methods described here do not use VHDL generics or Verilog parameters."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:177
+msgid "See also :ref:`Blackbox <blackbox>` for more information around support for that mechanism."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:182
+msgid "Synthesized component names"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:184
+msgid "Within a module, each component has a name, called a \"partial name\". The \"full\" name is built by joining every component's parent name with \"_\", for example: ``io_clockDomain_reset``. You can use ``setName`` to replace this convention with a custom name. This is especially useful when interfacing with external components. The other methods are called ``getName``, ``setPartialName``, and ``getPartialName`` respectively."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:190
+msgid "When synthesized, each module gets the name of the Scala class defining it. You can override this as well with ``setDefinitionName``."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/function.pot b/source/locale/gettext/SpinalHDL/Structuring/function.pot
new file mode 100644
index 00000000000..aa6a958e12c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/function.pot
@@ -0,0 +1,57 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/function.rst:4
+msgid "Function"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:6
+msgid "The ways you can use Scala functions to generate hardware are radically different than VHDL/Verilog for many reasons:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:8
+msgid "You can instantiate registers, combinational logic, and components inside them."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:9
+msgid "You don't have to play with ``process``\\ /\\ ``@always`` blocks that limit the scope of assignment of signals."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:0
+msgid "Everything is passed by reference, which allows easy manipulation."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:0
+msgid "For example, you can give a bus to a function as an argument, then the function can internally read/write to it. You can also return a Component, a Bus, or anything else from Scala and the Scala world."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:14
+msgid "RGB to gray"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:16
+msgid "For example, if you want to convert a Red/Green/Blue color into greyscale by using coefficients, you can use functions to apply them:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:30
+msgid "Valid Ready Payload bus"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/function.rst:32
+msgid "For instance, if you define a simple bus with ``valid``, ``ready``, and ``payload`` signals, you can then define some useful functions inside of it."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/index.pot b/source/locale/gettext/SpinalHDL/Structuring/index.pot
new file mode 100644
index 00000000000..48a005da9e8
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/index.pot
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/index.rst:3
+msgid "Structuring"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:5
+msgid "The chapters below explain:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:7
+msgid "how to build reusable components"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:8
+msgid "alternatives to components to group hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:9
+msgid "handling of clock/reset domains"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:10
+msgid "instantitation of existing VHDL and Verilog IP"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/index.rst:11
+msgid "how names are assigned in SpinalHDL, and how naming can be influenced"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/naming.pot b/source/locale/gettext/SpinalHDL/Structuring/naming.pot
new file mode 100644
index 00000000000..0e812a74261
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/naming.pot
@@ -0,0 +1,208 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/naming.rst:2
+msgid "Preserving names"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:4
+msgid "This page will describe how SpinalHDL propagate names from the scala code to the generated hardware. Knowing them should enable you to preserve those names as much as possible to generate understandable netlists."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:7
+msgid "Nameable base class"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:9
+msgid "All the things which can be named in SpinalHDL extends the Nameable base class which."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:11
+msgid "So in practice, the following classes extends Nameable :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:13
+msgid "Component"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:14
+msgid "Area"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:15
+msgid "Data (UInt, SInt, Bundle, ...)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:18
+msgid "There is a few example of that Nameable API"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:29
+msgid "Will generation :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:41
+msgid "In general, you don't realy need to access that API, unless you want to do tricky stuff for debug reasons or for elaboration purposes."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:44
+msgid "Name extraction from Scala"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:46
+msgid "First, since version 1.4.0, SpinalHDL use a scala compiler plugin which can provide a call back each time a new val is defined during the construction of an class."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:48
+msgid "There is a example showing more or less how SpinalHDL itself is implemented :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:78
+msgid "Using that ValCallback \"introspection\" feature, SpinalHDL's Component classes are able to be aware of their content and the content's name."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:80
+msgid "But this also mean that if you want something to get a name, and you only rely on this automatic naming feature, the reference to your Data (UInt, SInt, ...) instances should be stored somewhere in a Component val."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:82
+msgid "For instance :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:99
+#: ../../SpinalHDL/Structuring/naming.rst:197
+#: ../../SpinalHDL/Structuring/naming.rst:234
+msgid "Will generate :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:115
+msgid "Area in a Component"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:117
+msgid "One important aspect in the naming system is that you can define new namespaces inside components and manipulate"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:119
+msgid "For instance via Area :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:130
+#: ../../SpinalHDL/Structuring/naming.rst:298
+#: ../../SpinalHDL/Structuring/naming.rst:383
+#: ../../SpinalHDL/Structuring/naming.rst:418
+#: ../../SpinalHDL/Structuring/naming.rst:467
+#: ../../SpinalHDL/Structuring/naming.rst:521
+msgid "Will generate"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:145
+msgid "Area in a function"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:147
+msgid "You can also define function which will create new Area which will provide a namespace for all its content :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:163
+msgid "Which will generate :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:179
+msgid "Composite in a function"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:181
+msgid "Added in SpinalHDL 1.5.0, Composite which allow you to create a scope which will use as prefix another Nameable:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:213
+msgid "Composite chains"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:215
+msgid "You can also chain composites :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:252
+msgid "Composite in a Bundle's function"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:255
+msgid "This behaviour can be very useful when implementing Bundle utilities. For instance in the spinal.lib.Stream class is defined the following :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:288
+msgid "Which allow nested calls while preserving the names :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:363
+msgid "Unamed signal handling"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:365
+msgid "Since 1.5.0, for signal which end up without name, SpinalHDL will find a signal which is driven by that unamed signal and propagate its name. This can produce useful results as long you don't have too large island of unamed stuff."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:367
+msgid "The name attributed to such unamed signal is : _zz_ + drivenSignal.getName()"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:369
+msgid "Note that this naming pattern is also used by the generation backend when they need to breakup some specific expressions or long chain of expression into multiple signals."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:372
+msgid "Verilog expression splitting"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:374
+msgid "There is an instance of expressions (ex : the + operator) that SpinalHDL need to express in dedicated signals to match the behaviour with the Scala API :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:404
+msgid "Verilog long expression splitting"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:406
+msgid "There is a instance of how a very long expression chain will be splited up by SpinalHDL :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:448
+msgid "When statement condition"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:450
+msgid "The `when(cond) { }` statements condition are generated into separated signals named `when_` + fileName + line. A similar thing will also be done for switch statements."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:500
+msgid "In last resort"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:502
+msgid "In last resort, if a signal has no name (anonymous signal), SpinalHDL will seek for a named signal which is driven by the anonymous signal, and use it as a name postfix :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:542
+msgid "This last resort naming skim isn't ideal in all cases, but can help out."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/naming.rst:544
+msgid "Note that signal starting with a underscore aren't stored in the Verilator waves (on purpose)"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot b/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot
new file mode 100644
index 00000000000..c4b000becc2
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot
@@ -0,0 +1,161 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:2
+msgid "Parametrization"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:4
+msgid "There are multiple aspects to parametrization :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:6
+msgid "Providing and the management of, elaboration time parameters provided to SpinalHDL during elaboration of the design"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:8
+msgid "Using the parameter data to allow the designer to perform any kind of hardware construction, configuration and interconnection task needed in the design.  Such as optional component generation within the hardware design."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:13
+msgid "Parallels exist with the aims of HDL features such as Verilog module parameters and VHDL generics.  SpinalHDL brings a far richer and more powerful set of capabilities into this area with the additional protection of Scala type safety and SpinalHDL built in HDL design rule checking."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:19
+msgid "The SpinalHDL mechanisms for parameterization of components is not built on top of any native HDL mechanism and so is not impeded by HDL language level/version support or restrictions about what can be achieved in hand written HDL."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:24
+msgid "For readers looking to interoperate with parameterized Verilog or genericized VHDL using SpinalHDL, please see the section on :ref:`BlackBox <BlackBox>` IP for those scenarios your project requires."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:31
+msgid "Elaboration time parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:33
+msgid "You can use the whole Scala syntax to provide elaboration time parameters."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:35
+msgid "The whole syntax means you have the entire power and feature set of the Scala language at your disposal to solve parameterization requirements for your project at the level of complexity you choose."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:39
+msgid "SpinalHDL does not place any opinionated restrictions on how to achieve your parameterization goals.  As such there are many Scala design patterns and a few SpinalHDL helpers that can be used to manage parameters that are suited to different parameter management scenarios."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:44
+msgid "Here are some examples and ideas of the possibilities:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:46
+msgid "Hardwired code and constants (not strictly parameter management at all but serves to hilight the most basic mechanism, a code change, not a parameter data change)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:49
+msgid "Constant values provided from a companion object that are static constants in Scala."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:51
+msgid "Values provided to Scala class constructor, often a ``case class`` that causes Scala to capture those constructor argument values as constants."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:53
+msgid "Regular Scala flow-control syntax, not limited to but including conditionals, looping, lambdas/monads, everything."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:55
+msgid "Config class pattern (examples exist in library items such as UartCtrlConfig_, SpiMasterCtrlConfig)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:57
+msgid "Project defined 'Plugin' pattern (examples exist in the VexRiscV_ project to configure the feature set the resulting CPU IP core is built with)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:59
+msgid "Values and information loaded from a file or network based source, using standard Scala/JVM libraries and APIs."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:61
+msgid "`any mechanism you can create`"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:63
+msgid "All of the mechanisms result in a change in resulting elaborated HDL output."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:65
+msgid "This could vary from a single constant value change all the way through to describing the entire bus and interconnection architecture of an entire SoC all without leaving the Scala programming paradigm."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:70
+msgid "Here is an example of class parameters"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:84
+msgid "You can also use global variable defined in Scala objects (companion object pattern)."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:87
+msgid "A :ref:`ScopeProperty <scopeproperty>` can also be used for configuration."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:90
+msgid "Optional hardware"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:92
+msgid "So here there is more possibilities."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:96
+msgid "For optional signal :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:106
+msgid "The ``generate`` method is a mechanism to evaluate the expression that follows for an optional value.  If the predicate is true, generate will evaluate the given expression and return the result, otherwise it returns null."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:111
+msgid "This may be used in cases to help parameterize the SpinalHDL hardware description using an elaboration-time conditional expression.  Causing HDL constructs to be emitted or not-emitted in the resulting HDL. The generate method can be seen as SpinalHDL syntatic sugar reducing language clutter."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:116
+msgid "Project SpinalHDL code referencing ``mySignal`` would need to ensure it handles the possiblity of null gracefully.  This is usually not a problem as those parts of the design can also be omitted dependant on the ``flag`` value.  Thus the feature of parameterizing this component is demonstrated."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:122
+msgid "You can do the same in Bundle."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:124
+msgid "Note that you can also use scala Option."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:126
+msgid "If you want to disable the generation of a chunk of hardware :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:136
+msgid "You can also use scala for loops :"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:146
+msgid "So, you can extends those scala usages at elaboration time as much as you want, including using the whole scala collections (List, Set, Map, ...) to build some data model and then converting them into hardware in a procedural way (ex iterating over those list elements)."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/miscelenea/chisel.pot b/source/locale/gettext/SpinalHDL/miscelenea/chisel.pot
new file mode 100644
index 00000000000..2bd97ac2a86
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/miscelenea/chisel.pot
@@ -0,0 +1,17 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
diff --git a/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot b/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot
new file mode 100644
index 00000000000..101348356ab
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot
@@ -0,0 +1,490 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:8
+msgid "The ``spinal.core`` components"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:9
+msgid "The core components of the language are described in this document. It is part of the general"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:13
+msgid "The core language components are as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:15
+msgid ":ref:`*Clock domains* <core_components_clock_domain_definition>`, which allow to define and interoperate multiple clock domains within a design"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:16
+msgid "*Memory instantiation*\\ , which permit the automatic instantiation of RAM and ROM memories."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:17
+msgid "*IP instantiation*\\ , using either existing VHDL or Verilog component."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:18
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:160
+msgid "Assignments"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:19
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:229
+msgid "When / Switch"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:20
+msgid "Component hierarchy"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:21
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:328
+msgid "Area"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:22
+msgid "Functions"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:23
+msgid "Utility functions"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:24
+msgid "VHDL generator"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:29
+msgid "Clock domains definitions"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:31
+msgid "In *Spinal*\\ , clock and reset signals can be combined to create a **clock domain**. Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then **implicitly** use this clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:33
+msgid "Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:39
+msgid "Clock domain syntax"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:41
+msgid "The syntax to define a clock domain is as follows (using EBNF syntax):"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:43
+msgid "``ClockDomain(clock : Bool[,reset : Bool[,enable : Bool]]])``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:45
+msgid "This definition takes three parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:48
+msgid "The clock signal that defines the domain"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:49
+msgid "An optional ``reset``\\ signal. If a register which need a reset and his clock domain didn't provide one, an error message happen"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:50
+msgid "An optional ``enable`` signal. The goal of this signal is to disable the clock on the whole clock domain without having to  manually implement that on each synchronous element."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:52
+msgid "An applied example to define a specific clock domain within the design is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:70
+msgid "Clock configuration"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:72
+msgid "In addition to the constructor parameters given :ref:`here <core_componets_clock_constructor>` , the following elements of each clock domain are configurable via a ``ClockDomainConfig`` class :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:78
+msgid "Property"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:79
+msgid "Valid values"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:80
+msgid "``clockEdge``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:81
+msgid "``RISING``\\ , ``FALLING``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:82
+msgid "``ResetKind``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:83
+msgid "``ASYNC``\\ , ``SYNC``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:84
+msgid "``resetActiveHigh``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:85
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:87
+msgid "``true``\\ , ``false``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:86
+msgid "``clockEnableActiveHigh``"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:112
+msgid "By default, a ClockDomain is applied to the whole design. The configuration of this one is :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:115
+msgid "clock : rising edge"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:116
+msgid "reset: asynchronous, active high"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:117
+msgid "no enable signal"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:120
+msgid "External clock"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:122
+msgid "You can define everywhere a clock domain which is driven by the outside. It will then automatically add clock and reset wire from the top level inputs to all synchronous elements."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:140
+msgid "Cross Clock Domain"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:142
+msgid "SpinalHDL checks at compile time that there is no unwanted/unspecified cross clock domain signal reads. If you want to read a signal that is emitted by another ``ClockDomain`` area, you should add the ``crossClockDomain`` tag to the destination signal as depicted in the following example:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:162
+msgid "There are multiple assignment operator :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:168
+msgid "Symbole"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:169
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:204
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:307
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:488
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:170
+msgid ":="
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "Standard assignment, equivalent to '<=' in VHDL/Verilog"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "last assignment win, value updated at next delta cycle"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:173
+msgid "/="
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "Equivalent to := in VHDL and = in Verilog"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "value updated instantly"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:176
+msgid "<>"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "Automatic connection between 2 signals. Direction is inferred by using signal direction (in/out)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "Similar behavioural than :="
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:197
+msgid "SpinalHDL check that bitcount of left and right assignment side match. There is multiple ways to adapt bitcount of BitVector (Bits, UInt, SInt) :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:203
+msgid "Resizing ways"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:205
+msgid "x := y.resized"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:206
+msgid "Assign x wit a resized copy of y, resize value is automatically inferred to match x"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:207
+msgid "x := y.resize(newWidth)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:208
+msgid "Assign x with a resized copy of y, size is manually calculated"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:211
+msgid "There are 2 cases where spinal automaticly resize things :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:217
+msgid "Assignement"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:218
+msgid "Problem"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:219
+msgid "SpinalHDL action"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:220
+msgid "myUIntOf_8bit := U(3)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:221
+msgid "U(3) create an UInt of 2 bits, which don't match with left side"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:222
+msgid "Because  U(3) is a \"weak\" bit inferred signal, SpinalHDL resize it automatically"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:223
+msgid "myUIntOf_8bit := U(2 -> False default -> true)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:224
+msgid "The right part infer a 3 bit UInt, which doesn't match with the left part"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:225
+msgid "SpinalHDL reapply the default value to bit that are missing"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:231
+msgid "As VHDL and Verilog, wire and register can be conditionally assigned by using when and switch syntaxes"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:255
+msgid "You can also define new signals into a when/switch statement. It's useful if you want to calculate an intermediate value."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:272
+msgid "Component/Hierarchy"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:274
+msgid "Like in VHDL and Verilog, you can define components that could be used to build a design hierarchy.  But unlike them, you don't need to bind them at instantiation."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:300
+msgid "Syntax to define in/out is the following :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:306
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:487
+msgid "Syntax"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:308
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:489
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:309
+msgid "in/out(x : Data)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:310
+msgid "Set x an input/output"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:311
+msgid "x"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:312
+msgid "in/out Bool()"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:313
+msgid "Create an input/output Bool"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:314
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:315
+msgid "in/out Bits/UInt/SInt(x bits)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:316
+msgid "Create an input/output of the corresponding type"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:317
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:320
+msgid "There is some rules about component interconnection :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:323
+msgid "Components can only read outputs/inputs signals of children components"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:324
+msgid "Components can read outputs/inputs ports values"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:325
+msgid "If for some reason, you need to read a signals from far away in the hierarchy (debug, temporal patch) you can do it by using the value returned by some.where.else.theSignal.pull()."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:330
+msgid "Sometime, creating a component to define some logic is overkill and to much verbose. For this kind of cases you can use Area :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:360
+msgid "Function"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:362
+msgid "The ways you can use Scala functions to generate hardware are radically different than VHDL/Verilog for many reasons:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:365
+msgid "You can instantiate register, combinatorial logic and component inside them."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:366
+msgid "You don't have to play with ``process``\\ /\\ ``@always`` that limit the scope of assignment of signals"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "Everything work by reference, which allow many manipulation."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "For example you can give to a function an bus as argument, then the function can internaly read/write it."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:0
+msgid "You can also return a Component, a Bus, are anything else from scala the scala world."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:372
+msgid "RGB to gray"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:374
+msgid "For example if you want to convert a Red/Green/Blue color into a gray one by using coefficient, you can use functions to apply them :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:390
+msgid "Valid Ready Payload bus"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:392
+msgid "For instance if you define a simple Valid Ready Payload bus, you can then define useful function inside it."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:417
+msgid "VHDL generation"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:419
+msgid "There is a small component and a ``main`` that generate the corresponding VHDL."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:448
+msgid "Instantiate VHDL and Verilog IP"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:450
+msgid "In some cases, it could be useful to instantiate a VHDL or a Verilog component into a SpinalHDL design. To do that, you need to define BlackBox which is like a Component, but its internal implementation should be provided by a separate VHDL/Verilog file to the simulator/synthesis tool."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:479
+msgid "Utils"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:481
+msgid "The SpinalHDL core contain some utils :"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:490
+msgid "log2Up(x : BigInt)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:491
+msgid "Return the number of bit needed to represent x states"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:492
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:493
+msgid "isPow2(x : BigInt)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:494
+msgid "Return true if x is a power of two"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:495
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:498
+msgid "Much more tool and utils are present in spinal.lib"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/miscelenea/core/elements.pot b/source/locale/gettext/SpinalHDL/miscelenea/core/elements.pot
new file mode 100644
index 00000000000..b06ff523985
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/miscelenea/core/elements.pot
@@ -0,0 +1,131 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:9
+msgid "Element"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:11
+msgid "Elements could be defined as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:17
+msgid "Element syntax"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:18
+#: ../../SpinalHDL/miscelenea/core/elements.rst:44
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:19
+msgid "x : Int -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:20
+msgid "Set bit x with y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:21
+msgid "x : Range -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:22
+msgid "Set each bits in range x with y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:23
+msgid "x : Range -> y : T"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:0
+#: ../../SpinalHDL/miscelenea/core/elements.rst:24
+msgid "Set bits in range x with y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:25
+msgid "x : Range -> y : String"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:0
+msgid "The string format follow same rules than B\"xyz\" one"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:28
+msgid "default -> y : Boolean/Bool"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:0
+msgid "Set all unconnected bits with the y value."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:0
+msgid "This feature could only be use to do assignments without the B prefix or with the B prefix combined with the bits specification"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:35
+msgid "Range"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:37
+msgid "You can define a Range values"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:43
+msgid "Range syntax"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:45
+msgid "Width"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:46
+msgid "(x downto y)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:47
+msgid "[x:y], x >= y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:48
+msgid "x-y+1"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:49
+msgid "(x to y)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:50
+msgid "[x:y], x <= y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:51
+msgid "y-x+1"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:52
+msgid "(x until y)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:53
+msgid "[x:y[, x < y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/core/elements.rst:54
+msgid "y-x"
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot b/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot
new file mode 100644
index 00000000000..207963dd32c
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot
@@ -0,0 +1,86 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:7
+msgid "Frequent Errors"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:9
+msgid "This page will talk about errors which could happen when people are using SpinalHDL."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:12
+msgid "Exception in thread \"main\" java.lang.NullPointerException"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:14
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:39
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:87
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:114
+msgid "**Console symptoms :**"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:20
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:45
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:93
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:120
+msgid "**Code Example :**"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:27
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:80
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:107
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:139
+msgid "**Issue explanation :**"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:29
+msgid "SpinalHDL is not a language, it is an Scala library, which mean, it obey to the same rules than the Scala general purpose programming language. When you run your SpinalHDL hardware description to generate the corresponding VHDL/Verilog RTL, your SpinalHDL hardware description will be executed as a Scala programm, and b will be a ``null`` reference until the programm execution come to that line, and it's why you can't use it before."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:32
+msgid "Hierarchy violation"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:34
+msgid "The SpinalHDL compiler check that all your assignments are legal from an hierarchy perspective. Multiple cases are elaborated in following chapters"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:37
+msgid "Signal X can't be assigned by Y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:82
+msgid "You can only assign input signals of subcomponents, else there is an hierarchy violation. If this issue happend, you probably forgot to specify the X signal's direction."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:85
+msgid "Input signal X can't be assigned by Y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:109
+msgid "You can only assign an input signals from the parent component, else there is an hierarchy violation. If this issue happend, you probably mixed signals direction declaration."
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:112
+msgid "Output signal X can't be assigned by Y"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:141
+msgid "You can only assign output signals of a component from the inside of it, else there is an hierarchy violation. If this issue happend, you probably mixed signals direction declaration."
+msgstr ""
diff --git a/source/locale/gettext/SpinalHDL/miscelenea/index.pot b/source/locale/gettext/SpinalHDL/miscelenea/index.pot
new file mode 100644
index 00000000000..bd4418aeccc
--- /dev/null
+++ b/source/locale/gettext/SpinalHDL/miscelenea/index.pot
@@ -0,0 +1,45 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/miscelenea/index.rst:3
+msgid "Miscellaneous"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:5
+msgid "This section includes content that may be:"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:7
+msgid "out-of-date"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:8
+msgid "could be better curated"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:9
+msgid "may contain duplicate information (better found elsewhere here or in another repo)"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:10
+msgid "drafts of documentation and works in progress"
+msgstr ""
+
+#: ../../SpinalHDL/miscelenea/index.rst:12
+msgid "So please consider the information in this section with caution and a best effort on the author to provide documentation."
+msgstr ""
diff --git a/source/locale/gettext/index.pot b/source/locale/gettext/index.pot
new file mode 100644
index 00000000000..a9da4a56a9b
--- /dev/null
+++ b/source/locale/gettext/index.pot
@@ -0,0 +1,69 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL \n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../index.rst:2
+msgid "Spinal Hardware Description Language"
+msgstr ""
+
+#: ../../index.rst:4
+msgid "Welcome to SpinalHDL's documentation!"
+msgstr ""
+
+#: ../../index.rst:6
+msgid "SpinalHDL is an open source high-level hardware description language. It can be used as an alternative to VHDL or Verilog and has several advantages over them:"
+msgstr ""
+
+#: ../../index.rst:9
+msgid "It focuses on efficient hardware description instead of being event-driven."
+msgstr ""
+
+#: ../../index.rst:10
+msgid "It is embedded into a general purpose programming language, enabling powerful hardware generation."
+msgstr ""
+
+#: ../../index.rst:13
+msgid "More detailed introduction of the language in :ref:`Introduction/SpinalHDL`"
+msgstr ""
+
+#: ../../index.rst:15
+msgid "HTML and PDF formats of this documentation are available online:"
+msgstr ""
+
+#: ../../index.rst:16
+msgid "> `spinalhdl.github.io/SpinalDoc-RTD <https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html>`_"
+msgstr ""
+
+#: ../../index.rst:17
+msgid "(PDF format is accessible from the lower left corner, click ``v:master`` then PDF)"
+msgstr ""
+
+#: ../../index.rst:18
+msgid "Chinese version of documentation:"
+msgstr ""
+
+#: ../../index.rst:19
+msgid "> `github.com/thuCGRA/SpinalHDL_Chinese_Doc <https://github.com/thuCGRA/SpinalHDL_Chinese_Doc>`_"
+msgstr ""
+
+#: ../../index.rst:20
+msgid "You can also find the API documentation:"
+msgstr ""
+
+#: ../../index.rst:21
+msgid "> `spinalhdl.github.io/SpinalHDL <https://spinalhdl.github.io/SpinalHDL/dev/spinal/index.html>`_"
+msgstr ""
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po
new file mode 100644
index 00000000000..73c7f210e09
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po	
@@ -0,0 +1,270 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-27 15:40+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesafix/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Data types/AFix.rst:5
+msgid "AFix"
+msgstr "AFix"
+
+#: ../../SpinalHDL/Data types/AFix.rst:8
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/AFix.rst:10
+msgid ""
+"Auto-ranging Fixed-Point, ``AFix``, is a fixed-point class which tracks the "
+"representable range of values while preforming fixed-point operations."
+msgstr "``AFix`` 是一个支持自动范围的定点类型，它在执行定点运算时跟踪可表示值的范围。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:12
+msgid ""
+"**Warning: Much of this code is still under development. API and function "
+"calls may change.**"
+msgstr "**警告：此代码的大部分仍在开发中。 API 和函数原型可能会发生变化。**"
+
+#: ../../SpinalHDL/Data types/AFix.rst:14
+msgid "User feedback is appreciated!"
+msgstr "感谢用户反馈！"
+
+#: ../../SpinalHDL/Data types/AFix.rst:18
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/AFix.rst:20
+msgid "AFix can be created using bit sizes or exponents:"
+msgstr "AFix 可以在创建时指定总位宽或指数部分位宽："
+
+#: ../../SpinalHDL/Data types/AFix.rst:36
+msgid "These will have representable ranges for all bits."
+msgstr "这些将占据所有位的可表示范围。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:38
+msgid "For example:"
+msgstr "例如："
+
+#: ../../SpinalHDL/Data types/AFix.rst:40
+msgid "``AFix.U(12 bits)`` will have a range of 0 to 4095."
+msgstr "``AFix.U(12 bits)`` 可表示的范围是 0 to 4095。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:42
+msgid ""
+"``AFix.SQ(8 bits, 4 bits)`` will have a range of -4096 (-256) to 4095 "
+"(255.9375)"
+msgstr "``AFix.SQ(8 bits, 4 bits)`` 的范围为 -4096 (-256) 到 4095 (255.9375)"
+
+#: ../../SpinalHDL/Data types/AFix.rst:44
+msgid "``AFix.U(8 exp, 4 exp)`` will have a range of 0 to 256"
+msgstr "``AFix.U(8 exp, 4 exp)`` 的范围为 0 到 256"
+
+#: ../../SpinalHDL/Data types/AFix.rst:47
+msgid ""
+"Custom range ``AFix`` values can be created be directly instantiating the "
+"class."
+msgstr "可以通过直接实例化类来创建自定义范围 ``AFix`` 值。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:58
+msgid ""
+"The ``maxValue`` and ``minValue`` stores what backing integer values are "
+"representable. These values represent the true fixed-point value after "
+"multiplying by ``2^exp``."
+msgstr ""
+"在定点数表示法中， ``maxValue`` 和 ``minValue`` "
+"变量用于存储可表示的最大和最小整数值。这些数值是在进行 "
+"``2^exp``（即2的exp次方）的乘法运算后得到的定点数的实际值。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:61
+msgid ""
+"``AFix.U(2 exp, -1 exp)`` can represent: ``0, 0.5, 1.0, 1.5, 2, 2.5, 3, "
+"3.5``"
+msgstr "``AFix.U(2 exp, -1 exp)`` 可以表示：``0, 0.5, 1.0, 1.5, 2, 2.5, 3, 3.5``"
+
+#: ../../SpinalHDL/Data types/AFix.rst:64
+msgid ""
+"``AFix.S(2 exp, -2 exp)`` can represent: ``-2.0, -1.75, -1.5, -1.25, -1, "
+"-0.75, -0.5, -0.25, 0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75``"
+msgstr ""
+"``AFix.S(2 exp, -2 exp)`` 可以表示：``-2.0, -1.75, -1.5, -1.25, -1, -0.75, -"
+"0.5, -0.25, 0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75``"
+
+#: ../../SpinalHDL/Data types/AFix.rst:67
+msgid ""
+"Exponent values greater 0 are allowed and represent values which are larger "
+"than 1."
+msgstr "指数值大于 0 是允许的，用来表示该数值大于 1 。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:69
+msgid "``AFix.S(2 exp, 1 exp)`` can represent: ``-4, 2, 0, 2``"
+msgstr "``AFix.S(2 exp, 1 exp)`` 可以表示：``-4, 2, 0, 2``"
+
+#: ../../SpinalHDL/Data types/AFix.rst:72
+msgid ""
+"``AFix(8, 16, 2 exp)`` can represent: ``32, 36, 40, 44, 48, 52, 56, 60, 64``"
+msgstr "``AFix(8, 16, 2 exp)`` 可以表示：``32, 36, 40, 44, 48, 52, 56, 60, 64``"
+
+#: ../../SpinalHDL/Data types/AFix.rst:75
+msgid ""
+"Note: ``AFix`` will use 5 bits to save this type as that can store ``16``, "
+"its ``maxValue``."
+msgstr "注意：``AFix`` 将使用 5 位来保存此类型，因此它可以存储 ``16``，即它的 "
+"``maxValue``。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:79
+msgid "Mathematical Operations"
+msgstr "数学运算"
+
+#: ../../SpinalHDL/Data types/AFix.rst:81
+msgid ""
+"``AFix`` supports Addition (``+``), Subtraction (``-``), and Multiplication "
+"(``*``) at the hardware level. Division (``\\``) and Modulo (``%``) "
+"operators are provided but are not recommended for hardware elaboration."
+msgstr ""
+"``AFix`` 在硬件级别支持加法 (``+``)、减法 (``-``) 和乘法 "
+"(``*``)。也提供了除法（``\\``）和模（``%``）运算符，但这些不建议用硬件实现。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:85
+msgid ""
+"Operations are preformed as if the ``AFix`` value is a regular ``Int`` "
+"number. Signed and unsigned numbers are interoperable. There are no type "
+"differences between signed or unsigned values."
+msgstr "对 ``AFix`` 执行运算就像常规 ``Int`` 整型数一样。有符号数和无符号数是可以互操"
+"作的。有符号值和无符号值之间没有类型差异。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:103
+msgid ""
+"``AFix`` supports operations without without range expansion. It does this "
+"by selecting the aligned maximum and minimum ranges from each of the inputs."
+msgstr "``AFix`` 支持无范围扩展的操作。它通过从每个输入中选择对齐的最大和最小范围来实"
+"现此目的。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:106
+msgid "``+|`` Add without expansion. ``-|`` Subtract without expansion."
+msgstr "``+|`` 和 ``-|`` "
+"分别代表加法和减法操作，这两种操作在执行时不会对数值进行扩展。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:111
+msgid "Inequality Operations"
+msgstr "不等式运算"
+
+#: ../../SpinalHDL/Data types/AFix.rst:113
+msgid "``AFix`` supports standard inequality operations."
+msgstr "``AFix`` 支持标准的不等式运算。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:124
+msgid ""
+"Warning: Operations which are out of range at compile time will be optimized"
+" out!"
+msgstr "警告：编译时超出范围的操作将被优化掉！"
+
+#: ../../SpinalHDL/Data types/AFix.rst:128
+msgid "Bitshifting"
+msgstr "位移操作"
+
+#: ../../SpinalHDL/Data types/AFix.rst:130
+msgid "``AFix`` supports decimal and bit shifting"
+msgstr "``AFix`` 支持十进制和位移操作"
+
+#: ../../SpinalHDL/Data types/AFix.rst:132
+msgid ""
+"``<<`` Shifts the decimal to the left. Adds to the exponent. ``>>`` Shifts "
+"the decimal to the right. Subtracts from the exponent. ``<<|`` Shifts the "
+"bits to the left. Adds fractional zeros. ``>>|`` Shifts the bits to the "
+"right. Removes fractional bits."
+msgstr ""
+"``<<`` 将十进制小数点向左移动，即增加指数值。 ``>>`` "
+"将十进制小数点向右移动，即减小指数值。 ``<<|`` 将位左移。给小数位追加零。 "
+"``>>|`` 将位向右移动。删除小数位。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:139
+msgid "Saturation and Rounding"
+msgstr "饱和与舍入"
+
+#: ../../SpinalHDL/Data types/AFix.rst:141
+msgid "``AFix`` implements saturation and all common rounding methods."
+msgstr "``AFix`` 实现饱和和所有常见的舍入方法。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:143
+msgid ""
+"Saturation works by saturating the backing value range of an ``AFix`` value."
+" There are multiple helper functions which consider the exponent."
+msgstr "饱和的工作原理是使 ``AFix`` "
+"值的支持值范围饱和。有多个考虑到了指数特性的辅助函数。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:153
+msgid "``AFix`` rounding modes:"
+msgstr "``AFix`` 舍入模式:"
+
+#: ../../SpinalHDL/Data types/AFix.rst:170
+msgid ""
+"A mathematical example of these rounding modes is better explained here: "
+"`Rounding - Wikipedia <https://en.wikipedia.org/wiki/Rounding>`_"
+msgstr ""
+"这些舍入模式的数学示例在这里得到了更好的解释：`Rounding - Wikipedia "
+"<https://en.wikipedia.org/wiki/Rounding>`_"
+
+#: ../../SpinalHDL/Data types/AFix.rst:172
+msgid ""
+"All of these modes will result in an ``AFix`` value with 0 exponent. If "
+"rounding to a different exponent is required consider shifting or use an "
+"assignment with the ``truncated`` tag."
+msgstr ""
+"所有这些模式都会产生指数为 0 的 ``AFix`` 值。如果需要舍入到不同的指数，"
+"请考虑移位或使用带有 ``truncated`` 标签的赋值。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:177
+msgid "Assignment"
+msgstr "赋值"
+
+#: ../../SpinalHDL/Data types/AFix.rst:179
+msgid ""
+"``AFix`` will automatically check and expand range and precision during "
+"assignment. By default, it is an error to assign an ``AFix`` value to "
+"another ``AFix`` value with smaller range or precision."
+msgstr ""
+"``AFix`` 会在赋值时自动检查并扩大范围和精度。默认情况下，将一个 ``AFix`` "
+"值赋值给另一个范围或精度更小的 ``AFix`` 值是错误的。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:182
+msgid ""
+"The ``.truncated`` function is used to control how assignments to smaller "
+"types."
+msgstr "``.truncated`` 函数用于控制如何赋值给较小的类型。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:192
+msgid "``RoundType``:"
+msgstr "``RoundType``："
+
+#: ../../SpinalHDL/Data types/AFix.rst:207
+msgid ""
+"The ``saturation`` flag will add logic to saturate to the assigned datatype "
+"range."
+msgstr "当设置 ``saturation`` 标志时，系统会在数值超出指定数据类型的界限时，自动将其"
+"调整至该类型的有效范围，以防止溢出。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:209
+msgid ""
+"The ``overflow`` flag will allow assignment directly after rounding without "
+"range checking."
+msgstr "``overflow`` 标志将允许在舍入后直接赋值，而不进行范围检查。"
+
+#: ../../SpinalHDL/Data types/AFix.rst:211
+msgid ""
+"Rounding is always required when assigning a value with more precision to "
+"one with lower precision."
+msgstr "将精度较高的值分配给精度较低的值时，始终需要进行舍入。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po
new file mode 100644
index 00000000000..f1611ef0c2e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po	
@@ -0,0 +1,530 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesfix/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../SpinalHDL/Data types/Fix.rst:2
+msgid ""
+"SpinalHDL fixed-point support is only partially used/tested, if you find any"
+" bugs with it, or you think that some functionality is missing, please "
+"create a `Github issue <https://github.com/SpinalHDL/SpinalHDL/issues>`_. "
+"Also, please do not use undocumented features in your code."
+msgstr ""
+"SpinalHDL "
+"定点支持仅部分使用/测试，如果您发现任何错误，或者您认为缺少某些功能，请创建 `"
+"Github issue <https://github.com/SpinalHDL/SpinalHDL/"
+"issues>`_。另外，请不要在代码中使用未归档的功能。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:7
+msgid "UFix/SFix"
+msgstr "UFix/SFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:10 types/Fix.rst:169 types/Fix.rst:208
+#: types/Fix.rst:237 types/Fix.rst:273
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/Fix.rst:12
+msgid ""
+"The ``UFix`` and ``SFix`` types correspond to a vector of bits that can be "
+"used for fixed-point arithmetic."
+msgstr "``UFix`` 和 ``SFix`` 类型对应于可用于定点算术的位向量。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:15
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/Fix.rst:17
+msgid "The syntax to declare a fixed-point number is as follows:"
+msgstr "声明定点数的语法如下："
+
+#: ../../SpinalHDL/Data types/Fix.rst:20
+msgid "Unsigned Fixed-Point"
+msgstr "无符号定点小数"
+
+#: ../../SpinalHDL/Data types/Fix.rst:26 types/Fix.rst:49
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Data types/Fix.rst:27 types/Fix.rst:50
+msgid "bit width"
+msgstr "位宽"
+
+#: ../../SpinalHDL/Data types/Fix.rst:28 types/Fix.rst:51
+msgid "resolution"
+msgstr "分辨率"
+
+#: ../../SpinalHDL/Data types/Fix.rst:29 types/Fix.rst:52
+msgid "max"
+msgstr "最大值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:30 types/Fix.rst:53
+msgid "min"
+msgstr "最小值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:31
+msgid "UFix(peak: ExpNumber, resolution: ExpNumber)"
+msgstr "UFix(peak: ExpNumber, resolution: ExpNumber)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:32
+msgid "peak-resolution"
+msgstr "peak-resolution"
+
+#: ../../SpinalHDL/Data types/Fix.rst:33 types/Fix.rst:56
+msgid "2^resolution"
+msgstr "2^resolution"
+
+#: ../../SpinalHDL/Data types/Fix.rst:34 types/Fix.rst:57
+msgid "2^peak-2^resolution"
+msgstr "2^peak-2^resolution"
+
+#: ../../SpinalHDL/Data types/Fix.rst:35 types/Fix.rst:40
+msgid "0"
+msgstr "0"
+
+#: ../../SpinalHDL/Data types/Fix.rst:36
+msgid "UFix(peak: ExpNumber, width: BitCount)"
+msgstr "UFix(peak: ExpNumber, width: BitCount)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:37 types/Fix.rst:60
+msgid "width"
+msgstr "width"
+
+#: ../../SpinalHDL/Data types/Fix.rst:38
+msgid "2^(peak-width)"
+msgstr "2^(peak-width)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:39
+msgid "2^peak-2^(peak-width)"
+msgstr "2^peak-2^(peak-width)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:43
+msgid "Signed Fixed-Point"
+msgstr "有符号定点小数"
+
+#: ../../SpinalHDL/Data types/Fix.rst:54
+msgid "SFix(peak: ExpNumber, resolution: ExpNumber)"
+msgstr "SFix(peak: ExpNumber, resolution: ExpNumber)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:55
+msgid "peak-resolution+1"
+msgstr "peak-resolution+1"
+
+#: ../../SpinalHDL/Data types/Fix.rst:58 types/Fix.rst:63
+msgid "-(2^peak)"
+msgstr "-(2^peak)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:59
+msgid "SFix(peak: ExpNumber, width: BitCount)"
+msgstr "SFix(peak: ExpNumber, width: BitCount)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:61
+msgid "2^(peak-width-1)"
+msgstr "2^(peak-width-1)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:62
+msgid "2^peak-2^(peak-width-1)"
+msgstr "2^peak-2^(peak-width-1)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:66
+msgid "Format"
+msgstr "格式"
+
+#: ../../SpinalHDL/Data types/Fix.rst:68
+msgid ""
+"The chosen format follows the usual way of defining fixed-point number "
+"format using Q notation. More information can be found on the `Wikipedia "
+"page about the Q number format "
+"<https://en.wikipedia.org/wiki/Q_(number_format)>`_."
+msgstr ""
+"所选格式遵循使用 Q 表示法定义定点小数格式的常用方法。更多信息可以在 `Q "
+"数据格式的维基百科页面 <https://en.wikipedia.org/wiki/Q_(number_format)>`_ "
+"上找到。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:70
+msgid ""
+"For example Q8.2 will mean a fixed-point number of 8+2 bits, where 8 bits "
+"are used for the natural part and 2 bits for the fractional part. If the "
+"fixed-point number is signed, one more bit is used for the sign."
+msgstr "例如，Q8.2表示8+2位的定点数，其中8位用于自然部分，2位用于小数部分。如果定点数"
+"有符号，则多一位用于符号。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:73
+msgid ""
+"The resolution is defined as being the smallest power of two that can be "
+"represented in this number."
+msgstr "分辨率被定义为可以用该数字表示的最小的二的幂。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:76
+msgid ""
+"To make representing power-of-two numbers less error prone, there is a "
+"numeric type in ``spinal.core`` called ``ExpNumber``, which is used for the "
+"fixed-point type constructors. A convenience wrapper exists for this type, "
+"in the form of the ``exp`` function (used in the code samples on this page)."
+msgstr ""
+"为了使表示二次幂的数字不易出错，在 ``spinal.core``中有一个称为 ``ExpNumber`` "
+"的数字类型，它用于定点类型构造函数。这种类型有一个方便的封装，采用 ``exp`` "
+"函数的形式（在本页的代码示例中使用）。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:80
+msgid "Examples"
+msgstr "示例"
+
+#: ../../SpinalHDL/Data types/Fix.rst:99
+msgid "Assignments"
+msgstr "赋值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:102
+msgid "Valid Assignments"
+msgstr "有效赋值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:104
+msgid ""
+"An assignment to a fixed-point value is valid when there is no bit loss. Any"
+" bit loss will result in an error."
+msgstr "当没有位丢失时，对定点小数值的分配是有效的。任何位丢失都会导致错误。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:106
+msgid ""
+"If the source fixed-point value is too big, the ``truncated`` function will "
+"allow you to resize the source number to match the destination size."
+msgstr "如果源定点小数值太大，``truncated`` "
+"函数将允许您调整源数字的大小以匹配目标大小。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:109 types/Fix.rst:134 types/Fix.rst:148
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Data types/Fix.rst:129
+msgid "From a Scala constant"
+msgstr "来自 Scala 常量"
+
+#: ../../SpinalHDL/Data types/Fix.rst:131
+msgid ""
+"Scala ``BigInt`` or ``Double`` types can be used as constants when assigning"
+" to ``UFix`` or ``SFix`` signals."
+msgstr "当给 ``UFix`` 或 ``SFix`` 信号赋值时，Scala的 ``BigInt`` 或 ``Double`` "
+"类型可以用作常量。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:143
+msgid "Raw value"
+msgstr "原始值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:145
+msgid ""
+"The integer representation of the fixed-point number can be read or written "
+"by using the ``raw`` property."
+msgstr "可以使用 ``raw`` 属性读取或写入定点小数的整数表示形式。"
+
+#: ../../SpinalHDL/Data types/Fix.rst:157
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Fix.rst:159
+msgid "The following operators are available for the ``UFix`` type:"
+msgstr "以下运算符可用于 ``UFix`` 类型："
+
+#: ../../SpinalHDL/Data types/Fix.rst:162
+msgid "Arithmetic"
+msgstr "算术运算"
+
+#: ../../SpinalHDL/Data types/Fix.rst:168 types/Fix.rst:207 types/Fix.rst:236
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Fix.rst:170
+msgid "Returned resolution"
+msgstr "返回值的分辨率"
+
+#: ../../SpinalHDL/Data types/Fix.rst:171
+msgid "Returned amplitude"
+msgstr "返回值的幅度"
+
+#: ../../SpinalHDL/Data types/Fix.rst:172
+msgid "x + y"
+msgstr "x + y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:173
+msgid "Addition"
+msgstr "加法"
+
+#: ../../SpinalHDL/Data types/Fix.rst:174 types/Fix.rst:178
+msgid "Min(x.resolution, y.resolution)"
+msgstr "Min(x.resolution, y.resolution)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:175 types/Fix.rst:179
+msgid "Max(x.amplitude, y.amplitude)"
+msgstr "Max(x.amplitude, y.amplitude)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:176
+msgid "x - y"
+msgstr "x - y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:177
+msgid "Subtraction"
+msgstr "减法"
+
+#: ../../SpinalHDL/Data types/Fix.rst:180
+msgid "x * y"
+msgstr "x * y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:181
+msgid "Multiplication"
+msgstr "乘法"
+
+#: ../../SpinalHDL/Data types/Fix.rst:182
+msgid "x.resolution * y.resolution)"
+msgstr "x.resolution * y.resolution)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:183 types/Fix.rst:281
+msgid "x.amplitude * y.amplitude"
+msgstr "x.amplitude * y.amplitude"
+
+#: ../../SpinalHDL/Data types/Fix.rst:184
+msgid "x >> y"
+msgstr "x >> y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:185 types/Fix.rst:193
+msgid "Arithmetic shift right, y : Int"
+msgstr "算术右移，y : Int"
+
+#: ../../SpinalHDL/Data types/Fix.rst:186 types/Fix.rst:194
+msgid "x.amplitude >> y"
+msgstr "x.amplitude >> y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:187
+msgid "x.resolution >> y"
+msgstr "x.resolution >> y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:188
+msgid "x << y"
+msgstr "x << y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:189 types/Fix.rst:197
+msgid "Arithmetic shift left, y : Int"
+msgstr "算术左移，y : Int"
+
+#: ../../SpinalHDL/Data types/Fix.rst:190 types/Fix.rst:198
+msgid "x.amplitude << y"
+msgstr "x.amplitude << y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:191
+msgid "x.resolution << y"
+msgstr "x.resolution << y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:192
+msgid "x >>| y"
+msgstr "x >>| y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:195 types/Fix.rst:199 types/Fix.rst:280
+msgid "x.resolution"
+msgstr "x.resolution"
+
+#: ../../SpinalHDL/Data types/Fix.rst:196
+msgid "x <<| y"
+msgstr "x <<| y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:202
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/Fix.rst:209
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Fix.rst:210
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:211
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/Fix.rst:212 types/Fix.rst:215 types/Fix.rst:218
+#: types/Fix.rst:221 types/Fix.rst:224 types/Fix.rst:227
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/Fix.rst:213
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:214
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/Fix.rst:216
+msgid "x > y"
+msgstr "x > y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:217
+msgid "Greater than"
+msgstr "大于"
+
+#: ../../SpinalHDL/Data types/Fix.rst:219 types/Fix.rst:225
+msgid "x >= y"
+msgstr "x >= y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:220
+msgid "Greater than or equal"
+msgstr "大于或等于"
+
+#: ../../SpinalHDL/Data types/Fix.rst:222
+msgid "x < y"
+msgstr "x < y"
+
+#: ../../SpinalHDL/Data types/Fix.rst:223
+msgid "Less than"
+msgstr "小于"
+
+#: ../../SpinalHDL/Data types/Fix.rst:226
+msgid "Less than or equal"
+msgstr "小于或等于"
+
+#: ../../SpinalHDL/Data types/Fix.rst:230
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/Fix.rst:238 types/Fix.rst:272
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Fix.rst:239
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/Fix.rst:240
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/Fix.rst:241
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:242
+msgid "x.asUInt"
+msgstr "x.asUInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:243
+msgid "Binary cast to UInt"
+msgstr "二进制转换为 UInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:244
+msgid "UInt(w(x) bits)"
+msgstr "UInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:245
+msgid "x.asSInt"
+msgstr "x.asSInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:246
+msgid "Binary cast to SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:247
+msgid "SInt(w(x) bits)"
+msgstr "SInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Fix.rst:248
+msgid "x.asBools"
+msgstr "x.asBools"
+
+#: ../../SpinalHDL/Data types/Fix.rst:249
+msgid "Cast into a array of Bool"
+msgstr "转换为 Bool 数组"
+
+#: ../../SpinalHDL/Data types/Fix.rst:250
+msgid "Vec(Bool(),width(x))"
+msgstr "Vec(Bool(),width(x))"
+
+#: ../../SpinalHDL/Data types/Fix.rst:251
+msgid "x.toUInt"
+msgstr "x.toUInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:252
+msgid "Return the corresponding UInt (with truncation)"
+msgstr "返回对应的UInt（带截断）"
+
+#: ../../SpinalHDL/Data types/Fix.rst:253
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:254
+msgid "x.toSInt"
+msgstr "x.toSInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:255
+msgid "Return the corresponding SInt (with truncation)"
+msgstr "返回对应的SInt（带截断）"
+
+#: ../../SpinalHDL/Data types/Fix.rst:256
+msgid "SInt"
+msgstr "SInt"
+
+#: ../../SpinalHDL/Data types/Fix.rst:257
+msgid "x.toUFix"
+msgstr "x.toUFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:258
+msgid "Return the corresponding UFix"
+msgstr "返回对应的UFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:259
+msgid "UFix"
+msgstr "UFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:260
+msgid "x.toSFix"
+msgstr "x.toSFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:261
+msgid "Return the corresponding SFix"
+msgstr "返回对应的SFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:262
+msgid "SFix"
+msgstr "SFix"
+
+#: ../../SpinalHDL/Data types/Fix.rst:265
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Data types/Fix.rst:271
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Data types/Fix.rst:274
+msgid "x.maxValue"
+msgstr "x.maxValue"
+
+#: ../../SpinalHDL/Data types/Fix.rst:275
+msgid "Return the maximum value storable"
+msgstr "返回可存储的最大值"
+
+#: ../../SpinalHDL/Data types/Fix.rst:276 types/Fix.rst:279 types/Fix.rst:282
+msgid "Double"
+msgstr "Double"
+
+#: ../../SpinalHDL/Data types/Fix.rst:277
+msgid "x.minValue"
+msgstr "x.minValue"
+
+#: ../../SpinalHDL/Data types/Fix.rst:278
+msgid "Return the minimum value storable"
+msgstr "返回可存储的最小值"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Floating.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Floating.po
new file mode 100644
index 00000000000..01822516cd0
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Floating.po	
@@ -0,0 +1,346 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-27 15:40+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesfloating/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:2
+msgid ""
+"SpinalHDL floating-point support is under development and only partially "
+"used/tested, if you have any bugs with it, or you think that some "
+"functionality is missing, please create a `Github issue "
+"<https://github.com/SpinalHDL/SpinalHDL/issues>`_. Also, please do not use "
+"undocumented features in your code."
+msgstr ""
+"SpinalHDL 浮点小数支持正在开发中，仅部分使用/测试，如果您有任何错误，或者您认"
+"为缺少某些功能，请创建 `Github issue <https://github.com/SpinalHDL/SpinalHDL/"
+"issues>`_。另外，请不要在代码中使用未归档的功能。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:7
+msgid "Floating"
+msgstr "浮点小数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:10 types/Floating.rst:78
+#: types/Floating.rst:97 types/Floating.rst:122
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:12
+msgid ""
+"The ``Floating`` type corresponds to IEEE-754 encoded numbers. A second type"
+" called ``RecFloating`` helps in simplifying your design by recoding the "
+"floating-point value simplify some edge cases in IEEE-754 floating-point."
+msgstr ""
+"``Floating`` 类型对应于 IEEE-754 编码数字。第二种类型称为 ``RecFloating`` "
+"，通过重新编码浮点值来帮助简化设计，简化 IEEE-754 浮点中的一些边缘情况。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:14
+msgid ""
+"It's composed of a sign bit, an exponent field and a mantissa field. The "
+"widths of the different fields are defined in the IEEE-754 or de-facto "
+"standards."
+msgstr "它由一个符号位、一个指数字段和一个尾数字段组成。不同字段的宽度在 IEEE-754 "
+"或事实上的标准中定义。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:16
+msgid "This type can be used with the following import:"
+msgstr "此类型可通过以下方法导入使用："
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:23
+msgid "IEEE-754 floating format"
+msgstr "IEEE-754 浮点小数格式"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:25
+msgid ""
+"The numbers are encoded into IEEE-754 `floating-point format "
+"<https://en.wikipedia.org/wiki/IEEE_floating_point>`_."
+msgstr ""
+"这些数字被编码为 IEEE-754 `浮点格式 <https://en.wikipedia.org/wiki/"
+"IEEE_floating_point>`_。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:28
+msgid "Recoded floating format"
+msgstr "重新编码的浮动小数格式"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:30
+msgid ""
+"Since IEEE-754 has some quirks about denormalized numbers and special "
+"values, Berkeley proposed another way of recoding floating-point values."
+msgstr "由于 IEEE-754 对非规范化数字和特殊值有一些怪癖，加州大学伯克利分校提出了另一"
+"种重新编码浮点小数值的方法。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:32
+msgid ""
+"The mantissa is modified so that denormalized values can be treated the same"
+" as the normalized ones."
+msgstr "通过修改尾数，以便非标准化值可以与标准化值相同地对待。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:34
+msgid "The exponent field is one bit larger that one of the IEEE-754 number."
+msgstr "指数字段比 IEEE-754 定义的大一位。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:36
+msgid "The sign bit is kept unchanged between the two encodings."
+msgstr "两种编码之间的符号位保持不变。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:38
+msgid ""
+"Examples can be found `here <https://github.com/ucb-bar/berkeley-"
+"hardfloat/blob/master/README.md>`_"
+msgstr ""
+"示例可以在 `这里 <https://github.com/ucb-bar/berkeley-hardfloat/blob/master/"
+"README.md>`_ 找到"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:41
+msgid "Zero"
+msgstr "零"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:43
+msgid ""
+"The zero is encoded with the three leading zeros of the exponent field being"
+" set to zero."
+msgstr "零的编码是，指数字段的三个前导零被设置为零。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:46
+msgid "Denormalized values"
+msgstr "非规范化值"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:48
+msgid ""
+"Denormalized values are encoded in the same way as a normal floating-point "
+"number. The mantissa is shifted so that the first one becomes implicit. The "
+"exponent is encoded as 107 (decimal) plus the index of the highest bit set "
+"to 1."
+msgstr ""
+"在浮点数表示中，非规范化数值的编码方式与规范化数值相同。尾数部分会进行位移，"
+"使得最左边的1位成为隐含的，而指数部分则由107（十进制）加上最左边1位的位置索引"
+"来计算。这样的编码确保了非规范化数值能够正确表示。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:52
+msgid "Normalized values"
+msgstr "标准化值"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:54
+msgid ""
+"The recoded mantissa for normalized values is exactly the same as the "
+"original IEEE-754 mantissa. The recoded exponent is encoded as 130 (decimal)"
+" plus the original exponent value."
+msgstr "标准化值的重新编码尾数与原始 IEEE-754 尾数完全相同。重新编码的指数被编码为 "
+"130（十进制）加上原始指数值。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:57
+msgid "Infinity"
+msgstr "无穷大"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:59
+msgid ""
+"The recoded mantissa value is treated as don't care. The recoded exponent "
+"three highest bits is 6 (decimal), the rest of the exponent can be treated "
+"as don't care."
+msgstr "此时，重新编码的尾数值被视为无关紧要。重新编码的指数三位最高位是6（十进制），"
+"其余指数可以视为不关心。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:62
+msgid "NaN"
+msgstr "无效数（NaN）"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:64
+msgid ""
+"The recoded mantissa for normalized values is exactly the same as the "
+"original IEEE-754 mantissa. The recoded exponent three highest bits is 7 "
+"(decimal), the rest of the exponent can be treated as don't care."
+msgstr "此时，重新编码中尾数与原始 IEEE-754 "
+"尾数完全相同。重新编码的指数三位最高位是7（十进制），其余指数可以视为不关心。"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:67
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:69
+msgid "The syntax to declare a floating-point number is as follows:"
+msgstr "声明浮点小数的语法如下："
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:72
+msgid "IEEE-754 Number"
+msgstr "IEEE-754 编码数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:77 types/Floating.rst:96
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:79
+msgid "Floating(exponentSize: Int, mantissaSize: Int)"
+msgstr "Floating(exponentSize: Int, mantissaSize: Int)"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:80
+msgid "IEEE-754 Floating-point value with a custom exponent and mantissa size"
+msgstr "具有自定义指数和尾数大小的 IEEE-754 浮点值"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:81
+msgid "Floating16()"
+msgstr "Floating16()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:82
+msgid "IEEE-754 Half precision floating-point number"
+msgstr "IEEE-754 半精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:83
+msgid "Floating32()"
+msgstr "Floating32()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:84
+msgid "IEEE-754 Single precision floating-point number"
+msgstr "IEEE-754 单精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:85
+msgid "Floating64()"
+msgstr "Floating64()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:86
+msgid "IEEE-754 Double precision floating-point number"
+msgstr "IEEE-754 双精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:87
+msgid "Floating128()"
+msgstr "Floating128()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:88
+msgid "IEEE-754 Quad precision floating-point number"
+msgstr "IEEE-754 四精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:91
+msgid "Recoded floating-point number"
+msgstr "重新编码的浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:98
+msgid "RecFloating(exponentSize: Int, mantissaSize: Int)"
+msgstr "RecFloating(exponentSize: Int, mantissaSize: Int)"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:99
+msgid "Recoded Floating-point value with a custom exponent and mantissa size"
+msgstr "使用自定义指数和尾数大小重新编码的浮点小数值"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:100
+msgid "RecFloating16()"
+msgstr "RecFloating16()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:101
+msgid "Recoded Half precision floating-point number"
+msgstr "重新编码的半精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:102
+msgid "RecFloating32()"
+msgstr "RecFloating32()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:103
+msgid "Recoded Single precision floating-point number"
+msgstr "重新编码的单精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:104
+msgid "RecFloating64()"
+msgstr "RecFloating64()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:105
+msgid "Recoded Double precision floating-point number"
+msgstr "重新编码的双精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:106
+msgid "RecFloating128()"
+msgstr "RecFloating128()"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:107
+msgid "Recoded Quad precision floating-point number"
+msgstr "重新编码的四精度浮点数"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:110
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:112
+msgid ""
+"The following operators are available for the ``Floating`` and "
+"``RecFloating`` types:"
+msgstr "以下运算符可用于 ``Floating`` 和 ``RecFloating`` 类型："
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:115
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:121
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:123
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:124
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:125
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:126
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:127
+msgid "x.asBools"
+msgstr "x.asBools"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:128
+msgid "Cast into a array of Bool"
+msgstr "转换为 Bool 数组"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:129
+msgid "Vec(Bool(),width(x))"
+msgstr "Vec(Bool(),width(x))"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:130
+msgid "x.toUInt(size: Int)"
+msgstr "x.toUInt(size: Int)"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:131
+msgid "Return the corresponding UInt (with truncation)"
+msgstr "返回对应的UInt（带截断）"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:132 types/Floating.rst:138
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:133
+msgid "x.toSInt(size: Int)"
+msgstr "x.toSInt(size: Int)"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:134
+msgid "Return the corresponding SInt (with truncation)"
+msgstr "返回对应的SInt（带截断）"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:135 types/Floating.rst:141
+msgid "SInt"
+msgstr "SInt"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:136
+msgid "x.fromUInt"
+msgstr "x.fromUInt"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:137 types/Floating.rst:140
+msgid "Return the corresponding Floating (with truncation)"
+msgstr "返回对应的Floating（带截断）"
+
+#: ../../source/SpinalHDL/Data types/Floating.rst:139
+msgid "x.fromSInt"
+msgstr "x.fromSInt"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po
new file mode 100644
index 00000000000..e65a47b6b7b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po	
@@ -0,0 +1,1551 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesint/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Data types/Int.rst:4 types/Int.rst:620
+msgid "UInt/SInt"
+msgstr "UInt/SInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:6
+msgid ""
+"The ``UInt``/``SInt`` types are vectors of bits interpreted as two's "
+"complement unsigned/signed integers. They can do what ``Bits`` can do, with "
+"the addition of unsigned/signed integer arithmetic and comparisons."
+msgstr ""
+"``UInt``/``SInt`` 类型用于表达二进制补码无符号/有符号整数的位向量。"
+"他们可以做 ``Bits`` 相同的事情，但具有无符号/有符号整数算术和比较。"
+
+#: ../../SpinalHDL/Data types/Int.rst:10
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/Int.rst:12
+msgid ""
+"The syntax to declare an integer is as follows:  (everything between [] is "
+"optional)"
+msgstr "以下是声明一个整数的语法：（[] 中的内容是可选的）"
+
+#: ../../SpinalHDL/Data types/Int.rst:18
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Data types/Int.rst:19 types/Int.rst:78 types/Int.rst:179
+#: types/Int.rst:243 types/Int.rst:292 types/Int.rst:378 types/Int.rst:480
+#: types/Int.rst:674
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "UInt[()]"
+msgstr "UInt[()]"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "SInt[()]"
+msgstr "SInt[()]"
+
+#: ../../SpinalHDL/Data types/Int.rst:22
+msgid "Create an unsigned/signed integer, bits count is inferred"
+msgstr "创建一个无符号/有符号整数，自动推断位数"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "UInt(x bits)"
+msgstr "UInt(x bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "SInt(x bits)"
+msgstr "SInt(x bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:25
+msgid "Create an unsigned/signed integer with x bits"
+msgstr "创建一个 x 位的无符号/有符号整数"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "U(value: Int[,x bits])"
+msgstr "U(value: Int[,x bits])"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "U(value: BigInt[,x bits])"
+msgstr "U(value: BigInt[,x bits])"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "S(value: Int[,x bits])"
+msgstr "S(value: Int[,x bits])"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "S(value: BigInt[,x bits])"
+msgstr "S(value: BigInt[,x bits])"
+
+#: ../../SpinalHDL/Data types/Int.rst types/Int.rst:30
+msgid "Create an unsigned/signed integer assigned with 'value'"
+msgstr "创建一个无符号/有符号整数，并将其分配给 'value'"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "U\"[[size']base]value\""
+msgstr "U\"[[size']base]value\""
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "S\"[[size']base]value\""
+msgstr "S\"[[size']base]value\""
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "(base: 'h', 'd', 'o', 'b')"
+msgstr "(base: 'h', 'd', 'o', 'b')"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "U([x bits,] elements: Element*)"
+msgstr "U([x bits,] elements: Element*)"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "S([x bits,] elements: Element*)"
+msgstr "S([x bits,] elements: Element*)"
+
+#: ../../SpinalHDL/Data types/Int.rst:37
+msgid ""
+"Create an unsigned integer assigned with the value specified by "
+":ref:`elements <element>`"
+msgstr "创建一个无符号整数，并为其赋值一个由 :ref:`elements <element>` 指定的值"
+
+#: ../../SpinalHDL/Data types/Int.rst:66
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Int.rst:68
+msgid ""
+"The following operators are available for the ``UInt`` and ``SInt`` types:"
+msgstr "以下运算符可用于 ``UInt`` 和 ``SInt`` 类型："
+
+#: ../../SpinalHDL/Data types/Int.rst:71
+msgid "Logic"
+msgstr "逻辑运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:77 types/Int.rst:178 types/Int.rst:242
+#: types/Int.rst:291 types/Int.rst:377 types/Int.rst:479
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Int.rst:79 types/Int.rst:244
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Int.rst:80 types/Int.rst:208
+msgid "~x"
+msgstr "~x"
+
+#: ../../SpinalHDL/Data types/Int.rst:81
+msgid "Bitwise NOT"
+msgstr "按位非"
+
+#: ../../SpinalHDL/Data types/Int.rst:82 types/Int.rst:106 types/Int.rst:115
+#: types/Int.rst:118 types/Int.rst:122 types/Int.rst:126 types/Int.rst:204
+#: types/Int.rst:210 types/Int.rst:516
+msgid "T(w(x) bits)"
+msgstr "T(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:83
+msgid "x & y"
+msgstr "x & y"
+
+#: ../../SpinalHDL/Data types/Int.rst:84
+msgid "Bitwise AND"
+msgstr "按位与"
+
+#: ../../SpinalHDL/Data types/Int.rst:85 types/Int.rst:88 types/Int.rst:91
+#: types/Int.rst:183 types/Int.rst:189 types/Int.rst:192 types/Int.rst:198
+msgid "T(max(w(x), w(y)) bits)"
+msgstr "T(max(w(x), w(y)) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:86
+msgid "x | y"
+msgstr "x | y"
+
+#: ../../SpinalHDL/Data types/Int.rst:87
+msgid "Bitwise OR"
+msgstr "按位或"
+
+#: ../../SpinalHDL/Data types/Int.rst:89
+msgid "x ^ y"
+msgstr "x ^ y"
+
+#: ../../SpinalHDL/Data types/Int.rst:90
+msgid "Bitwise XOR"
+msgstr "按位异或"
+
+#: ../../SpinalHDL/Data types/Int.rst:92
+msgid "x.xorR"
+msgstr "x.xorR"
+
+#: ../../SpinalHDL/Data types/Int.rst:93
+msgid "XOR all bits of x (reduction operator)"
+msgstr "对 x 的所有位进行异或（缩减运算符）"
+
+#: ../../SpinalHDL/Data types/Int.rst:94 types/Int.rst:97 types/Int.rst:100
+#: types/Int.rst:247 types/Int.rst:250 types/Int.rst:253 types/Int.rst:256
+#: types/Int.rst:259 types/Int.rst:262 types/Int.rst:382 types/Int.rst:385
+#: types/Int.rst:403 types/Int.rst:406 types/Int.rst:409
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/Int.rst:95
+msgid "x.orR"
+msgstr "x.orR"
+
+#: ../../SpinalHDL/Data types/Int.rst:96
+msgid "OR all bits of x (reduction operator)"
+msgstr "对x 的所有位进行或操作（缩减运算符）"
+
+#: ../../SpinalHDL/Data types/Int.rst:98
+msgid "x.andR"
+msgstr "x.andR"
+
+#: ../../SpinalHDL/Data types/Int.rst:99
+msgid "AND all bits of x (reduction operator)"
+msgstr "对 x 的所有位进行与操作（缩减运算符）"
+
+#: ../../SpinalHDL/Data types/Int.rst:101 types/Int.rst:104
+msgid "x \\>\\> y"
+msgstr "x \\>\\> y"
+
+#: ../../SpinalHDL/Data types/Int.rst:102
+msgid "Arithmetic shift right, y : Int"
+msgstr "算术右移，y : Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:103
+msgid "T(w(x) - y bits)"
+msgstr "T(w(x) - y bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:105
+msgid "Arithmetic shift right, y : UInt"
+msgstr "算术右移，y : UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:107 types/Int.rst:110
+msgid "x \\<\\< y"
+msgstr "x \\<\\< y"
+
+#: ../../SpinalHDL/Data types/Int.rst:108
+msgid "Arithmetic shift left, y : Int"
+msgstr "算术左移，y : Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:109
+msgid "T(w(x) + y bits)"
+msgstr "T(w(x) + y bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:111
+msgid "Arithmetic shift left, y : UInt"
+msgstr "算术左移，y : UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:112
+msgid "T(w(x) + max(y) bits)"
+msgstr "T(w(x) + max(y) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:113
+msgid "x \\|\\>\\> y"
+msgstr "x \\|\\>\\> y"
+
+#: ../../SpinalHDL/Data types/Int.rst:114
+msgid "Logical shift right, y : Int/UInt"
+msgstr "逻辑右移，y : Int/UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:116
+msgid "x \\|\\<\\< y"
+msgstr "x \\|\\<\\< y"
+
+#: ../../SpinalHDL/Data types/Int.rst:117
+msgid "Logical shift left, y : Int/UInt"
+msgstr "逻辑左移，y : Int/UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:119
+msgid "x.rotateLeft(y)"
+msgstr "x.rotateLeft(y)"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "Logical left rotation, y : UInt/Int"
+msgstr "逻辑循环左移，y : UInt/Int"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "The width of y is constrained to the width of log2Up(x) or less"
+msgstr "y 的宽度被限制为 log2Up(x) 的宽度或更小"
+
+#: ../../SpinalHDL/Data types/Int.rst:123
+msgid "x.rotateRight(y)"
+msgstr "x.rotateRight(y)"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "Logical right rotation, y : UInt/Int"
+msgstr "逻辑循环右移，y : UInt/Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:127
+msgid "x.clearAll[()]"
+msgstr "x.clearAll[()]"
+
+#: ../../SpinalHDL/Data types/Int.rst:128
+msgid "Clear all bits"
+msgstr "清零所有位"
+
+#: ../../SpinalHDL/Data types/Int.rst:129 types/Int.rst:132 types/Int.rst:135
+#: types/Int.rst:138
+msgid "*modifies x*"
+msgstr "*修改x*"
+
+#: ../../SpinalHDL/Data types/Int.rst:130
+msgid "x.setAll[()]"
+msgstr "x.setAll[()]"
+
+#: ../../SpinalHDL/Data types/Int.rst:131
+msgid "Set all bits"
+msgstr "将所有的位设置为1"
+
+#: ../../SpinalHDL/Data types/Int.rst:133
+msgid "x.setAllTo(value : Boolean)"
+msgstr "x.setAllTo(value : Boolean)"
+
+#: ../../SpinalHDL/Data types/Int.rst:134
+msgid "Set all bits to the given Boolean value"
+msgstr "将所有位设置为给定的布尔值（Scala Boolean）"
+
+#: ../../SpinalHDL/Data types/Int.rst:136
+msgid "x.setAllTo(value : Bool)"
+msgstr "x.setAllTo(value : Bool)"
+
+#: ../../SpinalHDL/Data types/Int.rst:137
+msgid "Set all bits to the given Bool value"
+msgstr "将所有位设置为给定的布尔值（Spinal Bool）"
+
+#: ../../SpinalHDL/Data types/Int.rst:142
+msgid ""
+"Notice the difference in behaviour between ``x >> 2`` (result 2 bit narrower"
+" than x) and ``x >> U(2)`` (keeping width) due to the Scala type of "
+":code:`y`."
+msgstr ""
+"请注意由于 :code:`y` 的 Scala 类型原因， ``x >> 2`` （结果比 x 窄 2 位）和 ``"
+"x >> U(2)``（保持宽度）之间的行为有差异。"
+
+#: ../../SpinalHDL/Data types/Int.rst:145
+msgid ""
+"In the first case \"2\" is an ``Int`` (which can be seen as an \"elaboration"
+" integer constant\"), and in the second case it is a hardware signal (type "
+"``UInt``) that may or may not be a constant."
+msgstr ""
+"在第一种情况下，“2”是一个 ``Int`` "
+"的值（可以看作是“实例细化整数常量”），在第二种情况下，它是一个硬件信号（ "
+"``UInt`` 类型）这也可能不是一个常数。"
+
+#: ../../SpinalHDL/Data types/Int.rst:173
+msgid "Arithmetic"
+msgstr "算术运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:180 types/Int.rst:293 types/Int.rst:379
+#: types/Int.rst:481 types/Int.rst:674
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Int.rst:181
+msgid "x + y"
+msgstr "x + y"
+
+#: ../../SpinalHDL/Data types/Int.rst:182
+msgid "Addition"
+msgstr "加法"
+
+#: ../../SpinalHDL/Data types/Int.rst:184
+msgid "x +^ y"
+msgstr "x +^ y"
+
+#: ../../SpinalHDL/Data types/Int.rst:185
+msgid "Addition with carry"
+msgstr "带进位的加法"
+
+#: ../../SpinalHDL/Data types/Int.rst:186 types/Int.rst:195
+msgid "T(max(w(x), w(y)) + 1 bits)"
+msgstr "T(max(w(x), w(y)) + 1 bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:187
+msgid "x +| y"
+msgstr "x +| y"
+
+#: ../../SpinalHDL/Data types/Int.rst:188
+msgid ""
+"Addition of addend with `saturation`_ (see also `T.maxValue` and "
+"`T.minValue`)"
+msgstr "添加带有饱和（ `saturation`_）的加数（另请参见 `T.maxValue` 和 `T.minValue`）"
+
+#: ../../SpinalHDL/Data types/Int.rst:190
+msgid "x - y"
+msgstr "x - y"
+
+#: ../../SpinalHDL/Data types/Int.rst:191
+msgid "Subtraction"
+msgstr "减法"
+
+#: ../../SpinalHDL/Data types/Int.rst:193
+msgid "x -^ y"
+msgstr "x -^ y"
+
+#: ../../SpinalHDL/Data types/Int.rst:194
+msgid "Subtraction with carry"
+msgstr "带进位的减法"
+
+#: ../../SpinalHDL/Data types/Int.rst:196
+msgid "x -| y"
+msgstr "x -| y"
+
+#: ../../SpinalHDL/Data types/Int.rst:197
+msgid ""
+"Subtraction of subtrahend with `saturation`_ (see also `T.minValue` and "
+"`T.maxValue`)"
+msgstr "带饱和（ `saturation`_）的减法（另请参见 `T.minValue` 和 `T.maxValue`）"
+
+#: ../../SpinalHDL/Data types/Int.rst:199
+msgid "x * y"
+msgstr "x * y"
+
+#: ../../SpinalHDL/Data types/Int.rst:200
+msgid "Multiplication"
+msgstr "乘法"
+
+#: ../../SpinalHDL/Data types/Int.rst:201
+msgid "T(w(x) + w(y)) bits)"
+msgstr "T(w(x) + w(y)) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:202
+msgid "x / y"
+msgstr "x / y"
+
+#: ../../SpinalHDL/Data types/Int.rst:203
+msgid "Division"
+msgstr "除法"
+
+#: ../../SpinalHDL/Data types/Int.rst:205
+msgid "x % y"
+msgstr "x % y"
+
+#: ../../SpinalHDL/Data types/Int.rst:206
+msgid "Modulo"
+msgstr "求模运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:207
+msgid "T(min(w(x), w(y)) bits)"
+msgstr "T(min(w(x), w(y)) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:209
+msgid "Unary One's compliment, Bitwise NOT"
+msgstr "一元补码运算，按位非（NOT）"
+
+#: ../../SpinalHDL/Data types/Int.rst:211
+msgid "-x"
+msgstr "-x"
+
+#: ../../SpinalHDL/Data types/Int.rst:212
+msgid "Unary Two's compliment of SInt type.  Not available for UInt."
+msgstr "SInt 类型的一元二进制补码。不适用于 UInt。"
+
+#: ../../SpinalHDL/Data types/Int.rst:213 types/Int.rst:302 types/Int.rst:311
+msgid "SInt(w(x) bits)"
+msgstr "SInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:233
+msgid ""
+"Notice how simulation assertions are made here (with ``===``), as opposed to"
+" elaboration assertions in the previous example (with ``==``)."
+msgstr "请注意此处如何进行仿真时判断（使用 ``===``），而不是前面示例中的细化时判断（"
+"使用 ``==``）。"
+
+#: ../../SpinalHDL/Data types/Int.rst:237
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:245
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/Int.rst:246
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/Int.rst:248
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/Int.rst:249
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:251
+msgid "x > y"
+msgstr "x > y"
+
+#: ../../SpinalHDL/Data types/Int.rst:252
+msgid "Greater than"
+msgstr "大于"
+
+#: ../../SpinalHDL/Data types/Int.rst:254
+msgid "x >= y"
+msgstr "x >= y"
+
+#: ../../SpinalHDL/Data types/Int.rst:255
+msgid "Greater than or equal"
+msgstr "大于或等于"
+
+#: ../../SpinalHDL/Data types/Int.rst:257
+msgid "x < y"
+msgstr "x < y"
+
+#: ../../SpinalHDL/Data types/Int.rst:258
+msgid "Less than"
+msgstr "小于"
+
+#: ../../SpinalHDL/Data types/Int.rst:260
+msgid "x <= y"
+msgstr "x <= y"
+
+#: ../../SpinalHDL/Data types/Int.rst:261
+msgid "Less than or equal"
+msgstr "小于或等于"
+
+#: ../../SpinalHDL/Data types/Int.rst:282
+msgid ""
+"When comparing ``UInt`` values in a way that allows for \"wraparound\" "
+"behavior, meaning that the values will \"wrap around\" to the minimum value "
+"when they exceed the maximum value. The ``wrap`` method of ``UInt`` can be "
+"used as ``x.wrap < y`` for ``UInt`` variables ``x, y``, the result will be "
+"true if ``x`` is less than ``y`` in the wraparound sense."
+msgstr ""
+"当比较 ``UInt`` 值时，允许 \"环绕\" 行为，即当值超过最大值时，它们将\"环绕\" "
+"到最小值。在这种情况下，可以使用 ``UInt`` 的 wrap 方法。对于 ``UInt`` 变量 "
+"x、y，如果 x.wrap < y，则如果 x 在环绕意义上小于 y，结果为真。"
+
+#: ../../SpinalHDL/Data types/Int.rst:286
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/Int.rst:294
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/Int.rst:295
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/Int.rst:296
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:297
+msgid "x.asUInt"
+msgstr "x.asUInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:298
+msgid "Binary cast to UInt"
+msgstr "二进制转换为 UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:299 types/Int.rst:314
+msgid "UInt(w(x) bits)"
+msgstr "UInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:300
+msgid "x.asSInt"
+msgstr "x.asSInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:301
+msgid "Binary cast to SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:303
+msgid "x.asBools"
+msgstr "x.asBools"
+
+#: ../../SpinalHDL/Data types/Int.rst:304
+msgid "Cast into a array of Bool"
+msgstr "转换为 Bool 数组"
+
+#: ../../SpinalHDL/Data types/Int.rst:305
+msgid "Vec(Bool(), w(x))"
+msgstr "Vec(Bool(), w(x))"
+
+#: ../../SpinalHDL/Data types/Int.rst:306
+msgid "x.asBool"
+msgstr "x.asBool"
+
+#: ../../SpinalHDL/Data types/Int.rst:307
+msgid "Extract LSB of :code:`x`"
+msgstr "提取 :code:`x` 的 LSB"
+
+#: ../../SpinalHDL/Data types/Int.rst:308
+msgid "Bool(x.lsb)"
+msgstr "Bool(x.lsb)"
+
+#: ../../SpinalHDL/Data types/Int.rst:309
+msgid "S(x: T)"
+msgstr "S(x: T)"
+
+#: ../../SpinalHDL/Data types/Int.rst:310
+msgid "Cast a Data into a SInt"
+msgstr "将数据转换为 SInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:312
+msgid "U(x: T)"
+msgstr "U(x: T)"
+
+#: ../../SpinalHDL/Data types/Int.rst:313
+msgid "Cast a Data into an UInt"
+msgstr "将数据转换为 UInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:315
+msgid "x.intoSInt"
+msgstr "x.intoSInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:316
+msgid "Convert to SInt expanding sign bit"
+msgstr "转换为 SInt，扩展符号位"
+
+#: ../../SpinalHDL/Data types/Int.rst:317
+msgid "SInt(w(x) + 1 bits)"
+msgstr "SInt(w(x) + 1 bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:318
+msgid "myUInt.twoComplement(en: Bool)"
+msgstr "myUInt.twoComplement(en: Bool)"
+
+#: ../../SpinalHDL/Data types/Int.rst:319
+msgid ""
+"Generate two's complement of number if ``en`` is ``True``, unchanged "
+"otherwise. (``en`` makes result negative)"
+msgstr "如果 ``en`` 为真，则生成二进制补码的数值，否则不变。（``en`` 使结果为负数）"
+
+#: ../../SpinalHDL/Data types/Int.rst:320
+msgid "SInt(w(myUInt) + 1, bits)"
+msgstr "SInt(w(myUInt) + 1, bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:321
+msgid "mySInt.abs"
+msgstr "mySInt.abs"
+
+#: ../../SpinalHDL/Data types/Int.rst:322
+msgid "Return the absolute value as a UInt value"
+msgstr "以 UInt 值形式返回绝对值"
+
+#: ../../SpinalHDL/Data types/Int.rst:323 types/Int.rst:326
+msgid "UInt(w(mySInt) bits)"
+msgstr "UInt(w(mySInt) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:324
+msgid "mySInt.abs(en: Bool)"
+msgstr "mySInt.abs(en: Bool)"
+
+#: ../../SpinalHDL/Data types/Int.rst:325
+msgid ""
+"Return the absolute value as a UInt value when ``en`` is ``True``, otherwise"
+" just reinterpret bits as unsigned"
+msgstr "当 ``en`` 为真时，返回UInt类型的绝对值，否则，只需将位解释为无符号数。"
+
+#: ../../SpinalHDL/Data types/Int.rst:327
+msgid "mySInt.absWithSym"
+msgstr "mySInt.absWithSym"
+
+#: ../../SpinalHDL/Data types/Int.rst:328
+msgid ""
+"Return the absolute value of the UInt value with symmetric, shrink 1 bit"
+msgstr "返回对称的 UInt 值的绝对值，缩小 1 位"
+
+#: ../../SpinalHDL/Data types/Int.rst:329
+msgid "UInt(w(mySInt) - 1 bits)"
+msgstr "UInt(w(mySInt) - 1 bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:332
+msgid ""
+"To cast a ``Bool``, a ``Bits``, or an ``SInt`` into a ``UInt``, you can use "
+"``U(something)``. To cast things into an ``SInt``, you can use "
+"``S(something)``."
+msgstr ""
+"要将一个 ``Bool``、一个 ``Bits`` 或一个 ``SInt`` 转换为一个 ``UInt``，"
+"可以使用 ``U(something)``。要将东西转换为一个 ``SInt``，可以使用 "
+"``S(something)``。"
+
+#: ../../SpinalHDL/Data types/Int.rst:368
+msgid "Bit extraction"
+msgstr "位提取"
+
+#: ../../SpinalHDL/Data types/Int.rst:370
+msgid ""
+"All of the bit extraction operations can be used to read a bit / group of "
+"bits. Like in other HDLs the extraction operators can also be used to assign"
+" a part of a ``UInt`` / ``SInt`` ."
+msgstr "所有位提取操作均可用于读取一个位/一组位。与其他 HDL 一样，提取运算符也对 "
+"``UInt`` / ``SInt`` 的一部分赋值。"
+
+#: ../../SpinalHDL/Data types/Int.rst:380
+msgid "x(y: Int)"
+msgstr "x(y: Int)"
+
+#: ../../SpinalHDL/Data types/Int.rst:381
+msgid "Static bit access of y-th bit"
+msgstr "静态访问第 y 位"
+
+#: ../../SpinalHDL/Data types/Int.rst:383
+msgid "x(x: UInt)"
+msgstr "x(x: UInt)"
+
+#: ../../SpinalHDL/Data types/Int.rst:384
+msgid "Variable bit access of y-th bit"
+msgstr "访问第 y 位，这里y为可变的信号"
+
+#: ../../SpinalHDL/Data types/Int.rst:386
+msgid "x(offset: Int, width bits)"
+msgstr "x(offset: Int, width bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:387
+msgid "Fixed part select of fixed width, offset is LSB index"
+msgstr "固定地选择偏移量和宽度，``offset`` 为选择信号中LSB的索引"
+
+#: ../../SpinalHDL/Data types/Int.rst:388 types/Int.rst:391
+msgid "Bits(width bits)"
+msgstr "Bits(width bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:389
+msgid "x(offset: UInt, width bits)"
+msgstr "x(offset: UInt, width bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:390
+msgid "Variable part-select of fixed width, offset is LSB index"
+msgstr "选择偏移量可变和宽度固定的信号，``offset`` 为选择信号中LSB的索引 "
+"（可为另一信号）"
+
+#: ../../SpinalHDL/Data types/Int.rst:392
+msgid "x(range: Range)"
+msgstr "x(range: Range)"
+
+#: ../../SpinalHDL/Data types/Int.rst:393
+msgid "Access a :ref:`range <range>` of bits. Ex : myBits(4 downto 2)"
+msgstr "访问Bits的 :ref:`范围 <range>` 。例如：myBits(4 downto 2)"
+
+#: ../../SpinalHDL/Data types/Int.rst:394
+msgid "Bits(range.size bits)"
+msgstr "Bits(range.size bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:395
+msgid "x.subdivideIn(y slices, [strict: Boolean])"
+msgstr "x.subdivideIn(y slices, [strict: Boolean])"
+
+#: ../../SpinalHDL/Data types/Int.rst:396
+msgid "Subdivide x into y slices, y: Int"
+msgstr "将x分割为y片，y: Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:397
+msgid "Vec(Bits(...), y)"
+msgstr "Vec(Bits(...), y)"
+
+#: ../../SpinalHDL/Data types/Int.rst:398
+msgid "x.subdivideIn(y bits, [strict: Boolean])"
+msgstr "x.subdivideIn(y bits, [strict: Boolean])"
+
+#: ../../SpinalHDL/Data types/Int.rst:399
+msgid "Subdivide x in multiple slices of y bits, y: Int"
+msgstr "将 x 分割为 y 位的多个切片，y: Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:400
+msgid "Vec(Bits(y bit), ...)"
+msgstr "Vec(Bits(y bit), ...)"
+
+#: ../../SpinalHDL/Data types/Int.rst:401
+msgid "x.msb"
+msgstr "x.msb"
+
+#: ../../SpinalHDL/Data types/Int.rst:402
+msgid "Access most significant bit of x (highest index, sign bit for SInt)"
+msgstr "访问 x 的最高有效位（最高索引，SInt 的符号位）"
+
+#: ../../SpinalHDL/Data types/Int.rst:404
+msgid "x.lsb"
+msgstr "x.lsb"
+
+#: ../../SpinalHDL/Data types/Int.rst:405
+msgid "Access lowest significant bit of x (index 0)"
+msgstr "访问 x 的最低有效位（索引 0）"
+
+#: ../../SpinalHDL/Data types/Int.rst:407
+msgid "mySInt.sign"
+msgstr "mySInt.sign"
+
+#: ../../SpinalHDL/Data types/Int.rst:408
+msgid "Access most sign bit, only SInt"
+msgstr "访问最高符号位，仅适用于 SInt。"
+
+#: ../../SpinalHDL/Data types/Int.rst:413
+msgid "Some basic examples:"
+msgstr "一些基本示例："
+
+#: ../../SpinalHDL/Data types/Int.rst:442
+msgid "Subdivide details"
+msgstr "分割细节"
+
+#: ../../SpinalHDL/Data types/Int.rst:444
+msgid ""
+"Both overloads of ``subdivideIn`` have an optional parameter ``strict`` "
+"(i.e. ``subdivideIn(slices: SlicesCount, strict: Boolean = true)``). If "
+"``strict`` is ``true`` an error will be raised if the input could not be "
+"divided into equal parts. If set to ``false`` the last element may be "
+"smaller than the other (equal sized) elements."
+msgstr ""
+"两个 ``subdivideIn`` 函数的所有参数都有一个可选参数 ``strict`` 参数（即 "
+"``subdivideIn(slices: SlicesCount, strict: Boolean = true)`` ）。如果 "
+"``strict`` 为 ``true``，则如果输入无法等分，将引发错误。如果设置为 "
+"``false``，最后一个元素可能比其他（大小相等）元素小。"
+
+#: ../../SpinalHDL/Data types/Int.rst:470
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Data types/Int.rst:472
+msgid ""
+"In contrast to the bit extraction operations listed above it's not possible "
+"to use the return values to assign to the original signal."
+msgstr "与上面列出的位提取操作相反，上述函数不能使用其返回值给原始信号赋值。"
+
+#: ../../SpinalHDL/Data types/Int.rst:482
+msgid "x.getWidth"
+msgstr "x.getWidth"
+
+#: ../../SpinalHDL/Data types/Int.rst:483
+msgid "Return bitcount"
+msgstr "返回位数"
+
+#: ../../SpinalHDL/Data types/Int.rst:484 types/Int.rst:487
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:485
+msgid "x.high"
+msgstr "x.high"
+
+#: ../../SpinalHDL/Data types/Int.rst:486
+msgid "Return the index of the MSB (highest allowed index for Int)"
+msgstr "返回 MSB 的索引（对Int来说是允许的最高索引）"
+
+#: ../../SpinalHDL/Data types/Int.rst:488
+msgid "x.bitsRange"
+msgstr "x.bitsRange"
+
+#: ../../SpinalHDL/Data types/Int.rst:489
+msgid "Return the range (0 to x.high)"
+msgstr "返回范围（0 到 x.high）"
+
+#: ../../SpinalHDL/Data types/Int.rst:490 types/Int.rst:499
+msgid "Range"
+msgstr "范围"
+
+#: ../../SpinalHDL/Data types/Int.rst:491
+msgid "x.minValue"
+msgstr "x.minValue"
+
+#: ../../SpinalHDL/Data types/Int.rst:492
+msgid "Lowest possible value of x (e.g. 0 for UInt)"
+msgstr "x 的最低可能值（例如 UInt 为 0）"
+
+#: ../../SpinalHDL/Data types/Int.rst:493 types/Int.rst:496
+msgid "BigInt"
+msgstr "BigInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:494
+msgid "x.maxValue"
+msgstr "x.maxValue"
+
+#: ../../SpinalHDL/Data types/Int.rst:495
+msgid "Highest possible value of x"
+msgstr "x 的最大可能值"
+
+#: ../../SpinalHDL/Data types/Int.rst:497
+msgid "x.valueRange"
+msgstr "x.valueRange"
+
+#: ../../SpinalHDL/Data types/Int.rst:498
+msgid ""
+"Return the range from minimum to maximum possible value of x (x.minValue to "
+"x.maxValue)."
+msgstr "返回 x 的最小到最大可能值的范围（x.minValue 到 x.maxValue）。"
+
+#: ../../SpinalHDL/Data types/Int.rst:500
+msgid "x ## y"
+msgstr "x ## y"
+
+#: ../../SpinalHDL/Data types/Int.rst:501
+msgid "Concatenate, x->high, y->low"
+msgstr "连接Bits，x->高位，y->低位"
+
+#: ../../SpinalHDL/Data types/Int.rst:502
+msgid "Bits(w(x) + w(y) bits)"
+msgstr "Bits(w(x) + w(y) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:503
+msgid "x #* n"
+msgstr "x #* n"
+
+#: ../../SpinalHDL/Data types/Int.rst:504
+msgid "Repeat x n-times"
+msgstr "n次重复x并合并"
+
+#: ../../SpinalHDL/Data types/Int.rst:505
+msgid "Bits(w(x) * n bits)"
+msgstr "Bits(w(x) * n bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:506
+msgid "x @@ y"
+msgstr "x @@ y"
+
+#: ../../SpinalHDL/Data types/Int.rst:507
+msgid "Concatenate x:T with y:Bool/SInt/UInt"
+msgstr "将 x:T 与 y:Bool/SInt/UInt 连接"
+
+#: ../../SpinalHDL/Data types/Int.rst:508
+msgid "T(w(x) + w(y) bits)"
+msgstr "T(w(x) + w(y) bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:509
+msgid "x.resize(y)"
+msgstr "x.resize(y)"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "Return a resized copy of x, if enlarged, it is filled with zero"
+msgstr "返回 x 调整大小后的副本，如果位宽变大，则用零填充其他位"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "for UInt or filled with the sign for SInt, y: Int"
+msgstr "对于 UInt 或 SInt（用符号填充）操作, y: Int"
+
+#: ../../SpinalHDL/Data types/Int.rst:512
+msgid "T(y bits)"
+msgstr "T(y bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:513
+msgid "x.resized"
+msgstr "x.resized"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "Return a version of x which is allowed to be automatically"
+msgstr "返回自动位宽调整后的 x"
+
+#: ../../SpinalHDL/Data types/Int.rst
+msgid "resized where needed"
+msgstr "根据需要调整大小"
+
+#: ../../SpinalHDL/Data types/Int.rst:517
+msgid "x.expand"
+msgstr "x.expand"
+
+#: ../../SpinalHDL/Data types/Int.rst:518
+msgid "Return x with 1 bit expand"
+msgstr "返回 x 并进行 1 位扩展"
+
+#: ../../SpinalHDL/Data types/Int.rst:519
+msgid "T(w(x)+1 bits)"
+msgstr "T(w(x)+1 bits)"
+
+#: ../../SpinalHDL/Data types/Int.rst:520
+msgid "x.getZero"
+msgstr "x.getZero"
+
+#: ../../SpinalHDL/Data types/Int.rst:521
+msgid ""
+"Return a new instance of type T that is assigned a constant value of zeros "
+"the same width as x."
+msgstr "返回类型 T 的新实例，该实例被分配与 x 相同宽度的零值（常量）。"
+
+#: ../../SpinalHDL/Data types/Int.rst:522
+msgid "T(0, w(x) bits).clearAll()"
+msgstr "T(0, w(x) bits).clearAll()"
+
+#: ../../SpinalHDL/Data types/Int.rst:523
+msgid "x.getAllTrue"
+msgstr "x.getAllTrue"
+
+#: ../../SpinalHDL/Data types/Int.rst:524
+msgid ""
+"Return a new instance of type T that is assigned a constant value of ones "
+"the same width as x."
+msgstr "返回类型 T 的新实例，该实例被分配了与 x 宽度相同的常量值。"
+
+#: ../../SpinalHDL/Data types/Int.rst:525
+msgid "T(w(x) bits).setAll()"
+msgstr "T(w(x) bits).setAll()"
+
+#: ../../SpinalHDL/Data types/Int.rst:528
+msgid ""
+"`validRange` can only be used for types where the minimum and maximum values"
+" fit into a signed 32-bit integer. (This is a limitation given by the Scala "
+"``scala.collection.immutable.Range`` type which uses `Int`)"
+msgstr ""
+"`validRange` 只能用于最小值和最大值能够保存在32 位有符号整数的情况下。 （"
+"这是由于 Scala ``scala.collection.immutable.Range`` 类型使用 `Int` "
+"作为范围描述）"
+
+#: ../../SpinalHDL/Data types/Int.rst:547
+msgid "FixPoint operations"
+msgstr "定点小数操作"
+
+#: ../../SpinalHDL/Data types/Int.rst:549
+msgid "For fixpoint, we can divide it into two parts:"
+msgstr "对于定点小数，我们可以将其分为两部分："
+
+#: ../../SpinalHDL/Data types/Int.rst:551
+msgid "Lower bit operations (rounding methods)"
+msgstr "低位运算（舍入方法）"
+
+#: ../../SpinalHDL/Data types/Int.rst:552
+msgid "High bit operations (saturation operations)"
+msgstr "高位运算（饱和运算）"
+
+#: ../../SpinalHDL/Data types/Int.rst:555
+msgid "Lower bit operations"
+msgstr "低位运算"
+
+#: ../../SpinalHDL/Data types/Int.rst:559
+msgid "About Rounding: https://en.wikipedia.org/wiki/Rounding"
+msgstr "关于舍入运算: https://en.wikipedia.org/wiki/Rounding"
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "SpinalHDL-Name"
+msgstr "SpinalHDL中的名称"
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Wikipedia-Name"
+msgstr "维基百科中的名称"
+
+#: ../../SpinalHDL/Data types/Int.rst:562 types/Int.rst:620
+msgid "API"
+msgstr "API"
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Mathematic Algorithm"
+msgstr "数学算法描述"
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "return(align=false)"
+msgstr "返回类型（align=false）"
+
+#: ../../SpinalHDL/Data types/Int.rst:562
+msgid "Supported"
+msgstr "支持情况"
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "FLOOR"
+msgstr "FLOOR"
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "RoundDown"
+msgstr "RoundDown"
+
+#: ../../SpinalHDL/Data types/Int.rst:564 types/Int.rst:622
+msgid "floor"
+msgstr "floor"
+
+#: ../../SpinalHDL/Data types/Int.rst:564
+msgid "floor(x)"
+msgstr "floor(x)"
+
+#: ../../SpinalHDL/Data types/Int.rst:564 types/Int.rst:565 types/Int.rst:622
+#: types/Int.rst:623
+msgid "w(x)-n   bits"
+msgstr "w(x)-n bits"
+
+#: ../../SpinalHDL/Data types/Int.rst:564 types/Int.rst:565 types/Int.rst:566
+#: types/Int.rst:567 types/Int.rst:568 types/Int.rst:569 types/Int.rst:570
+#: types/Int.rst:571
+msgid "Yes"
+msgstr "是"
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "FLOORTOZERO"
+msgstr "FLOORTOZERO"
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "RoundToZero"
+msgstr "RoundToZero"
+
+#: ../../SpinalHDL/Data types/Int.rst:565 types/Int.rst:623
+msgid "floorToZero"
+msgstr "floorToZero"
+
+#: ../../SpinalHDL/Data types/Int.rst:565
+msgid "sign*floor(abs(x))"
+msgstr "sign*floor(abs(x))"
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "CEIL"
+msgstr "CEIL"
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "RoundUp"
+msgstr "RoundUp"
+
+#: ../../SpinalHDL/Data types/Int.rst:566 types/Int.rst:624
+msgid "ceil"
+msgstr "ceil"
+
+#: ../../SpinalHDL/Data types/Int.rst:566
+msgid "ceil(x)"
+msgstr "ceil(x)"
+
+#: ../../SpinalHDL/Data types/Int.rst:566 types/Int.rst:567 types/Int.rst:568
+#: types/Int.rst:569 types/Int.rst:570 types/Int.rst:571 types/Int.rst:624
+#: types/Int.rst:625 types/Int.rst:626 types/Int.rst:627 types/Int.rst:628
+#: types/Int.rst:629 types/Int.rst:630
+msgid "w(x)-n+1 bits"
+msgstr "w(x)-n+1 bits"
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "CEILTOINF"
+msgstr "CEILTOINF"
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "RoundToInf"
+msgstr "RoundToInf"
+
+#: ../../SpinalHDL/Data types/Int.rst:567 types/Int.rst:625
+msgid "ceilToInf"
+msgstr "ceilToInf"
+
+#: ../../SpinalHDL/Data types/Int.rst:567
+msgid "sign*ceil(abs(x))"
+msgstr "sign*ceil(abs(x))"
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "ROUNDUP"
+msgstr "ROUNDUP"
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "RoundHalfUp"
+msgstr "RoundHalfUp"
+
+#: ../../SpinalHDL/Data types/Int.rst:568 types/Int.rst:626
+msgid "roundUp"
+msgstr "roundUp"
+
+#: ../../SpinalHDL/Data types/Int.rst:568
+msgid "floor(x+0.5)"
+msgstr "floor(x+0.5)"
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "ROUNDDOWN"
+msgstr "ROUNDDOWN"
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "RoundHalfDown"
+msgstr "RoundHalfDown"
+
+#: ../../SpinalHDL/Data types/Int.rst:569 types/Int.rst:627
+msgid "roundDown"
+msgstr "roundDown"
+
+#: ../../SpinalHDL/Data types/Int.rst:569
+msgid "ceil(x-0.5)"
+msgstr "ceil(x-0.5)"
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "ROUNDTOZERO"
+msgstr "ROUNDTOZERO"
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "RoundHalfToZero"
+msgstr "RoundHalfToZero"
+
+#: ../../SpinalHDL/Data types/Int.rst:570 types/Int.rst:629
+msgid "roundToZero"
+msgstr "roundToZero"
+
+#: ../../SpinalHDL/Data types/Int.rst:570
+msgid "sign*ceil(abs(x)-0.5)"
+msgstr "sign*ceil(abs(x)-0.5)"
+
+#: ../../SpinalHDL/Data types/Int.rst:571 types/Int.rst:584 types/Int.rst:585
+#: types/Int.rst:588
+msgid "ROUNDTOINF"
+msgstr "ROUNDTOINF"
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+msgid "RoundHalfToInf"
+msgstr "RoundHalfToInf"
+
+#: ../../SpinalHDL/Data types/Int.rst:571 types/Int.rst:628
+msgid "roundToInf"
+msgstr "roundToInf"
+
+#: ../../SpinalHDL/Data types/Int.rst:571
+msgid "sign*floor(abs(x)+0.5)"
+msgstr "sign*floor(abs(x)+0.5)"
+
+#: ../../SpinalHDL/Data types/Int.rst:572 types/Int.rst:586
+msgid "ROUNDTOEVEN"
+msgstr "ROUNDTOEVEN"
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+msgid "RoundHalfToEven"
+msgstr "RoundHalfToEven"
+
+#: ../../SpinalHDL/Data types/Int.rst:572
+msgid "roundToEven"
+msgstr "roundToEven"
+
+#: ../../SpinalHDL/Data types/Int.rst:572 types/Int.rst:573
+msgid "No"
+msgstr "不支持"
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "ROUNDTOODD"
+msgstr "ROUNDTOODD"
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "RoundHalfToOdd"
+msgstr "RoundHalfToOdd"
+
+#: ../../SpinalHDL/Data types/Int.rst:573
+msgid "roundToOdd"
+msgstr "roundToOdd"
+
+#: ../../SpinalHDL/Data types/Int.rst:577
+msgid ""
+"The **RoundToEven** and **RoundToOdd** modes are very special, and are used "
+"in some big data statistical fields with high accuracy concerns, SpinalHDL "
+"doesn't support them yet."
+msgstr ""
+"**RoundToEven** 和 **RoundToOdd** "
+"模式非常特殊，用于一些精度要求较高的大数据统计领域，SpinalHDL 尚不支持。"
+
+#: ../../SpinalHDL/Data types/Int.rst:579
+msgid ""
+"You will find `ROUNDUP`, `ROUNDDOWN`, `ROUNDTOZERO`, `ROUNDTOINF`, "
+"`ROUNDTOEVEN`, `ROUNTOODD` are very close in behavior, `ROUNDTOINF` is the "
+"most common. The behavior of rounding in different programming languages may"
+" be different."
+msgstr ""
+"你会发现 `ROUNDUP`、`ROUNDDOWN`、`ROUNDTOZERO`、`ROUNDTOINF`、`ROUNDTOEVEN`、"
+"`ROUNTOODD` 在行为上非常接近，`ROUNDTOINF` "
+"是最常见的。不同编程语言中的舍入行为可能不同。"
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "Programming language"
+msgstr "编程语言"
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "default-RoundType"
+msgstr "默认舍入类型"
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Data types/Int.rst:582
+msgid "comments"
+msgstr "评论"
+
+#: ../../SpinalHDL/Data types/Int.rst:584
+msgid "Matlab"
+msgstr "Matlab"
+
+#: ../../SpinalHDL/Data types/Int.rst:584 types/Int.rst:585 types/Int.rst:588
+msgid "round(1.5)=2,round(2.5)=3;round(-1.5)=-2,round(-2.5)=-3"
+msgstr "round(1.5)=2,round(2.5)=3;round(-1.5)=-2,round(-2.5)=-3"
+
+#: ../../SpinalHDL/Data types/Int.rst:584 types/Int.rst:585 types/Int.rst:588
+msgid "round to ±Infinity"
+msgstr "四舍五入至±无穷大"
+
+#: ../../SpinalHDL/Data types/Int.rst:585
+msgid "python2"
+msgstr "python2"
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "python3"
+msgstr "蟒蛇3"
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "round(1.5)=round(2.5)=2;  round(-1.5)=round(-2.5)=-2"
+msgstr "round(1.5)=round(2.5)=2;  round(-1.5)=round(-2.5)=-2"
+
+#: ../../SpinalHDL/Data types/Int.rst:586
+msgid "close to Even"
+msgstr "向偶数舍入"
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "Scala.math"
+msgstr "Scala.math"
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "ROUNDTOUP"
+msgstr "ROUNDTOUP"
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "round(1.5)=2,round(2.5)=3;round(-1.5)=-1,round(-2.5)=-2"
+msgstr "round(1.5)=2,round(2.5)=3;round(-1.5)=-1,round(-2.5)=-2"
+
+#: ../../SpinalHDL/Data types/Int.rst:587
+msgid "always to +Infinity"
+msgstr "永远向正无穷舍入"
+
+#: ../../SpinalHDL/Data types/Int.rst:588
+msgid "SpinalHDL"
+msgstr "SpinalHDL"
+
+#: ../../SpinalHDL/Data types/Int.rst:592
+msgid ""
+"In SpinalHDL `ROUNDTOINF` is the default RoundType (``round = roundToInf``)"
+msgstr "在 SpinalHDL 中，`ROUNDTOINF` 是默认的舍入类型 (``round = roundToInf``)"
+
+#: ../../SpinalHDL/Data types/Int.rst:615
+msgid ""
+"Only ``floor`` and ``floorToZero`` work without the ``align`` option; they "
+"do not need a carry bit. Other rounding operations default to using a carry "
+"bit."
+msgstr ""
+"只有 ``floor`` 和 ``floorToZero`` 可以在没有 ``align`` "
+"选项的情况下工作；他们不需要进位位。其他舍入操作默认使用进位位。"
+
+#: ../../SpinalHDL/Data types/Int.rst:617
+msgid "**round Api**"
+msgstr "**round Api**"
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "Return(align=false)"
+msgstr "返回类型（align=false）"
+
+#: ../../SpinalHDL/Data types/Int.rst:620
+msgid "Return(align=true)"
+msgstr "返回类型（align=true）"
+
+#: ../../SpinalHDL/Data types/Int.rst:622 types/Int.rst:624 types/Int.rst:626
+#: types/Int.rst:627 types/Int.rst:630
+msgid "Both"
+msgstr "均支持"
+
+#: ../../SpinalHDL/Data types/Int.rst:622 types/Int.rst:623 types/Int.rst:624
+#: types/Int.rst:625 types/Int.rst:626 types/Int.rst:627 types/Int.rst:628
+#: types/Int.rst:629 types/Int.rst:630
+msgid "w(x)-n bits"
+msgstr "w(x)-n bits"
+
+#: ../../SpinalHDL/Data types/Int.rst:623 types/Int.rst:625 types/Int.rst:628
+#: types/Int.rst:629
+msgid "SInt"
+msgstr "SInt"
+
+#: ../../SpinalHDL/Data types/Int.rst:623
+msgid "equal to floor in UInt"
+msgstr "等于 UInt 类型的下限"
+
+#: ../../SpinalHDL/Data types/Int.rst:625
+msgid "equal to ceil in UInt"
+msgstr "等于 UInt 类型的 ceil值"
+
+#: ../../SpinalHDL/Data types/Int.rst:626
+msgid "simple for HW"
+msgstr "硬件实现简单"
+
+#: ../../SpinalHDL/Data types/Int.rst:628
+msgid "most Common"
+msgstr "最常使用"
+
+#: ../../SpinalHDL/Data types/Int.rst:629
+msgid "equal to roundDown in UInt"
+msgstr "等于 UInt 类型的roundDown"
+
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "round"
+msgstr "round"
+
+#: ../../SpinalHDL/Data types/Int.rst:630
+msgid "SpinalHDL chose roundToInf"
+msgstr "SpinalHDL 中等效于 roundToInf"
+
+#: ../../SpinalHDL/Data types/Int.rst:634
+msgid ""
+"Although ``roundToInf`` is very common, ``roundUp`` has the least cost and "
+"good timing, with almost no performance loss. As a result, ``roundUp`` is "
+"strongly recommended for production use."
+msgstr ""
+"虽然 ``roundToInf`` 很常见，但 ``roundUp`` "
+"的成本最低，时序也好，几乎没有性能损失。因此，强烈建议在生产环境中使用 "
+"``roundUp`` 。"
+
+#: ../../SpinalHDL/Data types/Int.rst:638
+msgid "High bit operations"
+msgstr "高位操作"
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "function"
+msgstr "函数"
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Operation"
+msgstr "操作"
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Positive-Op"
+msgstr "正向操作"
+
+#: ../../SpinalHDL/Data types/Int.rst:643
+msgid "Negative-Op"
+msgstr "负向操作"
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "sat"
+msgstr "sat"
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "Saturation"
+msgstr "饱和化"
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "when(Top[w-1, w-n].orR) set maxValue"
+msgstr "当(Top[w-1, w-n].orR)为真时设置为maxValue"
+
+#: ../../SpinalHDL/Data types/Int.rst:645
+msgid "When(Top[w-1, w-n].andR) set minValue"
+msgstr "当(Top[w-1, w-n].andR)为真时设置为 minValue"
+
+#: ../../SpinalHDL/Data types/Int.rst:646
+msgid "trim"
+msgstr "trim"
+
+#: ../../SpinalHDL/Data types/Int.rst:646
+msgid "Discard"
+msgstr "丢弃"
+
+#: ../../SpinalHDL/Data types/Int.rst:646 types/Int.rst:647
+msgid "N/A"
+msgstr "不适用"
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "symmetry"
+msgstr "symmetry"
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "Symmetric"
+msgstr "获取对称值"
+
+#: ../../SpinalHDL/Data types/Int.rst:647
+msgid "minValue = -maxValue"
+msgstr "最小值 = -最大值"
+
+#: ../../SpinalHDL/Data types/Int.rst:650
+msgid "Symmetric is only valid for ``SInt``."
+msgstr "对称仅对 ``SInt`` 有效。"
+
+#: ../../SpinalHDL/Data types/Int.rst:663
+msgid "fixTo function"
+msgstr "fixTo 函数"
+
+#: ../../SpinalHDL/Data types/Int.rst:665
+msgid "Two ways are provided in ``UInt``/``SInt`` to do fixpoint:"
+msgstr "``UInt``/``SInt`` 中提供了两种方法来实现定点小数位宽变化："
+
+#: ../../SpinalHDL/Data types/Int.rst:669
+msgid ""
+"``fixTo`` is strongly recommended in your RTL work, you don't need to handle"
+" carry bit alignment and bit width calculations manually like **Way1** in "
+"the above diagram."
+msgstr "在 RTL 工作中强烈建议使用 ``fixTo`` 函数，您不需要像上图中的 **Way1** "
+"那样手动处理进位对齐和位宽计算。"
+
+#: ../../SpinalHDL/Data types/Int.rst:671
+msgid "Factory Fix function with Auto Saturation:"
+msgstr "带自动饱和功能的定点数生成函数："
+
+#: ../../SpinalHDL/Data types/Int.rst:674
+msgid "Function"
+msgstr "函数"
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "fixTo(section, roundType, symmetric)"
+msgstr "fixTo(section, roundType, symmetric)"
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "Factory FixFunction"
+msgstr "定点数生成"
+
+#: ../../SpinalHDL/Data types/Int.rst:676
+msgid "section.size bits"
+msgstr "section.size bits"
+
+#~ msgid ""
+#~ "The ``UInt``/``SInt`` type corresponds to a vector of bits that can be used "
+#~ "for signed/unsigned integer arithmetic."
+#~ msgstr "``UInt``/``SInt`` 类型对应于可用于有符号/无符号整数算术的位向量。"
+
+#~ msgid "UInt"
+#~ msgstr "单位"
+
+#~ msgid ""
+#~ "Create an unsigned/signed integer assigned with 'value' (Base : 'h', 'd', "
+#~ "'o', 'b')"
+#~ msgstr "创建一个分配有“value”的无符号/有符号整数（基数：“h”、“d”、“o”、“b”）"
+
+#~ msgid "``x rotateLeft y`` and ``x rotateRight y`` are also valid syntax."
+#~ msgstr "“xrotateLeft y”和“xrotateRight y”也是有效的语法。"
+
+#~ msgid ""
+#~ "Notice the difference between ``x >> 2``:T(w(x)-2) and ``x >> "
+#~ "U(2)``:T(w(x))."
+#~ msgstr "注意 ``x >> 2``:T(w(x)-2) 和 ``x >> U(2)``:T(w(x)) 之间的区别。"
+
+#~ msgid "Addition by sat carry bit"
+#~ msgstr "通过 sat 进位位进行加法"
+
+#~ msgid "Subtraction by sat carry bit"
+#~ msgstr "通过 sat 进位位进行减法"
+
+#~ msgid "x(y)"
+#~ msgstr "x(y)"
+
+#~ msgid "Readbit, y : Int/UInt"
+#~ msgstr "读取位，y：Int/UInt"
+
+#~ msgid "Read bitfield, offset: UInt, width: Int"
+#~ msgstr "Read bitfield, offset: UInt, width: Int"
+
+#~ msgid "x(y) := z"
+#~ msgstr "x(y) := z"
+
+#~ msgid "x(offset, width) := z"
+#~ msgstr "x(offset, width) := z"
+
+#~ msgid "Assign bitfield, offset: UInt, width: Int"
+#~ msgstr "分配位域，偏移量：UInt，宽度：Int"
+
+#~ msgid "x(\\ :ref:`range <range>`\\ ) := z"
+#~ msgstr "x(\\ :ref:`范围 <范围>`\\ ) := z"
+
+#~ msgid "Assign a range of bit. Ex : myBits(4 downto 2) := U\"010\""
+#~ msgstr "指定一个位范围。例如：myBits(4 downto 2) := U\"010\""
+
+#~ msgid "Return the most significant bit"
+#~ msgstr "返回最高有效位"
+
+#~ msgid "Return the least significant bit"
+#~ msgstr "返回最低有效位"
+
+#~ msgid "Vec(T, w(x)/y)"
+#~ msgstr "Vec(T, w(x)/y)"
+
+#~ msgid "Use the two's complement to transform an UInt into an SInt"
+#~ msgstr "使用二进制补码将 UInt 转换为 SInt"
+
+#~ msgid "Return most significant bit"
+#~ msgstr "返回最高有效位"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po
new file mode 100644
index 00000000000..d6131e968bb
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po	
@@ -0,0 +1,242 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesvec/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../SpinalHDL/Data types/Vec.rst:7
+msgid "Vec"
+msgstr "Vec"
+
+#: ../../SpinalHDL/Data types/Vec.rst:10 types/Vec.rst:24 types/Vec.rst:72
+#: types/Vec.rst:99 types/Vec.rst:121 types/Vec.rst:147
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/Vec.rst:12
+msgid ""
+"A ``Vec`` is a composite type that defines a group of indexed signals (of "
+"any SpinalHDL basic type) under a single name."
+msgstr "``Vec`` 是一种复合类型，它在一个变量中定义一组可索引的信号（任何 SpinalHDL "
+"基本类型）。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:15 types/Vec.rst:23
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/Vec.rst:17
+msgid "The syntax to declare a vector is as follows:"
+msgstr "声明向量的语法如下："
+
+#: ../../SpinalHDL/Data types/Vec.rst:25
+msgid "Vec.fill(size: Int)(type: Data)"
+msgstr "Vec.fill(size: Int)(type: Data)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:26
+msgid "Create a vector of ``size`` elements of type ``Data``"
+msgstr "创建一个包含 ``size`` 个元素的 ``Data`` 类型向量"
+
+#: ../../SpinalHDL/Data types/Vec.rst:27
+msgid "Vec(x, y, ...)"
+msgstr "Vec(x, y, ...)"
+
+#: ../../SpinalHDL/Data types/Vec.rst
+msgid "Create a vector where indexes point to the provided elements."
+msgstr "创建一个向量，其中索引指向提供的元素。"
+
+#: ../../SpinalHDL/Data types/Vec.rst
+msgid "Does not create new hardware signals."
+msgstr "不会创建新的硬件信号。"
+
+#: ../../SpinalHDL/Data types/Vec.rst
+msgid "This constructor supports mixed element width."
+msgstr "此构造函数支持混合宽度的元素。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:34
+msgid "Examples"
+msgstr "示例"
+
+#: ../../SpinalHDL/Data types/Vec.rst:61
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Vec.rst:63
+msgid "The following operators are available for the ``Vec`` type:"
+msgstr "以下运算符可用于 ``Vec`` 类型："
+
+#: ../../SpinalHDL/Data types/Vec.rst:66
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/Vec.rst:71 types/Vec.rst:98 types/Vec.rst:120
+#: types/Vec.rst:146
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/Vec.rst:73
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Vec.rst:74
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/Vec.rst:75
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/Vec.rst:76 types/Vec.rst:79 types/Vec.rst:157
+#: types/Vec.rst:160
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/Vec.rst:77
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/Vec.rst:78
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/Vec.rst:93
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/Vec.rst:100 types/Vec.rst:122 types/Vec.rst:148
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/Vec.rst:101
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/Vec.rst:102
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/Vec.rst:103
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:114
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Data types/Vec.rst:123
+msgid "x.getBitsWidth"
+msgstr "x.getBitsWidth"
+
+#: ../../SpinalHDL/Data types/Vec.rst:124
+msgid "Return the full size of the Vec"
+msgstr "返回 Vec 的完整大小"
+
+#: ../../SpinalHDL/Data types/Vec.rst:125
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Data types/Vec.rst:137
+msgid "Lib helper functions"
+msgstr "库辅助函数"
+
+#: ../../SpinalHDL/Data types/Vec.rst:140
+msgid ""
+"You need to import ``import spinal.lib._`` to put these functions in scope."
+msgstr "您需要以 ``import spinal.lib._`` 导入库，以将这些函数置于作用域中。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:149
+msgid "x.sCount(condition: T => Bool)"
+msgstr "x.sCount(condition: T => Bool)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:150
+msgid "Count the number of occurence matching a given condition in the Vec."
+msgstr "计算 Vec 中与给定条件匹配的次数。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:151 types/Vec.rst:154 types/Vec.rst:163
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../SpinalHDL/Data types/Vec.rst:152
+msgid "x.sCount(value: T)"
+msgstr "x.sCount(value: T)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:153
+msgid "Count the number of occurence of a value in the Vec."
+msgstr "计算 Vec 中某个值出现的次数。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:155
+msgid "x.sExists(condition: T => Bool)"
+msgstr "x.sExists(condition: T => Bool)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:156
+msgid "Check if there is a matching condition in the Vec."
+msgstr "检查Vec中是否存在匹配条件的元素。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:158
+msgid "x.sContains(value: T)"
+msgstr "x.sContains(value: T)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:159
+msgid "Check if there is an element with a given value present in the Vec."
+msgstr "检查 Vec 中是否存在具有给定值的元素。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:161
+msgid "x.sFindFirst(condition: T => Bool)"
+msgstr "x.sFindFirst(condition: T => Bool)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:162
+msgid ""
+"Find the first element matching the given condition in the Vec, return the "
+"index of that element."
+msgstr "查找 Vec 中与给定条件匹配的第一个元素，返回该元素的索引。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:164
+msgid "x.reduceBalancedTree(op: (T, T) => T)"
+msgstr "x.reduceBalancedTree(op: (T, T) => T)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:165
+msgid ""
+"Balanced reduce function, to try to minimize the depth of the resulting "
+"circuit. ``op`` should be commutative and associative."
+msgstr "具有自动平衡功能的reduce函数，尽量减少生成电路的深度。 ``op`` "
+"应该是具有可交换性和可结合性的。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:166
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Data types/Vec.rst:167
+msgid "x.shuffle(indexMapping: Int => Int)"
+msgstr "x.shuffle(indexMapping: Int => Int)"
+
+#: ../../SpinalHDL/Data types/Vec.rst:168
+msgid ""
+"Shuffle the Vec using a function that maps the old indexes to new ones."
+msgstr "使用将旧索引映射到新索引的函数对 Vec 进行混洗（shuffle）。"
+
+#: ../../SpinalHDL/Data types/Vec.rst:169
+msgid "Vec[T]"
+msgstr "Vec[T]"
+
+#: ../../SpinalHDL/Data types/Vec.rst:191
+msgid ""
+"The sXXX prefix is used to disambiguate with respect to identically named "
+"Scala functions that accept a lambda function as argument."
+msgstr "sXXX 前缀用于消除使用 lambda 函数作为参数的同名 Scala 函数带来的歧义。"
+
+#~ msgid "Vec(type: Data, size: Int)"
+#~ msgstr "Vec（类型：数据，大小：Int）"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bits.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bits.po
new file mode 100644
index 00000000000..325fada60ec
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bits.po	
@@ -0,0 +1,768 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesbits/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Data types/bits.rst:4
+msgid "Bits"
+msgstr "位"
+
+#: ../../SpinalHDL/Data types/bits.rst:6
+msgid ""
+"The ``Bits`` type is a vector of bits without conveying any arithmetic "
+"meaning."
+msgstr "``Bits`` 类型表示多位向量，不传达任何算术含义。"
+
+#: ../../SpinalHDL/Data types/bits.rst:9
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/bits.rst:11
+msgid ""
+"The syntax to declare a bit vector is as follows (everything between [] is "
+"optional):"
+msgstr "声明位向量的语法如下（[]之间的所有内容都是可选的）："
+
+#: ../../SpinalHDL/Data types/bits.rst:17
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Data types/bits.rst:18 types/bits.rst:82 types/bits.rst:182
+#: types/bits.rst:207 types/bits.rst:260 types/bits.rst:358
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/bits.rst:19
+msgid "Bits [()]"
+msgstr "Bits [()]"
+
+#: ../../SpinalHDL/Data types/bits.rst:20
+msgid ""
+"Create Bits, bit count is inferred from the widest assignment statement "
+"after construction"
+msgstr "创建Bits，其位数是从构造后最宽的赋值语句推断出来的"
+
+#: ../../SpinalHDL/Data types/bits.rst:22 types/bits.rst:393
+msgid "Bits(x bits)"
+msgstr "Bits(x bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:23
+msgid "Create Bits with x bits"
+msgstr "创建具有 x 位的Bits"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "B(value: Int[, x bits])"
+msgstr "B(value: Int[, x bits])"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "B(value: BigInt[, x bits])"
+msgstr "B(value: BigInt[, x bits])"
+
+#: ../../SpinalHDL/Data types/bits.rst:26
+msgid "Create Bits with x bits assigned with 'value'"
+msgstr "创建 x 位Bits，且赋值为'value'"
+
+#: ../../SpinalHDL/Data types/bits.rst:27
+msgid "B\"[[size']base]value\""
+msgstr "B\"[[size']base]value\""
+
+#: ../../SpinalHDL/Data types/bits.rst:28
+msgid "Create Bits assigned with 'value' (base: 'h', 'd', 'o', 'b')"
+msgstr "创建Bits并赋值为'value'（基数：“h”、“d”、“o”、“b”）"
+
+#: ../../SpinalHDL/Data types/bits.rst:29
+msgid "B([x bits,] elements: Element*)"
+msgstr "B([x bits,] elements: Element*)"
+
+#: ../../SpinalHDL/Data types/bits.rst:30
+msgid ""
+"Create Bits assigned with the value specified by :ref:`elements <element>`"
+msgstr "创建并赋值由 :ref:`elements <element>` 指定值的Bits"
+
+#: ../../SpinalHDL/Data types/bits.rst:53
+msgid ""
+"When inferring the width of a ``Bits`` the sizes of assigned values still "
+"have to match the final size of the signal:"
+msgstr "当推断 ``Bits`` 的宽度时，赋予值的宽度仍然必须与信号的最终宽度相匹配："
+
+#: ../../SpinalHDL/Data types/bits.rst:70
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bits.rst:72
+msgid "The following operators are available for the ``Bits`` type:"
+msgstr "以下运算符可用于 ``Bits`` 类型："
+
+#: ../../SpinalHDL/Data types/bits.rst:75
+msgid "Logic"
+msgstr "逻辑运算"
+
+#: ../../SpinalHDL/Data types/bits.rst:81 types/bits.rst:181
+#: types/bits.rst:206 types/bits.rst:259 types/bits.rst:357
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bits.rst:83 types/bits.rst:183
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bits.rst:84
+msgid "~x"
+msgstr "~x"
+
+#: ../../SpinalHDL/Data types/bits.rst:85
+msgid "Bitwise NOT"
+msgstr "按位非"
+
+#: ../../SpinalHDL/Data types/bits.rst:86 types/bits.rst:114
+#: types/bits.rst:128 types/bits.rst:132 types/bits.rst:136 types/bits.rst:140
+#: types/bits.rst:211 types/bits.rst:226 types/bits.rst:374 types/bits.rst:389
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:87
+msgid "x & y"
+msgstr "x & y"
+
+#: ../../SpinalHDL/Data types/bits.rst:88
+msgid "Bitwise AND"
+msgstr "按位与"
+
+#: ../../SpinalHDL/Data types/bits.rst:89 types/bits.rst:92 types/bits.rst:95
+msgid "Bits(w(xy) bits)"
+msgstr "Bits(w(xy) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:90
+msgid "x | y"
+msgstr "x | y"
+
+#: ../../SpinalHDL/Data types/bits.rst:91
+msgid "Bitwise OR"
+msgstr "按位或"
+
+#: ../../SpinalHDL/Data types/bits.rst:93
+msgid "x ^ y"
+msgstr "x ^ y"
+
+#: ../../SpinalHDL/Data types/bits.rst:94
+msgid "Bitwise XOR"
+msgstr "按位异或"
+
+#: ../../SpinalHDL/Data types/bits.rst:96
+msgid "x.xorR"
+msgstr "x.xorR"
+
+#: ../../SpinalHDL/Data types/bits.rst:97
+msgid "XOR all bits of x"
+msgstr "对 x 的所有位进行异或"
+
+#: ../../SpinalHDL/Data types/bits.rst:98 types/bits.rst:101
+#: types/bits.rst:104 types/bits.rst:186 types/bits.rst:189 types/bits.rst:264
+#: types/bits.rst:267 types/bits.rst:285 types/bits.rst:288
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/bits.rst:99
+msgid "x.orR"
+msgstr "x.orR"
+
+#: ../../SpinalHDL/Data types/bits.rst:100
+msgid "OR all bits of x"
+msgstr "对x 的所有位做或运算"
+
+#: ../../SpinalHDL/Data types/bits.rst:102
+msgid "x.andR"
+msgstr "x.andR"
+
+#: ../../SpinalHDL/Data types/bits.rst:103
+msgid "AND all bits of x"
+msgstr "对x 的所有位做与运算"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "y = 1 // Int"
+msgstr "y = 1 // 整数"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "x \\>\\> y"
+msgstr "x \\>\\> y"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift right, y: Int"
+msgstr "逻辑右移，y: Int"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Result may reduce width"
+msgstr "结果的宽度可能会变少"
+
+#: ../../SpinalHDL/Data types/bits.rst:109
+msgid "Bits(w(x) - y bits)"
+msgstr "Bits(w(x) - y bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "y = U(1) // UInt"
+msgstr "y = U(1) // UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift right, y: UInt"
+msgstr "逻辑右移，y: UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Result is same width"
+msgstr "结果宽度相同"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "x \\<\\< y"
+msgstr "x \\<\\< y"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift left, y: Int"
+msgstr "逻辑左移，y: Int"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Result may increase width"
+msgstr "结果的宽度可能会增加"
+
+#: ../../SpinalHDL/Data types/bits.rst:119
+msgid "Bits(w(x) + y bits)"
+msgstr "Bits(w(x) + y bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift left, y: UInt"
+msgstr "逻辑左移，y: UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:124
+msgid "Bits(w(x) + max(y) bits)"
+msgstr "Bits(w(x) + max(y) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:125
+msgid "x \\|\\>\\> y"
+msgstr "x \\|\\>\\> y"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift right, y: Int/UInt"
+msgstr "逻辑右移，y: Int/UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:129
+msgid "x \\|\\<\\< y"
+msgstr "x \\|\\<\\< y"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical shift left, y: Int/UInt"
+msgstr "逻辑左移，y: Int/UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:133
+msgid "x.rotateLeft(y)"
+msgstr "x.rotateLeft(y)"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical left rotation, y: UInt/Int"
+msgstr "逻辑循环左移，y: UInt/Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:137
+msgid "x.rotateRight(y)"
+msgstr "x.rotateRight(y)"
+
+#: ../../SpinalHDL/Data types/bits.rst
+msgid "Logical right rotation, y: UInt/Int"
+msgstr "逻辑循环右移，y：UInt/Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:141
+msgid "x.clearAll[()]"
+msgstr "x.clearAll[()]"
+
+#: ../../SpinalHDL/Data types/bits.rst:142
+msgid "Clear all bits"
+msgstr "清零所有位"
+
+#: ../../SpinalHDL/Data types/bits.rst:143 types/bits.rst:146
+#: types/bits.rst:149 types/bits.rst:152
+msgid "*modifies x*"
+msgstr "*修改x*"
+
+#: ../../SpinalHDL/Data types/bits.rst:144
+msgid "x.setAll[()]"
+msgstr "x.setAll[()]"
+
+#: ../../SpinalHDL/Data types/bits.rst:145
+msgid "Set all bits"
+msgstr "将所有的位设置为1"
+
+#: ../../SpinalHDL/Data types/bits.rst:147
+msgid "x.setAllTo(value: Boolean)"
+msgstr "x.setAllTo(value: Boolean)"
+
+#: ../../SpinalHDL/Data types/bits.rst:148
+msgid "Set all bits to the given Boolean value"
+msgstr "将所有位设置为给定的布尔值（Scala Boolean）"
+
+#: ../../SpinalHDL/Data types/bits.rst:150
+msgid "x.setAllTo(value: Bool)"
+msgstr "x.setAllTo(value: Bool)"
+
+#: ../../SpinalHDL/Data types/bits.rst:151
+msgid "Set all bits to the given Bool value"
+msgstr "将所有位设置为给定的布尔值（Spinal Bool）"
+
+#: ../../SpinalHDL/Data types/bits.rst:176
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/bits.rst:184
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/bits.rst:185
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/bits.rst:187
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/bits.rst:188
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/bits.rst:201
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/bits.rst:208 types/bits.rst:261
+#: types/bits.rst:359
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bits.rst:209
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/bits.rst:210
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/bits.rst:212
+msgid "x.asUInt"
+msgstr "x.asUInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:213
+msgid "Binary cast to UInt"
+msgstr "二进制转换为 UInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:214
+msgid "UInt(w(x) bits)"
+msgstr "UInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:215
+msgid "x.asSInt"
+msgstr "x.asSInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:216
+msgid "Binary cast to SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Data types/bits.rst:217
+msgid "SInt(w(x) bits)"
+msgstr "SInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:218
+msgid "x.asBools"
+msgstr "x.asBools"
+
+#: ../../SpinalHDL/Data types/bits.rst:219
+msgid "Cast to an array of Bools"
+msgstr "转换为一个布尔数组"
+
+#: ../../SpinalHDL/Data types/bits.rst:220
+msgid "Vec(Bool(), w(x))"
+msgstr "Vec(Bool(), w(x))"
+
+#: ../../SpinalHDL/Data types/bits.rst:221
+msgid "x.asBool"
+msgstr "x.asBool"
+
+#: ../../SpinalHDL/Data types/bits.rst:222
+msgid "Extract LSB of :code:`x`"
+msgstr "提取 :code:`x` 的 LSB"
+
+#: ../../SpinalHDL/Data types/bits.rst:223
+msgid "Bool(x.lsb)"
+msgstr "Bool(x.lsb)"
+
+#: ../../SpinalHDL/Data types/bits.rst:224
+msgid "B(x: T)"
+msgstr "B(x: T)"
+
+#: ../../SpinalHDL/Data types/bits.rst:225
+msgid "Cast Data to Bits"
+msgstr "将数据转换为 ``Bits``"
+
+#: ../../SpinalHDL/Data types/bits.rst:229
+msgid ""
+"To cast a ``Bool``, ``UInt`` or an ``SInt`` into a ``Bits``, you can use "
+"``B(something)`` or ``B(something[, x bits])``:"
+msgstr ""
+"要将 ``Bool`` 、 ``UInt`` 或 ``SInt`` 转换为 ``Bits``，您可以使用 "
+"``B(something)`` 或 ``B(something[, x bits])``:"
+
+#: ../../SpinalHDL/Data types/bits.rst:247
+msgid "Bit extraction"
+msgstr "位提取"
+
+#: ../../SpinalHDL/Data types/bits.rst:249
+msgid ""
+"All of the bit extraction operations can be used to read a bit / group of "
+"bits. Like in other HDLs the extraction operators can also be used to assign"
+" a part of a ``Bits``."
+msgstr "所有位提取操作均可用于读取一个位/一组位。与其他 HDL 一样，"
+"提取运算符也可用于为 ``Bits`` 的一部分赋值。"
+
+#: ../../SpinalHDL/Data types/bits.rst:252
+msgid ""
+"All of the bit extraction operations can be used to read a bit / group of "
+"bits. Like in other HDLs They can also be used to select a range of bits to "
+"be written."
+msgstr "所有位提取操作均可用于读取一个位/一组位。与其他 HDL "
+"一样，它们也可用于选择要写入位的范围。"
+
+#: ../../SpinalHDL/Data types/bits.rst:262
+msgid "x(y: Int)"
+msgstr "x(y: Int)"
+
+#: ../../SpinalHDL/Data types/bits.rst:263
+msgid "Static bit access of y-th bit"
+msgstr "静态访问第 y 位"
+
+#: ../../SpinalHDL/Data types/bits.rst:265
+msgid "x(x: UInt)"
+msgstr "x(x: UInt)"
+
+#: ../../SpinalHDL/Data types/bits.rst:266
+msgid "Variable bit access of y-th bit"
+msgstr "访问第 y 位，这里y为可变的信号"
+
+#: ../../SpinalHDL/Data types/bits.rst:268
+msgid "x(offset: Int, width bits)"
+msgstr "x(offset: Int, width bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:269
+msgid "Fixed part select of fixed width, offset is LSB index"
+msgstr "固定地选择偏移量和宽度，``offset`` 为选择信号中LSB的索引"
+
+#: ../../SpinalHDL/Data types/bits.rst:270 types/bits.rst:273
+msgid "Bits(width bits)"
+msgstr "Bits(width bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:271
+msgid "x(offset: UInt, width bits)"
+msgstr "x(offset: UInt, width bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:272
+msgid "Variable part-select of fixed width, offset is LSB index"
+msgstr "选择偏移量可变和宽度固定的信号，``offset`` 为选择信号中LSB的索引 "
+"（可为另一信号）"
+
+#: ../../SpinalHDL/Data types/bits.rst:274
+msgid "x(range: Range)"
+msgstr "x(range: Range)"
+
+#: ../../SpinalHDL/Data types/bits.rst:275
+msgid "Access a :ref:`range <range>` of bits. Ex : myBits(4 downto 2)"
+msgstr "访问Bits的 :ref:`范围 <range>` 。例如：myBits(4 downto 2)"
+
+#: ../../SpinalHDL/Data types/bits.rst:276
+msgid "Bits(range.size bits)"
+msgstr "Bits(range.size bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:277
+msgid "x.subdivideIn(y slices, [strict: Boolean])"
+msgstr "x.subdivideIn(y slices, [strict: Boolean])"
+
+#: ../../SpinalHDL/Data types/bits.rst:278
+msgid "Subdivide x into y slices, y: Int"
+msgstr "将x分割为y片，y: Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:279
+msgid "Vec(Bits(...), y)"
+msgstr "Vec(Bits(...), y)"
+
+#: ../../SpinalHDL/Data types/bits.rst:280
+msgid "x.subdivideIn(y bits, [strict: Boolean])"
+msgstr "x.subdivideIn(y bits, [strict: Boolean])"
+
+#: ../../SpinalHDL/Data types/bits.rst:281
+msgid "Subdivide x in multiple slices of y bits, y: Int"
+msgstr "将 x 分割为 y 位的多个切片，y: Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:282
+msgid "Vec(Bits(y bit), ...)"
+msgstr "Vec(Bits(y bit), ...)"
+
+#: ../../SpinalHDL/Data types/bits.rst:283
+msgid "x.msb"
+msgstr "x.msb"
+
+#: ../../SpinalHDL/Data types/bits.rst:284
+msgid "Access most significant bit of x (highest index)"
+msgstr "访问 x 的最高有效位（最高索引）"
+
+#: ../../SpinalHDL/Data types/bits.rst:286
+msgid "x.lsb"
+msgstr "x.lsb"
+
+#: ../../SpinalHDL/Data types/bits.rst:287
+msgid "Access lowest significant bit of x (index 0)"
+msgstr "访问 x 的最低有效位（索引 0）"
+
+#: ../../SpinalHDL/Data types/bits.rst:291
+msgid "Some basic examples:"
+msgstr "一些基本示例："
+
+#: ../../SpinalHDL/Data types/bits.rst:320
+msgid "Subdivide details"
+msgstr "分割细节"
+
+#: ../../SpinalHDL/Data types/bits.rst:322
+msgid ""
+"Both overloads of ``subdivideIn`` have an optional parameter ``strict`` "
+"(i.e. ``subdivideIn(slices: SlicesCount, strict: Boolean = true)``). If "
+"``strict`` is ``true`` an error will be raised if the input could not be "
+"divided into equal parts. If set to ``false`` the last element may be "
+"smaller than the other (equal sized) elements."
+msgstr ""
+"两个 ``subdivideIn`` 函数的所有参数都有一个可选参数 ``strict`` 参数（即 "
+"``subdivideIn(slices: SlicesCount, strict: Boolean = true)`` ）。如果 "
+"``strict`` 为 ``true``，则如果输入无法等分，将引发错误。如果设置为 "
+"``false``，最后一个元素可能比其他（大小相等）元素小。"
+
+#: ../../SpinalHDL/Data types/bits.rst:348
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Data types/bits.rst:350
+msgid ""
+"In contrast to the bit extraction operations listed above it's not possible "
+"to use the return values to assign to the original signal."
+msgstr "与上面列出的位提取操作相反，上述函数不能使用其返回值给原始信号赋值。"
+
+#: ../../SpinalHDL/Data types/bits.rst:360
+msgid "x.getWidth"
+msgstr "x.getWidth"
+
+#: ../../SpinalHDL/Data types/bits.rst:361
+msgid "Return bitcount"
+msgstr "返回位数"
+
+#: ../../SpinalHDL/Data types/bits.rst:362 types/bits.rst:371
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:363
+msgid "x.bitsRange"
+msgstr "x.bitsRange"
+
+#: ../../SpinalHDL/Data types/bits.rst:364
+msgid "Return the range (0 to x.high)"
+msgstr "返回范围（0 到 x.high）"
+
+#: ../../SpinalHDL/Data types/bits.rst:365 types/bits.rst:368
+msgid "Range"
+msgstr "范围"
+
+#: ../../SpinalHDL/Data types/bits.rst:366
+msgid "x.valueRange"
+msgstr "x.valueRange"
+
+#: ../../SpinalHDL/Data types/bits.rst:367
+msgid ""
+"Return the range of minimum to maximum x values, interpreted as an unsigned "
+"integer (0 to 2 \\*\\* width - 1)."
+msgstr "返回最小到最大 x 值的范围，理解为无符号整数（0 到 2 \\*\\* width - 1）。"
+
+#: ../../SpinalHDL/Data types/bits.rst:369
+msgid "x.high"
+msgstr "x.high"
+
+#: ../../SpinalHDL/Data types/bits.rst:370
+msgid "Return the index of the MSB (highest allowed zero-based index for x)"
+msgstr "返回 MSB（最高有效位） 的索引（x的最高索引，该索引从0开始计数）"
+
+#: ../../SpinalHDL/Data types/bits.rst:372
+msgid "x.reversed"
+msgstr "x.reversed"
+
+#: ../../SpinalHDL/Data types/bits.rst:373
+msgid "Return a copy of x with reverse bit order, MSB<>LSB are mirrored."
+msgstr "返回 x 的副本，其位顺序相反，MSB<>LSB 是镜像的。"
+
+#: ../../SpinalHDL/Data types/bits.rst:375
+msgid "x ## y"
+msgstr "x ## y"
+
+#: ../../SpinalHDL/Data types/bits.rst:376
+msgid "Concatenate, x->high, y->low"
+msgstr "连接Bits，x->高位，y->低位"
+
+#: ../../SpinalHDL/Data types/bits.rst:377
+msgid "Bits(w(x) + w(y) bits)"
+msgstr "Bits(w(x) + w(y) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:378
+msgid "x #* n"
+msgstr "x #* n"
+
+#: ../../SpinalHDL/Data types/bits.rst:379
+msgid "Repeat x n-times"
+msgstr "n次重复x并合并"
+
+#: ../../SpinalHDL/Data types/bits.rst:380
+msgid "Bits(w(x) * n bits)"
+msgstr "Bits(w(x) * n bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:381
+msgid "x.resize(y)"
+msgstr "x.resize(y)"
+
+#: ../../SpinalHDL/Data types/bits.rst:382
+msgid ""
+"Return a resized representation of x, if enlarged, it is extended with zero "
+"padding at MSB as necessary, y: Int"
+msgstr "返回一个新的信号与 x 信号直接连接但位宽变成了y位。如果位宽变大了，"
+"则根据需要在 MSB 处用零填充进行扩展，y: Int"
+
+#: ../../SpinalHDL/Data types/bits.rst:384
+msgid "Bits(y bits)"
+msgstr "Bits(y bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:385
+msgid "x.resized"
+msgstr "x.resized"
+
+#: ../../SpinalHDL/Data types/bits.rst:386
+msgid ""
+"Return a version of x which is allowed to be automatically resized were "
+"needed.  The resize operation is deferred until the point of assignment "
+"later. The resize may widen or truncate, retaining the LSB."
+msgstr "返回一个允许自动调整位宽的 x 的副本信号。调整位宽操作被推迟到稍后的赋值操作。"
+"调整位宽可能会加宽或截断原信号，但保留 LSB。"
+
+#: ../../SpinalHDL/Data types/bits.rst:390
+msgid "x.resizeLeft(x)"
+msgstr "x.resizeLeft(x)"
+
+#: ../../SpinalHDL/Data types/bits.rst:391
+msgid ""
+"Resize by keeping MSB at the same place, x:Int The resize may widen or "
+"truncate, retaining the MSB."
+msgstr "调整位宽时保持 MSB 位置不变，x:Int 调整位宽可能会加宽或截断信号，同时保留 "
+"MSB。"
+
+#: ../../SpinalHDL/Data types/bits.rst:394
+msgid "x.getZero"
+msgstr "x.getZero"
+
+#: ../../SpinalHDL/Data types/bits.rst:395
+msgid ""
+"Return a new instance of Bits that is assigned a constant value of zeros the"
+" same width as x."
+msgstr "返回新的 Bits 的实例，该实例被分配了与 x 宽度相同的0值（常量）。"
+
+#: ../../SpinalHDL/Data types/bits.rst:396
+msgid "Bits(0, w(x) bits)"
+msgstr "Bits(0, w(x) bits)"
+
+#: ../../SpinalHDL/Data types/bits.rst:397
+msgid "x.getAllTrue"
+msgstr "x.getAllTrue"
+
+#: ../../SpinalHDL/Data types/bits.rst:398
+msgid ""
+"Return a new instance of Bits that is assigned a constant value of ones the "
+"same width as x."
+msgstr "返回 Bits 的新实例，该实例被赋予了与 x 宽度相同的1值（常量）。"
+
+#: ../../SpinalHDL/Data types/bits.rst:399
+msgid "Bits(w(x) bits).setAll()"
+msgstr "Bits(w(x) bits).setAll()"
+
+#: ../../SpinalHDL/Data types/bits.rst:402
+msgid ""
+"`validRange` can only be used for types where the minimum and maximum values"
+" fit into a signed 32-bit integer. (This is a limitation given by the Scala "
+"``scala.collection.immutable.Range`` type which uses `Int`)"
+msgstr ""
+"`validRange` 只能用于最小值和最大值能够保存在32 位有符号整数的情况下。 （"
+"这是由于 Scala ``scala.collection.immutable.Range`` 类型使用 `Int` "
+"作为范围描述）"
+
+#: ../../SpinalHDL/Data types/bits.rst:424
+msgid "MaskedLiteral"
+msgstr "掩码字面量"
+
+#: ../../SpinalHDL/Data types/bits.rst:426
+msgid ""
+"MaskedLiteral values are bit vectors with don't care values denoted with "
+"``-``. They can be used for direct comparison or for ``switch`` statements "
+"and ``mux`` es."
+msgstr ""
+"MaskedLiteral 值带有\"不关心\"值的位向量，其中\"不关心\"值用 ``-`` 表示。"
+"它们可用于直接比较或用于 ``switch`` 和 ``mux`` 等语句。"
+
+#~ msgid "Create a BitVector, bits count is inferred"
+#~ msgstr "Create a BitVector, bits count is inferred"
+
+#~ msgid "x(y)"
+#~ msgstr "x(y)"
+
+#~ msgid "Readbit, y: Int/UInt"
+#~ msgstr "读取位，y：Int/UInt"
+
+#~ msgid "Read bitfield, offset: UInt, width: Int"
+#~ msgstr "读取位域，偏移量：UInt，宽度：Int"
+
+#~ msgid "x(y) := z"
+#~ msgstr "x(y) := z"
+
+#~ msgid "Assign bits, y: Int/UInt"
+#~ msgstr "分配位，y：Int/UInt"
+
+#~ msgid "x(offset, width bits) := z"
+#~ msgstr "x(偏移量，宽度位) := z"
+
+#~ msgid "Assign bitfield, offset: UInt, width: Int"
+#~ msgstr "分配位域，偏移量：UInt，宽度：Int"
+
+#~ msgid "x(\\ :ref:`range <range>`\\ ) := z"
+#~ msgstr "x(\\ :ref:`范围 <范围>`\\ ) := z"
+
+#~ msgid "Assign a range of bit. Ex : myBits(4 downto 2) := B\"010\""
+#~ msgstr "指定一个位范围。例如：myBits(4 downto 2) := B\"010\""
+
+#~ msgid "Return the most significant bit"
+#~ msgstr "返回最高有效位"
+
+#~ msgid "Return the least significant bit"
+#~ msgstr "返回最低有效位"
+
+#~ msgid "Vec(Bits, w(x)/y)"
+#~ msgstr "Vec(位，w(x)/y)"
+
+#~ msgid ""
+#~ "Return a version of x which is allowed to be automatically resized were "
+#~ "needed"
+#~ msgstr "返回一个允许自动调整大小的 x 版本"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po
new file mode 100644
index 00000000000..02c8029c36b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po	
@@ -0,0 +1,546 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesbool/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Data types/bool.rst:4 types/bool.rst:70 types/bool.rst:73
+#: types/bool.rst:76 types/bool.rst:80 types/bool.rst:112 types/bool.rst:116
+#: types/bool.rst:120 types/bool.rst:123 types/bool.rst:126 types/bool.rst:135
+#: types/bool.rst:138 types/bool.rst:141 types/bool.rst:144 types/bool.rst:192
+#: types/bool.rst:195 types/bool.rst:198 types/bool.rst:201 types/bool.rst:204
+#: types/bool.rst:207 types/bool.rst:216 types/bool.rst:248 types/bool.rst:251
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/bool.rst:7 types/bool.rst:66 types/bool.rst:108
+#: types/bool.rst:188 types/bool.rst:244 types/bool.rst:271 types/bool.rst:305
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/bool.rst:9
+msgid ""
+"The ``Bool`` type corresponds to a boolean value (True or False) or a single"
+" bit/wire used in a hardware design.  While named similarly it should not be"
+" confused with Scala `Boolean` type which does not describe hardware but "
+"truth values in the Scala generator code."
+msgstr ""
+"``Bool`` 类型对应于硬件设计中使用的布尔值（True 或 "
+"False）或单个位/线。虽然名称类似，但不应与 Scala `Boolean` "
+"类型混淆，后者不描述硬件，而是描述 Scala 生成器代码中的真值。"
+
+#: ../../SpinalHDL/Data types/bool.rst:14
+msgid ""
+"An important concept and rule-of-thumb to understand is that the Scala "
+"`Boolean` type is used in places where elaboration-time HDL code-generation "
+"decision making is occuring in Scala code.  Like any regular program it "
+"affects execution of the Scala program that is SpinalHDL at the time the "
+"program is being run to perform HDL code generation."
+msgstr ""
+"需要理解的一个重要概念和经验是，Scala `Boolean` "
+"类型用于在实例细化时决定如何生成 HDL 代码。与任何常规程序一样，在运行 "
+"SpinalHDL 程序以执行 HDL 代码生成时，它会影响 Scala 程序的执行。"
+
+#: ../../SpinalHDL/Data types/bool.rst:20
+msgid ""
+"Therefore the value of a Scala `Boolean` can not be observed from hardware, "
+"because it only exists ahead-of-time in the SpinalHDL program at the time of"
+" HDL code-gen."
+msgstr ""
+"因此，Scala `Boolean` 的值无法从硬件中观察到，因为它仅在 HDL "
+"代码生成时存在于 SpinalHDL 程序中，这在硬件仿真/运行之前。"
+
+#: ../../SpinalHDL/Data types/bool.rst:24
+msgid ""
+"In scenarios where you might need this for your design, for example to pass "
+"a value (that maybe acting as a parameterized constant input) from Scala "
+"into your hardware design, you can type convert it to Bool with the "
+"constructor `Bool(value: Boolean)`."
+msgstr ""
+"在您的设计中可能需要这样做，例如从 Scala "
+"向硬件设计中传递一个值（该值可能作为参数化常量输入），您可以使用构造函数 "
+"`Bool(value: Boolean)` 将其类型转换为 `Bool` 。"
+
+#: ../../SpinalHDL/Data types/bool.rst:28
+msgid ""
+"Similarly the value of a SpinalHDL `Bool` can not be seen at code-"
+"generation, all that can be seen and manipulated is the HDL construct "
+"concerning a `wire` and how it is routed (through modules/Components), "
+"driven (sourced) and connected (sunk)."
+msgstr ""
+"同样，SpinalHDL `Bool` 的值在代码生成时无法看到，"
+"所有可以看到和操作的都是有关 `wire` 的 HDL "
+"构造以及它如何路由（通过模块/组件）、驱动（源）并连接（汇据点）。"
+
+#: ../../SpinalHDL/Data types/bool.rst:32
+msgid ""
+"The signal direction of assignment operators `:=` is managed by SpinalHDL. "
+"The use of the Bool instance on the left-hand-side or the right-hand-side of"
+" the assignment operator `:=` dictates if it is a source (provides state) or"
+" sink (captures state) for a given assignment."
+msgstr ""
+"赋值运算符 `:=` 的信号方向由 SpinalHDL 管理。在赋值运算符 `:=` "
+"左侧或右侧使用 `Bool` "
+"实例指示它是给定赋值的源（提供状态）还是接收器（捕获状态）。"
+
+#: ../../SpinalHDL/Data types/bool.rst:37
+msgid ""
+"Multiple uses of the assignment operator are allowed, such that it is normal"
+" for a signal wire to act as a source (provides a value to drive HDL state) "
+"to be able to connect and drive multiple inputs of other HDL constructs.  "
+"When a Bool instance used as a source the order the assignment statements "
+"appear or are executed in Scala does not matter, unlike when it is used as a"
+" sink (captures state)."
+msgstr ""
+"允许多次使用赋值运算符，因此信号线作为源（提供值以驱动 HDL 状态）"
+"连接并驱动其他 HDL 结构的多个输入是很正常的。 当 Bool 实例用作源时，"
+"赋值语句在 Scala "
+"中出现或执行的顺序并不重要，而当它用作汇（捕获状态）时则不同。"
+
+#: ../../SpinalHDL/Data types/bool.rst:44
+msgid ""
+"When multiple assignment operators drive the Bool (the Bool is on the left-"
+"hand-side of the assignment expression), the last assignment statement wins "
+"rule; take effect.  The last would be the last to execute in Scala code.  "
+"This matter can affect the layout and ordering of your SpinalHDL Scala code "
+"to ensure the correct precedence order is archived in the hardware design "
+"for assigning a new state to the Bool in hardware."
+msgstr ""
+"当多个赋值操作符驱动 Bool（Bool "
+"位于赋值表达式的左侧）时，最后一个赋值语句将赢得胜利；并开始生效。 "
+"最后一个将在 Scala 代码中最后执行。 此事会影响 SpinalHDL Scala "
+"代码的布局和排序，以确保在硬件设计中获得正确的优先顺序，以便在硬件中为 Bool "
+"赋值新状态。"
+
+#: ../../SpinalHDL/Data types/bool.rst:51
+msgid ""
+"It may help to understand the concept with relating the Scala/SpinalHDL "
+"`Bool` instance as a reference to a HDL `net` in the net-list.  Which the "
+"assignment `:=` operator is attaching HDL constructs into the same net."
+msgstr ""
+"将 Scala/SpinalHDL `Bool` 实例作为对 net-list 中 HDL `net` "
+"的引用，可能有助于理解这一概念。 其中，赋值 `:=` 操作符将 HDL "
+"结构加入到同一个网中。"
+
+#: ../../SpinalHDL/Data types/bool.rst:57
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/bool.rst:59
+msgid ""
+"The syntax to declare a boolean value is as follows: (everything between [] "
+"is optional)"
+msgstr "声明布尔值的语法如下：（[]之间的所有内容都是可选的）"
+
+#: ../../SpinalHDL/Data types/bool.rst:65
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Data types/bool.rst:67 types/bool.rst:272
+#: types/bool.rst:306
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bool.rst:68
+msgid "Bool()"
+msgstr "Bool()"
+
+#: ../../SpinalHDL/Data types/bool.rst:69
+msgid "Create a Bool"
+msgstr "创建Bool值"
+
+#: ../../SpinalHDL/Data types/bool.rst:71
+msgid "True"
+msgstr "True"
+
+#: ../../SpinalHDL/Data types/bool.rst:72
+msgid "Create a Bool assigned with ``true``"
+msgstr "创建一个分配有 ``true`` 值的 Bool对象"
+
+#: ../../SpinalHDL/Data types/bool.rst:74
+msgid "False"
+msgstr "False"
+
+#: ../../SpinalHDL/Data types/bool.rst:75
+msgid "Create a Bool assigned with ``false``"
+msgstr "创建一个Bool值并赋值为 ``false``"
+
+#: ../../SpinalHDL/Data types/bool.rst:77
+msgid "Bool(value: Boolean)"
+msgstr "Bool(value: Boolean)"
+
+#: ../../SpinalHDL/Data types/bool.rst:78
+msgid ""
+"Create a Bool assigned with a value from a Scala Boolean type (true, false)."
+" This explicitly converts to ``True`` or ``False``."
+msgstr "创建一个 Bool，并分配一个 Scala 布尔类型（true、false）的值。这显式地转换为 "
+"``True`` 或 ``False`` 。"
+
+#: ../../SpinalHDL/Data types/bool.rst:93
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bool.rst:95
+msgid "The following operators are available for the ``Bool`` type:"
+msgstr "以下运算符可用于 ``Bool`` 类型："
+
+#: ../../SpinalHDL/Data types/bool.rst:102
+msgid "Logic"
+msgstr "逻辑运算"
+
+#: ../../SpinalHDL/Data types/bool.rst:107 types/bool.rst:187
+#: types/bool.rst:243 types/bool.rst:270 types/bool.rst:304
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bool.rst:109 types/bool.rst:189
+#: types/bool.rst:245
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bool.rst:110
+msgid "!x"
+msgstr "!x"
+
+#: ../../SpinalHDL/Data types/bool.rst:111 types/bool.rst:125
+msgid "Logical NOT"
+msgstr "逻辑非"
+
+#: ../../SpinalHDL/Data types/bool.rst
+msgid "x && y"
+msgstr "x && y"
+
+#: ../../SpinalHDL/Data types/bool.rst
+msgid "x & y"
+msgstr "x & y"
+
+#: ../../SpinalHDL/Data types/bool.rst:115
+msgid "Logical AND"
+msgstr "逻辑与"
+
+#: ../../SpinalHDL/Data types/bool.rst
+msgid "x || y"
+msgstr "x || y"
+
+#: ../../SpinalHDL/Data types/bool.rst
+msgid "x | y"
+msgstr "x | y"
+
+#: ../../SpinalHDL/Data types/bool.rst:119
+msgid "Logical OR"
+msgstr "逻辑或"
+
+#: ../../SpinalHDL/Data types/bool.rst:121
+msgid "x ^ y"
+msgstr "x ^ y"
+
+#: ../../SpinalHDL/Data types/bool.rst:122
+msgid "Logical XOR"
+msgstr "逻辑异或"
+
+#: ../../SpinalHDL/Data types/bool.rst:124
+msgid "~x"
+msgstr "~x"
+
+#: ../../SpinalHDL/Data types/bool.rst:127
+msgid "x.set[()]"
+msgstr "x.set[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:128
+msgid "Set x to True"
+msgstr "将 x 设置为 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:129 types/bool.rst:132
+msgid "Unit (none)"
+msgstr "Unit (none)"
+
+#: ../../SpinalHDL/Data types/bool.rst:130
+msgid "x.clear[()]"
+msgstr "x.clear[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:131
+msgid "Set x to False"
+msgstr "将 x 设置为 False"
+
+#: ../../SpinalHDL/Data types/bool.rst:133
+msgid "x.setWhen(cond)"
+msgstr "x.setWhen(cond)"
+
+#: ../../SpinalHDL/Data types/bool.rst:134
+msgid "Set x when cond is True"
+msgstr "当 cond 为 True 时设置 x 为 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:136
+msgid "x.clearWhen(cond)"
+msgstr "x.clearWhen(cond)"
+
+#: ../../SpinalHDL/Data types/bool.rst:137
+msgid "Clear x when cond is True"
+msgstr "当 cond 为 True 时设置 x 为 False"
+
+#: ../../SpinalHDL/Data types/bool.rst:139
+msgid "x.riseWhen(cond)"
+msgstr "x.riseWhen(cond)"
+
+#: ../../SpinalHDL/Data types/bool.rst:140
+msgid "Set x when x is False and cond is True"
+msgstr "当 x 为 False 并且 cond 为 True 时设置 x 为 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:142
+msgid "x.fallWhen(cond)"
+msgstr "x.fallWhen(cond)"
+
+#: ../../SpinalHDL/Data types/bool.rst:143
+msgid "Clear x when x is True and cond is True"
+msgstr "当 x 为 True 并且 cond 为 True 时设置 x 为False"
+
+#: ../../SpinalHDL/Data types/bool.rst:173
+msgid "Edge detection"
+msgstr "边缘检测"
+
+#: ../../SpinalHDL/Data types/bool.rst:175
+msgid ""
+"All edge detection functions will instantiate an additional register via "
+":ref:`RegNext <regnext>` to get a delayed value of the ``Bool`` in question."
+msgstr ""
+"所有边缘检测函数都将通过 :ref:`RegNext <regnext>` 实例化一个附加寄存器，"
+"以获取相关 ``Bool`` 的延迟值（一拍）。"
+
+#: ../../SpinalHDL/Data types/bool.rst:178
+msgid ""
+"This feature does not reconfigure a D-type Flip-Flop to use an alternative "
+"CLK source, it uses two D-type Flip-Flop in series chain (with both CLK pins"
+" inheriting the default ClockDomain).  It has combinational logic to perform"
+" edge detection based on the output Q states."
+msgstr ""
+"此功能不会重新配置 D 型触发器以使用其他 CLK 时钟，它使用串联链中的两个 D "
+"型触发器（两个 CLK 引脚都继承默认的 ClockDomain）。它具有组合逻辑，"
+"可根据输出 Q 状态进行边缘检测。"
+
+#: ../../SpinalHDL/Data types/bool.rst:190
+msgid "x.edge[()]"
+msgstr "x.edge[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:191
+msgid "Return True when x changes state"
+msgstr "当 x 状态改变时返回 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:193
+msgid "x.edge(initAt: Bool)"
+msgstr "x.edge(initAt: Bool)"
+
+#: ../../SpinalHDL/Data types/bool.rst:194
+msgid "Same as x.edge but with a reset value"
+msgstr "与 x.edge 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Data types/bool.rst:196
+msgid "x.rise[()]"
+msgstr "x.rise[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:197
+msgid "Return True when x was low at the last cycle and is now high"
+msgstr "当 x 在上一个周期为低电平且现在为高电平时返回 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:199
+msgid "x.rise(initAt: Bool)"
+msgstr "x.rise(initAt: Bool)"
+
+#: ../../SpinalHDL/Data types/bool.rst:200
+msgid "Same as x.rise but with a reset value"
+msgstr "与 x.rise 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Data types/bool.rst:202
+msgid "x.fall[()]"
+msgstr "x.fall[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:203
+msgid "Return True when x was high at the last cycle and is now low"
+msgstr "当 x 在上一个周期为高且现在为低时返回 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:205
+msgid "x.fall(initAt: Bool)"
+msgstr "x.fall(initAt: Bool)"
+
+#: ../../SpinalHDL/Data types/bool.rst:206
+msgid "Same as x.fall but with a reset value"
+msgstr "与 x.fall 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Data types/bool.rst:208
+msgid "x.edges[()]"
+msgstr "x.edges[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:209
+msgid "Return a bundle (rise, fall, toggle)"
+msgstr "返回捆绑包（上升、下降、切换）"
+
+#: ../../SpinalHDL/Data types/bool.rst:210 types/bool.rst:213
+msgid "BoolEdges"
+msgstr "BoolEdges"
+
+#: ../../SpinalHDL/Data types/bool.rst:211
+msgid "x.edges(initAt: Bool)"
+msgstr "x.edges(initAt: Bool)"
+
+#: ../../SpinalHDL/Data types/bool.rst:212
+msgid "Same as x.edges but with a reset value"
+msgstr "与 x.edges 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Data types/bool.rst:214
+msgid "x.toggle[()]"
+msgstr "x.toggle[()]"
+
+#: ../../SpinalHDL/Data types/bool.rst:215
+msgid "Return True at every edge"
+msgstr "在每个边缘返回 True"
+
+#: ../../SpinalHDL/Data types/bool.rst:238
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/bool.rst:246
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/bool.rst:247
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/bool.rst:249
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/bool.rst:250
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/bool.rst:265
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/bool.rst:273
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/bool.rst:274
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/bool.rst:275
+msgid "Bits(1 bit)"
+msgstr "Bits(1 bit)"
+
+#: ../../SpinalHDL/Data types/bool.rst:276
+msgid "x.asUInt"
+msgstr "x.asUInt"
+
+#: ../../SpinalHDL/Data types/bool.rst:277
+msgid "Binary cast to UInt"
+msgstr "二进制转换为 UInt"
+
+#: ../../SpinalHDL/Data types/bool.rst:278
+msgid "UInt(1 bit)"
+msgstr "UInt(1 bit)"
+
+#: ../../SpinalHDL/Data types/bool.rst:279
+msgid "x.asSInt"
+msgstr "x.asSInt"
+
+#: ../../SpinalHDL/Data types/bool.rst:280
+msgid "Binary cast to SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Data types/bool.rst:281
+msgid "SInt(1 bit)"
+msgstr "SInt(1 bit)"
+
+#: ../../SpinalHDL/Data types/bool.rst:282
+msgid "x.asUInt(bitCount)"
+msgstr "x.asUInt(bitCount)"
+
+#: ../../SpinalHDL/Data types/bool.rst:283
+msgid ""
+"Binary cast to UInt and resize, putting Bool value in LSB and padding with "
+"zeros."
+msgstr "二进制转换为 UInt 并调整大小，将 Bool 值放入 LSB 并用零填充。"
+
+#: ../../SpinalHDL/Data types/bool.rst:285
+msgid "UInt(bitCount bits)"
+msgstr "UInt(bitCount bits)"
+
+#: ../../SpinalHDL/Data types/bool.rst:286
+msgid "x.asBits(bitCount)"
+msgstr "x.asBits(bitCount)"
+
+#: ../../SpinalHDL/Data types/bool.rst:287
+msgid ""
+"Binary cast to Bits and resize, putting Bool value in LSB and padding with "
+"zeros."
+msgstr "二进制转换为位并调整大小，将布尔值放入 LSB 并用零填充。"
+
+#: ../../SpinalHDL/Data types/bool.rst:289
+msgid "Bits(bitCount bits)"
+msgstr "Bits(bitCount bits)"
+
+#: ../../SpinalHDL/Data types/bool.rst:299
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Data types/bool.rst:307
+msgid "x ## y"
+msgstr "x ## y"
+
+#: ../../SpinalHDL/Data types/bool.rst:308
+msgid "Concatenate, x->high, y->low"
+msgstr "连接Bits，x->高位，y->低位"
+
+#: ../../SpinalHDL/Data types/bool.rst:309
+msgid "Bits(w(x) + w(y) bits)"
+msgstr "Bits(w(x) + w(y) bits)"
+
+#: ../../SpinalHDL/Data types/bool.rst:310
+msgid "x #* n"
+msgstr "x #* n"
+
+#: ../../SpinalHDL/Data types/bool.rst:311
+msgid "Repeat x n-times"
+msgstr "n次重复x并合并"
+
+#: ../../SpinalHDL/Data types/bool.rst:312
+msgid "Bits(n bits)"
+msgstr "Bits(n bits)"
+
+#: ../../SpinalHDL/Data types/bool.rst:324
+msgid "MaskedBoolean"
+msgstr "掩码布尔值"
+
+#: ../../SpinalHDL/Data types/bool.rst:326
+msgid ""
+"A masked boolean allows don’t care values. They are usually not used on "
+"their own but through :ref:`MaskedLiteral <maskedliteral>`."
+msgstr ""
+"具有掩码的布尔型允许任意值（don't care）。它们通常不单独使用，而是通过 :ref:`"
+"MaskedLiteral <maskedliteral>` 使用。"
+
+#~ msgid "The ``Bool`` type corresponds to a boolean value (True or False)."
+#~ msgstr "“Bool” 类型对应于布尔值（True 或 False）。"
+
+#~ msgid "Binary cast to UInt and resize"
+#~ msgstr "二进制转换为 UInt 并调整大小"
+
+#~ msgid "Binary cast to Bits and resize"
+#~ msgstr "二进制转换为位并调整大小"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bundle.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bundle.po
new file mode 100644
index 00000000000..af9717a956d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bundle.po	
@@ -0,0 +1,246 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesbundle/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../SpinalHDL/Data types/bundle.rst:5
+msgid "Bundle"
+msgstr "Bundle"
+
+#: ../../SpinalHDL/Data types/bundle.rst:8 types/bundle.rst:64
+#: types/bundle.rst:97 types/bundle.rst:121
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/bundle.rst:10
+msgid ""
+"The ``Bundle`` is a composite type that defines a group of named signals (of"
+" any SpinalHDL basic type) under a single name."
+msgstr "``Bundle`` 是一种复合类型，它在单个名称下定义一组具有命名的信号（任何 "
+"SpinalHDL 基本类型）。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:12
+msgid ""
+"A ``Bundle`` can be used to model data structures, buses, and interfaces."
+msgstr "``Bundle`` 可用于对数据结构、总线和接口进行建模。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:15
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/bundle.rst:17
+msgid "The syntax to declare a bundle is as follows:"
+msgstr "声明线束的语法如下："
+
+#: ../../SpinalHDL/Data types/bundle.rst:27
+msgid "For example, a bundle holding a color could be defined as:"
+msgstr "例如，包含颜色的线束可以定义为："
+
+#: ../../SpinalHDL/Data types/bundle.rst:35
+msgid ""
+"You can find an :ref:`APB3 definition <example_apb3>` among the :ref:`Spinal"
+" HDL examples <example_list>`."
+msgstr ""
+"您可以在 :ref:`Spinal HDL examples <example_list>` 中找到 :ref:`APB3 "
+"definition <example_apb3>` 。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:38
+msgid "Conditional signals"
+msgstr "条件信号"
+
+#: ../../SpinalHDL/Data types/bundle.rst:39
+msgid ""
+"The signals in the ``Bundle`` can be defined conditionally. Unless "
+"``dataWidth`` is greater than 0, there will be no ``data`` signal in "
+"elaborated ``myBundle``, as demonstrated in the example below."
+msgstr ""
+"``Bundle`` 中的信号可以有条件地定义。除非 ``dataWidth`` 大于 0，"
+"否则在实力细化后的 ``myBundle``中将不会有 ``data`` 信号，如下例所示。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:50
+msgid ""
+"See also :ref:`generate <generate>` for information about this SpinalHDL "
+"method."
+msgstr "另请参阅 :ref:`generate <generate>` 了解有关此 SpinalHDL 方法的信息。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:53
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bundle.rst:55
+msgid "The following operators are available for the ``Bundle`` type:"
+msgstr "以下运算符可用于 ``Bundle`` 类型："
+
+#: ../../SpinalHDL/Data types/bundle.rst:58
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/bundle.rst:63 types/bundle.rst:96
+#: types/bundle.rst:120
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/bundle.rst:65
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bundle.rst:66
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/bundle.rst:67
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/bundle.rst:68 types/bundle.rst:71
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/bundle.rst:69
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/bundle.rst:70
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/bundle.rst:91
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/bundle.rst:98 types/bundle.rst:122
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/bundle.rst:99
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/bundle.rst:100
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/bundle.rst:101
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/bundle.rst:108
+msgid ""
+"The elements of the bundle will be mapped into place in the order in which "
+"they are defined, LSB first. Thus, ``r`` in ``color1`` will occupy bits 0 to"
+" 8 of ``myBits`` (LSB), followed by ``g`` and ``b`` in that order, with "
+"``b.msb`` also being the MSB of the resulting Bits type."
+msgstr ""
+"线束中的元素将按其定义的顺序映射到位，按LSB 先放置的顺序。因此，``color1`` "
+"中的 ``r`` 将占据 ``myBits`` 的第 0 至 8 位（LSB），然后依次是 ``g`` 和 ``b``"
+" ，``b.msb`` 也是最终 Bits 类型的 MSB。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:113
+msgid "Convert Bits back to Bundle"
+msgstr "将位转换回线束"
+
+#: ../../SpinalHDL/Data types/bundle.rst:114
+msgid ""
+"The ``.assignFromBits`` operator can be viewed as the reverse of "
+"``.asBits``."
+msgstr "``.assignFromBits`` 运算符可以被视为 ``.asBits`` 的逆操作。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:123
+msgid "x.assignFromBits(y)"
+msgstr "x.assignFromBits(y)"
+
+#: ../../SpinalHDL/Data types/bundle.rst:124
+msgid "Convert Bits (y) to Bundle(x)"
+msgstr "将Bits (y)转换为Bundle(x)"
+
+#: ../../SpinalHDL/Data types/bundle.rst:125 types/bundle.rst:128
+msgid "Unit"
+msgstr "Unit"
+
+#: ../../SpinalHDL/Data types/bundle.rst:126
+msgid "x.assignFromBits(y, hi, lo)"
+msgstr "x.assignFromBits(y, hi, lo)"
+
+#: ../../SpinalHDL/Data types/bundle.rst:127
+msgid "Convert Bits (y) to Bundle(x) with high/low boundary"
+msgstr "将Bits (y) 转换为具有高/低边界的 Bundle(x)"
+
+#: ../../SpinalHDL/Data types/bundle.rst:130
+msgid ""
+"The following example saves a Bundle called CommonDataBus into a circular "
+"buffer (3rd party memory), reads the Bits out later and converts them back "
+"to CommonDataBus format."
+msgstr ""
+"下面的示例将名为 CommonDataBus "
+"的线束保存到循环缓冲区（第三方内存）中，随后读出比特，并将其转换回 "
+"CommonDataBus 格式。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:162
+msgid "IO Element direction"
+msgstr "IO元件方向"
+
+#: ../../SpinalHDL/Data types/bundle.rst:164
+msgid ""
+"When you define a ``Bundle`` inside the IO definition of your component, you"
+" need to specify its direction."
+msgstr "当您在组件的 IO 定义中实现 ``Bundle`` 时需要指定其方向。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:167
+msgid "in/out"
+msgstr "in/out"
+
+#: ../../SpinalHDL/Data types/bundle.rst:169
+msgid ""
+"If all elements of your bundle go in the same direction you can use "
+"``in(MyBundle())`` or ``out(MyBundle())``."
+msgstr "如果线束的所有元素中的信号都朝同一方向传播，则可以使用 ``in(MyBundle())`` or "
+"``out(MyBundle())``。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:171 types/bundle.rst:190
+msgid "For example:"
+msgstr "例如："
+
+#: ../../SpinalHDL/Data types/bundle.rst:181
+msgid "master/slave"
+msgstr "master/slave"
+
+#: ../../SpinalHDL/Data types/bundle.rst:183
+msgid ""
+"If your interface obeys to a master/slave topology, you can use the "
+"``IMasterSlave`` trait. Then you have to implement the function ``def "
+"asMaster(): Unit`` to set the direction of each element from the master's "
+"perspective. Then you can use the ``master(MyBundle())`` and "
+"``slave(MyBundle())`` syntax in the IO definition."
+msgstr ""
+"如果您的接口遵循主/从拓扑结构，您可以使用 ``IMasterSlave`` 特征。"
+"然后你必须实现函数 ``def asMaster(): Unit`` "
+"从master的角度设置每个元素的方向。然后你可以在 IO 定义中使用 "
+"``master(MyBundle())`` 和 ``slave(MyBundle())`` 语法来使用。"
+
+#: ../../SpinalHDL/Data types/bundle.rst:185
+msgid ""
+"There are functions defined as toXXX, such as the ``toStream`` method of the"
+" ``Flow`` class. These functions can usually be called by the master side. "
+"In addition, the fromXXX functions are designed for the slave side. It is "
+"common that there are more functions available for the master side than for "
+"the slave side."
+msgstr ""
+"有些函数定义为 toXXX，例如 ``Flow`` 类的 ``toStream`` 方法。这些函数通常可以"
+"由master端调用。另外，fromXXX函数是为slave侧设计的。通常master端可用的功能多"
+"于slave端。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/enum.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/enum.po
new file mode 100644
index 00000000000..d8a9cdd41d4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/enum.po	
@@ -0,0 +1,247 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-16 16:35+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesenum/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Data types/enum.rst:5
+msgid "SpinalEnum"
+msgstr "SpinalEnum"
+
+#: ../../SpinalHDL/Data types/enum.rst:8 types/enum.rst:48 types/enum.rst:122
+#: types/enum.rst:189
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Data types/enum.rst:10
+msgid "The ``Enumeration`` type corresponds to a list of named values."
+msgstr "``Enumeration`` （枚举）类型对应于命名值的列表。"
+
+#: ../../SpinalHDL/Data types/enum.rst:13
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Data types/enum.rst:15
+msgid "The declaration of an enumerated data type is as follows:"
+msgstr "枚举数据类型的声明如下："
+
+#: ../../SpinalHDL/Data types/enum.rst:23
+msgid ""
+"For the example above, the default encoding is used. The native enumeration "
+"type is used for VHDL and a binary encoding is used for Verilog."
+msgstr "在上面的示例中，使用的是默认编码。VHDL （默认）使用本地枚举类型，Verilog "
+"（默认）使用二进制编码。"
+
+#: ../../SpinalHDL/Data types/enum.rst:26
+msgid ""
+"The enumeration encoding can be forced by defining the enumeration as "
+"follows:"
+msgstr "可以通过如下定义来强制设置指定枚举的编码："
+
+#: ../../SpinalHDL/Data types/enum.rst:35
+msgid ""
+"If you want to define an enumeration as in/out for a given component, you "
+"have to do as following: ``in(MyEnum())`` or ``out(MyEnum())``"
+msgstr "如果要将枚举定义为给定组件的 in/out，则必须执行以下操作： ``in(MyEnum())`` "
+"或 ``out(MyEnum())``"
+
+#: ../../SpinalHDL/Data types/enum.rst:38 types/enum.rst:46
+msgid "Encoding"
+msgstr "编码"
+
+#: ../../SpinalHDL/Data types/enum.rst:40
+msgid "The following enumeration encodings are supported:"
+msgstr "支持以下枚举编码："
+
+#: ../../SpinalHDL/Data types/enum.rst:47
+msgid "Bit width"
+msgstr "位宽"
+
+#: ../../SpinalHDL/Data types/enum.rst:49
+msgid "``native``"
+msgstr "``native``"
+
+#: ../../SpinalHDL/Data types/enum.rst:51
+msgid "Use the VHDL enumeration system, this is the default encoding"
+msgstr "使用VHDL枚举系统，这是默认编码"
+
+#: ../../SpinalHDL/Data types/enum.rst:52
+msgid "``binarySequential``"
+msgstr "``binarySequential``"
+
+#: ../../SpinalHDL/Data types/enum.rst:53 types/enum.rst:60
+msgid "``log2Up(stateCount)``"
+msgstr "``log2Up(stateCount)``"
+
+#: ../../SpinalHDL/Data types/enum.rst:54
+msgid "Use Bits to store states in declaration order (value from 0 to n-1)"
+msgstr "使用 Bits 按声明顺序存储状态（值从 0 到 n-1）"
+
+#: ../../SpinalHDL/Data types/enum.rst:55
+msgid "``binaryOneHot``"
+msgstr "``binaryOneHot``"
+
+#: ../../SpinalHDL/Data types/enum.rst:56
+msgid "stateCount"
+msgstr "stateCount"
+
+#: ../../SpinalHDL/Data types/enum.rst:57
+msgid ""
+"Use Bits to store state. Each bit corresponds to one state, only one bit is "
+"set at a time in the hardware encoded state representation."
+msgstr "使用位来存储状态。每一位对应一个状态，在硬件编码状态表示中一次仅设置一位。"
+
+#: ../../SpinalHDL/Data types/enum.rst:59
+msgid "``graySequential``"
+msgstr "``graySequential``"
+
+#: ../../SpinalHDL/Data types/enum.rst:61
+msgid ""
+"Encode index (numbers as if using ``binarySequential``) as binary gray code."
+msgstr "将索引（像 ``binarySequential`` 中使用的数）编码为二进制格雷码。"
+
+#: ../../SpinalHDL/Data types/enum.rst:63
+msgid ""
+"Custom encodings can be performed in two different ways: static or dynamic."
+msgstr "自定义编码可以通过两种不同的方式执行：静态或动态。"
+
+#: ../../SpinalHDL/Data types/enum.rst:93
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Data types/enum.rst:95
+msgid "Instantiate an enumerated signal and assign a value to it:"
+msgstr "实例化一个枚举信号并为其赋值："
+
+#: ../../SpinalHDL/Data types/enum.rst:111
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/enum.rst:113
+msgid "The following operators are available for the ``Enumeration`` type:"
+msgstr "以下运算符可用于 ``Enumeration`` 类型："
+
+#: ../../SpinalHDL/Data types/enum.rst:116
+msgid "Comparison"
+msgstr "比较运算"
+
+#: ../../SpinalHDL/Data types/enum.rst:121 types/enum.rst:188
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Data types/enum.rst:123
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/enum.rst:124
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Data types/enum.rst:125
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Data types/enum.rst:126 types/enum.rst:129
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Data types/enum.rst:127
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Data types/enum.rst:128
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Data types/enum.rst:154
+msgid "Types"
+msgstr "类型"
+
+#: ../../SpinalHDL/Data types/enum.rst:156
+msgid ""
+"In order to use your enums, for example in a function, you may need its "
+"type."
+msgstr "为了使用枚举（例如在函数中），您可能需要其类型。"
+
+#: ../../SpinalHDL/Data types/enum.rst:158
+msgid "The value type (e.g. sIdle’s type) is"
+msgstr "值的类型（例如 sIdle 的类型）是"
+
+#: ../../SpinalHDL/Data types/enum.rst:164 types/enum.rst:176
+msgid "or equivalently"
+msgstr "或等效的"
+
+#: ../../SpinalHDL/Data types/enum.rst:170
+msgid "The bundle type (e.g. stateNext’s type) is"
+msgstr "线束类型（例如 stateNext 的类型）是"
+
+#: ../../SpinalHDL/Data types/enum.rst:183
+msgid "Type cast"
+msgstr "类型转换"
+
+#: ../../SpinalHDL/Data types/enum.rst:190
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Data types/enum.rst:191
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Data types/enum.rst:192
+msgid "Binary cast to Bits"
+msgstr "二进制转换为 Bits"
+
+#: ../../SpinalHDL/Data types/enum.rst:193
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/enum.rst:194
+msgid "x.asBits.asUInt"
+msgstr "x.asBits.asUInt"
+
+#: ../../SpinalHDL/Data types/enum.rst:195
+msgid "Binary cast to UInt"
+msgstr "二进制转换为 UInt"
+
+#: ../../SpinalHDL/Data types/enum.rst:196
+msgid "UInt(w(x) bits)"
+msgstr "UInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/enum.rst:197
+msgid "x.asBits.asSInt"
+msgstr "x.asBits.asSInt"
+
+#: ../../SpinalHDL/Data types/enum.rst:198
+msgid "Binary cast to SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Data types/enum.rst:199
+msgid "SInt(w(x) bits)"
+msgstr "SInt(w(x) bits)"
+
+#: ../../SpinalHDL/Data types/enum.rst:200
+msgid "e.assignFromBits(bits)"
+msgstr "e.assignFromBits(bits)"
+
+#: ../../SpinalHDL/Data types/enum.rst:201
+msgid "Bits cast to enum"
+msgstr "Bits转换为枚举"
+
+#: ../../SpinalHDL/Data types/enum.rst:202
+msgid "MyEnum()"
+msgstr "MyEnum()"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po
new file mode 100644
index 00000000000..65d5126113a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po	
@@ -0,0 +1,86 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: 2024-01-26 17:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldata-typesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Data types/index.rst:5
+msgid "Data types"
+msgstr "数据类型"
+
+#: ../../SpinalHDL/Data types/index.rst:7
+msgid ""
+"The language provides 5 base types, and 2 composite types that can be "
+"used."
+msgstr "该语言提供了 5 种基本类型和 2 种可以使用的复合类型。"
+
+#: ../../SpinalHDL/Data types/index.rst:9
+msgid ""
+"Base types: :ref:`Bool <Bool>` , :ref:`Bits <Bits>` , :ref:`UInt <Int>` "
+"for unsigned integers, :ref:`SInt <Int>` for signed integers and "
+":ref:`Enum <Enum>`."
+msgstr ""
+"基本类型有： :ref:`Bool <Bool>` , :ref:`Bits <Bits>` , 无符号整数 :ref:`UInt <Int>` "
+"对于，有符号整数 :ref:`SInt <Int>` ，以及 :ref:`Enum <Enum>`。"
+
+#: ../../SpinalHDL/Data types/index.rst:10
+msgid "Composite types: :ref:`Bundle <Bundle>` and :ref:`Vec <Vec>`."
+msgstr "复合类型有： :ref:`Bundle <Bundle>` 有 :ref:`Vec <Vec>`。"
+
+#: ../../SpinalHDL/Data types/index.rst:15
+msgid "In addition to the base types, Spinal has support under development for:"
+msgstr "除了基本类型之外，Spinal 还正在开发支持以下类型："
+
+#: ../../SpinalHDL/Data types/index.rst:17
+msgid ":ref:`Fixed-point <fixed>` numbers (partial support)"
+msgstr ":ref:`Fixed-point <fixed>` 定点小数（部分支持）"
+
+#: ../../SpinalHDL/Data types/index.rst:18
+msgid ":ref:`Auto-range Fixed-point <afix>` numbers (add,sub,mul support)"
+msgstr ":ref:`Auto-range Fixed-point <afix>` 自动范围定点小数（支持加法、减法、乘法 ）"
+
+#: ../../SpinalHDL/Data types/index.rst:19
+msgid ":ref:`Floating-point <Floating>` numbers (experimental support)"
+msgstr ":ref:`Floating-point <Floating>` 浮点小数（实验性支持）"
+
+#: ../../SpinalHDL/Data types/index.rst:22
+msgid ""
+"Additionaly, if you want to assign a don't care value to some hardware, "
+"for instance, to provide a default value, you can use the assignDontCare "
+"API to do so."
+msgstr "此外，如果您想为某些硬件分配一个 \"不关心 \"值，例如提供一个默认值，可以使用 "
+"assignDontCare API 来实现。"
+
+#: ../../SpinalHDL/Data types/index.rst:31
+msgid ""
+"Finally, a special type is available for checking equality between a "
+"BitVector and a bit constant pattern that contains holes defined like a "
+"bitmask (bit positions not to be compared by the equality expression)."
+msgstr "最后，还有一种特殊类型可用于检查 BitVector 是否符合位常量的指定模式，该模式包含像位掩码一样定义的空洞（位的位置不通过等式进行比较）。"
+
+#: ../../SpinalHDL/Data types/index.rst:34
+msgid ""
+"Here is an example to show how you can achieve this (note the use of 'M' "
+"prefix) :"
+msgstr "下面是一个示例，展示如何实现此目的（注意使用“M”前缀）："
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/assignment_overlap.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/assignment_overlap.po
new file mode 100644
index 00000000000..7458e5011fe
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/assignment_overlap.po	
@@ -0,0 +1,53 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsassignment_overlap/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:3
+msgid "Assignment overlap"
+msgstr "赋值覆盖(Assignment overlap)"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:8
+msgid ""
+"SpinalHDL will check that no signal assignment completely erases a previous "
+"one."
+msgstr "SpinalHDL将检查，没有任何信号赋值会完全擦除前面的信号赋值。"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:13
+msgid "The following code"
+msgstr "下面的代码"
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:23
+msgid "will throw the following error:"
+msgstr "会出现以下错误："
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:32
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/assignment_overlap.rst:44
+msgid ""
+"But in the case when you really want to override the previous assignment (as"
+" there are times when overriding makes sense), you can do the following:"
+msgstr "但是，如果您确实想要覆盖先前的赋值（因为有时覆盖是有意义的），您可以执行以下"
+"操作："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/clock_crossing_violation.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/clock_crossing_violation.po
new file mode 100644
index 00000000000..44fdee87502
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/clock_crossing_violation.po	
@@ -0,0 +1,110 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsclock_crossing_violation/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:3
+msgid "Clock crossing violation"
+msgstr "跨时钟域违例(Clock crossing violation)"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:8
+msgid ""
+"SpinalHDL will check that every register of your design only depends "
+"(through combinational logic paths) on registers which use the same or a "
+"synchronous clock domain."
+msgstr "SpinalHDL将检查您的设计中的每个寄存器是否仅（通过组合逻辑路径）与相同或同步时"
+"钟域的寄存器连接。"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:13
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:28
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:42
+msgid "There are multiple possible fixes, listed below:"
+msgstr "有多种可能的修复方法，如下所示："
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:44
+msgid ":ref:`crossClockDomain tags <crossclockdomain-tag>`"
+msgstr ":ref:`crossClockDomain 标签 <crossclockdomain-tag>`"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:45
+msgid ":ref:`setSynchronousWith method <setsynchronouswith>`"
+msgstr ":ref:`setSynchronousWith 方法 <setsynchronouswith>`"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:46
+msgid ":ref:`BufferCC type <buffercc>`"
+msgstr ":ref:`BufferCC 类型 <buffercc>`"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:51
+msgid "crossClockDomain tag"
+msgstr "crossClockDomain标签"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:53
+msgid ""
+"The ``crossClockDomain`` tag can be used to communicate \"It's alright, "
+"don't panic about this specific clock crossing\" to the SpinalHDL compiler."
+msgstr ""
+"标签 ``crossClockDomain`` 可用于向 SpinalHDL "
+"编译器传达“没关系，不要对这个特定的跨时钟域操作感到恐慌”的信息。"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:72
+msgid "setSynchronousWith"
+msgstr "setSynchronousWith"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:74
+msgid ""
+"You can also specify that two clock domains are synchronous together by "
+"using the ``setSynchronousWith`` method of one of the ``ClockDomain`` "
+"objects."
+msgstr "您还可以使用 ``ClockDomain`` 对象的 ``setSynchronousWith`` "
+"方法指定两个时钟域同步。"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:94
+msgid "BufferCC"
+msgstr "BufferCC"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:96
+msgid ""
+"When exchanging single-bit signals (such as ``Bool`` types), or Gray-coded "
+"values, you can use ``BufferCC`` to safely cross different ``ClockDomain`` "
+"regions."
+msgstr ""
+"当交换单比特信号（如 ``Bool`` 类型）或格雷码时，您可以使用 ``BufferCC`` "
+"安全地跨不同的 ``ClockDomain`` 时钟域。"
+
+#: ../../SpinalHDL/Design errors/clock_crossing_violation.rst:99
+msgid ""
+"Do not use ``BufferCC`` with multi-bit signals, as there is a risk of "
+"corrupted reads on the receiving side if the clocks are asynchronous. See "
+"the :ref:`Clock Domains <clock_domain>` page for more details."
+msgstr ""
+"不要将 ``BufferCC`` 用于多比特信号，因为如果时钟异步，那么接收端会存在读取损"
+"坏的风险。有关更多详细信息，请参阅 :ref:`时钟域 <clock_domain>` 页面。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/combinatorial_loop.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/combinatorial_loop.po
new file mode 100644
index 00000000000..f1c7180e60b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/combinatorial_loop.po	
@@ -0,0 +1,72 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorscombinatorial_loop/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:3
+msgid "Combinatorial loop"
+msgstr "组合逻辑环(Combinatorial loop)"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:8
+msgid ""
+"SpinalHDL will check that there are no combinatorial loops in the design."
+msgstr "SpinalHDL将检查设计中是否存在组合逻辑环。"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:13
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:29
+msgid "will throw :"
+msgstr "会出现："
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:47
+msgid "A possible fix could be:"
+msgstr "一个可能的修复方式是："
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:64
+msgid "False-positives"
+msgstr "误报"
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:66
+msgid ""
+"It should be said that SpinalHDL's algorithm to detect combinatorial loops "
+"can be pessimistic, and it may give false positives. If it is giving a false"
+" positive, you can manually disable loop checking on one signal of the loop "
+"like so:"
+msgstr "SpinalHDL检测组合逻辑环的算法可能是悲观的，并且可能会给出误报。如果出现误报，"
+"您可以手动禁用对某一信号的逻辑环的检查，如下所示："
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:77
+msgid "could be fixed by :"
+msgstr "可以通过以下方式修复："
+
+#: ../../source/SpinalHDL/Design errors/combinatorial_loop.rst:87
+msgid ""
+"It should also be said that assignments such as ``(a(1) := a(0))`` can make "
+"some tools like `Verilator <https://www.veripool.org/wiki/verilator>`_ "
+"unhappy. It may be better to use a ``Vec(Bool(), 8)`` in this case."
+msgstr ""
+"还应该指出，诸如 ``(a(1) := a(0))`` 之类的赋值可能会使一些工具如 `Verilator "
+"<https://www.veripool.org/wiki/verilator>`_ 无法适配。在这种情况下，使用 "
+"``Vec(Bool(), 8)`` 可能更好。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/hierarchy_violation.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/hierarchy_violation.po
new file mode 100644
index 00000000000..26610f8e8ad
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/hierarchy_violation.po	
@@ -0,0 +1,82 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorshierarchy_violation/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:3
+msgid "Hierarchy violation"
+msgstr "层次违例(Hierarchy violation)"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:8
+msgid ""
+"SpinalHDL will check that signals are never accessed outside of the current "
+"component's scope."
+msgstr "SpinalHDL将会检查当前层次设计的信号不会访问到该组件的外部区域。"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:10
+msgid "The following signals can be read inside a component:"
+msgstr "以下信号可以在组件内部读取："
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:12
+#: errors/hierarchy_violation.rst:18
+msgid "All directionless signals defined in the current component"
+msgstr "当前组件中定义的所有无方向信号"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:13
+msgid "All in/out/inout signals of the current component"
+msgstr "当前组件的所有in/out/inout信号"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:14
+msgid "All in/out/inout signals of child components"
+msgstr "子组件的所有in/out/inout信号"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:16
+msgid ""
+"In addition, the following signals can be assigned to inside of a component:"
+msgstr "同时，以下信号可以在组件内部赋值："
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:19
+msgid "All out/inout signals of the current component"
+msgstr "当前组件的所有out/inout信号"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:20
+msgid "All in/inout signals of child components"
+msgstr "子组件的所有in/inout信号"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:22
+msgid ""
+"If a ``HIERARCHY VIOLATION`` error appears, it means that one of the above "
+"rules was violated."
+msgstr "如果出现 ``HIERARCHY VIOLATION`` 错误，则意味着违反了上述规则之一。"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:25
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:27
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:39
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/hierarchy_violation.rst:48
+msgid "A fix could be :"
+msgstr "一个可能的修复方法是："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/index.po
new file mode 100644
index 00000000000..0c387c9f2a7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/index.po	
@@ -0,0 +1,82 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-13 12:07+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../SpinalHDL/Design errors/index.rst:3
+msgid "Design errors"
+msgstr "设计错误"
+
+#: ../../SpinalHDL/Design errors/index.rst:5
+msgid ""
+"The SpinalHDL compiler will perform many checks on your design to be sure "
+"that the generated VHDL/Verilog will be safe for simulation and synthesis. "
+"Basically, it should not be possible to generate a broken VHDL/Verilog "
+"design. Below is a non-exhaustive list of SpinalHDL checks:"
+msgstr ""
+"SpinalHDL编译器将对您的设计执行许多检查，以确保生成的 VHDL/Verilog "
+"对于仿真和综合来说是安全的。总体来说应该不可能生成有错误的VHDL/"
+"Verilog设计。以下是SpinalHDL检查的非详尽列表："
+
+#: ../../SpinalHDL/Design errors/index.rst:9
+msgid "Assignment overlapping"
+msgstr "赋值覆盖(Assignment overlapping)"
+
+#: ../../SpinalHDL/Design errors/index.rst:10
+msgid "Clock crossing"
+msgstr "跨时钟域(Clock crossing)"
+
+#: ../../SpinalHDL/Design errors/index.rst:11
+msgid "Hierarchy violation"
+msgstr "层次违例(Hierarchy violation)"
+
+#: ../../SpinalHDL/Design errors/index.rst:12
+msgid "Combinatorial loops"
+msgstr "组合逻辑环(Combinatorial loops)"
+
+#: ../../SpinalHDL/Design errors/index.rst:13
+msgid "Latches"
+msgstr "锁存器(Latches)"
+
+#: ../../SpinalHDL/Design errors/index.rst:14
+msgid "Undriven signals"
+msgstr "无驱动信号(Undriven signals)"
+
+#: ../../SpinalHDL/Design errors/index.rst:15
+msgid "Width mismatch"
+msgstr "位宽不匹配(Width mismatch)"
+
+#: ../../SpinalHDL/Design errors/index.rst:16
+msgid "Unreachable switch statements"
+msgstr "无法访问的switch语句(Unreachable switch statements)"
+
+#: ../../SpinalHDL/Design errors/index.rst:18
+msgid ""
+"On each SpinalHDL error report, you will find a stack trace, which can be "
+"useful to accurately find out where the design error is. These design checks"
+" may look like overkill at first glance, but they becomes invaluable as soon"
+" as you start to move away from the traditional way of doing hardware "
+"description."
+msgstr ""
+"在每个SpinalHDL错误报告中，您都会找到堆栈跟踪，这对于准确找出设计错误在哪里非"
+"常有用。乍一看，这些设计检查可能有点矫枉过正，但一旦您开始远离传统的硬件描述"
+"方式，它们就变得非常宝贵。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/iobundle.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/iobundle.po
new file mode 100644
index 00000000000..0f9c171e9b7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/iobundle.po	
@@ -0,0 +1,57 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsiobundle/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:3
+msgid "IO bundle"
+msgstr "IO线束"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:8
+msgid ""
+"SpinalHDL will check that each ``io`` bundle contains only in/out/inout "
+"signals. Other kinds of signals are called directionless signals."
+msgstr "SpinalHDL 将检查每个 ``io`` "
+"线束是否仅包含输入/输出/双向信号。其他类型的信号称为无方向信号。"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:12
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:14
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:24
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:33
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../SpinalHDL/Design errors/iobundle.rst:43
+msgid ""
+"But if for meta hardware description reasons you really want ``io.a`` to be "
+"directionless, you can do:"
+msgstr "但是，如果出于元硬件描述的原因，您确实希望 ``io.a`` 没有方向，您可以这样做："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/latch_detected.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/latch_detected.po
new file mode 100644
index 00000000000..59e6d62dcca
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/latch_detected.po	
@@ -0,0 +1,70 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorslatch_detected/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:3
+msgid "Latch detected"
+msgstr "锁存器检测(Latch detected)"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:8
+msgid ""
+"SpinalHDL will check that no combinational signals will infer a latch during"
+" synthesis. In other words, this is a check that no combinational signals "
+"are partially assigned."
+msgstr "SpinalHDL 将检查在综合期间没有组合信号会引入锁存器。换句话说，这是检查没有组"
+"合信号被部分赋值。"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:12
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:14
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:27
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:36
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:51
+msgid "Due to mux"
+msgstr "因多路复用器产生的错误"
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:53
+msgid ""
+"Another reason for a latch being detected is often a non-exhaustive "
+"``mux``/``muxList`` statement with a missing default:"
+msgstr "检测到锁存器的另一个原因通常是不详尽、缺少默认值的 ``mux``/``muxList`` 语句："
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:64
+msgid "which can be fixed by adding the missing case (or a default case):"
+msgstr "可以通过添加缺失的条件（或默认条件）来修复："
+
+#: ../../source/SpinalHDL/Design errors/latch_detected.rst:74
+msgid ""
+"In e.g. width generic code it is often a better solution to use "
+"``muxListDc`` as this will not generate an error for those cases were a "
+"default is not needed:"
+msgstr "例如对于通用位宽代码，使用 ``muxListDc`` "
+"通常是更好的解决方案，因为对于不需要默认值的情况，这不会生成错误："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/no_driver_on.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/no_driver_on.po
new file mode 100644
index 00000000000..c8f6b9f190d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/no_driver_on.po	
@@ -0,0 +1,46 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsno_driver_on/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:3
+msgid "No driver on"
+msgstr "无驱动检测(No driver on)"
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:8
+msgid ""
+"SpinalHDL will check that all combinational signals which have an impact on "
+"the design are assigned by something."
+msgstr "SpinalHDL 将检查所有对设计有影响的组合信号是否被赋值。"
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:13
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:23
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/no_driver_on.rst:32
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/nullpointerexception.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/nullpointerexception.po
new file mode 100644
index 00000000000..b7e2774c76c
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/nullpointerexception.po	
@@ -0,0 +1,71 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsnullpointerexception/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:5
+msgid "NullPointerException"
+msgstr "空指针异常(NullPointerException)"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:8
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:10
+msgid ""
+"``NullPointerException`` is a Scala runtime reported error which can happen "
+"when a variable is accessed before it has been initialized."
+msgstr "``NullPointerException`` 是 Scala "
+"运行时报告的错误，当变量在初始化之前被访问时可能会发生这种错误。"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:13
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:15
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:24
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:33
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:43
+msgid "Issue explanation"
+msgstr "问题说明"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:45
+msgid ""
+"SpinalHDL is not a language, it is a Scala library, which means that it "
+"obeys the same rules as the Scala general purpose programming language."
+msgstr "SpinalHDL 不是一种语言，它是一个 Scala 库，这意味着它遵循与 Scala "
+"通用编程语言相同的规则。"
+
+#: ../../source/SpinalHDL/Design errors/nullpointerexception.rst:47
+msgid ""
+"When running the above SpinalHDL hardware description to generate the "
+"corresponding VHDL/Verilog RTL, the SpinalHDL hardware description will be "
+"executed as a Scala program, and ``a`` will be a null reference until the "
+"program executes ``val a = UInt(8 bits)``, so trying to assign to it before "
+"then will result in a ``NullPointerException``."
+msgstr ""
+"当运行上面的 SpinalHDL 硬件描述生成相应的 VHDL/Verilog RTL 时，SpinalHDL "
+"硬件描述将作为 Scala 程序执行，并且 ``a`` 将是一个空引用，直到程序执行 ``val "
+"a = UInt(8 bits)`` ，因此试图在此之前赋值给它将导致 ``NullPointerException`` "
+"。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/out_of_range_constant.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/out_of_range_constant.po
new file mode 100644
index 00000000000..e7618f87774
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/out_of_range_constant.po	
@@ -0,0 +1,66 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsout_of_range_constant/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:3
+msgid "Out of Range Constant"
+msgstr "超出范围的常数(Out of Range Constant)"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:8
+msgid ""
+"SpinalHDL checks that in comparisons with literals the literal is not wider "
+"than the value compared to."
+msgstr "SpinalHDL会检查，当一个值和一个常量对比时，该值是否具有更宽的位数。"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:13
+msgid "For example the following code:"
+msgstr "例如下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:20
+msgid "Will result in the following error:"
+msgstr "会导致如下错误："
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:30
+msgid "Specifying exceptions"
+msgstr "特殊情况"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:32
+msgid ""
+"In some cases, because of the design parametrization, it can make sense to "
+"compare a value to a larger constant and get a statically known "
+"``True/False`` result."
+msgstr "在某些情况下，由于设计参数化，将值与更大的常量进行比较并获得静态已知的 ``"
+"True/False`` 结果是有意义的。"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:34
+msgid ""
+"You have the option to specifically whitelist one instance of a comparison "
+"with an out of range constant."
+msgstr "您可以选择将与超出范围的常量进行比较的一个实例列入专门的白名单。"
+
+#: ../../source/SpinalHDL/Design errors/out_of_range_constant.rst:42
+msgid ""
+"Alternatively, you can allow comparisons to out of range constants for the "
+"whole design."
+msgstr "或者，您可以允许整个设计对超出范围的常量进行比较。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/register_defined_as_component_input.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/register_defined_as_component_input.po
new file mode 100644
index 00000000000..9bee2d6ad31
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/register_defined_as_component_input.po	
@@ -0,0 +1,67 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsregister_defined_as_component_input/"
+"zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:3
+msgid "Register defined as component input"
+msgstr "定义为组件输入的寄存器(Register defined as component input)"
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:8
+msgid ""
+"In SpinalHDL, you are not allowed to define a component that has a register "
+"as an input. The reasoning behind this is to prevent surprises when the user"
+" tries to drive the inputs of child components with the registered signal. "
+"If a registered input is desired, you will need to declare the unregistered "
+"input in the ``io`` bundle, and register the signal in the body of the "
+"component."
+msgstr ""
+"在SpinalHDL中，用户不被允许定义一个将寄存器作为输入的组件。原因是为了防止用户"
+"试图用寄存器信号作为子组件的输入驱动时出现意外。如果确实需要一个寄存器输入，"
+"用户可以在 ``io`` 线束中先定义一个非寄存器输入, "
+"随后在组件内部对其添加寄存器。"
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:13
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:15
+msgid "The following code :"
+msgstr "以下代码："
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:25
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:34
+msgid "A fix could be :"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design
+#: errors/register_defined_as_component_input.rst:44
+msgid "If a registered ``a`` is required, it can be done like so:"
+msgstr "如果需要一个寄存器信号 ``a`` ，可以这样做："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/scope_violation.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/scope_violation.po
new file mode 100644
index 00000000000..44be2d388e7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/scope_violation.po	
@@ -0,0 +1,48 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsscope_violation/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:3
+msgid "Scope violation"
+msgstr "作用域违例(Scope violation)"
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:8
+msgid ""
+"SpinalHDL will check that there are no signals assigned outside the scope "
+"they are defined in. This error isn't easy to trigger as it requires some "
+"specific meta hardware description tricks."
+msgstr "SpinalHDL将会检查没有信号会在超出其定义的作用域之外被赋值使用。这个错误不容易"
+"触发，因为它需要一些特定的元硬件描述技巧。"
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:12
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:14
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:28
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/scope_violation.rst:37
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po
new file mode 100644
index 00000000000..f59e647536e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po	
@@ -0,0 +1,76 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsspinal_cant_clone/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:3
+msgid "Spinal can't clone class"
+msgstr "Spinal无法克隆类(Spinal can't clone class)"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:8
+msgid ""
+"This error happens when SpinalHDL wants to create a new datatype instance "
+"via the ``cloneOf`` function but isn't able to do it. The reason for this is"
+" nearly always because it can't retrieve the construction parameters of a "
+"``Bundle``."
+msgstr ""
+"当SpinalHDL想要通过 ``cloneOf`` "
+"函数创建一个新的数据类型实例，但做不到这一点时，就会出现此错误。"
+"出现这种情况的原因几乎都是因为它无法检索 ``Bundle`` 的构造参数。"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:12
+msgid "Example 1"
+msgstr "例子1"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:14
+#: errors/spinal_cant_clone.rst:54
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:27
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:39
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:52
+msgid "Example 2"
+msgstr "例子2"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:72
+msgid "raises an exeption:"
+msgstr "报错："
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:78
+msgid ""
+"In this case, a solution is to override the clone function to propagate the "
+"implicit parameter."
+msgstr "在这种情况下，一种解决方案是覆盖克隆函数以传递隐式参数。"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:90
+msgid ""
+"We need to clone the hardware element, not the eventually assigned value in "
+"it."
+msgstr "我们需要克隆的是硬件的单元，而不是最终在其中赋值的值。"
+
+#: ../../source/SpinalHDL/Design errors/spinal_cant_clone.rst:94
+msgid "An alternative is to used :ref:`ScopeProperty <scopeproperty>`."
+msgstr "另一种方法是使用 :ref:`ScopeProperty <scopeproperty>`。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unassigned_register.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unassigned_register.po
new file mode 100644
index 00000000000..72de5b4b640
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unassigned_register.po	
@@ -0,0 +1,67 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsunassigned_register/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:3
+msgid "Unassigned register"
+msgstr "未赋值的寄存器(Unassigned register)"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:8
+msgid ""
+"SpinalHDL will check that all registers which impact the design have been "
+"assigned somewhere."
+msgstr "SpinalHDL将检查所有影响设计的寄存器是否已在某处被赋值。"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:13
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:23
+#: errors/unassigned_register.rst:59
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:32
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:44
+msgid "Register with only init"
+msgstr "只有初始化(init)的寄存器"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:46
+msgid ""
+"In some cases, because of the design parameterization, it could make sense "
+"to generate a register which has no assignment but only an ``init`` "
+"statement."
+msgstr "在某些情况下，由于设计参数化，生成一个没有赋值而只有 ``init`` "
+"语句的寄存器可能是有意义的。"
+
+#: ../../source/SpinalHDL/Design errors/unassigned_register.rst:68
+msgid ""
+"To fix it, you can ask SpinalHDL to transform the register into a "
+"combinational one if no assignment is present but it has an ``init`` "
+"statement:"
+msgstr "要修复这个问题，如果寄存器有一个 ``init`` "
+"语句但没有赋值，你可以让SpinalHDL将该未赋值的寄存器转换为组合逻辑："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unreachable_is_statement.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unreachable_is_statement.po
new file mode 100644
index 00000000000..a17caf96cdf
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/unreachable_is_statement.po	
@@ -0,0 +1,46 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorsunreachable_is_statement/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:3
+msgid "Unreachable is statement"
+msgstr "无法访问的is语句(Unreachable is statement)"
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:8
+msgid ""
+"SpinalHDL will check to ensure that all ``is`` statements in a ``switch`` "
+"are reachable."
+msgstr "SpinalHDL将确保 ``switch`` 中的所有 ``is`` 语句均可访问。"
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:11
+msgid "Example"
+msgstr "示例"
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:13
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:29
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/unreachable_is_statement.rst:38
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/width_mismatch.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/width_mismatch.po
new file mode 100644
index 00000000000..66c9ab25da7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/width_mismatch.po	
@@ -0,0 +1,53 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldesign-errorswidth_mismatch/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:3
+msgid "Width mismatch"
+msgstr "位宽不匹配(Width mismatch)"
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:8
+msgid ""
+"SpinalHDL will check that operators and signals on the left and right side "
+"of assignments have the same widths."
+msgstr "SpinalHDL将检查赋值左侧和右侧的运算操作和信号具有相同的位宽。"
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:11
+msgid "Assignment example"
+msgstr "赋值示例"
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:13
+#: errors/width_mismatch.rst:45
+msgid "The following code:"
+msgstr "下面的代码："
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:23
+#: errors/width_mismatch.rst:55
+msgid "will throw:"
+msgstr "会报错："
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:32
+#: errors/width_mismatch.rst:67
+msgid "A fix could be:"
+msgstr "一个可能的修复方法是："
+
+#: ../../source/SpinalHDL/Design errors/width_mismatch.rst:43
+msgid "Operator example"
+msgstr "运算操作示例"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/bus_slave_factory_impl.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/bus_slave_factory_impl.po
new file mode 100644
index 00000000000..af1b31eb07b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/bus_slave_factory_impl.po	
@@ -0,0 +1,426 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-10 17:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areabus_slave_factory_impl/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:7
+msgid "Bus Slave Factory Implementation"
+msgstr "总线从端（Factory）实现"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:12
+msgid ""
+"This page will document the implementation of the BusSlaveFactory tool and "
+"one of those variant. You can get more information about the functionality "
+"of that tool :ref:`here <bus_slave_factory>`."
+msgstr ""
+"本页将记录 BusSlaveFactory 工具及其变体之一的实现。"
+"您可以在此处获取有关该工具功能的更多信息 :ref:`here <bus_slave_factory>`。"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:15
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:17
+msgid "The class diagram is the following :"
+msgstr "类图如下："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:23
+msgid ""
+"The ``BusSlaveFactory`` abstract class define minimum requirements that each"
+" implementation of it should provide :"
+msgstr "``BusSlaveFactory`` 抽象类定义了每个实现应提供的最低要求："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:29
+#: area/bus_slave_factory_impl.rst:52
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:30
+#: area/bus_slave_factory_impl.rst:54 area/bus_slave_factory_impl.rst:340
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:31
+msgid "busDataWidth"
+msgstr "busDataWidth"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:32
+msgid "Return the data width of the bus"
+msgstr "返回总线的数据宽度"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:33
+msgid "read(that,address,bitOffset)"
+msgstr "read(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:34
+msgid ""
+"When the bus read the ``address``\\ , fill the response with ``that`` at "
+"``bitOffset``"
+msgstr "当通过总线读取地址 ``address`` 时，用 ``that`` 中 ``bitOffset`` "
+"位置的数据填充响应"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:35
+msgid "write(that,address,bitOffset)"
+msgstr "write(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:36
+msgid ""
+"When the bus write the ``address``\\ , assign ``that`` with bus's data from "
+"``bitOffset``"
+msgstr "当通过总线写入地址 ``address`` 时，将总线上 ``bitOffset`` 位置的数据赋值 "
+"``that``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:37
+msgid "onWrite(address)(doThat)"
+msgstr "onWrite(address)(doThat)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:38
+msgid "Call ``doThat`` when a write transaction occur on ``address``"
+msgstr "当 ``address`` 地址上发生写操作（出现写事务）时调用 ``doThat``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:39
+msgid "onRead(address)(doThat)"
+msgstr "onRead(address)(doThat)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:40
+msgid "Call ``doThat`` when a read transaction occur on ``address``"
+msgstr "当 ``address`` 上发生读操作（出现读事务）时调用 ``doThat``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:41
+msgid "nonStopWrite(that,bitOffset)"
+msgstr "nonStopWrite(that,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:42
+msgid "Permanently assign ``that`` by the bus write data from ``bitOffset``"
+msgstr "将通过总线写入的 ``bitOffset`` 的数据赋值到 ``that``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:45
+msgid ""
+"By using them the ``BusSlaveFactory`` should also be able to provide many "
+"utilities :"
+msgstr "通过使用它们， ``BusSlaveFactory`` 还能够提供许多实用工具："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:53
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:55
+msgid "readAndWrite(that,address,bitOffset)"
+msgstr "readAndWrite(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:57
+msgid ""
+"Make ``that`` readable and writable at ``address`` and placed at "
+"``bitOffset`` in the word"
+msgstr "使 ``that`` 信号可通过 ``address`` 地址读写，并且该信号放置在数据的 "
+"``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:58
+msgid "readMultiWord(that,address)"
+msgstr "readMultiWord(that,address)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "Create the memory mapping to read ``that`` from 'address'. :"
+msgstr "创建内存映射以从 'address' 地址读取 ``that`` 信号。 ："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid ""
+"If ``that`` is bigger than one word it extends the register on followings "
+"addresses"
+msgstr "如果 ``that`` 的位宽大于一个字（32位），它将在以下地址上扩展寄存器"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:62
+msgid "writeMultiWord(that,address)"
+msgstr "writeMultiWord(that,address)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "Create the memory mapping to write ``that`` at 'address'. :"
+msgstr "创建内存映射以通过总线 'address' 地址写入 ``that`` 信号。 ："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:66
+msgid "createWriteOnly(dataType,address,bitOffset)"
+msgstr "createWriteOnly(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:67
+#: area/bus_slave_factory_impl.rst:70
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:68
+msgid ""
+"Create a write only register of type ``dataType`` at ``address`` and placed "
+"at ``bitOffset`` in the word"
+msgstr "在 ``address`` 地址处创建一个 ``dataType`` 类型的只写寄存器，"
+"并将其放置在字中的 ``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:69
+msgid "createReadWrite(dataType,address,bitOffset)"
+msgstr "createReadWrite(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:71
+msgid ""
+"Create a read write register of type ``dataType`` at ``address`` and placed "
+"at ``bitOffset`` in the word"
+msgstr "在 ``address`` 处创建一个 ``dataType`` 类型的读写寄存器，并将其放置在字中的 "
+"``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:72
+msgid "createAndDriveFlow(dataType,address,bitOffset)"
+msgstr "createAndDriveFlow(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:73
+msgid "Flow[T]"
+msgstr "Flow[T]"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:74
+msgid ""
+"Create a writable Flow register of type ``dataType`` at ``address`` and "
+"placed at ``bitOffset`` in the word"
+msgstr ""
+"在 ``address`` 地址处创建一个 ``dataType`` 类型的可写流（Flow）寄存器，"
+"并将其放置在字中的 ``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:75
+msgid "drive(that,address,bitOffset)"
+msgstr "drive(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:77
+msgid ""
+"Drive ``that`` with a register writable at ``address`` placed at "
+"``bitOffset`` in the word"
+msgstr "使用位于 ``address`` 地址的可写寄存器中 ``bitOffset`` 位置的信号驱动 ``that``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:78
+msgid "driveAndRead(that,address,bitOffset)"
+msgstr "driveAndRead(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:80
+msgid ""
+"Drive ``that`` with a register writable and readable at ``address`` placed "
+"at ``bitOffset`` in the word"
+msgstr "使用位于 ``address`` 地址的可读写寄存器中 ``bitOffset`` 位置的信号驱动 "
+"``that``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:81
+msgid "driveFlow(that,address,bitOffset)"
+msgstr "driveFlow(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:83
+msgid ""
+"Emit on ``that`` a transaction when a write happen at ``address`` by using "
+"data placed at ``bitOffset`` in the word"
+msgstr "当对 ``address`` 地址写入时，通过使用位于 ``bitOffset`` 位的数据，在 ``that``"
+" 流（Flow）上发出事务"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "readStreamNonBlocking(that,address,"
+msgstr "readStreamNonBlocking(that,address,"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "validBitOffset,payloadBitOffset)"
+msgstr "validBitOffset,payloadBitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid ""
+"Read ``that`` and consume the transaction when a read happen at ``address``."
+msgstr "读取 ``that`` 信号并在读取 ``address`` 地址时消耗事务。"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "valid <= validBitOffset bit"
+msgstr "valid <= validBitOffset bit"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid ""
+"payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+msgstr ""
+"payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "doBitsAccumulationAndClearOnRead"
+msgstr "doBitsAccumulationAndClearOnRead"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "(that,address,bitOffset)"
+msgstr "(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "Instantiate an internal register which at each cycle do :"
+msgstr "实例化一个内部寄存器，该寄存器在每个周期执行以下操作："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid "reg := reg | that"
+msgstr "reg := reg | that"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst
+msgid ""
+"Then when a read occur, the register is cleared. This register is readable "
+"at ``address`` and placed at ``bitOffset`` in the word"
+msgstr "然后，当发生读取时，寄存器被清除。该寄存器可通过 ``address`` 地址读取，"
+"并放置在字中的 ``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:98
+msgid ""
+"About ``BusSlaveFactoryDelayed``, it's still an abstract class, but it "
+"capture each primitives (BusSlaveFactoryElement) calls into a data-model. "
+"This datamodel is one list that contain all primitives, but also a HashMap "
+"that link each address used to a list of primitives that are using it. Then "
+"when they all are collected (at the end of the current component), it do a "
+"callback that should be implemented by classes that extends it. The "
+"implementation of this callback should implement the hardware corresponding "
+"to all primitives collected."
+msgstr ""
+"关于 ``BusSlaveFactoryDelayed``，它仍然是一个抽象类，但它捕获每个原语（BusSla"
+"veFactoryElement）对数据模型的调用。该数据模型是一个包含所有原语的列表，"
+"也是一个 HashMap，它将使用的每个地址链接到正在使用它的原语列表。然后，当它们"
+"全部被收集时（在当前组件的末尾），它会执行一个回调，该回调应该由扩展它的类实"
+"现。该回调函数中实现了这个原语列表中每个原语相对应的硬件。"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:101
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:104
+msgid "BusSlaveFactory"
+msgstr "BusSlaveFactory"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:106
+msgid "Let's describe primitives abstract function :"
+msgstr "让我们来描述一下原语抽象函数："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:133
+msgid "Then let's operate the magic to implement all utile based on them :"
+msgstr "然后让我们利用这些来实现一些有用的工具："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:246
+msgid "BusSlaveFactoryDelayed"
+msgstr "BusSlaveFactoryDelayed"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:248
+msgid "Let's implement classes that will be used to store primitives :"
+msgstr "让我们实现用于存储原语的类："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:279
+msgid "Then let's implement the ``BusSlaveFactoryDelayed`` itself :"
+msgstr "然后让我们实现 ``BusSlaveFactoryDelayed`` 本身："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:330
+msgid "AvalonMMSlaveFactory"
+msgstr "AvalonMMSlaveFactory"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:332
+msgid ""
+"First let's implement the companion object that provide the compatible "
+"AvalonMM configuration object that correspond to the following table :"
+msgstr "首先，让我们实现提供兼容 AvalonMM 配置对象的伴随对象，对应于下表："
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:338
+msgid "Pin name"
+msgstr "信号名称"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:339
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:341
+msgid "read"
+msgstr "read"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:342
+#: area/bus_slave_factory_impl.rst:345 area/bus_slave_factory_impl.rst:354
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:343
+msgid "High one cycle to produce a read request"
+msgstr "保持一个周期高电平来产生一个读请求"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:344
+msgid "write"
+msgstr "write"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:346
+msgid "High one cycle to produce a write request"
+msgstr "保持一个周期高电平来产生一个写请求"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:347
+msgid "address"
+msgstr "address"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:348
+msgid "UInt(addressWidth bits)"
+msgstr "UInt(addressWidth bits)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:349
+msgid "Byte granularity but word aligned"
+msgstr "字节为粒度但是字对齐的"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:350
+msgid "writeData"
+msgstr "writeData"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:351
+#: area/bus_slave_factory_impl.rst:357
+msgid "Bits(dataWidth bits)"
+msgstr "Bits(dataWidth bits)"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:353
+msgid "readDataValid"
+msgstr "readDataValid"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:355
+msgid "High to respond a read command"
+msgstr "保持高电平来响应读命令"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:356
+msgid "readData"
+msgstr "readData"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:358
+msgid "Valid when readDataValid is high"
+msgstr "readDataValid 为高时有效"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:378
+msgid "Then, let's implement the AvalonMMSlaveFactory itself."
+msgstr "然后，让我们实现 AvalonMMSlaveFactory 本身。"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:429
+msgid "Conclusion"
+msgstr "结论"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:431
+msgid ""
+"That's all, you can check one example that use this ``Apb3SlaveFactory`` to "
+"create an Apb3UartCtrl :ref:`here <memory_mapped_uart>`."
+msgstr ""
+"就这些了，您可以在此处查看一个使用 ``Apb3SlaveFactory`` 来创建 Apb3UartCtrl "
+"的 :ref:`示例 <memory_mapped_uart>`。"
+
+#: ../../SpinalHDL/Developers area/bus_slave_factory_impl.rst:433
+msgid ""
+"If you want to add the support of a new memory bus, it's very simple you "
+"just need to implement another variation of the ``BusSlaveFactoryDelayed`` "
+"trait. The ``Apb3SlaveFactory`` is probably a good starting point :D"
+msgstr ""
+"如果您想添加对新内存总线的支持，非常简单，您只需继承、实现 "
+"``BusSlaveFactoryDelayed`` 特征（trait）的另一个变体即可。 "
+"``Apb3SlaveFactory`` 可能是一个很好的参考：D"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/howtodocument.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/howtodocument.po
new file mode 100644
index 00000000000..8640f0499f9
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/howtodocument.po	
@@ -0,0 +1,181 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-16 16:35+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areahowtodocument/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:2
+msgid "How to HACK this documentation"
+msgstr "如何修改本文档"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:3
+msgid ""
+"If you want to add your page to this documentation you need to add your "
+"source file in the appropriate section. I opted to create a structure that "
+"resample the various section of the documentation, this is not strictly "
+"necessary, but for clarity sake, highly encourage."
+msgstr ""
+"如果您希望将您的页面添加到此文档中，需要将源文件添加到适当的部分。我选择创建"
+"一个结构来重新整理文档的各个部分，这并不是严格必要的，但为了清晰性，强烈建议"
+"这样做。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:8
+msgid ""
+"This documentation uses a recursive index tree: every folder have a special "
+"``index.rst`` files that tell sphinx which file, and in what order to put it"
+" in the documentation tree."
+msgstr ""
+"本文档使用递归索引树：每个文件夹都有一个特殊的 ``index.rst`` 文件，告诉 "
+"sphinx 哪个文件存在、以什么顺序将其放入文档树中。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:12
+msgid "Title convention"
+msgstr "标题约定"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:13
+msgid ""
+"Sphinx is very smart, the document structure is deduced from how you use non"
+" alphanumerical characters (like:  ``= - ` : ' \" ~ ^ _ * + # < >``), you "
+"only need to be consistent. Still, for consistency sakes we use this "
+"progression:"
+msgstr ""
+"Sphinx 非常智能，文档结构是根据您如何使用非字母数字字符（例如：``= - ` : ' \""
+" ~ ^ _ * + # < >``）推导出来的，您只需要保持一致即可。不过，为了保持一致性，"
+"我们使用这些约定："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:17
+msgid "``=`` over and underline for section titles"
+msgstr "``=`` 用于章节标题的前后行"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:18
+msgid "``=`` underline for titles"
+msgstr "``=`` 标题的下划线"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:19
+msgid "``-`` underline for paragraph"
+msgstr "``-`` 段落的下划线"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:20
+msgid "``^`` for subparagraph"
+msgstr "``^`` 表示子段落"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:23
+msgid "Wavedrom integration"
+msgstr "Wavedrom 的集成"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:24
+msgid ""
+"This documentation makes use of the ``sphinxcontrib-wavedrom`` plugin, So "
+"you can specify a timing diagram, or a register description with the "
+"WaveJSON_ syntax like so:"
+msgstr ""
+"本文档使用了 ``sphinxcontrib-wavedrom`` 插件，因此您可以使用 WaveJSON_ "
+"语法指定时序图或寄存器描述，如下所示："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:44
+msgid "and you get:"
+msgstr "你可以得到："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:62
+msgid ""
+"if you want the Wavedrom diagram to be present in the pdf export, you need "
+"to use the \"non relaxed\" JSON dialect. long story short, no javascript "
+"code and use ``\"`` around key value (Eg. ``\"name\"``)."
+msgstr ""
+"如果您希望 Wavedrom 图出现在 pdf 导出中，则需要使用 \"non relaxed\" JSON "
+"方言。长话短说，就是没有使用 javascript 代码并使用 ``\"`` 包围键值（例如 ``"
+"\"name\"`` ）。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:65
+msgid "you can describe register mapping with the same syntax:"
+msgstr "您可以使用相同的语法描述寄存器映射："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:88
+msgid "New section"
+msgstr "新章节"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:89
+msgid ""
+"if you want to add a new  section you need to specify in the top index, the "
+"index file of the new section. I suggest to name the folder like the section"
+" name, but is not required; Sphinx will take the name of the section from "
+"the title of the index file."
+msgstr ""
+"如果你想添加一个新的节，你需要在顶部索引中指定新节的索引文件。我建议将文件夹"
+"命名为节名称，但这不是必需的； Sphinx 将从索引文件的标题中获取该部分的名称。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:94
+msgid "example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:95
+msgid ""
+"I want to document the new feature in SpinalHDL, and I want to create a "
+"section for it; let's call it ``Cheese``"
+msgstr "我想记录 SpinalHDL 中的新功能，并且我想为其创建一个章节；我们称之为 "
+"``Cheese``"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:97
+msgid ""
+"So I need to create a folder named ``Cheese`` (name is not important), and "
+"in it create a index file like:"
+msgstr "所以我需要创建一个名为 ``Cheese`` "
+"的文件夹（名称并不重要），并在其中创建一个索引文件，例如："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:112
+msgid ""
+"The ``.. toctree::`` directive accept some parameters, in this case "
+"``:glob:`` makes so you can use the ``*`` to include all the remaining "
+"files."
+msgstr "``.. toctree::`` 指令接受一些参数，在本例中 ``:glob:`` 使您可以使用 ``*`` "
+"包含所有剩余文件。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:116
+msgid ""
+"The file path is relative to the index file, if you want to specify the "
+"absolute path, you need to prepend ``/``"
+msgstr "文件路径是相对于索引文件的，如果要指定绝对路径，需要在前面加上``/``"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:119
+msgid ""
+"``introduction.rst`` will be always the first on the list because it's "
+"specified in the index file. Other files will be included in alphabetical "
+"order."
+msgstr "``introduction.rst`` 将始终是列表中的第一个，因为它是在索引文件中指定的。其他"
+"文件将按字母顺序排列。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:122
+msgid ""
+"Now I can add the ``introduction.rst`` and other files like ``cheddar.rst``,"
+" ``stilton.rst``, etc."
+msgstr ""
+"现在我可以添加 ``introduction.rst`` 和其他文件，比如 ``cheddar."
+"rst``，``stilton.rst`` 等。"
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:124
+msgid ""
+"The only thing remaining to do is to add cheese to the top index file like "
+"so:"
+msgstr "剩下要做的唯一一件事就是将 ``cheese`` 添加到顶部索引文件中，如下所示："
+
+#: ../../SpinalHDL/Developers area/howtodocument.rst:151
+msgid ""
+"that's it, now you can add all you want in cheese and all pages will show up"
+" in the documentation."
+msgstr "就是这样，现在您可以在 ``cheese`` "
+"中添加您想要的所有内容，所有页面都将显示在文档中。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/index.po
new file mode 100644
index 00000000000..069c89494b1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-16 16:35+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areaindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Developers area/index.rst:3
+msgid "Developers area"
+msgstr "开发者专区"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/mill support.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/mill support.po
new file mode 100644
index 00000000000..87d969b2f70
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/mill support.po	
@@ -0,0 +1,61 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-16 16:35+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areamill-support/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:2
+msgid "Build through Mill"
+msgstr "通过Mill构建（输出）"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:4
+msgid ""
+"SpinalHDL itself can be built with Mill.  This is an alternative to the Sbt "
+"build tool that can be found at Introduction_to_Mill_. It can "
+"compile/test/publishLocal the existing modules. Build through mill can be "
+"much faster than Sbt, which is useful while debugging."
+msgstr ""
+"SpinalHDL 本身可以用 Mill 构建。这是一个 Sbt 构建工具的替代品，可以在 "
+"Introduction_to_Mill_ 中找到。它可以编译/测试/发布本地现有模块。通过 mill "
+"构建可以比 Sbt 快得多，这在调试时很有用。"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:10
+msgid "Compile the library"
+msgstr "编译SpinalHDL库"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:18
+msgid "Run all test suites"
+msgstr "运行所有测试套件"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:26
+msgid "Run a specified test suite"
+msgstr "运行指定的测试套件"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:34
+msgid "Run a specified App"
+msgstr "运行指定程序（App）"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:42
+msgid "Publish locally"
+msgstr "本地发布"
+
+#: ../../SpinalHDL/Developers area/mill support.rst:44
+msgid ""
+"Mill can also publish the library to the local ivy2 repository as a ``dev`` "
+"version."
+msgstr "Mill 还可以将库作为 ``dev`` 版本发布到本地 ivy2 存储库。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po
new file mode 100644
index 00000000000..b79f9487e95
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po	
@@ -0,0 +1,301 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areaspinalhdl_datamodel/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:3
+msgid "SpinalHDL internal datamodel"
+msgstr "SpinalHDL 内部数据模型"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:12
+msgid ""
+"This page provides documentation on the internal data structure utilized by "
+"SpinalHDL for storing and modifying the netlist described by users via the "
+"SpinalHDL API."
+msgstr "本页面提供有关 SpinalHDL 使用的内部数据结构的文档，用于存储和修改用户通过 "
+"SpinalHDL API 描述的网表。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:15
+msgid "General structure"
+msgstr "总体结构"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:17
+msgid "The following diagrams follow the UML nomenclature :"
+msgstr "下图遵循 UML 命名法："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:19
+msgid "A link with a white arrow mean \"base extend target\""
+msgstr "带有白色箭头的链接表示“源继承目标”"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:20
+msgid "A link with a black diamond mean \"base contains target\""
+msgstr "带有黑色菱形的链接表示“源包含目标”"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:21
+msgid "A link with a white diamond mean \"base has a reference to target\""
+msgstr "带有白色菱形的链接意味着“源中有一个对目标的引用”"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:22
+msgid "The * symbol mean \"multiple\""
+msgstr "``* `` 符号表示“多个”"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:24
+msgid ""
+"The majority of the data structures are stored using double-linked lists, "
+"which facilitate the insertion and removal of elements."
+msgstr "大多数数据结构都是使用双向链表存储，这方便了元素的插入和删除。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:26
+msgid "There is a diagram of the global data structure :"
+msgstr "全局数据结构图如下："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:31
+msgid "And here more details about the `Statement` class :"
+msgstr "这里是关于 `Statement` 类的更多细节："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:36
+msgid ""
+"In general, when an element within the data model utilizes other expressions"
+" or statements, that element typically includes functions for iterating over"
+" these usages. For example, each Expression is equipped with a "
+"*foreachExpression* function."
+msgstr ""
+"一般来说，当数据模型内的元素使用其他表达式或语句时，该元素通常包括迭代这些用"
+"法的函数。例如，每个表达式都配有一个 *foreachExpression* 函数。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:38
+msgid ""
+"When using these iteration functions, you have the option to remove the "
+"current element from the tree."
+msgstr "使用这些迭代函数时，您也可以从树中删除当前元素。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:40
+msgid ""
+"Additionally, as a side note, while the *foreachXXX* functions iterate only "
+"one level deep, there are often corresponding *walkXXX* functions that "
+"perform recursive iteration. For instance, using "
+"*myExpression.walkExpression* on *((a+b)+c)+d* will traverse the entire tree"
+" of addition operations."
+msgstr ""
+"此外，作为旁注，虽然 *foreachXXX* 函数仅迭代一层深度，但通常有相应的 "
+"*walkXXX* 函数执行递归迭代。例如，在 *((a+b)+c)+d* 表达式上使用 *myExpression"
+".walkExpression* ，这将遍历整个加法运算树。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:42
+msgid ""
+"There are also utilities like *myExpression.remapExpressions(Expression => "
+"Expression),* which iterate through all the expressions used within "
+"*myExpression* and replace them with the one you provide."
+msgstr ""
+"还有像 *myExpression.remapExpressions(Expression => Expression),* "
+"这样的实用工具，它会迭代 *myExpression* "
+"中使用的所有表达式，并将它们替换为您提供的表达式。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44
+msgid ""
+"More generaly, most of the graph checks and transformations done by "
+"SpinalHDL are located in "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala>"
+msgstr ""
+"通常来说，SpinalHDL 完成的大多数图(graph)关系检查和转换都位于 <https://github"
+".com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/"
+"Phase.scala >"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47
+msgid "Exploring the datamodel"
+msgstr "探索数据模型"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:49
+msgid ""
+"Here is an example that identifies all adders within the netlist without "
+"utilizing shortcuts. :"
+msgstr "在不使用快捷方式的情况下，识别网表中所有加法器的示例如下 ："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:109
+msgid "Which will produces :"
+msgstr "这将生成："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:127
+msgid ""
+"Please note that in many cases, shortcuts are available. All the recursive "
+"processes mentioned earlier could have been replaced by a single one. :"
+msgstr "请注意，在许多情况下，都可以使用快捷方式。前面提到的所有递归过程，都可以用一"
+"个递归过程代替。 ："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:141
+msgid "Compilation Phases"
+msgstr "编译环节"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:143
+msgid ""
+"Here is the complete list of default phases, arranged in order, that are "
+"employed to modify, check, and generate Verilog code from a top-level "
+"component. :"
+msgstr "以下是按顺序排列的默认环节的完整列表，用于从顶级组件修改、检查和生成 Verilog "
+"代码。 ："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:145
+msgid ""
+"<https://github.com/SpinalHDL/SpinalHDL/blob/ec8cd9f513566b43cbbdb08d0df4dee1f0fee655/core/src/main/scala/spinal/core/internals/Phase.scala#L2487>"
+msgstr ""
+"<https://github.com/SpinalHDL/SpinalHDL/blob/"
+"ec8cd9f513566b43cbbdb08d0df4dee1f0fee655/core/src/main/scala/spinal/core/"
+"internals/Phase.scala#L2487>"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:147
+msgid ""
+"If you, as a user, add a new compilation phase by using "
+"*SpinalConfig.addTransformationPhase(new MyPhase())*, this phase will be "
+"inserted immediately after the user component elaboration process, which is "
+"relatively early in the compilation sequence. During this phase, you can "
+"still make use of the complete SpinalHDL user API to introduce elements into"
+" the netlist."
+msgstr ""
+"如果您作为用户使用 *SpinalConfig.addTransformationPhase(new MyPhase())* 添加"
+"新的编译环节，则该环节将在用户组件实例细化后立即插入，这在编译序列中相对较早"
+"。在此环节，您仍然可以使用完整的 SpinalHDL 用户 API 将元素引入网表。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:149
+msgid ""
+"If you choose to use the SpinalConfig.phasesInserters API, it's essential to"
+" exercise caution and ensure that any modifications made to the netlist "
+"align with the phases that have already been executed. For instance, if you "
+"insert your phase after the *PhaseInferWidth*, you must specify the width of"
+" each node you introduce."
+msgstr ""
+"如果您选择使用 SpinalConfig.phasesInserters "
+"API，则必须谨慎行事并确保对网表所做的任何修改与已执行的阶段保持一致。例如，"
+"如果您在 *PhaseInferWidth* 之后插入环节，则必须指定引入的每个节点的位宽。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:152
+msgid "Modifying a netlist as a user without plugins"
+msgstr "在不使用插件的情况下，以用户身份修改网表"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:154
+msgid ""
+"There are several user APIs that enable you to make modifications during the"
+" user elaboration phase. :"
+msgstr "有多个用户 API 使您能够在用户实例细化环节进行修改。 ："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:156
+msgid ""
+"mySignal.removeAssignments : Will remove all previous `:=` affecting the "
+"given signal"
+msgstr "mySignal.removeAssignments ：将删除所有先前对给定信号的赋值 `:=`"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:157
+msgid "mySignal.removeStatement : Will void the existance of the signal"
+msgstr "mySignal.removeStatement：将消除存在的信号"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:158
+msgid ""
+"mySignal.setAsDirectionLess : Will turn a in / out signal into a internal "
+"signal"
+msgstr "mySignal.setAsDirectionLess ：将输入/输出信号转换为内部信号（无方向）"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:159
+msgid ""
+"mySignal.setName : Enforce a given name on a signal (there is many other "
+"variants)"
+msgstr "mySignal.setName ：在信号上强制指定名称（还有许多其他变体）"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:160
+msgid ""
+"mySubComponent.mySignal.pull() : Will provide a readable copy of the given "
+"signal, even if that signal is somewhere else in the hierarchy"
+msgstr "mySubComponent.mySignal.pull() "
+"：将提供给定信号的可读副本，即使该信号位于层次结构中的其他位置"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:161
+msgid ""
+"myComponent.rework\\{ myCode \\} : Execute `myCode` in the context of "
+"`myComponent`, allowing modifying it with the user API"
+msgstr ""
+"myComponent.rework\\{ myCode \\} ：在 `myComponent` 上下文中执行 `myCode`，"
+"允许使用用户 API 修改它"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:163
+msgid ""
+"For example, the following code can be used to modify a top-level component "
+"by adding a three-stage shift register to each input and output of the "
+"component. This is particularly useful for synthesis testing."
+msgstr "例如，以下代码可用于修改顶级组件，向组件的每个输入和输出添加三级移位寄存器。"
+"这对于综合器测试特别有用。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:187
+msgid "You can use the code in the following manner: :"
+msgstr "您可以通过以下方式使用该代码："
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:193
+msgid ""
+"Here is a function that enables you to execute the body code as if the "
+"current component's context did not exist. This can be particularly useful "
+"for defining new signals without the influence of the current conditional "
+"scope (such as when or switch)."
+msgstr ""
+"这是一个函数，使您能够执行主体代码，就好像当前组件的上下文不存在一样。这对于"
+"定义新信号特别有用，这样信号不受当前条件范围（例如when或switch）的影响。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:223
+msgid ""
+"This kind of functionality is, for instance, employed in the VexRiscv "
+"pipeline to dynamically create components or elements as needed."
+msgstr "例如，这种功能被用在 VexRiscv 管道中，以根据需要动态创建组件或元素。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:226
+msgid "User space netlist analysis"
+msgstr "用户空间网表分析"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:228
+msgid ""
+"The SpinalHDL data model is also accessible and can be read during user-time"
+" elaboration. Here's an example that can help find the shortest logical path"
+" (in terms of clock cycles) to traverse a list of signals. In this specific "
+"case, it is being used to analyze the latency of the VexRiscv FPU design."
+msgstr ""
+"SpinalHDL 的数据模型也是可访问的，并且可以在用户实力细化时读取。下面的示例可"
+"以帮助找到遍历信号列表的最短逻辑路径（就时钟周期而言）。在本例中，它用于分析 "
+"VexRiscv FPU 设计的延迟。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:242
+msgid ""
+"Here you can find the implementation of that LatencyAnalysis tool : "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/3b87c898cb94dc08456b4fe2b1e8b145e6c86f63/lib/src/main/scala/spinal/lib/Utils.scala#L620>"
+msgstr ""
+"在这里您可以找到该 LatencyAnalysis 工具的实现：<https://github.com/SpinalHDL/"
+"SpinalHDL/blob/3b87c898cb94dc08456b4fe2b1e8b145e6c86f63/lib/src/main/scala/"
+"spinal/lib/Utils.scala#L620>"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:247
+msgid "Enumerating every ClockDomain in use"
+msgstr "遍历、枚举正在使用的每个时钟域"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:249
+msgid ""
+"In this case, this is accomplished after the elaboration process by "
+"utilizing the SpinalHDL report."
+msgstr "在本例中，这是在实例细化完成之后利用 SpinalHDL 报告完成的。"
+
+#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:285
+msgid "Will print out"
+msgstr "打印信息是"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po
new file mode 100644
index 00000000000..d3ab607d47b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po	
@@ -0,0 +1,1199 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdldevelopers-areatypes/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Developers area/types.rst:3
+msgid "Types"
+msgstr "类型"
+
+#: ../../SpinalHDL/Developers area/types.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Developers area/types.rst:12
+msgid ""
+"The language provides 5 base types and 2 composite types that can be used."
+msgstr "该语言提供了 5 种基本类型和 2 种复合类型。"
+
+#: ../../SpinalHDL/Developers area/types.rst:15
+msgid ""
+"Base types : ``Bool``, ``Bits``, ``UInt`` for unsigned integers, ``SInt`` "
+"for signed integers, ``Enum``."
+msgstr "基本类型： ``Bool``、``Bits``、 ``UInt`` "
+"（无符号整数）、``SInt``（有符号整数）、 ``Enum``。"
+
+#: ../../SpinalHDL/Developers area/types.rst:16
+msgid "Composite types : Bundle, Vec."
+msgstr "复合类型：``Bundle``、``Vec``。"
+
+#: ../../SpinalHDL/Developers area/types.rst:22
+msgid "Those types and their usage (with examples) are explained hereafter."
+msgstr "这些类型及其用法（包括示例）将在后面解释。"
+
+#: ../../SpinalHDL/Developers area/types.rst:24
+msgid "Fixed point support is documented :ref:`Fixed-Point <fixed>`"
+msgstr "定点小数支持已归档 :ref:`Fixed-Point <fixed>`"
+
+#: ../../SpinalHDL/Developers area/types.rst:27 area/types.rst:45
+#: area/types.rst:48 area/types.rst:51 area/types.rst:54 area/types.rst:79
+#: area/types.rst:83 area/types.rst:87 area/types.rst:90 area/types.rst:99
+#: area/types.rst:102 area/types.rst:105 area/types.rst:108 area/types.rst:111
+#: area/types.rst:114 area/types.rst:240 area/types.rst:249 area/types.rst:258
+#: area/types.rst:261 area/types.rst:270 area/types.rst:273 area/types.rst:276
+#: area/types.rst:363 area/types.rst:366 area/types.rst:369 area/types.rst:372
+#: area/types.rst:709 area/types.rst:712
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Developers area/types.rst:29
+msgid "This is the standard *boolean* type that corresponds to a single bit."
+msgstr "这是对应于单个位的标准 *boolean* 类型。"
+
+#: ../../SpinalHDL/Developers area/types.rst:32 area/types.rst:420
+msgid "Declaration"
+msgstr "声明"
+
+#: ../../SpinalHDL/Developers area/types.rst:34
+msgid "The syntax to declare such as value is as follows:"
+msgstr "声明值/对象的语法如下："
+
+#: ../../SpinalHDL/Developers area/types.rst:40 area/types.rst:130
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Developers area/types.rst:41 area/types.rst:75
+#: area/types.rst:131 area/types.rst:157 area/types.rst:180 area/types.rst:224
+#: area/types.rst:315 area/types.rst:350 area/types.rst:397 area/types.rst:421
+#: area/types.rst:434 area/types.rst:664 area/types.rst:705
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Developers area/types.rst:42 area/types.rst:132
+#: area/types.rst:225 area/types.rst:316 area/types.rst:351 area/types.rst:398
+#: area/types.rst:435 area/types.rst:706
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Developers area/types.rst:43
+msgid "Bool()"
+msgstr "Bool()"
+
+#: ../../SpinalHDL/Developers area/types.rst:44
+msgid "Create a Bool"
+msgstr "创建Bool值"
+
+#: ../../SpinalHDL/Developers area/types.rst:46
+msgid "True"
+msgstr "True"
+
+#: ../../SpinalHDL/Developers area/types.rst:47
+msgid "Create a Bool assigned with ``true``"
+msgstr "创建一个分配有 ``true`` 值的 Bool对象"
+
+#: ../../SpinalHDL/Developers area/types.rst:49
+msgid "False"
+msgstr "False"
+
+#: ../../SpinalHDL/Developers area/types.rst:50
+msgid "Create a Bool assigned with ``false``"
+msgstr "创建一个Bool值并赋值为 ``false``"
+
+#: ../../SpinalHDL/Developers area/types.rst:52
+msgid "Bool(value : Boolean)"
+msgstr "Bool(value : Boolean)"
+
+#: ../../SpinalHDL/Developers area/types.rst:53
+msgid "Create a Bool assigned with a Scala Boolean"
+msgstr "创建一个赋值有 Scala 布尔值的 Bool信号"
+
+#: ../../SpinalHDL/Developers area/types.rst:57
+msgid "Using this type into SpinalHDL yields:"
+msgstr "在 SpinalHDL 中使用这种类型会生成："
+
+#: ../../SpinalHDL/Developers area/types.rst:66 area/types.rst:217
+msgid "Operators"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Developers area/types.rst:68
+msgid "The following operators are available for the ``Bool`` type"
+msgstr "以下运算符可用于 ``Bool`` 类型"
+
+#: ../../SpinalHDL/Developers area/types.rst:74 area/types.rst:223
+#: area/types.rst:314 area/types.rst:349 area/types.rst:396 area/types.rst:433
+#: area/types.rst:704
+msgid "Operator"
+msgstr "运算符"
+
+#: ../../SpinalHDL/Developers area/types.rst:76
+msgid "Return type"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Developers area/types.rst:77
+msgid "!x"
+msgstr "!x"
+
+#: ../../SpinalHDL/Developers area/types.rst:78
+msgid "Logical NOT"
+msgstr "逻辑非"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "x && y"
+msgstr "x && y"
+
+#: ../../SpinalHDL/Developers area/types.rst area/types.rst:229
+msgid "x & y"
+msgstr "x & y"
+
+#: ../../SpinalHDL/Developers area/types.rst:82
+msgid "Logical AND"
+msgstr "逻辑与"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "x || y"
+msgstr "x || y"
+
+#: ../../SpinalHDL/Developers area/types.rst area/types.rst:232
+msgid "x | y"
+msgstr "x | y"
+
+#: ../../SpinalHDL/Developers area/types.rst:86
+msgid "Logical OR"
+msgstr "逻辑或"
+
+#: ../../SpinalHDL/Developers area/types.rst:88 area/types.rst:235
+msgid "x ^ y"
+msgstr "x ^ y"
+
+#: ../../SpinalHDL/Developers area/types.rst:89
+msgid "Logical XOR"
+msgstr "逻辑异或"
+
+#: ../../SpinalHDL/Developers area/types.rst:91
+msgid "x.set[()]"
+msgstr "x.set[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:92
+msgid "Set x to True"
+msgstr "将 x 设置为 True"
+
+#: ../../SpinalHDL/Developers area/types.rst:94
+msgid "x.clear[()]"
+msgstr "x.clear[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:95
+msgid "Set x to False"
+msgstr "将 x 设置为 False"
+
+#: ../../SpinalHDL/Developers area/types.rst:97
+msgid "x.rise[()]"
+msgstr "x.rise[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:98
+msgid "Return True when x was low at the last cycle and is now high"
+msgstr "当 x 在上一个周期为低电平且现在为高电平时返回 True"
+
+#: ../../SpinalHDL/Developers area/types.rst:100
+msgid "x.rise(initAt : Bool)"
+msgstr "x.rise(initAt : Bool)"
+
+#: ../../SpinalHDL/Developers area/types.rst:101
+msgid "Same as x.rise but with a reset value"
+msgstr "与 x.rise 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Developers area/types.rst:103
+msgid "x.fall[()]"
+msgstr "x.fall[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:104
+msgid "Return True when x was high at the last cycle and is now low"
+msgstr "当 x 在上一个周期为高且现在为低时返回 True"
+
+#: ../../SpinalHDL/Developers area/types.rst:106
+msgid "x.fall(initAt : Bool)"
+msgstr "x.fall(initAt : Bool)"
+
+#: ../../SpinalHDL/Developers area/types.rst:107
+msgid "Same as x.fall but with a reset value"
+msgstr "与 x.fall 相同但具有重置后的初始值"
+
+#: ../../SpinalHDL/Developers area/types.rst:109
+msgid "x.setWhen(cond)"
+msgstr "x.setWhen(cond)"
+
+#: ../../SpinalHDL/Developers area/types.rst:110
+msgid "Set x when cond is True"
+msgstr "当 cond 为 True 时设置 x 为 True"
+
+#: ../../SpinalHDL/Developers area/types.rst:112
+msgid "x.clearWhen(cond)"
+msgstr "x.clearWhen(cond)"
+
+#: ../../SpinalHDL/Developers area/types.rst:113
+msgid "Clear x when cond is True"
+msgstr "当 cond 为 True 时设置 x 为 False"
+
+#: ../../SpinalHDL/Developers area/types.rst:118
+msgid "The BitVector family - (``Bits``, ``UInt``, ``SInt``)"
+msgstr "BitVector 系列 - (``Bits``, ``UInt``, ``SInt``)"
+
+#: ../../SpinalHDL/Developers area/types.rst:120
+msgid ""
+"``BitVector`` is a family of types for storing multiple bits of information "
+"in a single value. This type has three subtypes that can be used to model "
+"different behaviours:"
+msgstr "``BitVector`` 是一个系列的类型，用于在单个值中存储多位信息。该类型具有三个子"
+"类型，可用于描述不同的行为："
+
+#: ../../SpinalHDL/Developers area/types.rst:121
+msgid ""
+"``Bits`` do not convey any sign information whereas the ``UInt`` (unsigned "
+"integer) and ``SInt`` (signed integer) provide the required operations to "
+"compute correct results if signed / unsigned arithmetic is used."
+msgstr ""
+"``Bits`` 不传达任何符号信息，而 ``UInt`` （无符号整数）和 ``SInt`` "
+"（有符号整数）提供了计算正确结果所需的操作（如果使用有符号/无符号算术）。"
+
+#: ../../SpinalHDL/Developers area/types.rst:124
+msgid "Declaration syntax"
+msgstr "声明语法"
+
+#: ../../SpinalHDL/Developers area/types.rst:133
+msgid "Bits/UInt/SInt [()]"
+msgstr "Bits/UInt/SInt [()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:134
+msgid "Create a BitVector, bits count is inferred"
+msgstr "创建一个 BitVector，自动推断其位数"
+
+#: ../../SpinalHDL/Developers area/types.rst:135 area/types.rst:138
+#: area/types.rst:141 area/types.rst:144 area/types.rst:147
+msgid "Bits/UInt/SInt"
+msgstr "Bits/UInt/SInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:136
+msgid "Bits/UInt/SInt(x bits)"
+msgstr "Bits/UInt/SInt(x bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:137
+msgid "Create a BitVector with x bits"
+msgstr "创建一个具有 x 位的 BitVector信号"
+
+#: ../../SpinalHDL/Developers area/types.rst:139
+msgid "B/U/S(value : Int[,width : BitCount])"
+msgstr "B/U/S(value : Int[,width : BitCount])"
+
+#: ../../SpinalHDL/Developers area/types.rst:140 area/types.rst:143
+msgid "Create a BitVector assigned with 'value'"
+msgstr "创建一个赋值为“value”的 BitVector信号"
+
+#: ../../SpinalHDL/Developers area/types.rst:142
+msgid "B/U/S\"[[size']base]value\""
+msgstr "B/U/S\"[[size']base]value\""
+
+#: ../../SpinalHDL/Developers area/types.rst:145
+msgid "B/U/S([x bits], element, ...)"
+msgstr "B/U/S([x bits], element, ...)"
+
+#: ../../SpinalHDL/Developers area/types.rst:146
+msgid ""
+"Create a BitVector assigned with the value specified by elements (see the "
+"table below)"
+msgstr "创建一个 BitVector信号，并为各元素赋值（见下表）"
+
+#: ../../SpinalHDL/Developers area/types.rst:150
+msgid "Elements could be defined as follows:"
+msgstr "可以这样定义元素："
+
+#: ../../SpinalHDL/Developers area/types.rst:156
+msgid "Element syntax"
+msgstr "元素语法"
+
+#: ../../SpinalHDL/Developers area/types.rst:158
+msgid "x : Int -> y : Boolean/Bool"
+msgstr "x : Int -> y : Boolean/Bool"
+
+#: ../../SpinalHDL/Developers area/types.rst:159
+msgid "Set bit x with y"
+msgstr "用 y 设置位 x"
+
+#: ../../SpinalHDL/Developers area/types.rst:160
+msgid "x : Range -> y : Boolean/Bool"
+msgstr "x : Range -> y : Boolean/Bool"
+
+#: ../../SpinalHDL/Developers area/types.rst:161
+msgid "Set each bits in range x with y"
+msgstr "设置 x 范围内的每个位为 y"
+
+#: ../../SpinalHDL/Developers area/types.rst:162 area/types.rst:167
+msgid "x : Range -> y : T"
+msgstr "x : Range -> y : T"
+
+#: ../../SpinalHDL/Developers area/types.rst area/types.rst:163
+#: area/types.rst:168
+msgid "Set bits in range x with y"
+msgstr "设置 x 范围内的位为y"
+
+#: ../../SpinalHDL/Developers area/types.rst:164
+msgid "x : Range -> y : String"
+msgstr "x : Range -> y : String"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "The string format follows the same rules as B/U/S\"xyz\" one"
+msgstr "字符串格式遵循与B/U/S\"xyz\"相同的规则"
+
+#: ../../SpinalHDL/Developers area/types.rst:169
+msgid "default -> y : Boolean/Bool"
+msgstr "default -> y : Boolean/Bool"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "Set all unconnected bits with the y value."
+msgstr "使用 y 值设置所有未连接的位。"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid ""
+"This feature can only be used to do assignments without the U/B/S prefix"
+msgstr "此功能只能用于对没有 U/B/S 前缀信号的赋值"
+
+#: ../../SpinalHDL/Developers area/types.rst:174
+msgid "You can define a Range values"
+msgstr "您可以定义一个范围值"
+
+#: ../../SpinalHDL/Developers area/types.rst:179
+msgid "Range syntax"
+msgstr "范围语法"
+
+#: ../../SpinalHDL/Developers area/types.rst:181
+msgid "Width"
+msgstr "位宽"
+
+#: ../../SpinalHDL/Developers area/types.rst:182
+msgid "(x downto y)"
+msgstr "(x downto y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:183
+msgid "[x:y] x >= y"
+msgstr "[x:y] x >= y"
+
+#: ../../SpinalHDL/Developers area/types.rst:184
+msgid "x-y+1"
+msgstr "x-y+1"
+
+#: ../../SpinalHDL/Developers area/types.rst:185
+msgid "(x to y)"
+msgstr "(x to y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:186
+msgid "[x:y] x <= y"
+msgstr "[x:y] x <= y"
+
+#: ../../SpinalHDL/Developers area/types.rst:187
+msgid "y-x+1"
+msgstr "y-x+1"
+
+#: ../../SpinalHDL/Developers area/types.rst:188
+msgid "(x until y)"
+msgstr "(x until y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:189
+msgid "[x:y[ x < y"
+msgstr "[x:y[ x < y"
+
+#: ../../SpinalHDL/Developers area/types.rst:190
+msgid "y-x"
+msgstr "y-x"
+
+#: ../../SpinalHDL/Developers area/types.rst:226
+msgid "~x"
+msgstr "~x"
+
+#: ../../SpinalHDL/Developers area/types.rst:227
+msgid "Bitwise NOT"
+msgstr "按位非"
+
+#: ../../SpinalHDL/Developers area/types.rst:228 area/types.rst:322
+#: area/types.rst:378
+msgid "T(w(x) bits)"
+msgstr "T(w(x) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:230
+msgid "Bitwise AND"
+msgstr "按位与"
+
+#: ../../SpinalHDL/Developers area/types.rst:231 area/types.rst:234
+#: area/types.rst:237 area/types.rst:354 area/types.rst:357 area/types.rst:724
+msgid "T(max(w(x), w(y) bits)"
+msgstr "T(max(w(x), w(y) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:233
+msgid "Bitwise OR"
+msgstr "按位或"
+
+#: ../../SpinalHDL/Developers area/types.rst:236
+msgid "Bitwise XOR"
+msgstr "按位异或"
+
+#: ../../SpinalHDL/Developers area/types.rst:238 area/types.rst:436
+msgid "x(y)"
+msgstr "x(y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:239
+msgid "Read bitfield, y : Int/UInt"
+msgstr "读取位域，y : Int/UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:241
+msgid "x(hi,lo)"
+msgstr "x(hi,lo)"
+
+#: ../../SpinalHDL/Developers area/types.rst:242
+msgid "Read bitfield, hi : Int, lo : Int"
+msgstr "读取位域，hi : Int，lo : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:243 area/types.rst:252
+#: area/types.rst:733
+msgid "T(hi-lo+1 bits)"
+msgstr "T(hi-lo+1 bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:244
+msgid "x(offset,width)"
+msgstr "x(offset,width)"
+
+#: ../../SpinalHDL/Developers area/types.rst:245
+msgid "Read bitfield, offset: UInt, width: Int"
+msgstr "读取位域，offset: UInt，width: Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:246 area/types.rst:255
+#: area/types.rst:736
+msgid "T(width bits)"
+msgstr "T(width bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:247 area/types.rst:439
+msgid "x(y) := z"
+msgstr "x(y) := z"
+
+#: ../../SpinalHDL/Developers area/types.rst:248
+msgid "Assign bits, y : Int/UInt"
+msgstr "赋值位，y : Int/UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:250
+msgid "x(hi,lo) := z"
+msgstr "x(hi,lo) := z"
+
+#: ../../SpinalHDL/Developers area/types.rst:251 area/types.rst:732
+msgid "Assign bitfield, hi : Int, lo : Int"
+msgstr "赋值位域，hi : Int，lo : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:253
+msgid "x(offset,width) := z"
+msgstr "x(offset,width) := z"
+
+#: ../../SpinalHDL/Developers area/types.rst:254 area/types.rst:735
+msgid "Assign bitfield, offset: UInt, width: Int"
+msgstr "赋值位域，offset: UInt，width: Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:256
+msgid "x.msb"
+msgstr "x.msb"
+
+#: ../../SpinalHDL/Developers area/types.rst:257
+msgid "Return the most significant bit"
+msgstr "返回最高有效位"
+
+#: ../../SpinalHDL/Developers area/types.rst:259
+msgid "x.lsb"
+msgstr "x.lsb"
+
+#: ../../SpinalHDL/Developers area/types.rst:260
+msgid "Return the least significant bit"
+msgstr "返回最低有效位"
+
+#: ../../SpinalHDL/Developers area/types.rst:262
+msgid "x.range"
+msgstr "x.range"
+
+#: ../../SpinalHDL/Developers area/types.rst:263
+msgid "Return the range (x.high downto 0)"
+msgstr "返回范围（x.high downto 0）"
+
+#: ../../SpinalHDL/Developers area/types.rst:264
+msgid "Range"
+msgstr "范围"
+
+#: ../../SpinalHDL/Developers area/types.rst:265
+msgid "x.high"
+msgstr "x.high"
+
+#: ../../SpinalHDL/Developers area/types.rst:266
+msgid "Return the upper bound of the type x"
+msgstr "返回类型 x 的上限"
+
+#: ../../SpinalHDL/Developers area/types.rst:267 area/types.rst:715
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:268
+msgid "x.xorR"
+msgstr "x.xorR"
+
+#: ../../SpinalHDL/Developers area/types.rst:269
+msgid "XOR all bits of x"
+msgstr "对 x 的所有位进行异或"
+
+#: ../../SpinalHDL/Developers area/types.rst:271
+msgid "x.orR"
+msgstr "x.orR"
+
+#: ../../SpinalHDL/Developers area/types.rst:272
+msgid "OR all bits of x"
+msgstr "对x 的所有位做或运算"
+
+#: ../../SpinalHDL/Developers area/types.rst:274
+msgid "x.andR"
+msgstr "x.andR"
+
+#: ../../SpinalHDL/Developers area/types.rst:275
+msgid "AND all bits of x"
+msgstr "对x 的所有位做与运算"
+
+#: ../../SpinalHDL/Developers area/types.rst:277
+msgid "x.clearAll[()]"
+msgstr "x.clearAll[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:278
+msgid "Clear all bits"
+msgstr "清零所有位"
+
+#: ../../SpinalHDL/Developers area/types.rst:279 area/types.rst:282
+#: area/types.rst:438 area/types.rst:739
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Developers area/types.rst:280
+msgid "x.setAll[()]"
+msgstr "x.setAll[()]"
+
+#: ../../SpinalHDL/Developers area/types.rst:281
+msgid "Set all bits"
+msgstr "将所有的位设置为1"
+
+#: ../../SpinalHDL/Developers area/types.rst:283
+msgid "x.setAllTo(value : Boolean)"
+msgstr "x.setAllTo(value : Boolean)"
+
+#: ../../SpinalHDL/Developers area/types.rst:284
+msgid "Set all bits to the given Boolean value"
+msgstr "将所有位设置为给定的布尔值（Scala Boolean）"
+
+#: ../../SpinalHDL/Developers area/types.rst:286
+msgid "x.setAllTo(value : Bool)"
+msgstr "x.setAllTo(value : Bool)"
+
+#: ../../SpinalHDL/Developers area/types.rst:287
+msgid "Set all bits to the given Bool value"
+msgstr "将所有位设置为给定的布尔值（Spinal Bool）"
+
+#: ../../SpinalHDL/Developers area/types.rst:289
+msgid "x.asBools"
+msgstr "x.asBools"
+
+#: ../../SpinalHDL/Developers area/types.rst:290
+msgid "Cast into an array of Bool"
+msgstr "转换为 Bool 数组"
+
+#: ../../SpinalHDL/Developers area/types.rst:291
+msgid "Vec(Bool(),width(x))"
+msgstr "Vec(Bool(),width(x))"
+
+#: ../../SpinalHDL/Developers area/types.rst:295
+msgid "Masked comparison"
+msgstr "掩码过滤结果比较"
+
+#: ../../SpinalHDL/Developers area/types.rst:297
+msgid ""
+"Sometimes you need to check equality between a ``BitVector`` and a bits "
+"constant that contain holes defined as a bitmask (bit positions not to be "
+"compared by the equality expression)."
+msgstr "有时候，你需要检查一个 ``BitVector`` "
+"和一个包含空位（不需要进行相等性表达式比较的位）的位掩码之间的相等性。"
+
+#: ../../SpinalHDL/Developers area/types.rst:300
+msgid "An example demonstrating how to do that (note the use of 'M' prefix) :"
+msgstr "此操作的示例（注意使用“M”前缀）："
+
+#: ../../SpinalHDL/Developers area/types.rst:308
+msgid "Bits"
+msgstr "位"
+
+#: ../../SpinalHDL/Developers area/types.rst:317 area/types.rst:320
+#: area/types.rst:373 area/types.rst:376
+msgid "x >> y"
+msgstr "x >> y"
+
+#: ../../SpinalHDL/Developers area/types.rst:318
+msgid "Logical shift right, y : Int"
+msgstr "逻辑右移，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:319 area/types.rst:375
+msgid "T(w(x) - y bits)"
+msgstr "T(w(x) - y bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:321
+msgid "Logical shift right, y : UInt"
+msgstr "逻辑右移，y : UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:323 area/types.rst:326
+#: area/types.rst:379 area/types.rst:382
+msgid "x << y"
+msgstr "x << y"
+
+#: ../../SpinalHDL/Developers area/types.rst:324
+msgid "Logical shift left, y : Int"
+msgstr "逻辑左移，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:325 area/types.rst:381
+msgid "T(w(x) + y bits)"
+msgstr "T(w(x) + y bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:327
+msgid "Logical shift left, y : UInt"
+msgstr "逻辑左移， y : UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:328 area/types.rst:384
+msgid "T(w(x) + max(y) bits)"
+msgstr "T(w(x) + max(y) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:329
+msgid "x.rotateLeft(y)"
+msgstr "x.rotateLeft(y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:330
+msgid "Logical left rotation, y : UInt"
+msgstr "逻辑循环左移，y : UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:331
+msgid "T(w(x))"
+msgstr "T(w(x))"
+
+#: ../../SpinalHDL/Developers area/types.rst:332 area/types.rst:385
+msgid "x.resize(y)"
+msgstr "x.resize(y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:333
+msgid ""
+"Return a resized copy of x, filled with zero bits as necessary at the MSB to"
+" widen, may also truncate width retaining at the LSB side, y : Int"
+msgstr "返回调整位宽后的 x，根据需要在 MSB 处填充零位以加大位宽，也可以截断保留在 "
+"LSB 侧的宽度，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:335 area/types.rst:339
+#: area/types.rst:387
+msgid "T(y bits)"
+msgstr "T(y bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:336
+msgid "x.resizeLeft(y)"
+msgstr "x.resizeLeft(y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:337
+msgid ""
+"Return a resized copy of x, filled with zero bits as necessary at the LSB to"
+" widen, may also truncate width retraining at the MSB side, y : Int"
+msgstr "返回调整位宽的 x，根据需要在 LSB 处填充零位以加大位宽，也可以在 MSB "
+"端截断宽度，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:343
+msgid "UInt, SInt"
+msgstr "UInt、SInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:352
+msgid "x + y"
+msgstr "x + y"
+
+#: ../../SpinalHDL/Developers area/types.rst:353
+msgid "Addition"
+msgstr "加法"
+
+#: ../../SpinalHDL/Developers area/types.rst:355
+msgid "x - y"
+msgstr "x - y"
+
+#: ../../SpinalHDL/Developers area/types.rst:356
+msgid "Subtraction"
+msgstr "减法"
+
+#: ../../SpinalHDL/Developers area/types.rst:358
+msgid "x * y"
+msgstr "x * y"
+
+#: ../../SpinalHDL/Developers area/types.rst:359
+msgid "Multiplication"
+msgstr "乘法"
+
+#: ../../SpinalHDL/Developers area/types.rst:360
+msgid "T(w(x) + w(y) bits)"
+msgstr "T(w(x) + w(y) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:361
+msgid "x > y"
+msgstr "x > y"
+
+#: ../../SpinalHDL/Developers area/types.rst:362
+msgid "Greater than"
+msgstr "大于"
+
+#: ../../SpinalHDL/Developers area/types.rst:364
+msgid "x >= y"
+msgstr "x >= y"
+
+#: ../../SpinalHDL/Developers area/types.rst:365
+msgid "Greater than or equal"
+msgstr "大于或等于"
+
+#: ../../SpinalHDL/Developers area/types.rst:367
+msgid "x < y"
+msgstr "x < y"
+
+#: ../../SpinalHDL/Developers area/types.rst:368
+msgid "Less than"
+msgstr "小于"
+
+#: ../../SpinalHDL/Developers area/types.rst:370
+msgid "x <= y"
+msgstr "x <= y"
+
+#: ../../SpinalHDL/Developers area/types.rst:371
+msgid "Less than or equal"
+msgstr "小于或等于"
+
+#: ../../SpinalHDL/Developers area/types.rst:374
+msgid "Arithmetic shift right, y : Int"
+msgstr "算术右移，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:377
+msgid "Arithmetic shift right, y : UInt"
+msgstr "算术右移，y : UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:380
+msgid "Arithmetic shift left, y : Int"
+msgstr "算术左移，y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:383
+msgid "Arithmetic shift left, y : UInt"
+msgstr "算术左移，y : UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:386
+msgid "Return an arithmetic resized copy of x, y : Int"
+msgstr "返回算术位宽调整后的x，y。x, y : Int"
+
+#: ../../SpinalHDL/Developers area/types.rst:391
+msgid "Bool, Bits, UInt, SInt"
+msgstr "Bool, Bits, UInt, SInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:399 area/types.rst:725
+msgid "x.asBits"
+msgstr "x.asBits"
+
+#: ../../SpinalHDL/Developers area/types.rst:400
+msgid "Binary cast in Bits"
+msgstr "二进制转换为Bits"
+
+#: ../../SpinalHDL/Developers area/types.rst:401
+msgid "Bits(w(x) bits)"
+msgstr "Bits(w(x) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:402
+msgid "x.asUInt"
+msgstr "x.asUInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:403
+msgid "Binary cast in UInt"
+msgstr "二进制转换为UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:404
+msgid "UInt(w(x) bits)"
+msgstr "UInt(w(x) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:405
+msgid "x.asSInt"
+msgstr "x.asSInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:406
+msgid "Binary cast in SInt"
+msgstr "二进制转换为SInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:407
+msgid "SInt(w(x) bits)"
+msgstr "SInt(w(x) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:408
+msgid "x.asBool"
+msgstr "x.asBool"
+
+#: ../../SpinalHDL/Developers area/types.rst:409
+msgid "Binary cast in Bool"
+msgstr "二进制转换为Bool"
+
+#: ../../SpinalHDL/Developers area/types.rst:410
+msgid "Bool(x.lsb)"
+msgstr "Bool(x.lsb)"
+
+#: ../../SpinalHDL/Developers area/types.rst:414
+msgid "Vec"
+msgstr "Vec"
+
+#: ../../SpinalHDL/Developers area/types.rst:422
+msgid "Vec(type : Data, size : Int)"
+msgstr "Vec(type : Data, size : Int)"
+
+#: ../../SpinalHDL/Developers area/types.rst:423
+msgid "Create a vector of size time the given type"
+msgstr "创建一个指定类型和位宽的向量"
+
+#: ../../SpinalHDL/Developers area/types.rst:424
+msgid "Vec(x,y,..)"
+msgstr "Vec(x,y,..)"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "Create a vector where indexes point to given elements."
+msgstr "创建一个向量，其中索引指向给定元素。"
+
+#: ../../SpinalHDL/Developers area/types.rst
+msgid "this construct supports mixed element width"
+msgstr "这会构造支持混合宽度的元素"
+
+#: ../../SpinalHDL/Developers area/types.rst:437
+msgid "Read element y, y : Int/UInt"
+msgstr "读取元素 y, y : Int/UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:440
+msgid "Assign element y with z, y : Int/UInt"
+msgstr "将元素 y 赋值给 z, y : Int/UInt"
+
+#: ../../SpinalHDL/Developers area/types.rst:460
+msgid "Bundle"
+msgstr "Bundle"
+
+#: ../../SpinalHDL/Developers area/types.rst:462
+msgid ""
+"Bundles could be used to model data structure line buses and interfaces."
+msgstr "线束可用于对数据结构信号总线和接口进行建模。"
+
+#: ../../SpinalHDL/Developers area/types.rst:463
+msgid ""
+"All attributes that extends Data (Bool, Bits, UInt, ...) that are defined "
+"inside the bundle are considered as part of the bundle."
+msgstr "线束内定义的所有数据属性（Bool、Bits、UInt...）都被视为线束的一部分。"
+
+#: ../../SpinalHDL/Developers area/types.rst:466
+msgid "Simple example (RGB/VGA)"
+msgstr "简单示例（RGB/VGA）"
+
+#: ../../SpinalHDL/Developers area/types.rst:468
+msgid ""
+"The following example show an RGB bundle definition with some internal "
+"function."
+msgstr "以下示例显示了具有某些内部函数的 RGB 线束的定义。"
+
+#: ../../SpinalHDL/Developers area/types.rst:484
+msgid ""
+"Then you can also incorporate a Bundle inside Bundle as deeply as you want:"
+msgstr "然后，您还可以根据需要将一个线束实例放置在另一个线束中（没有深度限制）："
+
+#: ../../SpinalHDL/Developers area/types.rst:494
+msgid "And finaly instantiate your Bundles inside the hardware :"
+msgstr "最后在硬件中实例化您的线束："
+
+#: ../../SpinalHDL/Developers area/types.rst:504
+msgid ""
+"If you want to specify your bundle as an input or an output of a Component, "
+"you have to do it by the following way :"
+msgstr "如果想将你的线束指定为组件的输入或输出，你必须通过以下方式来完成："
+
+#: ../../SpinalHDL/Developers area/types.rst:518
+msgid "Interface example (APB)"
+msgstr "接口示例（APB）"
+
+#: ../../SpinalHDL/Developers area/types.rst:520
+msgid ""
+"If you want to define an interface, let's imagine an APB interface, you can "
+"also use bundles :"
+msgstr "如果你想定义一个接口，比如一个APB接口，就可以使用线束："
+
+#: ../../SpinalHDL/Developers area/types.rst:546
+msgid ""
+"One good practice is to group all construction parameters inside a "
+"configuration class. This could make the parametrization much easier later "
+"in your components, especially if you have to reuse the same configuration "
+"at multiple places. Also if one time you need to add another construction "
+"parameter, you will only have to add it into the configuration class and "
+"everywhere this one is instantiated:"
+msgstr ""
+"一种好的做法是将所有构造参数分组到一个配置类中。这可以使组件中的参数化变得更"
+"加容易，特别是当您必须在多个位置重用相同的配置时。另外，如果您需要添加另一个"
+"构造参数，您只需将其添加到配置类中，并且在任何地方都可以实例化该参数："
+
+#: ../../SpinalHDL/Developers area/types.rst:573
+msgid ""
+"Then at some points, you will probably need to use the APB bus as master or "
+"as slave interface of some components. To do that you can define some "
+"functions :"
+msgstr "然后在某些时候，您可能需要使用 APB "
+"总线作为某些组件的主端接口或从端接口。为此，您可以定义一些函数："
+
+#: ../../SpinalHDL/Developers area/types.rst:611
+msgid ""
+"Then to make that better, the spinal.lib integrates a small master slave "
+"utility named IMasterSlave. When a bundle extends IMasterSlave, it should "
+"implement/override the asMaster function. It give you the ability to setup a"
+" master or a slave interface in a smoother way :"
+msgstr ""
+"更进一步优化，spine.lib 中集成了一个名为 IMasterSlave 的小型主、从端口定义工"
+"具。当线束扩展IMasterSlave时，它应该实现/覆盖asMaster函数，以便设置主端接口或"
+"从端接口中的信号方向："
+
+#: ../../SpinalHDL/Developers area/types.rst:622
+msgid "An example of an APB bus that implement this IMasterSlave :"
+msgstr "实现此 IMasterSlave 的 APB 总线示例："
+
+#: ../../SpinalHDL/Developers area/types.rst:654
+msgid "Enum"
+msgstr "Enum"
+
+#: ../../SpinalHDL/Developers area/types.rst:656
+msgid "SpinalHDL supports enumeration with some encodings :"
+msgstr "SpinalHDL 支持一些编码的枚举："
+
+#: ../../SpinalHDL/Developers area/types.rst:662
+msgid "Encoding"
+msgstr "编码"
+
+#: ../../SpinalHDL/Developers area/types.rst:663
+msgid "Bit width"
+msgstr "位宽"
+
+#: ../../SpinalHDL/Developers area/types.rst:665
+msgid "native"
+msgstr "native"
+
+#: ../../SpinalHDL/Developers area/types.rst:667
+msgid "Use the VHDL enumeration system, this is the default encoding"
+msgstr "使用VHDL枚举系统，这是默认编码"
+
+#: ../../SpinalHDL/Developers area/types.rst:668
+msgid "binarySequancial"
+msgstr "二进制顺序"
+
+#: ../../SpinalHDL/Developers area/types.rst:669
+msgid "log2Up(stateCount)"
+msgstr "log2Up(stateCount)"
+
+#: ../../SpinalHDL/Developers area/types.rst:670
+msgid "Use Bits to store states in declaration order (value from 0 to n-1)"
+msgstr "使用 Bits 按声明顺序存储状态（值从 0 到 n-1）"
+
+#: ../../SpinalHDL/Developers area/types.rst:671
+msgid "binaryOneHot"
+msgstr "binaryOneHot"
+
+#: ../../SpinalHDL/Developers area/types.rst:672
+msgid "stateCount"
+msgstr "stateCount"
+
+#: ../../SpinalHDL/Developers area/types.rst:673
+msgid ""
+"Use Bits to store state. Each bit position corresponds to one state, only "
+"one bit is active at a time when encoded."
+msgstr "使用位来存储状态。每个位对应一种状态，编码时一次只有一位有效。"
+
+#: ../../SpinalHDL/Developers area/types.rst:677
+msgid "Define an enumeration type:"
+msgstr "定义一个枚举类型："
+
+#: ../../SpinalHDL/Developers area/types.rst:685
+msgid ""
+"Instantiate a signal to store the enumeration encoded value and assign it a "
+"value :"
+msgstr "实例化一个信号来存储枚举编码值并为其赋值："
+
+#: ../../SpinalHDL/Developers area/types.rst:697
+msgid "Data (Bool, Bits, UInt, SInt, Enum, Bundle, Vec)"
+msgstr "Data (Bool, Bits, UInt, SInt, Enum, Bundle, Vec)"
+
+#: ../../SpinalHDL/Developers area/types.rst:699
+msgid ""
+"All hardware types extends the Data class, which mean that all of them "
+"provide following operators :"
+msgstr "所有硬件类型都扩展了 Data 类，这意味着它们都提供以下运算符："
+
+#: ../../SpinalHDL/Developers area/types.rst:707
+msgid "x === y"
+msgstr "x === y"
+
+#: ../../SpinalHDL/Developers area/types.rst:708
+msgid "Equality"
+msgstr "等价性判断"
+
+#: ../../SpinalHDL/Developers area/types.rst:710
+msgid "x =/= y"
+msgstr "x =/= y"
+
+#: ../../SpinalHDL/Developers area/types.rst:711
+msgid "Inequality"
+msgstr "不等价判断运算"
+
+#: ../../SpinalHDL/Developers area/types.rst:713
+msgid "x.getWidth"
+msgstr "x.getWidth"
+
+#: ../../SpinalHDL/Developers area/types.rst:714
+msgid "Return bitcount"
+msgstr "返回位数"
+
+#: ../../SpinalHDL/Developers area/types.rst:716
+msgid "x ## y"
+msgstr "x ## y"
+
+#: ../../SpinalHDL/Developers area/types.rst:717
+msgid "Concatenate, x->high, y->low"
+msgstr "连接Bits，x->高位，y->低位"
+
+#: ../../SpinalHDL/Developers area/types.rst:718
+msgid "Bits(width(x) + width(y) bits)"
+msgstr "Bits(width(x) + width(y) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:719
+msgid "Cat(x)"
+msgstr "Cat(x)"
+
+#: ../../SpinalHDL/Developers area/types.rst:720
+msgid "Concatenate list, first element on lsb, x : Array[Data]"
+msgstr "连接列表，第一个元素放置在lsb 上，x : Array[Data]"
+
+#: ../../SpinalHDL/Developers area/types.rst:721
+msgid "Bits(sumOfWidth bits)"
+msgstr "Bits(sumOfWidth bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:722
+msgid "Mux(cond,x,y)"
+msgstr "Mux(cond,x,y)"
+
+#: ../../SpinalHDL/Developers area/types.rst:723
+msgid "if cond ? x : y"
+msgstr "if cond ? x : y"
+
+#: ../../SpinalHDL/Developers area/types.rst:726
+msgid "Cast in Bits"
+msgstr "类型转换到Bits"
+
+#: ../../SpinalHDL/Developers area/types.rst:727
+msgid "Bits(width(x) bits)"
+msgstr "Bits(width(x) bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:728
+msgid "x.assignFromBits(bits)"
+msgstr "x.assignFromBits(bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:729
+msgid "Assign from Bits"
+msgstr "从Bits获取信号来赋值"
+
+#: ../../SpinalHDL/Developers area/types.rst:731
+msgid "x.assignFromBits(bits,hi,lo)"
+msgstr "x.assignFromBits(bits,hi,lo)"
+
+#: ../../SpinalHDL/Developers area/types.rst:734
+msgid "x.assignFromBits(bits,offset,width)"
+msgstr "x.assignFromBits(bits,offset,width)"
+
+#: ../../SpinalHDL/Developers area/types.rst:737
+msgid "x.getZero"
+msgstr "x.getZero"
+
+#: ../../SpinalHDL/Developers area/types.rst:738
+msgid "Get equivalent type assigned with zero"
+msgstr "获取等效类型且赋值0"
+
+#: ../../SpinalHDL/Developers area/types.rst:743
+msgid "Literals as signal declaration"
+msgstr "使用字面量声明信号"
+
+#: ../../SpinalHDL/Developers area/types.rst:745
+msgid ""
+"Literals are generally use as a constant value. But you can also use them to"
+" do two things in a single one :"
+msgstr "字面量通常用作常量值。但您也可以使用它们一次完成两件事："
+
+#: ../../SpinalHDL/Developers area/types.rst:748
+msgid "Define a wire which is assigned with a constant value"
+msgstr "定义一条分配有常量值的连线"
+
+#: ../../SpinalHDL/Developers area/types.rst:749
+msgid "Setup inferred type: UInt(4 bits)"
+msgstr "设置推断类型：UInt(4 bits)"
+
+#: ../../SpinalHDL/Developers area/types.rst:750
+msgid ""
+"Clock cycles where `cond =/= True` will result in the constant being "
+"reinstated"
+msgstr "当条件 `cond =/= True` 满足的时钟周期，将信号重新设置为常量"
+
+#: ../../SpinalHDL/Developers area/types.rst:751
+msgid ""
+"Clock cycles where `cond === True` will result in the signal having the "
+"value of `red` due to the last statement wins rule."
+msgstr "由于最后一条语句获胜规则，满足 `cond === True` "
+"条件的时钟周期将导致信号具有“red”值。"
+
+#: ../../SpinalHDL/Developers area/types.rst:754
+msgid "An example :"
+msgstr "实例："
+
+#: ../../SpinalHDL/Developers area/types.rst:770
+msgid "Continuous Assignment Literals as signal declaration"
+msgstr "用连续赋值字面量作来声明信号"
+
+#: ../../SpinalHDL/Developers area/types.rst:772
+msgid "You can also use them in expressions to do three things at once :"
+msgstr "您还可以在表达式中使用它们来同时达成三件事："
+
+#: ../../SpinalHDL/Developers area/types.rst:774
+msgid "Define a wire"
+msgstr "定义一个信号（一条线）"
+
+#: ../../SpinalHDL/Developers area/types.rst:775
+msgid ""
+"Maintain the result of an equality operation in the hardware logic "
+"implementation with the constant value and another signal"
+msgstr "在硬件逻辑实现中，保持等价性比较运算结果的常数值和另一信号的结果"
+
+#: ../../SpinalHDL/Developers area/types.rst:777
+msgid ""
+"Setup inferred type: Bool due to use of === equality operator having a "
+"result of type Bool"
+msgstr "设置推断类型：Bool，因为使用 === 相等运算符，其结果为 Bool 类型"
+
+#: ../../SpinalHDL/Developers area/types.rst:780
+msgid "There is an example :"
+msgstr "这里是一个例子："
+
+#~ msgid "There is an example about how to do that :"
+#~ msgstr "有一个关于如何执行此操作的示例："
+
+#~ msgid "Return a resized copy of x, filled with zero, y : Int"
+#~ msgstr "返回 x 的调整大小副本，用零填充，y : Int"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/index.po
new file mode 100644
index 00000000000..66370cea0f5
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-13 12:07+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/index.rst:3
+msgid "Advanced ones"
+msgstr "高级示例"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/jtag.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/jtag.po
new file mode 100644
index 00000000000..586986f3f26
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/jtag.po	
@@ -0,0 +1,273 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onesjtag/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:3 ones/jtag.rst:60
+msgid "JTAG TAP"
+msgstr "JTAG TAP"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:9
+msgid ""
+"The goal of this page is to show the implementation of a JTAG TAP (a slave) "
+"by a non-conventional way."
+msgstr "本页的目的是展示一个JTAG TAP（从设备）的非常规方式实现方法。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst
+msgid ""
+"This implementation is not a simple one, it mix object oriented programming,"
+" abstract interfaces decoupling, hardware generation and hardware "
+"description."
+msgstr "这个实现并不简单，它混合了面向对象编程、抽象接口解耦、硬件生成和硬件描述。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst
+msgid ""
+"Of course a simple JTAG TAP implementation could be done only with a simple "
+"hardware description, but the goal here is really to going forward and "
+"creating an very reusable and extensible JTAG TAP generator"
+msgstr "当然，简单的JTAG "
+"TAP实现只需通过简单的硬件描述就可以完成，但这里的目标实际上是更进一步，"
+"创建一个可重用和可扩展的JTAG TAP生成器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:16
+msgid ""
+"This page will not explain how JTAG works. A good tutorial can be found "
+"`there <https://www.fpga4fun.com/JTAG.html>`_."
+msgstr ""
+"本页不会解释 JTAG 的工作原理。可以在 `这里 <https://www.fpga4fun.com/JTAG."
+"html>`_ 找到一个很好的教程。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:18
+msgid ""
+"One big difference between commonly used HDL and Spinal, is the fact that "
+"SpinalHDL allow you to define hardware generators/builders. It's very "
+"different than describing hardware. Let's take a look into the example "
+"bellow because the difference between generate/build/describing could seem "
+"\"playing with word\" or could be interpreted differently."
+msgstr ""
+"常用的HDL与Spinal之间的一个重要区别在于，SpinalHDL允许您定义硬件生成器/构建器"
+"。这与描述硬件的方式非常不同。让我们看看下面的例子，因为在生成/构建/描述之间"
+"的区别可能看起来像是在“玩文字游戏”，或者可以用不同的方式解释。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:21
+msgid ""
+"The example bellow is a JTAG TAP which allow the JTAG master to read "
+"``switchs``\\ /\\ ``keys`` inputs and write ``leds`` outputs. This TAP could"
+" also be recognized by a master by using the UID 0x87654321."
+msgstr ""
+"下面的示例是一个JTAG TAP，它允许JTAG主设备读取 ``switchs``\\ /\\ ``keys`` "
+"的输入并写入 ``leds`` 的输出。主设备也可以通过使用UID 0x87654321来识别此 "
+"TAP。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:28
+msgid ""
+"As you can see, a JtagTap is created but then some Generator/Builder "
+"functions (idcode,read,write) are called to create each JTAG instruction. "
+"This is what i call \"Hardware generator/builder\", then these "
+"Generator/Builder are used by the user to describing an hardware. And there "
+"is the point, in commonly HDL you can only describe your hardware, which "
+"imply many donkey job."
+msgstr ""
+"正如您所看到的，上例创建了一个 JtagTap，不过又调用了一些生成(Generator)/构建("
+"Builder)函数（idcode、read、write）来创建每个JTAG指令。这就是我所说的“硬件生"
+"成器/构建器”，然后用户使用这些生成器/构建器来描述硬件。还有一点是，在通常的HD"
+"L中，你只能描述你的硬件，这意味着很多繁琐的工作。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:30
+msgid ""
+"This JTAG TAP tutorial is based on `this "
+"<https://github.com/SpinalHDL/SpinalHDL/tree/master/lib/src/main/scala/spinal/lib/com/jtag>`_"
+" implementation."
+msgstr ""
+"本JTAG TAP教程基于 `该库 <https://github.com/SpinalHDL/SpinalHDL/tree/master/"
+"lib/src/main/scala/spinal/lib/com/jtag>`_ 实现。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:35
+msgid "JTAG bus"
+msgstr "JTAG总线"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:37
+msgid "First we need to define a JTAG bus bundle."
+msgstr "首先我们需要定义一个JTAG总线束。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:44
+msgid ""
+"As you can see this bus don't contain the TCK pin because it will be "
+"provided by the clock domain."
+msgstr "正如您所看到的，该总线不包含TCK引脚，因为它将由时钟域提供。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:47
+msgid "JTAG state machine"
+msgstr "JTAG状态机"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:49
+msgid ""
+"Let's define the JTAG state machine as explained `here "
+"<https://www.fpga4fun.com/JTAG2.html>`_"
+msgstr "让我们定义JTAG状态机，依据 `此处 <https://www.fpga4fun.com/JTAG2.html>`_ "
+"所述。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:57
+msgid ""
+"The ``randBoot()`` on ``state`` make it initialized with a random state. "
+"It's only for simulation purpose."
+msgstr "``state`` 中的 ``randBoot()`` 会使其以随机状态初始化。这仅用于仿真目的。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:62
+msgid ""
+"Let's implement the core of the JTAG TAP, without any instruction, just the "
+"base manage the instruction register (IR) and the bypass."
+msgstr "让我们不使用任何指令，只用最基本的指令寄存器(IR)控制和旁路控制实现JTAG "
+"TAP的核心部分。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:71
+msgid ""
+"Ignore the reference to `with JTagTapAccess` for now, it will be explained "
+"further down."
+msgstr "暂时忽略 `with JTagTapAccess` 的引用，下面将会进一步解释。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:74
+msgid "Jtag instructions"
+msgstr "Jtag指令"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:76
+msgid ""
+"Now that the JTAG TAP core is done, we can think about how to implement JTAG"
+" instructions by an reusable way."
+msgstr "现在JTAG "
+"TAP核心部分已经完成了，我们可以考虑如何通过可重用的方式来实现JTAG指令。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:79
+msgid "JTAG TAP class interface"
+msgstr "JTAG TAP类接口"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:81
+msgid ""
+"First we need to define how an instruction could interact with the JTAG TAP "
+"core. We could of course directly take the JtagTap area, but it's not very "
+"nice because is some situation the JTAG TAP core is provided by another IP "
+"(Altera virtual JTAG for example)."
+msgstr ""
+"首先，我们需要定义指令如何与JTAG "
+"TAP内核交互。我们当然可以直接使用JtagTap区域（area）。但这不是很好，"
+"因为在某些情况下JTAG TAP内核是由另一个IP（例如Altera的虚拟JTAG）提供的。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:83
+msgid ""
+"So let's define a simple and abstract interface between the JTAG TAP core "
+"and instructions :"
+msgstr "因此，让我们在JTAG TAP内核和指令之间定义一个简单抽象接口："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:91
+msgid "Then let the ``JtagTap`` implement this abstract interface:"
+msgstr "然后让 ``JtagTap`` 实现这个抽象接口："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:93
+msgid "Additions to ``class JtagTap``"
+msgstr "添加到 ``class JtagTap``"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:102
+msgid "Base class"
+msgstr "基类"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:104
+msgid ""
+"Let's define a useful base class for JTAG instruction that provide some "
+"callback (doCapture/doShift/doUpdate/doReset) depending the selected "
+"instruction and the state of the JTAG TAP :"
+msgstr ""
+"让我们为JTAG指令定义一个有用的基类，它根据所选指令和JTAG "
+"TAP的状态提供一些回调（doCapture/doShift/doUpdate/doReset）："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst
+msgid "About the Component.current.addPrePopTask(...) :"
+msgstr "关于Component.current.addPrePopTask(...) ："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst
+msgid ""
+"This allows you to call the given code at the end of the current component "
+"construction. Because of object oriented nature of JtagInstruction, "
+"doCapture, doShift, doUpdate and doReset should not be called before "
+"children classes construction (because children classes will use it as a "
+"callback to do some logic)."
+msgstr ""
+"这允许您在当前组件构造结束时调用给定的代码。由于JtagInstruction面向对象的性质"
+"，doCapture、doShift、doUpdate 和 doReset "
+"不应在子类构造之前调用（因为子类将使用它作为回调来执行某些逻辑）。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:116
+msgid "Read instruction"
+msgstr "读指令"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:118
+msgid "Let's implement an instruction that allow the JTAG to read a signal."
+msgstr "让我们实现一条允许JTAG读取信号的指令。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:126
+msgid "Write instruction"
+msgstr "写指令"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:128
+msgid ""
+"Let's implement an instruction that allow the JTAG to write a register (and "
+"also read its current value)."
+msgstr "让我们实现一条允许JTAG写入寄存器（并读取其当前值）的指令。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:136
+msgid "Idcode instruction"
+msgstr "Idcode指令"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:138
+msgid ""
+"Let's implement the instruction that return a idcode to the JTAG and also, "
+"when a reset occur, set the instruction register (IR) to it own "
+"instructionId."
+msgstr "让我们实现向JTAG返回idcode的指令，并且当发生复位时，将指令寄存器 (IR) "
+"设置为它自己的instructionId。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:146
+msgid "User friendly wrapper"
+msgstr "用户友好型包装"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:148
+msgid ""
+"Let's add some user friendly function to the JtagTapAccess to make "
+"instructions instantiation easier ."
+msgstr "让我们向JtagTapAccess添加一些对用户友好的功能，使指令实例化更容易。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:150
+msgid "Additions to ``trait JtagTapAccess``"
+msgstr "添加 ``trait JtagTapAccess``"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:159
+msgid "Usage demonstration"
+msgstr "使用演示"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:161
+msgid ""
+"And there we are, we can now very easily create an application specific JTAG"
+" TAP without having to write any logic or any interconnections."
+msgstr "现在，我们可以非常容易地创建应用特定的JTAG "
+"TAP，而无需编写任何逻辑或任何互连。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/jtag.rst:168
+msgid ""
+"This way of doing things (Generating hardware) could also be applied to, for"
+" example, generating an APB/AHB/AXI bus slave."
+msgstr "这种处理方式（生成硬件）也可以应用于生成APB/AHB/AXI的从端总线等。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.po
new file mode 100644
index 00000000000..ff38db7c8f1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.po	
@@ -0,0 +1,201 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onesmemory_mapped_uart/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:4
+msgid "Memory mapped UART"
+msgstr "内存映射UART"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:7
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:9
+msgid ""
+"This example will take the ``UartCtrl`` component implemented in the "
+"previous :ref:`example <example_uart>` to create a memory mapped UART "
+"controller."
+msgstr "此示例将采用先前 :ref:`示例 <example_uart>` 中实现的 ``UartCtrl`` "
+"组件来创建内存映射UART控制器。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:12
+msgid "Specification"
+msgstr "规范"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:14
+msgid "The implementation will be based on the APB3 bus with a RX FIFO."
+msgstr "该实现将基于带有RX FIFO的APB3总线。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:16
+msgid "Here is the register mapping table:"
+msgstr "这是寄存器映射表："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:22
+msgid "Name"
+msgstr "名称"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:23
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:24
+msgid "Access"
+msgstr "访问"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:25
+msgid "Address"
+msgstr "地址"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:26
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:27
+msgid "clockDivider"
+msgstr "clockDivider"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:28
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:29
+#: ones/memory_mapped_uart.rst:34
+msgid "RW"
+msgstr "RW"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:30
+msgid "0"
+msgstr "0"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:31
+msgid "Set the UartCtrl clock divider"
+msgstr "设置UartCtrl时钟分频器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:32
+msgid "frame"
+msgstr "frame"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:33
+msgid "UartCtrlFrameConfig"
+msgstr "UartCtrlFrameConfig"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:35
+msgid "4"
+msgstr "4"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:36
+msgid "Set the dataLength, the parity and the stop bit configuration"
+msgstr "设置数据长度、奇偶校验和停止位配置"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:37
+msgid "writeCmd"
+msgstr "writeCmd"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:38
+msgid "Bits"
+msgstr "位"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:39
+msgid "W"
+msgstr "W"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:40
+#: ones/memory_mapped_uart.rst:45
+msgid "8"
+msgstr "8"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:41
+msgid "Send a write command to UartCtrl"
+msgstr "向UartCtrl发送写命令"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:42
+msgid "writeBusy"
+msgstr "writeBusy"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:43
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:44
+#: ones/memory_mapped_uart.rst:49
+msgid "R"
+msgstr "R"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:46
+msgid "Bit 0 => zero when a new writeCmd can be sent"
+msgstr "当可以发送新的writeCmd时，位0 => 0"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:47
+msgid "read"
+msgstr "read"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:48
+msgid "Bool / Bits"
+msgstr "Bool / Bits"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:50
+msgid "12"
+msgstr "12"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst
+msgid "Bits 7 downto 0 => rx payload"
+msgstr "位7到0 => rx payload"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst
+msgid "Bit 31 => rx payload valid"
+msgstr "位31 => rx payload valid"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:56
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:58
+msgid ""
+"For this implementation, the Apb3SlaveFactory tool will be used. It allows "
+"you to define a APB3 slave with a nice syntax. You can find the "
+"documentation of this tool :ref:`there <bus_slave_factory>`."
+msgstr ""
+"此实现将使用Apb3SlaveFactory工具。它允许您使用良好的语法定义APB3从端。"
+"您可以在 :ref:`这里 <bus_slave_factory>` 找到该工具的文档。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:60
+msgid ""
+"First, we just need to define the ``Apb3Config`` that will be used for the "
+"controller. It is defined in a Scala object as a function to be able to get "
+"it from everywhere."
+msgstr "首先，我们只需要定义控制器要使用的 ``Apb3Config``。它在Scala "
+"object中被定义为一个函数，以便能够从任何地方获取它。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst:67
+msgid ""
+"Then we can define a ``Apb3UartCtrl`` component which instantiates a "
+"``UartCtrl`` and creates the memory mapping logic between it and the APB3 "
+"bus:"
+msgstr ""
+"然后我们可以定义一个 ``Apb3UartCtrl`` 组件，该组件实例化了一个 ``UartCtrl`` "
+"并在它和APB3总线之间创建内存映射逻辑："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst
+msgid "Yes, that's all it takes. It's also synthesizable."
+msgstr "是的，仅此而已。它同样是可综合的。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.rst
+msgid ""
+"The Apb3SlaveFactory tool is not something hard-coded into the SpinalHDL "
+"compiler. It's something implemented with SpinalHDL regular hardware "
+"description syntax."
+msgstr "Apb3SlaveFactory工具不是硬编码到SpinalHDL编译器中的东西。它是使用SpinalHDL常"
+"规的硬件描述语法实现的。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/pinesec.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/pinesec.po
new file mode 100644
index 00000000000..e31d2e9663c
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/pinesec.po	
@@ -0,0 +1,24 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 09:29+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onespinesec/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/pinesec.rst:2
+msgid "Pinesec"
+msgstr "Pinesec"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/pinesec.rst:4
+msgid "Remember to add it"
+msgstr "记得添加内容！XD"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po
new file mode 100644
index 00000000000..d347b465169
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po	
@@ -0,0 +1,94 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-31 10:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onesslots/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:4
+msgid "Slots"
+msgstr "插槽(Slots)"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:7
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:9
+msgid ""
+"Let's say you have some hardware which has to keep track of multiple similar"
+" ongoing activities, you may want to implement an array of \"slots\" to do "
+"so. This example show how to do it using Area, OHMasking.first, onMask and "
+"reader."
+msgstr ""
+"假设您有一些硬件必须跟踪多个相似的正在进行的活动，您可能需要实现一组“插槽”来"
+"执行此操作。此示例展示如何使用 Area、OHMasking."
+"first、onMask和reader来完成此操作。"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:13
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:15
+msgid ""
+"This implementation avoid the use of Vec. Instead, it use Area which allow "
+"to mix signal, registers and logic definitions in each slot."
+msgstr "此实现避免使用Vec。相反，它使用允许在每个插槽中混合信号、寄存器和逻辑定义的逻"
+"辑区。"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17
+msgid ""
+"Note that the `reader` API is for SpinalHDL version comming after 1.9.1"
+msgstr "请注意， `reader` API 适用于1.9.1之后推出的SpinalHDL版本"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24
+msgid "In practice"
+msgstr "应用"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:26
+msgid ""
+"For instance, this kind of slot pattern is used in Tilelink coherency hub to"
+" keep track of all ongoing memory probes in flight:"
+msgstr "例如，在Tilelink总线（具有一致性机制）hub中，这种插槽模式用于跟踪所有正在进行"
+"的内存操作："
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:28
+msgid ""
+"https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376"
+msgstr ""
+"https://github.com/SpinalHDL/SpinalHDL/blob/"
+"008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/"
+"tilelink/coherent/Hub.scala#L376"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30
+msgid ""
+"As well in the DRAM / SDR / DDR memory controller to implement the handeling"
+" of multiple memory transactions at once (having multiple precharge / active"
+" / read / write running at the same time to improve performances) :"
+msgstr "以及在 DRAM / SDR / DDR 内存控制器中实现同时处理多个内存事务（同时运行多个预"
+"充电/激活/读/写以提高性能）："
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32
+msgid ""
+"https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202"
+msgstr ""
+"https://github.com/SpinalHDL/SpinalHDL/blob/"
+"1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/"
+"memory/sdram/xdr/Tasker.scala#L202"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:34
+msgid ""
+"As well in the NaxRiscv (out of order CPU) load-store-unit to handle the "
+"store-queue / load-queue hardware (a bit too scary to show here in the doc "
+"XD)"
+msgstr "以及在NaxRiscv（乱序 CPU）的加载存储单元中处理存储队列/加载队列的硬件（难度有"
+"些可怕，不宜在文档中展示XD）"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po
new file mode 100644
index 00000000000..1921e7e8aab
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po	
@@ -0,0 +1,372 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesadvanced-onestimer/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:4 ones/timer.rst:12
+msgid "Timer"
+msgstr "计时器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:7
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:9
+msgid ""
+"A timer module is probably one of the most basic pieces of hardware. But "
+"even for a timer, there are some interesting things that you can do with "
+"SpinalHDL. This example will define a simple timer component which "
+"integrates a bus bridging utile."
+msgstr ""
+"计时器模块可能是最基本的硬件模块之一。但即使对于计时器，您也可以使用SpinalHDL"
+"做一些有趣的事情。这个示例将定义一个简单的计时器组件，其中集成了一个总线桥接"
+"实用工具。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:14
+msgid "So let's start with the ``Timer`` component."
+msgstr "那么让我们从 ``Timer`` 组件开始。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:17
+#: ones/timer.rst:84
+msgid "Specification"
+msgstr "规范"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:19
+msgid "The ``Timer`` component will have a single construction parameter:"
+msgstr "``Timer`` 组件将具有一个构造参数："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:25
+#: ones/timer.rst:92
+msgid "Parameter Name"
+msgstr "参数名称"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:26
+#: ones/timer.rst:41 ones/timer.rst:93
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:27
+#: ones/timer.rst:42 ones/timer.rst:94 ones/timer.rst:120
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:28
+#: ones/timer.rst:135 ones/timer.rst:142
+msgid "width"
+msgstr "width"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:29
+msgid "Int"
+msgstr "Int"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:30
+msgid "Specify the bit width of the timer counter"
+msgstr "指定计时器计数器的位宽"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:33
+msgid "And also some inputs/outputs:"
+msgstr "还有一些输入/输出："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:39
+msgid "IO Name"
+msgstr "IO名称"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:40
+msgid "Direction"
+msgstr "方向"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:43
+msgid "tick"
+msgstr "tick"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:44
+#: ones/timer.rst:48 ones/timer.rst:52
+msgid "in"
+msgstr "in"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:45
+#: ones/timer.rst:49 ones/timer.rst:57
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:46
+msgid "When ``tick`` is True, the timer count up until ``limit``."
+msgstr "当 ``tick`` 为 True 时，计时器计数到 ``limit`` 。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:47
+#: ones/timer.rst:146
+msgid "clear"
+msgstr "clear"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:50
+msgid ""
+"When ``tick`` is True, the timer is set to zero. ``clear`` has priority over"
+" ``tick``."
+msgstr "当 ``tick`` 为 True 时，计时器设为零。 ``clear`` 优先于 ``tick`` 。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:51
+#: ones/timer.rst:133
+msgid "limit"
+msgstr "limit"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:53
+#: ones/timer.rst:61
+msgid "UInt(width bits)"
+msgstr "UInt(width bits)"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:54
+msgid ""
+"When the timer value is equal to ``limit``\\ , the ``tick`` input is "
+"inhibited."
+msgstr "当计时器值等于 ``limit`` 时，禁止 ``tick`` 输入。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:55
+msgid "full"
+msgstr "full"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:56
+#: ones/timer.rst:60
+msgid "out"
+msgstr "out"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:58
+msgid ""
+"``full`` is high when the timer value is equal to ``limit`` and ``tick`` is "
+"high."
+msgstr "当计时器值等于 ``limit`` 并且 ``tick`` 为高时，``full`` 为高。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:59
+#: ones/timer.rst:140
+msgid "value"
+msgstr "value"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:62
+msgid "Wire out the timer counter value."
+msgstr "引出计时器的计数器值。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:66
+#: ones/timer.rst:155
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:75
+msgid "Bridging function"
+msgstr "桥接函数"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:77
+msgid ""
+"Now we can start with the main purpose of this example: defining a bus "
+"bridging function. To do that we will use two techniques:"
+msgstr "现在我们可以从这个例子的主要目的开始：定义总线桥接功能。为此，我们将使用两种"
+"技术："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:80
+msgid ""
+"Using the ``BusSlaveFactory`` tool documented :ref:`here "
+"<bus_slave_factory>`"
+msgstr "使用在文档 :ref:`此处 <bus_slave_factory>` 的 ``BusSlaveFactory`` 工具"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:81
+msgid ""
+"Defining a function inside the ``Timer`` component which can be called from "
+"the parent component to drive the ``Timer``\\ 's IO in an abstract way."
+msgstr "在 ``Timer`` 组件内定义一个函数，这个函数可以从父组件调用该函数，"
+"并以抽象方式驱动 ``Timer`` 的 IO。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:86
+msgid "This bridging function will take the following parameters:"
+msgstr "该桥接函数将使用以下参数："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:95
+msgid "busCtrl"
+msgstr "busCtrl"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:96
+msgid "BusSlaveFactory"
+msgstr "BusSlaveFactory"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:97
+msgid ""
+"The ``BusSlaveFactory`` instance that will be used by the function to create"
+" the bridging logic."
+msgstr "函数将使用 ``BusSlaveFactory`` 实例来创建桥接逻辑。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:98
+msgid "baseAddress"
+msgstr "baseAddress"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:99
+msgid "BigInt"
+msgstr "BigInt"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:100
+msgid "The base address where the bridging logic should be mapped."
+msgstr "桥接逻辑应映射到的基地址。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:101
+msgid "ticks"
+msgstr "ticks"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:102
+#: ones/timer.rst:105
+msgid "Seq[Bool]"
+msgstr "Seq[Bool]"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:103
+msgid "A list of Bool sources that can be used as a tick signal."
+msgstr "可用作tick信号的Bool源序列。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:104
+msgid "clears"
+msgstr "clears"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:106
+msgid "A list of Bool sources that can be used as a clear signal."
+msgstr "可用作clear信号的Bool源序列。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:109
+msgid "The register mapping assumes that the bus system is 32 bits wide:"
+msgstr "假设寄存器映射的总线系统位宽是32位："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:115
+msgid "Name"
+msgstr "名称"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:116
+msgid "Access"
+msgstr "访问"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:117
+msgid "Width"
+msgstr "位宽"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:118
+msgid "Address offset"
+msgstr "地址偏移"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:119
+msgid "Bit offset"
+msgstr "位偏移"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:121
+msgid "ticksEnable"
+msgstr "ticksEnable"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:122
+#: ones/timer.rst:128 ones/timer.rst:134
+msgid "RW"
+msgstr "RW"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:123
+msgid "len(ticks)"
+msgstr "len(ticks)"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:124
+#: ones/timer.rst:125 ones/timer.rst:130 ones/timer.rst:137 ones/timer.rst:144
+msgid "0"
+msgstr "0"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:126
+msgid ""
+"Each ``ticks`` bool can be actived if the corresponding ``ticksEnable`` bit "
+"is high."
+msgstr "每个 ``ticks`` 逻辑值都可以被相应的 ``ticksEnable`` 位取高激活。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:127
+msgid "clearsEnable"
+msgstr "clearsEnable"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:129
+msgid "len(clears)"
+msgstr "len(clears)"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:131
+msgid "16"
+msgstr "16"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:132
+msgid ""
+"Each ``clears`` bool can be actived if the corresponding ``clearsEnable`` "
+"bit is high."
+msgstr "每个 ``clears`` 逻辑值都可以被相应的 ``clearsEnable`` 位取高激活。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:136
+msgid "4"
+msgstr "4"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst
+msgid "Access the limit value of the timer component."
+msgstr "访问计时器组件的limit值。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst
+msgid "When this register is written to, the timer is cleared."
+msgstr "当写入该寄存器时，计时器清零。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:141
+msgid "R"
+msgstr "R"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:143
+#: ones/timer.rst:149
+msgid "8"
+msgstr "8"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:145
+msgid "Access the value of the timer."
+msgstr "访问计时器的值。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:147
+msgid "W"
+msgstr "W"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:151
+msgid "When this register is written to, it clears the timer."
+msgstr "当写入该寄存器时，计时器清零。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:157
+msgid "Let's add this bridging function inside the ``Timer`` component."
+msgstr "让我们在 ``Timer`` 组件中添加这个桥接函数。"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:167
+msgid "Usage"
+msgstr "用法"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:169
+msgid ""
+"Here is some demonstration code which is very close to the one used in the "
+"Pinsec SoC timer module. Basically it instantiates following elements:"
+msgstr "下面是一些演示代码，它与Pinsec "
+"SoC计时器模块中使用的代码非常接近。基本上，它实例化了以下元素："
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:171
+msgid "One 16 bit prescaler"
+msgstr "1个16位预分频器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:172
+msgid "One 32 bit timer"
+msgstr "1个32位计时器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:173
+msgid "Three 16 bit timers"
+msgstr "3个16位计时器"
+
+#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:175
+msgid ""
+"Then by using an ``Apb3SlaveFactory`` and functions defined inside the "
+"``Timer``\\ s, it creates bridging logic between the APB3 bus and all "
+"instantiated components."
+msgstr ""
+"然后，通过使用 ``Apb3SlaveFactory`` 和 ``Timer`` 内定义的函数，它在 APB3 "
+"总线和所有实例化组件之间创建桥接逻辑。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/fractal.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/fractal.po
new file mode 100644
index 00000000000..9a2ebd9fac2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/fractal.po	
@@ -0,0 +1,173 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-31 10:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesintermediates-onesfractal/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:2
+msgid "Fractal calculator"
+msgstr "分形计算器"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:5
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:7
+msgid ""
+"This example will show a simple implementation (without optimization) of a "
+"Mandelbrot fractal calculator by using data streams and fixed point "
+"calculations."
+msgstr "此示例将展示使用数据流和定点计算实现一个未经优化的Mandelbrot分形计算器。"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:10
+msgid "Specification"
+msgstr "规范"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:12
+msgid ""
+"The component will receive one ``Stream`` of pixel tasks (which contain the "
+"XY coordinates in the Mandelbrot space) and will produce one ``Stream`` of "
+"pixel results (which contain the number of iterations done for the "
+"corresponding task)."
+msgstr ""
+"该组件将接收像素任务的一个 ``Stream`` （其中包含Mandelbrot空间中的XY坐标），"
+"并将生成一个像素结果的一个 ``Stream`` （包含对应任务的迭代次数）。"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:14
+msgid "Let's specify the IO of our component:"
+msgstr "定义组件的IO为："
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:20
+msgid "IO Name"
+msgstr "IO名称"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:21
+msgid "Direction"
+msgstr "方向"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:22
+#: ones/fractal.rst:41 ones/fractal.rst:58
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:23
+#: ones/fractal.rst:42 ones/fractal.rst:59
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:24
+msgid "cmd"
+msgstr "cmd"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:25
+msgid "slave"
+msgstr "slave"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:26
+msgid "Stream[PixelTask]"
+msgstr "Stream[PixelTask]"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:27
+msgid "Provide XY coordinates to process"
+msgstr "提供XY坐标来处理"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:28
+msgid "rsp"
+msgstr "rsp"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:29
+msgid "master"
+msgstr "master"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:30
+msgid "Stream[PixelResult]"
+msgstr "Stream[PixelResult]"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:31
+msgid "Return iteration count needed for the corresponding cmd transaction"
+msgstr "返回对应cmd交换所需的迭代次数"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:34
+msgid "Let's specify the PixelTask ``Bundle``\\ :"
+msgstr "让我们设计 PixelTask ``Bundle``\\ ："
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:40
+#: ones/fractal.rst:57
+msgid "Element Name"
+msgstr "元素名称"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:43
+msgid "x"
+msgstr "x"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:44
+#: ones/fractal.rst:47
+msgid "SFix"
+msgstr "SFix"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:45
+#: ones/fractal.rst:48
+msgid "Coordinate in the Mandelbrot space"
+msgstr "Mandelbrot空间中的坐标"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:46
+msgid "y"
+msgstr "y"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:51
+msgid "Let's specify the PixelResult ``Bundle``\\ :"
+msgstr "定义PixelResult ``Bundle`` ："
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:60
+msgid "iteration"
+msgstr "iteration"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:61
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:62
+msgid "Number of iterations required to solve the Mandelbrot coordinates"
+msgstr "求解Mandelbrot坐标所需的迭代次数"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:66
+msgid "Elaboration parameters (Generics)"
+msgstr "细化参数（泛型）"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:68
+msgid ""
+"Let's define the class that will provide construction parameters of our "
+"system:"
+msgstr "让我们定义为系统提供构造参数的类："
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:76
+msgid ""
+"iterationType and fixType are functions that you can call to instantiate new"
+" signals. It's like a typedef in C."
+msgstr "iterationType和fixType是可以调用来实例化新信号的函数，它就像C语言中的typedef"
+"。"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:79
+msgid "Bundle definition"
+msgstr "Bundle定义"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:87
+msgid "Component implementation"
+msgstr "组件实现"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/fractal.rst:89
+msgid ""
+"And now the implementation. The one below is a very simple one without "
+"pipelining / multi-threading."
+msgstr "现在进行实现。下面是一个非常简单的实现，没有使用流水线处理/多线程技术。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/index.po
new file mode 100644
index 00000000000..7be267403a2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:45+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesintermediates-onesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Intermediates ones/index.rst:3
+msgid "Intermediates ones"
+msgstr "中级示例"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/uart.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/uart.po
new file mode 100644
index 00000000000..43e0bfb78e4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/uart.po	
@@ -0,0 +1,431 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesintermediates-onesuart/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:4
+msgid "UART"
+msgstr "串口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:7
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:9
+msgid ""
+"This UART controller tutorial is based on `this "
+"<https://github.com/SpinalHDL/SpinalHDL/tree/master/lib/src/main/scala/spinal/lib/com/uart>`_"
+" implementation."
+msgstr ""
+"本UART控制器教程基于 `此文件 <https://github.com/SpinalHDL/SpinalHDL/tree/"
+"master/lib/src/main/scala/spinal/lib/com/uart>`_ 实现。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:11
+msgid "This implementation is characterized by:"
+msgstr "该实现的特征有："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:14
+msgid ""
+"ClockDivider/Parity/StopBit/DataLength configs are set by the component "
+"inputs."
+msgstr "ClockDivider/Parity/StopBit/DataLength的配置由组件输入设置。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:15
+msgid ""
+"RXD input is filtered by using a sampling window of N samples and a majority"
+" vote."
+msgstr "RXD输入通过使用N个样本的采样窗口和多数投票法进行滤波。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:18
+msgid "Interfaces of this UartCtrl are:"
+msgstr "该UartCtrl控制端口为："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:24 ones/uart.rst:53
+#: ones/uart.rst:133 ones/uart.rst:218
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:25 ones/uart.rst:54
+#: ones/uart.rst:134 ones/uart.rst:219
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:26 ones/uart.rst:55
+#: ones/uart.rst:135 ones/uart.rst:220
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:27
+msgid "config"
+msgstr "config"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:28
+msgid "UartCtrlConfig"
+msgstr "UartCtrlConfig"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:29
+msgid "Give all configurations to the controller"
+msgstr "将所有配置发给控制器"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:30 ones/uart.rst:142
+msgid "write"
+msgstr "write"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:31 ones/uart.rst:143
+msgid "Stream[Bits]"
+msgstr "Stream[Bits]"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:32
+msgid "Port used by the system to give transmission order to the controller"
+msgstr "系统向控制器发送传输顺序所用的端口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:33 ones/uart.rst:227
+msgid "read"
+msgstr "read"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:34 ones/uart.rst:228
+msgid "Flow[Bits]"
+msgstr "Flow[Bits]"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:35 ones/uart.rst:229
+msgid ""
+"Port used by the controller to notify the system about a successfully "
+"received frame"
+msgstr "控制器发送已成功接收帧给系统所用的端口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:36
+msgid "uart"
+msgstr "uart"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:37
+msgid "Uart"
+msgstr "Uart"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:38
+msgid "Uart interface with rxd / txd"
+msgstr "带rxd/txd的Uart接口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:42
+msgid "Data structures"
+msgstr "数据结构"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:44
+msgid ""
+"Before implementing the controller itself we need to define some data "
+"structures."
+msgstr "在实现控制器本体之前，我们需要定义一些数据结构。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:47
+msgid "Controller construction parameters"
+msgstr "控制器构造参数"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:56
+msgid "dataWidthMax"
+msgstr "dataWidthMax"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:57 ones/uart.rst:60
+#: ones/uart.rst:63 ones/uart.rst:66 ones/uart.rst:69
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:58
+msgid ""
+"Maximum number of data bits that could be sent using a single UART frame"
+msgstr "使用单个UART帧可以发送的最大数据位数"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:59
+msgid "clockDividerWidth"
+msgstr "clockDividerWidth"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:61
+msgid "Number of bits that the clock divider has"
+msgstr "时钟分频器的位数"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:62
+msgid "preSamplingSize"
+msgstr "preSamplingSize"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:64
+msgid "Number of samples to drop at the beginning of the sampling window"
+msgstr "采样窗口开始时要丢弃的样本数"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:65
+msgid "samplingSize"
+msgstr "samplingSize"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:67
+msgid ""
+"Number of samples use at the middle of the window to get the filtered RXD "
+"value"
+msgstr "使用多个窗口中部的样本来获得过滤后的 RXD 值"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:68
+msgid "postSamplingSize"
+msgstr "postSamplingSize"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:70
+msgid "Number of samples to drop at the end of the sampling window"
+msgstr "采样窗口结束时丢弃的样本数"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:73
+msgid ""
+"To make the implementation easier let's assume that ``preSamplingSize + "
+"samplingSize + postSamplingSize`` is always a power of two. If so we can "
+"skip resetting counters in a few places."
+msgstr ""
+"为了使实现更容易，我们假设 ``preSamplingSize + samplingSize + "
+"postSamplingSize`` 始终是 2 "
+"的幂次方。这样做可以在一些地方跳过计数器清零操作。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:76
+msgid ""
+"Instead of adding each construction parameters (generics) to ``UartCtrl`` "
+"one by one, we can group them inside a class that will be used as single "
+"parameter of ``UartCtrl``."
+msgstr ""
+"同时，不需要将每个构造参数（泛型）一一添加到 ``UartCtrl`` "
+"中，我们可以将它们分组到一个类中，该类将用作 ``UartCtrl`` 的单个参数。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:84
+msgid "UART interface"
+msgstr "UART接口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:86
+msgid "Let's define a UART interface bundle without flow control."
+msgstr "让我们定义一个没有流量控制的UART接口线束。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:95
+msgid "UART configuration enums"
+msgstr "UART配置枚举"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:97
+msgid "Let's define parity and stop bit enumerations."
+msgstr "让我们定义奇偶校验和停止位枚举。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:105
+msgid "UartCtrl configuration Bundles"
+msgstr "UartCtrl配置线束"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:107
+msgid ""
+"Let's define bundles that will be used as IO elements to setup ``UartCtrl``."
+msgstr "让我们定义一些线束，它们将被用于设置 ``UartCtrl`` 的IO单元。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:115
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:117
+msgid "In ``UartCtrl``\\ , 3 things will be instantiated:"
+msgstr "在 ``UartCtrl`` 中会实例化3个东西 ："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:120
+msgid ""
+"One clock divider that generates a tick pulse at the UART RX sampling rate."
+msgstr "一个时钟分频器，以UART RX采样率产生采样脉冲。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:121
+msgid "One ``UartCtrlTx`` component"
+msgstr "一个 ``UartCtrlTx`` 组件"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:122
+msgid "One ``UartCtrlRx`` component"
+msgstr "一个 ``UartCtrlRx`` 组件"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:125
+msgid "UartCtrlTx"
+msgstr "UARTCtrlTx"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:127
+msgid "The interfaces of this ``Component`` are the following :"
+msgstr "该 ``Component`` 的接口如下："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:136 ones/uart.rst:221
+msgid "configFrame"
+msgstr "configFrame"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:137 ones/uart.rst:222
+msgid "UartCtrlFrameConfig"
+msgstr "UartCtrlFrameConfig"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:138
+msgid "Contains data bit width count and party/stop bits configurations"
+msgstr "包含数据位宽计数和奇偶校验位/停止位配置"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:139 ones/uart.rst:224
+msgid "samplingTick"
+msgstr "samplingTick"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:140 ones/uart.rst:146
+#: ones/uart.rst:225 ones/uart.rst:231
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:141 ones/uart.rst:226
+msgid "Time reference that pulses ``rxSamplePerBit`` times per UART baud"
+msgstr "以每UART波特 ``rxSamplePerBit`` 次脉冲为时间参考"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:144
+msgid "Port used by the system to give transmission orders to the controller"
+msgstr "系统向控制器发出传输命令的端口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:145
+msgid "txd"
+msgstr "txd"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:147
+msgid "UART txd pin"
+msgstr "UART txd引脚"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:150 ones/uart.rst:235
+msgid ""
+"Let's define the enumeration that will be used to store the state of "
+"``UartCtrlTx``\\ :"
+msgstr "让我们定义用于存储 ``UartCtrlTx`` 状态的枚举："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:158
+msgid "Let's define the skeleton of ``UartCtrlTx``\\ :"
+msgstr "让我们定义 ``UartCtrlTx`` 的框架："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:202 ones/uart.rst:296
+msgid "And here is the complete implementation:"
+msgstr "完整实现如下："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:210
+msgid "UartCtrlRx"
+msgstr "UartCtrlRx"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:212
+msgid "The interfaces of this ``Component`` are the following:"
+msgstr "该 ``Component`` 的接口如下："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:223
+msgid "Contains data bit width and party/stop bits configurations"
+msgstr "包含数据位宽和奇偶校验/停止位配置"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:230
+msgid "rxd"
+msgstr "rxd"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:232
+msgid "UART rxd pin, not synchronized with the current clock domain"
+msgstr "UART rxd 引脚，与当前时钟域不同步"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:244
+msgid "Let's define the skeleton of the UartCtrlRx :"
+msgstr "让我们定义 UartCtrlRx 的框架："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:304
+msgid "UartCtrl"
+msgstr "UartCtrl"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:306
+msgid ""
+"Let's write ``UartCtrl`` that instantiates the ``UartCtrlRx`` and "
+"``UartCtrlTx`` parts, generate the clock divider logic, and connect them to "
+"each other."
+msgstr ""
+"让我们编写 ``UartCtrl`` 来实例化 ``UartCtrlRx`` 和 ``UartCtrlTx`` "
+"部分，生成时钟分频器逻辑，并将它们相互连接。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:313
+msgid ""
+"To make it easier to use the UART with fixed settings, we introduce an "
+"companion object for ``UartCtrl``. It allows us to provide additional ways "
+"of instantiating a UartCtrl component with different sets of parameters. "
+"Here we define a ``UartCtrlInitConfig`` holding the settings for a component"
+" that is not runtime configurable. Note that it is still possible to "
+"instantiate the UartCtrl manually like all other components, which one would"
+" do if a runtime-configurable UART is needed (via ``val uart = new "
+"UartCtrl()``)."
+msgstr ""
+"为了更简单地使用具有固定设置的 UART，我们引入了 ``UartCtrl`` 的伴生对象。这使"
+"我们能够以不同的参数集实例化UartCtrl组件，提供了额外的实例化方式。"
+"这里我们定义了 ``UartCtrlInitConfig`` ，用它保存那些无法在运行时配置的组件的"
+"设置。请注意，如果需要一个能在运行时进行配置的UART，您仍然可以像所有其他组件"
+"一样（通过 ``val uart = new UartCtrl()`` ）手动实例化UartCtrl。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:325
+msgid "Simple usage"
+msgstr "简单应用"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:327
+msgid "To synthesize a ``UartCtrl`` as ``115200-N-8-1``:"
+msgstr "用 ``115200-N-8-1`` 的参数综合 ``UartCtrl`` ："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:334
+msgid "If you are using ``txd`` pin only, add:"
+msgstr "如果您仅使用 ``txd`` 引脚，请添加："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:341
+msgid "On the contrary, if you are using ``rxd`` pin only:"
+msgstr "相反，如果您仅使用 ``rxd`` 引脚："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:349
+msgid "Example with test bench"
+msgstr "带TestBench的例子"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:351
+msgid "Here is a top level example that does the followings things:"
+msgstr "下面是一个顶层的示例，它执行以下操作："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:354
+msgid ""
+"Instantiate ``UartCtrl`` and set its configuration to 921600 baud/s, no "
+"parity, 1 stop bit."
+msgstr "实例化 ``UartCtrl`` 并将其配置设置为 921600 baud/s，无奇偶校验，1 个停止位。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:355
+msgid ""
+"Each time a byte is received from the UART, it writes it on the leds output."
+msgstr "每次从 UART 接收到一个字节时，它都会将其写到 LED 输出上。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:356
+msgid "Every 2000 cycles, it sends the switches input value to the UART."
+msgstr "把switches输入值以每2000个周期发送到 UART。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:363
+msgid ""
+"`Here "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/master/tester/src/test/resources/UartCtrlUsageExample_tb.vhd>`_"
+" you can get a simple VHDL testbench for this small "
+"``UartCtrlUsageExample``."
+msgstr ""
+"您可以在 `这里 <https://github.com/SpinalHDL/SpinalHDL/blob/master/tester/"
+"src/test/resources/UartCtrlUsageExample_tb.vhd>`_ 为这个小 "
+"``UartCtrlUsageExample`` 获取一个简单的 VHDL 测试文件。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:366
+msgid "Bonus: Having fun with Stream"
+msgstr "额外奖励：享受 Stream 带来的乐趣"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:368
+msgid "If you want to queue data received from the UART:"
+msgstr "如果您想将从 UART 接收到的数据入队："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:375
+msgid ""
+"If you want to add a queue on the write interface and do some flow control:"
+msgstr "如果要在写接口上添加一个队列并做一些流控制："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/uart.rst:382
+msgid ""
+"If you want to send a 0x55 header before sending the value of switches, you "
+"can replace the write generator of the preceding example by:"
+msgstr "如果您想在发送switches值之前发送 0x55 标头，可以将上例中的写生成器替换为："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po
new file mode 100644
index 00000000000..0110cbe2b40
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po	
@@ -0,0 +1,320 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesintermediates-onesvga/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:2
+msgid "VGA"
+msgstr "VGA"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:5
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:7
+msgid ""
+"VGA interfaces are becoming an endangered species, but implementing a VGA"
+" controller is still a good exercise."
+msgstr "VGA接口正在成为一种“濒危”的技术，但实现VGA控制器仍然是一个很好的练习。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:9
+msgid ""
+"An explanation about the VGA protocol can be found `here "
+"<https://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml>`_."
+msgstr ""
+"有关 VGA 协议的说明可以在 `此处 <https://web.mit.edu/6.111/www/s2004/NEWKIT/"
+"vga.shtml>`_ 找到。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:11
+msgid ""
+"This VGA controller tutorial is based on `this "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/graphic/vga/VgaCtrl.scala>`_"
+" implementation."
+msgstr ""
+"本VGA控制器教程基于 `此文件 "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/graphic/vga/VgaCtrl.scala>`_"
+" 实现。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:14
+msgid "Data structures"
+msgstr "数据结构"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:16
+msgid ""
+"Before implementing the controller itself we need to define some data "
+"structures."
+msgstr "在实现控制器本体之前，我们需要定义一些数据结构。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:19
+msgid "RGB color"
+msgstr "RGB颜色"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:21
+msgid ""
+"First, we need a three channel color structure (Red, Green, Blue). This "
+"data structure will be used to feed the controller with pixels and also "
+"will be used by the VGA bus."
+msgstr "首先，我们需要一个三通道的颜色结构（红、绿、蓝）。该数据结构将用于向控制器提供像素，也将由 VGA 总线使用。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:29
+msgid "VGA bus"
+msgstr "VGA总线"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:35 ones/vga.rst:109
+msgid "io name"
+msgstr "io名称"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:36
+msgid "Driver"
+msgstr "驱动"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:37 ones/vga.rst:111
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:38
+msgid "vSync"
+msgstr "vSync"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:39 ones/vga.rst:42
+#: ones/vga.rst:45 ones/vga.rst:48 ones/vga.rst:128
+msgid "master"
+msgstr "master"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:40
+msgid "Vertical synchronization, indicate the beginning of a new frame"
+msgstr "垂直同步，表示新帧的开始"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:41
+msgid "hSync"
+msgstr "hSync"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:43
+msgid "Horizontal synchronization, indicate the beginning of a new line"
+msgstr "水平同步，表示新行的开始"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:44
+msgid "colorEn"
+msgstr "colorEn"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:46
+msgid "High when the interface is in the visible part"
+msgstr "当位于界面可见部分时为高"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:47
+msgid "color"
+msgstr "color"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:49
+msgid "Carry the color, don't care when colorEn is low"
+msgstr "携带颜色信息，当colorEn为低时无效"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:57
+msgid ""
+"This Vga ``Bundle`` uses the ``IMasterSlave`` trait, which allows you to "
+"create master/slave VGA interfaces using the following:"
+msgstr "此Vga ``Bundle`` 使用 ``IMasterSlave`` 特质，它允许您使用以下命令创建主/从 VGA 接口："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:65
+msgid "VGA timings"
+msgstr "VGA时序"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:67
+msgid ""
+"The VGA interface is driven by using 8 different timings. Here is one "
+"simple example of a ``Bundle`` that is able to carry them."
+msgstr "VGA接口使用8种不同的时序进行驱动。以下是一个能够携带它们的 ``Bundle`` 的简单示例。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:82
+msgid ""
+"But this not a very good way to specify it because it is redundant for "
+"vertical and horizontal timings."
+msgstr "但这并不是一种很好的指定方式，因为在垂直和水平时序方面存在冗余。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:84
+msgid "Let's write it in a clearer way:"
+msgstr "让我们写得更清晰一些："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:92
+msgid ""
+"Then we can add some some functions to set these timings for specific "
+"resolutions and frame rates:"
+msgstr "然后，我们可以添加一些函数来为特定分辨率和帧率设置这些时序参数："
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:100
+msgid "VGA Controller"
+msgstr "VGA控制器"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:103
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:110
+msgid "Direction"
+msgstr "方向"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:112
+msgid "softReset"
+msgstr "softReset"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:113 ones/vga.rst:116
+msgid "in"
+msgstr "in"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:114
+msgid "Reset internal counters and keep the VGA interface inactive"
+msgstr "复位内部计数器并保持 VGA 接口不激活"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:115
+msgid "timings"
+msgstr "timings"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:117
+msgid "Specify VGA horizontal and vertical timings"
+msgstr "指定 VGA 水平和垂直时序"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:118
+msgid "pixels"
+msgstr "pixels"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:119
+msgid "slave"
+msgstr "slave"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:120
+msgid "Stream of RGB colors that feeds the VGA controller"
+msgstr "为VGA控制器提供RGB颜色流输入"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:121
+msgid "error"
+msgstr "error"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:122 ones/vga.rst:125
+msgid "out"
+msgstr "out"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:123
+msgid "High when the pixels stream is too slow"
+msgstr "当像素流太慢时为高"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:124
+msgid "frameStart"
+msgstr "frameStart"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:126
+msgid "High when a new frame starts"
+msgstr "新帧开始时为高电平"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:127
+msgid "vga"
+msgstr "vga"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:129
+msgid "VGA interface"
+msgstr "VGA接口"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:132
+msgid ""
+"The controller does not integrate any pixel buffering. It directly takes "
+"them from the ``pixels`` ``Stream`` and puts them on the ``vga.color`` "
+"out at the right time. If ``pixels`` is not valid then ``error`` becomes "
+"high for one cycle."
+msgstr ""
+"该控制器不集成任何像素缓冲。它直接从 ``pixels`` ``Stream`` 中获取像素，并在正确的时间将它们放在 ``vga.color``"
+" 上。如果 ``pixels`` 无效，则 ``error`` 在一个周期内变高。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:135
+msgid "Component and io definition"
+msgstr "组件及io定义"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:137
+msgid ""
+"Let's define a new VgaCtrl ``Component``\\ , which takes as ``RgbConfig``"
+" and ``timingsWidth`` as parameters. Let's give the bit width a default "
+"value of 12."
+msgstr ""
+"让我们定义一个新的 VgaCtrl ``Component`` ，它将 ``RgbConfig`` 和 ``timingsWidth`` "
+"作为参数。我们将位宽设置为默认值 12。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:146
+msgid "Horizontal and vertical logic"
+msgstr "水平和垂直逻辑"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148
+msgid ""
+"The logic that generates horizontal and vertical synchronization signals "
+"is quite the same. It kind of resembles ~PWM~. The horizontal one counts "
+"up each cycle, while the vertical one use the horizontal syncronization "
+"signal as to increment."
+msgstr "产生水平和垂直同步信号的逻辑完全相同，它有点类似于〜PWM〜。水平同步每周期计数一次，垂直同步则利用水平同步信号递增。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150
+msgid ""
+"Let's define ``HVArea``\\ , which represents one ~PWM~ and then "
+"instantiate it two times: one for both horizontal and vertical "
+"syncronization."
+msgstr "让我们定义 ``HVArea`` ，它代表一个~PWM~，然后实例化它两次：一次用于水平同步，一次用于垂直同步。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160
+msgid ""
+"As you can see, it's done by using ``Area``. This is to avoid the "
+"creation of a new ``Component`` which would have been much more verbose."
+msgstr "正如你所看到的，它是通过使用 ``Area`` 来完成的。这是为了避免创建一个新的 ``Component`` ，否则会变得冗长得多。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:163
+msgid "Interconnections"
+msgstr "互连"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:165
+msgid ""
+"Now that we have timing generators for horizontal and vertical "
+"synchronization, we need to drive the outputs."
+msgstr "现在我们有了水平和垂直同步的时序生成器，我们需要驱动输出。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:176
+msgid "Bonus"
+msgstr "额外奖励"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:178
+msgid ""
+"The VgaCtrl that was defined above is generic (not application specific)."
+" We can imagine a case where the system provides a ``Stream`` of "
+"``Fragment`` of RGB, which means the system transmits pixels between "
+"start/end of picture indications."
+msgstr ""
+"上面定义的VgaCtrl是通用的（不特定于某个应用）。我们可以假设这样一种情况，系统提供RGB的 ``Fragment`` 流 "
+"``Stream`` ，这意味着系统在图片开始/结束指示之间传输像素。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:181
+msgid ""
+"In this case we can automatically manage the ``softReset`` input by "
+"asserting it when an ``error`` occurs, then wait for the end of the "
+"current ``pixels`` picture to deassert ``error``."
+msgstr ""
+"在这种情况下，我们可以通过在发生 ``error`` 时激活 ``softReset`` 输入以实现自动管理 ``softReset`` "
+"，然后等待当前 ``pixels`` 图片结束以取消激活 ``error``。"
+
+#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:183
+msgid ""
+"Let's add a function to ``VgaCtrl`` that can be called from the parent "
+"component to feed ``VgaCtrl`` by using this ``Stream`` of ``Fragment`` of"
+" RGB."
+msgstr ""
+"让我们向 ``VgaCtrl`` 添加一个函数，可以从父组件调用该函数，以通过使用RGB的 ``Fragment`` 流 ``Stream`` "
+"来提供数据给 ``VgaCtrl`` 。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/apb3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/apb3.po
new file mode 100644
index 00000000000..68c09bc756d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/apb3.po	
@@ -0,0 +1,149 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-16 16:35+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onesapb3/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:4
+msgid "APB3 definition"
+msgstr "APB3定义"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:7
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:9
+msgid "This example will show the syntax to define an APB3 ``Bundle``."
+msgstr "此示例将展示定义一个APB3 ``Bundle`` 的语句。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:12
+msgid "Specification"
+msgstr "规范"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:14
+msgid "The specification from ARM could be interpreted as follows:"
+msgstr "ARM关于APB3的端口规范如下："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:20
+msgid "Signal Name"
+msgstr "信号名称"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:21
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:22
+msgid "Driver side"
+msgstr "驱动端"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:23
+msgid "Comment"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:24
+msgid "PADDR"
+msgstr "PADDR"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:25
+msgid "UInt(addressWidth bits)"
+msgstr "UInt(addressWidth bits)"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:26 ones/apb3.rst:30
+#: ones/apb3.rst:34 ones/apb3.rst:38 ones/apb3.rst:42
+msgid "Master"
+msgstr "Master"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:27
+msgid "Address in byte"
+msgstr "以字节为单位的地址"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:28
+msgid "PSEL"
+msgstr "PSEL"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:29
+msgid "Bits(selWidth)"
+msgstr "Bits(selWidth)"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:31
+msgid "One bit per slave"
+msgstr "每个从端1bit"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:32
+msgid "PENABLE"
+msgstr "PENABLE"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:33 ones/apb3.rst:37
+#: ones/apb3.rst:45 ones/apb3.rst:53
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:36
+msgid "PWRITE"
+msgstr "PWRITE"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:40
+msgid "PWDATA"
+msgstr "PWDATA"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:41 ones/apb3.rst:49
+msgid "Bits(dataWidth bits)"
+msgstr "Bits(dataWidth bits)"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:44
+msgid "PREADY"
+msgstr "PREADY"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:46 ones/apb3.rst:50
+#: ones/apb3.rst:54
+msgid "Slave"
+msgstr "Slave"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:48
+msgid "PRDATA"
+msgstr "PRDATA"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:52
+msgid "PSLVERROR"
+msgstr "PSLVERROR"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:55
+msgid "Optional"
+msgstr "可选"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:59
+msgid "Implementation"
+msgstr "实现"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:61
+msgid ""
+"This specification shows that the APB3 bus has multiple possible "
+"configurations. To represent that, we can define a configuration class in "
+"Scala:"
+msgstr "该规范表明APB3总线具有多种可能的配置。为了实现这一点，我们可以在Scala中定义一"
+"个配置类："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:68
+msgid ""
+"Then we can define the APB3 ``Bundle`` which will be used to represent the "
+"bus in hardware:"
+msgstr "然后我们可以定义用于表示硬件总线的APB3 ``Bundle`` ："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:76
+msgid "Usage"
+msgstr "用法"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/apb3.rst:78
+msgid "Here is a usage example of this definition:"
+msgstr "以下是该定义的用法示例："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/carry_adder.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/carry_adder.po
new file mode 100644
index 00000000000..973b1ad8946
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/carry_adder.po	
@@ -0,0 +1,30 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-13 12:07+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onescarry_adder/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/carry_adder.rst:2
+msgid "Carry adder"
+msgstr "进位加法器"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/carry_adder.rst:4
+msgid ""
+"This example defines a component with inputs ``a`` and ``b``\\ , and a "
+"``result`` output. At any time, ``result`` will be the sum of ``a`` and "
+"``b`` (combinatorial). This sum is manually done by a carry adder logic."
+msgstr ""
+"此示例定义了一个具有输入 ``a`` 和 ``b`` 以及输出 ``result`` "
+"的组件。在任何时候， ``result`` 将是 ``a`` 和 ``b`` "
+"（组合逻辑）的和。该和是由进位加法器手动完成的。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/color_summing.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/color_summing.po
new file mode 100644
index 00000000000..a4262cd8abd
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/color_summing.po	
@@ -0,0 +1,31 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-13 12:07+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onescolor_summing/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/color_summing.rst:2
+msgid "Color summing"
+msgstr "颜色求和"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/color_summing.rst:4
+msgid "First let's define a Color ``Bundle`` with an addition operator."
+msgstr "首先，我们定义一个带加法运算符的Color ``Bundle`` 。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/color_summing.rst:11
+msgid ""
+"Then let's define a component with a ``sources`` input which is a vector of "
+"colors, and a ``result`` output which is the sum of the ``sources`` input."
+msgstr "然后，我们定义一个带 ``sources`` 颜色向量输入、输出 ``sources`` 输入之和 "
+"``result`` 的组件。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/counter_with_clear.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/counter_with_clear.po
new file mode 100644
index 00000000000..afff44ee724
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/counter_with_clear.po	
@@ -0,0 +1,29 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-13 12:07+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onescounter_with_clear/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/counter_with_clear.rst:2
+msgid "Counter with clear"
+msgstr "带清零的计数器"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/counter_with_clear.rst:4
+msgid ""
+"This example defines a component with a ``clear`` input and a ``value`` "
+"output. Each clock cycle, the ``value`` output is incrementing, but when "
+"``clear`` is high, ``value`` is cleared."
+msgstr ""
+"此示例定义了一个具有 ``clear`` 输入和 ``value`` 输出的组件。每个时钟周期 "
+"``value`` 输出都会递增，但是当 ``clear`` 为高电平时，``value`` 被清零。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/index.po
new file mode 100644
index 00000000000..e600a1c1def
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-19 09:19+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/index.rst:3
+msgid "Simple ones"
+msgstr "简单示例"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/pll_resetctrl.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/pll_resetctrl.po
new file mode 100644
index 00000000000..1c1283d8317
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/pll_resetctrl.po	
@@ -0,0 +1,61 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onespll_resetctrl/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:2
+msgid "PLL BlackBox and reset controller"
+msgstr "锁相环黑盒和复位控制器"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:4
+msgid ""
+"Let's imagine you want to define a ``TopLevel`` component which instantiates"
+" a PLL ``BlackBox``\\ , and create a new clock domain from it which will be "
+"used by your core logic. Let's also imagine that you want to adapt an "
+"external asynchronous reset into this core clock domain to a synchronous "
+"reset source."
+msgstr ""
+"假设您想要定义一个 ``TopLevel`` 组件来实例化 PLL ``BlackBox`` ，并利用它创建"
+"一个新的时钟域，该时钟域将由您的核心逻辑使用。我们还假设您希望将一个外部的异"
+"步复位适配到这个核心时钟域的同步复位源中。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:6
+msgid "The following imports will be used in code examples on this page:"
+msgstr "本页的代码示例中将默认使用以下导入："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:14
+msgid "The PLL BlackBox definition"
+msgstr "PLL BlackBox定义"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:16
+msgid "This is how to define the PLL ``BlackBox``\\ :"
+msgstr "这是定义PLL ``BlackBox`` 的方法："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:23
+msgid "This will correspond to the following VHDL component:"
+msgstr "其对应下面的VHDL组件："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:36
+msgid "TopLevel definition"
+msgstr "TopLevel定义"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/pll_resetctrl.rst:38
+msgid ""
+"This is how to define your ``TopLevel`` which instantiates the PLL, creates "
+"the new ``ClockDomain``\\ , and also adapts the asynchronous reset input to "
+"a synchronous reset:"
+msgstr ""
+"下面的例子展示了如何定义 ``TopLevel`` 来实例化锁相环，创建新的 "
+"``ClockDomain`` 并将异步复位输入调整连接至同步复位端口："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/rgb_to_gray.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/rgb_to_gray.po
new file mode 100644
index 00000000000..6f2bab645ef
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/rgb_to_gray.po	
@@ -0,0 +1,88 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onesrgb_to_gray/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:2
+msgid "RGB to gray"
+msgstr "RGB信号转灰度信号"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:4
+msgid ""
+"Let's imagine a component that converts an RGB color into a gray one, and "
+"then writes it into external memory."
+msgstr "让我们假设需要一个将RGB颜色转换为灰度并将其写入外部存储器的组件。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:10
+msgid "io name"
+msgstr "io名称"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:11
+msgid "Direction"
+msgstr "方向"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:12
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:13
+msgid "clear"
+msgstr "clear"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:14
+#: ones/rgb_to_gray.rst:17
+msgid "in"
+msgstr "in"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:15
+msgid "Clear all internal registers"
+msgstr "将所有内部寄存器清零"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:16
+msgid "r,g,b"
+msgstr "r,g,b"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:18
+msgid "Color inputs"
+msgstr "颜色输入"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:19
+msgid "wr"
+msgstr "wr"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:20
+#: ones/rgb_to_gray.rst:23 ones/rgb_to_gray.rst:26
+msgid "out"
+msgstr "out"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:21
+msgid "Memory write"
+msgstr "写存储器"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:22
+msgid "address"
+msgstr "address"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:24
+msgid "Memory address, incrementing each cycle"
+msgstr "存储器地址，每个周期增加"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:25
+msgid "data"
+msgstr "data"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/rgb_to_gray.rst:27
+msgid "Memory data, gray level"
+msgstr "存储器数据，灰度等级"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/sinus_rom.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/sinus_rom.po
new file mode 100644
index 00000000000..13d11054ee4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Simple ones/sinus_rom.po	
@@ -0,0 +1,122 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:03+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplessimple-onessinus_rom/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:4
+msgid "Sinus rom"
+msgstr "正弦rom"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:6
+msgid ""
+"Let's imagine that you want to generate a sine wave and also have a filtered"
+" version of it (which is completely useless in practical, but let's do it as"
+" an example)."
+msgstr "让我们假设您想要生成一个正弦波，并且还有它的滤波版本（这在实际中完全没用，但"
+"让我们以此为例）。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:12
+msgid "Parameters name"
+msgstr "参数名称"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:13
+#: ones/sinus_rom.rst:29
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:14
+#: ones/sinus_rom.rst:30
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:15
+msgid "resolutionWidth"
+msgstr "resolutionWidth"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:16
+#: ones/sinus_rom.rst:19
+msgid "Int"
+msgstr "Int"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:17
+msgid "Number of bits used to represent numbers"
+msgstr "用于表示数值的位宽"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:18
+msgid "sampleCount"
+msgstr "sampleCount"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:20
+msgid "Number of samples in a sine period"
+msgstr "一个正弦周期内的采样点数"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:27
+msgid "IO name"
+msgstr "IO名称"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:28
+msgid "Direction"
+msgstr "方向"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:31
+msgid "sin"
+msgstr "sin"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:32
+#: ones/sinus_rom.rst:36
+msgid "out"
+msgstr "out"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:33
+#: ones/sinus_rom.rst:37
+msgid "SInt(resolutionWidth bits)"
+msgstr "SInt(resolutionWidth bits)"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:34
+msgid "Output which plays the sine wave"
+msgstr "作为正弦波的输出"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:35
+msgid "sinFiltered"
+msgstr "sinFiltered"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:38
+msgid "Output which plays the filtered version of the sine"
+msgstr "作为滤波后正弦波的输出"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:41
+msgid "So let's define the ``Component``\\ :"
+msgstr "那么让我们定义一个 ``Component`` ："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:49
+msgid ""
+"To play the sine wave on the ``sin`` output, you can define a ROM which "
+"contain all samples of a sine period (it could be just a quarter, but let's "
+"do things the most simple way). Then you can read that ROM with an phase "
+"counter and this will generate your sine wave."
+msgstr ""
+"为了在 ``sin`` 输出端口上输出正弦波，您可以定义一个 ROM，其包含正弦波一个周期"
+"内所有采样点（可能只是四分之一，但让我们以最简单的方式做事）。然后你可以用相"
+"位计数器读取该ROM，这将生成你的正弦波。"
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:57
+msgid ""
+"Then to generate ``sinFiltered``\\ , you can for example use a first order "
+"low pass filter implementation:"
+msgstr "随后生成 ``sinFiltered`` ，例如您可以使用一个一阶低通滤波器："
+
+#: ../../source/SpinalHDL/Examples/Simple ones/sinus_rom.rst:64
+msgid "Here is the complete code:"
+msgstr "这是完整的代码："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/index.po
new file mode 100644
index 00000000000..f8c380e847d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/index.po
@@ -0,0 +1,83 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-14 06:03+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlexamplesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-rc\n"
+
+#: ../../SpinalHDL/Examples/index.rst:3
+msgid "Examples"
+msgstr "示例"
+
+#: ../../SpinalHDL/Examples/index.rst:18
+msgid "Examples are split into three kinds:"
+msgstr "示例分为三类："
+
+#: ../../SpinalHDL/Examples/index.rst:20
+msgid ""
+"Simple examples that could be used to get used to the basics of SpinalHDL."
+msgstr "可用于熟悉SpinalHDL基础知识的简单示例。"
+
+#: ../../SpinalHDL/Examples/index.rst:21
+msgid ""
+"Intermediate examples which implement components by using a traditional "
+"approach."
+msgstr "使用传统方法设计组件的中级示例。"
+
+#: ../../SpinalHDL/Examples/index.rst:22
+msgid ""
+"Advanced examples which go further than traditional HDL by using object-"
+"oriented programming, functional programming, and meta-hardware description."
+msgstr "通过使用面向对象编程、函数式编程和元硬件描述，比传统HDL更进一步的高级示例。"
+
+#: ../../SpinalHDL/Examples/index.rst:24
+msgid ""
+"They are all accessible in the sidebar under the corresponding sections."
+msgstr "它们都可以在相应部分下的侧边栏中访问。"
+
+#: ../../SpinalHDL/Examples/index.rst:27
+msgid ""
+"The SpinalHDL workshop contains many labs with their solutions. See `here "
+"<https://github.com/SpinalHDL/SpinalWorkshop>`_."
+msgstr ""
+"SpinalHDL实践教程包含许多实验及其解决方案。请参阅 `此处 <https://github.com/"
+"SpinalHDL/SpinalWorkshop>`_。"
+
+#: ../../SpinalHDL/Examples/index.rst:30
+msgid ""
+"You can also find a list of repositories using SpinalHDL :ref:`there "
+"<users_repositories>`"
+msgstr "您还可以在 :ref:`这里 <users_repositories>` 找到使用SpinalHDL的仓库列表"
+
+#: ../../SpinalHDL/Examples/index.rst:34
+msgid "Getting started"
+msgstr "入门"
+
+#: ../../SpinalHDL/Examples/index.rst:35
+msgid ""
+"All examples assume that you have the following imports on the top of your "
+"scala file:"
+msgstr "所有示例均假设您的scala文件顶部有以下导入："
+
+#: ../../SpinalHDL/Examples/index.rst:42
+msgid ""
+"To generate VHDL for a given component, you can place the following at the "
+"bottom of your scala file:"
+msgstr "要为给定组件生成 VHDL，您可以将以下内容放在scala文件的底部："
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po
new file mode 100644
index 00000000000..3e46f3cd22d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po
@@ -0,0 +1,286 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-07 15:47+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlforewordindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../SpinalHDL/Foreword/index.rst:4
+msgid "Foreword"
+msgstr "前言"
+
+#: ../../SpinalHDL/Foreword/index.rst:6
+msgid "Preliminary notes:"
+msgstr "初步说明："
+
+#: ../../SpinalHDL/Foreword/index.rst:8
+msgid ""
+"All the following statements will be about describing digital hardware. "
+"Verification is another tasty topic."
+msgstr "以下所有陈述都是关于描述数字硬件电路的。验证是另一个有趣的话题。"
+
+#: ../../SpinalHDL/Foreword/index.rst:10
+msgid ""
+"For conciseness, let's assume that SystemVerilog is a recent revision of "
+"Verilog."
+msgstr "为了简洁，我们假设SystemVerilog是Verilog的最新版本。"
+
+#: ../../SpinalHDL/Foreword/index.rst:12
+msgid ""
+"When reading this, we should not underestimate how much our attachment for "
+"our favourite HDL will bias our judgement."
+msgstr "当我们阅读这段话时，我们不应低估最喜欢的硬件描述语言对我们判断的影响。"
+
+#: ../../SpinalHDL/Foreword/index.rst:17
+msgid "Why moving away from traditional HDL"
+msgstr "为什么要放弃传统的 HDL"
+
+#: ../../SpinalHDL/Foreword/index.rst:20
+msgid "VHDL/Verilog aren't Hardware Description Languages"
+msgstr "VHDL/Verilog 不是硬件描述语言"
+
+#: ../../SpinalHDL/Foreword/index.rst:22
+msgid ""
+"Those languages are event driven languages created initially for "
+"simulation/documentation purposes. Only in a second time they were used as "
+"inputs languages for synthesis tools. Which explain the roots of a lot of "
+"the following points."
+msgstr "这些语言最初是为了模拟/文档目的而创建的事件驱动语言。只有在后来，它们才被用作"
+"综合工具的输入语言。这就解释了以下许多观点的根源。"
+
+#: ../../SpinalHDL/Foreword/index.rst:29
+msgid "Event driven paradigm doesn't make any sense for RTL"
+msgstr "事件驱动范式对于 RTL 没有任何意义"
+
+#: ../../SpinalHDL/Foreword/index.rst:31
+msgid ""
+"When you think about it, describing digital hardware (RTL) by using "
+"process/always blocks doesn't make any practical senses. Why do we have to "
+"worry about a sensitivity list? Why do we have to split our design between "
+"processes/always blocks of different natures (combinatorial logic / register"
+" without reset / register with async reset)?"
+msgstr ""
+"仔细想想，使用 process/always 块描述数字硬件 (RTL) 没有任何实际意义。为什么我"
+"们必须担心敏感列表？为什么我们必须在不同性质的进程(process)/always块之间分割"
+"我们的设计（组合逻辑/不带复位的寄存器/带异步复位的寄存器）？"
+
+#: ../../SpinalHDL/Foreword/index.rst:37
+msgid "For instance, to implement this:"
+msgstr "例如，要实现这个："
+
+#: ../../SpinalHDL/Foreword/index.rst:42
+msgid "Using VHDL processes you write this:"
+msgstr "使用 VHDL 流程，您可以编写以下内容："
+
+#: ../../SpinalHDL/Foreword/index.rst:78
+msgid "Using SpinalHDL you write this:"
+msgstr "使用 SpinalHDL 你可以这样写："
+
+#: ../../SpinalHDL/Foreword/index.rst:93
+msgid ""
+"As for everything, you can get used to this event driven semantic, until you"
+" taste something better."
+msgstr "所有事情都是这样，您可以习惯这种事件驱动的语义，直到您尝试更好的事物。"
+
+#: ../../SpinalHDL/Foreword/index.rst:98
+msgid "Recent revisions of VHDL and Verilog aren't usable"
+msgstr "VHDL 和 Verilog 的最新版本不可用"
+
+#: ../../SpinalHDL/Foreword/index.rst:100
+msgid ""
+"The EDA industry is really slow to implement VHDL 2008 and SystemVerilog "
+"synthesis capabilities in their tools. Additionally, when it's done, it "
+"appear that only a constraining subset of the language is implemented (not "
+"talking about simulation features). It result that using any interesting "
+"feature of those language revision isn't safe as:"
+msgstr ""
+"EDA 行业在其工具中实现 VHDL 2008 和 SystemVerilog 综合功能的速度确实很慢。此"
+"外，当它完成时，似乎只实现了该语言的一个约束子集（不谈论仿真功能）。结果是使"
+"用这些语言修订版的任何有趣功能都不安全，因为："
+
+#: ../../SpinalHDL/Foreword/index.rst:106
+msgid "It will probably make your code incompatible with many EDA tools."
+msgstr "它可能会使您的代码与许多 EDA 工具不兼容。"
+
+#: ../../SpinalHDL/Foreword/index.rst:107
+msgid ""
+"Other companies will likely not accept your IP as their flow isn't ready for"
+" it."
+msgstr "其他公司可能不会接受您的 IP，因为他们的流程尚未准备好。"
+
+#: ../../SpinalHDL/Foreword/index.rst:110
+msgid ""
+"Anyway, those revisions don't change the heart of those HDL issues: they are"
+" based on a event driven paradigm which doesn't make sense to describe "
+"digital hardware."
+msgstr "无论如何，这些修订并没有改变 HDL "
+"问题的核心：它们基于事件驱动范的范式，这对于描述数字硬件没有意义。"
+
+#: ../../SpinalHDL/Foreword/index.rst:116
+msgid ""
+"VHDL records, Verilog struct are broken (SystemVerilog is good on this, if "
+"you can use it)"
+msgstr "VHDL 结构记录（record），Verilog 结构（struct）已经破碎（SystemVerilog "
+"在这方面很好，如果您可以使用它）"
+
+#: ../../SpinalHDL/Foreword/index.rst:118
+msgid ""
+"You can't use them to define an interface, because you can't define their "
+"internal signal directions. Even worst, you can't give them construction "
+"parameters! So, define your RGB record/struct once, and hope you never have "
+"to use it with bigger/smaller color channels..."
+msgstr ""
+"您不能使用它们来定义接口，因为您无法定义它们的内部信号方向。更糟糕的是，您无"
+"法向他们提供构造参数！因此，只能一次性定义好 RGB "
+"记录/结构，但愿您永远不必将其与不同大小的颜色通道一起使用......"
+
+#: ../../SpinalHDL/Foreword/index.rst:123
+msgid ""
+"Also a fancy thing with VHDL is the fact that if you want to add an array of"
+" something into a component entity, you have to define the type of this "
+"array into a package... Which can't be parameterized..."
+msgstr "VHDL 的另一个奇特之处是，如果您想将某个数组添加到组件实体中，则必须将该数组的"
+"类型定义到包中...这就不能参数化了..."
+
+#: ../../SpinalHDL/Foreword/index.rst:127
+msgid "For instance, below is a SpinalHDL APB3 bus definition:"
+msgstr "例如，下面是 SpinalHDL APB3 总线定义："
+
+#: ../../SpinalHDL/Foreword/index.rst:159
+msgid ""
+"Then about the VHDL 2008 partial solution and the SystemVerilog "
+"interface/modport, lucky you are if your EDA tools / company flow / company "
+"policy allow you to use them."
+msgstr ""
+"然后VHDL 2008有部分的解决方案和SystemVerilog接口/modport也能有所帮助，如果您"
+"的EDA工具/公司流程/公司政策允许您使用它们，那么您很幸运。"
+
+#: ../../SpinalHDL/Foreword/index.rst:165
+msgid "VHDL and Verilog are so verbose"
+msgstr "VHDL 和 Verilog 太冗长了"
+
+#: ../../SpinalHDL/Foreword/index.rst:167
+msgid ""
+"Really, with VHDL and Verilog, when it starts to be about component "
+"instantiation interconnection, the copy-paste god has to be invoked."
+msgstr "对于VHDL和Verilog，当它开始涉及组件实例化互连时，必须使用Ctrl-V/C大法。"
+
+#: ../../SpinalHDL/Foreword/index.rst:170
+msgid ""
+"To understand it more deeply, below is a SpinalHDL example performing some "
+"peripherals instantiation and adding the APB3 decoder required to access "
+"them."
+msgstr "要更深入地理解它，下面是一个使用SpinalHDL实例化一些外设并添加用于访问它们所需"
+"的APB3解码器的示例。"
+
+#: ../../SpinalHDL/Foreword/index.rst:203
+msgid ""
+"Done. That's all. You don't have to bind each signal one by one when you "
+"instantiate a module/component because you can access their interfaces in a "
+"object-oriented manner."
+msgstr "完成。这就是所有内容。在实例化模块/组件时，你不必一个接一个地绑定信号，因为你"
+"可以以面向对象的方式访问它们的接口。"
+
+#: ../../SpinalHDL/Foreword/index.rst:207
+msgid ""
+"Also about VHDL/Verilog struct/records, we can say that they are really "
+"dirty tricks, without true parameterization and reusability capabilities, "
+"trying to hide the fact that those languages were poorly designed."
+msgstr ""
+"另外，关于 VHDL/Verilog 结构/记录，可以说它们确实是无用的，没有真正的参数化和"
+"可重用性功能，仅仅是试图掩盖这些语言设计不佳的事实。"
+
+#: ../../SpinalHDL/Foreword/index.rst:213
+msgid "Meta Hardware Description capabilities"
+msgstr "元硬件描述能力"
+
+#: ../../SpinalHDL/Foreword/index.rst:215
+msgid ""
+"Basically VHDL and Verilog provide some elaboration tools which aren't "
+"directly mapped into hardware as loops / generate statements / macro / "
+"function / procedure / task. But that's all."
+msgstr "VHDL 和 Verilog 提供了一些实例细化工具，这些工具不会直接映射到硬件中，如循环/"
+"生成语句/宏/函数/过程/任务。但仅此而已。"
+
+#: ../../SpinalHDL/Foreword/index.rst:219
+msgid ""
+"And even then, they are really limited. For instance, one can't define "
+"process/always/component/module blocks into a task/procedure. It is really a"
+" bottleneck for many fancy things."
+msgstr "即便如此，它们的作用也确实有限。例如，不能将进程/always块/组件/模块块定义到任"
+"务/过程中。这确实是许多高级功能的瓶颈。"
+
+#: ../../SpinalHDL/Foreword/index.rst:223
+msgid ""
+"With SpinalHDL you can call a user-defined task/procedure on a bus like "
+"that: ``myHandshakeBus.queue(depth=64)``. Below is some code including the "
+"definition."
+msgstr ""
+"使用 "
+"SpinalHDL，您可以在总线上调用用户定义的任务/过程，如下所示：``myHandshakeBus."
+"queue(depth=64)``。下面是一些包含定义的代码。"
+
+#: ../../SpinalHDL/Foreword/index.rst:249
+msgid ""
+"Let's see further, imagine you want to define a state machine. With "
+"VHDL/Verilog you have to write a lot of raw code with some switch statements"
+" to do it. You can't define the notion of \"StateMachine\", which would give"
+" you a nice syntax to define each state. Else you can use a third-party tool"
+" to draw your state machine and then generate your VHDL/Verilog equivalent "
+"code..."
+msgstr ""
+"让我们进一步想象，假设你想定义一个有限状态机。使用VHDL/"
+"Verilog，你需要编写大量原始代码，并使用一些switch语句来实现它。"
+"你不能定义\"StateMachine\"的概念，这将为你提供一个很好的语法来定义每个状态。"
+"否则，你可以使用第三方工具来绘制你的有限状态机，然后生成等价的VHDL/"
+"Verilog代码..."
+
+#: ../../SpinalHDL/Foreword/index.rst:255
+msgid ""
+"Meta-hardware description capabilities of SpinalHDL enable you to define "
+"your own tools which then allow you to define things in abstracts ways, as "
+"for state machines."
+msgstr "SpinalHDL 的元硬件描述能力使您能够定义自己的工具，然后允许您以抽象方式定义事"
+"物，例如有限状态机。"
+
+#: ../../SpinalHDL/Foreword/index.rst:259
+msgid ""
+"Below is an simple example of the usage of a state machine abstraction "
+"defined on the top of SpinalHDL:"
+msgstr "下面是SpinalHDL上有限状态机的一个简单的用法示例："
+
+#: ../../SpinalHDL/Foreword/index.rst:290
+msgid ""
+"Imagine you want to generate the instruction decoding of your CPU. It could "
+"require some fancy elaboration time algorithms to generate the less logic "
+"possible. But in VHDL/Verilog, your only option to do these kind of things "
+"is to write a script which generates the ``.vhd`` and ``.v`` that you want."
+msgstr ""
+"假设你想生成CPU的指令解码逻辑。这可能需要一些复杂的实例细化时算法来生成尽可能"
+"少的逻辑。但是，在VHDL/Verilog中，你唯一的选择是用脚本生成你想要的 ``.vhd`` "
+"和 ``.v`` 文件。"
+
+#: ../../SpinalHDL/Foreword/index.rst:295
+msgid ""
+"There is really much to say about meta-hardware description, but the only "
+"true way to understand it and get its real taste is to experiment it. The "
+"goal with it is to stop playing with wires and gates, to start taking some "
+"distance with that low level stuff, to think reusable."
+msgstr ""
+"关于元硬件描述确实有很多话要说，但理解它并得其真味的唯一方法就是进行实验。它"
+"的目标是停止直接使用电线和门，与那些抽象层级较低的东西保持一定的距离，并思考"
+"可重用的方法。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po
new file mode 100644
index 00000000000..696bb48df7a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po	
@@ -0,0 +1,381 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 01:17+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlformal-verificationindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Formal verification/index.rst:3
+msgid "Formal verification"
+msgstr "形式化验证"
+
+#: ../../SpinalHDL/Formal verification/index.rst:7
+msgid "General"
+msgstr "介绍"
+
+#: ../../SpinalHDL/Formal verification/index.rst:9
+msgid ""
+"SpinalHDL allows to generate a subset of the SystemVerilog Assertions (SVA)."
+" Mostly assert, assume, cover and a few others."
+msgstr ""
+"SpinalHDL 允许生成 SystemVerilog 断言 (SVA) "
+"的子集。主要是断言（assert）、假设（assume）、覆盖（cover）和其他一些内容。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:11
+msgid ""
+"In addition it provide a formal verification backend which allows to "
+"directly run the formal verification in the open-source Symbi-Yosys "
+"toolchain."
+msgstr "此外，它还提供了形式化验证后端，允许直接在开源 Symbi-Yosys "
+"工具链中运行形式化验证。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:16
+msgid "Formal backend"
+msgstr "形式化验证后端"
+
+#: ../../SpinalHDL/Formal verification/index.rst:18
+msgid "You can run the formal verification of a component via:"
+msgstr "您可以通过以下方式运行组件的形式化验证："
+
+#: ../../SpinalHDL/Formal verification/index.rst:28
+msgid "Currently, 3 modes are supported :"
+msgstr "目前支持3种模式："
+
+#: ../../SpinalHDL/Formal verification/index.rst:30
+msgid "withBMC(depth)"
+msgstr "withBMC(depth)"
+
+#: ../../SpinalHDL/Formal verification/index.rst:31
+msgid "withProve(depth)"
+msgstr "withProve(depth)"
+
+#: ../../SpinalHDL/Formal verification/index.rst:32
+msgid "withCover(depth)"
+msgstr "withCover(depth)"
+
+#: ../../SpinalHDL/Formal verification/index.rst:35
+msgid "Installing requirements"
+msgstr "安装要求"
+
+#: ../../SpinalHDL/Formal verification/index.rst:37
+msgid ""
+"To install the Symbi-Yosys, you have a few options. You can fetch a "
+"precompiled package at:"
+msgstr "要安装 Symbi-Yosys，您有几种选择。您可以在以下位置获取预编译包："
+
+#: ../../SpinalHDL/Formal verification/index.rst:39
+msgid "https://github.com/YosysHQ/oss-cad-suite-build/releases"
+msgstr "https://github.com/YosysHQ/oss-cad-suite-build/releases"
+
+#: ../../SpinalHDL/Formal verification/index.rst:40
+msgid ""
+"https://github.com/YosysHQ/fpga-toolchain/releases (EOL - superseded by oss-"
+"cad-suite)"
+msgstr ""
+"https://github.com/YosysHQ/fpga-toolchain/releases（EOL - 由 oss-cad-suite "
+"取代）"
+
+#: ../../SpinalHDL/Formal verification/index.rst:42
+msgid "Or you can compile things from scratch :"
+msgstr "或者你可以从头开始编译："
+
+#: ../../SpinalHDL/Formal verification/index.rst:44
+msgid "https://symbiyosys.readthedocs.io/en/latest/install.html"
+msgstr "https://symbiyosys.readthedocs.io/en/latest/install.html"
+
+#: ../../SpinalHDL/Formal verification/index.rst:48
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Formal verification/index.rst:52
+msgid "External assertions"
+msgstr "外部断言"
+
+#: ../../SpinalHDL/Formal verification/index.rst:54
+msgid ""
+"Here is an example of a simple counter and the corresponding formal "
+"testbench."
+msgstr "这是一个简单计数器和相应的形式化测试代码的示例。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:91
+msgid "Internal assertions"
+msgstr "内部断言"
+
+#: ../../SpinalHDL/Formal verification/index.rst:93
+msgid "If you want you can embed formal statements directly into the DUT:"
+msgstr "如果您愿意，可以将形式化验证语句直接嵌入到 DUT 中："
+
+#: ../../SpinalHDL/Formal verification/index.rst:120
+msgid "External stimulus"
+msgstr "外部激励"
+
+#: ../../SpinalHDL/Formal verification/index.rst:122
+msgid ""
+"If your DUT has inputs, you need to drive them from the testbench. You can "
+"use all the regular hardware statements to do it, but you can also use the "
+"formal `anyseq`, `anyconst`, `allseq`, `allconst` statement:"
+msgstr ""
+"如果您的 DUT "
+"有输入，您需要从测试代码中驱动它们。您可以使用所有常规硬件语句来执行此操作，"
+"但您也可以使用形式化验证中的 `anyseq`、`anyconst`、`allseq`、`allconst` "
+"语句："
+
+#: ../../SpinalHDL/Formal verification/index.rst:151
+msgid "More assertions / past"
+msgstr "更多关于断言/past（以前某个时钟内的状态）的例子"
+
+#: ../../SpinalHDL/Formal verification/index.rst:153
+msgid ""
+"For instance we can check that the value is counting up (if not already at "
+"10):"
+msgstr "例如，我们可以检查该值是否在正向计数（如果尚未达到 10）："
+
+#: ../../SpinalHDL/Formal verification/index.rst:169
+msgid "Assuming memory content"
+msgstr "假设内存中的内容"
+
+#: ../../SpinalHDL/Formal verification/index.rst:171
+msgid ""
+"Here is an example where we want to prevent the value ``1`` from ever being "
+"present in a memory :"
+msgstr "这是一个示例，我们希望防止值 ``1`` 出现在内存中："
+
+#: ../../SpinalHDL/Formal verification/index.rst:207
+msgid "Utilities and primitives"
+msgstr "实用工具和原语"
+
+#: ../../SpinalHDL/Formal verification/index.rst:210
+msgid "Assertions / clock / reset"
+msgstr "断言/时钟/复位"
+
+#: ../../SpinalHDL/Formal verification/index.rst:212
+msgid ""
+"Assertions are always clocked and disabled during resets. This also apply "
+"for assumes and covers."
+msgstr "断言（assert）是一直被时钟驱动的，但在复位期间被禁用。这也适用于假设（assume"
+"）和覆盖（cover）。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:214
+msgid "If you want to keep your assertion enabled during reset you can do:"
+msgstr "如果您想在复位期间保持断言被检查，您可以执行以下操作："
+
+#: ../../SpinalHDL/Formal verification/index.rst:224
+msgid "Specifying the initial value of a signal"
+msgstr "指定信号的初始值"
+
+#: ../../SpinalHDL/Formal verification/index.rst:226
+msgid ""
+"For instance, for the reset signal of the current clockdomain (usefull at "
+"the top)"
+msgstr "例如，对于当前时钟域的复位信号（在顶部有用）"
+
+#: ../../SpinalHDL/Formal verification/index.rst:233
+msgid "Specifying a initial assumption"
+msgstr "指定初始假设"
+
+#: ../../SpinalHDL/Formal verification/index.rst:240
+msgid "Memory content (Mem)"
+msgstr "内存内容（Mem）检查"
+
+#: ../../SpinalHDL/Formal verification/index.rst:242
+msgid ""
+"If you have a Mem in your design, and you want to check its content, you can"
+" do it the following ways :"
+msgstr "如果您的设计中有 Mem，并且想要检查其内容，可以通过以下方式进行："
+
+#: ../../SpinalHDL/Formal verification/index.rst:257
+msgid "Specifying assertion in the reset scope"
+msgstr "在复位的时候进行断言检查，可以这样做"
+
+#: ../../SpinalHDL/Formal verification/index.rst:267
+msgid "Formal primitives"
+msgstr "形式化验证的原语"
+
+#: ../../SpinalHDL/Formal verification/index.rst:273
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Formal verification/index.rst:274
+msgid "Returns"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Formal verification/index.rst:275
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Formal verification/index.rst:276
+msgid "``assert(Bool)``"
+msgstr "``assert(Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:279
+msgid "``assume(Bool)``"
+msgstr "``assume(Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:282
+msgid "``cover(Bool)``"
+msgstr "``cover(Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst
+msgid "``past(that : T, delay : Int)``"
+msgstr "``past(that : T, delay : Int)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst
+msgid "``past(that : T)``"
+msgstr "``past(that : T)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:287
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Formal verification/index.rst:288
+msgid "Return ``that`` delayed by ``delay`` cycles. (default 1 cycle)"
+msgstr "返回 ``delay`` 周期以前的 ``that``值 。 （默认1个周期）"
+
+#: ../../SpinalHDL/Formal verification/index.rst:289
+msgid "``rose(that : Bool)``"
+msgstr "``rose(that : Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:290
+#: verification/index.rst:293 verification/index.rst:296
+#: verification/index.rst:299 verification/index.rst:302
+#: verification/index.rst:305 verification/index.rst:308
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Formal verification/index.rst:291
+msgid "Return True when ``that`` transitioned from False to True"
+msgstr "当 ``that`` 从 False 变为 True 时返回 True"
+
+#: ../../SpinalHDL/Formal verification/index.rst:292
+msgid "``fell(that : Bool)``"
+msgstr "``fell(that : Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:294
+msgid "Return True when ``that`` transitioned from True to False"
+msgstr "当 ``that`` 从 True 变为 False 时返回 True"
+
+#: ../../SpinalHDL/Formal verification/index.rst:295
+msgid "``changed(that : Bool)``"
+msgstr "``changed(that : Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:297
+msgid ""
+"Return True when ``that`` current value changed between compared to the last"
+" cycle"
+msgstr "当 ``that`` 当前值与上一个周期相比发生变化时返回 True"
+
+#: ../../SpinalHDL/Formal verification/index.rst:298
+msgid "``stable(that : Bool)``"
+msgstr "``stable(that : Bool)``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:300
+msgid ""
+"Return True when ``that`` current value didn't changed between compared to "
+"the last cycle"
+msgstr "当 ``that`` 当前值与上一个周期相比没有改变时返回 True"
+
+#: ../../SpinalHDL/Formal verification/index.rst:301
+msgid "``initstate()``"
+msgstr "``initstate()``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:303
+msgid "Return True the first cycle"
+msgstr "第一个周期时返回 True"
+
+#: ../../SpinalHDL/Formal verification/index.rst:304
+msgid "``pastValid()``"
+msgstr "``pastValid()``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:306
+msgid ""
+"Returns True when the past value is valid (False on the first cycle). "
+"Recommended to be used with each application of ``past``, ``rose``, "
+"``fell``, ``changed`` and ``stable``."
+msgstr ""
+"当过去的值有效时返回 True（第一个周期为 False）。建议在 ``past``, ``rose``, "
+"``fell``, ``changed`` 和 ``stable`` 每次使用的地方均使用它。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:307
+msgid "``pastValidAfterReset()``"
+msgstr "``pastValidAfterReset()``"
+
+#: ../../SpinalHDL/Formal verification/index.rst:309
+msgid ""
+"Simliar to ``pastValid``, where only difference is that this would take "
+"reset into account. Can be understood as ``pastValid & past(!reset)``."
+msgstr ""
+"与“pastValid”类似，唯一的区别是这会考虑重置。可以理解为 ``pastValid & "
+"past(!reset)``，同步逻辑中建议使用。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:311
+msgid "Note that you can use the init statement on past:"
+msgstr "请注意，您可以对past的返回值使用 init 语句："
+
+#: ../../SpinalHDL/Formal verification/index.rst:320
+msgid "Limitations"
+msgstr "局限性"
+
+#: ../../SpinalHDL/Formal verification/index.rst:322
+msgid ""
+"There is no support for unclocked assertions. But their usage in third party"
+" formal verification examples seems mostly code style related."
+msgstr "不支持非时钟驱动的断言。但它们在第三方形式化验证示例中有这样使用，似乎主要与"
+"代码风格相关。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:326
+msgid "Naming polices"
+msgstr "命名策略"
+
+#: ../../SpinalHDL/Formal verification/index.rst:328
+msgid ""
+"All formal validation related functions return Area or Composite "
+"(preferred), and naming as formalXXXX. ``formalContext`` can be used to "
+"create formal related logic, there could be ``formalAsserts``, "
+"``formalAssumes`` and ``formalCovers`` in it."
+msgstr ""
+"所有与形式验证相关的函数都返回 Area 或 "
+"Composite（首选），并命名为formalXXXX。 ``formalContext`` "
+"可用于创建形式相关逻辑，还有可能是 ``formalAsserts``、 ``formalAssumes`` 和 "
+"``formalCovers`` 。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:332
+msgid "For Component"
+msgstr "对于组件"
+
+#: ../../SpinalHDL/Formal verification/index.rst:333
+msgid ""
+"The minimum required assertions internally in a ``Component`` for \"prove\" "
+"can be named as ``formalAsserts``."
+msgstr "证明模式中需要的， ``Component`` 内部所需的最少断言可以命名为 "
+"``formalAsserts``。"
+
+#: ../../SpinalHDL/Formal verification/index.rst:336
+msgid "For interfaces implement IMasterSlave"
+msgstr "对于实现 IMasterSlave的接口"
+
+#: ../../SpinalHDL/Formal verification/index.rst:337
+msgid ""
+"There could be functions in name ``formalAssertsMaster``, "
+"``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or "
+"``formalCovers``. Master/Slave are target interface type, so that "
+"``formalAssertsMaster`` can be understand as \"formal verfication assertions"
+" for master interface\"."
+msgstr ""
+"可能存在以 ``formalAssertsMaster``, ``formalAssertsSlave``, "
+"``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers`` "
+"命名的函数。 Master/Slave 是目标接口类型，因此，``formalAssertsMaster`` "
+"可以理解为“主接口的形式化验证断言”。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/core.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/core.po
new file mode 100644
index 00000000000..1726bfef099
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/core.po	
@@ -0,0 +1,28 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedcheatsheetscore/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/core.rst:2
+msgid "Core"
+msgstr "Core"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/core.rst:3
+msgid ""
+"Redirection to "
+"https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_core_oo.pdf"
+msgstr ""
+"重定向到 https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/"
+"cheatSheet_core_oo.pdf"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/index.po
new file mode 100644
index 00000000000..8e3a9851f52
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedcheatsheetsindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/index.rst:3
+msgid "Cheatsheets"
+msgstr "快速参考"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/lib.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/lib.po
new file mode 100644
index 00000000000..607849bd93c
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/lib.po	
@@ -0,0 +1,28 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedcheatsheetslib/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/lib.rst:2
+msgid "Lib"
+msgstr "Lib"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/lib.rst:4
+msgid ""
+"Redirection to "
+"https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_lib_oo.pdf"
+msgstr ""
+"重定向到 https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/"
+"cheatSheet_lib_oo.pdf"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/symbolic.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/symbolic.po
new file mode 100644
index 00000000000..21ae7c88893
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Cheatsheets/symbolic.po	
@@ -0,0 +1,28 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedcheatsheetssymbolic/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/symbolic.rst:2
+msgid "Symbolic"
+msgstr "Symbolic"
+
+#: ../../source/SpinalHDL/Getting Started/Cheatsheets/symbolic.rst:4
+msgid ""
+"Redirection to "
+"https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/cheatSheet_symbolic.pdf"
+msgstr ""
+"重定向到 https://github.com/SpinalHDL/SpinalDoc/blob/master/cheatsheet/"
+"cheatSheet_symbolic.pdf"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/index.po
new file mode 100644
index 00000000000..b8673e4cf8e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedhelp-for-vhdl-peopleindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for people/index.rst:3
+msgid "Help for VHDL people"
+msgstr "VHDL 用户入门"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po
new file mode 100644
index 00000000000..f6a3122fa4a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po	
@@ -0,0 +1,431 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedhelp-for-vhdl-peoplevhdl_comp/zh_Hans/>"
+"\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for people/vhdl_comp.rst:5
+msgid "VHDL comparison"
+msgstr "与VHDL对比"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for people/vhdl_comp.rst:8
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:10
+msgid ""
+"This page will show the main differences between VHDL and SpinalHDL. Things "
+"will not be explained in depth."
+msgstr "本页将讨论 VHDL 和 SpinalHDL 之间的主要区别。但不会深入解释。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:13
+msgid "Process"
+msgstr "过程（Process）"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:15
+msgid ""
+"Processes are often needed when you write RTL, however, their semantics can "
+"be clunky to work with. Due to how they work in VHDL, they can force you to "
+"split your code and duplicate things."
+msgstr "通常编写 RTL 时需要用到过程，但是它们的语义使用起来可能很笨拙。由于它们在 "
+"VHDL 中的工作方式，可能会迫使您拆分代码并重复编写。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:17
+msgid "To produce the following RTL:"
+msgstr "要生成以下 RTL："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:21
+msgid "You will have to write the following VHDL:"
+msgstr "您必须编写以下 VHDL："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:57
+msgid "While in SpinalHDL, it's:"
+msgstr "在 SpinalHDL 中，它是："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:73
+msgid "Implicit vs explicit definitions"
+msgstr "隐式与显式定义对比"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:75
+msgid ""
+"In VHDL, when you declare a signal, you don't specify if it is a "
+"combinatorial signal or a register. Where and how you assign to it decides "
+"whether it is combinatorial or registered."
+msgstr "在 VHDL 中，当声明一个信号时，您无需指定它是组合信号还是寄存器。给它赋值的位"
+"置和方式决定了它是组合电路还是寄存器。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:77
+msgid ""
+"In SpinalHDL these kinds of things are explicit. Registers are defined as "
+"registers directly in their declaration."
+msgstr "在 SpinalHDL 中，这些事情是明确的。寄存器直接在其声明中就定义为寄存器。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:80
+msgid "Clock domains"
+msgstr "时钟域"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:82
+msgid ""
+"In VHDL, every time you want to define a bunch of registers, you need the "
+"carry the clock and the reset wire to them. In addition, you have to "
+"hardcode everywhere how those clock and reset signals should be used (clock "
+"edge, reset polarity, reset nature (async, sync))."
+msgstr ""
+"在 VHDL 中，每次想要定义一堆寄存器时，都需要将时钟和复位信号传递给它们。此外"
+"，您必须在各处硬编码如何使用这些时钟和复位信号（包括它们的属性时钟沿、复位极"
+"性、复位性质（异步、同步））。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:84
+msgid ""
+"In SpinalHDL you can define a ``ClockDomain``, and then define the area of "
+"your hardware that uses it."
+msgstr "在 SpinalHDL 中，您可以定义 ``ClockDomain``，然后定义使用它的硬件区域。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:86
+msgid "For example:"
+msgstr "例如："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:107
+msgid "Component's internal organization"
+msgstr "组件的内部组织方式"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:109
+msgid ""
+"In VHDL, there is a ``block`` feature that allows you to define sub-areas of"
+" logic inside your component. However, almost no one uses this feature, "
+"because most people don't know about them, and also because all signals "
+"defined inside these regions are not readable from the outside."
+msgstr ""
+"在 VHDL 中，有一个 ``block`` 功能，允许您在组件内定义逻辑子区域。然而，几乎没"
+"有人使用这一功能，因为大多数人不了解它们，也因为这些区域内定义的所有信号都无"
+"法从外部读取、使用。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:111
+msgid ""
+"In SpinalHDL you have an ``Area`` feature that does this concept much more "
+"nicely:"
+msgstr "在 SpinalHDL 中，你有一个 ``Area`` 功能，可以更好地实现这个概念："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:131
+msgid ""
+"Variables and signals defined inside of an ``Area`` are accessible elsewhere"
+" in the component, including in other ``Area`` regions."
+msgstr "在 ``Area`` 内部定义的变量和信号可以在组件的其他地方访问，包括其他 ``Area`` "
+"区域内。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:134
+msgid "Safety"
+msgstr "安全性"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:136
+msgid ""
+"In VHDL as in SpinalHDL, it's easy to write combinatorial loops, or to infer"
+" a latch by forgetting to drive a signal in the path of a process."
+msgstr "在 VHDL 中，就像在 SpinalHDL 中一样，很容易编写出组合逻辑环，或者因为忘记给路"
+"径中的信号驱动而得到一个锁存器（latch）。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:138
+msgid ""
+"Then, to detect those issues, you can use some ``lint`` tools that will "
+"analyze your VHDL, but those tools aren't free. In SpinalHDL the ``lint`` "
+"process in integrated inside the compiler, and it won't generate the RTL "
+"code until everything is fine. It also checks clock domain crossing."
+msgstr ""
+"然后，为了检测这些问题，您可以使用一些 ``lint`` 工具来分析您的 "
+"VHDL，但这些工具不是免费的。在 SpinalHDL 中， ``lint`` 过程集成在编译器内部，"
+"并且在一切正常之前它不会生成 RTL 代码。此外，它还会检查跨时钟域信号。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:141
+msgid "Functions and procedures"
+msgstr "功能与流程"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:143
+msgid ""
+"Functions and procedures are not used very often in VHDL, probably because "
+"they are very limited:"
+msgstr "函数和过程在 VHDL 中不经常使用，可能是因为它们的功能非常有限："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:145
+msgid ""
+"You can only define a chunk of combinational hardware, or only a chunk of "
+"registers (if you call the function/procedure inside a clocked process)."
+msgstr "您只能定义一块组合逻辑硬件，或者只能定义一块寄存器（如果您在时钟进程内调用函"
+"数/过程）。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:146
+msgid "You can't define a process inside them."
+msgstr "您无法在其中定义流程。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:147
+msgid "You can't instantiate a component inside them."
+msgstr "您无法在其中实例化组件。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:148
+msgid "The scope of what you can read/write inside them is limited."
+msgstr "在这里面，您可以读/写的范围是有限的。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:150
+msgid "In SpinalHDL, all those limitations are removed."
+msgstr "在 SpinalHDL 中，所有这些限制都被消除了。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:152
+msgid ""
+"An example that mixes combinational logic and a register in a single "
+"function:"
+msgstr "在单个函数中混合使用组合逻辑和寄存器的示例："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:168
+msgid ""
+"An example with the queue function inside the Stream Bundle (handshake). "
+"This function instantiates a FIFO component:"
+msgstr "Stream线束内的队列函数示例（带握手）。该函数实例化一个 FIFO 组件："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:184
+msgid ""
+"An example where a function assigns a signal defined outside of itself:"
+msgstr "为在外部定义的信号赋值的示例函数："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:200
+msgid "Buses and Interfaces"
+msgstr "总线和接口"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:202
+msgid ""
+"VHDL is very boring when it comes to buses and interfaces. You have two "
+"options:"
+msgstr "当谈到总线和接口时，VHDL 非常无聊。您有两个选择："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:204
+msgid "Define buses and interfaces wire-by-wire, each time and everywhere:"
+msgstr "随时随地逐线定义总线和接口："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:216
+msgid ""
+"Use records but lose parameterization (statically fixed in the package), and"
+" you have to define one for each directions:"
+msgstr "使用记录但无法参数化（静态固定在包中），并且您必须为每个信号定义方向："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:223
+msgid ""
+"SpinalHDL has very strong support for bus and interface declarations with "
+"limitless parameterizations:"
+msgstr "SpinalHDL 对参数化总线和接口的声明提供非常强大的支持："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:229
+msgid ""
+"You can also use object oriented programming to define configuration "
+"objects:"
+msgstr "您还可以使用面向对象编程来定义专门的配置对象："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:273
+msgid "Signal declaration"
+msgstr "信号声明"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:275
+msgid ""
+"VHDL forces you to define all signals at the top of your architecture "
+"description, which is annoying."
+msgstr "VHDL 强制您在架构描述的顶部定义所有信号，这很烦人。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:295
+msgid "SpinalHDL is flexible when it comes to signal declarations."
+msgstr "SpinalHDL 在信号声明方面非常灵活。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:302
+msgid "It also allows you to define and assign signals in a single line."
+msgstr "它还允许您在一行中定义和赋值信号。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:309
+msgid "Component instantiation"
+msgstr "组件实例化"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:311
+msgid ""
+"VHDL is very verbose about this, as you have to redefine all signals of your"
+" sub-component entity, and then bind them one-by-one when you instantiate "
+"your component."
+msgstr "VHDL 对此非常冗长，因为您必须重新定义子组件实体的所有信号，然后在实例化组件时"
+"将它们一一绑定。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:338
+msgid ""
+"SpinalHDL removes that, and allows you to access the IO of sub-components in"
+" an object-oriented way."
+msgstr "SpinalHDL 在这方面做出了很大提升，并允许您以面向对象的方式访问子组件的 IO。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:349
+msgid "Casting"
+msgstr "类型转换"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:351
+msgid "There are two annoying casting methods in VHDL:"
+msgstr "VHDL 中有两种烦人的转换方法："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:353
+msgid ""
+"boolean <> std_logic (ex: To assign a signal using a condition such as "
+"``mySignal <= myValue < 10`` is not legal)"
+msgstr "boolean <> std_logic （例如：使用 ``mySignal <= myValue < 10`` "
+"等条件赋值信号是不合法的）"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:354
+msgid "unsigned <> integer  (ex: To access an array)"
+msgstr "unsigned <> integer（例如：访问数组）"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:356
+msgid "SpinalHDL removes these casts by unifying things."
+msgstr "SpinalHDL 通过统一化对象来转换这些类型。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:358
+msgid "boolean/std_logic:"
+msgstr "boolean/std_logic:"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:366
+msgid "unsigned/integer:"
+msgstr "unsigned/integer:"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:375
+msgid "Resizing"
+msgstr "调整位宽"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:377
+msgid "The fact that VHDL is strict about bit size is probably a good thing."
+msgstr "VHDL 对位宽限制严格可能是一件好事。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:383
+msgid "In SpinalHDL you have two ways to do the same:"
+msgstr "在 SpinalHDL 中，您有两种方法可以实现相同的目的："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:394
+msgid "Parameterization"
+msgstr "参数化"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:396
+msgid ""
+"VHDL prior to the 2008 revision has many issues with generics. For example, "
+"you can't parameterize records, you can't parameterize arrays in the entity,"
+" and you can't have type parameters."
+msgstr "2008 年修订版之前的 VHDL 在泛型方面存在许多问题。例如，您不能参数化记录，不能"
+"参数化实体中的数组，并且不能具有类型参数。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:397
+msgid ""
+"Then VHDL 2008 came and fixed those issues. But RTL tool support for VHDL "
+"2008 is really weak depending on the vendor."
+msgstr "然后 VHDL 2008 出现并解决了这些问题。但根据供应商的不同，RTL 工具对VHDL 2008 "
+"的支持确实很弱。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:399
+msgid ""
+"SpinalHDL has full support for generics integrated natively in its compiler,"
+" and it doesn't rely on VHDL generics."
+msgstr "SpinalHDL 完全支持在其编译器中自然的集成泛型，并且它不依赖于 VHDL 泛型。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:401
+msgid "Here is an example of parameterized data structures:"
+msgstr "这是参数化数据结构的示例："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:409
+msgid "Here is an example of a parameterized component:"
+msgstr "以下是参数化组件的示例："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:422
+msgid "Meta hardware description"
+msgstr "元硬件描述"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:424
+msgid ""
+"VHDL has kind of a closed syntax. You can't add abstraction layers on top of"
+" it."
+msgstr "VHDL 具有某种封闭的语法。您无法在其上添加抽象层。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:426
+msgid ""
+"SpinalHDL, because it's built on top of Scala, is very flexible, and allows "
+"you to define new abstraction layers very easily."
+msgstr "而SpinalHDL， 由于它构建在 Scala "
+"之上，所以非常灵活，并且允许您非常轻松地定义新的抽象层。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_comp.rst:428
+msgid ""
+"Some examples of this flexibility are the :ref:`FSM <state_machine>` "
+"library, the :ref:`BusSlaveFactory <bus_slave_factory>` library, and also "
+"the :ref:`JTAG <jtag>` library."
+msgstr ""
+"这种灵活性在后面的库中表现突出： :ref:`FSM <state_machine>` 库、 :ref:`"
+"BusSlaveFactory <bus_slave_factory>` 库以及 :ref:`JTAG <jtag>` 库。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.po
new file mode 100644
index 00000000000..ad07b17f18f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.po	
@@ -0,0 +1,237 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedhelp-for-vhdl-peoplevhdl_perspective/"
+"zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:5
+msgid "VHDL equivalences"
+msgstr "VHDL 等效语法"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:8
+msgid "Entity and architecture"
+msgstr "实体和架构"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:10
+msgid ""
+"In SpinalHDL, a VHDL entity and architecture are both defined inside a "
+"``Component``."
+msgstr "在 SpinalHDL 中，VHDL 实体和架构都在 ``Component`` 内定义。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:12
+msgid ""
+"Here is an example of a component which has 3 inputs (``a``, ``b``, ``c``) "
+"and an output (``result``). This component also has an ``offset`` "
+"construction parameter (like a VHDL generic)."
+msgstr ""
+"这是一个具有 3 个输入（``a``、``b``、``c``）和一个输出（``result``）的组件。"
+"该组件还有一个 ``offset`` 构造参数（类似于 VHDL generic）。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:24
+msgid "Then to instantiate that component, you don't need to bind it:"
+msgstr "然后实例化该组件，您不需要绑定它："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:43
+msgid "Data types"
+msgstr "数据类型"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:45
+msgid "SpinalHDL data types are similar to the VHDL ones:"
+msgstr "SpinalHDL 与 VHDL 相似的数据类型："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:50 people/vhdl_perspective.rst:68
+msgid "VHDL"
+msgstr "VHDL"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:51 people/vhdl_perspective.rst:69
+msgid "SpinalHDL"
+msgstr "SpinalHDL"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:52
+msgid "std_logic"
+msgstr "std_logic"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:53
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:54
+msgid "std_logic_vector"
+msgstr "std_logic_vector"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:55
+msgid "Bits"
+msgstr "位"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:56
+msgid "unsigned"
+msgstr "unsigned"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:57
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:58
+msgid "signed"
+msgstr "signed"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:59
+msgid "SInt"
+msgstr "SInt"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:62
+msgid ""
+"In VHDL, to define an 8 bit ``unsigned`` you have to give the range of bits "
+"``unsigned(7 downto 0)``,"
+msgstr "在 VHDL 中，要定义 8 位 ``unsigned`` ，您必须给出位范围 ``unsigned(7 downto "
+"0)``，"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:63
+msgid ""
+"whereas in SpinalHDL you simply supply the number of bits ``UInt(8 bits)``."
+msgstr "而在 SpinalHDL 中，您只需提供位数 ``UInt(8 bits)``。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:70
+msgid "records"
+msgstr "records"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:71
+msgid "Bundle"
+msgstr "Bundle"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:72
+msgid "array"
+msgstr "array"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:73
+msgid "Vec"
+msgstr "Vec"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:74
+msgid "enum"
+msgstr "enum"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:75
+msgid "SpinalEnum"
+msgstr "SpinalEnum"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:77
+msgid ""
+"Here is an example of the SpinalHDL ``Bundle`` definition. ``channelWidth`` "
+"is a construction parameter, like VHDL generics, but for data structures:"
+msgstr ""
+"这是 SpinalHDL ``Bundle`` 定义的示例。 ``channelWidth`` 是一个构造参数，"
+"类似于 VHDL 泛型，但用于数据结构："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:85
+msgid ""
+"Then for example, to instantiate a ``Bundle``, you need to write ``val "
+"myColor = RGB(channelWidth=8)``."
+msgstr "例如，要实例化一个 ``Bundle``，您需要这样写 ``val myColor = "
+"RGB(channelWidth=8)``。"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:88
+msgid "Signal"
+msgstr "信号"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:90
+msgid "Here is an example about signal instantiations:"
+msgstr "这是一个关于信号实例化的示例："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:107
+msgid "Assignments"
+msgstr "赋值"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:109
+msgid ""
+"In SpinalHDL, the ``:=`` assignment operator is equivalent to the VHDL "
+"signal assignment (``<=``):"
+msgstr "在 SpinalHDL 中，``:=`` 赋值运算符相当于 VHDL 信号赋值 (``<=``)："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:116
+msgid ""
+"Conditional assignments are done like in VHDL by using ``if``/``case`` "
+"statements:"
+msgstr "在 VHDL 中，条件赋值通过使用 ``if``/``case`` 语句来完成："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:141
+msgid "Literals"
+msgstr "字面量（Literals）"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:143
+msgid "Literals are a little bit different than in VHDL:"
+msgstr "与 VHDL 中的字面量略有不同："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:163
+msgid "Registers"
+msgstr "寄存器"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:165
+msgid ""
+"In SpinalHDL, registers are explicitly specified while in VHDL registers are"
+" inferred. Here is an example of SpinalHDL registers:"
+msgstr "在 SpinalHDL 中，寄存器是显式指定的，而在 VHDL 中寄存器是推断的。以下是 "
+"SpinalHDL 寄存器的示例："
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:175
+msgid "Process blocks"
+msgstr "过程块"
+
+#: ../../source/SpinalHDL/Getting Started/Help VHDL for
+#: people/vhdl_perspective.rst:177
+msgid ""
+"Process blocks are a simulation feature that is unnecessary to design RTL. "
+"It's why SpinalHDL doesn't contain any feature analogous to process blocks, "
+"and you can assign what you want, where you want."
+msgstr ""
+"过程块是一种仿真功能，对于设计 RTL 来说是不必要的。这就是为什么 SpinalHDL "
+"不包含任何类似于过程块的功能，并且您可以在您想要的位置分配您想要的内容。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po
new file mode 100644
index 00000000000..5b442184212
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po	
@@ -0,0 +1,686 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"POT-Creation-Date: 2024-01-27 15:39+0000\n"
+"PO-Revision-Date: 2024-01-28 14:12+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedinstall-and-setup/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:4
+msgid "Install and setup"
+msgstr "安装和设置"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:6
+msgid ""
+"Spinal is a Scala library (a programming language using the Java VM) so "
+"it requires setting up a Scala environment; there are many ways to do so."
+" Also, it generates VHDL, Verilog or SystemVerilog, which can be used by "
+"many different tools. This section describes the supported way to install"
+" a *SpinalHDL description to Simulation* flow, but there can be many "
+"variations."
+msgstr ""
+"Spinal是一个Scala库（使用Java VM的编程语言），因此需要设置Scala环境；有很多方法可以做到这一点。此外，它还生成 "
+"VHDL、Verilog 或 SystemVerilog，可供许多不同的工具使用。本节介绍支持的 *SpinalHDL 描述到仿真* "
+"流程的安装方法，但可能还有其他方法。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:13
+msgid "Required/Recommended tools"
+msgstr "必需/推荐的工具"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:15
+msgid ""
+"Before you download the SpinalHDL tools, you need to install a Scala "
+"environment:"
+msgstr "在下载 SpinalHDL 工具之前，您需要安装 Scala 环境："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:17
+msgid ""
+"`Java JDK <https://www.oracle.com/java/technologies/downloads/>`_, a Java"
+" environment"
+msgstr "`Java JDK <https://www.oracle.com/java/technologies/downloads/>`_，Java 环境"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:19
+msgid "`Scala 2 <https://www.scala-lang.org/>`_, compiler and library"
+msgstr "`Scala 2 <https://www.scala-lang.org/>`_，编译器和库"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:20
+msgid "`SBT <https://www.scala-sbt.org/download/>`_, a Scala build tool"
+msgstr "`SBT <https://www.scala-sbt.org/download/>`_ ，Scala 程序构建工具"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:22
+msgid ""
+"These tools enable to use Spinal; but without any other tools, it is "
+"limited to HDL code generation."
+msgstr "这些工具可以支持使用 Spinal生成代码；但在没有任何其他工具的情况下，它仅限于HDL代码生成。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:25
+msgid "To enable more features we recommend:"
+msgstr "要启用更多功能，我们建议："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:27
+msgid ""
+"An IDE (for instance the currently recommended `IntelliJ "
+"<https://www.jetbrains.com/idea/>`_ with its Scala plugin or `VSCodium "
+"<https://vscodium.com/>`_ with Metals extension) to get features such as:"
+msgstr ""
+"一个 IDE（例如当前推荐的带有 Scala 插件的 `IntelliJ <https://www.jetbrains.com/idea/>`_ "
+"或带有 Metals 扩展的 `VSCodium <https://vscodium.com/>`_ ）可获得如下功能："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:31
+msgid "Code suggestions / completion"
+msgstr "代码建议/自动完成"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:32
+msgid "Automatic build with syntax errors right in the code"
+msgstr "自动构建，在代码中显示存在语法错误"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:33
+msgid "Generate code with a single click"
+msgstr "通过单击生成代码"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:34
+msgid ""
+"Run simulation / tests with a single click (if a supported simulator is "
+"set up)"
+msgstr "单击即可运行仿真/测试（如果设置了支持的仿真器）"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:37
+msgid ""
+"A supported simulator like `Verilator "
+"<https://www.veripool.org/verilator/>`_ to test the design right from "
+"SpinalHDL."
+msgstr ""
+"支持的仿真器，例如 `Verilator <https://www.veripool.org/verilator/>`_ ，可以直接从 "
+"SpinalHDL 测试设计。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:39
+msgid ""
+"`Gtkwave <https://gtkwave.sourceforge.net/>`_ to view the waves generated"
+" by Verilator during simulation."
+msgstr "`Gtkwave <https://gtkwave.sourceforge.net/>`_ 查看 Verilator 在仿真过程中生成的波形。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:41
+msgid "`Git <https://git-scm.com/>`_ for version control system"
+msgstr "`Git <https://git-scm.com/>`_ 版本控制系统"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:42
+msgid "A C++ toolchain, needed for simulating with Verilator"
+msgstr "用 Verilator 进行仿真所需的 C++ 工具链"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:43
+msgid "A linux shell, needed for simulating with Verilator"
+msgstr "一个 linux shell，需要使用 Verilator 进行仿真"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:46
+msgid "Linux Installation"
+msgstr "Linux安装"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:48
+msgid ""
+"At time of writing the recommended way of installing Scala and SBT is via"
+" `Coursier <https://get-coursier.io/docs/cli-installation>`_. Coursier is"
+" able to in addition to the scala tools install a Java JDK to use, in the"
+" example below we install Java from the package manager. We recommend to "
+"install JDK 17 (LTS) because of compatibility with the used Scala "
+"version."
+msgstr ""
+"在撰写本文时，推荐的 Scala 和 SBT 安装方法是通过 `Coursier <https://get-coursier.io/docs"
+"/cli-installation>`_。除了 scala 工具之外，Coursier 还能够安装 Java JDK "
+"，在下面的示例中，我们通过包管理器安装 Java。出于 Scala 版本兼容的考量，我们建议安装 JDK 17 (LTS)。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:53
+msgid "For Debian or Ubuntu we run:"
+msgstr "对于 Debian 或 Ubuntu，运行："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:65
+msgid ""
+"If you want to install the tools for simulation and/or formal proofs, we "
+"recommend `oss-cad-suite <https://github.com/YosysHQ/oss-cad-suite-"
+"build>`_. It contains a waveform viewer (gtkWave), verilog simulators "
+"(verilator and iverilog), VHDL simulator (GHDL) and other tools. In case "
+"you want to build the tools yourself have a look at the legacy simulation"
+" tool :ref:`installation instructions <sim backend install>`."
+msgstr ""
+"如果您想安装用于仿真和/或形式化证明的工具，我们推荐 `oss-cad-suite <https://github.com/YosysHQ"
+"/oss-cad-suite-"
+"build>`_。它包含波形查看器（gtkWave）、verilog仿真器（verilator和iverilog）、VHDL仿真器（GHDL）以及一些其他工具。如果您想自己构建工具，请查看旧版仿真工具"
+" :ref:`安装说明 <sim backend install>`。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:69
+msgid ""
+"We first install the needed C++ toolchain and download oss-cad-suite. To "
+"use it we must load the oss-cad-suite environment for each shell we want "
+"to use it in. Note that oss-cad-suite contains a Python 3 interpreter "
+"that may interfere with the system Python installation if loaded "
+"permanently."
+msgstr ""
+"首先，我们安装所需的C++工具链并下载oss-cad-suite。要使用它，我们必须为每个我们想要使用它的shell加载oss-cad-"
+"suite环境。请注意，oss-cad-suite包含一个可能会干扰系统Python安装的Python 3解释器，如果永久加载（loaded "
+"permanently）它。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:73
+msgid ""
+"Go to the oss-cad-suite `release page <https://github.com/YosysHQ/oss-"
+"cad-suite-build/releases/latest>`_ to get the download link for the "
+"latest version. You can download/extract oss-cad-suite to a folder of "
+"your choice. (last tested version of oss-cad-suite is `2023-10-22`, but "
+"more recent ones will most likely also work)"
+msgstr ""
+"前往 oss-cad-suite `发布页面 <https://github.com/YosysHQ/oss-cad-suite-"
+"build/releases/latest>`_ 获取最新版本的下载链接。您可以将 oss-cad-suite 下载/解压到您选择的文件夹中。 "
+"（oss-cad-suite 的最后测试版本是 `2023-10-22`，但最新的版本可能也可以工作）"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:83
+msgid ""
+"To use oss-cad-suite in a shell you need to load it's environment, e.g. "
+"via ``souce <path to oss-cad-suite>/environment``."
+msgstr ""
+"要在 shell 中使用 oss-cad-suite，您需要加载它的环境，例如通过 ``souce <path to oss-cad-"
+"suite>/environment`` 实现。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:87
+msgid "Mac OS X Installation"
+msgstr "Mac OS X 安装"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:88
+msgid ""
+"You can use homebrew to install on Mac OS X.  By default homebrew "
+"installs Java 21, but the  SpinalHDL tutorial SpinalTemplateSbt uses "
+"Scala version 2.12.16, which is not supported by Java 21 (17 is still the"
+" recommended LTS version, https://whichjdk.com/). So to install Java "
+"version 1.7 do:"
+msgstr ""
+"Mac OS X 上可以使用 homebrew 安装。默认情况下 homebrew 安装 Java 21，但 SpinalHDL 教程 "
+"SpinalTemplateSbt 使用 Scala 版本 2.12.16，Java 21 不支持该版本（17 仍然是推荐的 LTS "
+"版本，https://whichjdk.com/）。因此，要安装 Java 1.7 版本，请执行以下操作："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:96
+msgid "And then add this to your path."
+msgstr "然后，将其添加到您的路径（path）中。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:102
+msgid ""
+"To manage multiple versions of Java it is also essential to have jenv "
+"installed."
+msgstr "要管理 Java 的多个版本，还必须安装 jenv。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:108
+msgid "Jenv added these lines to my .bash_profile"
+msgstr "Jenv 将这些行添加到 .bash_profile 中"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:115
+msgid "Next you have to install scala's interactive build tool sbt."
+msgstr "接下来你必须安装scala的交互式构建工具sbt。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:121
+msgid ""
+"If this works for you, please let us know.  If this does not work for "
+"you, you can read the github issue about Mac o SX installation here. "
+"https://github.com/SpinalHDL/SpinalHDL/issues/1216"
+msgstr ""
+"如果这对您有用，请告诉我们。如果这对您不起作用，您可以在此处阅读有关 Mac o SX 安装的 github 问题。 "
+"https://github.com/SpinalHDL/SpinalHDL/issues/1216"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:124
+msgid ""
+"If you want to install the tools for simulation and/or formal proofs, we "
+"recommend `oss-cad-suite <https://github.com/YosysHQ/oss-cad-suite-"
+"build>`_."
+msgstr ""
+"如果您想安装用于仿真和/或形式化证明的工具，我们推荐 `oss-cad-suite <https://github.com/YosysHQ"
+"/oss-cad-suite-build>`_。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:127
+msgid "Windows installation"
+msgstr "Windows安装"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:130
+msgid ""
+"While a native installation is possible the simpler and currently "
+"recommended way is to use WSL on Windows. If you want to use WSL, install"
+" `it <https://learn.microsoft.com/en-us/windows/wsl/install>`_, a "
+"distribution of your choice and follow the Linux installation "
+"instructions. Data in your WSL instance can be accessed from windows "
+"under ``\\\\wsl$``. In case you want to use IntelliJ you'll have to "
+"download the Linux version to WSL, if you want to use VSCode then the "
+"Windows version can be used to remotely edit in WSL."
+msgstr ""
+"虽然可以进行本机安装，但更简单且目前推荐的方法是在 Windows 上使用 WSL。如果您想使用 WSL，请安装您选择的 `发行版 "
+"<https://learn.microsoft.com/en-us/windows/wsl/install>`_，并按照 Linux "
+"安装说明进行操作。WSL 实例中的数据可以从Windows访问，在 ``\\\\wsl$`` 路径下。如果您想使用 IntelliJ，则必须将 "
+"Linux 版本下载到 WSL，如果您想使用 VSCode，则可以使用 Windows 版本远程编辑WSL中的数据。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:136
+msgid ""
+"At time of writing the recommended way of installing Scala and SBT is via"
+" `Coursier <https://get-coursier.io/docs/cli-installation>`_. Coursier is"
+" able to in addition to the scala tools install a Java JDK to use, in the"
+" example below we install Java manually. We recommend to install JDK 17 "
+"(LTS) because of compatibility with Scala."
+msgstr ""
+"在撰写本文时，推荐的安装 Scala 和 SBT 方法是通过 `Coursier <https://get-coursier.io/docs"
+"/cli-installation>`_。除了 scala 工具之外，Coursier 还能够安装 Java JDK "
+"来使用，在下面的示例中我们手动安装 Java。由于 Scala 兼容性原因，我们建议安装 JDK 17 (LTS)。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:141
+msgid ""
+"First download and install `Adoptium JDK 17 "
+"<https://adoptium.net/temurin/releases/?os=windows&version=17>`_. "
+"Download, unzip and run the `Coursier installer "
+"<https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-"
+"win32.zip>`_, when asked agree to an update of your ``PATH`` variable. "
+"Reboot to force an update of ``PATH``."
+msgstr ""
+"首先，下载并安装 `Adoptium JDK 17 "
+"<https://adoptium.net/temurin/releases/?os=windows&version=17>`_。下载、解压并运行"
+" `Coursier 安装程序 "
+"<https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-"
+"win32.zip>`_，当询问是否更新您的 ``PATH`` 变量时，选择同意。重新启动以强制更新 ``PATH``。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:145
+msgid ""
+"This is sufficient for generating hardware. For simulation continue with "
+"either choice below. In case you want to build the tools yourself have a "
+"look at the legacy simulation tool :ref:`installation instructions <sim "
+"backend install>`."
+msgstr ""
+"这足以生成硬件。对于仿真，请继续选择以下任一选项。如果您想自己构建仿真工具，请查看旧版仿真工具 :ref:`安装说明 <sim backend "
+"install>`。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:149
+msgid ""
+"An All-in-One solution offered by SpinalHDL maintainer `Readon "
+"<https://github.com/Readon>` is available to install and run SpinalHDL "
+"with Verilator simulation and formal verification via SymbiYosys. "
+"Download `it <https://github.com/Readon/msys2-installer/releases>`_ and "
+"install the environment anywhere on your disk. Start the build "
+"environment by clicking on the MSYS2-MINGW64 icon in the Start menu and "
+"use the MSYS2 default console. An alternative is to use the Windows "
+"Terminal or a Tabby-like application and use the startup command "
+"``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``, "
+"where the ``%MSYS2_ROOT%`` is the location of the msys2 installation. It "
+"is worth noting that if you want to use it offline, you should carefully "
+"select the libraries that the project depends on, otherwise you will need"
+" to download the packages manually. See the README for the repos for more"
+" details."
+msgstr ""
+"SpinalHDL 维护者 `Readon <https://github.com/Readon>` 提供的一体化解决方案可用于安装和运行 "
+"SpinalHDL，并通过 Verilator 仿真、通过 SymbiYosys 进行形式化验证。下载 `安装程序 "
+"<https://github.com/Readon/msys2-installer/releases>`_ "
+"并将该环境安装在磁盘上的任何位置。单击“开始”菜单中的 MSYS2-MINGW64 图标启动构建环境，并使用 MSYS2 "
+"默认控制台。另一种方法是使用“Windows Terminal”或类似 Tabby 的应用程序，并使用启动命令 "
+"``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``，其中 "
+"``%MSYS2_ROOT%`` 是 msys2 "
+"安装的位置。值得注意的是，如果要离线使用，要仔细选择项目所依赖的库，否则需要手动下载安装包。有关更多详细信息，请参阅对应仓库的自述文件。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:158
+msgid "MSYS2 verilator for simulation"
+msgstr "用于仿真的 MSYS2 verilator工具"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:160
+msgid ""
+"We recommend to install compiler/verilator through `MSYS2 "
+"<https://www.msys2.org>`. Other methods of installing gcc/make/shell "
+"(e.g. chocolatey, scoop, etc.) may also work but are untested."
+msgstr ""
+"我们建议通过 `MSYS2 <https://www.msys2.org>` 安装编译器/仿真器。其他安装 gcc/make/shell "
+"的方法（例如 Chocolatey、scoop 等）也可能有效，但未经测试。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:163
+msgid ""
+"SpinalHDL maintainer `Readon <https://github.com/Readon>` is maintaining "
+"a MSYS2 fork that default installs all needed officially available and "
+"custom built packages (also maintained by Readon `here "
+"<https://github.com/Readon/MINGW-SpinalHDL>`) for simulation and formal "
+"verification. It can be found `here "
+"<https://github.com/Readon/msys2-installer>`. If used then the packages "
+"installed below via ``pacman`` are already installed and those "
+"installation steps can be skipped."
+msgstr ""
+"SpinalHDL 维护者 `Readon <https://github.com/Readon>` 正在维护一个 MSYS2 "
+"分支，默认安装所有需要的官方可用和自定义构建的软件包（也由 Readon 在 `此处 <https://github.com/Readon/ "
+"MINGW-SpinalHDL>` 维护) 用于仿真和形式化验证。可以在 `此处 "
+"<https://github.com/Readon/msys2-installer>` 找到。如果使用该安装包，则已经安装了下面通过 "
+"pacman 安装的软件包，并且可以跳过这些安装步骤。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:169
+msgid "Currently verilator 4.228 is latest available version known to work."
+msgstr "目前 verilator 4.228 是已知可以工作的最新版本。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:171
+msgid ""
+"Download the latest installer and install MSYS2 with default settings. "
+"You should get a MSYS2 terminal at the end of the installation, there "
+"run:"
+msgstr "下载最新的安装程序并使用默认设置安装 MSYS2。安装结束后你应该会得到一个 MSYS2 终端，运行："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:184
+msgid ""
+"In a MSYS2 MINGW64 terminal we need to set some environment variables to "
+"make Java/sbt available (you can make these settings persistent by adding"
+" them to ``~/.bashrc`` in MSYS2):"
+msgstr ""
+"在 MSYS2 MINGW64 终端中，我们需要设置一些环境变量以使 Java/sbt 可用（您可以通过将它们添加到 MSYS2 中的 "
+"``~/.bashrc`` 来长期保存这些设置）："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:193
+msgid ""
+"With this you should be able to run sbt/verilator simulations from MSYS2 "
+"terminals (sbt via calling ``sbt.bat``)."
+msgstr "有了这个，您应该能够从 MSYS2 终端运行 sbt/verilator 仿真（通过调用 ``sbt.bat`` 使用）。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:196
+msgid "MSYS2 for formal verification"
+msgstr "用 MSYS2 实施形式化验证"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:198
+msgid ""
+"In addition to the steps above we also need to install yosys, sby, z3 and"
+" yices. Both yosys(yosys-smtbmc workable) and sby are not available as "
+"official MSYS2 packages, but packages are provided by `Readon "
+"<https://github.com/Readon>`. If you used their installer then these "
+"steps are not needed (you should check if there are newer packages "
+"available)."
+msgstr ""
+"除了上面的步骤之外，我们还需要安装yosys、sby、z3和yices。 yosys(可用的yosys-smtbmc) 和 sby 并不使用 "
+"MSYS2 官方提供的包（无法使用），而是由 `Readon <https://github.com/Readon>` "
+"提供。如果您使用他们的安装程序，则不需要后面这些步骤（您应该检查是否有更新的软件包可用）。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:212
+msgid "OCI Container"
+msgstr "OCI容器"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:214
+msgid ""
+"A container for SpinalHDL development is available as well. The container"
+" is hosted at ``ghcr.io/spinalhdl/docker:master`` and can be used with "
+"Docker/Podman/Github Codespaces. It is used for the SpinalHDL CI "
+"regression and can therefore be an easy way to run the CI commands "
+"locally."
+msgstr ""
+"也可以使用 SpinalHDL 开发容器。该容器托管在 ``ghcr.io/spinalhdl/docker:master`` ，可以与 "
+"Docker/Podman/Github Codespaces 一起使用。它用于 SpinalHDL CI "
+"测试，因此，也可以成为本地运行的简单方法。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:218
+msgid ""
+"To run the container run e.g. ``podman run -v .:/workspace -it "
+"ghcr.io/spinalhdl/docker:master`` in a SpinalHDL project root directory, "
+"making the project directory available in ``/workspace``."
+msgstr ""
+"要使用容器，请运行例如SpinalHDL 项目根目录中的 ``podman run -v .:/workspace -it "
+"ghcr.io/spinalhdl/docker:master`` ，使项目目录在 ``/workspace`` 中可用。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:221
+msgid ""
+"Please consult the documentation of you Distribution (Linux, WSL) or "
+"Docker (Windows) on how to install the container runtime you want to use."
+" Multiple editors/IDEs (e.g. VSCode, IntelliJ, Neovide) allow for remote "
+"development in a container. Please consult the documentation of the "
+"editor on how to do remote development."
+msgstr ""
+"请查阅您的发行版（Linux、WSL）或 Docker (Windows) "
+"的文档，了解如何安装您想要使用容器的运行时依赖。多个编辑器/IDE（例如 "
+"VSCode、IntelliJ、Neovide）允许对容器进行远程开发。如何进行远程开发请查阅相应编辑器的文档。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:226
+msgid "Installing SBT in an internet-free Linux environment"
+msgstr "在无网络的 Linux 环境中安装 SBT"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:229
+msgid ""
+"If you are not using an air-gapped environment we recommend to go with "
+"the normal linux installation. (which is a subset of the installation for"
+" an air-gapped environment)"
+msgstr "如果您不使用无网环境，我们建议您使用正常的 Linux 安装。 （这里是无网环境安装的方法）"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:233
+msgid ""
+"Normally, SBT uses online repositories to download and cache your "
+"projects dependencies. This cache is located in several folders:"
+msgstr "通常，SBT 使用在线仓库来下载和缓存项目的依赖项。该缓存位于几个文件夹中："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:236
+msgid "``~/.sbt``"
+msgstr "``~/.sbt``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:237
+msgid "``~/.cache/JNA``"
+msgstr "``~/.cache/JNA``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:238
+msgid "``~/.cache/coursier``"
+msgstr "``~/.cache/coursier``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:240
+msgid "To set up an internet-free environment, you can:"
+msgstr "要设置无互联网环境，您可以："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:242
+msgid "Set up an environment with internet (see above)"
+msgstr "在有互联网的场景下配置环境（见上文）"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:243
+msgid ""
+"Launch a Spinal command (see :ref:`Using SBT`) to fetch dependencies (for"
+" instance using the `getting started "
+"<https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository)"
+msgstr ""
+"启动 Spinal 命令（请参阅 :ref:`Using SBT`）来获取依赖项（例如使用 `入门 "
+"<https://github.com/SpinalHDL/SpinalTemplateSbt>`_ 仓库）"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:246
+msgid "Copy the caches to the internet-free environment."
+msgstr "将缓存复制到无互联网环境。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:251
+msgid "Create a first SpinalHDL project"
+msgstr "创建第一个 SpinalHDL 项目"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:253
+msgid ""
+"We have prepared a ready-to-go project for you the: `getting started "
+"<https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository."
+msgstr "我们为您准备了一个现成的项目：`入门 <https://github.com/SpinalHDL/SpinalTemplateSbt>`_ 仓库。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:255
+msgid ""
+"You can `download "
+"<https://codeload.github.com/SpinalHDL/SpinalTemplateSbt/zip/master>`_ "
+"it, or clone it."
+msgstr ""
+"您可以 `下载 "
+"<https://codeload.github.com/SpinalHDL/SpinalTemplateSbt/zip/master>`_ "
+"它，或克隆它。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:257
+msgid ""
+"The following commands clone the project into a new directory named "
+"``MySpinalProject`` and initialize a fresh ``git`` history:"
+msgstr "以下命令将项目克隆到名为 ``MySpinalProject`` 的新目录中，并初始化新的 ``git`` 历史记录："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:271
+msgid "The directory structure of a project"
+msgstr "项目的目录结构"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:275
+msgid ""
+"The structure described here is the default structure, but it can be "
+"easily modified."
+msgstr "这里描述的结构是默认结构，但可以轻松修改。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:278
+msgid "In the root of the project are the following files:"
+msgstr "项目的根目录中有以下文件："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:281
+msgid "File"
+msgstr "文件"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:281
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:283
+msgid "``build.sbt``"
+msgstr "``build.sbt``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:283
+msgid "Scala configuration for ``sbt``"
+msgstr "``sbt`` 的 Scala 配置"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:284
+msgid "``build.sc``"
+msgstr "``build.sc``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:284
+msgid "Scala configuration for ``mill``, an alternative to ``sbt``"
+msgstr "``mill`` 是一个 ``sbt`` 的替代品，它的配置方法是"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:285
+msgid "``hw/``"
+msgstr "``hw/``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:285
+msgid "The folder containing hardware descriptions"
+msgstr "包含硬件描述的文件夹"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:286
+msgid "``project/``"
+msgstr "``project/``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:286
+msgid "More Scala configuration"
+msgstr "更多 Scala 配置"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:287
+msgid "``README.md``"
+msgstr "``README.md``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:287
+msgid "A ``text/markdown`` file describing your project"
+msgstr "描述您的项目的 ``text/markdown`` 文件"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:288
+msgid "``.gitignore``"
+msgstr "``.gitignore``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:288
+msgid "List of files to ignore in versioning"
+msgstr "版本控制中要忽略的文件列表"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:289
+msgid "``.mill-version``"
+msgstr "``.mill-version``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:289
+msgid "More configuration for ``mill``"
+msgstr "``mill`` 的更多配置"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:290
+msgid "``.scalafmt.conf``"
+msgstr "``.scalafmt.conf``"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:290
+msgid "Configuration of rules to auto-format the code"
+msgstr "配置自动格式化代码的规则"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:293
+msgid ""
+"As you probably guessed it, the interesting thing here is ``hw/``. It "
+"contains four folders: ``spinal/``, ``verilog/`` and ``vhdl/`` for your "
+"IPs and ``gen/`` for IPs generated with Spinal."
+msgstr ""
+"正如您可能猜到的，这里有趣的是 ``hw/``。它包含四个文件夹： ``spinal/``、 ``verilog/`` 和 ``vhdl/`` "
+"保存您的 IP， ``gen/`` 保存 Spinal 生成的 IP。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:297
+msgid ""
+"``hw/spinal/`` contains a folder named after your project name. This name"
+" must be set in ``build.sbt`` (along with the company name) and in "
+"``build.sc``; and it must be the one in ``package yourprojectname`` at "
+"the beginning of ``.scala`` files."
+msgstr ""
+"``hw/spinal/`` 包含一个以您的项目名称命名的文件夹。该名称以及公司名称必须在 ``build.sbt`` 和 "
+"``build.sc`` 中设置；并且这个名称必须在 ``.scala`` 文件开头以 ``package yourprojectname`` "
+"的形式给出。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:302
+msgid ""
+"In ``hw/spinal/yourprojectname/``, are the descriptions of your IPs, "
+"simulation tests, formal tests; and there is ``Config.scala``, which "
+"contains the configuration of ``Spinal``."
+msgstr ""
+"在 ``hw/spinal/yourprojectname/`` 中，是你的IP描述，仿真测试，形式化验证测试；还有 "
+"``Config.scala``，其中包含 ``Spinal``的配置。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:308
+msgid ""
+"``sbt`` must be used **only** at the root of the project, in the folder "
+"containing ``build.sbt``."
+msgstr "``sbt`` 必须且**仅**在项目的根目录中使用，该目录包含 ``build.sbt`` 文件。"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:313
+msgid "Using Spinal on SpinalHDL code"
+msgstr "在 SpinalHDL 代码中使用 Spinal"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:315
+msgid ""
+"Now the tutorial shows how to use Spinal on SpinalHDL code depending on "
+"your development environment:"
+msgstr "现在，教程展示了如何根据您的开发环境在 SpinalHDL 代码中使用 Spinal："
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:318
+msgid ":ref:`Using SBT`"
+msgstr ":ref:`Using SBT`"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:319
+msgid ":ref:`Using VSCodium`"
+msgstr ":ref:`Using VSCodium`"
+
+#: ../../SpinalHDL/Getting Started/Install and setup.rst:320
+msgid ":ref:`Using IntelliJ`"
+msgstr ":ref:`Using IntelliJ`"
+
+#~ msgid "Mandatory requirements"
+#~ msgstr "强制性要求"
+
+#~ msgid "For instance, to install them on the Debian distribution:"
+#~ msgstr "例如，要将它们安装在 Debian 发行版上："
+
+#~ msgid ""
+#~ "If you do not need this, you "
+#~ "can skip to the next section: "
+#~ ":ref:`recommended`."
+#~ msgstr "如果您不需要这个，您可以跳到下一部分：:ref:`推荐`。"
+
+#~ msgid ""
+#~ "You can get a portable SBT setup"
+#~ " here: https://www.scala-sbt.org/download.html"
+#~ msgstr "您可以在此处获取便携式 SBT 设置：https://www.scala-sbt.org/download.html"
+
+#~ msgid ""
+#~ "You might be interested in `SpinalNomad"
+#~ " <https://github.com/SpinalHDL/SpinalNomad/tree/main/sbt>`_."
+#~ msgstr ""
+#~ "您可能对“SpinalNomad "
+#~ "<https://github.com/SpinalHDL/SpinalNomad/tree/main/sbt>”感兴趣。"
+
+#~ msgid "Recommended requirements"
+#~ msgstr "推荐要求"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/IntelliJ.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/IntelliJ.po
new file mode 100644
index 00000000000..4e57ca885a5
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/IntelliJ.po	
@@ -0,0 +1,72 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedintellij/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:4
+msgid "Using Spinal from IntelliJ IDEA"
+msgstr "从 IntelliJ IDEA 使用 Spinal"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:6
+msgid ""
+"In addition to the aforementioned requirements, you also need to download "
+"the IntelliJ IDEA (the free *Community edition* is enough). When you have "
+"installed IntelliJ, also check that you have enabled its Scala plugin (\\ "
+"`install information <https://www.jetbrains.com/help/idea/2016.1/enabling-"
+"and-disabling-plugins.html?origin=old_help>`_ can be found here)."
+msgstr ""
+"除了上述要求，你还需要下载IntelliJ IDEA（免费的*社区版*即可）。安装 IntelliJ "
+"后，还需检查是否启用了 Scala 插件（可在此处查看 `安装信息 <https://www."
+"jetbrains.com/help/idea/2016.1/enabling-and-disabling-plugins."
+"html?origin=old_help>`_ ）。"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:8
+msgid "And do the following:"
+msgstr "并进行以下操作："
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:10
+msgid ""
+"In *Intellij IDEA*\\ , \"import project\" with the root of this repository, "
+"the choose the *Import project from external model SBT* and be sure to check"
+" all boxes."
+msgstr "在 *Intellij IDEA* 中，在该仓库的根目录下 \"导入项目\"，选择 "
+"*从外部模型导入SBT工程* 并确保勾选所有复选框。"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:11
+msgid ""
+"In addition, you might need to specify some path like where you installed "
+"the JDK to *IntelliJ*."
+msgstr "此外，您可能需要在 *IntelliJ* 中指定一些路径，例如 JDK 的安装位置。"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:12
+msgid ""
+"In the project (Intellij project GUI), right click on "
+"``src/main/scala/mylib/MyTopLevel.scala`` and select \"Run MyTopLevel\"."
+msgstr ""
+"在项目（Intellij 项目 GUI）中，右键单击 ``src/main/scala/mylib/MyTopLevel."
+"scala`` 并选择“Run MyTopLevel”。"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:14
+msgid ""
+"This should generate the output file ``MyTopLevel.vhd`` in the project "
+"directory, which implements a simple 8-bit counter."
+msgstr "这将在项目目录中生成输出文件 ``MyTopLevel.vhd``，该文件实现了一个简单的 8 "
+"位计数器。"
+
+#: ../../source/SpinalHDL/Getting Started/IntelliJ.rst:16
+msgid ""
+"Now you can use your environment, let's explore the code: :ref:`Simple "
+"example`."
+msgstr "现在您可以使用您的环境了，让我们探索一下代码： :ref:`Simple example`。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/SBT.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/SBT.po
new file mode 100644
index 00000000000..dc25ad6a895
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/SBT.po	
@@ -0,0 +1,127 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedsbt/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:4
+msgid "Using Spinal from CLI with SBT"
+msgstr "在 CLI （命令行）中结合 SBT 使用 Spinal"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:6
+msgid ""
+"First, open a terminal in the root of the template you have downloaded "
+"earlier in :ref:`template`."
+msgstr "首先，在 template （提前下载）的根目录中打开一个终端。"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:9
+msgid "Commands can be executed right from the terminal:"
+msgstr "可以直接从终端执行命令："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:15
+msgid ""
+"But ``sbt`` has a quite long boot time so the we recommend to use its "
+"interactive mode:"
+msgstr "但是 ``sbt`` 有一个相当长的启动时间，所以我们建议使用它的交互模式："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:22
+msgid ""
+"Now ``sbt`` shows a prompt. Let's start by doing Scala compilation. It will "
+"fetch dependencies so it can take time the first time:"
+msgstr "现在 ``sbt`` 会显示提示。让我们从 Scala "
+"编译开始。它将获取依赖项，因此第一次运行可能需要一些时间："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:29
+msgid ""
+"Actually you never need to just ``compile`` as it is done automatically when"
+" needed. The first build time will take a few moments longer compared to "
+"future builds as the sbt tool builds the entire project from a cold start "
+"and then uses incremental building where possible from that point on.  "
+"``sbt`` supports autocompletion inside the interactive shell to assist "
+"discovery and usage of the available commands. You can start the interactive"
+" shell with ``sbt shell`` or running ``sbt`` with no arguments from the "
+"command line."
+msgstr ""
+"实际上，您永远不会仅使用 ``compile`` 命令，因为它会在需要时自动完成。与后续的"
+"构建相比，第一次构建时间将花费较长时间，因为 sbt "
+"工具需要从冷启动构建整个项目，后续构建则尽可能使用增量构建。 ``sbt`` "
+"支持交互式 shell 内的自动补全，以帮助发现和使用可用命令。您可以使用 ``sbt "
+"shell`` 或者 ``sbt`` （不带参数）命令启动交互式 shell。"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:37
+msgid ""
+"To run a specific HDL code-generation or simulation, the command is "
+"``runMain``. So if you type ``runMain``, space, and tab, you should get "
+"this:"
+msgstr ""
+"要运行特定的 HDL 代码生成或仿真，命令是 ``runMain``。因此，如果您输入 "
+"``runMain``、空格和tab，您应该得到以下结果："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:47
+msgid ""
+"The autocompletion suggests all things that can be run. Let's run the "
+"Verilog generation for instance:"
+msgstr "自动补全功能会建议所有可以运行的内容。这是一个生成 Verilog 代码的例子："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:54
+msgid "Look at the directory ./hw/gen/: there is a new ``MyTopLevel.v`` file!"
+msgstr "查看目录./hw/gen/：有一个新的 ``MyTopLevel.v`` 文件！"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:56
+msgid "Now add a ``~`` at the beginning of the command:"
+msgstr "现在在命令的开头添加一个 ``~`` ："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:62
+msgid "It prints this:"
+msgstr "它打印出这个："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:83
+msgid ""
+"So now, each time you save a source file, it will re-generate "
+"``MyTopLevel.v``. To do this, it automatically compiles the source files and"
+" it performs lint checks. This way you can get errors printed on the "
+"terminal almost in real-time while you are editing the source files."
+msgstr ""
+"所以现在，每次保存源文件时，它都会重新生成 ``MyTopLevel.v``。为此，"
+"它会自动编译源文件并执行 lint "
+"检查。这样，当您编辑源文件时，您几乎可以实时在终端上打印错误。"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:88
+msgid ""
+"You can press Enter to stop automatic generation, then Ctrl-D to exit "
+"``sbt``."
+msgstr "您可以按 Enter 停止自动生成，然后按 Ctrl-D 退出 ``sbt``。"
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:90
+msgid ""
+"It is also possible to start it right from the terminal, without using "
+"``sbt``'s interactive prompt:"
+msgstr "也可以直接从终端启动它，而不使用 ``sbt`` 的交互式提示："
+
+#: ../../SpinalHDL/Getting Started/SBT.rst:97
+msgid ""
+"Now you can use your environment, let's explore the code: :ref:`Simple "
+"example`."
+msgstr "现在您可以使用您的环境了，让我们探索一下代码： :ref:`Simple example`。"
+
+#~ msgid ""
+#~ "Actually you never need to just ``compile`` as it is done automatically when"
+#~ " needed. This time was just to evacuate the long first build, and to get all"
+#~ " ``sbt`` autocompletion features on the next commands."
+#~ msgstr ""
+#~ "实际上，您永远不需要仅仅“编译”，因为它会在需要时自动完成。这次只是为了撤离漫长的第一次构建，并在下一个命令中获得所有“sbt”自动完成功能。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po
new file mode 100644
index 00000000000..62e834b8ebe
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po	
@@ -0,0 +1,331 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedscala-guidebasics/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:3 Started/Scala
+msgid ""
+"Variables and functions should be defined into ``object``\\ , ``class``\\ , "
+"``function``. You can't define them on the root of a Scala file."
+msgstr ""
+"变量和函数应该定义为``object``\\，``class``\\，``function``。"
+"您不能在根目录下的 Scala 文件中定义它们。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:6 Started/Scala
+msgid "Basics"
+msgstr "基础内容"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:9 Started/Scala
+msgid "Types"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:11 Started/Scala
+msgid "In Scala, there are 5 major types:"
+msgstr "在Scala中，主要有5种类型："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:17 Started/Scala
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:18 Started/Scala
+msgid "Literal"
+msgstr "形式"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:19 Started/Scala
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:20 Started/Scala
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:21 Started/Scala
+msgid "true, false"
+msgstr "true, false"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:23 Started/Scala
+msgid "Int"
+msgstr "Int"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:24 Started/Scala
+msgid "3, 0x32"
+msgstr "3, 0x32"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:25 Started/Scala
+msgid "32 bits integer"
+msgstr "32 位整数"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:26 Started/Scala
+msgid "Float"
+msgstr "Float"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:27 Started/Scala
+msgid "3.14f"
+msgstr "3.14f"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:28 Started/Scala
+msgid "32 bits floating point"
+msgstr "32 位浮点数"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:29 Started/Scala
+msgid "Double"
+msgstr "Double"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:30 Started/Scala
+msgid "3.14"
+msgstr "3.14"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:31 Started/Scala
+msgid "64 bits floating point"
+msgstr "64位浮点"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:32 Started/Scala
+msgid "String"
+msgstr "String"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:33 Started/Scala
+msgid "\"Hello world\""
+msgstr "\"Hello world\""
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:34 Started/Scala
+msgid "UTF-16 string"
+msgstr "UTF-16 字符串"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:38 Started/Scala
+msgid "Variables"
+msgstr "变量"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:40 Started/Scala
+msgid "In Scala, you can define a variable by using the ``var`` keyword:"
+msgstr "在 Scala 中，您可以使用 var 关键字定义变量："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:49 Started/Scala
+msgid ""
+"Scala is able to infer the type automatically. You don't need to specify it "
+"if the variable is assigned at declaration:"
+msgstr "Scala 能够自动推断类型。如果变量是在声明时赋值的，则不需要指定类型："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:55 Started/Scala
+msgid ""
+"However, it's not very common to use ``var`` in Scala. Instead, constant "
+"values defined by ``val`` are often used:"
+msgstr "然而，在 Scala 中使用 var 并不常见。相反，经常使用由 ``val`` 定义的常量值："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:64 Started/Scala
+msgid "Functions"
+msgstr "函数"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:66 Started/Scala
+msgid ""
+"For example, if you want to define a function which returns ``true`` if the "
+"sum of its two arguments is bigger than zero, you can do as follows:"
+msgstr "例如，如果你想定义一个函数，当两个参数之和大于零时返回 ``true`` "
+"，你可以这样做："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:74 Started/Scala
+msgid "Then, to call this function, you can write:"
+msgstr "然后，要调用该函数，您可以编写："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:80 Started/Scala
+msgid ""
+"You can also specify arguments by name, which is useful if you have many "
+"arguments:"
+msgstr "您还可以按名称指定参数，如果您有很多参数，这会很有用："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:90 Started/Scala
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:92 Started/Scala
+msgid ""
+"The ``return`` keyword is not necessary. In absence of it, Scala takes the "
+"last statement of your function as the returned value."
+msgstr "``return`` 关键字不是必需的。如果没有它，Scala "
+"会将函数的最后一条语句作为返回值。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:101 Started/Scala
+msgid "Return type inferation"
+msgstr "返回类型推断"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:103 Started/Scala
+msgid ""
+"Scala is able to automatically infer the return type. You don't need to "
+"specify it:"
+msgstr "Scala 能够自动推断返回类型。您不需要指定它："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:112 Started/Scala
+msgid "Curly braces"
+msgstr "大括号"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:114 Started/Scala
+msgid ""
+"Scala functions don't require curly braces if your function contains only "
+"one statement:"
+msgstr "如果您的函数仅包含一条语句，则 Scala 函数不需要大括号："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:121 Started/Scala
+msgid "Function that returns nothing"
+msgstr "不返回任何内容的函数"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:123 Started/Scala
+msgid ""
+"If you want a function to return nothing, the return type should be set to "
+"``Unit``. It's equivalent to the C/C++ ``void`` type."
+msgstr "如果您希望函数不返回任何内容，则返回类型应设置为 ``Unit``。它相当于 C/C++ "
+"``void`` 类型。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:133 Started/Scala
+msgid "Argument default values"
+msgstr "参数默认值"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:135 Started/Scala
+msgid "You can specify a default value for each argument of a function:"
+msgstr "您可以为函数的每个参数指定默认值："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:144 Started/Scala
+msgid "Apply"
+msgstr "Apply函数"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:146 Started/Scala
+msgid ""
+"Functions named ``apply`` are special because you can call them without "
+"having to type their name:"
+msgstr "名为 ``apply`` 的函数很特殊，因为您无需输入名称即可调用它们："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:157 Started/Scala
+msgid "This concept is also applicable for Scala ``object`` (static)"
+msgstr "这个概念也适用于 Scala ``object``（静态）"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:168 Started/Scala
+msgid "Object"
+msgstr "对象（Object）"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:170 Started/Scala
+msgid ""
+"In Scala, there is no ``static`` keyword. In place of that, there is "
+"``object``. Everything defined inside an ``object`` definition is static."
+msgstr ""
+"在 Scala 中，没有 ``static`` 关键字。取而代之的是 ``object``。在 ``object`` "
+"定义中所有内容都是静态的。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:172 Started/Scala
+msgid ""
+"The following example defines a static function named ``pow2`` which takes a"
+" floating point value as parameter and returns a floating point value as "
+"well."
+msgstr "以下示例定义了一个名为 ``pow2`` "
+"的静态函数，它接受浮点值作为参数并返回浮点值。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:180 Started/Scala
+msgid "Then you can call it by writing:"
+msgstr "然后你可以这样来调用它："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:187 Started/Scala
+msgid "Entry point (main)"
+msgstr "入口点（main）"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:189 Started/Scala
+msgid ""
+"The entry point of a Scala program (the main function) should be defined "
+"inside an object as a function named ``main``."
+msgstr "Scala 程序的入口点（主函数）应在对象内部定义为名为 ``main`` 的函数。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:200 Started/Scala
+msgid "Class"
+msgstr "类"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:202 Started/Scala
+msgid ""
+"The class syntax is very similar to Java. Imagine that you want to define a "
+"``Color`` class which takes as construction parameters three Float values "
+"(r,g,b) :"
+msgstr "类的语法与Java非常相似。想象一下，您想要定义一个 ``Color`` 类，它将三个 "
+"Float 值 (r,g,b) 作为构造函数的参数："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:210 Started/Scala
+msgid ""
+"Then, to instantiate the class from the previous example and use its "
+"``getGrayLevel`` function:"
+msgstr "然后，实例化上一个示例中的类并使用其 ``getGrayLevel`` 函数："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:217 Started/Scala
+msgid ""
+"Be careful, if you want to access a construction parameter of the class from"
+" the outside, this construction parameter should be defined as a ``val``:"
+msgstr "注意，如果你想从外部访问类的构造参数，那么这个参数应该定义为 ``val``："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:227 Started/Scala
+msgid "Inheritance"
+msgstr "继承"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:229 Started/Scala
+msgid ""
+"As an example, suppose that you want to define two classes, ``Rectangle`` "
+"and ``Square``, which extend the class ``Shape``:"
+msgstr "举个例子，假设您要定义两个类，``Rectangle`` 和 ``Square``，它们扩展了 "
+"``Shape`` 类："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:246 Started/Scala
+msgid "Case class"
+msgstr "样例类"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:248 Started/Scala
+msgid "Case class is an alternative way of declaring classes."
+msgstr "样例类是声明类的另一种方式。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:256 Started/Scala
+msgid "Then there are some differences between ``case class`` and ``class`` :"
+msgstr "``case class`` 和 ``class`` 之间有下面区别："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:258 Started/Scala
+msgid "case classes don't need the ``new`` keyword to be instantiated."
+msgstr "样例类不需要 ``new`` 关键字来实例化。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:259 Started/Scala
+msgid ""
+"construction parameters are accessible from outside; you don't need to "
+"define them as ``val``."
+msgstr "构造参数可从外部获取；你不需要将它们定义为 ``val``。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:261 Started/Scala
+msgid ""
+"In SpinalHDL, this explains the reasoning behind the coding conventions: "
+"it's in general recommended to use ``case class`` instead of ``class`` in "
+"order to have less typing and more coherency."
+msgstr ""
+"在 SpinalHDL 中，这解释了编码约定背后的原因：通常建议使用``case class`` "
+"而不是 ``class``，以减少代码量并提高一致性。"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:264 Started/Scala
+msgid "Templates / Type parameterization"
+msgstr "模板/类型参数化"
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:266 Started/Scala
+msgid ""
+"Imagine you want to design a class which is a queue of a given datatype, in "
+"that case you need to provide a type parameter to the class:"
+msgstr "想象一下，您想要设计一个类，它是某数据类型的队列，在这种情况下，您需要向该类"
+"提供类型参数："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:275 Started/Scala
+msgid ""
+"If you want to restrict the ``T`` type to be a sub class of a given type "
+"(for example ``Shape``), you can use the ``<: Shape`` syntax :"
+msgstr "如果你想将 ``T`` 类型限制为给定类型的子类（例如 ``Shape``），你可以使用 ``<: "
+"Shape`` 语法："
+
+#: ../../source/SpinalHDL/Getting Guide/basics.rst:289 Started/Scala
+msgid "The same is possible for functions:"
+msgstr "对于函数来说也是如此："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/coding_conventions.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/coding_conventions.po
new file mode 100644
index 00000000000..5be73af1569
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/coding_conventions.po	
@@ -0,0 +1,192 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedscala-guidecoding_conventions/zh_Hans/>"
+"\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:3 Started/Scala
+msgid "Coding conventions"
+msgstr "编码规范"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:6 Started/Scala
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:8 Started/Scala
+msgid ""
+"The coding conventions used in SpinalHDL are the same as the ones documented"
+" in the `Scala Style Guide <https://docs.scala-lang.org/style/>`_."
+msgstr ""
+"SpinalHDL 中使用的编码规范与 `Scala 风格指南 <https://docs.scala-lang.org/"
+"style/>`_ 中的规定相同。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:10 Started/Scala
+msgid ""
+"Some additional practical details and cases are explained in next pages."
+msgstr "一些额外的细节和案例将在下几页中解释。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:13 Started/Scala
+msgid "class vs case class"
+msgstr "类与样例类"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:15 Started/Scala
+msgid ""
+"When you define a ``Bundle`` or a ``Component``, it is preferable to declare"
+" it as a case class."
+msgstr "当您定义一个 ``Bundle`` 或 ``Component`` 时，最好将其声明为案例类。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:17 Started/Scala
+msgid "The reasons are:"
+msgstr "原因是："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:19 Started/Scala
+msgid ""
+"It avoids the use of ``new`` keywords. Never having to use it is better than"
+" sometimes, under some conditions."
+msgstr "它避免使用 ``new`` 关键字。在某些情况下，永远不必使用它比有时使用它要好。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:20 Started/Scala
+msgid ""
+"A ``case class`` provides a ``clone`` function. This is useful in SpinalHDL "
+"when there is a need to clone a ``Bundle``, for example, when you define a "
+"new ``Reg`` or a new ``Stream`` of some kind."
+msgstr ""
+"``case class`` 提供了 ``clone`` 函数。当需要克隆 ``Bundle`` "
+"时，该函数非常有用。例如，当您定义新的 ``Reg`` 或某种新的 ``Stream`` 时。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:21 Started/Scala
+msgid "Construction parameters are directly visible from outside."
+msgstr "构造参数从外部直接可见。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:24 Started/Scala
+msgid "[case] class"
+msgstr "样例类/类"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:26 Started/Scala
+msgid "All classes names should start with a uppercase letter"
+msgstr "所有类名称都应以大写字母开头"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:43 Started/Scala
+msgid "companion object"
+msgstr "伴生对象"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:45 Started/Scala
+msgid ""
+"A `companion object <https://docs.scala-lang.org/overviews/scala-"
+"book/companion-objects.html>`_ should start with an uppercase letter."
+msgstr ""
+"`伴随对象 <https://docs.scala-lang.org/overviews/scala-book/companion-objects"
+".html>`_ 应该以大写字母开头。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:57 Started/Scala
+msgid ""
+"An exception to this rule is when the companion object is used as a function"
+" (only ``apply`` inside), and these ``apply`` functions don't generate "
+"hardware:"
+msgstr "此规则的一个例外是当伴生对象用作函数时（其中包含了 ``apply`` 函数），"
+"并且这些 ``apply`` 函数不生成硬件："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:66 Started/Scala
+msgid "function"
+msgstr "函数"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:68 Started/Scala
+msgid "A function should always start with a lowercase letter:"
+msgstr "函数应始终以小写字母开头："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:80 Started/Scala
+msgid "instances"
+msgstr "实例"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:82 Started/Scala
+msgid "Instances of classes should always start with a lowercase letter:"
+msgstr "类的实例应始终以小写字母开头："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:90 Started/Scala
+msgid "if / when"
+msgstr "if / when"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:92 Started/Scala
+msgid ""
+"Scala ``if`` and SpinalHDL ``when`` should normally be written in the "
+"following way:"
+msgstr "Scala中的 ``if`` 和 SpinalHDL中的 ``when`` 通常应按以下方式编写："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:112 Started/Scala
+msgid "Exceptions could be:"
+msgstr "例外情况可能是："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:114 Started/Scala
+msgid ""
+"It's fine to include a dot before the keyword like methods ``.elsewhen`` and"
+" ``.otherwise``."
+msgstr "可以在关键字前添加一个点，例如方法 ``.elsewhen`` 和 ``.otherwise`` 。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:115 Started/Scala
+msgid ""
+"It's fine to compress an ``if``\\ /\\ ``when`` statement onto a single line "
+"if it makes the code more readable."
+msgstr "如果可以提高代码可读性，可以将 ``if``\\ /\\ ``when`` 语句压缩到一行中。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:118 Started/Scala
+msgid "switch"
+msgstr "switch"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:120 Started/Scala
+msgid "SpinalHDL ``switch`` should normally be written in the following way:"
+msgstr "SpinalHDL中的 ``switch`` 通常应按以下方式编写："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:136 Started/Scala
+msgid ""
+"It's fine to compress an ``is``\\ /\\ ``default`` statement onto a single "
+"line if it makes the code more readable."
+msgstr "如果可以提高代码可读性，可以将 ``is``\\ /\\ ``default`` 语句压缩到一行中。"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:139 Started/Scala
+msgid "Parameters"
+msgstr "参数"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:141 Started/Scala
+msgid ""
+"Grouping parameters of a ``Component``/``Bundle`` inside a case class is "
+"generally welcome because:"
+msgstr "在样例类中对 ``Component``/``Bundle`` 的参数进行分组通常是受欢迎的，因为："
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:143 Started/Scala
+msgid "Easier to carry/manipulate to configure the design"
+msgstr "更容易使用/操作设计的配置"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:144 Started/Scala
+msgid "Better maintainability"
+msgstr "更好的可维护性"
+
+#: ../../SpinalHDL/Getting Guide/coding_conventions.rst:158 Started/Scala
+msgid ""
+"But this should not be applied in all cases. For example: in a FIFO, it "
+"doesn't make sense to group the ``dataType`` parameter with the ``depth`` "
+"parameter of the fifo because, in general, the ``dataType`` is something "
+"related to the design, while the ``depth`` is something related to the "
+"configuration of the design."
+msgstr ""
+"但这不应该适用于所有情况。例如：在 FIFO 中，将 ``dataType`` 参数与 fifo 的 "
+"``depth`` 参数分组是没有意义的。因为一般情况下， ``dataType`` 与设计相关，而 "
+"``depth`` 则与设计的配置有关。"
+
+#~ msgid "It's fine to omit the dot before ``otherwise``."
+#~ msgstr "省略“otherwise”之前的点就可以了。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/index.po
new file mode 100644
index 00000000000..7225e1da430
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/index.po	
@@ -0,0 +1,45 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedscala-guideindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Getting Guide/index.rst:3 Started/Scala
+msgid "Scala Guide"
+msgstr "Scala 使用指南"
+
+#: ../../source/SpinalHDL/Getting Guide/index.rst:14 Started/Scala
+msgid "Scala guide"
+msgstr "Scala 使用指南"
+
+#: ../../source/SpinalHDL/Getting Guide/index.rst:17 Started/Scala
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Getting Guide/index.rst:18 Started/Scala
+msgid ""
+"Scala is a very capable programming language that was influenced by a unique"
+" set of languages, but often, this set of languages doesn't cross the ones "
+"that most programmers use. That can hinder newcomers' understanding of the "
+"concepts and design choices behind Scala."
+msgstr ""
+"Scala 是一种非常强大的编程语言，它受到一组语言的影响。但通常，这组语言与大多"
+"数程序员使用的语言并不交叉。这可能会阻碍新手理解 Scala "
+"背后的概念和设计选择缘由。"
+
+#: ../../source/SpinalHDL/Getting Guide/index.rst:20 Started/Scala
+msgid ""
+"The following pages will present Scala, and try to provide enough "
+"information about it for newcomers to be comfortable with SpinalHDL."
+msgstr "接下来的几页将介绍 Scala，并尝试提供足够的信息，以便新手熟悉 SpinalHDL。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/interaction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/interaction.po
new file mode 100644
index 00000000000..9600e914d2a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/interaction.po	
@@ -0,0 +1,196 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedscala-guideinteraction/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:3 Started/Scala
+msgid "Interaction"
+msgstr "交互"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:6 Started/Scala
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:8 Started/Scala
+msgid ""
+"SpinalHDL is, in fact, not an language: it's a regular Scala library. This "
+"could seem strange at first glance, but it is a very powerful combination."
+msgstr "事实上，SpinalHDL 不是一种语言：它是一个常规的 Scala "
+"库。乍一看这似乎很奇怪，但这是一个非常强大的组合。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:10 Started/Scala
+msgid ""
+"You can use the whole Scala world to help you in the description of your "
+"hardware via the SpinalHDL library, but to do that properly, it's important "
+"to understand how SpinalHDL interacts with Scala."
+msgstr ""
+"您可以使用整个 Scala 世界的工具，通过 SpinalHDL "
+"库来帮助您描述硬件，但要正确地做到这一点，了解 SpinalHDL 如何与 Scala "
+"交互非常重要。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:13 Started/Scala
+msgid "How SpinalHDL works behind the API"
+msgstr "SpinalHDL 在 API 隐藏后的工作原理"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:15 Started/Scala
+msgid ""
+"When you execute your SpinalHDL hardware description, each time you use "
+"SpinalHDL functions, operators, or classes, it will build an in-memory graph"
+" that represents the netlist of your design."
+msgstr "当您执行 SpinalHDL 硬件描述时，每次使用 SpinalHDL "
+"函数、运算符或类时，它都会构建一个内存中图来表示您设计的网表。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:17 Started/Scala
+msgid ""
+"Then, when the elaboration is done (instantiation of your top-level "
+"``Component`` classes), SpinalHDL will do some passes on the graph that was "
+"constructed, and if everything is fine, it will flush that graph into a VHDL"
+" or Verilog file."
+msgstr ""
+"然后，当实例细化完成后（顶层 ``Component`` 类的实例化），SpinalHDL "
+"将对构建的图进行一些处理，如果一切正常，它将把该图生成为 VHDL 或 "
+"Verilog文件。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:20 Started/Scala
+msgid "Everything is a reference"
+msgstr "一切都是引用"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:22 Started/Scala
+msgid ""
+"For example, if you define a Scala function which takes a parameter of type "
+"``Bits``, when you call it, it will be passed as a reference. As consequence"
+" of that, if you assign that argument inside the function, it has the same "
+"effect on the underlying ``Bits`` object as if you had assigned to it "
+"outside the function."
+msgstr ""
+"例如，如果您定义一个 Scala 函数，它接受类型为 ``Bits`` 的参数，那么当您调用它"
+"时，它将作为引用传递。因此，如果您在函数内部赋值（通过“:=”）该参数，它对底层 "
+"``Bits`` 对象具有相同的效果，就像您在函数外部给它赋值一样。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:27 Started/Scala
+msgid "Hardware types"
+msgstr "硬件类型"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:29 Started/Scala
+msgid "Hardware data types in SpinalHDL are the combination of two things:"
+msgstr "SpinalHDL 中的硬件数据类型是两个概念的组合："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:32 Started/Scala
+msgid "An instance of a given Scala type"
+msgstr "给定 Scala 类型的实例"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:33 Started/Scala
+msgid "The configuration of that instance"
+msgstr "该实例的配置信息"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:35 Started/Scala
+msgid ""
+"For example ``Bits(8 bits)`` is the combination of the Scala type ``Bits`` "
+"and its ``8 bits`` configuration (as a construction parameter)."
+msgstr ""
+"例如，``Bits(8 bits)`` 是 Scala 类型 ``Bits`` 及其 ``8 bits`` "
+"这一配置信息（作为构造参数）的组合。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:38 Started/Scala
+msgid "RGB example"
+msgstr "RGB 示例"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:40 Started/Scala
+msgid "Let's take an Rgb bundle class as example:"
+msgstr "我们以 Rgb 线束类为例："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:50 Started/Scala
+msgid ""
+"The hardware data type here is the combination of the Scala ``Rgb`` class "
+"and its ``rWidth``, ``gWidth``, and ``bWidth`` parameterization."
+msgstr ""
+"这里的硬件数据类型是 Scala ``Rgb`` 类及其 ``rWidth``, ``gWidth``, 和 "
+"``bWidth`` 参数的组合。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:52 Started/Scala
+msgid "Here is an example of usage:"
+msgstr "这是一个用法示例："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:62 Started/Scala
+msgid ""
+"You can also use functions to define various kinds of type factories "
+"(typedef):"
+msgstr "您还可以使用函数来定义各种类型工厂（typedef）："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:73 Started/Scala
+msgid "Names of signals in the generated RTL"
+msgstr "生成的 RTL 中的信号名称"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:75 Started/Scala
+msgid ""
+"To name signals in the generated RTL, SpinalHDL uses Java reflections to "
+"walk through your entire component hierarchy, collecting all references "
+"stored inside the class attributes, and naming them with their attribute "
+"name."
+msgstr ""
+"为了命名生成的 RTL 中的信号，SpinalHDL 使用 Java 反射遍历整个组件层次结构，收"
+"集存储在类属性内的所有引用，并使用属性名称命名它们。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:77 Started/Scala
+msgid ""
+"This is why the names of every signal defined inside a function are lost:"
+msgstr "这就是函数内定义的每个信号的名称都会丢失的原因："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:88 Started/Scala
+msgid ""
+"One solution if you want preserve the names of the internal variables in the"
+" generated RTL, is to use ``Area``:"
+msgstr "如果您想在生成的 RTL 中保留内部变量的名称，一种解决方案是使用逻辑区（ "
+"``Area``）："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:100 Started/Scala
+msgid "Scala is for elaboration, SpinalHDL for hardware description"
+msgstr "Scala 用于实例细化，SpinalHDL 用于硬件描述"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:102 Started/Scala
+msgid ""
+"For example, if you write a Scala for loop to generate some hardware, it "
+"will generate the unrolled result in VHDL/Verilog."
+msgstr "例如，如果您编写 Scala for 循环来生成某些硬件，它将生成展开的 VHDL/Verilog "
+"代码。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:104 Started/Scala
+msgid ""
+"Also, if you want a constant, you should not use SpinalHDL hardware literals"
+" but the Scala ones. For example:"
+msgstr "另外，如果你想要一个常量，你不应该使用 SpinalHDL 硬件代码，而应该使用 Scala "
+"代码。例如："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:119 Started/Scala
+msgid "Scala elaboration capabilities (if, for, functional programming)"
+msgstr "Scala 实例细化能力（if、for、函数式编程）"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:121 Started/Scala
+msgid ""
+"All of Scala's syntax can be used to elaborate hardware designs, for "
+"instance, a Scala ``if`` statement could be used to enable or disable the "
+"generation of hardware:"
+msgstr "在Scala中，所有的语法都可以用来细化硬件设计。例如，Scala的 ``if`` "
+"语句可以用于启用或禁用部分硬件的生成。"
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:133 Started/Scala
+msgid "The same is true for Scala ``for`` loops:"
+msgstr "Scala 的 ``for`` 循环也是如此："
+
+#: ../../source/SpinalHDL/Getting Guide/interaction.rst:145 Started/Scala
+msgid ""
+"Also, functional programming techniques can be used with many SpinalHDL "
+"types:"
+msgstr "此外，函数式编程技术可用于许多 SpinalHDL 类型："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/VSCodium.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/VSCodium.po
new file mode 100644
index 00000000000..ffca96105a4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/VSCodium.po	
@@ -0,0 +1,113 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-31 10:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedvscodium/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:4
+msgid "Using Spinal from VSCodium"
+msgstr "在 VSCodium 中使用 Spinal"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:7
+msgid ""
+"`VSCodium <https://vscodium.com/>`_ is the open source build of Visual "
+"Studio Code, but without the telemetry included in Microsoft's downloadable "
+"version."
+msgstr ""
+"`VSCodium <https://vscodium.com/>`_ 是 Visual Studio Code 的开源版本，"
+"但不包含 Microsoft 可下载版本的数据报告功能。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:9
+msgid ""
+"As a one-time setup task, go to view->extensions search for \"Scala\" and "
+"install the \"Scala (Metals)\" `extension "
+"<https://marketplace.visualstudio.com/items?itemName=scalameta.metals>`_."
+msgstr ""
+"作为一次性安装任务，请转到“查看”->“扩展” "
+"菜单栏搜索“Scala”并安装“Scala（Metals）” `扩展 <https://marketplace."
+"visualstudio.com/items?itemName=scalameta.metals>`_。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:11
+msgid ""
+"Open the workspace: ``File`` > ``Open Folder...`` and open the folder you "
+"have downloaded earlier in :ref:`template`."
+msgstr "打开工作区：``File`` > ``Open Folder...`` 并打开您之前在 :ref:`template` "
+"中下载的文件夹。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:13
+msgid ""
+"The other way to start it, is to cd into the appropriate directory and type "
+"``codium .``"
+msgstr "另一种启动方法是 cd 进入适当的目录并输入 ``codium .``"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:15
+msgid ""
+"Wait a little bit, a notification pop-up should appear on the bottom-right "
+"corner: \"Multiple build definitions found. Which would you like to use?\". "
+"Click ``sbt``, then another pop-up appears, click ``Import build``."
+msgstr ""
+"稍等一下，右下角应该会出现一个弹出通知：“找到多个构建定义。您想使用哪个？”。"
+"单击 ``sbt`` ，然后出现另一个弹出窗口，单击 ``Import build``。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:19
+msgid ""
+"Wait while running ``sbt bloopInstall``. Then a warning pop-up appears, you "
+"can ignore it (don't show again)."
+msgstr "运行 ``sbt bloopInstall`` "
+"时稍等片刻。然后会出现一个警告弹出窗口，您可以忽略它（不再显示）。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:22
+msgid ""
+"Find and open ``hw/spinal/projectname/MyTopLevel.scala``.  Wait a little "
+"bit, and see the ``run | debug`` line that is displayed by Metals, before "
+"each ``App``. For instance, click on ``run`` just above ``object "
+"MyTopLevelVerilog``. Alternatively, you can select Menu Bar -> Run -> Run "
+"Without Debugging.  Either approach performs design checks and, as the "
+"checks pass, generates the Verilog file ``./hw/gen/MyTopLevel.v``"
+msgstr ""
+"找到并打开 ``hw/spinal/projectname/MyTopLevel.scala``。稍等一下，然后看到 "
+"Metals 在每个 ``App`` 之前显示的 ``run | debug`` 行。例如，单击 ``object "
+"MyTopLevelVerilog`` 上方的 ``run`` 。或者，您可以选择菜单栏 -> 运行 -> "
+"运行而不调试。两种方法都会执行设计检查，并在检查通过后生成 Verilog 文件 ``./"
+"hw/gen/MyTopLevel.v``"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:25
+msgid ""
+"This is all you need to do to use SpinalHDL from VSCodium.  You now have the"
+" design-rule-checked Verilog and/or VHDL which you can use as input to your "
+"favorite synthesis tool."
+msgstr ""
+"这就是使用 VSCodium 的 SpinalHDL 所需要做的全部工作。"
+"您现在拥有经过设计规则检查的 Verilog 和/或 "
+"VHDL，您可以将其用作您最喜欢的综合工具的输入。"
+
+#: ../../SpinalHDL/Getting Started/VSCodium.rst:27
+msgid ""
+"Now that you know how to use the VSCodium development environment, let's "
+"explore the code: :ref:`Simple example`."
+msgstr "现在您已经知道如何使用 VSCodium 开发环境了，让我们来探索一下代码： :ref:`"
+"Simple example` 。"
+
+#~ msgid "VSCode works the same way as VSCodium."
+#~ msgstr "VSCode 的工作方式与 VSCodium 相同。"
+
+#~ msgid "The first time, in the extensions, install \"Scala (Metals)\"."
+#~ msgstr "第一次，在扩展中安装“Scala (Metals)”。"
+
+#~ msgid "This is all you need to do to use Spinal from VSCodium!"
+#~ msgstr "这就是使用 VSCodium 的 Spinal 所需要做的全部事情！"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/index.po
new file mode 100644
index 00000000000..554e7a37125
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/index.po	
@@ -0,0 +1,30 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlgetting-startedindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Getting Started/index.rst:3
+msgid "Getting Started"
+msgstr "入门"
+
+#: ../../source/SpinalHDL/Getting Started/index.rst:5
+msgid ""
+"Let's start learning SpinalHDL! In this chapter, we will install and setup "
+"an environment, taste the language and learn how to generate VHDL and "
+"Verilog, and perform lints on the fly."
+msgstr ""
+"让我们开始学习 SpinalHDL！在本章中，我们将安装和设置环境，"
+"体验该语言并学习如何生成 VHDL 和 "
+"Verilog，以及如何在编写代码的同时进行lint检查。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po
new file mode 100644
index 00000000000..b018b7964c1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po	
@@ -0,0 +1,173 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-17 12:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductiona-simple-example/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Introduction/A example.rst:4 simple
+msgid "A simple example"
+msgstr "一个简单的例子"
+
+#: ../../SpinalHDL/Introduction/A example.rst:6 simple
+msgid ""
+"Below is a simple hardware description from the `getting started "
+"<https://github.com/SpinalHDL/SpinalTemplateSbt>`_ repository."
+msgstr "以下是来自 `入门 <https://github.com/SpinalHDL/SpinalTemplateSbt>`_ "
+"仓库的简单硬件描述。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:29 simple
+msgid "It is split into chunks and explained in this section."
+msgstr "它在本节中被分成多个块进行解释。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:33 simple
+msgid "Component"
+msgstr "Component"
+
+#: ../../SpinalHDL/Introduction/A example.rst:35 simple
+msgid "First, there is the structure of a SpinalHDL ``Component``."
+msgstr "首先，这里有一个 SpinalHDL ``Component`` 的结构。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:37 simple
+msgid ""
+"A component is a piece of logic which can be instantiated (pasted) as many "
+"times as needed, and where the only accessible signals are its inputs and "
+"outputs."
+msgstr "组件是一段逻辑，可以根据需要多次实例化（粘贴），外部仅可通过输入和输出信号（i"
+"o）对其访问。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:50 simple
+msgid "``MyTopLevel`` is the name of the component."
+msgstr "``MyTopLevel`` 是组件的名称。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:52 simple
+msgid "In SpinalHDL, components use ``UpperCamelCase``."
+msgstr "在 SpinalHDL 中，组件使用 ``UpperCamelCase`` （驼峰命名法）。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:56 simple
+msgid "See also :ref:`Component` for more information."
+msgstr "请参阅 :ref:`组件<Component>` 了解更多信息。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:60 simple
+msgid "Ports"
+msgstr "端口"
+
+#: ../../SpinalHDL/Introduction/A example.rst:62 simple
+msgid "Then, the ports are defined."
+msgstr "然后，定义端口。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:71 simple
+msgid "Directions:"
+msgstr "方向："
+
+#: ../../SpinalHDL/Introduction/A example.rst:73 simple
+msgid "``cond0`` and ``cond1`` are inputs ports"
+msgstr "``cond0`` 和 ``cond1`` 是输入端口"
+
+#: ../../SpinalHDL/Introduction/A example.rst:74 simple
+msgid "``flag`` and ``state`` are outputs ports"
+msgstr "``flag`` 和 ``state`` 是输出端口"
+
+#: ../../SpinalHDL/Introduction/A example.rst:76 simple
+msgid "Types:"
+msgstr "类型："
+
+#: ../../SpinalHDL/Introduction/A example.rst:78 simple
+msgid "``cond0``, ``cond1`` and ``flag`` are 1 bit each (as 3 individual wires)"
+msgstr "``cond0``、``cond1`` 和 ``flag`` 各为一个比特（3 条单独的线）"
+
+#: ../../SpinalHDL/Introduction/A example.rst:79 simple
+msgid ""
+"``state`` is an 8-bit unsigned integer (a bus of 8 wires representing an "
+"unsigned integer)"
+msgstr "``state`` 是一个8位无符号整数（用一组8根线来表示一个无符号整数）"
+
+#: ../../SpinalHDL/Introduction/A example.rst:84 simple
+msgid ""
+"This syntax is only available since SpinalHDL 1.8, see :ref:`io` for legacy "
+"syntax and more information."
+msgstr "此语法仅自 SpinalHDL 1.8 起可用，请参阅 :ref:`io` 了解旧语法和更多信息。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:89 simple
+msgid "Internal logic"
+msgstr "内部逻辑"
+
+#: ../../SpinalHDL/Introduction/A example.rst:91 simple
+msgid "Finally, there is the component logic:"
+msgstr "最后，还有组件的逻辑："
+
+#: ../../SpinalHDL/Introduction/A example.rst:104 simple
+msgid ""
+"``counter`` is a register containing an 8-bits unsigned integer, with the "
+"initial value 0. Assignments to change the state of a register are available"
+" for read-back only after the next clock sampling."
+msgstr "``counter`` 是一个包含 8 位无符号整数的寄存器，初始值为 "
+"0。更改寄存器状态的赋值仅可在下一个时钟采样后回读。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:110 simple
+msgid ""
+"Because of the presence of a register, two implicit signals are added to the"
+" component for the clock and the reset. See :ref:`Reg` and "
+":ref:`clock_domain` for more information."
+msgstr ""
+"由于寄存器的存在，时钟和复位两个隐式信号被添加组件中。有关更多信息，请参阅 "
+":ref:`Reg` 和 :ref:`clock_domain` 。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:114 simple
+msgid ""
+"Then a conditional rule is described: when the input ``cond0`` (which is in "
+"the ``io`` bundle) is set, the ``counter`` is incremented by one, else "
+"``counter`` keeps its value set in the last rule. But, there is no previous "
+"rule, you would say. With a simple signal it would be a latch, and trigger "
+"an error. But here ``counter`` is a register, so it has a default case: it "
+"just keeps the same value."
+msgstr ""
+"然后描述一个条件规则：当输入 ``cond0`` （位于“io”线束中）被置1时，``counter``"
+" 加一，否则 ``counter`` 保持其值在最后一条规则中设置的值。但是，您可能会说，"
+"如果没有给出前置规则呢？对一个简单的**信号**来说，它将成为一个锁存器，并触发"
+"一个错误。但这里的 ``counter`` "
+"是一个寄存器，所以它有一个默认值，没有其他规则，它就保持初始值。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:121 simple
+msgid ""
+"This creates a multiplexer: the input of the ``counter`` register can be "
+"its output or its output plus one depending on ``io.cond0``."
+msgstr "这里创建了一个多路复用器： ``counter`` 寄存器的输入可以是其输出或其输出加一，"
+"这取决于 ``io.cond0`` 的值。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:124 simple
+msgid "Then unconditional rules (assignments) are described:"
+msgstr "然后描述无条件规则（赋值）："
+
+#: ../../SpinalHDL/Introduction/A example.rst:126 simple
+msgid ""
+"The output ``state`` is connected to the output of the register "
+"``counter``."
+msgstr "输出端口 ``state`` 连接到寄存器 ``counter`` 的输出。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:127 simple
+msgid ""
+"The output ``flag`` is the output of an ``or`` gate between a signal which "
+"is true when the output of \"``counter`` equals 0\", and the input "
+"``cond1``."
+msgstr ""
+"输出端口 ``flag`` 是输入信号 ``cond1`` 与另一信号之间的 ``or`` 门的输出，"
+"该信号在 ``counter`` 信号等于0时为真，否则为假。"
+
+#: ../../SpinalHDL/Introduction/A example.rst:132 simple
+msgid "See also :ref:`semantics` for more information."
+msgstr "有关更多信息，请参阅 :ref:`semantics` 。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Contributing.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Contributing.po
new file mode 100644
index 00000000000..5a7f56ada2a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Contributing.po
@@ -0,0 +1,42 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductioncontributing/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Introduction/Contributing.rst:2
+msgid "Contributing"
+msgstr "贡献"
+
+#: ../../source/SpinalHDL/Introduction/Contributing.rst:4
+msgid "`Repository of the language <https://github.com/SpinalHDL/SpinalHDL>`_"
+msgstr "`主代码库 <https://github.com/SpinalHDL/SpinalHDL>`_"
+
+#: ../../source/SpinalHDL/Introduction/Contributing.rst:5
+msgid ""
+"`Contributor guide "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/dev/CONTRIBUTING.md>`_"
+msgstr ""
+"`贡献者指南 <https://github.com/SpinalHDL/SpinalHDL/blob/dev/CONTRIBUTING."
+"md>`_"
+
+#: ../../source/SpinalHDL/Introduction/Contributing.rst:6
+msgid ""
+"`Repository of this documentation <https://github.com/SpinalHDL/SpinalDoc-"
+"RTD>`_"
+msgstr "`本文档的存储库 <https://github.com/SpinalHDL/SpinalDoc-RTD>`_"
+
+#: ../../source/SpinalHDL/Introduction/Contributing.rst:7
+msgid "`Donation channel <https://opencollective.com/spinalhdl>`_"
+msgstr "`捐赠渠道 <https://opencollective.com/spinalhdl>`_"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Getting in touch.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Getting in touch.po
new file mode 100644
index 00000000000..16ba783e4c6
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Getting in touch.po	
@@ -0,0 +1,55 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductiongetting-in-touch/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:2
+msgid "Getting in touch"
+msgstr "联系方式"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:4
+msgid "For questions about SpinalHDL syntax and live talks:"
+msgstr "有关 SpinalHDL 语法和现场演讲的问题："
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:6
+msgid "`English Matrix channel <https://gitter.im/SpinalHDL/SpinalHDL>`_"
+msgstr "`英文Matrix频道 <https://gitter.im/SpinalHDL/SpinalHDL>`_"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:7
+msgid "`Chinese Matrix channel <https://gitter.im/SpinalHDL-CN/Community>`_"
+msgstr "`中文Matrix频道 <https://gitter.im/SpinalHDL-CN/Community>`_"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:8
+msgid "`Google group <https://groups.google.com/forum/#!forum/spinalhdl-hardware-description-language>`_"
+msgstr ""
+"`Google 群组 <https://groups.google.com/forum/#!forum/spinalhdl-hardware-"
+"description-language>`_"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:10
+msgid "For bug reports, feature requests and questions:"
+msgstr "对于错误报告、功能请求和问题："
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:12
+msgid "`Open a ticket <https://github.com/SpinalHDL/SpinalHDL/issues/new>`_"
+msgstr "`开启一个工单 <https://github.com/SpinalHDL/SpinalHDL/issues/new>`_"
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:14
+msgid "If you are interested in a presentation, a workshop, or consulting:"
+msgstr "如果您对演示、研讨会或咨询感兴趣："
+
+#: ../../source/SpinalHDL/Introduction/Getting in touch.rst:16
+msgid ""
+"`Contact us by email: spinalhdl@gmail.com <mailto:spinalhdl@gmail.com>`_"
+msgstr "`通过电子邮件联系我们：spinalhdl@gmail.com <mailto:spinalhdl@gmail.com>`_"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/License.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/License.po
new file mode 100644
index 00000000000..7cb08535e47
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/License.po
@@ -0,0 +1,68 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-14 12:30+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionlicense/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Introduction/License.rst:2
+msgid "License"
+msgstr "许可证"
+
+#: ../../SpinalHDL/Introduction/License.rst:4
+msgid ""
+"SpinalHDL uses two licenses, one for ``spinal.core`` and one for "
+"``spinal.lib`` and everything else in the repository."
+msgstr ""
+"SpinalHDL 使用两种许可证，一种用于 ``spinal.core`` ，一种用于 ``spinal.lib`` "
+"以及仓库中的其他所有内容。"
+
+#: ../../SpinalHDL/Introduction/License.rst:7
+msgid ""
+"``spinal.core`` (the compiler) is under the LGPL license, which can be "
+"summarized as follows:"
+msgstr "``spinal.core`` （编译器）采用 LGPL 许可证，可概括如下："
+
+#: ../../SpinalHDL/Introduction/License.rst:10
+msgid ""
+"You can make money with your SpinalHDL description and its generated RTL."
+msgstr "您可以通过 SpinalHDL 描述及其生成的 RTL 赚钱。"
+
+#: ../../SpinalHDL/Introduction/License.rst:11
+msgid ""
+"You don't have to share your SpinalHDL description and its generated RTL."
+msgstr "您不必共享 SpinalHDL 描述及其生成的 RTL。"
+
+#: ../../SpinalHDL/Introduction/License.rst:12
+msgid "There are no fees and no royalties."
+msgstr "没有任何费用，也没有特许权使用费。"
+
+#: ../../SpinalHDL/Introduction/License.rst:13
+msgid ""
+"If your make improvements to the SpinalHDL core, and you wish to "
+"redistribute those modifications, you have to share those modifications "
+"to make the tool better for everybody."
+msgstr "如果您对 SpinalHDL "
+"核心进行改进，您必须分享您的修改以使该工具更好地为所有人服务。"
+
+#: ../../SpinalHDL/Introduction/License.rst:17
+msgid ""
+"``spinal.lib`` (a general purpose library of components/tools/interfaces)"
+" is under the permissive MIT license so you do not have to share it, even"
+" if contributions are really appreciated."
+msgstr "``spinal.lib`` （组件/工具/接口的通用库）处于宽松的 MIT "
+"许可证下，因此您不必共享它，若您做出贡献也非常感谢。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Other learning materials.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Other learning materials.po
new file mode 100644
index 00000000000..078b9d6eb5f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Other learning materials.po	
@@ -0,0 +1,77 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionother-learning-materials/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:2
+msgid "Other learning materials"
+msgstr "其他学习资料"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:4
+msgid ""
+"`A short show case (PDF slideshow) "
+"<https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/motivation.pdf>`_"
+msgstr ""
+"`一个简短的展示案例（PDF 幻灯片） "
+"<https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/motivation.pdf>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:5
+msgid ""
+"`Presentation of the language (PDF slideshow) "
+"<https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/presentation.pdf>`_"
+msgstr ""
+"`语言演示（PDF 幻灯片） "
+"<https://cdn.jsdelivr.net/gh/SpinalHDL/SpinalDoc@master/presentation/en/presentation.pdf>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:6
+msgid "`Jupyter bootcamp <https://github.com/SpinalHDL/Spinal-bootcamp>`_"
+msgstr "`Jupyter 训练营 <https://github.com/SpinalHDL/Spinal-bootcamp>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:7
+msgid "`Workshop <https://github.com/SpinalHDL/SpinalWorkshop>`_"
+msgstr "`研讨会 <https://github.com/SpinalHDL/SpinalWorkshop>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:9
+msgid "There is also a few more specific videos online :"
+msgstr "网上还有一些更具体的视频："
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:11
+msgid "`On youtube <https://www.youtube.com/results?search_query=SpinalHDL>`_"
+msgstr "`YouTube视频 <https://www.youtube.com/results?search_query=SpinalHDL>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:12
+msgid "`On f-si's peertube <https://peertube.f-si.org/search?search=SpinalHDL>`_"
+msgstr "`f-si peertube上的视频 <https://peertube.f-si.org/search?search=SpinalHDL>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:14
+msgid "A few SpinalHDL webinar were made and are recorded here :"
+msgstr "这里有几场 SpinalHDL 网络研讨会的视频录像："
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:16
+msgid "`Datenlord's youtube channel <https://www.youtube.com/@datenlord>`_"
+msgstr "`Datenlord的Youtube频道 <https://www.youtube.com/@datenlord>`_"
+
+#: ../../SpinalHDL/Introduction/Other learning materials.rst:21
+msgid ""
+"Some of those tutorials are not using the latest version of SpinalHDL, so"
+" they may lack some recent SpinalHDL features."
+msgstr "其中一些教程没有使用最新版本的 SpinalHDL，因此它们可能会缺少一些最新的 SpinalHDL 功能。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po
new file mode 100644
index 00000000000..ec97811ccef
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po	
@@ -0,0 +1,162 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionprojects-using-spinalhdl/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:2 using
+msgid "Projects using SpinalHDL"
+msgstr "使用 SpinalHDL 的项目"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:4 using
+msgid "Note that the following lists are very incompletes."
+msgstr "请注意，以下列表非常不完整。"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:9 using
+msgid "Repositories"
+msgstr "仓库"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:11 using
+msgid "`J1Sc Stack CPU <https://github.com/SteffenReith/J1Sc>`_"
+msgstr "`J1Sc 堆栈 CPU <https://github.com/SteffenReith/J1Sc>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:12 using
+msgid "`VexRiscv CPU and SoC <https://github.com/SpinalHDL/VexRiscv>`_"
+msgstr "`VexRiscv CPU 和 SoC <https://github.com/SpinalHDL/VexRiscv>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:13 using
+msgid "`NaxRiscv CPU <https://github.com/SpinalHDL/NaxRiscv>`_"
+msgstr "`NaxRiscv CPU <https://github.com/SpinalHDL/NaxRiscv>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:14 using
+msgid ""
+"`SaxonSoc "
+"<https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux>`_"
+msgstr ""
+"`SaxonSoc <https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/"
+"ArtyA7SmpLinux>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:15 using
+msgid "`open-rdma <https://github.com/datenlord/open-rdma>`_"
+msgstr "`open-rdma <https://github.com/datenlord/open-rdma>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:16 using
+msgid "`MicroRV32 SoC <https://github.com/agra-uni-bremen/microrv32>`_"
+msgstr "`MicroRV32 SoC <https://github.com/agra-uni-bremen/microrv32>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:17 SpinalHDL.rst:46
+#: SpinalHDL.rst:63 using
+msgid "\\.\\.\\."
+msgstr "\\.\\.\\."
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:21 using
+msgid "Companies"
+msgstr "公司"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:23 using
+msgid "`DatenLord, China <https://datenlord.github.io/>`_"
+msgstr "`达坦科技，中国 <https://datenlord.github.io/en/home.html>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:25 using
+msgid ""
+"`RoCE v2 hardware implementation <https://github.com/datenlord/open-rdma>`_"
+msgstr "`RoCE v2 硬件实现 <https://github.com/datenlord/open-rdma>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:26 using
+msgid ""
+"`WaveBPF <https://github.com/datenlord/wavebpf>`_ (wBPF): a \"tightly-"
+"coupled multi-core\" eBPF CPU, designed to be a high-throughput coprocessor "
+"for processing in-memory data (e.g. network packets)."
+msgstr ""
+"`WaveBPF <https://github.com/datenlord/wavebpf>`_ (wBPF)：一个“紧耦合多核”"
+"eBPF CPU，设计为用于处理内存数据的高吞吐量协处理器（例如网络数据包）。"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:30 using
+msgid "`Elitestek (FPGA Vendor), China <https://elitestek.com/product/RISC_V/>`_"
+msgstr "`易灵思（FPGA 供应商），中国 <https://elitestek.com/product/RISC_V/>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:32 using
+msgid ""
+"\"Elitestek has used the VexRISC-V core in FPGAs and applied in multi "
+"applications in worldwide customers.\""
+msgstr "\"易灵思已在 FPGA 中使用 VexRISC-V 内核，并应用于全球客户的多种应用。\""
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:35 using
+msgid "`LeafLabs, Massachusetts, USA <https://www.leaflabs.com>`_"
+msgstr "`LeafLabs，美国马萨诸塞州 <https://www.leaflabs.com>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:37 using
+msgid ""
+"`SpinalHDL To Accelerate Neuroscience (PDF slideshow) "
+"<https://github.com/SpinalHDL/SpinalHDL/files/10219043/SpinalHDL.To.Accelerate.Neuro.pdf>`_"
+msgstr ""
+"`SpinalHDL 加速神经科学（PDF 幻灯片） <https://github.com/SpinalHDL/"
+"SpinalHDL/files/10219043/SpinalHDL.To.Accelerate.Neuro.pdf>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:40 using
+msgid "QsPin, Belgium"
+msgstr "QsPin，比利时"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:42 using
+msgid "`Tiempo Secure, France <https://www.tiempo-secure.com/>`_"
+msgstr "`Tiempo Secure，法国 <https://www.tiempo-secure.com/>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:44 using
+msgid ""
+"`SpinalHDL for ASIC (PDF slideshow) "
+"<https://github.com/SpinalHDL/SpinalHDL/files/10239051/SpinalHDL.for.ASIC.pdf>`_"
+msgstr ""
+"`适用于 ASIC 的 SpinalHDL（PDF 幻灯片） <https://github.com/SpinalHDL/"
+"SpinalHDL/files/10239051/SpinalHDL.for.ASIC.pdf>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:49 using
+msgid "Universities"
+msgstr "大学"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:51 using
+msgid ""
+"`Universität Bremen - Fachbereich 3 - Informatik, Germany "
+"<http://www.informatik.uni-bremen.de/agra/ger/index.php>`_"
+msgstr ""
+"`不来梅大学 - 数学与计算机科学学院，德国 <http://www.informatik.uni-bremen."
+"de/agra/ger/index.php>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:54 using
+msgid ""
+"`SpinalHDL in Computer Architecture Research and Education (PDF slideshow) "
+"<https://github.com/SpinalHDL/SpinalHDL/files/10244833/20221216_summit_saahm.pdf>`_"
+msgstr ""
+"`计算机体系结构研究和教育中的 SpinalHDL（PDF 幻灯片） <https://github.com/"
+"SpinalHDL/SpinalHDL/files/10244833/20221216_summit_saahm.pdf>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:57 using
+msgid ""
+"`Universität Potsdam - Embedded Systems Architectures for Signalprocessing, "
+"Germany <https://www.uni-potsdam.de/en/aess/>`_"
+msgstr "`波茨坦大学 - 用于信号处理的嵌入式系统架构，德国 <https://www.uni-potsdam.de/"
+"en/aess/>`_"
+
+#: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:60 using
+msgid ""
+"`A Network Attached Deep Learning Accelerator for FPGA Clusters (PDF "
+"slideshow) "
+"<https://github.com/SpinalHDL/SpinalHDL/files/10238707/A_Network_Attached_Deep_Learning_Accelerator_for_FPGA_Clusters.pdf>`_"
+msgstr ""
+"`用于 FPGA 集群的网络附加深度学习加速器（PDF 幻灯片） <https://github.com/"
+"SpinalHDL/SpinalHDL/files/10238707/"
+"A_Network_Attached_Deep_Learning_Accelerator_for_FPGA_Clusters.pdf>`_"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/SpinalHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/SpinalHDL.po
new file mode 100644
index 00000000000..45c6f4ef4df
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/SpinalHDL.po
@@ -0,0 +1,224 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-02 16:43+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionspinalhdl/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:4
+msgid "About SpinalHDL"
+msgstr "关于 SpinalHDL"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:7
+msgid "What is SpinalHDL?"
+msgstr "什么是SpinalHDL？"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:9
+msgid ""
+"SpinalHDL is an open source high-level hardware description language with "
+"associated tools. Its development started in December 2014."
+msgstr "SpinalHDL 是一种开源高级硬件描述语言及其相关工具。它的开发始于 2014 年 12 "
+"月。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:12
+msgid ""
+"SpinalHDL makes it possible to efficiently describe hardware, giving names "
+"to digital hardware notions; the most obvious examples are ``Reg`` and "
+"``Latch``. In event-driven languages such as VHDL and Verilog, to use these "
+"two common elements, the user has to describe how to simulate them with a "
+"process, so that the synthesis tool can infer what cell it is. With "
+"SpinalHDL, you just have to declare a ``Reg`` or a ``Latch``."
+msgstr ""
+"SpinalHDL 通过对数字硬件命名和建模使得高效地描述硬件成为可能；最明显的例子是 "
+"``Reg`` 和 ``Latch``。在VHDL和Verilog等事件驱动语言中，要使用这两个常见元素，"
+"用户必须用过程来模拟它们，以便综合工具可以推断出它是什么单元。使用 "
+"SpinalHDL，您只需声明一个 ``Reg`` 或 ``Latch``。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:19
+msgid ""
+"SpinalHDL is a *domain-specific language* based on Scala a general-purpose "
+"language. It brings several benefits:"
+msgstr "SpinalHDL 是一种基于通用语言 Scala 的 *领域专用语言* 。它带来了几个好处："
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:22
+msgid ""
+"There are free integrated development environments supporting it, providing "
+"many features that simple text editors don't have:"
+msgstr "有免费的集成开发环境支持它，提供了许多简单文本编辑器所没有的功能："
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:25
+msgid "syntax and type errors are highlighted right in the code"
+msgstr "语法和类型错误在代码中高亮显示"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:26
+msgid "correct renaming, even across files"
+msgstr "正确的重命名，甚至是跨文件的"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:27
+msgid "smart auto completion / suggestions"
+msgstr "智能自动完成/建议"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:28
+msgid "navigation tools (go to definition, show all references, etc.)"
+msgstr "导航工具（转到定义、显示所有引用等）"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:30
+msgid ""
+"It allows to implement simple to complex hardware generators (meta-hardware "
+"description) with no need to deal with several languages."
+msgstr "它允许实现简单到复杂的硬件生成器（元硬件描述），而无需处理多种语言（译者注："
+"例如Python+Verilog）。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:35
+msgid ""
+"`Scala <https://scala-lang.org/>`_ is a statically-typed, functional and "
+"object-oriented language using the Java virtual machine (JVM)."
+msgstr ""
+"`Scala <https://scala-lang.org/>`_ 是一种使用 Java 虚拟机 (JVM) "
+"的静态类型、函数式和面向对象的语言。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:40
+msgid "What SpinalHDL is not"
+msgstr "SpinalHDL 不是什么"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:42
+msgid ""
+"SpinalHDL is not an HLS tool: its goal is not to automagically transform an "
+"abstract algorithm into a digital circuit. Its goal is to create a new "
+"abstraction level by naming things, to help the designer reuse their code "
+"and not write the same thing over and over again."
+msgstr ""
+"SpinalHDL 不是 HLS 工具：它的目标不是自动将抽象算法转换为数字电路。它的目的是"
+"借助命名事物来创建新的高层次抽象，以帮助设计人员重用他们的代码，而不是一遍又"
+"一遍地编写相同的事物。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:47
+msgid ""
+"SpinalHDL is not an analog modeling language. VHDL and Verilog make it "
+"possible for analog designers to provide a model of their IP to digital "
+"designers. SpinalHDL does not address this case, and is for digital "
+"designers to describe their own digital designs."
+msgstr ""
+"SpinalHDL 不是模拟电路建模语言。 VHDL 和 Verilog "
+"使模拟电路设计人员能够向数字设计人员提供其 IP 模型。 SpinalHDL "
+"不解决这种情况，而是供数字设计师描述他们自己的数字设计。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:54
+msgid "The Spinal development flow"
+msgstr "Spinal开发流程"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:56
+msgid "Once code is written in *SpinalHDL*, the tool can:"
+msgstr "一旦用 *SpinalHDL* 编写代码，该工具就可以："
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:58
+msgid ""
+"Generate VHDL, Verilog or SystemVerilog, to instantiate it in one of these "
+"languages or give it to any simulator or synthesis tool. There is no logic "
+"overhead, hierarchy and names are preserved, and it runs design checks "
+"during generation."
+msgstr ""
+"生成 VHDL、Verilog 或 SystemVerilog，以这些语言之一实例化它或将其提供给任何仿"
+"真器或综合工具。没有逻辑开销，保留层次结构和名称，并且在生成期间运行设计检查"
+"。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:62
+msgid "Boot a simulation using Verilator or another supported simulator."
+msgstr "使用 Verilator 或其他支持的仿真器进行仿真。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:68
+msgid ""
+"As SpinalHDL is interoperable with VHDL and (System)Verilog, you can both "
+"instantiate SpinalHDL IPs in these language (using generated code) and "
+"instantiate IPs in these languages in SpinalHDL (using ``BlackBox``)."
+msgstr ""
+"由于 SpinalHDL 可以与 VHDL 和（System）Verilog 互操作，"
+"因此您既可以用这些语言实例化 SpinalHDL IP（使用生成的代码），也可以用 "
+"SpinalHDL 实例化这些语言的 IP（使用 ``BlackBox``）。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:74
+msgid ""
+"SpinalHDL is *fully interoperable* with standard VHDL/Verilog-based EDA "
+"tools (simulators and synthesizers) as the output generated by the toolchain"
+" can be VHDL or Verilog."
+msgstr ""
+"SpinalHDL 与基于标准 VHDL/Verilog 的 EDA "
+"工具（仿真器和综合器）*完全可互操作*，因为工具链生成的输出是 VHDL 或 "
+"Verilog。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:80
+msgid "Advantages of using SpinalHDL over VHDL / Verilog"
+msgstr "SpinalHDL 相对于 VHDL / Verilog 的优势"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:82
+msgid ""
+"As SpinalHDL is based on a high-level language, it provides several "
+"advantages to improve your hardware coding:"
+msgstr "由于 SpinalHDL 基于高级语言，因此它提供了多种优势来改进您的硬件编码："
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:84
+msgid ""
+"**No more endless wiring** - Create and connect complex buses like AXI in "
+"one single line."
+msgstr "**不再需要无休止的布线** - 一行代码完成复杂总线（例如 AXI）的创建和连接。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:85
+msgid ""
+"**Evolving capabilities** - Create your own bus definitions and abstraction "
+"layers."
+msgstr "**不断发展的功能** - 创建您自己的总线定义和抽象层。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:86
+msgid ""
+"**Reduce code size** - By a high factor, especially for wiring. This enables"
+" you to have a better overview of your code base, increase your productivity"
+" and create fewer headaches."
+msgstr "**减少代码大小** - 大幅减少，特别是对于接线而言。这使您能够更好地了解代码库、"
+"提高工作效率并减少麻烦。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:87
+msgid ""
+"**Free and user friendly IDE** - Thanks to Scala tools for auto-completion, "
+"error highlighting, navigation shortcuts, and many others."
+msgstr "**免费且用户友好的 IDE** - 得益于 Scala "
+"工具的自动完成、错误突出显示、导航快捷方式等。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:88
+msgid ""
+"**Powerful and easy type conversions** - Bidirectional translation between "
+"any data type and bits. Useful when loading a complex data structure from a "
+"CPU interface."
+msgstr "**功能强大且简单的类型转换** - 任何数据类型和位向量之间的双向转换。从 CPU "
+"接口加载复杂的数据结构时非常有用。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:89
+msgid ""
+"**Design checks** - Early stage lints to check that there are eg no "
+"combinatorial loops / latches."
+msgstr "**设计检查** - 早期阶段检查是否存在组合循环/锁存器。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:90
+msgid ""
+"**Clock domain safety** - Early stage lints to inform you that there are "
+"no unintentional clock domain crossings."
+msgstr "**时钟域安全** - 早期 lint 通知是否存在无意识引入的违例跨时钟域信号。"
+
+#: ../../SpinalHDL/Introduction/SpinalHDL.rst:91
+msgid ""
+"**Generic design** - There are no restrictions to the genericity of your "
+"hardware description by using Scala constructs."
+msgstr "**通用设计** - 使用 Scala 构造，因此对硬件描述的通用性没有任何限制。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/faq.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/faq.po
new file mode 100644
index 00000000000..b8a00e87595
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/faq.po
@@ -0,0 +1,192 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-02 16:43+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionfaq/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../SpinalHDL/Introduction/faq.rst:2
+msgid "FAQ"
+msgstr "常见问题"
+
+#: ../../SpinalHDL/Introduction/faq.rst:5
+msgid ""
+"What is the overhead of SpinalHDL generated RTL compared to human written "
+"VHDL/Verilog?"
+msgstr "与人工编写的 VHDL/Verilog 相比，SpinalHDL 生成的 RTL 的开销是多少？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:7
+msgid ""
+"The overhead is nil.  SpinalHDL generates the same HDL constructs found in "
+"human written VHDL/Verilog with no additional instantiated artifacts present"
+" in the resulting implementation due to its use.  This makes the overhead "
+"zero when comparing the generated HDL against handwritten HDL."
+msgstr ""
+"开销为零。 SpinalHDL 生成与人类编写的 VHDL/Verilog 中相同的 HDL "
+"构造，在最终实现中不存在额外的实例化工件，这也取决于你的使用方法。"
+"这使得在将生成的 HDL 与手写 HDL 进行比较时的开销为零。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:12
+msgid ""
+"Due to the powerful expressive nature of the Scala/SpinalHDL languages, the "
+"design is more concise for a given complex hardware design and has strong "
+"type safety, strong HDL safety paradigms that result in fewer lines of code,"
+" able to achieve more functionality with fewer bugs."
+msgstr ""
+"由于Scala/SpinalHDL语言强大的表达能力，对于给定的复杂硬件设计来说，设计更加简"
+"洁，并且具有很强的类型安全性，强大的HDL安全范式导致更少的代码行，能够以更少的"
+"错误实现更多的功能。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:17
+msgid ""
+"SpinalHDL does not take a HLS approach and is not itself a HLS solution. Its"
+" goal is not to translate any arbitrary code into RTL, but to provide a "
+"powerful language to describe RTL and raise the abstraction level and "
+"increase code reuse at the level the designer is working."
+msgstr ""
+"SpinalHDL 不采用 HLS 方法，本身也不是 HLS 解决方案。"
+"其目标不是将任意代码转换为 RTL，而是通过提高抽象级别、"
+"增加代码重用能力来提供一种功能强大的语言来描述 RTL。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:22
+msgid "What if SpinalHDL becomes unsupported in the future?"
+msgstr "如果 SpinalHDL 将来没有支持了怎么办？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:24
+msgid "This question has two sides:"
+msgstr "这个问题有两个方面："
+
+#: ../../SpinalHDL/Introduction/faq.rst:26
+msgid ""
+"SpinalHDL generates VHDL/Verilog files, which means that SpinalHDL will be "
+"supported by all EDA tools for many decades."
+msgstr "SpinalHDL 生成 VHDL/Verilog 文件，这意味着 SpinalHDL "
+"仍将在未来几十年内得到所有 EDA 工具的支持。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:27
+msgid ""
+"If there is a bug in SpinalHDL and there is no longer support to fix it, "
+"it's not a deadly situation, because the SpinalHDL compiler is fully open "
+"source.  For simple issues, you may be able to fix the issue yourself within"
+" a few hours."
+msgstr ""
+"如果 SpinalHDL 中存在错误并且不再支持修复它，这也不是致命的情况，因为 "
+"SpinalHDL "
+"编译器是完全开源的。对于简单的问题，您也许可以在几个小时内自行解决问题。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:30
+msgid ""
+"Consider how much time it takes for a commercial EDA vendor to fix issues or"
+" to add new features in their closed tools. Consider also your cost and time"
+" savings achieved when using SpinalHDL and the potential for your own entity"
+" to give back to the community some of this as engineering time, open-source"
+" contribution time or donations to the project to improve its future."
+msgstr ""
+"考虑一下商业 EDA 供应商需要多少时间来解决问题或在其封闭工具中添加新功能。"
+"还要考虑使用 SpinalHDL 时节省的成本和时间，以及您自己的实体回馈社区的潜力，其"
+"中包括工程时间、开源贡献时间或对项目的捐赠，以改善其未来。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:36
+msgid "Does SpinalHDL keep comments in generated VHDL/verilog?"
+msgstr "SpinalHDL 是否在生成的 VHDL/Verilog 中保留注释？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:38
+msgid ""
+"No, it doesn't. Generated files should be considered as a netlist. For "
+"example, when you compile C code, do you care about your comments in the "
+"generated assembly code?"
+msgstr "事实并非如此。生成的文件应被视为网表。例如，当你编译C代码时，你关心生成的汇编"
+"代码中的注释吗？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:42
+msgid "Could SpinalHDL scale up to big projects?"
+msgstr "SpinalHDL 可以扩展到大型项目吗？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:44
+msgid ""
+"Yes, some experiments were done, and it appears that generating hundreds "
+"of 3KLUT CPUs with caches takes around 12 seconds, which is a "
+"ridiculously short time compared to the time required to simulate or "
+"synthesize this kind of design."
+msgstr ""
+"是的，已经进行了一些实验，如生成数百个带缓存的 3KLUT CPU 大约需要 12 "
+"秒，与仿真或综合此类设计所需的时间相比，这是一个短得多的时间。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:48
+msgid "How SpinalHDL came to be"
+msgstr "SpinalHDL 是如何诞生的"
+
+#: ../../SpinalHDL/Introduction/faq.rst:50
+msgid ""
+"Between December 2014 and April 2016, it was as a personal hobby project.  "
+"But since April 2016 one person is working full time on it. Some people are "
+"also regularly contributing to the project."
+msgstr ""
+"2014年12月至2016年4月期间，这是一个个人爱好项目。但自 2016 年 4 "
+"月起，就有一个人全职从事这项工作。有些人也定期为该项目做出贡献。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:54
+msgid "Why develop a new language when there is VHDL/Verilog/SystemVerilog?"
+msgstr "既然有了VHDL/Verilog/SystemVerilog，为什么还要开发新的语言呢？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:56
+msgid "The :ref:`Foreword` is dedicated to this topic."
+msgstr ":ref:`前言<Foreword>` 专门讨论这个主题。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:59
+msgid "How to use an unreleased version of SpinalHDL (but committed on git)?"
+msgstr "如何使用 SpinalHDL 的未发布版本（但在 git 上提交）？"
+
+#: ../../SpinalHDL/Introduction/faq.rst:61
+msgid "First, you need to get the repository, if you haven't cloned it yet:"
+msgstr "首先，如果您还没有克隆存储库，则需要获取存储库："
+
+#: ../../SpinalHDL/Introduction/faq.rst:68
+msgid ""
+"In the command above you can replace ``dev`` by the name of the branch you "
+"want to checkout. ``--depth 1`` prevents from downloading the repository "
+"history."
+msgstr "在上面的命令中，您可以将 ``dev`` 替换为您要签出的分支的名称。 ``--depth 1`` "
+"阻止下载存储库历史记录。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:71
+msgid "Then publish the code as it is in the directory fetched:"
+msgstr "然后将获取目录中的代码发布："
+
+#: ../../SpinalHDL/Introduction/faq.rst:77
+msgid ""
+"Here ``2.12.13`` is the Scala version used. The first two numbers must "
+"match the ones of the version used in your project. You can find it in "
+"your ``build.sbt`` and/or ``build.sc``:"
+msgstr ""
+"这里 ``2.12.13`` "
+"是使用的Scala版本。前两个数字必须与您的项目中使用的版本相匹配。您可以在 "
+"``build.sbt`` 和/或 ``build.sc`` 中找到它："
+
+#: ../../SpinalHDL/Introduction/faq.rst:87
+msgid ""
+"Then in your project, update the SpinalHDL version specified in your "
+"``build.sbt`` or ``build.sc``: it should be set to ``dev`` instead of a "
+"version number."
+msgstr ""
+"然后在您的项目中，更新 ``build.sbt`` 或 ``build.sc`` 中指定的 SpinalHDL "
+"版本：应将其设置为 ``dev`` 而不是版本号。"
+
+#: ../../SpinalHDL/Introduction/faq.rst:99
+msgid ""
+"Here it is always ``dev`` no matter the branch you have checked out earlier."
+msgstr "无论您之前签出哪个分支，这里总是 ``dev`` 。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/index.po
new file mode 100644
index 00000000000..5d2a379f3c2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/index.po
@@ -0,0 +1,26 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlintroductionindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Introduction/index.rst:2
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Introduction/index.rst:4
+msgid ""
+"This section introduces the SpinalHDL project: the language, and everything "
+"around it."
+msgstr "本节介绍 SpinalHDL 项目：该语言以及与之相关的所有内容。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/index.po
new file mode 100644
index 00000000000..d0f5f6c7a30
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-15 15:56+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacyindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Legacy/index.rst:3
+msgid "Legacy"
+msgstr "历史遗留"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware.po
new file mode 100644
index 00000000000..ec67c317b63
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware.po
@@ -0,0 +1,188 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacypinsechardware/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:5
+msgid "Hardware"
+msgstr "硬件"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:8
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:10
+msgid "There is the Pinsec toplevel hardware diagram :"
+msgstr "这是Pinsec顶层硬件图："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:16
+msgid "RISCV"
+msgstr "RISCV"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:18
+msgid "The RISCV is a 5 stage pipelined CPU with following features :"
+msgstr "RISCV是一款5级流水线CPU，具有以下特性："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:21
+msgid "Instruction cache"
+msgstr "指令缓存"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:22
+msgid "Single cycle Barrel shifter"
+msgstr "单周期桶式移位器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:23
+msgid "Single cycle MUL, 34 cycle DIV"
+msgstr "单周期MUL、34周期DIV"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:24
+msgid "Interruption support"
+msgstr "中断支持"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:25
+msgid "Dynamic branch prediction"
+msgstr "动态分支预测"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:26
+msgid "Debug port"
+msgstr "调试端口"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:29
+msgid "AXI4"
+msgstr "AXI4"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:31
+msgid ""
+"As previously said, Pinsec integrates an AXI4 bus fabric. AXI4 is not the "
+"easiest bus to work with but has many advantages like:"
+msgstr "如前所述，Pinsec集成了AXI4总线结构。 "
+"AXI4不是最容易使用的总线，但具有许多优点，例如："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:34
+msgid "A flexible topology"
+msgstr "灵活的拓扑结构"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:35
+msgid "High bandwidth potential"
+msgstr "高带宽潜力"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:36
+msgid "Potential out of order request completion"
+msgstr "潜在的乱序请求完成"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:37
+msgid "Easy methods to meets clocks timings"
+msgstr "满足时钟时序的简单方法"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:38
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:59
+msgid "Standard used by many IP cores"
+msgstr "被许多IP核使用的标准"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:39
+msgid "A handshake methodology that fits with SpinalHDL Stream."
+msgstr "适合SpinalHDL反压流(Stream)的握手方法。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:41
+msgid ""
+"From an Area utilization perspective, AXI4 is for sure not the lightest "
+"solution, but some techniques could dramatically reduce that concern :"
+msgstr "从面积利用率的角度来看，AXI4肯定不是最轻量的解决方案，但某些技术可以大大减少"
+"这种担忧："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:44
+msgid "Using Read-Only/Write-Only AXI4 variations where that is possible"
+msgstr "在可能的情况下使用只读/只写AXI4变体"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:45
+msgid ""
+"Introducing an Axi4-Shared variation where a new ARW channel is introduced "
+"to replace and combine AR and AW channels. This solution reduces resource "
+"usage by a factor of two for the address decoding and the address "
+"arbitration."
+msgstr "引入Axi4-Shared变体，其中引入新的ARW通道来代替和组合AR和AW通道。该解决方案将"
+"地址解码和地址仲裁的资源使用量减少了两倍。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:46
+msgid ""
+"Timing relaxation is possible depending upon the interconnect "
+"implementation, and if all masters never stall the R/B channel (RREADY and "
+"BREADY are strapped to 1). Both xREADY signals can be removed by synthesis "
+"in this case, relaxing timings."
+msgstr ""
+"根据互连实现的不同，如果所有主设备都不会使R/B通道停滞（RREADY和BREADY被固定为"
+"1），则可以进行时序松弛。在这种情况下，可以通过综合去除两个xREADY信号，从而放"
+"宽时序。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:47
+msgid ""
+"As the AXI4 spec suggests, the interconnect can expand the transactions ID "
+"by aggregating the corresponding input port ID. This allows the interconnect"
+" to have an infinite number of pending requests and also to support out of "
+"order completion with a negligible area cost (transaction ID expand)."
+msgstr ""
+"正如AXI4规范所建议的，互连可以通过聚合相应的输入端口ID来扩展事务ID。这允许互"
+"连具有无限数量的待处理请求，并且能够以极小的面积成本（扩大事务ID）支持乱序完"
+"成。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:49
+msgid "The Pinsec interconnect doesn't introduce latency cycles."
+msgstr "Pinsec互连不会引入延迟周期。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:52
+msgid "APB3"
+msgstr "APB3"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:54
+msgid ""
+"In Pinsec, all peripherals implement an APB3 bus to be interfaced. The APB3 "
+"choice was motivated by following reasons :"
+msgstr "在Pinsec中，所有外设均实现了一个APB3总线接口。选择APB3的原因如下："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:57
+msgid "Very simple bus (no burst)"
+msgstr "非常简单的总线（无突发）"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:58
+msgid "Use very few resources"
+msgstr "使用很少的资源"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:62
+msgid "Generate the RTL"
+msgstr "生成RTL"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:64
+msgid "To generate the RTL, you have multiple solutions :"
+msgstr "要生成RTL，您有多种方案："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:66
+msgid "You can download the SpinalHDL source code, and then run :"
+msgstr "您可以下载SpinalHDL源代码，然后运行："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:72
+msgid ""
+"Or you can create your own main into your own SBT project and then run it :"
+msgstr "或者您可以在自己的SBT项目中创建自己的main，然后运行它："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware.rst:86
+msgid ""
+"Currently, only the verilog version was tested in simulation and in FPGA "
+"because the last release of GHDL is not compatible with cocotb."
+msgstr "目前，由于最新版本的GHDL与cocotb不兼容，因此仅在仿真和FPGA中测试了verilog版本"
+"。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po
new file mode 100644
index 00000000000..d5c26774bf0
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po
@@ -0,0 +1,429 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacypinsechardware_toplevel/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:7
+msgid "SoC toplevel (Pinsec)"
+msgstr "SoC顶层(Pinsec)"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:12
+msgid ""
+"``Pinsec`` is a little SoC designed for FPGA. It is available in the "
+"SpinalHDL library and some documentation could be find :ref:`there "
+"<pinsec_introduction>`"
+msgstr ""
+"``Pinsec`` 是一个专为FPGA设计的小型 SoC。它可以在SpinalHDL库中找到，"
+"并且可以在 :ref:`这里 <pinsec_introduction>` 找到一些文档"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:14
+msgid ""
+"Its toplevel implementation is an interesting example, because it is a mix "
+"some design patterns that make it very easy to modify. Adding a new master "
+"or a new peripheral to the bus fabric could be done with little effort."
+msgstr "它的顶层实现是一个有趣的例子，因为它混合了一些设计模式，使其非常容易修改。可"
+"以轻松实现向总线结构添加新的主设备或新的外设。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:16
+msgid ""
+"The toplevel implementation could be consulted at the links here : "
+"`https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala"
+" "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala>`_"
+msgstr ""
+"可以在以下链接中查阅顶层实现：`https://github.com/SpinalHDL/SpinalHDL/blob/"
+"master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala <https://github."
+"com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/"
+"Pinsec.scala>`_"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:19
+msgid "This is the Pinsec toplevel hardware diagram :"
+msgstr "这是Pinsec顶层硬件图："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:25
+msgid "Defining all IO"
+msgstr "定义所有IO"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:47
+msgid "Clock and resets"
+msgstr "时钟和复位"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:49
+msgid "Pinsec has three clocks inputs :"
+msgstr "Pinsec有三个时钟输入："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:52
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:70
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:73
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:76
+msgid "axiClock"
+msgstr "axiClock"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:53
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:79
+msgid "vgaClock"
+msgstr "vgaClock"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:54
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:82
+msgid "jtag.tck"
+msgstr "jtag.tck"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:56
+msgid "And one reset input :"
+msgstr "以及一个复位输入："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:59
+msgid "asyncReset"
+msgstr "asyncReset"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:61
+msgid "Which will finally give 5 ClockDomain (clock/reset couple) :"
+msgstr "最终将给出5个时钟域(ClockDomain)（时钟/复位对）："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:66
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:67
+msgid "Clock"
+msgstr "时钟"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:68
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:69
+msgid "resetCtrlClockDomain"
+msgstr "resetCtrlClockDomain"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:71
+msgid ""
+"Used by the reset controller, Flops of this clock domain are initialized by "
+"the FPGA bitstream"
+msgstr "由复位控制器使用，该时钟域的触发器由FPGA比特流初始化"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:72
+msgid "axiClockDomain"
+msgstr "axiClockDomain"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:74
+msgid "Used by all component connected to the AXI and the APB interconnect"
+msgstr "由连接到AXI和APB互连的所有组件使用"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:75
+msgid "coreClockDomain"
+msgstr "coreClockDomain"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:77
+msgid ""
+"The only difference with the axiClockDomain, is the fact that the reset "
+"could also be asserted by the debug module"
+msgstr "与axiClockDomain的唯一区别是，复位也可以通过调试模块控制"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:78
+msgid "vgaClockDomain"
+msgstr "vgaClockDomain"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:80
+msgid "Used by the VGA controller backend as a pixel clock"
+msgstr "被VGA控制器后端用作像素时钟"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:81
+msgid "jtagClockDomain"
+msgstr "jtagClockDomain"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:83
+msgid "Used to clock the frontend of the JTAG controller"
+msgstr "用于为JTAG控制器的前端提供时钟"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:87
+msgid "Reset controller"
+msgstr "复位控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:89
+msgid ""
+"First we need to define the reset controller clock domain, which has no "
+"reset wire, but use the FPGA bitstream loading to setup flipflops."
+msgstr "首先我们需要定义复位控制器时钟域，它没有复位线，而是使用FPGA比特流加载来设置"
+"触发器。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:100
+msgid "Then we can define a simple reset controller under this clock domain."
+msgstr "然后我们可以在这个时钟域下定义一个简单的复位控制器。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:131
+msgid "Clock domain setup for each system"
+msgstr "每个系统的时钟域设置"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:133
+msgid ""
+"Now that the reset controller is implemented, we can define clock domain for"
+" all sub-systems of Pinsec :"
+msgstr "现在复位控制器已经实现，我们可以为Pinsec的所有子系统定义时钟域："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:157
+msgid ""
+"Also all the core system of Pinsec will be defined into a ``axi`` clocked "
+"area :"
+msgstr "此外，Pinsec的所有核心系统都将在一个 ``axi`` 时钟域里定义："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:166
+msgid "Main components"
+msgstr "主要组件"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:168
+msgid "Pinsec is constituted mainly by 4 main components :"
+msgstr "Pinsec主要由4个主要组件构成："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:171
+msgid "One RISCV CPU"
+msgstr "1个RISCV CPU"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:172
+msgid "One SDRAM controller"
+msgstr "1个SDRAM控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:173
+msgid "One on chip memory"
+msgstr "1个片上存储器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:174
+msgid "One JTAG controller"
+msgstr "1个JTAG控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:177
+msgid "RISCV CPU"
+msgstr "RISCV CPU"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:179
+msgid "The RISCV CPU used in Pinsec as many parametrization possibilities :"
+msgstr "Pinsec中使用的RISCV CPU具有多种参数化可能性："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:226
+msgid "On chip RAM"
+msgstr "片上RAM"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:228
+msgid "The instantiation of the AXI4 on chip RAM is very simple."
+msgstr "AXI4片上RAM的实例化非常简单。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:230
+msgid ""
+"In fact it's not an AXI4 but an Axi4Shared, which mean that a ARW channel "
+"replace the AR and AW ones. This solution uses less area while being fully "
+"interoperable with full AXI4."
+msgstr ""
+"事实上，它不是AXI4，而是Axi4Shared，这意味着ARW通道取代了AR和AW通道。该解决方"
+"案占用的面积更少，同时可与完整的AXI4实现完全互操作。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:242
+msgid "SDRAM controller"
+msgstr "SDRAM控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:244
+msgid ""
+"First you need to define the layout and timings of your SDRAM device. On the"
+" DE1-SOC, the SDRAM device is an IS42x320D one."
+msgstr "首先，您需要定义SDRAM设备的布局和时序。在DE1-SOC上，SDRAM型号是IS42x320D。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:271
+msgid ""
+"Then you can used those definition to parametrize the SDRAM controller "
+"instantiation."
+msgstr "然后您可以使用这些定义来参数化SDRAM控制器实例。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:284
+msgid "JTAG controller"
+msgstr "JTAG控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:286
+msgid ""
+"The JTAG controller could be used to access memories and debug the CPU from "
+"an PC."
+msgstr "JTAG控制器可用于在PC访问存储器并调试CPU。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:298
+msgid "Peripherals"
+msgstr "外设"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:300
+msgid "Pinsec has some integrated peripherals :"
+msgstr "Pinsec有一些集成的外设："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:303
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:309
+msgid "GPIO"
+msgstr "GPIO"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:304
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:322
+msgid "Timer"
+msgstr "计时器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:305
+msgid "UART"
+msgstr "串口"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:306
+msgid "VGA"
+msgstr "VGA"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:324
+msgid "The Pinsec timer module consists of :"
+msgstr "Pinsec定时器模块包括："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:327
+msgid "One prescaler"
+msgstr "1个预分频器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:328
+msgid "One 32 bits timer"
+msgstr "1个32位定时器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:329
+msgid "Three 16 bits timers"
+msgstr "三个16位定时器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:331
+msgid "All of them are packed into the PinsecTimerCtrl component."
+msgstr "所有这些都被打包到PinsecTimerCtrl组件中。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:338
+msgid "UART controller"
+msgstr "UART控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:340
+msgid "First we need to define a configuration for our UART controller :"
+msgstr "首先我们需要为UART控制器定义一个配置："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:356
+msgid "Then we can use it to instantiate the UART controller"
+msgstr "然后我们可以用它来实例化UART控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:363
+msgid "VGA controller"
+msgstr "VGA控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:365
+msgid "First we need to define a configuration for our VGA controller :"
+msgstr "首先我们需要定义VGA控制器的配置："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:379
+msgid "Then we can use it to instantiate the VGA controller"
+msgstr "然后我们可以用它来实例化VGA控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:386
+msgid "Bus interconnects"
+msgstr "总线互连"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:388
+msgid "There is three interconnections components :"
+msgstr "共有三个互连组件："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:391
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:409
+msgid "AXI4 crossbar"
+msgstr "AXI4交叉开关(crossbar)"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:392
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:396
+msgid "AXI4 to APB3 bridge"
+msgstr "AXI4桥接到APB3"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:393
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:471
+msgid "APB3 decoder"
+msgstr "APB3解码器"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:398
+msgid ""
+"This bridge will be used to connect low bandwidth peripherals to the AXI "
+"crossbar."
+msgstr "该桥将用于将低带宽外设连接到AXI交叉开关。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411
+msgid ""
+"The AXI4 crossbar that interconnect AXI4 masters and slaves together is "
+"generated by using an factory. The concept of this factory is to create it, "
+"then call many function on it to configure it, and finaly call the ``build``"
+" function to ask the factory to generate the corresponding hardware :"
+msgstr ""
+"将AXI4主端和从端互连在一起的AXI4交叉开关是使用生成器(factory)生成的。这个生成"
+"器的概念是先创建它，然后调用它的许多函数来配置，最后调用 ``build`` "
+"函数来使生成器生成相应的硬件："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421
+msgid "First you need to populate slaves interfaces :"
+msgstr "首先，您需要添加从端接口："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:433
+msgid ""
+"Then you need to populate a matrix of interconnections between slaves and "
+"masters (this sets up visibility) :"
+msgstr "然后，您需要添加从端和主端之间的互连矩阵（这展现可见性）："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:446
+msgid ""
+"Then to reduce combinatorial path length and have a good design FMax, you "
+"can ask the factory to insert pipelining stages between itself a given "
+"master or slave :"
+msgstr "然后，为了减少组合路径长度并拥有良好的设计FMax，您可以要求生成器在给定的主端"
+"或从端之间插入流水线级："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst
+msgid ""
+"``halfPipe`` / >> / << / >/->  in the following code are provided by the "
+"Stream bus library."
+msgstr "以下代码中的 ``halfPipe`` / >> / << / >/-> 由反压流(Stream)总线库提供。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst
+msgid ""
+"Some documentation could be find :ref:`there <stream>`. In short, it's just "
+"some pipelining and interconnection stuff."
+msgstr "可以在 :ref:`这里 <stream>` "
+"找到一些文档。简而言之，这只是一些流水线和互连的东西。"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:473
+msgid ""
+"The interconnection between the APB3 bridge and all peripherals is done via "
+"an APB3Decoder :"
+msgstr "APB3桥和所有外设之间的互连是通过APB3Decoder完成的："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:490
+msgid "Misc"
+msgstr "杂项"
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:492
+msgid ""
+"To connect all toplevel IO to components, the following code is required :"
+msgstr "要将所有顶层IO连接到组件，需要以下代码："
+
+#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:503
+msgid ""
+"And finally some connections between components are required like interrupts"
+" and core debug module resets"
+msgstr "最后需要组件之间的一些连接，例如中断和核心调试模块复位"
+
+#~ msgid "Systems clock domains"
+#~ msgstr "系统时钟域"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/index.po
new file mode 100644
index 00000000000..18baf82590e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacypinsecindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/index.rst:3
+msgid "pinsec"
+msgstr "pinsec"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po
new file mode 100644
index 00000000000..5f24e57df42
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po
@@ -0,0 +1,122 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacypinsecintroduction/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:7
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:15
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10
+msgid ""
+"This page only documents the SoC implemented with the first generation of "
+"RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV "
+"CPU, which is the second generation of this SoC (and CPU) is available `here"
+" <https://github.com/SpinalHDL/VexRiscv>`__ and offers better "
+"perforance/area/features."
+msgstr ""
+"本页仅记录使用SpinalHDL创造的第一代用RISC-V CPU实现的SoC。"
+"本页面未记录VexRiscV CPU，这是该 SoC（和 CPU）的第二代，可在 `这里 "
+"<https://github.com/SpinalHDL/VexRiscv>`__ 获得，并提供更好的性能/面积/功能。"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17
+msgid ""
+"Pinsec is the name of a little FPGA SoC fully written in SpinalHDL. Goals of"
+" this project are multiple :"
+msgstr "Pinsec是完全用SpinalHDL编写的一个小型FPGA SoC的名称。该项目有多个目的："
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:20
+msgid ""
+"Prove that SpinalHDL is a viable HDL alternative in non-trivial projects."
+msgstr "证明SpinalHDL是重要项目中可行的HDL替代方案。"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:21
+msgid ""
+"Show advantage of SpinalHDL meta-hardware description capabilities in a "
+"concrete project."
+msgstr "在具体项目中展示SpinalHDL元硬件描述功能的优势。"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:22
+msgid "Provide a fully open source SoC."
+msgstr "提供完全开源的SoC。"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:25
+msgid "Pinsec has followings hardware features:"
+msgstr "Pinsec具有以下硬件特性："
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:28
+msgid "AXI4 interconnect for high speed busses"
+msgstr "用于高速总线的AXI4互连"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:29
+msgid "APB3 interconnect for peripherals"
+msgstr "用于外设的APB3互连"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:30
+msgid ""
+"RISCV CPU with instruction cache, MUL/DIV extension and interrupt controller"
+msgstr "具有指令缓存、MUL/DIV扩展和中断控制器的RISCV CPU"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:31
+msgid "JTAG bridge to load binaries and debug the CPU"
+msgstr "用于加载二进制文件和调试CPU的JTAG桥"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:32
+msgid "SDRAM SDR controller"
+msgstr "SDRAM SDR控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:33
+msgid "On chip ram"
+msgstr "片上内存"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:34
+msgid "One UART controller"
+msgstr "1个UART控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:35
+msgid "One VGA controller"
+msgstr "1个VGA控制器"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:36
+msgid "Some timer module"
+msgstr "一些定时器模块"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:37
+msgid "Some GPIO"
+msgstr "一些GPIO"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:39
+msgid ""
+"The toplevel code explanation could be find :ref:`there "
+"<pinsec_hardware_toplevel>`"
+msgstr "顶层代码的解释可以在 :ref:`这里 <pinsec_hardware_toplevel>` 找到"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:42
+msgid "Board support"
+msgstr "板级支持"
+
+#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:44
+msgid ""
+"A DE1-SOC FPGA project can be find `here "
+"<https://drive.google.com/drive/folders/0B-CqLXDTaMbKOGhIU0JGdHVVSk0?usp=sharing>`__"
+" with some demo binaries."
+msgstr ""
+"DE1-SOC FPGA项目可以在 `这里 <https://drive.google.com/drive/folders/0B-"
+"CqLXDTaMbKOGhIU0JGdHVVSk0?usp=sharing>`__ 找到，其中包含一些二进制文件demo。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/software.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/software.po
new file mode 100644
index 00000000000..ddf6d22ba0f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/software.po
@@ -0,0 +1,93 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacypinsecsoftware/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:5
+msgid "Software"
+msgstr "软件"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:8
+msgid "RISCV tool-chain"
+msgstr "RISCV工具链"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:10
+msgid ""
+"Binaries executed by the CPU can be defined in ASM/C/C++ and compiled by the"
+" GCC RISCV fork. Also, to load binaries and debug the CPU, an OpenOCD fork "
+"and RISCV GDB can be used."
+msgstr ""
+"CPU执行的二进制文件可以用ASM/C/C++定义，并由GCC的RISCV分支进行编译。此外，"
+"为了加载二进制文件并调试 CPU，可以使用OpenOCD分支和RISCV的GDB。"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:12
+msgid ""
+"RISCV tools : `https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-"
+"Status <https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status>`_"
+msgstr ""
+"RISCV工具： `https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status "
+"<https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status>`_"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:13
+msgid ""
+"OpenOCD fork : `https://github.com/Dolu1990/openocd_riscv "
+"<https://github.com/Dolu1990/openocd_riscv>`_"
+msgstr ""
+"OpenOCD分支： `https://github.com/Dolu1990/openocd_riscv <https://github.com/"
+"Dolu1990/openocd_riscv>`_"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:14
+msgid ""
+"Software examples : `https://github.com/Dolu1990/pinsecSoftware "
+"<https://github.com/Dolu1990/pinsecSoftware>`_"
+msgstr ""
+"软件示例： `https://github.com/Dolu1990/pinsecSoftware <https://github.com/"
+"Dolu1990/pinsecSoftware>`_"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:17
+msgid "OpenOCD/GDB/Eclipse  configuration"
+msgstr "OpenOCD/GDB/Eclipse配置"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:19
+msgid ""
+"About the OpenOCD fork, there is the configuration file that could be used "
+"to connect the Pinsec SoC : "
+"`https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg"
+" "
+"<https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg>`_"
+msgstr ""
+"关于OpenOCD分支，这里有一个可用于连接Pinsec SoC的配置文件：`https://github."
+"com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg "
+"<https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/"
+"riscv_spinal.cfg>`_"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:21
+msgid "There is an example of arguments used to run the OpenOCD tool :"
+msgstr "这是一个用于运行OpenOCD工具的参数示例："
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:27
+msgid ""
+"To debug with eclipse, you will need the Zylin plugin and then create an "
+"\"Zynlin embedded debug (native)\"."
+msgstr "要使用eclipse进行调试，您将需要Zylin插件，然后创建一个“Zynlin embedded debug "
+"(native)”。"
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:29
+msgid "Initialize commands :"
+msgstr "初始化命令："
+
+#: ../../source/SpinalHDL/Legacy/pinsec/software.rst:37
+msgid "Run commands :"
+msgstr "运行命令："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po
new file mode 100644
index 00000000000..ed71d1c9733
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po
@@ -0,0 +1,197 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllegacyriscv/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:3
+msgid "RiscV"
+msgstr "RiscV"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:6
+msgid ""
+"This page only documents the first generation of RISC-V CPU created in "
+"SpinalHDL. This page does not document the VexRiscV CPU, which is the second"
+" generation of this CPU and is available `here "
+"<https://github.com/SpinalHDL/VexRiscv>`_ and offers better "
+"performance/area/features."
+msgstr ""
+"本页仅记录在SpinalHDL中创造的第一代RISC-V CPU。本页面未记录VexRiscV "
+"CPU，它是该CPU的第二代，可在 `此处 <https://github.com/SpinalHDL/VexRiscv>` "
+"获取，并提供更好的性能/面积/特性。"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:11
+msgid "Features"
+msgstr "特性"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:13
+msgid "RISC-V CPU"
+msgstr "RISC-V CPU"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:16
+msgid "Pipelined on 5 stages (Fetch Decode Execute0 Execute1 WriteBack)"
+msgstr "5级流水线（获取 解码 执行0 执行1 回写）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:17
+msgid "Multiple branch prediction modes : (disable, static or dynamic)"
+msgstr "多种分支预测模式：（禁用、静态或动态）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:18
+msgid "Data path parameterizable between fully bypassed to fully interlocked"
+msgstr "数据路径可在完全旁路和完全互锁之间进行参数化"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:20
+msgid "Extensions"
+msgstr "扩展"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:23
+msgid "One cycle multiplication"
+msgstr "一周期的乘法"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:24
+msgid "34 cycle division"
+msgstr "34个周期的除法"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:25
+msgid "Iterative shifter (N shift -> N cycles)"
+msgstr "迭代移位器（N次移位 -> N个周期）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:26
+msgid "Single cycle shifter"
+msgstr "单周期移位器"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:27
+msgid "Interruption controller"
+msgstr "中断控制器"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:28
+msgid "Debugging module (with JTAG bridge, openOCD port and GDB)"
+msgstr "调试模块（带有JTAG桥、openOCD端口和GDB）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:29
+msgid "Instruction cache with wrapped burst memory interface, one way"
+msgstr "具有封装的突发内存接口的指令缓存，单向"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:30
+msgid ""
+"Data cache with instructions to evict/flush the whole cache or a given "
+"address, one way"
+msgstr "具有清除/刷新整个缓存或特定地址的指令的数据缓存，单向"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:32
+msgid "Performance/Area (on cyclone II)"
+msgstr "性能/面积（在cyclone II上）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:35
+msgid "small core -> 846 LE, 0.6 DMIPS/Mhz"
+msgstr "小核 -> 846 LE, 0.6 DMIPS/Mhz"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:36
+msgid "debug module (without JTAG) -> 240 LE"
+msgstr "调试模块（无 JTAG）-> 240 LE"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:37
+msgid "JTAG Avalon master -> 238 LE"
+msgstr "JTAG Avalon主控 -> 238 LE"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:38
+msgid ""
+"big core with MUL/DIV/Full shifter/I$/Interrupt/Debug -> 2200 LE, 1.15 "
+"DMIPS/Mhz, at least 100 Mhz (with default synthesis option)"
+msgstr "带MUL/DIV/全移位器/I$/中断/调试的大核 -> 2200 LE，1.15 DMIPS/"
+"Mhz，至少100Mhz（使用默认综合选项）"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:41
+msgid "Base FPGA project"
+msgstr "基础FPGA项目"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:43
+msgid ""
+"You can find a DE1-SOC project which integrate two instance of the CPU with "
+"MUL/DIV/Full shifter/I$/Interrupt/Debug there :"
+msgstr "您可以在这里找到一个DE1-SOC项目，它将两个CPU实例与 MUL/DIV/"
+"全移位器/I$/中断/调试集成在一起："
+
+#: ../../SpinalHDL/Legacy/riscv.rst:45
+msgid ""
+"https://drive.google.com/drive/folders/0B-CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing"
+msgstr ""
+"https://drive.google.com/drive/folders/0B-"
+"CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:47
+msgid "CPU/JTAG/VGA IP are pre-generated. Quartus Prime : 15.1."
+msgstr "CPU/JTAG/VGA IP是预先生成的。 Quartus Prime：15.1。"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:51
+msgid "How to generate the CPU VHDL"
+msgstr "如何生成CPU VHDL"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:54
+msgid ""
+"This avalon version of the CPU isn't present in recent releases of "
+"SpinalHDL. Please consider the `VexRiscv "
+"<https://github.com/SpinalHDL/VexRiscv>`_ instead."
+msgstr ""
+"最近版本的SpinalHDL中不存在该Avalon版本的CPU。请考虑使用 `VexRiscv "
+"<https://github.com/SpinalHDL/VexRiscv>`_ 。"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:63
+msgid "How to debug"
+msgstr "如何调试"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:65
+msgid "You can find the openOCD fork here :"
+msgstr "你可以在这里找到openOCD分支："
+
+#: ../../SpinalHDL/Legacy/riscv.rst:67
+msgid "https://github.com/Dolu1990/openocd_riscv"
+msgstr "https://github.com/Dolu1990/openocd_riscv"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:69
+msgid "An example target configuration file could be find here :"
+msgstr "可以在此处找到示例目标配置文件："
+
+#: ../../SpinalHDL/Legacy/riscv.rst:71
+msgid ""
+"https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg"
+msgstr ""
+"https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/"
+"riscv_spinal.cfg"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:73
+msgid "Then you can use the RISCV GDB."
+msgstr "然后就可以使用RISCV GDB了。"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:76
+msgid "Todo"
+msgstr "Todo"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:79
+msgid "Documentation"
+msgstr "文档"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:80
+msgid ""
+"Optimise instruction/data caches FMax by moving line hit condition forward "
+"into combinatorial paths."
+msgstr "通过将行命中条件向前移动到组合路径来优化指令/数据缓存FMax。"
+
+#: ../../SpinalHDL/Legacy/riscv.rst:82
+msgid "Contact spinalhdl@gmail.com for more information"
+msgstr "联系spinhdl@gmail.com了解更多信息"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po
new file mode 100644
index 00000000000..fee0b97a17a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po
@@ -0,0 +1,92 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbusamba3ahblite3/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:3
+msgid "AHB-Lite3"
+msgstr "AHB-Lite3"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6
+msgid "Configuration and instanciation"
+msgstr "配置和实例化"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8
+msgid ""
+"First each time you want to create a AHB-Lite3 bus, you will need a "
+"configuration object. This configuration object is an ``AhbLite3Config`` and"
+" has following arguments :"
+msgstr "首先，每当您想要创建AHB-Lite3总线时，您都需要一个配置对象。该配置对象是一个 "
+"``AhbLite3Config`` 并具有以下参数："
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:14
+msgid "Parameter name"
+msgstr "参数名称"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:15
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:16
+msgid "Default"
+msgstr "默认值"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:17
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:18
+msgid "addressWidth"
+msgstr "addressWidth"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:19
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:23
+msgid "Int"
+msgstr "Int"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:21
+msgid "Width of HADDR (byte granularity)"
+msgstr "HADDR的位宽（字节粒度）"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:22
+msgid "dataWidth"
+msgstr "dataWidth"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:25
+msgid "Width of HWDATA and HRDATA"
+msgstr "HWDATA和HRDATA的位宽"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:28
+msgid ""
+"There is in short how the AHB-Lite3 bus is defined in the SpinalHDL library "
+":"
+msgstr "简而言之，AHB-Lite3总线在SpinalHDL库中是如下定义的："
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:58
+msgid "There is a short example of usage :"
+msgstr "这是一个简单的使用示例："
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:74
+msgid "Variations"
+msgstr "变体"
+
+#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:76
+msgid ""
+"There is an AhbLite3Master variation. The only difference is the absence of "
+"the ``HREADYOUT`` signal. This variation should only be used by masters "
+"while the interconnect and slaves use ``AhbLite3``."
+msgstr ""
+"有一个AhbLite3Master变体，唯一的区别是缺少 ``HREADYOUT`` 信号。"
+"当互连线和从端使用 ``AhbLite3`` 时，此变体只能由主端使用。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po
new file mode 100644
index 00000000000..0835437ef7b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po
@@ -0,0 +1,148 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbusamba3apb3/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:3
+msgid "Apb3"
+msgstr "Apb3"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:5
+msgid ""
+"The AMBA3-APB bus is commonly used to interface low bandwidth peripherals."
+msgstr "AMBA3-APB总线通常用于连接低带宽外设。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8
+msgid "Configuration and instanciation"
+msgstr "配置和实例化"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:10
+msgid ""
+"First each time you want to create a APB3 bus, you will need a configuration"
+" object. This configuration object is an ``Apb3Config`` and has following "
+"arguments :"
+msgstr "首先，每当您想要创建APB3总线时，您都需要一个配置对象。该配置对象是一个 "
+"``Apb3Config`` 并具有以下参数："
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:16
+msgid "Parameter name"
+msgstr "参数名称"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:17
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:18
+msgid "Default"
+msgstr "默认值"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:19
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:78
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:20
+msgid "addressWidth"
+msgstr "addressWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:21
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:25
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:29
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:23
+msgid "Width of PADDR (byte granularity)"
+msgstr "PADDR的位宽（字节粒度）"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:24
+msgid "dataWidth"
+msgstr "dataWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:27
+msgid "Width of PWDATA and PRDATA"
+msgstr "PWDATA和PRDATA的位宽"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:28
+msgid "selWidth"
+msgstr "selWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:30
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:31
+msgid "With of PSEL"
+msgstr "PSEL的位宽"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:32
+msgid "useSlaveError"
+msgstr "useSlaveError"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:33
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:34
+msgid "false"
+msgstr "false"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:35
+msgid "Specify the presence of PSLVERROR"
+msgstr "指定是否出现PSLVERROR"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:38
+msgid ""
+"There is in short how the APB3 bus is defined in the SpinalHDL library :"
+msgstr "简而言之，APB3总线在SpinalHDL库中定义方式如下："
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:54
+msgid "There is a short example of usage :"
+msgstr "这是一个简单的使用示例："
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:70
+msgid "Functions and operators"
+msgstr "函数和运算符"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:76
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:77
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:79
+msgid "X >> Y"
+msgstr "X >> Y"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:81
+msgid "Connect X to Y. Address of Y could be smaller than the one of X"
+msgstr "将X连接到Y。Y的地址可以小于X的地址"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:82
+msgid "X << Y"
+msgstr "X << Y"
+
+#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:84
+msgid "Do the reverse of the >> operator"
+msgstr "执行>>运算符相反的操作"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po
new file mode 100644
index 00000000000..b676fef5dbf
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po
@@ -0,0 +1,281 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbusamba4axi4/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:2
+msgid "Axi4"
+msgstr "Axi4"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:4
+msgid "The AXI4 is a high bandwidth bus defined by ARM."
+msgstr "AXI4是ARM定义的高带宽总线。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7
+msgid "Configuration and instanciation"
+msgstr "配置和实例化"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:9
+msgid ""
+"First each time you want to create a AXI4 bus, you will need a configuration"
+" object. This configuration object is an ``Axi4Config`` and has following "
+"arguments :"
+msgstr "首先，每当您想要创建AXI4总线时，您都需要一个配置对象。该配置对象是一个 "
+"``Axi4Config`` 并具有以下参数："
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:11
+msgid "Note : useXXX specify if the bus has XXX signal present."
+msgstr "注意：useXXX用于指定总线是否存在XXX信号。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:16
+msgid "Parameter name"
+msgstr "参数名称"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:17
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:114
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:18
+msgid "Default"
+msgstr "默认值"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:19
+msgid "addressWidth"
+msgstr "addressWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:20
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:23
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:26
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:29
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:22
+msgid "dataWidth"
+msgstr "dataWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:25
+msgid "idWidth"
+msgstr "idWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:28
+msgid "userWidth"
+msgstr "userWidth"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:31
+msgid "useId"
+msgstr "useId"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:32
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:35
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:38
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:41
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:44
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:47
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:50
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:53
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:56
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:59
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:62
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:65
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:68
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:33
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:36
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:39
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:42
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:45
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:48
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:51
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:54
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:57
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:60
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:63
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:66
+msgid "true"
+msgstr "true"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:34
+msgid "useRegion"
+msgstr "useRegion"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:37
+msgid "useBurst"
+msgstr "useBurst"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:40
+msgid "useLock"
+msgstr "useLock"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:43
+msgid "useCache"
+msgstr "useCache"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:46
+msgid "useSize"
+msgstr "useSize"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:49
+msgid "useQos"
+msgstr "useQos"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:52
+msgid "useLen"
+msgstr "useLen"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:55
+msgid "useLast"
+msgstr "useLast"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:58
+msgid "useResp"
+msgstr "useResp"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:61
+msgid "useProt"
+msgstr "useProt"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:64
+msgid "useStrb"
+msgstr "useStrb"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:67
+msgid "useUser"
+msgstr "useUser"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:69
+msgid "false"
+msgstr "false"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:72
+msgid ""
+"There is in short how the AXI4 bus is defined in the SpinalHDL library :"
+msgstr "简而言之，AXI4总线在SpinalHDL库中定义方式如下："
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:89
+msgid "There is a short example of usage :"
+msgstr "这是一个简单的使用示例："
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:106
+msgid "Variations"
+msgstr "变体"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:108
+msgid "There is 3 other variation of the Axi4 bus :"
+msgstr "Axi4总线还有其他3种变体："
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:115
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:136
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:116
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:147
+msgid "Axi4ReadOnly"
+msgstr "Axi4ReadOnly"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:117
+msgid "Only AR and R channels are present"
+msgstr "只存在AR和R通道"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:118
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:144
+msgid "Axi4WriteOnly"
+msgstr "Axi4WriteOnly"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:119
+msgid "Only AW, W and B channels are present"
+msgstr "只存在AW、W和B通道"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:120
+msgid "Axi4Shared"
+msgstr "Axi4Shared"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst
+msgid "This variation is a library initiative."
+msgstr "此变体是该库的首创。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst
+msgid "It use 4 channels, W, B ,R and also a new one which is named AWR."
+msgstr "它使用4个通道，W、B、R，还有一个新通道，称为AWR。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst
+msgid ""
+"The AWR channel can be used to transmit AR and AW transactions. To "
+"dissociate them, a signal ``write`` is present."
+msgstr "AWR通道可用于传输AR和AW事务。为了分离它们，需要一个 ``write`` 信号。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst
+msgid ""
+"The advantage of this Axi4Shared variation is to use less area, especially "
+"in the interconnect."
+msgstr "这种Axi4Shared变体的优点是使用更少的面积，特别是在互连方面。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:128
+msgid "Functions and operators"
+msgstr "函数和运算符"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:134
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:135
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:137
+msgid "X >> Y"
+msgstr "X >> Y"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:139
+msgid ""
+"Connect X to Y. Able infer default values as specified in the AXI4 "
+"specification, and also to adapt some width in a safe manner."
+msgstr "将X连接到Y。能够像AXI4规范中指定的那样推断默认值，并以安全的方式调整一些位宽"
+"。"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:140
+msgid "X << Y"
+msgstr "X << Y"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:142
+msgid "Do the reverse of the >> operator"
+msgstr "执行>>运算符相反的操作"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:143
+msgid "X.toWriteOnly"
+msgstr "X.toWriteOnly"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:145
+msgid "Return an Axi4WriteOnly bus drive by X"
+msgstr "返回由X驱动的Axi4WriteOnly总线"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:146
+msgid "X.toReadOnly"
+msgstr "X.toReadOnly"
+
+#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:148
+msgid "Return an Axi4ReadOnly bus drive by X"
+msgstr "返回由X驱动的Axi4ReadOnly总线"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po
new file mode 100644
index 00000000000..78f0fa66f87
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po
@@ -0,0 +1,140 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbusavalonavalonmm/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:3
+msgid "AvalonMM"
+msgstr "AvalonMM"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:5
+msgid "The AvalonMM bus fit very well in FPGA. It is very flexible :"
+msgstr "AvalonMM总线非常适合FPGA。它非常灵活："
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:7
+msgid "Able of the same simplicity than APB"
+msgstr "能够与APB一样简单"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:8
+msgid ""
+"Better for than AHB in many application that need bandwidth because AvalonMM"
+" has a mode that decouple read response from commands (reduce latency read "
+"latency impact)."
+msgstr "在许多需要带宽的应用中比AHB更好，因为AvalonMM有一种将读取响应与命令解耦的模式"
+"（减少延迟读延迟的影响）。"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:9
+msgid ""
+"Less performance than AXI but use much less area (Read and write command use"
+" the same handshake channel. The master don't need to store address of "
+"pending request to avoid Read/Write hazard)"
+msgstr "性能不如AXI，但使用的逻辑面积少得多（读取和写入命令使用相同的握手通道。主端不"
+"需要存储挂起请求的地址，从而避免读取/写入冒险）"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:12
+msgid "Configuration and instanciation"
+msgstr "配置和实例化"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:14
+msgid ""
+"The ``AvalonMM`` Bundle has a construction argument ``AvalonMMConfig``. "
+"Because of the flexible nature of the Avalon bus, the ``AvalonMMConfig`` as "
+"many configuration elements. For more information the Avalon spec could be "
+"find on the intel website."
+msgstr ""
+"``AvalonMM`` 包有一个构造参数 ``AvalonMMConfig`` 。由于Avalon总线的灵活性， "
+"``AvalonMMConfig`` "
+"有很多配置元素。有关Avalon规范的更多信息，请访问英特尔网站。"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:46
+msgid "This configuration class has also some functions :"
+msgstr "这个配置类还有一些函数："
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:52
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:69
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:53
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:70
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:54
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:71
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:55
+msgid "getReadOnlyConfig"
+msgstr "getReadOnlyConfig"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:56
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:59
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:73
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:76
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:79
+msgid "AvalonMMConfig"
+msgstr "AvalonMMConfig"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:57
+msgid "Return a similar configuration but with all write feature disabled"
+msgstr "返回一个类似的配置，但禁用所有写入属性"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:58
+msgid "getWriteOnlyConfig"
+msgstr "getWriteOnlyConfig"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:60
+msgid "Return a similar configuration but with all read feature disabled"
+msgstr "返回一个类似的配置，但禁用所有读取属性"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:63
+msgid ""
+"This configuration companion object has also some functions to provide some "
+"``AvalonMMConfig`` templates :"
+msgstr "这个配置伴随对象还有一些函数来提供一些 ``AvalonMMConfig`` 模板："
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:72
+msgid "fixed(addressWidth,dataWidth,readLatency)"
+msgstr "fixed(addressWidth,dataWidth,readLatency)"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:74
+msgid "Return a simple configuration with fixed read timings"
+msgstr "返回一个具有固定读取时间的简单配置"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:75
+msgid "pipelined(addressWidth,dataWidth)"
+msgstr "pipelined(addressWidth,dataWidth)"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:77
+msgid "Return a configuration with variable latency read (readDataValid)"
+msgstr "返回一个具有可变延迟读取的配置 (readDataValid)"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:78
+msgid "bursted(addressWidth,dataWidth,burstCountWidth)"
+msgstr "bursted(addressWidth,dataWidth,burstCountWidth)"
+
+#: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:80
+msgid ""
+"Return a configuration with variable latency read and burst capabilities"
+msgstr "返回一个具有可变延迟读取和突发功能的配置"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/index.po
new file mode 100644
index 00000000000..3930962f42f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-19 09:19+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbusindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Libraries/Bus/index.rst:3
+msgid "Bus"
+msgstr "总线"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po
new file mode 100644
index 00000000000..3e92fd6af10
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po
@@ -0,0 +1,45 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbustilelinktilelink/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:3
+msgid "Tilelink"
+msgstr "Tilelink"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:6
+msgid "Configuration and instanciation"
+msgstr "配置和实例化"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:8
+msgid ""
+"There is a short example to define two non coherent tilelink bus instance "
+"and connect them:"
+msgstr "这是一个简单的示例，它定义了两个不相干的tilelink总线实例并将它们连接起来："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:22
+msgid "Here is the same as above, but with coherency channels"
+msgstr "这里与上面相同，但是具有一致性通道"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:43
+msgid ""
+"Those above where for the hardware instanciation, the thing is that it is "
+"the simple / easy part. When things goes into SoC / memory coherency, you "
+"kind of need an additional layer to negociate / propagate parameters all "
+"around. That's what tilelink.fabric.Node is about."
+msgstr ""
+"以上的内容是关于硬件实例化的，这是简单/容易的部分。当涉及SoC/"
+"内存一致性时，您可能需要一个额外的层来协调/传递参数。这就是tilelink.fabric."
+"Node的作用。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po
new file mode 100644
index 00000000000..1649b147dcc
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po
@@ -0,0 +1,230 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbustilelinktilelink_fabric/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:3
+msgid "tilelink.fabric.Node"
+msgstr "tilelink.fabric.Node"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:5
+msgid ""
+"tilelink.fabric.Node is an additional layer over the regular tilelink "
+"hardware instanciation which handle negociation and parameters propagation "
+"at a SoC level."
+msgstr "tilelink.fabric."
+"Node是常规tilelink硬件实例之上的附加层，用于处理SoC级别的协调和参数传递。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:7
+msgid ""
+"It is mostly based on the Fiber API, which allows to create elaboration time"
+" fibers (user-space threads), allowing to schedule future parameter "
+"propagation / negociation and hardware elaboration."
+msgstr "它主要基于Fiber API，它允许创建精化时间纤程（用户空间线程），从而允许确定未来"
+"的参数传递/协调和硬件生成。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:9
+msgid "A Node can be created in 3 ways :"
+msgstr "可以通过3种方式创建节点(Node)："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:11
+msgid ""
+"tilelink.fabric.Node.down() : To create a node which can connect downward "
+"(toward slaves), so it would be used in a CPU / DMA / bridges agents"
+msgstr "tilelink.fabric.Node."
+"down()：创建一个可以向下连接（向从端）的节点，因此它将用于CPU/DMA/桥的代理"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:12
+msgid "tilelink.fabric.Node() : To create an intermediate nodes"
+msgstr "tilelink.fabric.Node()：创建中间节点"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:13
+msgid ""
+"tilelink.fabric.Node.up() : To create a node which can connect upward "
+"(toward masters), so it would be used in peripherals / memories / bridges "
+"agents"
+msgstr "tilelink.fabric.Node."
+"up()：创建一个可以向上连接（向主端）的节点，因此它将用于外设/存储器/桥的代理"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:15
+msgid "Nodes mostly have the following attributes :"
+msgstr "节点大多具有以下属性："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:17
+msgid "bus : Handle[tilelink.Bus]; the hardware instance of the bus"
+msgstr "bus : Handle[tilelink.Bus]；总线的硬件实例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:18
+msgid ""
+"m2s.proposed : Handle[tilelink.M2sSupport]; The set of features which is "
+"proposed by the upward connections"
+msgstr "m2s.proposed : Handle[tilelink.M2sSupport]；由向上连接提出的功能集"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:19
+msgid ""
+"m2s.supported : Handle[tilelink.M2sSupport] : The set of feature supported "
+"by the downward connections"
+msgstr "m2s.supported : Handle[tilelink.M2sSupport]: 向下连接支持的功能集"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:20
+msgid ""
+"m2s.parameter : Handle[tilelink.M2sParameter] : The final bus parameter"
+msgstr "m2s.parameter : Handle[tilelink.M2sParameter]: 最终的总线参数"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:22
+msgid ""
+"You can note that they all are Handles. Handle is a way in SpinalHDL to have"
+" share a value between fibers. If a fiber read a Handle while this one has "
+"no value yet, it will block the execution of that fiber until another fiber "
+"provide a value to the Handle."
+msgstr ""
+"您可以注意到它们都是句柄。Handle是SpinalHDL中在纤程之间共享值的一种方式。如果"
+"一个纤程读取一个句柄，而这个句柄还没有值，它将阻止该纤程的执行，直到另一个纤"
+"程向该句柄提供一个值。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:24
+msgid ""
+"There is also a set of attribues like m2s, but reversed (named s2m) which "
+"specify the parameters for the transactions initiated by the slave side of "
+"the interconnect (ex memory coherency)."
+msgstr "还有一组属性，类似于m2s，但是反向的（名为s2m），它们指定了由互连的从端发起的"
+"事务的参数（例如内存一致性）。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:26
+msgid ""
+"There is two talks which where introducing the tilelink.fabric.Node. Those "
+"talk may not exactly follow the actual syntax, they are still follow the "
+"concepts :"
+msgstr "有两个演讲介绍了tilelink.fabric."
+"Node。这两个演讲可能并不完全遵循实际语法，它们仍然遵循以下概念："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:28
+msgid "Introduction : https://youtu.be/hVi9xOGuuek"
+msgstr "介绍：https://youtu.be/hVi9xOGuuek"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:29
+msgid ""
+"In depth : "
+"https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-96d7eb89e907"
+msgstr ""
+"深入：https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-"
+"96d7eb89e907"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:32
+msgid "Example Toplevel"
+msgstr "顶层示例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:34
+msgid "Here is an example of a simple fictive SoC toplevel :"
+msgstr "以下是一个简单的虚拟SoC顶层设计示例："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:46
+msgid ""
+"You can also define intermediate nodes in the interconnect as following :"
+msgstr "您还可以定义互连中的中间节点，如下所示："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:70
+msgid "Example GpioFiber"
+msgstr "GPIOFiber示例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:72
+msgid ""
+"GpioFiber is a simple tilelink peripheral which can read / drive a 32 bits "
+"tristate array."
+msgstr "GpioFiber是一个简单的tilelink外设，可以读取/驱动32位三态阵列。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:116
+msgid "Example RamFiber"
+msgstr "RamFiber示例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:118
+msgid "RamFiber is the integration layer of a regular tilelink Ram component."
+msgstr "RamFiber是常规tilelink Ram组件的集成层。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:146
+msgid "Example CpuFiber"
+msgstr "CpuFiber示例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:148
+msgid "CpuFiber is an fictive example of a master integration."
+msgstr "CpuFiber是一个虚拟的主端集成的示例。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:195
+msgid ""
+"One particularity of Tilelink, is that it assumes a master will not emit "
+"requests to a unmapped memory space. To allow a master to identify what "
+"memory access it is allowed to do, you can use the "
+"spinal.lib.system.tag.MemoryConnection.getMemoryTransfers tool as following "
+":"
+msgstr ""
+"Tilelink的一个特殊性是，它假设主端不会向未映射的内存空间发出请求。为了让主机"
+"识别允许访问哪些内存，您可以使用spinal.lib.system.tag.MemoryConnection."
+"getMemoryTransfers工具，如下所示："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:206
+msgid "If you run this in the Cpu's fiber, in the following soc :"
+msgstr "如果您在CPU的纤程中运行此命令，在下面的soc中："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:228
+msgid "You will get :"
+msgstr "你会得到 ："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:236
+msgid ""
+"\"through=\" specify the chain of address transformations done to reach the "
+"target."
+msgstr "\"through=\" 指定了到达目标所需的地址转换链。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:237
+msgid "\"SM\" means SizeMapping(address, size)"
+msgstr "\"SM\" 表示SizeMapping(address, size)"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:238
+msgid "\"OT\" means OffsetTransformer(offset)"
+msgstr "\"OT\" 表示OffsetTransformer(offset)"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:240
+msgid ""
+"Note that you can also add PMA (Physical Memory Attributes) to nodes and "
+"retreives them via this getMemoryTransfers utilities."
+msgstr "请注意，您还可以将PMA（物理内存属性）添加到节点，并通过此getMemoryTransfers工"
+"具检索它们。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:242
+msgid "The currently defined PMA are :"
+msgstr "当前PMA的定义是："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:258
+msgid "The getMemoryTransfers utility rely on a dedicated SpinalTag :"
+msgstr "getMemoryTransfers工具依赖于专用的SpinalTag："
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:270
+msgid ""
+"That SpinalTag can be used applied to both ends of a given memory bus "
+"connection to keep this connection discoverable at elaboration time, "
+"creating a graph of MemoryConnection. One good thing about it is that is is "
+"bus agnostic, meaning it isn't tilelink specific."
+msgstr ""
+"该SpinalTag可以应用于给定内存总线连接的两端，以保持该连接在生成时可被发现，从"
+"而创建内存连接(MemoryConnection)图。它的一个优点是它与总线无关，这意味着它不"
+"是tilelink特有的。"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:274
+msgid "Example WidthAdapter"
+msgstr "位宽适配器(WidthAdapter)示例"
+
+#: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:276
+msgid "The width adapter is a simple example of bridge."
+msgstr "位宽适配器是桥的一个简单例子。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/index.po
new file mode 100644
index 00000000000..a3c58e3eb30
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariescomindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Com/index.rst:3
+msgid "Com"
+msgstr "通信接口"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/spiXdr.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/spiXdr.po
new file mode 100644
index 00000000000..d1523d8d32e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/spiXdr.po
@@ -0,0 +1,78 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2024.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariescomspixdr/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:3
+msgid "SPI XDR"
+msgstr "SPI XDR"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:5
+msgid "There is a SPI controller which support :"
+msgstr "这是一个SPI控制器，它支持："
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:7
+msgid "half/full duplex"
+msgstr "半双工/全双工"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:8
+msgid "single/dual/quad SPI"
+msgstr "单线/双线/四线 SPI"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:9
+msgid "SDR/DDR/.. data rate"
+msgstr "SDR/DDR/.. 数据速率"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:12
+msgid "You can find its APB3 implementation here :"
+msgstr "您可以在此处找到其APB3实现："
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:14
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/68b6158700fc2440ea7980406f927262c004faca/lib/src/main/scala/spinal/lib/com/spi/xdr/Apb3SpiXdrMasterCtrl.scala#L43"
+msgstr ""
+"https://github.com/SpinalHDL/SpinalHDL/blob/"
+"68b6158700fc2440ea7980406f927262c004faca/lib/src/main/scala/spinal/lib/com/"
+"spi/xdr/Apb3SpiXdrMasterCtrl.scala#L43"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:17
+msgid "Configuration"
+msgstr "配置"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:19
+msgid "Here is an example."
+msgstr "这是一个示例。"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:50
+msgid "Software Driver"
+msgstr "软件驱动"
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:52
+msgid "See :"
+msgstr "看："
+
+#: ../../SpinalHDL/Libraries/Com/spiXdr.rst:54
+msgid ""
+"https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/spi.h"
+" "
+"https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/spiDemo/src/main.c"
+msgstr ""
+"https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/"
+"driver/spi.h https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/"
+"standalone/spiDemo/src/main.c"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/uart.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/uart.po
new file mode 100644
index 00000000000..56c861c4949
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/uart.po
@@ -0,0 +1,194 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariescomuart/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:3
+msgid "UART"
+msgstr "串口"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:5
+msgid ""
+"The UART protocol could be used, for instance, to emit and receive RS232 / "
+"RS485 frames."
+msgstr "例如，UART协议可用于发送和接收RS232/RS485帧。"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:7
+msgid ""
+"There is an example of an 8 bits frame, with no parity and one stop bit :"
+msgstr "有一个8位帧的示例，无奇偶校验和一位停止位："
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:12
+msgid "Bus definition"
+msgstr "总线定义"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:27
+msgid "UartCtrl"
+msgstr "UartCtrl"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:29
+msgid ""
+"An Uart controller is implemented in the library. This controller has the "
+"specificity to use a sampling window to read the ``rxd`` pin and then to "
+"using an majority vote to filter its value."
+msgstr "库中实现了Uart控制器。该控制器的特性是使用一个采样窗口读取 ``rxd`` "
+"引脚，然后使用多数投票制来过滤其值。"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:35
+msgid "IO name"
+msgstr "IO名称"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:36
+msgid "direction"
+msgstr "方向"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:37
+#: ../../SpinalHDL/Libraries/Com/uart.rst:64
+msgid "type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:38
+#: ../../SpinalHDL/Libraries/Com/uart.rst:65
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:39
+msgid "config"
+msgstr "config"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:40
+msgid "in"
+msgstr "in"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:41
+msgid "UartCtrlConfig"
+msgstr "UartCtrlConfig"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:42
+msgid ""
+"Used to set the clock divider/parity/stop/data length of the controller"
+msgstr "用于设置控制器的时钟分频器/奇偶校验/停止/数据长度"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:43
+msgid "write"
+msgstr "write"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:44
+msgid "slave"
+msgstr "slave"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:45
+msgid "Stream[Bits]"
+msgstr "Stream[Bits]"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:46
+msgid "Stream port used to request a frame transmission"
+msgstr "用于请求帧传输的反压流端口"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:47
+msgid "read"
+msgstr "read"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:48
+#: ../../SpinalHDL/Libraries/Com/uart.rst:52
+msgid "master"
+msgstr "master"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:49
+msgid "Flow[Bits]"
+msgstr "Flow[Bits]"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:50
+msgid "Flow port used to receive decoded frames"
+msgstr "用于接收解码帧的流端口"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:51
+msgid "uart"
+msgstr "uart"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:53
+msgid "Uart"
+msgstr "Uart"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:54
+msgid "Interface to the real world"
+msgstr "与实际实现的连接接口"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:57
+msgid ""
+"The controller could be instantiated via an ``UartCtrlGenerics`` "
+"configuration object :"
+msgstr "控制器可以通过一个 ``UartCtrlGenerics`` 配置对象来实例化："
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:63
+msgid "Attribute"
+msgstr "属性"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:66
+msgid "dataWidthMax"
+msgstr "dataWidthMax"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:67
+#: ../../SpinalHDL/Libraries/Com/uart.rst:70
+#: ../../SpinalHDL/Libraries/Com/uart.rst:73
+#: ../../SpinalHDL/Libraries/Com/uart.rst:76
+#: ../../SpinalHDL/Libraries/Com/uart.rst:79
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:68
+msgid "Maximal number of bit inside a frame"
+msgstr "帧内最大位数"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:69
+msgid "clockDividerWidth"
+msgstr "clockDividerWidth"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:71
+msgid "Width of the internal clock divider"
+msgstr "内部时钟分频器的位宽"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:72
+msgid "preSamplingSize"
+msgstr "preSamplingSize"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:74
+msgid "Specify how many samplingTick are drop at the beginning of a UART baud"
+msgstr "指定在一个UART波特开始时丢弃多少samplingTick"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:75
+msgid "samplingSize"
+msgstr "samplingSize"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:77
+msgid ""
+"Specify how many samplingTick are used to sample ``rxd`` values in the "
+"middle of the UART baud"
+msgstr "指定有多少samplingTick用于采样UART波特中段的 ``rxd`` 值"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:78
+msgid "postSamplingSize"
+msgstr "postSamplingSize"
+
+#: ../../SpinalHDL/Libraries/Com/uart.rst:80
+msgid "Specify how many samplingTick are drop at the end of a UART baud"
+msgstr "指定在UART波特结束时丢弃多少个samplingTick"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po
new file mode 100644
index 00000000000..33b54dc2f0e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po
@@ -0,0 +1,754 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariescomusb_device/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:3
+msgid "USB device"
+msgstr "USB设备"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:5
+msgid "Here exists a USB device controller in the SpinalHDL library."
+msgstr "SpinalHDL库中存在一个USB设备控制器。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:7
+msgid "A few bullet points to summarise support:"
+msgstr "用几个要点总结支持的功能："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:9
+msgid "Implemented to allow a CPU to configure and manage the endpoints"
+msgstr "实现了允许CPU配置和管理端点"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:10
+msgid ""
+"A internal ram which store the endpoints states and transactions descriptors"
+msgstr "存储端点状态和事务描述符的内部RAM"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:11
+msgid "Up to 16 endpoints (for virtualy no price)"
+msgstr "多达6个端点（几乎没有额外开销）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:12
+msgid "Support USB host full speed (12Mbps)"
+msgstr "支持全速USB主机（12Mbps）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:13
+msgid ""
+"Test on linux using its own driver "
+"(https://github.com/SpinalHDL/linux/blob/dev/drivers/usb/gadget/udc/spinal_udc.c)"
+msgstr ""
+"在Linux上使用自己的驱动程序进行测试(https://github.com/SpinalHDL/linux/blob/"
+"dev/drivers/usb/gadget/udc/spinal_udc.c)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:14
+msgid "Bmb memory interace for the configuration"
+msgstr "用于配置的Bmb内存接口"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:15
+msgid ""
+"Require a clock for the internal phy which is a multiple of 12 Mhz at least "
+"48 Mhz"
+msgstr "内部物理层需要一个时钟，该时钟需为12 Mhz的倍数，至少48 Mhz"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:16
+msgid "The controller frequency is not restricted"
+msgstr "控制器频率不受限制"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:17
+msgid "No external phy required"
+msgstr "无需外部物理层"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:19
+msgid "Linux gadget tested and functional :"
+msgstr "Linux小工具经过测试且功能正常："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:21
+msgid "Serial connection"
+msgstr "串行连接"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:22
+msgid "Ethernet connection"
+msgstr "以太网连接"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:23
+msgid "Mass storage (~8 Mbps on ArtyA7 linux)"
+msgstr "大容量存储（ArtyA7 Linux上约为8 Mbps）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:25
+msgid "Deployments :"
+msgstr "部署："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:27
+msgid ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux"
+msgstr ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/"
+"ArtyA7SmpLinux"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:28
+msgid ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+msgstr ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:32
+msgid "Architecture"
+msgstr "架构"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:34
+msgid "The controller is composed of :"
+msgstr "控制器由以下部分组成："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:36
+msgid "A few control registers"
+msgstr "一小部分控制寄存器"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:37
+msgid ""
+"A internal ram used to store the endpoint status, the transfer descriptors "
+"and the endpoint 0 SETUP data."
+msgstr "一个用于存储端点状态、传输描述符和端点0配置数据的内部RAM。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:39
+msgid ""
+"A linked list of descriptors for each endpoint in order to handle the USB "
+"IN/OUT transactions and data."
+msgstr "每个端点的描述符链表时用于处理USB出入(IN/OUT)事务和数据。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:41
+msgid ""
+"The endpoint 0 manage the IN/OUT transactions like all the other endpoints "
+"but has some additional hardware to manage the SETUP transactions :"
+msgstr "端点0也像所有其他端点一样管理出入USB的传输事务，但也会有一些额外的硬件来管理"
+"设置(SETUP)事务："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:43
+msgid "Its linked list is cleared on each setup transactions"
+msgstr "它的链表在每次设置事务时都会被清除"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:44
+msgid ""
+"The data from the SETUP transaction is stored in a fixed location "
+"(SETUP_DATA)"
+msgstr "来自设置(SETUP)事务的数据存储在固定位置(SETUP_DATA)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:45
+msgid "It has a specific interrupt flag for SETUP transactions"
+msgstr "它有一个用于设置(SETUP)事务的特定中断标志"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:48
+msgid "Registers"
+msgstr "寄存器"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:50
+msgid ""
+"Note that all registers and memories of the controller are only accessible "
+"in 32 bits word access, bytes access isn't supported."
+msgstr "请注意，控制器的所有寄存器和存储器只能以32位字的访问方式进行访问，不支持字节"
+"访问。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:53
+msgid "FRAME (0xFF00)"
+msgstr "帧FRAME (0xFF00)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Bits"
+msgstr "位"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:56
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:66
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:88
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:110
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:124
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:139
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:150
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "usbFrameId"
+msgstr "usbFrameId"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "RO"
+msgstr "RO"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "31-0"
+msgstr "31-0"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:58
+msgid "Current usb frame id"
+msgstr "当前USB帧的ID"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:63
+msgid "ADDRESS (0xFF04)"
+msgstr "地址ADDRESS (0xFF04)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid "address"
+msgstr "address"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "WO"
+msgstr "WO"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid "6-0"
+msgstr "6-0"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:68
+msgid ""
+"The device will only listen at tokens with the specified address This field "
+"is automaticaly cleared on usb reset events"
+msgstr "设备将仅侦听具有指定地址的令牌，该字段在USB复位事件发生时自动清除"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+msgid "enable"
+msgstr "enable"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+msgid "8"
+msgstr "8"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:71
+msgid "Enable the USB address filtering if set"
+msgstr "如果置1，启用USB地址过滤"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid "trigger"
+msgstr "trigger"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid "9"
+msgstr "9"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:73
+msgid ""
+"Set the enable (see above) on the next EP0 IN tocken completion Cleared by "
+"the hardware after any EP0 completion"
+msgstr "在下一个EP0 IN令牌完成时置位enable（见上文），在任何EP0完成后由硬件清零"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:77
+msgid ""
+"The idea here is to keep the whole register cleared until a USB SET_ADDRESS "
+"setup packet is received on EP0. At that moment, you can set the address and"
+" the trigger field, then provide the IN zero length descriptor to EP0 to "
+"finalise the SET_ADDRESS sequance. The controller will then automaticaly "
+"turn on the address filtering at the completion of that descriptor."
+msgstr ""
+"这里的想法是在EP0上收到USB SET_ADDRESS的设置(setup)数据包前，保持整个寄存器清"
+"零。此时，您可以设置地址和触发字段，然后向EP0提供IN零长度描述符以完成SET_ADDR"
+"ESS序列。控制器将在该描述符完成时自动打开地址过滤。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:82
+msgid "INTERRUPT (0xFF08)"
+msgstr "中断INTERRUPT (0xFF08)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:84
+msgid ""
+"Individual bits of this register can be cleared by writing '1' in them. "
+"Reading this register returns the current interrupt status."
+msgstr "该寄存器的每个位都可以通过写入 '1' 来清除。读取该寄存器将返回当前中断状态。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+msgid "endpoints"
+msgstr "endpoints"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "W1C"
+msgstr "W1C"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "15-0"
+msgstr "15-0"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:90
+msgid "Raised when an endpoint generates an interrupt"
+msgstr "当端点产生中断时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+msgid "reset"
+msgstr "reset"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "16"
+msgstr "16"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:92
+msgid "Raised when a USB reset occurs"
+msgstr "当USB复位发生时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+msgid "ep0Setup"
+msgstr "ep0Setup"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "17"
+msgstr "17"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:94
+msgid "Raised when endpoint 0 receives a setup transaction"
+msgstr "当端点0收到设置请求时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+msgid "suspend"
+msgstr "suspend"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid "18"
+msgstr "18"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:96
+msgid "Raised when a USB suspend occurs"
+msgstr "当发生USB挂起时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+msgid "resume"
+msgstr "resume"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "19"
+msgstr "19"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:98
+msgid "Raised when a USB resume occurs"
+msgstr "当USB发生恢复时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "disconnect"
+msgstr "disconnect"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "20"
+msgstr "20"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:100
+msgid "Raised when a USB disconnect occurs"
+msgstr "当USB断开连接时拉高"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:104
+msgid "HALT (0xFF0C)"
+msgstr "暂停HALT (0xFF0C)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:106
+msgid ""
+"This register allows placement of a single endpoint into a dormant state in "
+"order to ensure atomicity of CPU operations, allowing to do things as "
+"read/modify/write on the endpoint registers and descriptors. The peripheral "
+"will return NAK if the given endpoint is addressed by the usb host while "
+"halt is enabled and the endpoint is enabled."
+msgstr ""
+"该寄存器允许将单个端点置于休眠状态，以确保CPU操作的原子性，从而允许在端点寄存"
+"器和描述符上执行读/修改/写操作。如果USB主机在暂停启用且端点启用的情况下寻址给"
+"定端点，那么外设将返回NAK。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+msgid "endpointId"
+msgstr "endpointId"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "3-0"
+msgstr "3-0"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:112
+msgid "The endpoint you want to put in sleep"
+msgstr "您想要进入休眠状态的目标端点"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "4"
+msgstr "4"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:114
+msgid "When set halt is active, when clear endpoint is unhalted."
+msgstr "当设置暂停时为活动状态，当清除时端点解除暂停。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid "effective enable"
+msgstr "effective enable"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid "5"
+msgstr "5"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:116
+msgid ""
+"After setting the enable, you need to wait for this bit to be set by the "
+"hardware itself to ensure atomicity"
+msgstr "设置使能后，需要等待硬件本身设置该位，以保证原子性"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:121
+msgid "CONFIG (0xFF10)"
+msgstr "配置CONFIG (0xFF10)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+msgid "pullupSet"
+msgstr "pullupSet"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+msgid "SO"
+msgstr "SO"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "0"
+msgstr "0"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:126
+msgid "Write '1' to enable the USB device pullup on the dp pin"
+msgstr "写入 '1' 以使能dp引脚上的USB设备上拉"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+msgid "pullupClear"
+msgstr "pullupClear"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:128
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+msgid "interruptEnableSet"
+msgstr "interruptEnableSet"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "2"
+msgstr "2"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:130
+msgid "Write '1' to let the present and future interrupt happening"
+msgstr "写入 '1' 让当前和未来的中断发生"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+msgid "interruptEnableClear"
+msgstr "interruptEnableClear"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:132
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid "3"
+msgstr "3"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:136
+msgid "INFO (0xFF20)"
+msgstr "信息INFO (0xFF20)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "ramSize"
+msgstr "ramSize"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:141
+msgid "The internal ram will have (1 << this) bytes"
+msgstr "内部RAM将有 (1 << this) 字节"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:145
+msgid "ENDPOINTS (0x0000 - 0x003F)"
+msgstr "端点ENDPOINTS (0x0000 - 0x003F)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:147
+msgid ""
+"The endpoints status are stored at the begining of the internal ram over one"
+" 32 bits word each."
+msgstr "端点状态存储在内部RAM的开头，每个端点状态有一个32位字。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "RW"
+msgstr "RW"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:152
+msgid "If not set, the endpoint will ignore all the trafic"
+msgstr "如果不设置，端点将忽略所有流量"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+msgid "stall"
+msgstr "stall"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:154
+msgid "If set, the endpoint will always return STALL status"
+msgstr "如果设置，端点将始终返回STALL状态"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+msgid "nack"
+msgstr "nack"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:156
+msgid "If set, the endpoint will always return NACK status"
+msgstr "如果设置，端点将始终返回NACK状态"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid "dataPhase"
+msgstr "dataPhase"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:158
+msgid ""
+"Specify the IN/OUT data PID used. '0' => DATA0. This field is also updated "
+"by the controller."
+msgstr "指定使用的出入数据PID。 '0' => DATA0。该字段也由控制器更新。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+msgid "head"
+msgstr "head"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "15-4"
+msgstr "15-4"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:161
+msgid ""
+"Specify the current descriptor head (linked list). 0 => empty list, byte "
+"address = this << 4"
+msgstr "指定当前描述符头（链表）。0 => 空列表，字节地址 = this << 4"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:164
+msgid "isochronous"
+msgstr "isochronous"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "maxPacketSize"
+msgstr "maxPacketSize"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:166
+msgid "31-22"
+msgstr "31-22"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:169
+msgid "To get a endpoint responsive you need :"
+msgstr "要获得端点响应，您需要："
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:171
+msgid "Set its enable flag to 1"
+msgstr "将其使能标志设置为1"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:173
+msgid ""
+"Then the there is a few cases : - Either you have the stall or nack flag "
+"set, and so, the controller will always respond with the corresponding "
+"responses - Either, for EP0 setup request, the controller will not use "
+"descriptors, but will instead write the data into the SETUP_DATA register, "
+"and ACK - Either you have a empty linked list (head==0) in which case it "
+"will answer NACK - Either you have at least one descriptor pointed by head, "
+"in which case it will execute it and ACK if all was going smooth"
+msgstr ""
+"那么有几种情况： -要么设置了stall或nack标志，所以控制器将始终响应相应的响应 "
+"-要么，对于EP0设置请求，控制器不会使用描述符，"
+"而是会将数据写入SETUP_DATA寄存器和ACK -要么你有一个空链表 (head==0)，"
+"在这种情况下它将响应NACK -要么你至少有一个由head指向的描述符，在这种情况下，"
+"它将执行该描述符，并在一切顺利时进行ACK"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:180
+msgid "SETUP_DATA (0x0040 - 0x0047)"
+msgstr "设置数据SETUP_DATA (0x0040 - 0x0047)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:182
+msgid ""
+"When endpoint 0 receives a SETUP transaction, the data of the transaction "
+"will be stored in this location."
+msgstr "当端点0接收到SETUP事务时，该事务的数据将存储在该位置。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:185
+msgid "Descriptors"
+msgstr "描述符"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:187
+msgid ""
+"Descriptors allows to specify how an endpoint needs to handle the data phase"
+" of IN/OUT transactions. They are stored in the internal ram, can be linked "
+"together via their linked lists and need to be aligned on 16 bytes "
+"boundaries"
+msgstr ""
+"描述符允许指定一个端点需要如何处理出入(IN/OUT)事务的数据阶段。它们存储在内部 "
+"RAM 中，可以通过链表链接在一起，并且需要在16字节边界上对齐"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:191
+msgid "Word"
+msgstr "字"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "offset"
+msgstr "offset"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:193
+msgid "Specify the current progress in the transfer (in byte)"
+msgstr "指定当前传输进度（以字节为单位）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "code"
+msgstr "code"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "19-16"
+msgstr "19-16"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:195
+msgid "0xF => in progress, 0x0 => success"
+msgstr "0xF => 进行中，0x0 => 成功"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "next"
+msgstr "next"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:197
+msgid "Pointer to the next descriptor 0 => nothing, byte address = this << 4"
+msgstr "指向下一个描述符 0 => 无，字节地址 = this << 4"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "length"
+msgstr "length"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "31-16"
+msgstr "31-16"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:200
+msgid "Number of bytes allocated for the data field"
+msgstr "分配给数据字段的字节数"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "direction"
+msgstr "方向"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:202
+msgid "'0' => OUT, '1' => IN"
+msgstr "'0' => 输出，'1' => 输入"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "interrupt"
+msgstr "interrupt"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:204
+msgid "If set, the completion of the descriptor will generate an interrupt."
+msgstr "如果置位，描述符完成时将产生中断。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid "completionOnFull"
+msgstr "completionOnFull"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:207
+msgid ""
+"Normally, a descriptor completion only occurs when a USB transfer is smaller"
+" than the maxPacketSize. But if this field is set, then when the descriptor "
+"become full is also a considered as a completion event. (offset == length)"
+msgstr ""
+"通常，描述符补全只会在USB传输小于maxPacketSize时发生。但如果置位了该字段，那"
+"么当描述符被填满时也被视为事件已完成。(offset == length)"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid "data1OnCompletion"
+msgstr "data1OnCompletion"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:212
+msgid ""
+"force the endpoint dataPhase to DATA1 on the completion of the descriptor"
+msgstr "描述符完成时强制端点dataPhase为DATA1"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:215
+msgid "data"
+msgstr "data"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:215
+msgid "..."
+msgstr "..."
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:218
+msgid ""
+"Note, if the controller receives a frame where the IN/OUT does not match the"
+" descriptor IN/OUT, the frame will be ignored."
+msgstr "请注意，如果控制器接收到IN/OUT与描述符IN/OUT不匹配的帧，那么该帧将被忽略。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:220
+msgid ""
+"Also, to initialise a descriptor, the CPU should set the code field to 0xF"
+msgstr "此外，要初始化描述符，CPU应将代码字段设置为0xF"
+
+#: ../../SpinalHDL/Libraries/Com/usb_device.rst:223
+msgid "Usage"
+msgstr "用法"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
+
+#~ msgid "RC"
+#~ msgstr "RC"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po
new file mode 100644
index 00000000000..11c28fbeef6
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po
@@ -0,0 +1,146 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariescomusb_ohci/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:3
+msgid "USB OHCI"
+msgstr "USB OHCI"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:5
+msgid "Here exists a USB OHCi controller (host) in the SpinalHDL library."
+msgstr "SpinalHDL库中有USB OHCi控制器（主机）。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:7
+msgid "A few bullet points to summarise support:"
+msgstr "用几个要点总结支持的功能："
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:9
+msgid ""
+"It follow the `OpenHCI Open Host Controller Interface Specification for USB`"
+" specification (OHCI)."
+msgstr "它遵循 `OpenHCI USB开放式主机控制接口规范` (OHCI)。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:10
+msgid ""
+"It is compatible with the upstream linux / uboot OHCI drivers already. "
+"(there is also an OHCI driver on tinyUSB)"
+msgstr "它已经与上游的linux/uboot OHCI驱动兼容。（tinyUSB上也有OHCI驱动）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:11
+msgid ""
+"This provides USB host full speed and low speed capabilities (12Mbps and "
+"1.5Mbps)"
+msgstr "它提供了USB主机全速和低速功能（12Mbps和1.5Mbps）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:12
+msgid "Tested on linux and uboot"
+msgstr "在linux和uboot上测试过"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:13
+msgid "One controller can host multiple ports (up to 16)"
+msgstr "一个可以承载多个端口（多至16个）的控制器"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:14
+msgid "Bmb memory interface for DMA accesses"
+msgstr "用于DMA访问的Bmb存储器接口"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:15
+msgid "Bmb memory interace for the configuration"
+msgstr "用于配置的Bmb内存接口"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:16
+msgid ""
+"Requires a clock for the internal phy which is a multiple of 12 Mhz at least"
+" 48 Mhz"
+msgstr "内部物理层需要一个时钟，该时钟需要为12 Mhz的倍数，至少48 Mhz"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:17
+msgid "The controller frequency is not restricted"
+msgstr "控制器频率不受限制"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:18
+msgid "No external phy required"
+msgstr "无需外部物理层"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:20
+msgid "Devices tested and functional :"
+msgstr "经过测试且功能正常的设备："
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:22
+msgid "Mass storage (~8 Mbps on ArtyA7 linux)"
+msgstr "大容量存储（ArtyA7 Linux上约为8 Mbps）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:23
+msgid "Keyboard / Mouse"
+msgstr "键盘/鼠标"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:24
+msgid "Audio output"
+msgstr "音频输出"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:25
+msgid "Hub"
+msgstr "集线器"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:27
+msgid "Limitations :"
+msgstr "限制："
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:29
+msgid ""
+"Some USB hub (had one so far) do not like having a full speed host with low "
+"speed devices attached."
+msgstr "某些USB集线器（目前已有一个）对将低速设备连接至全速主机的模式不友好。"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:30
+msgid ""
+"Some modern devices will not work on USB full speed (ex :  Gbps ethernet "
+"adapter)"
+msgstr "某些现代设备无法在USB全速上运行（例如：Gbps以太网适配器）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:31
+msgid ""
+"Require memory coherency with the CPU (or the cpu need to be able to flush "
+"its data cache in the driver)"
+msgstr "需要与CPU保持内存一致性（或者需要CPU能够刷新驱动中的数据缓存）"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:33
+msgid "Deployments :"
+msgstr "部署："
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:35
+msgid ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux"
+msgstr ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/"
+"ArtyA7SmpLinux"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:36
+msgid ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+msgstr ""
+"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp"
+
+#: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:39
+msgid "Usage"
+msgstr "用法"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po
new file mode 100644
index 00000000000..261398f5718
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po
@@ -0,0 +1,115 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesedaalteraqsysify/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:3
+msgid "QSysify"
+msgstr "QSysify"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:5
+msgid ""
+"QSysify is a tool which is able to generate a QSys IP (tcl script) from a "
+"SpinalHDL component by analysing its IO definition. It currently implement "
+"the following interfaces features :"
+msgstr "QSysify是一个能够通过分析SpinalHDL组件的IO定义来生成QSys "
+"IP（tcl脚本）的工具。目前它实现了以下接口特性："
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:7
+msgid "Master/Slave AvalonMM"
+msgstr "主/从AvalonMM"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:8
+msgid "Master/Slave APB3"
+msgstr "主/从APB3"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:9
+msgid "Clock domain input"
+msgstr "时钟域输入"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:10
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:67
+msgid "Reset output"
+msgstr "复位输出"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:11
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:60
+msgid "Interrupt input"
+msgstr "中断输入"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:12
+msgid "Conduit (Used in last resort)"
+msgstr "导线（作为最后手段使用）"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:15
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:17
+msgid "In the case of a UART controller :"
+msgstr "以UART控制器为例："
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:30
+msgid ""
+"The following  ``main`` will generate the Verilog and the QSys TCL script "
+"with io.bus as an AvalonMM and io.uart as a conduit :"
+msgstr "下面的 ``main`` 将生成Verilog和QSys TCL脚本，其中io.bus将作为AvalonMM总线，io"
+".uart作为导线："
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:48
+msgid "tags"
+msgstr "标签"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:50
+msgid ""
+"Because QSys require some information that are not specified in the "
+"SpinalHDL hardware specification, some tags should be added to interface:"
+msgstr "由于QSys需要一些SpinalHDL硬件规范中未指定的信息，因此应在接口中添加一些标签："
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:53
+msgid "AvalonMM / APB3"
+msgstr "AvalonMM / APB3"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:74
+msgid "Adding new interface support"
+msgstr "添加新的接口支持"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:76
+msgid ""
+"Basically, the QSysify tool can be setup with a list of interface "
+"``emitter`` `(as you can see here) "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L12>`_"
+msgstr ""
+"基本上，QSysify工具可以使用接口 ``emitter`` 列表进行设置 "
+"`（如您在此处看到的） <https://github.com/SpinalHDL/SpinalHDL/blob/"
+"764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/"
+"altera/QSys.scala#L12>`"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:78
+msgid ""
+"You can create your own emitter by creating a new class extending "
+"`QSysifyInterfaceEmiter "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L24>`_"
+msgstr ""
+"您可以通过创建一个扩展 `QSysifyInterfaceEmiter <https://github.com/SpinalHDL/"
+"SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/"
+"spinal/lib/eda/altera/QSys.scala #L24>`_ 的新类来创建自己的发射器(emitter)"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/quartus_flow.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/quartus_flow.po
new file mode 100644
index 00000000000..019218ad710
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/quartus_flow.po
@@ -0,0 +1,116 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesedaalteraquartus_flow/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:3
+msgid "QuartusFlow"
+msgstr "QuartusFlow"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:5
+msgid ""
+"A compilation flow is an Altera-defined sequence of commands that use a "
+"combination of command-line executables. A full compilation flow launches "
+"all Compiler modules in sequence to synthesize, fit, analyze final timing, "
+"and generate a device programming file."
+msgstr ""
+"编译流是Altera定义的命令序列，这些命令使用命令行可执行文件的组合。完整的编译"
+"流会按顺序启动所有的编译器模块，进行综合、拟合、最终时序分析，并生成设备编程"
+"文件。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:8
+msgid ""
+"Tools in `this file "
+"<https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/eda/altera/QuartusFlow.scala>`__"
+" help you get rid of redundant Quartus GUI."
+msgstr ""
+"`此文件 <https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/"
+"spinal/lib/eda/altera/QuartusFlow.scala>`__ "
+"中的工具会帮助您消除冗余的Quartus GUI。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:11
+msgid "For a single rtl file"
+msgstr "对于单个rtl文件"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:13
+msgid ""
+"The object ``spinal.lib.eda.altera.QuartusFlow`` can automatically report "
+"the used area and maximum frequency of a single rtl file."
+msgstr "对象 ``spinal.lib.eda.altera.QuartusFlow`` "
+"可以自动报告单个rtl文件的使用面积和最大频率。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:16
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:54
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:30
+msgid ""
+"The code above will create a new Quartus project with ``TopLevel.vhd``."
+msgstr "上面的代码将使用 ``TopLevel.vhd`` 创建一个新的 Quartus 项目。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:33
+msgid "This operation will remove the folder ``workspacePath``!"
+msgstr "此操作将删除文件夹 ``workspacePath`` ！"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:36
+msgid ""
+"The ``family`` and ``device`` values are passed straight to the Quartus CLI "
+"as parameters. Please check the Quartus documentation for the correct value "
+"to use in your project."
+msgstr ""
+"``family`` 和 ``device`` 值作为参数直接传递到Quartus "
+"CLI。请检查Quartus文档以确定在您的项目中使用的正确值。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:39
+msgid "Tip"
+msgstr "小贴士"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:41
+msgid ""
+"To test a component that has too many pins, set them as ``VIRTUAL_PIN``."
+msgstr "为了测试具有太多引脚的组件，请将它们设置为 ``VIRTUAL_PIN`` 。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:49
+msgid "For an existing project"
+msgstr "对于一个现有项目"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:51
+msgid ""
+"The class ``spinal.lib.eda.altera.QuartusProject`` can automatically find "
+"configuration files in an existing project. Those are used for compilation "
+"and programming the device."
+msgstr ""
+"类 ``spinal.lib.eda.altera.QuartusProject`` "
+"可以自动查找现有项目中的配置文件。它们用于对设备进行编译和编程。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:56
+msgid ""
+"Specify the path that contains your project files like ``.qpf`` and "
+"``.cdf``."
+msgstr "指定包含项目文件的路径，例如 ``.qpf`` 和 ``.cdf`` 。"
+
+#: ../../SpinalHDL/Libraries/EDA/altera/quartus_flow.rst:68
+msgid ""
+"Remember to save the ``.cdf`` of your project before calling "
+"``prj.program()``."
+msgstr "请记住在调用 ``prj.program()`` 之前保存项目的 ``.cdf`` 文件。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/index.po
new file mode 100644
index 00000000000..77b3389d2b9
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesedaindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/EDA/index.rst:3
+msgid "EDA"
+msgstr "自动设计工具(EDA)"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/colors.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/colors.po
new file mode 100644
index 00000000000..9d8a3bc27c9
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/colors.po
@@ -0,0 +1,36 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesgraphicscolors/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Graphics/colors.rst:3
+msgid "Colors"
+msgstr "颜色"
+
+#: ../../source/SpinalHDL/Libraries/Graphics/colors.rst:6
+msgid "RGB"
+msgstr "RGB"
+
+#: ../../source/SpinalHDL/Libraries/Graphics/colors.rst:8
+msgid ""
+"You can use an Rgb bundle to model colors in hardware. This Rgb bundle take "
+"as parameter an RgbConfig classes which specify the number of bits for each "
+"channels :"
+msgstr "您可以使用Rgb线束在硬件中对建模颜色。该Rgb线束采用RgbConfig类作为参数，该类指"
+"定每个通道的位数："
+
+#: ../../source/SpinalHDL/Libraries/Graphics/colors.rst:22
+msgid "Those classes could be used as following :"
+msgstr "这些类的使用如下："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/index.po
new file mode 100644
index 00000000000..99d359ec5df
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesgraphicsindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Graphics/index.rst:3
+msgid "Graphics"
+msgstr "图形"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/vga.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/vga.po
new file mode 100644
index 00000000000..a19a7a66d44
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Graphics/vga.po
@@ -0,0 +1,66 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesgraphicsvga/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:5
+msgid "VGA"
+msgstr "VGA"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:8
+msgid "VGA bus"
+msgstr "VGA总线"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:10
+msgid "An VGA bus definition is available via the Vga bundle."
+msgstr "VGA总线通过Vga线束定义。"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:25
+msgid "VGA timings"
+msgstr "VGA时序"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:27
+msgid ""
+"VGA timings could be modeled in hardware by using an VgaTimings bundle :"
+msgstr "VGA时序可以使用VgaTimings线束在硬件中建模："
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:47
+msgid "VGA controller"
+msgstr "VGA控制器"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:49
+msgid "An VGA controller is available. Its definition is the following :"
+msgstr "现有VGA控制器，其定义如下："
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:67
+msgid ""
+"``frameStart`` is a signals that pulse one cycle at the beginning of each "
+"new frame."
+msgstr "``frameStart`` 是一个在每个新帧开始时脉冲一个周期的信号。"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:68
+msgid ""
+"``pixels`` is a stream of color used to feed the VGA interface when needed."
+msgstr "``pixels`` 是一种颜色反压流，用于在需要时为VGA接口提供数据。"
+
+#: ../../SpinalHDL/Libraries/Graphics/vga.rst:69
+msgid ""
+"``error`` is high when a transaction on the pixels is needed, but nothing is"
+" present."
+msgstr "当需要传输像素但没有对象时， ``error`` 为高。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/index.po
new file mode 100644
index 00000000000..d2e42066ad2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesioindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/IO/index.rst:3
+msgid "IO"
+msgstr "IO口"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/readableOpenDrain.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/readableOpenDrain.po
new file mode 100644
index 00000000000..1f7b333c787
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/readableOpenDrain.po
@@ -0,0 +1,37 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesioreadableopendrain/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/IO/readableOpenDrain.rst:3
+#: ../../source/SpinalHDL/Libraries/IO/readableOpenDrain.rst:6
+msgid "ReadableOpenDrain"
+msgstr "可读开漏IO(ReadableOpenDrain)"
+
+#: ../../source/SpinalHDL/Libraries/IO/readableOpenDrain.rst:8
+msgid "The ReadableOpenDrain bundle is defined as following :"
+msgstr "ReadableOpenDrain线束定义如下："
+
+#: ../../source/SpinalHDL/Libraries/IO/readableOpenDrain.rst:21
+msgid ""
+"Then, as a master, you can use the ``read`` signal to read the outside value"
+" and use the ``write`` to set the value that you want to drive on the "
+"output."
+msgstr "然后，作为主端，您可以使用 ``read`` 信号读取外部值，并使用 ``write`` "
+"设置您想要在输出上驱动的值。"
+
+#: ../../source/SpinalHDL/Libraries/IO/readableOpenDrain.rst:23
+msgid "There is an example of usage :"
+msgstr "这是一个用法示例："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/tristate.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/tristate.po
new file mode 100644
index 00000000000..188e6c40d43
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/IO/tristate.po
@@ -0,0 +1,126 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesiotristate/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:4
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:22
+msgid "TriState"
+msgstr "三态"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:6
+msgid "Tri-state signals are difficult to handle in many cases:"
+msgstr "在许多情况下，三态信号难以处理："
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:8
+msgid "They are not really kind of digital things"
+msgstr "它们不是真正的数字性"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:9
+msgid "And except for IO, they aren't used for digital design"
+msgstr "除了IO之外，它们不用于数字设计"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:10
+msgid ""
+"The tristate concept doesn't fit naturally in the SpinalHDL internal graph."
+msgstr "三态概念并不自然地适合SpinalHDL内部图。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:12
+msgid ""
+"SpinalHDL provides two different abstractions for tristate signals. The "
+"``TriState`` bundle and :ref:`section-analog_and_inout` signals. Both serve "
+"different purposes:"
+msgstr ""
+"SpinalHDL为三态信号提供两种不同的抽象。 ``TriState`` 线束和 :ref:`section-"
+"analog_and_inout` 信号。两者有不同的目的："
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:15
+msgid ""
+"TriState should be used for most purposes, especially within a design. The "
+"bundle contains an additional signal to carry the current direction."
+msgstr "TriState应用于大多数目的，尤其是在设计中。该束包含一个附加信号来传递当前的方"
+"向。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:16
+msgid ""
+"``Analog`` and ``inout`` should be used for drivers on the device boundary "
+"and in some other special cases. See the referenced documentation page for "
+"more details."
+msgstr "``Analog`` 和 ``inout`` 应用于设备边界上的驱动以及其他一些特殊情况。有关更多"
+"详细信息，请参阅参考文档页面。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:18
+msgid ""
+"As stated above, the recommended approach is to use ``TriState`` within a "
+"design. On the top-level the ``TriState`` bundle is then assigned to an "
+"analog inout to get the synthesis tools to infer the correct I/O driver. "
+"This can be done automatically done via the :ref:`InOutWrapper <section-"
+"analog_and_inout>` or manually if needed."
+msgstr ""
+"如上所述，推荐的方法是在设计中使用 ``TriState`` 。然后，在顶层， ``TriState``"
+" 线束被赋值给模拟输入输出，以使综合工具推断出正确的I/O驱动。这可以通过 "
+":ref:`输入/出包装器 <section-analog_and_inout>` "
+"自动完成，或者根据需要手动完成。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:24
+msgid "The TriState bundle is defined as following :"
+msgstr "TriState线束定义如下："
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:38
+msgid ""
+"A master can use the ``read`` signal to read the outside value, the "
+"``writeEnable`` to enable the output, and finally use ``write`` to set the "
+"value that is driven on the output."
+msgstr ""
+"主端可以使用 ``read`` 信号读取外部值，使用 ``writeEnable`` 启用输出，"
+"最后使用 ``write`` 设置输出驱动的值。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:41
+msgid "There is an example of usage:"
+msgstr "这是一个使用示例："
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:56
+msgid "TriStateArray"
+msgstr "三态阵列"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:58
+msgid ""
+"In some case, you need to have the control over the output enable of each "
+"individual pin (Like for GPIO). In this range of cases, you can use the "
+"TriStateArray bundle."
+msgstr "在某些情况下，您需要控制每个单独引脚的输出使能（像GPIO一样）。在这种情况下，"
+"您可以使用TriStateArray线束。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:60
+msgid "It is defined as following :"
+msgstr "它的定义如下："
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:73
+msgid ""
+"It is the same than the TriState bundle, except that the ``writeEnable`` is "
+"an Bits to control each output buffer."
+msgstr "它与TriState线束相同，不同的是 ``writeEnable`` "
+"是一个位(Bits)来控制每个输出缓冲区。"
+
+#: ../../SpinalHDL/Libraries/IO/tristate.rst:75
+msgid "There is an example of usage :"
+msgstr "这是一个用法示例："
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po
new file mode 100644
index 00000000000..ff65ff64479
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po
@@ -0,0 +1,116 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesmiscplicplic_mapper/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:7
+msgid "Plic Mapper"
+msgstr "Plic映射器"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:9
+msgid ""
+"The PLIC Mapper defines the register generation and access for a PLIC "
+"(Platform Level Interrupt Controller."
+msgstr "PLIC映射器定义了PLIC（平台级中断控制器）的寄存器生成和访问。"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:12
+msgid "``PlicMapper.apply``"
+msgstr "``PlicMapper.apply``"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:14
+msgid ""
+"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : Seq[PlicGateway], "
+"targets : Seq[PlicTarget])``"
+msgstr ""
+"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : Seq[PlicGateway], "
+"targets : Seq[PlicTarget])``"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:16
+msgid "args for PlicMapper:"
+msgstr "PlicMapper的参数："
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:18
+msgid "**bus**: bus to which this ctrl is attached"
+msgstr "**bus**：连接此控制器的总线"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:19
+msgid "**mapping**: a mapping configuration (see above)"
+msgstr "**mapping**：一个映射配置（见上文）"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:20
+msgid ""
+"**gateways**: a sequence of PlicGateway (interrupt sources) to generate the "
+"bus access control"
+msgstr "**gateways**：用于生成总线访问控制的PlicGateway（中断源）序列"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:21
+msgid ""
+"**targets**: the sequence of PlicTarget (eg. multiple cores) to generate the"
+" bus access control"
+msgstr "**targets**：生成总线访问控制的PlicTarget序列（如：多核）"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:24
+msgid ""
+"It follows the interface given by riscv: https://github.com/riscv/riscv-"
+"plic-spec/blob/master/riscv-plic.adoc"
+msgstr ""
+"它遵循riscv提供的接口：https://github.com/riscv/riscv-plic-spec/blob/master/"
+"riscv-plic.adoc"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:26
+msgid "As of now, two memory mappings are available :"
+msgstr "截至目前，有两种内存映射可用："
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:29
+msgid "``PlicMapping.sifive``"
+msgstr "``PlicMapping.sifive``"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:30
+msgid ""
+"Follows the SiFive PLIC mapping (eg. `E31 core complex Manual "
+"<https://sifive.cdn.prismic.io/sifive/9169d157-0d50-4005-a289-36c684de671b_e31_core_complex_manual_21G1.pdf>`_"
+" ), basically a full fledged PLIC"
+msgstr ""
+"遵循SiFive的PLIC映射（例如 `E31核心复合手册 <https://sifive.cdn.prismic.io/"
+"sifive/9169d157-0d50-4005-a289-36c684de671b_e31_core_complex_manual_21G1."
+"pdf>`_ )，基本上是一个成熟的PLIC"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:33
+msgid "``PlicMapping.light``"
+msgstr "``PlicMapping.light``"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:34
+msgid ""
+"This mapping generates a lighter PLIC, at the cost of some missing optional "
+"features:"
+msgstr "此映射生成更轻量级的PLIC，但代价是缺少一些可选特性："
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36
+msgid "no reading the intrerrupt's priority"
+msgstr "不读取中断优先级"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37
+msgid ""
+"no reading the interrupts's pending bit (must use the claim/complete "
+"mechanism)"
+msgstr "不读取中断的挂起位（必须使用声明(claim)/完成(complete)机制）"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38
+msgid "no reading the target's threshold"
+msgstr "不读取目标的阈值"
+
+#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:40
+msgid "The rest of the registers & logic is generated."
+msgstr "剩下的寄存器&逻辑会被生成."
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/index.po
new file mode 100644
index 00000000000..d23619dd5ab
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-02 14:47+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesmiscindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/Misc/index.rst:3
+msgid "Misc"
+msgstr "杂项"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po
new file mode 100644
index 00000000000..41632b7a2b0
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po
@@ -0,0 +1,210 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2024.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesmiscservice_plugin/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:5
+msgid "Plugin"
+msgstr "插件"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:8
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:10
+msgid ""
+"For some design, instead of implementing your Component's hardware directly "
+"in it, you may instead want to compose its hardware by using some sorts of "
+"Plugins. This can provide a few key features :"
+msgstr "对于某些设计，您可能希望通过使用某种插件来组合组件的硬件，而不是直接在组件中"
+"实现硬件。这可以提供一些关键特性："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:13
+msgid ""
+"You can extend the features of your component by adding new plugins in its "
+"parameters. For instance adding Floating point support in a CPU."
+msgstr "您可以通过在组件的参数中添加新的插件来扩展组件的功能。例如，在CPU中添加浮点支"
+"持。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:14
+msgid ""
+"You can swap various implementations of the same functionality just by using "
+"another set of plugins. For instance one implementation of a CPU multiplier "
+"may fit well on some FPGA, while others may fit well on ASIC."
+msgstr ""
+"您可以通过使用另一组插件来轻松切换相同功能的各种实现。例如，某个CPU乘法器的实"
+"现可能在某些FPGA上表现良好，而其他实现可能在ASIC上表现良好。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:15
+msgid ""
+"It avoid the very very very large hand written toplevel syndrom where "
+"everything has to be connected manualy. Instead plugins can discover their "
+"neighborhood by looking/using the software interface of other plugins."
+msgstr "它避免了非常非常庞大的手写顶层结构，其中一切都必须手动连接的情况。相反，插件"
+"可以通过查看/使用其他插件的软件接口来发现它们的关联关系。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:17
+msgid ""
+"VexRiscv and NaxRiscv projects are an example of this. Their are CPUs which "
+"have a mostly empty toplevel, and their hardware parts are injected using "
+"plugins. For instance :"
+msgstr "VexRiscv和NaxRiscv项目就是这方面的例子。它们是具有大部分是空白的顶层的CPU，其"
+"硬件部分通过插件注入。例如："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:20
+msgid "PcPlugin"
+msgstr "PcPlugin"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:21
+msgid "FetchPlugin"
+msgstr "FetchPlugin"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:22
+msgid "DecoderPlugin"
+msgstr "DecoderPlugin"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:23
+msgid "RegFilePlugin"
+msgstr "RegFilePlugin"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:24
+msgid "IntAluPlugin"
+msgstr "IntAluPlugin"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:25
+msgid "..."
+msgstr "..."
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:27
+msgid ""
+"And those plugins will then negociate/propagate/interconnect to each others "
+"via their pool of services."
+msgstr "这些插件将通过他们的服务池进行协调/传递/互连。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:29
+msgid ""
+"While VexRiscv use a strict synchronous 2 phase system (setup/build "
+"callback), NaxRiscv uses a more flexible approach which uses the spinal.core."
+"fiber API to fork elaboration threads which can interlock each others in "
+"order to ensure a workable elaboration ordering."
+msgstr ""
+"虽然VexRiscv使用严格的同步二阶段系统（设置(setup)/构建(build)回调(callback)）"
+"，但NaxRiscv采用了一种更灵活的方法，使用spinal.core.fiber "
+"API来分叉实例化线程，这些线程可以联锁，以确保可行的实例化顺序。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:31
+msgid ""
+"The Plugin API provide a NaxRiscv like system to define composable "
+"components using plugins."
+msgstr "插件API(Plugin API)提供了一个类似NaxRiscv的系统来定义使用插件的可组合组件。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:34
+msgid "Execution order"
+msgstr "执行顺序"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:36
+msgid "The main idea is that you have multiple 2 executions phases :"
+msgstr "主要思想是您有多个2执行环节："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:38
+msgid ""
+"Setup phase, in which plugins can lock/retain each others. The idea is not "
+"to start negociation / elaboration yet."
+msgstr "设置(Setup)环节，在此环节插件可以联锁/保留。其目的并非开始协调/实例化。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:39
+msgid "Build phase, in which plugins can negociation / elaboration hardware."
+msgstr "构建(Build)环节，在此环节插件可以协调/实例化硬件。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:41
+msgid ""
+"The build phase will not start before all FiberPlugin are done with their "
+"setup phase."
+msgstr "构建环节将不会在所有FiberPlugin完成其设置环节前启动。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:61
+msgid "Simple example"
+msgstr "简单示例"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:63
+msgid ""
+"Here is a simple dummy example with a SubComponent which will be composed "
+"using 2 plugins :"
+msgstr "这是一个简单的虚设示例，其中包含一个将使用两个插件组合的SubComponent："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:102
+msgid "Such TopLevel would generate the following Verilog code :"
+msgstr "该TopLevel会生成以下Verilog代码："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:131
+msgid ""
+"Note each \"during build\" fork an elaboration thread, the DriverPlugin."
+"logic thread execution will be blocked on the \"sp\" evaluation until the "
+"StatePlugin.logic execution is done."
+msgstr ""
+"请注意，每次在“构建期间”分叉一个实例化线程时，DriverPlugin."
+"logic线程的执行将在“sp”评估上被阻塞，直到StatePlugin.logic执行完成。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:135
+msgid "Interlocking / Ordering"
+msgstr "联锁/排序"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:137
+msgid ""
+"Plugins can interlock each others using Retainer instances. Each plugin "
+"instance has a built in lock which can be controlled using retain/release "
+"functions."
+msgstr "插件可以通过Retainer实例相互联锁。每个插件实例都有一个内置锁，可以通过retain/"
+"release函数进行控制。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:140
+msgid ""
+"Here is an example based on the above `Simple example` but that time, the "
+"DriverPlugin will increment the StatePlugin.logic.signal by an amount set by "
+"other plugins (SetupPlugin in our case). And to ensure that the DriverPlugin "
+"doesn't generate the hardware too early, the SetupPlugin uses the "
+"DriverPlugin.retain/release functions."
+msgstr ""
+"这是一个基于上面的 `简单示例` 的例子，但这次，DriverPlugin将通过由其他插件（"
+"在我们的例子中是SetupPlugin）设置的数量对StatePlugin.logic."
+"signal递增。为了确保DriverPlugin不会过早生成硬件，SetupPlugin使用DriverPlugin"
+".retain/release函数。"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:207
+msgid "Here is the generated verilog"
+msgstr "这是生成的verilog"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:236
+msgid ""
+"Clearly, those examples are overkilled for what they do, the idea in general "
+"is more about :"
+msgstr "显然，这些示例对于它们的功能来说有些过度，总体上的思路更多地是："
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:238
+msgid "Negociate / create interfaces between plugins (ex jump / flush ports)"
+msgstr "协调/创建插件之间的接口（例如跳转(jump)/刷新(flush)端口）"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:239
+msgid "Schedule the elaboration (ex decode / dispatch specification)"
+msgstr "安排实例化（例如解码/调度规范）"
+
+#: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:240
+msgid "Provide a distributed framework which can scale up (minimal hardcoding)"
+msgstr "提供一个可扩展的分布式框架（最小硬编码）"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po
new file mode 100644
index 00000000000..512cbe3da89
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2024.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-22 03:53+0000\n"
+"PO-Revision-Date: 2024-01-23 07:01+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariespipelineindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Libraries/Pipeline/index.rst:3
+msgid "Pipeline"
+msgstr "Pipeline"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po
new file mode 100644
index 00000000000..95d860e3079
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po
@@ -0,0 +1,866 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2024.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: 2024-01-26 17:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariespipelineintroduction/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:3
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:5
+msgid ""
+"spinal.lib.misc.pipeline provides a pipelining API. The main advantages over "
+"manual pipelining are :"
+msgstr ""
+"spinal.lib.misc.pipeline提供了一套流水线API。相对于手动流水线它的主要优点是："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:7
+msgid ""
+"You don't have to predefine all the signal elements needed for the entire "
+"staged system upfront. You can create and consume stagable signals in a more "
+"ad hoc fashion as your design requires - without needing to refactor all the "
+"intervening stages to know about the signal"
+msgstr ""
+"您不必预先准备好整个流水系统中所需的所有信号元素。您可以根据设计需要，以更特"
+"别的方式创建和使用可分级的信号，而无需重构所有中间阶段来处理信号"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:8
+msgid ""
+"Signals of the pipeline can utilize the powerful parametrization "
+"capabilities of SpinalHDL and be subject to optimization/removal if a "
+"specific design build does not require a particular parametrized feature, "
+"without any need to modify the staging system design or project code base in "
+"a significant way."
+msgstr ""
+"流水线的信号可以利用SpinalHDL的强大参数化能力，并且如果设计构建中不需要特定的"
+"参数化特征，则可以进行优化/移除，而不需要以显著的方式修改流水系统设计或项目代"
+"码库。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:9
+msgid ""
+"Manual retiming is much easier, as you don't have to handle the registers / "
+"arbitration manualy"
+msgstr "手动时序调整要容易得多，因为您不必手动处理寄存器/仲裁器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10
+msgid "Manage the arbitration by itself"
+msgstr "它会自行管理仲裁器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:12
+msgid "The API is composed of 4 main things :"
+msgstr "API由4个主要部分组成："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:14
+msgid "Node : which represents a layer in the pipeline"
+msgstr "Node：表示管道中的层"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:15
+msgid "Link : which allows to connect nodes to each other"
+msgstr "Link：允许节点相互连接"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:16
+msgid ""
+"Builder : which will generate the hardware required for a whole pipeline"
+msgstr "Builder：生成整个管道所需的硬件"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:17
+msgid ""
+"Payload : which are used to retrieve hardware signals on nodes along the "
+"pipeline"
+msgstr "Payload：用于获取流水线的节点上的硬件信号"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:19
+msgid ""
+"It is important to understand that Payload isn't a hardware data/signal "
+"instance, but a key to retrieve a data/signal on nodes along the pipeline, "
+"and that the pipeline builder will then automatically interconnect/pipeline "
+"every occurrence of a given Payload between nodes."
+msgstr ""
+"重要的是，Payload不是硬件数据/信号实例，而是用于检索流水线在节点中数据/信号的"
+"关键，并且流水线构建器随后将在节点之间的每次给定Payload出现时自动互连/流水"
+"线。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:21
+msgid "Here is an example to illustrate :"
+msgstr "以下是一个用于阐述的例子："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:27
+msgid "Here is a video about this API :"
+msgstr "以下是关于此API的视频："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:29
+msgid "https://www.youtube.com/watch?v=74h_-FMWWIM"
+msgstr "https://www.youtube.com/watch?v=74h_-FMWWIM"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:32
+msgid "Simple example"
+msgstr "简单示例"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:34
+msgid "Here is a simple example which only uses the basics of the API :"
+msgstr "下面是一个简单的例子，它只使用了基本的API："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:78
+msgid "This will produce the following hardware :"
+msgstr "这将产生以下硬件："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:83
+msgid "Here is a simulation wave :"
+msgstr "下面是一个仿真波形："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:105
+msgid "Here is the same example but using more of the API :"
+msgstr "下面是相同的示例，但使用了更多的API："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:148
+msgid "Payload"
+msgstr "Payload"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:150
+msgid ""
+"Payload objects are used to refer to data which can go through the pipeline. "
+"Technicaly speaking, Payload is a HardType which has a name and is used as a "
+"\"key\" to retrieve the signals in a certain pipeline stage."
+msgstr ""
+"Payload对象用于引用可以通过流水线的数据。从技术上讲，Payload是一个HardType，"
+"它有一个名字，并被用作在流水线某个级中检索信号的“键”。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:163
+msgid ""
+"Note that I got used to name the Payload instances using uppercase. This is "
+"to make it very explicit that the thing isn't a hardware signal, but are "
+"more like a \"key/type\" to access things."
+msgstr ""
+"请注意，我习惯于使用大写对Payload实例命名。这是为了让它非常明确，这不是一个硬"
+"件信号，更像是一个“键/类型”访问的东西。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:166
+msgid "Node"
+msgstr "Node"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:168
+msgid ""
+"Node mostly hosts the valid/ready arbitration signals, and the hardware "
+"signals required for all the Payload values going through it."
+msgstr "Node主要托管有效/就绪仲裁信号，以及所有通过它的硬件信号所需的Payload。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:170
+msgid "You can access its arbitration via :"
+msgstr "您可以通过以下方式访问其仲裁器："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:177
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:238
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:268
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:390
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:427
+msgid "API"
+msgstr "API"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:178
+msgid "Access"
+msgstr "访问"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:179
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:239
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:269
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:391
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:428
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:180
+msgid "node.valid"
+msgstr "node.valid"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:181
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:184
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:187
+msgid "RW"
+msgstr "RW"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:182
+msgid ""
+"Is the signal which specifies if a transaction is present on the node. It is "
+"driven by the upstream. Once asserted, it must only be de-asserted the cycle "
+"after which either both valid and ready or node.cancel are high. valid must "
+"not depend on ready."
+msgstr ""
+"指定节点上是否存在事务的信号。它是由上游逻辑驱动的。一旦置为1，则它必须且仅能"
+"在valid和ready同时置位或node.cancel为高的周期后解除置位。valid不依赖于ready。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:183
+msgid "node.ready"
+msgstr "node.ready"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:185
+msgid ""
+"Is the signal which specifies if the node's transaction can proceed "
+"downstream. It is driven by the downstream to create backpresure. The signal "
+"has no meaning when there is no transaction (node.valid being deasserted)"
+msgstr ""
+"指定节点的事务是否可以向下游进行的信号。它是由下游驱动以创建反压。当没有事务"
+"（node.valid被置0）时，该信号无意义"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:186
+msgid "node.cancel"
+msgstr "node.cancel"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:188
+msgid ""
+"Is the signal which specifies if the node's transaction in being canceled "
+"from the pipeline. It is driven by the downstream. The signal has no meaning "
+"when there is no transaction (node.valid being deasserted)"
+msgstr ""
+"指定节点的事务是否正在从流水线中取消的信号。它由下游驱动。当没有事务时（node."
+"valid被置0），该信号没有意义"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:189
+msgid "node.isValid"
+msgstr "node.isValid"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:190
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:193
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:196
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:199
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:202
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:207
+msgid "RO"
+msgstr "RO"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:191
+msgid "node.valid's read only accessor"
+msgstr "node.valid的只读访问器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:192
+msgid "node.isReady"
+msgstr "node.isReady"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:194
+msgid "node.ready's read only accessor"
+msgstr "node.ready的只读访问器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:195
+msgid "node.isCancel"
+msgstr "node.isCancel"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:197
+msgid "node.cancel's read only accessor"
+msgstr "node.cancel的只读访问器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:198
+msgid "node.isFiring"
+msgstr "node.isFiring"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200
+msgid ""
+"True when the node transaction is successfuly moving futher (valid && ready "
+"&& !cancel). Useful to commit state changes."
+msgstr ""
+"当节点事务成功继续进行时为True（valid && ready && !cancel）。用于提交状态更"
+"改。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201
+msgid "node.isMoving"
+msgstr "node.isMoving"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:203
+msgid ""
+"True when the node transaction will not be present anymore on the node "
+"(starting from the next cycle), either because downstream is ready to take "
+"the transaction, or because the transaction is canceled from the pipeline. "
+"(valid && (ready || cancel)). Useful to \"reset\" states."
+msgstr ""
+"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好"
+"接收事务，要么是因为事务已从流水线中取消。（valid && (ready || cancel)）用"
+"于“复位”(reset)状态。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:206
+msgid "node.isCanceling"
+msgstr "node.isCanceling"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:208
+msgid ""
+"True when the node transaction is being canceled. Meaning that it will not "
+"appear anywhere in the pipeline in future cycles."
+msgstr ""
+"当节点事务正在被取消时为True。这意味着在将来的周期中它不会出现在流水线中的任"
+"何地方。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:210
+msgid ""
+"Note that the node.valid/node.ready signals follows the same conventions "
+"than the :doc:`../stream`'s ones ."
+msgstr ""
+"请注意，node.valid/node.ready信号遵循与 :doc:`../stream` 中相同的规范。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:212
+msgid ""
+"The Node controls (valid/ready/cancel) and status (isValid, isReady, "
+"isCancel, isFiring, ...) signals are created on demande. So for instance you "
+"can create pipeline with no backpresure by never refering to the ready "
+"signal. That's why it is important to use status signals when you want to "
+"read the status of something and only use control signals when you to drive "
+"something."
+msgstr ""
+"Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、"
+"isFiring等）是按需创建的。因此，例如，您可以通过永远不引用ready信号来创建没有"
+"反压的流水线。这就是在想要读取某物的状态时使用状态信号，仅在想要驱动某物时使"
+"用控制信号的重要性所在。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215
+msgid ""
+"Here is a list of arbitration cases you can have on a node. valid/ready/"
+"cancel define the state we are in, while isFiring/isMoving result of those :"
+msgstr ""
+"以下是节点上可能出现的仲裁情况列表。valid/ready/cancel定义了我们所处的状态，"
+"而isFiring/isMoving是这些状态的结果："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "valid"
+msgstr "valid"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "ready"
+msgstr "ready"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "cancel"
+msgstr "cancel"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "isFiring"
+msgstr "isFiring"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218
+msgid "isMoving"
+msgstr "isMoving"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "0"
+msgstr "0"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "X"
+msgstr "X"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220
+msgid "No transaction"
+msgstr "无事务"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:222
+msgid "Going through"
+msgstr "正在进行"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:224
+msgid "Blocked"
+msgstr "阻塞"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226
+msgid "Canceled"
+msgstr "取消"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:230
+msgid ""
+"Note that if you want to model things like for instance a CPU stage which "
+"can block and flush stuff, take a look a the CtrlLink, as it provides the "
+"API to do such things."
+msgstr ""
+"请注意，如果您想要建模诸如CPU级可能的阻塞和刷新的情况，可以查看 CtrlLink，因"
+"为它提供了执行此类操作的 API。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:232
+msgid "You can access signals referenced by a Payload via:"
+msgstr "您可以通过以下方式访问由Payload引用的信号："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:240
+msgid "node(Payload)"
+msgstr "node(Payload)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:241
+msgid "Return the corresponding hardware signal"
+msgstr "返回对应的硬件信号"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:242
+msgid "node(Payload, Any)"
+msgstr "node(Payload, Any)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:243
+msgid ""
+"Same as above, but include a second argument which is used as a \"secondary "
+"key\". This eases the construction of multi-lane hardware. For instance, "
+"when you have a multi issue CPU pipeline, you can use the lane Int id as "
+"secondary key"
+msgstr ""
+"与上述相同，但包括一个用作“次要键”的第二个参数。这有助于构建多通道硬件。例"
+"如，当您有一个多发射CPU流水线时，您可以使用通道Int id作为次要键"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:244
+msgid "node.insert(Data)"
+msgstr "node.insert(Data)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:245
+msgid ""
+"Return a new Payload instance which is connected to the given Data hardware "
+"signal"
+msgstr "返回一个新的Payload实例，该实例连接到给定的Data硬件信号"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:261
+msgid ""
+"While you can manualy drive/read the arbitration/data of the first/last "
+"stage of your pipeline, there is a few utilities to connect its boundaries."
+msgstr ""
+"虽然您可以手动驱动/读取流水线的第一个/最后一级的仲裁/数据，但有一些实用工具可"
+"以连接其边界。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:270
+msgid "node.arbitrateFrom(Stream[T]])"
+msgstr "node.arbitrateFrom(Stream[T]])"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:271
+msgid "Drive a node arbitration from a stream."
+msgstr "由反压流驱动节点仲裁。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:272
+msgid "node.arbitrateFrom(Flow[T]])"
+msgstr "node.arbitrateFrom(Flow[T]])"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:273
+msgid "Drive a node arbitration from the Flow."
+msgstr "由数据流驱动节点仲裁。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:274
+msgid "node.arbitrateTo(Stream[T]])"
+msgstr "node.arbitrateTo(Stream[T]])"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:275
+msgid "Drive a stream arbitration from the node."
+msgstr "由节点驱动反压流仲裁。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:276
+msgid "node.arbitrateTo(Flow[T]])"
+msgstr "node.arbitrateTo(Flow[T]])"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:277
+msgid "Drive a Flow arbitration from the node."
+msgstr "由节点驱动数据流仲裁。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:278
+msgid "node.driveFrom(Stream[T]])((Node, T) => Unit)"
+msgstr "node.driveFrom(Stream[T]])((Node, T) => Unit)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:279
+msgid ""
+"Drive a node from a stream. The provided lambda function can be use to "
+"connect the data"
+msgstr "由反压流驱动节点。提供的lambda函数可以用于连接数据"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:280
+msgid "node.driveFrom(Flow[T]])((Node, T) => Unit)"
+msgstr "node.driveFrom(Flow[T]])((Node, T) => Unit)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:281
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:285
+msgid "Same as above but for Flow"
+msgstr "与上述类似，但适用于Flow"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:282
+msgid "node.driveTo(Stream[T]])((T, Node) => Unit)"
+msgstr "node.driveTo(Stream[T]])((T, Node) => Unit)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:283
+msgid ""
+"Drive a stream from the node. The provided lambda function can be use to "
+"connect the data"
+msgstr "由节点驱动反压流。提供的lambda函数可以用于连接数据"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:284
+msgid "node.driveTo(Flow[T]])((T, Node) => Unit)"
+msgstr "node.driveTo(Flow[T]])((T, Node) => Unit)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:305
+msgid ""
+"In order to reduce verbosity, there is a set of implicit conversions between "
+"Payload toward their data representation which can be used when you are in "
+"the context of a Node :"
+msgstr ""
+"为了减少冗长，在Payload与其数据表示之间有一组隐式转换，可在Node下使用："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:314
+msgid "You can also use those implicit conversions by importing them :"
+msgstr "您还可以通过导入它们来使用这些隐式转换："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:327
+msgid ""
+"There is also an API which alows you to create new Area which provide the "
+"whole API of a given node instance (including implicit convertion) without "
+"import :"
+msgstr ""
+"还有一个API，它允许你创建新的Area，这个Area提供了给定节点实例的全部API（包括"
+"隐式转换），而无需导入："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:338
+msgid ""
+"Such feature is very useful when you have parametrizable pipeline locations "
+"for your hardware (see retiming example)."
+msgstr ""
+"当硬件具有可参数化的流水线位置时，这样的功能非常有用（请参阅重定时示例）。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:342
+msgid "Links"
+msgstr "Links"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:344
+msgid ""
+"There is few different Links already implemented (but you could also create "
+"your own custom one). The idea of Links is to connect two nodes together in "
+"various ways. They generally have a `up` Node and a `down` Node."
+msgstr ""
+"目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想"
+"是以各种方式将两个节点连接在一起，它们通常有一个 `up` 节点和一个 `down` 节"
+"点。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:349
+msgid "DirectLink"
+msgstr "DirectLink"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:351
+msgid "Very simple, it connect two nodes with wires only. Here is an example :"
+msgstr "非常简单，它只使用导线连接两个节点。以下是一个示例："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:361
+msgid "StageLink"
+msgstr "StageLink"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:363
+msgid ""
+"This connect two nodes using registers on the data / valid signals and some "
+"arbitration on the ready."
+msgstr "这使用data/valid信号上的寄存器和ready信号上的一些仲裁连接了两个节点。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:371
+msgid "S2mLink"
+msgstr "S2mLink"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:373
+msgid ""
+"This connect two nodes using registers on the ready signal, which can be "
+"useful to improve backpresure combinatorial timings."
+msgstr ""
+"这使用ready信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:380
+msgid "CtrlLink"
+msgstr "CtrlLink"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:382
+msgid ""
+"This is kind of a special Link, as connect two nodes with optional flow "
+"control / bypass logic. Its API should be flexible enough to implement a CPU "
+"stage with it."
+msgstr "这是一种特殊的 Link，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用"
+"程序接口应该足够灵活，可以用它来实现 CPU 流水级。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:384
+msgid "Here is its flow control API (The Bool arguments enable the features) :"
+msgstr "以下是其流量控制 API（Bool 参数启用了相关功能）："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:392
+msgid "haltWhen(Bool)"
+msgstr "haltWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:393
+msgid "Allows to block the current transaction (clear up.ready down.valid)"
+msgstr "允许阻止当前传输事务（清除 up.ready down.valid）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:394
+msgid "throwWhen(Bool)"
+msgstr "throwWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:395
+msgid ""
+"Allows to cancel the current transaction from the pipeline (clear down.valid "
+"and make the transaction driver forget its current state)"
+msgstr "允许从流水线中取消当前事务（清除 down.valid，使事务驱动逻辑忘记其当前状态）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:396
+msgid "forgetOneWhen(Bool)"
+msgstr "forgetOneWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:397
+msgid ""
+"Allows to request the upstream to forget its current transaction  (but "
+"doesn't clear the down.valid)"
+msgstr "允许请求上游节点忘记其当前事务（但不会清除 down.valid）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:398
+msgid "ignoreReadyWhen(Bool)"
+msgstr "ignoreReadyWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:399
+msgid "Allows to ignore the downstream ready (set up.ready)"
+msgstr "允许忽略下游节点ready（设置 up.ready 为1）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:400
+msgid "duplicateWhen(Bool)"
+msgstr "duplicateWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:401
+msgid "Allows to duplicate the current transaction (clear up.ready)"
+msgstr "允许复制当前传输事务（清零 up.ready）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:402
+msgid "terminateWhen(Bool)"
+msgstr "terminateWhen(Bool)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:403
+msgid ""
+"Allows to hide the current transaction from downstream (clear down.valid)"
+msgstr "允许下游节点隐藏当前传输事务（清零 down.valid）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:405
+msgid ""
+"Also note that if you want to do flow control in a conditional scope (ex in "
+"a when statement), you can call the following functions :"
+msgstr "还要注意的是，如果要在条件作用域（例如在 when 语句中）进行通信流控制，"
+"可以调用以下函数 ："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:407
+msgid ""
+"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), "
+"throwIt()"
+msgstr ""
+"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), "
+"throwIt()"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:419
+msgid ""
+"You can retrieve which nodes are connected to the Link using node.up / node."
+"down."
+msgstr "您可以使用 node.up / node.down 查看哪些节点连接到了链接。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:421
+msgid "The CtrlLink also provide an API to access Payload :"
+msgstr "CtrlLink 还提供了访问Payload的 API："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:429
+msgid "link(Payload)"
+msgstr "link(Payload)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:430
+msgid "Same as Link.down(Payload)"
+msgstr "与 Link.down(Payload) 相同"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:431
+msgid "link(Payload, Any)"
+msgstr "link(Payload, Any)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:432
+msgid "Same as Link.down(Payload, Any)"
+msgstr "与 Link.down(Payload, Any) 相同"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:433
+msgid "link.insert(Data)"
+msgstr "link.insert(Data)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:434
+msgid "Same as Link.down.insert(Data)"
+msgstr "与 Link.down.insert(Data) 相同"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:435
+msgid "link.bypass(Payload)"
+msgstr "link.bypass(Payload)"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436
+msgid ""
+"Allows to conditionaly override a Payload value between link.up -> link."
+"down. This can be used to fix data hazard in CPU pipelines for instance."
+msgstr "允许在 link.up -> link.down 之间有条件地覆盖 Payload 值。例如，这可用于修复 "
+"CPU 流水线中的数据冲突。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:455
+msgid ""
+"Note that if you create a CtrlLink without node arguments, it will create "
+"its own nodes internally."
+msgstr "请注意，如果创建的 CtrlLink 不带节点参数，它将在内部创建自己的节点。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:466
+msgid "Other Links"
+msgstr "其他链接"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:468
+msgid "There is also a JoinLink / ForkLink implemented."
+msgstr "此外，还实现了 JoinLink / ForkLink。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:471
+msgid "Your custom Link"
+msgstr "您的自定义链接"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:473
+msgid ""
+"You can implement your custom links by implementing the Link base class."
+msgstr "您可以通过实现 Link 基类来实现自定义链接。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:486
+msgid "But that API may change a bit, as it is still fresh."
+msgstr "不过，由于 API 还很新，后面可能会有一些变化。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:489
+msgid "Builder"
+msgstr "Builder"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:491
+msgid ""
+"To generate the hardware of your pipeline, you need to give a list of all "
+"the Links used in your pipeline."
+msgstr "要生成流水线硬件，您需要提供流水线中使用的所有链接列表。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:506
+msgid ""
+"There is also a set of \"all in one\" builders that you can instanciate to "
+"help yourself."
+msgstr "此外，还有一套 \"一体化 \"的构建工具，您可以利用它来帮助你自己。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:508
+msgid ""
+"For instance there is the NodesBuilder class which can be used to create "
+"sequentially staged pipelines :"
+msgstr "例如，有一个 NodesBuilder 类，可用于创建按顺序分级的流水线："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:521
+msgid "Composability"
+msgstr "组合能力（Composability）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:523
+msgid ""
+"One good thing about the API is that it easily allows to compose a pipeline "
+"with multiple parallel things. What i mean by \"compose\" is that sometime "
+"the pipeline you need to design has parallel processing to do."
+msgstr "该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的 \"组成 "
+"\"是指有时你设计的流水线需要进行并行处理。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:525
+msgid ""
+"Imagine you need to do floating point multiplication on 4 pairs of numbers "
+"(to later sum them). If those 4 pairs a provided at the same time by a "
+"single stream of data, then you don't want 4 different pipelines to multiply "
+"them, instead you want to process them all in parallel in the same pipeline."
+msgstr ""
+"试想一下，如果您需要对 4 对数字进行浮点乘法运算（稍后求和）。并且这 4 "
+"对数字是由一个数据流同时提供的，那么就不需要 4 "
+"条不同的流水线来进行乘法运算，而需要在同一条流水线上并行处理。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:527
+msgid ""
+"The example below show a pattern which composes a pipeline with multiple "
+"lanes to process them in parallel."
+msgstr "下面的示例展示了一种模式，它将多个通道组成一个流水线，来并行处理它们。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:571
+msgid ""
+"This will produce the following data path (assuming lanesCount = 2), "
+"abitration not being shown :"
+msgstr "这将产生以下数据路径（假设 lanesCount = 2），仲裁器没有显示："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:578
+msgid "Retiming / Variable lenth"
+msgstr "重定时/可变长度"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:580
+msgid ""
+"Sometime you want to design a pipeline, but you don't really know where the "
+"critical paths will be and what the right balance between stages is. And "
+"often you can't rely on the synthesis tool doing a good job with automatic "
+"retiming."
+msgstr "有时，你想设计一个流水线，但你并不真正知道关键路径在哪里，也不知道各阶段之间"
+"如何平衡。而且通常情况下，你无法依赖综合工具做好自动重定时工作。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:582
+msgid ""
+"So, you kind of need a easy way to move the logic of your pipeline around."
+msgstr "因此，你需要一种简单的方法来构建流水线逻辑。"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:584
+msgid "Here is how it can be done with this pipelining API :"
+msgstr "下面介绍如何使用此流水线 API："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:646
+msgid "If then you generate this component like this :"
+msgstr "如果像这样生成该组件："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:659
+msgid ""
+"You will get a 4 stages separated by 3 layer of flip flop doing your "
+"processing :"
+msgstr "您将获得由 3 层寄存器（flip flop）分隔的 4 个处理阶段："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:664
+msgid ""
+"Note the generated hardware verilog is kinda clean (by my standards at "
+"least :P) :"
+msgstr "请注意，生成的硬件 verilog 还算干净（至少按我的标准来说是这样 :P）："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:779
+msgid ""
+"Also, you can easily tweak how many stages and where you want the processing "
+"to be done, for instance you may want to move the inversion hardware in the "
+"same stage as the adder. This can be done the following way :"
+msgstr "此外，您还可以轻松调整处理的级数和位置，例如，您可能希望将翻转的硬件逻辑移到"
+"与加法器相同级上。具体方法如下："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:793
+msgid "Then you may want to remove the output register stage :"
+msgstr "那么您可能需要移除输出寄存器级："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:809
+msgid "Simple CPU example"
+msgstr "简单的CPU示例"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:811
+msgid "Here is a simple/stupid 8 bits CPU example with :"
+msgstr "下面是一个简单的 8 位 CPU 示例："
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:813
+msgid "3 stages (fetch, decode, execute)"
+msgstr "三级流水线（fetch, decode, execute）"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:814
+msgid "embedded fetch memory"
+msgstr "嵌入的获取存储器"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:815
+msgid "add / jump / led /delay instructions"
+msgstr "add / jump / led /delay 指令"
+
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:886
+msgid ""
+"Here is a simple testbench which implement a loop which will make the led "
+"counting up."
+msgstr "下面是一个简单的测试平台，它实现了一个循环，使 led 计数值上升。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/binarySystem.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/binarySystem.po
new file mode 100644
index 00000000000..e906ddc7426
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/binarySystem.po
@@ -0,0 +1,339 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbinarysystem/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:3
+msgid "BinarySystem"
+msgstr "二进制系统"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:6
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:8
+msgid ""
+"Here things have nothing to do with HDL, but they are very common in digital"
+" systems, In particular, the algorithm reference model is widely used. In "
+"addition, it is also used in build testbench."
+msgstr "这里的对象与HDL无关，但是它们在数字系统中很常见，尤其是算法参考模型被广泛使用"
+"。此外，它们还用于testbench的编写。"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:16
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:17
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:18
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:20
+msgid "**String**.asHex"
+msgstr "**String**.asHex"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:21
+msgid "HexString to BigInt == BigInt(string, 16)"
+msgstr "十六进制字符串转为BigInt == BigInt(string, 16)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:22
+#: ../../SpinalHDL/Libraries/binarySystem.rst:25
+#: ../../SpinalHDL/Libraries/binarySystem.rst:28
+#: ../../SpinalHDL/Libraries/binarySystem.rst:31
+#: ../../SpinalHDL/Libraries/binarySystem.rst:103
+#: ../../SpinalHDL/Libraries/binarySystem.rst:109
+#: ../../SpinalHDL/Libraries/binarySystem.rst:112
+#: ../../SpinalHDL/Libraries/binarySystem.rst:115
+msgid "BigInt"
+msgstr "BigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:23
+msgid "**String**.asDec"
+msgstr "**String**.asDec"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:24
+msgid "Decimal String to BigInt == BigInt(string, 10)"
+msgstr "十进制字符串转为BigInt == BigInt(string, 10)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:26
+msgid "**String**.asOct"
+msgstr "**String**.asOct"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:27
+msgid "Octal String to BigInt == BigInt(string, 8)"
+msgstr "八进制字符串转为BigInt == BigInt(string, 8)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:29
+msgid "**String**.asBin"
+msgstr "**String**.asBin"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:30
+msgid "Binary String to BigInt == BigInt(string, 2)"
+msgstr "二进制字符串转为BigInt == BigInt(string, 2)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:35
+msgid "**Byte|Int|Long|BigInt**.hexString()"
+msgstr "**Byte|Int|Long|BigInt**.hexString()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:36
+msgid "to HEX String"
+msgstr "转为十六进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:37
+#: ../../SpinalHDL/Libraries/binarySystem.rst:40
+#: ../../SpinalHDL/Libraries/binarySystem.rst:43
+#: ../../SpinalHDL/Libraries/binarySystem.rst:46
+#: ../../SpinalHDL/Libraries/binarySystem.rst:49
+#: ../../SpinalHDL/Libraries/binarySystem.rst:52
+#: ../../SpinalHDL/Libraries/binarySystem.rst:85
+#: ../../SpinalHDL/Libraries/binarySystem.rst:88
+#: ../../SpinalHDL/Libraries/binarySystem.rst:91
+#: ../../SpinalHDL/Libraries/binarySystem.rst:94
+msgid "String"
+msgstr "String"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:38
+msgid "**Byte|Int|Long|BigInt**.octString()"
+msgstr "**Byte|Int|Long|BigInt**.octString()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:39
+msgid "to Oct String"
+msgstr "转为十进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:41
+msgid "**Byte|Int|Long|BigInt**.binString()"
+msgstr "**Byte|Int|Long|BigInt**.binString()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:42
+msgid "to Bin String"
+msgstr "转为二进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:44
+msgid "**Byte|Int|Long|BigInt**.hexString(bitSize)"
+msgstr "**Byte|Int|Long|BigInt**.hexString(bitSize)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:45
+msgid "first align to bit Size, then to HEX String"
+msgstr "首先对齐位大小，然后转为十六进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:47
+msgid "**Byte|Int|Long|BigInt**.octString(bitSize)"
+msgstr "**Byte|Int|Long|BigInt**.octString(bitSize)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:48
+msgid "first align to bit Size, then to Oct String"
+msgstr "首先对齐位大小，然后转为八进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:50
+msgid "**Byte|Int|Long|BigInt**.binString(bitSize)"
+msgstr "**Byte|Int|Long|BigInt**.binString(bitSize)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:51
+msgid "first align to bit Size, then to Bin String"
+msgstr "首先对齐位大小，然后转为二进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:56
+msgid "**Byte|Int|Long|BigInt**.toBinInts()"
+msgstr "**Byte|Int|Long|BigInt**.toBinInts()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:57
+msgid "to BinaryList"
+msgstr "转为二进制列表(BinaryList)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:58
+#: ../../SpinalHDL/Libraries/binarySystem.rst:61
+#: ../../SpinalHDL/Libraries/binarySystem.rst:64
+#: ../../SpinalHDL/Libraries/binarySystem.rst:67
+#: ../../SpinalHDL/Libraries/binarySystem.rst:70
+#: ../../SpinalHDL/Libraries/binarySystem.rst:73
+#: ../../SpinalHDL/Libraries/binarySystem.rst:76
+#: ../../SpinalHDL/Libraries/binarySystem.rst:79
+msgid "List[Int]"
+msgstr "List[Int]"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:59
+msgid "**Byte|Int|Long|BigInt**.toDecInts()"
+msgstr "**Byte|Int|Long|BigInt**.toDecInts()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:60
+msgid "to DecimalList"
+msgstr "转为十进制列表(DecimalList)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:62
+msgid "**Byte|Int|Long|BigInt**.toOctInts()"
+msgstr "**Byte|Int|Long|BigInt**.toOctInts()"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:63
+msgid "to OctalList"
+msgstr "转为八进制列表(OctalList)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:65
+msgid "**Byte|Int|Long|BigInt**.toBinInts(num)"
+msgstr "**Byte|Int|Long|BigInt**.toBinInts(num)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:66
+msgid "to BinaryList, align to num size and fill 0"
+msgstr "转为二进制列表(BinaryList)，对齐到num参数大小并填充0"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:68
+msgid "**Byte|Int|Long|BigInt**.toDecInts(num)"
+msgstr "**Byte|Int|Long|BigInt**.toDecInts(num)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:69
+msgid "to DecimalList, align to num size and fill 0"
+msgstr "转为十进制列表(DecimalList)，对齐到num参数大小并填充0"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:71
+msgid "**Byte|Int|Long|BigInt**.toOctInts(num)"
+msgstr "**Byte|Int|Long|BigInt**.toOctInts(num)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:72
+msgid "to OctalList, align to num size and fill 0"
+msgstr "转为八进制列表(OctalList)，对齐到num参数大小并填充0"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:74
+msgid "**\"3F2A\"**.hexToBinInts"
+msgstr "**\"3F2A\"**.hexToBinInts"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:75
+msgid "Hex String to BinaryList"
+msgstr "十六进制字符串转为二进制列表"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:77
+msgid "**\"3F2A\"**.hexToBinIntsAlign"
+msgstr "**\"3F2A\"**.hexToBinIntsAlign"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:78
+msgid "Hex String to BinaryList Align to times of 4"
+msgstr "十六进制字符串转为二进制列表，并对齐到4的倍数大小"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:83
+msgid "**List(1,0,1,0,...)**.binIntsToHex"
+msgstr "**List(1,0,1,0,...)**.binIntsToHex"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:84
+msgid "BinaryList to HexString"
+msgstr "二进制列表转为十六进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:86
+msgid "**List(1,0,1,0,...)**.binIntsToOct"
+msgstr "**List(1,0,1,0,...)**.binIntsToOct"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:87
+msgid "BinaryList to OctString"
+msgstr "二进制列表转为八进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:89
+msgid "**List(1,0,1,0,...)**.binIntsToHexAlignHigh"
+msgstr "**List(1,0,1,0,...)**.binIntsToHexAlignHigh"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:90
+msgid "BinaryList size align to times of 4 (fill 0) then to HexString"
+msgstr "二进制列表大小对齐到4的倍数（填充 0），然后转为十六进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:92
+msgid "**List(1,0,1,0,...)**.binIntsToOctAlignHigh"
+msgstr "**List(1,0,1,0,...)**.binIntsToOctAlignHigh"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:93
+msgid "BinaryList size align to times of 3 (fill 0) then to HexString"
+msgstr "二进制列表大小对齐到3的倍数（填充 0），然后转为十六进制字符串"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:95
+msgid "**List(1,0,1,0,...)**.binIntsToInt"
+msgstr "**List(1,0,1,0,...)**.binIntsToInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:96
+msgid "BinaryList (maxSize 32) to Int"
+msgstr "二进制列表(最大数目为32)转为Int"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:97
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:98
+msgid "**List(1,0,1,0,...)**.binIntsToLong"
+msgstr "**List(1,0,1,0,...)**.binIntsToLong"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:99
+msgid "BinaryList (maxSIZE 64) to Long"
+msgstr "二进制列表(最大数目为64)转为Long"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:100
+msgid "Long"
+msgstr "Long"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:101
+msgid "**List(1,0,1,0,...)**.binIntsToBigInt"
+msgstr "**List(1,0,1,0,...)**.binIntsToBigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:102
+msgid "BinaryList (size no restrictions) to BigInt"
+msgstr "二进制列表（数目无限制）转为BigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:107
+msgid "**Int**.toBigInt"
+msgstr "**Int**.toBigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:108
+msgid "32.toBigInt == BigInt(32)"
+msgstr "32.toBigInt == BigInt(32)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:110
+msgid "**Long**.toBigInt"
+msgstr "**Long**.toBigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:111
+msgid "3233113232L.toBigInt == BigInt(3233113232L)"
+msgstr "3233113232L.toBigInt == BigInt(3233113232L)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:113
+msgid "**Byte**.toBigInt"
+msgstr "**Byte**.toBigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:114
+msgid "8.toByte.toBigInt == BigInt(8.toByte)"
+msgstr "8.toByte.toBigInt == BigInt(8.toByte)"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:118
+msgid "String to Int/Long/BigInt"
+msgstr "String转为Int/Long/BigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:134
+msgid "Int/Long/BigInt to String"
+msgstr "Int/Long/BigInt转为String"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:155
+msgid "Int/Long/BigInt to Binary-List"
+msgstr "Int/Long/BigInt转为二进制列表"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:174
+msgid "align to a fixed width"
+msgstr "对齐到固定位宽"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:187
+msgid "Binary-List to Int/Long/BigInt"
+msgstr "二进制列表转为Int/Long/BigInt"
+
+#: ../../SpinalHDL/Libraries/binarySystem.rst:215
+msgid "BigInt enricher"
+msgstr "BigInt放大器"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/bus_slave_factory.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/bus_slave_factory.po
new file mode 100644
index 00000000000..6ecc0e357a2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/bus_slave_factory.po
@@ -0,0 +1,308 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-10 17:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesbus_slave_factory/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:7
+msgid "Bus Slave Factory"
+msgstr "总线从端生成器"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:12
+msgid ""
+"In many situation it's needed to implement a bus register bank. The "
+"``BusSlaveFactory`` is a tool that provide an abstract and smooth way to "
+"define them."
+msgstr "在许多情况下，需要实现总线寄存器组， ``BusSlaveFactory`` "
+"是一个提供了一种抽象且流畅的方式来定义它们的工具。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:14
+msgid ""
+"To see capabilities of the tool, an simple example use the Apb3SlaveFactory "
+"variation to implement an :ref:`memory mapped UART <memory_mapped_uart>`. "
+"There is also another example with an :ref:`Timer <timer>` which contain a "
+"memory mapping function."
+msgstr ""
+"要了解该工具的功能，可以通过一个简单的使用Apb3SlaveFactory变体来实现 :ref:`"
+"内存映射UART <memory_mapped_uart>` 的示例。还有另一个 :ref:`计时器 <timer>` "
+"的示例，其中包含内存映射函数。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:16
+msgid ""
+"You can find more documentation about the internal implementation of the "
+"``BusSlaveFactory`` tool :ref:`there <bus_slave_factory_implementation>`"
+msgstr ""
+"您可以在 :ref:`这里 <bus_slave_factory_implementation>` 找到有关 "
+"``BusSlaveFactory`` 工具内部实现的更多文档"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:19
+msgid "Functionality"
+msgstr "功能"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:21
+msgid ""
+"There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, "
+"APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and "
+"PipelinedMemoryBus."
+msgstr ""
+"有许多 ``BusSlaveFactory`` 工具的实现：AHB3-lite、APB3、APB4、AvalonMM、AXI-"
+"lite 3、AXI4、BMB、Wishbone 和 PipelinedMemoryBus。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:22
+msgid ""
+"Each implementation of that tool take as an argument one instance of the "
+"corresponding bus and then offers the following functions to map your "
+"hardware into the memory mapping :"
+msgstr "该工具的每个实现都接受相应总线的一个实例作为参数，然后提供以下函数，用于将您"
+"的硬件映射到内存映射："
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:28
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:29
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:30
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:31
+msgid "busDataWidth"
+msgstr "busDataWidth"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:32
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:33
+msgid "Return the data width of the bus"
+msgstr "返回总线的数据宽度"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:34
+msgid "read(that,address,bitOffset)"
+msgstr "read(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:36
+msgid ""
+"When the bus read the ``address``\\ , fill the response with ``that`` at "
+"``bitOffset``"
+msgstr "当通过总线读取地址 ``address`` 时，用 ``that`` 中 ``bitOffset`` "
+"位置的数据填充响应"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:37
+msgid "write(that,address,bitOffset)"
+msgstr "write(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:39
+msgid ""
+"When the bus write the ``address``\\ , assign ``that`` with bus's data from "
+"``bitOffset``"
+msgstr "当通过总线写入地址 ``address`` 时，将总线上 ``bitOffset`` 位置的数据赋值 "
+"``that``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:40
+msgid "onWrite(address)(doThat)"
+msgstr "onWrite(address)(doThat)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:42
+msgid "Call ``doThat`` when a write transaction occur on ``address``"
+msgstr "当 ``address`` 地址上发生写操作（出现写事务）时调用 ``doThat``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:43
+msgid "onRead(address)(doThat)"
+msgstr "onRead(address)(doThat)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:45
+msgid "Call ``doThat`` when a read transaction occur on ``address``"
+msgstr "当 ``address`` 上发生读操作（出现读事务）时调用 ``doThat``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:46
+msgid "nonStopWrite(that,bitOffset)"
+msgstr "nonStopWrite(that,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:48
+msgid "Permanently assign ``that`` by the bus write data from ``bitOffset``"
+msgstr "将通过总线写入的 ``bitOffset`` 的数据赋值到 ``that``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:49
+msgid "readAndWrite(that,address,bitOffset)"
+msgstr "readAndWrite(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:51
+msgid ""
+"Make ``that`` readable and writable at ``address`` and placed at "
+"``bitOffset`` in the word"
+msgstr "使 ``that`` 信号可通过 ``address`` 地址读写，并且该信号放置在数据的 "
+"``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:52
+msgid "readMultiWord(that,address)"
+msgstr "readMultiWord(that,address)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "Create the memory mapping to read ``that`` from 'address'."
+msgstr "创建内存映射以从 'address' 读取 ``that`` 。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid ""
+"If ``that`` is bigger than one word it extends the register on followings "
+"addresses"
+msgstr "如果 ``that`` 的位宽大于一个字（32位），它将在以下地址上扩展寄存器"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:56
+msgid "writeMultiWord(that,address)"
+msgstr "writeMultiWord(that,address)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "Create the memory mapping to write ``that`` at 'address'."
+msgstr "创建内存映射以在 'address' 处写入 ``that`` 。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:60
+msgid "createWriteOnly(dataType,address,bitOffset)"
+msgstr "createWriteOnly(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:61
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:64
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:62
+msgid ""
+"Create a write only register of type ``dataType`` at ``address`` and placed "
+"at ``bitOffset`` in the word"
+msgstr "在 ``address`` 地址处创建一个 ``dataType`` 类型的只写寄存器，"
+"并将其放置在字中的 ``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:63
+msgid "createReadWrite(dataType,address,bitOffset)"
+msgstr "createReadWrite(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:65
+msgid ""
+"Create a read write register of type ``dataType`` at ``address`` and placed "
+"at ``bitOffset`` in the word"
+msgstr "在 ``address`` 处创建一个 ``dataType`` 类型的读写寄存器，并将其放置在字中的 "
+"``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:66
+msgid "createAndDriveFlow(dataType,address,bitOffset)"
+msgstr "createAndDriveFlow(dataType,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:67
+msgid "Flow[T]"
+msgstr "Flow[T]"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:68
+msgid ""
+"Create a writable Flow register of type ``dataType`` at ``address`` and "
+"placed at ``bitOffset`` in the word"
+msgstr ""
+"在 ``address`` 地址处创建一个 ``dataType`` 类型的可写流（Flow）寄存器，"
+"并将其放置在字中的 ``bitOffset`` 位置"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:69
+msgid "drive(that,address,bitOffset)"
+msgstr "drive(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:71
+msgid ""
+"Drive ``that`` with a register writable at ``address`` placed at "
+"``bitOffset`` in the word"
+msgstr "使用位于 ``address`` 地址的可写寄存器中 ``bitOffset`` 位置的信号驱动 ``that``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:72
+msgid "driveAndRead(that,address,bitOffset)"
+msgstr "driveAndRead(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:74
+msgid ""
+"Drive ``that`` with a register writable and readable at ``address`` placed "
+"at ``bitOffset`` in the word"
+msgstr "使用位于 ``address`` 地址的可读写寄存器中 ``bitOffset`` 位置的信号驱动 "
+"``that``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:75
+msgid "driveFlow(that,address,bitOffset)"
+msgstr "driveFlow(that,address,bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:77
+msgid ""
+"Emit on ``that`` a transaction when a write happen at ``address`` by using "
+"data placed at ``bitOffset`` in the word"
+msgstr "当对 ``address`` 地址写入时，通过使用位于 ``bitOffset`` 位的数据，在 ``that``"
+" 流（Flow）上发出事务"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "readStreamNonBlocking(that,"
+msgstr "readStreamNonBlocking(that,"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "address,"
+msgstr "address,"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "validBitOffset,"
+msgstr "validBitOffset,"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "payloadBitOffset)"
+msgstr "payloadBitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid ""
+"Read ``that`` and consume the transaction when a read happen at ``address``."
+msgstr "读取 ``that`` 信号并在读取 ``address`` 地址时消耗事务。"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "valid <= validBitOffset bit"
+msgstr "valid <= validBitOffset bit"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid ""
+"payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+msgstr ""
+"payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "doBitsAccumulationAndClearOnRead(that,"
+msgstr "doBitsAccumulationAndClearOnRead(that,"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "bitOffset)"
+msgstr "bitOffset)"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "Instantiate an internal register which at each cycle do :"
+msgstr "实例化一个内部寄存器，该寄存器在每个周期执行以下操作："
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid "reg := reg | that"
+msgstr "reg := reg | that"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst
+msgid ""
+"Then when a read occur, the register is cleared. This register is readable "
+"at ``address`` and placed at ``bitOffset`` in the word"
+msgstr "然后，当发生读取时，寄存器被清除。该寄存器可通过 ``address`` 地址读取，"
+"并放置在字中的 ``bitOffset`` 位置"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po
new file mode 100644
index 00000000000..65aa3f17e34
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po
@@ -0,0 +1,182 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesfiber/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:7
+msgid "Fiber framework"
+msgstr "纤程框架"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:10
+msgid ""
+"This framework is not expected to be used for general RTL generation and "
+"targets large system design management and code generation. It is currently "
+"used as toplevel integration tool in SaxonSoC."
+msgstr "该框架设计目标不是用于一般 RTL 生成，而是针对大型系统设计管理和代码生成。"
+"它目前在 SaxonSoC 中用作顶级集成工具。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:13
+msgid "Currently in developpement."
+msgstr "目前正在开发中。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:15
+msgid ""
+"The Fiber to run the hardware elaboration in a out of order manner, a bit "
+"similarly to Makefile, where you can define rules and dependencies which "
+"will then be solved when you run a make command. It is very similar to the "
+"Scala Future feature."
+msgstr ""
+"纤程(Fiber)以乱序的方式运行硬件生成，有点类似于Makefile，您可以在其中定义规则"
+"和依赖关系，然后在运行make命令时解决这些依赖关系。这与Scala "
+"Future功能非常相似。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:17
+msgid ""
+"Using this framework can complicate simple things but provide some strong "
+"features for complex cases :"
+msgstr "使用这个框架可能会使简单的事情复杂化，但为复杂的情况提供了一些强大的功能："
+
+#: ../../SpinalHDL/Libraries/fiber.rst:19
+msgid ""
+"You can define things before even knowing all their requirements, ex : "
+"instantiating a interruption controller, before knowing how many interrupt "
+"signal lines you need"
+msgstr "您甚至可以在知道所有要求之前就定义事物，例如：在知道需要多少中断信号线之前实"
+"例化中断控制器"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:21
+msgid ""
+"Abstract/lazy/partial SoC architecture definition allowing the creation of "
+"SoC template for further specialisations"
+msgstr "抽象/懒惰化/部分化SoC架构定义，允许创建SoC模板以供进一步专门化"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:22
+msgid ""
+"Automatic requirement negotiation between multiple agents in a decentralized"
+" way, ex : between masters and slaves of a memory bus"
+msgstr "以分散方式在多个代理之间自动进行需求协商，例如：内存总线的主设备和从设备之间"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:24
+msgid "The framework is mainly composed of :"
+msgstr "该框架主要由以下部分组成："
+
+#: ../../SpinalHDL/Libraries/fiber.rst:26
+msgid "``Handle[T]``, which can be used later to store a value of type ``T``."
+msgstr "``Handle[T]``，稍后可用于存储 ``T`` 类型的值。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:27
+msgid ""
+"``handle.load`` which allow to set the value of a handle (will reschedule "
+"all tasks waiting on it)"
+msgstr "``handle.load`` 允许设置句柄的值（将启动等待它的所有任务）"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:28
+msgid ""
+"``handle.get``, which return the value of the given handle. Will block the "
+"task execution if that handle isn't loaded yet"
+msgstr "``handle.get``，返回给定句柄的值。如果尚未加载该句柄，将阻止任务执行进入等待"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:29
+msgid ""
+"``Handle{ /*code*/ }``, which fork a new task which will execute the given "
+"code. The result of that code will be loaded into the Handle"
+msgstr "``Handle{ /*code*/ "
+"}``，它派生一个新任务来执行给定的代码。该代码的结果将被加载到句柄中"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:30
+msgid ""
+"``soon(handle)``, which allows the current task to announce that it will "
+"load ``handle`` with a value (used for scheduling)"
+msgstr "``soon(handle)``，允许当前任务宣称它将加载 一个 ``handle`` 句柄（用于调度）"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:34
+msgid "Simple dummy example"
+msgstr "简单的示例"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:36
+msgid "There is a simple example :"
+msgstr "这是一个简单的例子："
+
+#: ../../SpinalHDL/Libraries/fiber.rst:59
+msgid "Its runtime will be :"
+msgstr "它的运行步骤会是："
+
+#: ../../SpinalHDL/Libraries/fiber.rst:61
+msgid "create a and b"
+msgstr "创建a和b"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:62
+msgid "fork the calculator task, but is blocked when executing a.get"
+msgstr "创建计算器任务分支，但在执行a.get时被阻塞"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:63
+msgid "fork the printer task, but is blocked when executing calculator.get"
+msgstr "创建打印任务分支，但在执行calculator.get时被阻塞"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:64
+msgid ""
+"load a and b, which reschedule the calculator task (as it was waiting on a)"
+msgstr "加载a和b，这会重新调度计算器任务（因为它正在等待 a）"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:65
+msgid ""
+"calculator do its a + b sum, and load its Handle with that result, which "
+"reschedule the printer task"
+msgstr "计算器执行a+b求和操作，并将结果加载到其句柄，这将重新调度打印任务"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:66
+msgid "printer task print its stuff"
+msgstr "打印任务打印其结果"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:67
+msgid "everything done"
+msgstr "完成所有任务"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:70
+msgid ""
+"So, the main point of that example is to show that we kind of overcome the "
+"sequential execution of things, as a and b are loaded after the definition "
+"of the calculator."
+msgstr "因此，该示例的要点是表明我们在某种程度上克服了顺序执行，因为a和b可以在计算器"
+"定义之后被加载。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:74
+msgid "Handle[T]"
+msgstr "Handle[T]"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:76
+msgid ""
+"Handle[T] are a bit like scala's Future[T], they allow to talk about "
+"something before it is even existing, and wait on it."
+msgstr "Handle[T]有点像scala的Future[T]，它们允许在某个对象存在之前就谈及它，并等待它"
+"。"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:87
+msgid "soon(handle)"
+msgstr "soon(handle)"
+
+#: ../../SpinalHDL/Libraries/fiber.rst:89
+msgid ""
+"In order to maintain a proper graph of dependencies between tasks and "
+"Handle, a task can specify in advance that it will load a given handle. This"
+" is very usefull in case of a generation starvation/deadlock for SpinalHDL "
+"to report accuratly where is the issue."
+msgstr ""
+"为了维护任务和句柄之间正确的依赖关系图，任务可以预先指明它将加载给定的句柄。"
+"在生成饥饿(starvation)/死锁的情况下非常有用，以便SpinalHDL准确报告问题所在。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po
new file mode 100644
index 00000000000..66e0fcde4b3
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po
@@ -0,0 +1,258 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-25 03:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesflow/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/flow.rst:3
+msgid "Flow"
+msgstr "Flow"
+
+#: ../../SpinalHDL/Libraries/flow.rst:6
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Libraries/flow.rst:8
+msgid ""
+"The Flow interface is a simple valid/payload protocol which means the slave "
+"can't halt the bus. It could be used to represent data coming from an UART "
+"controller, requests to write an on-chip memory, etc."
+msgstr "数据流接口是一个简单的有效/负载协议，这意味着从端无法终止总线。它可用于表示来"
+"自UART控制器的数据、写入片上存储器的请求等。"
+
+#: ../../SpinalHDL/Libraries/flow.rst:15
+msgid "Signal"
+msgstr "信号"
+
+#: ../../SpinalHDL/Libraries/flow.rst:16
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/flow.rst:17
+msgid "Driver"
+msgstr "驱动"
+
+#: ../../SpinalHDL/Libraries/flow.rst:18 ../../SpinalHDL/Libraries/flow.rst:40
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/flow.rst:19
+msgid "Don't care when"
+msgstr "何时忽略"
+
+#: ../../SpinalHDL/Libraries/flow.rst:20
+msgid "valid"
+msgstr "valid"
+
+#: ../../SpinalHDL/Libraries/flow.rst:21
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Libraries/flow.rst:22 ../../SpinalHDL/Libraries/flow.rst:27
+msgid "Master"
+msgstr "Master"
+
+#: ../../SpinalHDL/Libraries/flow.rst:23
+msgid "When high => payload present on the interface"
+msgstr "当为高时 => 接口上存在有效负载(payload)"
+
+#: ../../SpinalHDL/Libraries/flow.rst:25
+msgid "payload"
+msgstr "payload"
+
+#: ../../SpinalHDL/Libraries/flow.rst:26 ../../SpinalHDL/Libraries/flow.rst:74
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Libraries/flow.rst:28
+msgid "Content of the transaction"
+msgstr "传输任务内容"
+
+#: ../../SpinalHDL/Libraries/flow.rst:29
+msgid "valid is low"
+msgstr "valid为低"
+
+#: ../../SpinalHDL/Libraries/flow.rst:33
+msgid "Functions"
+msgstr "函数"
+
+#: ../../SpinalHDL/Libraries/flow.rst:39
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Libraries/flow.rst:41
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/flow.rst:42
+msgid "Latency"
+msgstr "延迟"
+
+#: ../../SpinalHDL/Libraries/flow.rst:43
+msgid "Flow(type : Data)"
+msgstr "Flow(type : Data)"
+
+#: ../../SpinalHDL/Libraries/flow.rst ../../SpinalHDL/Libraries/flow.rst:44
+msgid "Create a Flow of a given type"
+msgstr "创建给定类型的数据流"
+
+#: ../../SpinalHDL/Libraries/flow.rst:45 ../../SpinalHDL/Libraries/flow.rst:50
+#: ../../SpinalHDL/Libraries/flow.rst:55 ../../SpinalHDL/Libraries/flow.rst:70
+msgid "Flow[T]"
+msgstr "Flow[T]"
+
+#: ../../SpinalHDL/Libraries/flow.rst:47
+msgid "master/slave Flow(type : Data)"
+msgstr "master/slave Flow(type : Data)"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "Initialized with corresponding in/out setup"
+msgstr "使用相应的输入/输出设置进行初始化"
+
+#: ../../SpinalHDL/Libraries/flow.rst:52
+msgid "x.m2sPipe()"
+msgstr "x.m2sPipe()"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "Return a Flow drived by x"
+msgstr "返回由x驱动的数据流"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "through a register stage that cut valid/payload paths"
+msgstr "通过寄存器级断开 valid/payload 路径（优化时序）"
+
+#: ../../SpinalHDL/Libraries/flow.rst:56 ../../SpinalHDL/Libraries/flow.rst:66
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "x << y"
+msgstr "x << y"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "y >> x"
+msgstr "y >> x"
+
+#: ../../SpinalHDL/Libraries/flow.rst:59
+msgid "Connect y to x"
+msgstr "将y连接到x"
+
+#: ../../SpinalHDL/Libraries/flow.rst:61 ../../SpinalHDL/Libraries/flow.rst:71
+msgid "0"
+msgstr "0"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "x <-< y"
+msgstr "x <-< y"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "y >-> x"
+msgstr "y >-> x"
+
+#: ../../SpinalHDL/Libraries/flow.rst:64
+msgid "Connect y to x through a m2sPipe"
+msgstr "通过m2sPipe将y连接到x"
+
+#: ../../SpinalHDL/Libraries/flow.rst:67
+msgid "x.throwWhen(cond : Bool)"
+msgstr "x.throwWhen(cond : Bool)"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "Return a Flow connected to x"
+msgstr "返回连接到x的数据流"
+
+#: ../../SpinalHDL/Libraries/flow.rst
+msgid "When cond is high, transaction are dropped"
+msgstr "当cond为高时，传输任务会被抛弃"
+
+#: ../../SpinalHDL/Libraries/flow.rst:72
+msgid "x.toReg()"
+msgstr "x.toReg()"
+
+#: ../../SpinalHDL/Libraries/flow.rst:73
+msgid "Return a register which is loaded with ``payload`` when valid is high"
+msgstr "当valid为高时，返回载有 ``payload`` 的寄存器"
+
+#: ../../SpinalHDL/Libraries/flow.rst:76
+msgid "x.setIdle()"
+msgstr "x.setIdle()"
+
+#: ../../SpinalHDL/Libraries/flow.rst:77
+msgid ""
+"Set the Flow in an Idle state: ``valid`` is ``False`` and don't care about "
+"``payload``."
+msgstr "将数据流设置为空闲状态：``valid`` 为``False`` ，同时不关心 ``payload`` 。"
+
+#: ../../SpinalHDL/Libraries/flow.rst:80
+msgid "x.push(newPayload: T)"
+msgstr "x.push(newPayload: T)"
+
+#: ../../SpinalHDL/Libraries/flow.rst:81
+msgid "Assign a new valid payload to the Flow. ``valid`` is set to ``True``."
+msgstr "为数据流分配一个新的有效负载。 ``valid`` 设置为 ``True`` 。"
+
+#: ../../SpinalHDL/Libraries/flow.rst:86
+msgid "Code example"
+msgstr "代码示例"
+
+#: ../../SpinalHDL/Libraries/flow.rst:94
+msgid "Simulation Support"
+msgstr "仿真支持"
+
+#: ../../SpinalHDL/Libraries/flow.rst:100
+msgid "Class"
+msgstr "类"
+
+#: ../../SpinalHDL/Libraries/flow.rst:101
+msgid "Usage"
+msgstr "用法"
+
+#: ../../SpinalHDL/Libraries/flow.rst:102
+msgid "FlowMonitor"
+msgstr "FlowMonitor"
+
+#: ../../SpinalHDL/Libraries/flow.rst:103
+msgid ""
+"Used for both master and slave sides, calls function with payload if Flow "
+"transmits data."
+msgstr "用于主端和从端，如果数据流传输数据，则调用带有负载的函数。"
+
+#: ../../SpinalHDL/Libraries/flow.rst:104
+msgid "FlowDriver"
+msgstr "FlowDriver"
+
+#: ../../SpinalHDL/Libraries/flow.rst:105
+msgid ""
+"Testbench master side, drives values by calling function to apply value (if "
+"available). Function must return if value was available. Supports random "
+"delays."
+msgstr "Testbench中主端通过调用函数来应用值（如果可用）以驱动值。如果值可用，则函数必"
+"须返回。支持随机的延迟。"
+
+#: ../../SpinalHDL/Libraries/flow.rst:106
+msgid "ScoreboardInOrder"
+msgstr "ScoreboardInOrder"
+
+#: ../../SpinalHDL/Libraries/flow.rst:107
+msgid "Often used to compare reference/dut data"
+msgstr "通常用于比较参考/dut数据"
+
+#~ msgid ""
+#~ "The Flow interface is a simple valid/payload protocol which mean the slave "
+#~ "can't halt the bus."
+#~ msgstr "Flow 接口是一个简单的有效/有效负载协议，这意味着从设备无法停止总线。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fragment.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fragment.po
new file mode 100644
index 00000000000..f9b56648201
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fragment.po
@@ -0,0 +1,209 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-25 03:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesfragment/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:3
+msgid "Fragment"
+msgstr "Fragment"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:6
+msgid "Specification"
+msgstr "规范"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:8
+msgid ""
+"The ``Fragment`` bundle is the concept of transmitting a \"big\" thing by "
+"using multiple \"small\" fragments. For examples :"
+msgstr "``Fragment`` 包是通过使用多个“小”片段来传输“大”东西的概念。比如 ："
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:11
+msgid ""
+"A picture transmitted with width*height transaction on a "
+"``Stream[Fragment[Pixel]]``"
+msgstr "一张通过 ``Stream[Fragment[Pixel]]`` 传输尺寸为 宽*高 的图片"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:12
+msgid ""
+"An UART packet received from an controller without flow control could be "
+"transmitted on a ``Flow[Fragment[Bits]]``"
+msgstr "一个可以在 ``Flow[Fragment[Bits]]`` 上传输的、"
+"从没有流量控制的控制器里接收到的 UART 数据包"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:13
+msgid ""
+"An AXI read burst could be carried by an "
+"``Stream[Fragment[AxiReadResponse]]``"
+msgstr "一个可以由 ``Stream[Fragment[AxiReadResponse]]`` 承载的AXI突发读"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:15
+msgid "Signals defined by the ``Fragment`` bundle are :"
+msgstr "``Fragment`` 包定义的信号是："
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:21
+msgid "Signal"
+msgstr "信号"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:22
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:23
+msgid "Driver"
+msgstr "驱动"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:24
+#: ../../source/SpinalHDL/Libraries/fragment.rst:51
+#: ../../source/SpinalHDL/Libraries/fragment.rst:77
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:25
+msgid "fragment"
+msgstr "fragment"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:26
+msgid "T"
+msgstr "T"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:27
+#: ../../source/SpinalHDL/Libraries/fragment.rst:31
+msgid "Master"
+msgstr "Master"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:28
+msgid "The \"payload\" of the current transaction"
+msgstr "当前传输任务的“负载”"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:29
+msgid "last"
+msgstr "last"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:30
+#: ../../source/SpinalHDL/Libraries/fragment.rst:53
+#: ../../source/SpinalHDL/Libraries/fragment.rst:56
+#: ../../source/SpinalHDL/Libraries/fragment.rst:59
+#: ../../source/SpinalHDL/Libraries/fragment.rst:62
+#: ../../source/SpinalHDL/Libraries/fragment.rst:65
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:32
+msgid "High when the fragment is the last of the current packet"
+msgstr "当该片段是当前数据包的最后一个片段时为高"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:35
+msgid ""
+"As you can see with this specification and precedent example, the "
+"``Fragment`` concept doesn't specify how transaction are transmitted (You "
+"can use Stream,Flow or any other communication protocol). It only add enough"
+" information (\\ ``last``\\ ) to know if the current transaction is the "
+"first one, the last one or one in the middle of a given packet."
+msgstr ""
+"正如您在本说明和先例中看到的， ``Fragment`` 概念并未指定传输任务如何传输（"
+"您可以使用 Stream、Flow 或任何其他通信协议）。它仅添加足够的信息(\\ ``last``"
+"\\ ) 来了解当前传输是给定数据包的第一个、最后一个还是中间的一个。"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:38
+msgid ""
+"The protocol didn't carry a \\'first\\' bit because it can be generated at "
+"any place by doing \\'RegNextWhen(bus.last, bus.fire) init(True)\\'"
+msgstr ""
+"该协议没有携带 \\'first\\' 位，因为它可以通过执行 \\'RegNextWhen(bus.last, "
+"bus.fire) init(True)\\' 被生成在任何位置"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:41
+msgid "Functions"
+msgstr "函数"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:43
+msgid ""
+"For ``Stream[Fragment[T]]`` and ``Flow[Fragment[T]]``\\ , following function"
+" are presents :"
+msgstr "对于 ``Stream[Fragment[T]]`` 和 ``Flow[Fragment[T]]`` ，给出以下函数："
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:49
+#: ../../source/SpinalHDL/Libraries/fragment.rst:75
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:50
+#: ../../source/SpinalHDL/Libraries/fragment.rst:76
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:52
+msgid "x.first"
+msgstr "x.first"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:54
+msgid ""
+"Return True when the next or the current transaction is/would be the first "
+"of a packet"
+msgstr "当当前或下一个传输是/将是数据包的第一个片段时返回 True"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:55
+msgid "x.tail"
+msgstr "x.tail"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:57
+msgid ""
+"Return True when the next or the current transaction is/would be not the "
+"first of a packet"
+msgstr "当当前或下一个传输不是数据包的第一个片段时返回 True"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:58
+msgid "x.isFirst"
+msgstr "x.isFirst"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:60
+msgid ""
+"Return True when an transaction is present and is the first of a packet"
+msgstr "当当前传输任务被提交并且为数据包的第一个片段时返回 True"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:61
+msgid "x.isTail"
+msgstr "x.isTail"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:63
+msgid ""
+"Return True when an transaction is present and is the not the first/last of "
+"a packet"
+msgstr "当当前传输任务被提交并且不是数据包的第一个/最后一个片段时返回 True"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:64
+msgid "x.isLast"
+msgstr "x.isLast"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:66
+msgid "Return True when an transaction is present and is the last of a packet"
+msgstr "当当前传输任务被提交并且为数据包的最后一个片段时返回 True"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:69
+msgid "For ``Stream[Fragment[T]]``\\ , following function are also accessible :"
+msgstr "对于 ``Stream[Fragment[T]]`` ，以下函数也是可用的："
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:78
+msgid "x.insertHeader(header : T)"
+msgstr "x.insertHeader(header : T)"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:79
+msgid "Stream[Fragment[T]]"
+msgstr "Stream[Fragment[T]]"
+
+#: ../../source/SpinalHDL/Libraries/fragment.rst:80
+msgid ""
+"Add the ``header`` to each packet on ``x`` and return the resulting bus"
+msgstr "对每个数据包 ``x`` 添加 ``header`` 并返回生成的总线"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po
new file mode 100644
index 00000000000..8a51630e0a1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po
@@ -0,0 +1,327 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-10 17:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesfsm/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:7
+msgid "State machine"
+msgstr "状态机"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:10
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:12
+msgid ""
+"In SpinalHDL you can define your state machine like in VHDL/Verilog, by "
+"using enumerations and switch/case statements. But in SpinalHDL you can also"
+" use a dedicated syntax."
+msgstr ""
+"在SpinalHDL中，您可以像在VHDL/Verilog中一样，通过使用枚举和switch/"
+"case语句来定义状态机。但在SpinalHDL中，您还可以使用专门的语句。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:14
+msgid "The state machine below is implemented in the following examples:"
+msgstr "下面的状态机在随后的示例中实现："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:20
+msgid "Style A:"
+msgstr "样式A："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:54
+msgid "Style B:"
+msgstr "样式B："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:92
+msgid "StateMachine"
+msgstr "StateMachine"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:94
+msgid "``StateMachine`` is the base class. It manages the logic of the FSM."
+msgstr "``StateMachine`` 是基类，它管理FSM的逻辑。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:102
+msgid "``StateMachine`` also provides some accessors:"
+msgstr "``StateMachine`` 还提供了一些访问器："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:108 ../../SpinalHDL/Libraries/fsm.rst:189
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:109
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:110 ../../SpinalHDL/Libraries/fsm.rst:190
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:111
+msgid "``isActive(state)``"
+msgstr "``isActive(state)``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:112 ../../SpinalHDL/Libraries/fsm.rst:115
+msgid "``Bool``"
+msgstr "``Bool``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:113
+msgid "Returns ``True`` when the state machine is in the given state"
+msgstr "当状态机处于给定状态时返回 ``True``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:114
+msgid "``isEntering(state)``"
+msgstr "``isEntering(state)``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:116
+msgid "Returns ``True`` when the state machine is entering the given state"
+msgstr "当状态机进入给定状态时返回 ``True``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:119
+msgid "Entry point"
+msgstr "入口点"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:121
+msgid ""
+"A state can be defined as the entry point of the state machine by extending "
+"the EntryPoint trait:"
+msgstr "通过扩展EntryPoint特征，可以将状态定义为状态机的入口点："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:127
+msgid "Or by using ``setEntry(state)``:"
+msgstr "或者使用 ``setEntry(state)`` ："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:135
+msgid "Transitions"
+msgstr "转换"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:137
+msgid ""
+"Transitions are represented by ``goto(nextState)``, which schedules the "
+"state machine to be in ``nextState`` the next cycle."
+msgstr "转换由 ``goto(nextState)`` 表示，它使状态机的状态在下一个周期转换到 "
+"``nextState`` 。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:138
+msgid ""
+"``exit()`` schedules the state machine to be in the boot state the next "
+"cycle (or, in ``StateFsm``, to exit the current nested state machine)."
+msgstr "``exit()`` 使状态机在下一个周期处于启动(boot)状态（或者，在 ``StateFsm`` "
+"中，退出当前的嵌套状态机）。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:140
+msgid ""
+"These two functions can be used inside state definitions (see below) or "
+"using ``always { yourStatements }``, which always applies "
+"``yourStatements``, with a priority over states."
+msgstr ""
+"这两个函数可以在状态定义中使用（见下文），或使用 ``always { yourStatements "
+"}`` ，这将始终应用 ``yourStatements``，并且优先级高于状态。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:144
+msgid "State encoding"
+msgstr "状态编码"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:146
+msgid ""
+"By default the FSM state vector will be encoded using the native encoding of"
+" the language/tools the RTL is generated for (Verilog or VHDL). This default"
+" can be overriden by using the ``setEncoding(...)`` method which either "
+"takes a ``SpinalEnumEncoding`` or varargs of type ``(State, BigInt)`` for a "
+"custom encoding."
+msgstr ""
+"默认情况下，FSM状态向量将使用（针对Verilog或VHDL）生成RTL的语言/工具的本地编"
+"码进行编码。可以通过使用 ``setEncoding(...)`` 函数覆盖此默认设置，该方法接收 "
+"``SpinalEnumEncoding`` 或类型为 ``(State, BigInt)`` "
+"的可变参数以进行自定义编码。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:150
+msgid "Using a ``SpinalEnumEncoding``"
+msgstr "使用 ``SpinalEnumEncoding``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:159
+msgid "Using a custom encoding"
+msgstr "使用自定义编码"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:169
+msgid ""
+"When using the ``graySequential`` enum encoding, no check is done to verify "
+"that the FSM transitions only produce single-bit changes in the state "
+"vector. The encoding is done according to the order of state definitions and"
+" the designer must ensure that only valid transitions are done if needed."
+msgstr ""
+"当使用 ``graySequential`` 枚举编码时，不会进行任何检查以验证FSM转换是否只在状"
+"态向量中产生单比特的变化。编码是根据状态定义的顺序完成的，设计者必须确保仅在"
+"需要时进行有效的转换。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:174
+msgid "States"
+msgstr "状态"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:176
+msgid "Multiple kinds of states can be used:"
+msgstr "可以使用多种类型的状态："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:178
+msgid "``State`` (the base one)"
+msgstr "``State`` （基础状态）"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:179
+msgid "``StateDelay``"
+msgstr "``StateDelay``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:180
+msgid "``StateFsm``"
+msgstr "``StateFsm``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:181
+msgid "``StateParallelFsm``"
+msgstr "``StateParallelFsm``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:183
+msgid ""
+"Each of them provides the following functions to define the logic associated"
+" to them:"
+msgstr "它们每个都提供了以下函数来定义与之相关的逻辑："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:196
+msgid ""
+"``yourStatements`` is applied when the state machine is not in ``state`` and"
+" will be in ``state`` the next cycle"
+msgstr "当状态机不在 ``state`` 状态，并且在下一个周期将处于 ``state`` 状态时，执行 "
+"``yourStatements``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:202
+msgid ""
+"``yourStatements`` is applied when the state machine is in ``state`` and "
+"will be in another state the next cycle"
+msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements`` "
+"，并且在下一个周期将处于另一个状态"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:208
+msgid "``yourStatements`` is applied when the state machine is in ``state``"
+msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements``"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:214
+msgid ""
+"``yourStatements`` is executed when the state machine will be in ``state`` "
+"the next cycle (even if it is already in it)"
+msgstr "当状态机在下一个周期处于 ``state`` 状态时， ``yourStatements`` "
+"被执行（即使它已经处于该状态）"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:216
+msgid "``state.`` is implicit in a ``new State`` block:"
+msgstr "``state.`` 隐含在 ``new State`` 块中："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:236
+msgid "StateDelay"
+msgstr "StateDelay（状态延迟）"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:238
+msgid ""
+"``StateDelay`` allows you to create a state which waits for a fixed number "
+"of cycles before executing statements in ``whenCompleted {...}``. The "
+"preferred way to use it is:"
+msgstr ""
+"``StateDelay`` 允许您创建一个状态，该状态在执行 ``whenCompleted {...}`` "
+"中的语句之前等待固定数量的周期。首选的使用方式是："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:248
+msgid "It can also be written in one line:"
+msgstr "也可以写成一行："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:255
+msgid "StateFsm"
+msgstr "StateFsm"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:257
+msgid ""
+"``StateFsm`` allows you to describe a state containing a nested state "
+"machine. When the nested state machine is done (exited), statements in "
+"``whenCompleted { ... }`` are executed."
+msgstr ""
+"``StateFsm`` 允许您描述一个包含嵌套状态机的状态。当嵌套状态机完成（退出）时，"
+"执行 ``whenCompleted { ... }`` 中的语句。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:259
+msgid "There is an example of StateFsm definition :"
+msgstr "这是一个StateFsm定义的示例："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:290
+msgid ""
+"In the example above, ``exit()`` makes the state machine jump to the boot "
+"state (a internal hidden state). This notifies ``StateFsm`` about the "
+"completion of the inner state machine."
+msgstr "在上面的示例中， ``exit()`` 使状态机跳转到启动状态（内部隐藏状态）。这将通知 "
+"``StateFsm`` 其内部状态机已经完成。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:293
+msgid "StateParallelFsm"
+msgstr "StateParallelFsm"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:295
+msgid ""
+"``StateParallelFsm`` allows you to handle multiple nested state machines. "
+"When all nested state machine are done, statements in ``whenCompleted { ... "
+"}`` are executed."
+msgstr ""
+"``StateParallelFsm`` 允许您处理多个嵌套状态机。当所有嵌套状态机完成时，执行 "
+"``whenCompleted { ... }`` 中的语句。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:297 ../../SpinalHDL/Libraries/fsm.rst:322
+msgid "Example:"
+msgstr "示例："
+
+#: ../../SpinalHDL/Libraries/fsm.rst:308
+msgid "Notes about the entry state"
+msgstr "关于入口状态的注释"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:310
+msgid ""
+"The way the entry state has been defined above makes it so that between the "
+"reset and the first clock sampling, the state machine is in a boot state. It"
+" is only after the first clock sampling that the defined entry state becomes"
+" active. This allows to properly enter the entry state (applying statements "
+"in ``onEntry``), and allows nested state machines."
+msgstr ""
+"上面定义入口状态的方式使得在复位和第一次时钟采样之间，状态机处于启动状态。只"
+"有在第一次时钟采样之后，定义的入口状态才会变为活动状态。这保证了能正确进入入"
+"口状态（在 ``onEntry`` 中应用语句），并支持嵌套状态机。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:312
+msgid ""
+"While it is usefull, it is also possible to bypass that feature and directly"
+" having a state machine booting into a user state."
+msgstr "虽然它很有用，但也可以绕过该功能并直接让状态机启动到用户状态。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:314
+msgid ""
+"To do so, use `makeInstantEntry()` instead of defining a ``new State``. This"
+" function returns the boot state, active directly after reset."
+msgstr "为此，请使用 `makeInstantEntry()` 而不是定义 ``new State`` "
+"。该函数返回启动状态，复位后直接激活。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:317
+msgid ""
+"The ``onEntry`` of that state will only be called when it transitions from "
+"another state to this state and not during boot."
+msgstr "该状态的 ``onEntry`` 仅在从另一个状态转换到该状态时调用，而不是在启动期间。"
+
+#: ../../SpinalHDL/Libraries/fsm.rst:320
+msgid "During simulation, the boot state is always named ``BOOT``."
+msgstr "在仿真过程中，启动状态始终命名为 ``BOOT`` 。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po
new file mode 100644
index 00000000000..363bb4f0910
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po
@@ -0,0 +1,75 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-20 16:13+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Libraries/index.rst:5
+msgid "Libraries"
+msgstr "模块库"
+
+#: ../../SpinalHDL/Libraries/index.rst:7
+msgid "The spinal.lib package goals are :"
+msgstr "spinal.lib包的目的是："
+
+#: ../../SpinalHDL/Libraries/index.rst:9
+msgid ""
+"Provide things that are commonly used in hardware design (FIFO, clock "
+"crossing bridges, useful functions)"
+msgstr "提供硬件设计中常用的模块（FIFO、跨时钟域桥、一些有用的函数）"
+
+#: ../../SpinalHDL/Libraries/index.rst:10
+msgid "Provide simple peripherals (UART, JTAG, VGA, ..)"
+msgstr "提供简单的外设(UART, JTAG, VGA, ..)"
+
+#: ../../SpinalHDL/Libraries/index.rst:11
+msgid "Provide some bus definition (Avalon, AMBA, ..)"
+msgstr "提供一些总线定义(Avalon, AMBA, ..)"
+
+#: ../../SpinalHDL/Libraries/index.rst:12
+msgid "Provide some methodology (Stream, Flow, Fragment)"
+msgstr "提供一些方法(Stream, Flow, Fragment)"
+
+#: ../../SpinalHDL/Libraries/index.rst:13
+msgid "Provide some example to get the spirit of spinal"
+msgstr "提供一些例子以理解spinal的精髓"
+
+#: ../../SpinalHDL/Libraries/index.rst:14
+msgid ""
+"Provide some tools and facilities (latency analyser, QSys converter, ...)"
+msgstr "提供一些工具和功能（延迟分析器、QSys转换器……）"
+
+#: ../../SpinalHDL/Libraries/index.rst:16
+msgid ""
+"To use features introduced in followings chapter you need, in most of cases,"
+" to ``import spinal.lib._`` in your sources."
+msgstr "要使用以下章节中介绍的特性，在大多数情况下，您需要使用 ``import spinal.lib."
+"_`` 在您的代码中。"
+
+#: ../../SpinalHDL/Libraries/index.rst
+msgid ""
+"This package is currently under construction. Documented features could be "
+"considered as stable."
+msgstr "该包目前正在建设中。文档中的特性可以被认为是稳定的。"
+
+#: ../../SpinalHDL/Libraries/index.rst
+msgid "Do not hesitate to use github for suggestions/bug/fixes/enhancements"
+msgstr "请不要犹豫，使用GitHub提供建议/错误/修复/增强等意见"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po
new file mode 100644
index 00000000000..456a8b817d2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po
@@ -0,0 +1,734 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-25 03:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesregif/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:3
+msgid "RegIf"
+msgstr "RegIf"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:5
+msgid "Register Interface Builder"
+msgstr "寄存器接口搭建器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:7
+msgid "Automatic address, fields allocation and conflict detection"
+msgstr "自动寻址、字段分配和冲突检测"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:8
+msgid ""
+"28 Register Access types (Covering the 25 types defined by the UVM standard)"
+msgstr "28种寄存器访问类型（涵盖UVM标准定义的25种类型）"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:9
+#: ../../SpinalHDL/Libraries/regIf.rst:112
+msgid "Automatic documentation generation"
+msgstr "自动生成文档"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:12
+msgid "Automatic allocation"
+msgstr "自动分配"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:14
+msgid "Automatic address allocation"
+msgstr "自动地址分配"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:39
+msgid "Automatic fileds allocation"
+msgstr "自动字段分配"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:54
+msgid "conflict detection"
+msgstr "冲突检测"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:70
+msgid "28 Access Types"
+msgstr "28种访问类型"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:72
+msgid "Most of these come from UVM specification"
+msgstr "其中大部分来自UVM规范"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+msgid "AccessType"
+msgstr "访问类型"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+#: ../../SpinalHDL/Libraries/regIf.rst:436
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:75
+msgid "From"
+msgstr "来源"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "RO"
+msgstr "RO"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+msgid "w: no effect, r: no effect"
+msgstr "w：无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:77
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid "UVM"
+msgstr "UVM"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "RW"
+msgstr "RW"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:78
+msgid "w: as-is, r: no effect"
+msgstr "w：保持原样，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+msgid "RC"
+msgstr "RC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:79
+msgid "w: no effect, r: clears all bits"
+msgstr "w：无影响，r：清除所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+msgid "RS"
+msgstr "RS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:80
+msgid "w: no effect, r: sets all bits"
+msgstr "w：无影响，r：置位所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+msgid "WRC"
+msgstr "WRC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:81
+msgid "w: as-is, r: clears all bits"
+msgstr "w：保持原样，r：清除所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+msgid "WRS"
+msgstr "WRS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:82
+msgid "w: as-is, r: sets all bits"
+msgstr "w：保持原样，r：置位所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+msgid "WC"
+msgstr "WC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:83
+msgid "w: clears all bits, r: no effect"
+msgstr "w：清除所有比特，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+msgid "WS"
+msgstr "WS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:84
+msgid "w: sets all bits, r: no effect"
+msgstr "w：置位所有比特，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+msgid "WSRC"
+msgstr "WSRC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:85
+msgid "w: sets all bits, r: clears all bits"
+msgstr "w：置位所有比特，r：清除所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+msgid "WCRS"
+msgstr "WCRS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:86
+msgid "w: clears all bits, r: sets all bits"
+msgstr "w：清除所有比特，r：置位所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "W1C"
+msgstr "W1C"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:87
+msgid "w: 1/0 clears/no effect on matching bit, r: no effect"
+msgstr "w：1/0 对匹配位清除/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+msgid "W1S"
+msgstr "W1S"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:88
+msgid "w: 1/0 sets/no effect on matching bit, r: no effect"
+msgstr "w：1/0 对匹配位置位/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+msgid "W1T"
+msgstr "W1T"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:89
+msgid "w: 1/0 toggles/no effect on matching bit, r: no effect"
+msgstr "w：1/0 对匹配位翻转/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+msgid "W0C"
+msgstr "W0C"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:90
+msgid "w: 1/0 no effect on/clears matching bit, r: no effect"
+msgstr "w：1/0 对匹配位清除/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+msgid "W0S"
+msgstr "W0S"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:91
+msgid "w: 1/0 no effect on/sets matching bit, r: no effect"
+msgstr "w：1/0 对匹配位置位/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+msgid "W0T"
+msgstr "W0T"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:92
+msgid "w: 1/0 no effect on/toggles matching bit, r: no effect"
+msgstr "w：1/0 对匹配位翻转/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+msgid "W1SRC"
+msgstr "W1SRC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:93
+msgid "w: 1/0 sets/no effect on matching bit, r: clears all bits"
+msgstr "w：1/0 对匹配位置位/无影响，r：清除所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+msgid "W1CRS"
+msgstr "W1CRS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:94
+msgid "w: 1/0 clears/no effect on matching bit, r: sets all bits"
+msgstr "w：1/0 对匹配位清除/无影响，r：置位所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+msgid "W0SRC"
+msgstr "W0SRC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:95
+msgid "w: 1/0 no effect on/sets matching bit, r: clears all bits"
+msgstr "w：1/0 对匹配位置位/无影响，r：清除所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+msgid "W0CRS"
+msgstr "W0CRS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:96
+msgid "w: 1/0 no effect on/clears matching bit, r: sets all bits"
+msgstr "w：1/0 对匹配位清除/无影响，r：置位所有比特"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+msgid "WO"
+msgstr "WO"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:97
+msgid "w: as-is, r: error"
+msgstr "w：保持原样，r：错误"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+msgid "WOC"
+msgstr "WOC"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:98
+msgid "w: clears all bits, r: error"
+msgstr "w：清除所有比特，r：错误"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+msgid "WOS"
+msgstr "WOS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:99
+msgid "w: sets all bits, r: error"
+msgstr "w：置位所有比特，r：错误"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+msgid "W1"
+msgstr "W1"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:100
+msgid ""
+"w: first one after hard reset is as-is, other w have no effects, r: no "
+"effect"
+msgstr "w：硬复位后第一个w保持原样，其他w无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid "WO1"
+msgstr "WO1"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:101
+msgid ""
+"w: first one after hard reset is as-is, other w have no effects, r: error"
+msgstr "w：硬复位后第一个w保持原样，其他w无影响，r：错误"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+msgid "NA"
+msgstr "NA"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+msgid "w: reserved, r: reserved"
+msgstr "w：保留，r：保留"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:102
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "New"
+msgstr "新的"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+msgid "W1P"
+msgstr "W1P"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:103
+msgid "w: 1/0 pulse/no effect on matching bit, r: no effect"
+msgstr "w：1/0 对匹配位脉冲(pulse)/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+msgid "W0P"
+msgstr "W0P"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:104
+msgid "w: 0/1 pulse/no effect on matching bit, r: no effect"
+msgstr "w：0/1 对匹配位脉冲(pulse)/无影响，r：无影响"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+msgid "HSRW"
+msgstr "HSRW"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:105
+msgid "w: Hardware Set, SoftWare RW"
+msgstr "w：硬件置位，软件RW"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+msgid "RWHS"
+msgstr "RWHS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:106
+msgid "w: SoftWare RW, Hardware Set"
+msgstr "w：软件RW、硬件置位"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+msgid "ROV"
+msgstr "ROV"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:107
+msgid "w: ReadOnly Value, used for hardware version"
+msgstr "w：只读值，用于硬件版本"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "CSTM"
+msgstr "CSTM"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:108
+msgid "w: user custom Type, used for document"
+msgstr "w：用户自定义类型，用于文档"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:114
+msgid "Document Type"
+msgstr "文档类型"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Document"
+msgstr "文档类型"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Usage"
+msgstr "用法"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:117
+msgid "Status"
+msgstr "状态"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+msgid "HTML"
+msgstr "HTML"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+msgid "``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``"
+msgstr ""
+"``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:119
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid "Y"
+msgstr "Y"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+msgid "CHeader"
+msgstr "CHeader"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:120
+msgid "``busif.accept(CHeaderGenerator(\"header\", \"AP\"))``"
+msgstr "``busif.accept(CHeaderGenerator(\"header\", \"AP\"))``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+msgid "JSON"
+msgstr "JSON"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:121
+msgid "``busif.accept(JsonGenerator(\"regif\"))``"
+msgstr "``busif.accept(JsonGenerator(\"regif\"))``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+msgid "RALF(UVM)"
+msgstr "RALF(UVM)"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:122
+msgid "``busif.accept(RalfGenerator(\"header\"))``"
+msgstr "``busif.accept(RalfGenerator(\"header\"))``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid "SystemRDL"
+msgstr "SystemRDL"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:123
+msgid ""
+"``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", "
+"Some(\"name\"), Some(\"desc\")))``"
+msgstr ""
+"``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", Some(\"name\")"
+", Some(\"desc\")))``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:124
+msgid "Latex(pdf)"
+msgstr "Latex(pdf)"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:124
+#: ../../SpinalHDL/Libraries/regIf.rst:125
+msgid "N"
+msgstr "N"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:125
+msgid "docx"
+msgstr "docx"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:128
+msgid "HTML auto-doc is now complete, Example source Code:"
+msgstr "HTM 自动文档现已完成，源代码示例："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:133
+msgid "generated HTML document:"
+msgstr "生成的 HTML 文档："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:139
+msgid "Special Access Usage"
+msgstr "特殊访问用途"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:141
+msgid "**CASE1:** ``RO`` usage"
+msgstr "**案例1：** ``RO`` 用法"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:143
+msgid ""
+"``RO`` is different from other types. It does not create registers and "
+"requires an external signal to drive it, Attention, please don't forget to "
+"drive it."
+msgstr "``RO`` 与其他类型不同。它不创建寄存器，需要外部信号来驱动它，注意，请不要忘记"
+"驱动它。"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:175
+msgid "**CASE2:** ``ROV`` usage"
+msgstr "**案例2：** ``ROV`` 用法"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:177
+msgid ""
+"ASIC design often requires some solidified version information. Unlike RO, "
+"it is not expected to generate wire signals"
+msgstr "ASIC设计常常需要一些固化的版本信息。与 RO 不同，它不会产生有线信号"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:179
+msgid "old way:"
+msgstr "旧方法："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:186
+msgid "new way:"
+msgstr "新方法："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:194
+msgid ""
+"**CASE3:** ``HSRW/RWHS`` hardware set type In some cases, such registers are"
+" not only configured by software, but also set by hardware signals"
+msgstr "**案例3:** ``HSRW/RWHS`` 在某些情况下的硬件设置类型，此类寄存器不仅可以由软件"
+"配置，还可以由硬件信号设置"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:231
+msgid ""
+"**CASE4:** ``CSTM`` Although SpinalHDL includes 25 register types and 6 "
+"extension types, there are still various demands for private register types "
+"in practical application. Therefore, we reserve CSTM types for scalability. "
+"CSTM is only used to generate software interfaces, and does not generate "
+"actual circuits"
+msgstr ""
+"**案例4:** ``CSTM`` 虽然SpinalHDL包含25种寄存器类型和6种扩展类型，但在实际应"
+"用中仍然对私有寄存器类型有各种需求。因此，我们保留CSTM类型以实现可扩展性。 "
+"CSTM仅用于生成软件接口，不生成实际电路"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:246
+msgid "**CASE5:** ``parasiteField``"
+msgstr "**案例5：** ``parasiteField``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:248
+msgid ""
+"This is used for software to share the same register on multiple address "
+"instead of generating multiple register entities"
+msgstr "这用于软件在多个地址上共享同一寄存器，而不是生成多个寄存器实体"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:250
+msgid "example1: clock gate software enable"
+msgstr "示例1：时钟门软件使能"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:262
+msgid "example2: interrupt raw reg with foce interface for software"
+msgstr "示例2：使用软件的带强制(force)接口的中断原始(raw)状态寄存器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:273
+msgid "Byte Mask"
+msgstr "字节掩码"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:275
+msgid "withStrb"
+msgstr "withStrb"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:279
+msgid "Typical Example"
+msgstr "典型例子"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:281
+msgid "Batch create REG-Address and fields register"
+msgstr "批量创建REG-Address和字段寄存器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:321
+msgid "Interrupt Factory"
+msgstr "中断生成器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:323
+msgid "Manual writing interruption"
+msgstr "手动写中断"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:366
+msgid ""
+"this is a very tedious and repetitive work, a better way is to use the "
+"\"factory\" paradigm to auto-generate the documentation for each signal."
+msgstr "这是一项非常繁琐且重复的工作，更好的方法是使用“生成器(factory)”范例来自动生成"
+"每个信号的文档。"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:368
+msgid "now the InterruptFactory can do that."
+msgstr "现在InterruptFactory可以做到这一点。"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:370
+msgid "Easy Way create interruption:"
+msgstr "创建中断的简单方法："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:394
+msgid "IP level interrupt Factory"
+msgstr "IP级中断生成器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:397
+#: ../../SpinalHDL/Libraries/regIf.rst:418
+msgid "Register"
+msgstr "寄存器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "RAW"
+msgstr "RAW"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:399
+msgid "int raw register, set by int event, clear when bus write 1"
+msgstr "中断原始状态(int raw)寄存器，由int事件设置，总线写1时清零"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+msgid "FORCE"
+msgstr "FORCE"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:400
+msgid "int force register, for SW debug use"
+msgstr "中断强制寄存器，用于软件调试"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "MASK"
+msgstr "MASK"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:401
+#: ../../SpinalHDL/Libraries/regIf.rst:420
+msgid "int mask register, 1: off; 0: open; defualt 1 int off"
+msgstr "中断掩码寄存器，1：关闭；0：打开；默认1 中断关闭"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "STATUS"
+msgstr "STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:402
+msgid "int status, Read Only, ``status = raw && ! mask``"
+msgstr "中断状态，只读， ``status = raw && ! mask``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:408
+#: ../../SpinalHDL/Libraries/regIf.rst:426
+msgid "SpinalUsage:"
+msgstr "Spinal用法："
+
+#: ../../SpinalHDL/Libraries/regIf.rst:415
+msgid "SYS level interrupt merge"
+msgstr "SYS级中断合并"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+msgid "int status, RO, ``status = int_level && ! mask``"
+msgstr "中断状态，RO， ``status = int_level && ! mask``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:433
+msgid "Spinal Factory"
+msgstr "Spinal的生成器"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:436
+msgid "BusInterface method"
+msgstr "总线接口方法"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:438
+#: ../../SpinalHDL/Libraries/regIf.rst:440
+msgid "``InterruptFactory(regNamePre: String, triggers: Bool*)``"
+msgstr "``InterruptFactory(regNamePre: String, triggers: Bool*)``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:438
+msgid "create RAW/FORCE/MASK/STATUS for pulse event"
+msgstr "为脉冲事件创建RAW/FORCE/MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:439
+msgid "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``"
+msgstr "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:439
+msgid "create RAW/MASK/STATUS for pulse event"
+msgstr "为脉冲事件创建RAW/MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:440
+msgid "create MASK/STATUS for level_int merge"
+msgstr "为level_int合并创建MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:441
+#: ../../SpinalHDL/Libraries/regIf.rst:443
+msgid ""
+"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
+msgstr ""
+"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:441
+msgid "create RAW/FORCE/MASK/STATUS for pulse event at addrOffset"
+msgstr "在addrOffset处为脉冲事件创建RAW/FORCE/MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:442
+msgid ""
+"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: "
+"Bool*)``"
+msgstr ""
+"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: "
+"Bool*)``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:442
+msgid "create RAW/MASK/STATUS for pulse event at addrOffset"
+msgstr "在addrOffset处为脉冲事件创建 RAW/MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:443
+msgid "create MASK/STATUS for level_int merge at addrOffset"
+msgstr "在addrOffset处为level_int合并创建MASK/STATUS"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:447
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:479
+msgid "DefaultReadValue"
+msgstr "默认读取值"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:481
+msgid ""
+"When the software reads a reserved address, the current policy is to return "
+"normally, readerror=0. In order to facilitate software debugging, the read "
+"back value can be configured, which is 0 by default"
+msgstr "当软件读取保留地址时，当前的策略是正常返回，readerror=0。为了方便软件调试，可"
+"以配置回读值，默认为0"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:499
+msgid "Developers Area"
+msgstr "开发者区域"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:501
+msgid "You can add your document Type by extending the `BusIfVistor` Trait"
+msgstr "您可以通过扩展 `BusIfVistor` 特征来添加文档类型"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:503
+msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``"
+msgstr "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``"
+
+#: ../../SpinalHDL/Libraries/regIf.rst:505
+msgid "BusIfVistor give access BusIf.RegInsts to do what you want"
+msgstr "BusIfVistor给予访问BusIf.RegInsts的权限来执行您想要的操作"
+
+#~ msgid "Interrupt Design Spec"
+#~ msgstr "中断设计规范"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po
new file mode 100644
index 00000000000..9a50baf60a9
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po
@@ -0,0 +1,924 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-25 03:01+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesstream/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/stream.rst:7
+msgid "Stream"
+msgstr "Stream"
+
+#: ../../SpinalHDL/Libraries/stream.rst:10
+msgid "Specification"
+msgstr "规范"
+
+#: ../../SpinalHDL/Libraries/stream.rst:12
+msgid "The Stream interface is a simple handshake protocol to carry payload."
+msgstr "反压数据流接口(Stream)是一个用于承载有效负载的简单握手协议。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:13
+msgid ""
+"It could be used for example to push and pop elements into a FIFO, send "
+"requests to a UART controller, etc."
+msgstr "例如，它可用于对FIFO推入和弹出数据、向UART控制器发送请求等。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:19
+msgid "Signal"
+msgstr "信号"
+
+#: ../../SpinalHDL/Libraries/stream.rst:20
+#: ../../SpinalHDL/Libraries/stream.rst:217
+#: ../../SpinalHDL/Libraries/stream.rst:232
+#: ../../SpinalHDL/Libraries/stream.rst:273
+#: ../../SpinalHDL/Libraries/stream.rst:294
+#: ../../SpinalHDL/Libraries/stream.rst:335
+#: ../../SpinalHDL/Libraries/stream.rst:353
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/stream.rst:21
+msgid "Driver"
+msgstr "驱动"
+
+#: ../../SpinalHDL/Libraries/stream.rst:22
+#: ../../SpinalHDL/Libraries/stream.rst:96
+#: ../../SpinalHDL/Libraries/stream.rst:218
+#: ../../SpinalHDL/Libraries/stream.rst:233
+#: ../../SpinalHDL/Libraries/stream.rst:274
+#: ../../SpinalHDL/Libraries/stream.rst:295
+#: ../../SpinalHDL/Libraries/stream.rst:336
+#: ../../SpinalHDL/Libraries/stream.rst:354
+#: ../../SpinalHDL/Libraries/stream.rst:423
+#: ../../SpinalHDL/Libraries/stream.rst:438
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/stream.rst:23
+msgid "Don't care when"
+msgstr "何时忽略"
+
+#: ../../SpinalHDL/Libraries/stream.rst:24
+msgid "valid"
+msgstr "valid"
+
+#: ../../SpinalHDL/Libraries/stream.rst:25
+#: ../../SpinalHDL/Libraries/stream.rst:30
+#: ../../SpinalHDL/Libraries/stream.rst:110
+#: ../../SpinalHDL/Libraries/stream.rst:114
+#: ../../SpinalHDL/Libraries/stream.rst:241
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Libraries/stream.rst:26
+#: ../../SpinalHDL/Libraries/stream.rst:36
+msgid "Master"
+msgstr "Master"
+
+#: ../../SpinalHDL/Libraries/stream.rst:27
+msgid "When high => payload present on the interface"
+msgstr "当为高时 => 接口上存在有效负载(payload)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:29
+msgid "ready"
+msgstr "ready"
+
+#: ../../SpinalHDL/Libraries/stream.rst:31
+msgid "Slave"
+msgstr "Slave"
+
+#: ../../SpinalHDL/Libraries/stream.rst:32
+msgid "When low => transaction are not consumed by the slave"
+msgstr "当为低时 => 从端不接收传输"
+
+#: ../../SpinalHDL/Libraries/stream.rst:33
+#: ../../SpinalHDL/Libraries/stream.rst:38
+msgid "valid is low"
+msgstr "valid为低"
+
+#: ../../SpinalHDL/Libraries/stream.rst:34
+msgid "payload"
+msgstr "payload"
+
+#: ../../SpinalHDL/Libraries/stream.rst:35
+#: ../../SpinalHDL/Libraries/stream.rst:220
+#: ../../SpinalHDL/Libraries/stream.rst:276
+#: ../../SpinalHDL/Libraries/stream.rst:338
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Libraries/stream.rst:37
+msgid "Content of the transaction"
+msgstr "传输任务内容"
+
+#: ../../SpinalHDL/Libraries/stream.rst:49
+msgid "There is some examples of usage in SpinalHDL :"
+msgstr "这里有一些在SpinalHDL中的用法示例："
+
+#: ../../SpinalHDL/Libraries/stream.rst:70
+msgid ""
+"Each slave can or can't allow the payload to change when valid is high and "
+"ready is low. For examples:"
+msgstr "当valid为高且ready为低时，每个从端都可以控制是否允许有效负载变化。例如："
+
+#: ../../SpinalHDL/Libraries/stream.rst:73
+msgid ""
+"An priority arbiter without lock logic can switch from one input to the "
+"other (which will change the payload)."
+msgstr "没有锁逻辑的优先级仲裁器可以从一个输入切换到另一个输入（这将改变有效负载）。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:74
+msgid ""
+"An UART controller could directly use the write port to drive UART pins and "
+"only consume the transaction at the end of the transmission. Be careful with"
+" that."
+msgstr "UART控制器可以直接使用写端口驱动UART引脚，并且只在传输结束时完成数据交换。对"
+"此需要注意。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:78
+msgid "Semantics"
+msgstr "语义"
+
+#: ../../SpinalHDL/Libraries/stream.rst:80
+msgid ""
+"When manually reading/driving the signals of a Stream keep in mind that:"
+msgstr "当手动读取/驱动反压流的信号时，请记住："
+
+#: ../../SpinalHDL/Libraries/stream.rst:82
+msgid ""
+"After being asserted, ``valid`` may only be deasserted once the current "
+"payload was acknowleged. This means ``valid`` can only toggle to 0 the cycle"
+" after a the slave did a read by asserting ``ready``."
+msgstr ""
+"当 ``valid`` 被置为有效后，它只有在当前负载被使用后才能被置为无效。这意味着 "
+"``valid`` 只能在从端通过置高 ``ready`` "
+"完成一次读取后的下一个周期，才可以切换到0。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:83
+msgid "In contrast to that ``ready`` may change at any time."
+msgstr "相反， ``ready`` 可以随时改变。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:84
+msgid ""
+"A transfer is only done on cycles where both ``valid`` and ``ready`` are "
+"asserted."
+msgstr "传输仅在 ``valid`` 和 ``ready`` 均已置高的周期内进行。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:85
+msgid ""
+"``valid`` of a Stream must not depend on ``ready`` in a combinatorial way "
+"and any path between the two must be registered."
+msgstr "一个反压流的 ``valid`` 不能以组合逻辑方式和 ``ready`` "
+"连接，并且两者之间的任何路径都必须经过寄存器。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:86
+msgid "It is recommended that ``valid`` does not depend on ``ready`` at all."
+msgstr "推荐 ``valid`` 和 ``ready`` 之间没有任何依赖。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:89
+msgid "Functions"
+msgstr "函数"
+
+#: ../../SpinalHDL/Libraries/stream.rst:95
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Libraries/stream.rst:97
+#: ../../SpinalHDL/Libraries/stream.rst:453
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/stream.rst:98
+msgid "Latency"
+msgstr "延迟"
+
+#: ../../SpinalHDL/Libraries/stream.rst:99
+msgid "Stream(type : Data)"
+msgstr "Stream(type : Data)"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+#: ../../SpinalHDL/Libraries/stream.rst:100
+msgid "Create a Stream of a given type"
+msgstr "创建一个给定类型的Stream反压流"
+
+#: ../../SpinalHDL/Libraries/stream.rst:101
+#: ../../SpinalHDL/Libraries/stream.rst:106
+#: ../../SpinalHDL/Libraries/stream.rst:118
+#: ../../SpinalHDL/Libraries/stream.rst:125
+#: ../../SpinalHDL/Libraries/stream.rst:131
+#: ../../SpinalHDL/Libraries/stream.rst:137
+#: ../../SpinalHDL/Libraries/stream.rst:163
+#: ../../SpinalHDL/Libraries/stream.rst:168
+#: ../../SpinalHDL/Libraries/stream.rst:235
+#: ../../SpinalHDL/Libraries/stream.rst:238
+#: ../../SpinalHDL/Libraries/stream.rst:297
+#: ../../SpinalHDL/Libraries/stream.rst:300
+#: ../../SpinalHDL/Libraries/stream.rst:356
+#: ../../SpinalHDL/Libraries/stream.rst:359
+#: ../../SpinalHDL/Libraries/stream.rst:455
+#: ../../SpinalHDL/Libraries/stream.rst:457
+msgid "Stream[T]"
+msgstr "Stream[T]"
+
+#: ../../SpinalHDL/Libraries/stream.rst:103
+msgid "master/slave Stream(type : Data)"
+msgstr "master/slave Stream(type : Data)"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Initialized with corresponding in/out setup"
+msgstr "使用相应的输入/输出设置进行初始化"
+
+#: ../../SpinalHDL/Libraries/stream.rst:108
+msgid "x.fire"
+msgstr "x.fire"
+
+#: ../../SpinalHDL/Libraries/stream.rst:109
+msgid "Return True when a transaction is consumed on the bus (valid && ready)"
+msgstr "当总线上的传输完成时返回 True(valid && ready)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:112
+msgid "x.isStall"
+msgstr "x.isStall"
+
+#: ../../SpinalHDL/Libraries/stream.rst:113
+msgid "Return True when a transaction is stall on the bus (valid && ! ready)"
+msgstr "当总线上的传输停滞时返回True(valid && ! ready)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:116
+msgid "x.queue(size:Int)"
+msgstr "x.queue(size:Int)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:117
+msgid "Return a Stream connected to x through a FIFO"
+msgstr "返回一个通过FIFO连接到x的Stream"
+
+#: ../../SpinalHDL/Libraries/stream.rst:119
+msgid "2"
+msgstr "2"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x.m2sPipe()"
+msgstr "x.m2sPipe()"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x.stage()"
+msgstr "x.stage()"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Return a Stream drived by x"
+msgstr "返回由x驱动的Stream反压流"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "through a register stage that cut valid/payload paths"
+msgstr "通过寄存器级断开 valid/payload 路径（优化时序）"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Cost = (payload width + 1) flop flop"
+msgstr "Cost = (payload width + 1) 触发器"
+
+#: ../../SpinalHDL/Libraries/stream.rst:126
+#: ../../SpinalHDL/Libraries/stream.rst:138
+#: ../../SpinalHDL/Libraries/stream.rst:148
+#: ../../SpinalHDL/Libraries/stream.rst:159
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Libraries/stream.rst:127
+msgid "x.s2mPipe()"
+msgstr "x.s2mPipe()"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "ready paths is cut by a register stage"
+msgstr "通过寄存器级断开ready路径"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Cost = payload width * (mux2 + 1 flip flop)"
+msgstr "Cost = payload width * (mux2 + 1 flip flop)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:132
+#: ../../SpinalHDL/Libraries/stream.rst:143
+#: ../../SpinalHDL/Libraries/stream.rst:153
+#: ../../SpinalHDL/Libraries/stream.rst:164
+#: ../../SpinalHDL/Libraries/stream.rst:169
+msgid "0"
+msgstr "0"
+
+#: ../../SpinalHDL/Libraries/stream.rst:133
+msgid "x.halfPipe()"
+msgstr "x.halfPipe()"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "valid/ready/payload paths are cut by some register"
+msgstr "valid/ready/payload路径通过一些寄存器分割"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Cost = (payload width + 2) flip flop, bandwidth divided by two"
+msgstr "成本 = (payload位宽 + 2)个触发器，带宽除以二"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x << y"
+msgstr "x << y"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "y >> x"
+msgstr "y >> x"
+
+#: ../../SpinalHDL/Libraries/stream.rst:141
+msgid "Connect y to x"
+msgstr "将y连接到x"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x <-< y"
+msgstr "x <-< y"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "y >-> x"
+msgstr "y >-> x"
+
+#: ../../SpinalHDL/Libraries/stream.rst:146
+msgid "Connect y to x through a m2sPipe"
+msgstr "通过m2sPipe将y连接到x"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x </< y"
+msgstr "x </< y"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "y >/> x"
+msgstr "y >/> x"
+
+#: ../../SpinalHDL/Libraries/stream.rst:151
+msgid "Connect y to x through a s2mPipe"
+msgstr "通过s2mPipe将y连接到x"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "x <-/< y"
+msgstr "x <-/< y"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "y >/-> x"
+msgstr "y >/-> x"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Connect y to x through s2mPipe().m2sPipe()"
+msgstr "通过 s2mPipe().m2sPipe() 将 y 连接到 x"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Which imply no combinatorial path between x and y"
+msgstr "这意味着x和y之间没有组合逻辑路径"
+
+#: ../../SpinalHDL/Libraries/stream.rst:160
+msgid "x.haltWhen(cond : Bool)"
+msgstr "x.haltWhen(cond : Bool)"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Return a Stream connected to x"
+msgstr "返回连接到x的反压流"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Halted when cond is true"
+msgstr "cond为true时暂停"
+
+#: ../../SpinalHDL/Libraries/stream.rst:165
+msgid "x.throwWhen(cond : Bool)"
+msgstr "x.throwWhen(cond : Bool)"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "When cond is true, transaction are dropped"
+msgstr "当cond为true时，传输数据将被抛弃"
+
+#: ../../SpinalHDL/Libraries/stream.rst:172
+msgid "The following code will create this logic :"
+msgstr "以下代码将创建此逻辑："
+
+#: ../../SpinalHDL/Libraries/stream.rst:192
+msgid "Utils"
+msgstr "实用工具"
+
+#: ../../SpinalHDL/Libraries/stream.rst:194
+msgid ""
+"There is many utils that you can use in your design in conjunction with the "
+"Stream bus, this chapter will document them."
+msgstr "有许多实用工具可以在设计中与反压流总线结合使用，本章将介绍它们。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:197
+msgid "StreamFifo"
+msgstr "StreamFifo"
+
+#: ../../SpinalHDL/Libraries/stream.rst:199
+msgid ""
+"On each stream you can call the .queue(size) to get a buffered stream. But "
+"you can also instantiate the FIFO component itself :"
+msgstr "您可以在每个反压流上调用 .queue(size) 来获取一个缓冲反压流。但您也可以实例化 "
+"FIFO 组件本身："
+
+#: ../../SpinalHDL/Libraries/stream.rst:216
+#: ../../SpinalHDL/Libraries/stream.rst:272
+#: ../../SpinalHDL/Libraries/stream.rst:334
+msgid "parameter name"
+msgstr "参数名称"
+
+#: ../../SpinalHDL/Libraries/stream.rst:219
+#: ../../SpinalHDL/Libraries/stream.rst:275
+#: ../../SpinalHDL/Libraries/stream.rst:337
+msgid "dataType"
+msgstr "数据类型"
+
+#: ../../SpinalHDL/Libraries/stream.rst:221
+#: ../../SpinalHDL/Libraries/stream.rst:277
+#: ../../SpinalHDL/Libraries/stream.rst:339
+msgid "Payload data type"
+msgstr "有效负载(payload)数据类型"
+
+#: ../../SpinalHDL/Libraries/stream.rst:222
+#: ../../SpinalHDL/Libraries/stream.rst:278
+msgid "depth"
+msgstr "depth"
+
+#: ../../SpinalHDL/Libraries/stream.rst:223
+#: ../../SpinalHDL/Libraries/stream.rst:279
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/stream.rst:224
+#: ../../SpinalHDL/Libraries/stream.rst:280
+msgid "Size of the memory used to store elements"
+msgstr "用于存储数据的存储器的大小"
+
+#: ../../SpinalHDL/Libraries/stream.rst:231
+#: ../../SpinalHDL/Libraries/stream.rst:293
+#: ../../SpinalHDL/Libraries/stream.rst:352
+msgid "io name"
+msgstr "io名称"
+
+#: ../../SpinalHDL/Libraries/stream.rst:234
+#: ../../SpinalHDL/Libraries/stream.rst:296
+msgid "push"
+msgstr "push"
+
+#: ../../SpinalHDL/Libraries/stream.rst:236
+#: ../../SpinalHDL/Libraries/stream.rst:298
+#: ../../SpinalHDL/Libraries/stream.rst:357
+msgid "Used to push elements"
+msgstr "用于压入数据"
+
+#: ../../SpinalHDL/Libraries/stream.rst:237
+#: ../../SpinalHDL/Libraries/stream.rst:299
+msgid "pop"
+msgstr "pop"
+
+#: ../../SpinalHDL/Libraries/stream.rst:239
+#: ../../SpinalHDL/Libraries/stream.rst:301
+#: ../../SpinalHDL/Libraries/stream.rst:360
+msgid "Used to pop elements"
+msgstr "用于弹出数据"
+
+#: ../../SpinalHDL/Libraries/stream.rst:240
+msgid "flush"
+msgstr "flush"
+
+#: ../../SpinalHDL/Libraries/stream.rst:242
+msgid "Used to remove all elements inside the FIFO"
+msgstr "用于清除FIFO内的所有数据"
+
+#: ../../SpinalHDL/Libraries/stream.rst:243
+msgid "occupancy"
+msgstr "occupancy"
+
+#: ../../SpinalHDL/Libraries/stream.rst:244
+#: ../../SpinalHDL/Libraries/stream.rst:303
+#: ../../SpinalHDL/Libraries/stream.rst:306
+msgid "UInt of log2Up(depth + 1) bits"
+msgstr "log2Up(depth + 1) bits 的 UInt"
+
+#: ../../SpinalHDL/Libraries/stream.rst:245
+msgid "Indicate the internal memory occupancy"
+msgstr "反映内部存储占用情况"
+
+#: ../../SpinalHDL/Libraries/stream.rst:249
+msgid "StreamFifoCC"
+msgstr "StreamFifoCC"
+
+#: ../../SpinalHDL/Libraries/stream.rst:251
+msgid ""
+"You can instantiate the dual clock domain version of the fifo the following "
+"way :"
+msgstr "您可以通过以下方式实例化双时钟域版本的fifo："
+
+#: ../../SpinalHDL/Libraries/stream.rst:281
+msgid "pushClock"
+msgstr "pushClock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:282
+#: ../../SpinalHDL/Libraries/stream.rst:285
+#: ../../SpinalHDL/Libraries/stream.rst:341
+#: ../../SpinalHDL/Libraries/stream.rst:344
+msgid "ClockDomain"
+msgstr "ClockDomain"
+
+#: ../../SpinalHDL/Libraries/stream.rst:283
+#: ../../SpinalHDL/Libraries/stream.rst:342
+msgid "Clock domain used by the push side"
+msgstr "压入数据端使用的时钟域"
+
+#: ../../SpinalHDL/Libraries/stream.rst:284
+msgid "popClock"
+msgstr "popClock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:286
+#: ../../SpinalHDL/Libraries/stream.rst:345
+msgid "Clock domain used by the pop side"
+msgstr "弹出数据端使用的时钟域"
+
+#: ../../SpinalHDL/Libraries/stream.rst:302
+msgid "pushOccupancy"
+msgstr "pushOccupancy"
+
+#: ../../SpinalHDL/Libraries/stream.rst:304
+msgid ""
+"Indicate the internal memory occupancy (from the push side perspective)"
+msgstr "反映内部存储器占用情况（从压入数据端的角度）"
+
+#: ../../SpinalHDL/Libraries/stream.rst:305
+msgid "popOccupancy"
+msgstr "popOccupancy"
+
+#: ../../SpinalHDL/Libraries/stream.rst:307
+msgid ""
+"Indicate the internal memory occupancy  (from the pop side perspective)"
+msgstr "反映内部存储器占用情况（从弹出数据端的角度）"
+
+#: ../../SpinalHDL/Libraries/stream.rst:311
+msgid "StreamCCByToggle"
+msgstr "StreamCCByToggle"
+
+#: ../../SpinalHDL/Libraries/stream.rst:313
+msgid ""
+"Component that connects Streams across clock domains based on toggling "
+"signals."
+msgstr "基于信号切换来连接跨时钟域的反压流组件。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:314
+msgid ""
+"This way of implementing a cross clock domain bridge is characterized by a "
+"small area usage but also a low bandwidth."
+msgstr "这种实现跨时钟域桥的方式的特点是占用逻辑区小，但带宽较低。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:340
+msgid "inputClock"
+msgstr "inputClock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:343
+msgid "outputClock"
+msgstr "outputClock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:355
+msgid "input"
+msgstr "input"
+
+#: ../../SpinalHDL/Libraries/stream.rst:358
+msgid "output"
+msgstr "output"
+
+#: ../../SpinalHDL/Libraries/stream.rst:363
+msgid ""
+"Alternatively you can also use a this shorter syntax which directly return "
+"you the cross clocked stream:"
+msgstr "或者您也可以使用更简短的语句，直接返回跨时钟域的反压流："
+
+#: ../../SpinalHDL/Libraries/stream.rst:377
+msgid "StreamWidthAdapter"
+msgstr "StreamWidthAdapter（反压流位宽适应器）"
+
+#: ../../SpinalHDL/Libraries/stream.rst:379
+msgid ""
+"This component adapts the width of the input stream to the output stream. "
+"When the width of the ``outStream`` payload is greater than the "
+"``inStream``, by combining the payloads of several input transactions into "
+"one; conversely, if the payload width of the ``outStream`` is less than the "
+"``inStream``, one input transaction will be split into several output "
+"transactions."
+msgstr ""
+"该组件使输入反压流的位宽和输出反压流匹配。当 ``outStream`` 的负载的位宽大于 "
+"``inStream`` 时，通过将多个输入传输任务的负载合并为一个；相反，如果 "
+"``outStream`` 的负载位宽小于 ``inStream`` "
+"，则一个输入传输任务将被拆分为多个输出传输任务。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:382
+msgid ""
+"In the best case, the width of the payload of the ``inStream`` should be an "
+"integer multiple of the ``outStream`` as shown below."
+msgstr "在最好的情况下， ``inStream`` 的负载位宽应该是 ``outStream`` "
+"的整数倍，如下所示。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:390
+msgid ""
+"As in the example above, the two ``inStream`` transactions will be merged "
+"into one ``outStream`` transaction, and the payload of the first input "
+"transaction will be placed on the lower bits of the output payload by "
+"default."
+msgstr ""
+"如上例所示，两个 ``inStream`` 传输任务将合并为一个 ``outStream`` "
+"传输任务，并且第一个输入传输任务的负载将默认置于输出负载的低位上。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:392
+msgid ""
+"If the expected order of input transaction payload placement is different "
+"from the default setting, here is an example."
+msgstr "如果输入传输任务负载放置的期望顺序与默认设置不同，请参阅以下示例。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:400
+msgid ""
+"There is also a traditional parameter called ``endianness``, which has the "
+"same effect as ``ORDER``. The value of ``endianness`` is the same as "
+"``LOWER_FIRST`` of ``order`` when it is ``LITTLE``, and the same as "
+"``HIGHER_FIRST`` when it is ``BIG``. The ``padding`` parameter is an "
+"optional boolean value to determine whether the adapter accepts non-integer "
+"multiples of the input and output payload width."
+msgstr ""
+"还有一个称为 ``endianness`` 的传统参数，它与 ``ORDER`` 具有相同的效果。当 "
+"``endianness`` 的值为 ``LITTLE`` 时，它与 ``order`` 的 ``LOWER_FIRST`` 相同；"
+"当为 ``BIG`` 时，它与 ``HIGHER_FIRST`` 相同。 ``padding`` 参数是一个可选的布"
+"尔逻辑值，它用于确定适应器是否接受输入和输出负载位宽为非整数倍。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:406
+msgid "StreamArbiter"
+msgstr "StreamArbiter（反压流仲裁器）"
+
+#: ../../SpinalHDL/Libraries/stream.rst:408
+msgid ""
+"When you have multiple Streams and you want to arbitrate them to drive a "
+"single one, you can use the StreamArbiterFactory."
+msgstr "当您有多个Stream反压流并且您想要仲裁它们以驱动单个反压流时，您可以使用 "
+"StreamArbiterFactory。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:422
+msgid "Arbitration functions"
+msgstr "仲裁函数"
+
+#: ../../SpinalHDL/Libraries/stream.rst:424
+msgid "lowerFirst"
+msgstr "lowerFirst"
+
+#: ../../SpinalHDL/Libraries/stream.rst:425
+msgid "Lower port have priority over higher port"
+msgstr "较低端口优先级高于较高端口"
+
+#: ../../SpinalHDL/Libraries/stream.rst:426
+msgid "roundRobin"
+msgstr "roundRobin"
+
+#: ../../SpinalHDL/Libraries/stream.rst:427
+msgid "Fair round robin arbitration"
+msgstr "公平轮询仲裁"
+
+#: ../../SpinalHDL/Libraries/stream.rst:428
+msgid "sequentialOrder"
+msgstr "sequentialOrder"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Could be used to retrieve transaction in a sequancial order"
+msgstr "可用于按顺序遍历任务"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "First transaction should come from port zero, then from port one, ..."
+msgstr "第一个传输应该来自端口 0，然后来自端口 1，..."
+
+#: ../../SpinalHDL/Libraries/stream.rst:437
+msgid "Lock functions"
+msgstr "锁函数"
+
+#: ../../SpinalHDL/Libraries/stream.rst:439
+msgid "noLock"
+msgstr "noLock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:440
+msgid ""
+"The port selection could change every cycle, even if the transaction on the "
+"selected port is not consumed."
+msgstr "端口选择可以在每个周期改变，即使被选择的端口的传输没有执行。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:441
+msgid "transactionLock"
+msgstr "transactionLock"
+
+#: ../../SpinalHDL/Libraries/stream.rst:442
+msgid ""
+"The port selection is locked until the transaction on the selected port is "
+"consumed."
+msgstr "端口选择被锁定，直到所选端口上的数据传输完成。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:443
+msgid "fragmentLock"
+msgstr "fragmentLock"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid "Could be used to arbitrate Stream[Flow[T]]."
+msgstr "可用于仲裁 Stream[Flow[T]]。"
+
+#: ../../SpinalHDL/Libraries/stream.rst
+msgid ""
+"In this mode, the port selection is locked until the selected port finish is"
+" burst (last=True)."
+msgstr "在此模式下，端口选择被锁定，直到所选端口完成突发（last=True）。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:452
+msgid "Generation functions"
+msgstr "生成函数"
+
+#: ../../SpinalHDL/Libraries/stream.rst:454
+msgid "on(inputs : Seq[Stream[T]])"
+msgstr "on(inputs : Seq[Stream[T]])"
+
+#: ../../SpinalHDL/Libraries/stream.rst:456
+msgid "onArgs(inputs : Stream[T]*)"
+msgstr "onArgs(inputs : Stream[T]*)"
+
+#: ../../SpinalHDL/Libraries/stream.rst:460
+msgid "StreamJoin"
+msgstr "StreamJoin"
+
+#: ../../SpinalHDL/Libraries/stream.rst:462
+msgid ""
+"This utility takes multiple input streams and waits until all of them fire "
+"`valid` before letting all of them through by providing `ready`."
+msgstr "该实用工具接收多个输入反压流并等待所有输入反压流触发 `valid` ，"
+"然后再通过提供 `ready` 信号让所有输入流通过。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:471
+msgid "StreamFork"
+msgstr "StreamFork"
+
+#: ../../SpinalHDL/Libraries/stream.rst:473
+msgid ""
+"A StreamFork will clone each incoming data to all its output streams. If "
+"synchronous is true, all output streams will always fire together, which "
+"means that the stream will halt until all output streams are ready. If "
+"synchronous is false, output streams may be ready one at a time, at the cost"
+" of an additional flip flop (1 bit per output). The input stream will block "
+"until all output streams have processed each item regardlessly."
+msgstr ""
+"StreamFork会将每个传入数据克隆到其所有输出流。如果synchronous为true，则所有输"
+"出流将始终一起触发，这意味着直到所有输出流准备就绪前该流将都将暂停。如果synch"
+"ronous为false，那么一次可能只有一个输出流准备就绪，但需要一个额外的触发器（每"
+"个输出1位）。直到所有输出流都处理完每个项目前，输入流将阻塞。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:485
+msgid "or"
+msgstr "或者"
+
+#: ../../SpinalHDL/Libraries/stream.rst:493
+msgid "StreamMux"
+msgstr "StreamMux"
+
+#: ../../SpinalHDL/Libraries/stream.rst:495
+msgid ""
+"A mux implementation for ``Stream``. It takes a ``select`` signal and "
+"streams in ``inputs``, and returns a ``Stream`` which is connected to one of"
+" the input streams specified by ``select``. ``StreamArbiter`` is a facility "
+"works similar to this but is more powerful."
+msgstr ""
+"``Stream`` 的多路复用器实现。它接受一个 ``select`` 信号和 ``inputs`` "
+"中的反压流，并返回一个 ``Stream`` ，该 ``Stream`` 连接到 ``select`` "
+"指定的其中一个输入流。 ``StreamArbiter`` 是一个与此类似的工具，但功能更强大。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:507
+msgid ""
+"The ``UInt`` type of ``select`` signal could not be changed while output "
+"stream is stalled, or it might break the transaction on the fly. Use "
+"``Stream`` typed ``select`` can generate a stream interface which only fire "
+"and change the routing when it is safe."
+msgstr ""
+"当输出流暂停时， ``select`` 信号的 ``UInt`` "
+"类型不能更改，否则可能会中断执行中的传输任务。使用 ``Stream`` 类型的 "
+"``select`` 可以生成一个流接口，该接口仅在安全时触发并更改路径。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:512
+msgid "StreamDemux"
+msgstr "StreamDemux"
+
+#: ../../SpinalHDL/Libraries/stream.rst:514
+msgid ""
+"A demux implementation for ``Stream``. It takes a ``input``, a ``select`` "
+"and a ``portCount`` and returns a ``Vec(Stream)`` where the output stream "
+"specified by ``select`` is connected to ``input``, the other output streams "
+"are inactive. For safe transaction, refer the notes above."
+msgstr ""
+"``Stream`` 的解复用实现。它需要一个 ``input`` 、一个 ``select`` 和一个 "
+"``portCount`` 并返回一个 ``Vec(Stream)`` ，其中输出流由 ``select`` "
+"指定并连接到 ``input`` "
+"，其他输出流处于非活动状态。为了安全传输，请参阅上面的注释。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:525
+msgid "StreamDispatcherSequencial"
+msgstr "StreamDispatcherSequencial"
+
+#: ../../SpinalHDL/Libraries/stream.rst:527
+msgid ""
+"This util take its input stream and routes it to ``outputCount`` stream in a"
+" sequential order."
+msgstr "该工具获取其输入流并将其按顺序连接到 ``outputCount`` 反压流。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:538
+msgid "StreamTransactionExtender"
+msgstr "StreamTransactionExtender"
+
+#: ../../SpinalHDL/Libraries/stream.rst:540
+msgid ""
+"This utility will take one input transfer and generate several output "
+"transfers, it provides the facility to repeat the payload value ``count+1`` "
+"times into output transfers. The ``count`` is captured and registered each "
+"time inputStream fires for an individual payload."
+msgstr ""
+"该工具将使用一个输入传输并生成多个输出传输，它提供了将负载值重复 ``count+1`` "
+"次到输出传输的功能。每当为单个负载而触发inputStream时，都会捕获并寄存 "
+"``count`` 。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:555
+msgid ""
+"This ``extender`` provides several status signals, such as ``working``, "
+"``last``, ``done`` where ``working`` means there is one input transfer "
+"accepted and in-progress, ``last`` indicates the last output transfer is "
+"prepared and waiting to complete, ``done`` become valid represents the last "
+"output transfer is fireing and making the current input transaction process "
+"complete and ready to start another transaction."
+msgstr ""
+"该 ``extender`` 提供了多种状态信号，例如 ``working`` 、 ``last`` 、``done`` "
+"，其中 ``working`` 表示有一个输入传输已接受并正在进行中， ``last`` "
+"表示最后一个输出传输已准备好并等待完成，``done`` 变为有效表示最后一个输出传输"
+"正在触发，并使当前输入传输任务处理完成且准备好启动另一个传输。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:572
+msgid ""
+"If only count for output stream is required then use "
+"``StreamTransactionCounter`` instead."
+msgstr "如果仅需要对输出流计数，那么可以使用 ``StreamTransactionCounter`` 。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:575
+msgid "Simulation support"
+msgstr "仿真支持"
+
+#: ../../SpinalHDL/Libraries/stream.rst:577
+msgid "For simulation master and slave implementations are available:"
+msgstr "对于仿真，有以下可用的主端和从端实现："
+
+#: ../../SpinalHDL/Libraries/stream.rst:583
+msgid "Class"
+msgstr "类"
+
+#: ../../SpinalHDL/Libraries/stream.rst:584
+msgid "Usage"
+msgstr "用法"
+
+#: ../../SpinalHDL/Libraries/stream.rst:585
+msgid "StreamMonitor"
+msgstr "StreamMonitor"
+
+#: ../../SpinalHDL/Libraries/stream.rst:586
+msgid ""
+"Used for both master and slave sides, calls function with payload if Stream "
+"fires."
+msgstr "用于主端和从端，如果Stream触发，则调用带有负载的函数。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:587
+msgid "StreamDriver"
+msgstr "StreamDriver"
+
+#: ../../SpinalHDL/Libraries/stream.rst:588
+msgid ""
+"Testbench master side, drives values by calling function to apply value (if "
+"available). Function must return if value was available. Supports random "
+"delays."
+msgstr "Testbench中主端通过调用函数来应用值（如果可用）以驱动值。如果值可用，则函数必"
+"须返回。支持随机的延迟。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:589
+msgid "StreamReadyRandmizer"
+msgstr "StreamReadyRandmizer"
+
+#: ../../SpinalHDL/Libraries/stream.rst:590
+msgid ""
+"Randomizes ``ready`` for reception of data, testbench is the slave side."
+msgstr "随机产生 ``ready`` 以接收数据，testbench为从端。"
+
+#: ../../SpinalHDL/Libraries/stream.rst:591
+msgid "ScoreboardInOrder"
+msgstr "ScoreboardInOrder"
+
+#: ../../SpinalHDL/Libraries/stream.rst:592
+msgid "Often used to compare reference/dut data"
+msgstr "通常用于比较参考/dut数据"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po
new file mode 100644
index 00000000000..ceebf6cf386
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po
@@ -0,0 +1,504 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesutils/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Libraries/utils.rst:5
+msgid "Utils"
+msgstr "实用工具"
+
+#: ../../SpinalHDL/Libraries/utils.rst:7
+msgid "Some utils are also present in :ref:`spinal.core <utils>`"
+msgstr "一些实用工具也在 :ref:`spinal.core <utils>` 中"
+
+#: ../../SpinalHDL/Libraries/utils.rst:10
+msgid "State less utilities"
+msgstr "免状态工具"
+
+#: ../../SpinalHDL/Libraries/utils.rst:16
+#: ../../SpinalHDL/Libraries/utils.rst:83
+#: ../../SpinalHDL/Libraries/utils.rst:216
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Libraries/utils.rst:17
+#: ../../SpinalHDL/Libraries/utils.rst:84
+#: ../../SpinalHDL/Libraries/utils.rst:217
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Libraries/utils.rst:18
+#: ../../SpinalHDL/Libraries/utils.rst:85
+#: ../../SpinalHDL/Libraries/utils.rst:189
+#: ../../SpinalHDL/Libraries/utils.rst:218
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Libraries/utils.rst:19
+msgid "toGray(x : UInt)"
+msgstr "toGray(x : UInt)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:20
+#: ../../SpinalHDL/Libraries/utils.rst:44
+#: ../../SpinalHDL/Libraries/utils.rst:47
+#: ../../SpinalHDL/Libraries/utils.rst:53
+msgid "Bits"
+msgstr "位"
+
+#: ../../SpinalHDL/Libraries/utils.rst:21
+msgid "Return the gray value converted from ``x`` (UInt)"
+msgstr "返回从 ``x`` (UInt)转换而来的灰度值"
+
+#: ../../SpinalHDL/Libraries/utils.rst:22
+msgid "fromGray(x : Bits)"
+msgstr "fromGray(x : Bits)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:23
+#: ../../SpinalHDL/Libraries/utils.rst:30
+#: ../../SpinalHDL/Libraries/utils.rst:34
+msgid "UInt"
+msgstr "UInt"
+
+#: ../../SpinalHDL/Libraries/utils.rst:24
+msgid "Return the UInt value converted value from ``x`` (gray)"
+msgstr "返回从 ``x`` (灰度)转换而来的UInt值"
+
+#: ../../SpinalHDL/Libraries/utils.rst:25
+msgid "Reverse(x : T)"
+msgstr "Reverse(x : T)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:26
+#: ../../SpinalHDL/Libraries/utils.rst:41
+#: ../../SpinalHDL/Libraries/utils.rst:61
+#: ../../SpinalHDL/Libraries/utils.rst:67
+#: ../../SpinalHDL/Libraries/utils.rst:72
+#: ../../SpinalHDL/Libraries/utils.rst:87
+#: ../../SpinalHDL/Libraries/utils.rst:95
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Libraries/utils.rst:27
+msgid "Flip all bits (lsb + n -> msb - n)"
+msgstr "翻转所有位(lsb + n -> msb - n)"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "OHToUInt(x : Seq[Bool])"
+msgstr "OHToUInt(x : Seq[Bool])"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "OHToUInt(x : BitVector)"
+msgstr "OHToUInt(x : BitVector)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:31
+msgid "Return the index of the single bit set (one hot) in ``x``"
+msgstr "返回 ``x`` 中唯一被设置（为1）的比特位的索引"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "CountOne(x : Seq[Bool])"
+msgstr "CountOne(x : Seq[Bool])"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "CountOne(x : BitVector)"
+msgstr "CountOne(x : BitVector)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:35
+msgid "Return the number of bit set in ``x``"
+msgstr "返回 ``x`` 中被设为1的位数"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "MajorityVote(x : Seq[Bool])"
+msgstr "MajorityVote(x : Seq[Bool])"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "MajorityVote(x : BitVector)"
+msgstr "MajorityVote(x : BitVector)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:38
+#: ../../SpinalHDL/Libraries/utils.rst:191
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Libraries/utils.rst:39
+msgid "Return True if the number of bit set is > x.size / 2"
+msgstr "如果设置为1的位数 > x.size / 2，则返回 True"
+
+#: ../../SpinalHDL/Libraries/utils.rst:40
+msgid "EndiannessSwap(that: T[, base:BitCount])"
+msgstr "EndiannessSwap(that: T[, base:BitCount])"
+
+#: ../../SpinalHDL/Libraries/utils.rst:42
+msgid "Big-Endian <-> Little-Endian"
+msgstr "大端 <-> 小端"
+
+#: ../../SpinalHDL/Libraries/utils.rst:43
+msgid "OHMasking.first(x : Bits)"
+msgstr "OHMasking.first(x : Bits)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:45
+msgid "Apply a mask on x to only keep the first bit set"
+msgstr "对x应用掩码以仅保留第一个设为1的位"
+
+#: ../../SpinalHDL/Libraries/utils.rst:46
+msgid "OHMasking.last(x : Bits)"
+msgstr "OHMasking.last(x : Bits)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:48
+msgid "Apply a mask on x to only keep the last bit set"
+msgstr "对x应用掩码以仅保留最后一个设为1的位"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "OHMasking.roundRobin("
+msgstr "OHMasking.roundRobin("
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "requests : Bits,"
+msgstr "requests : Bits,"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "ohPriority : Bits"
+msgstr "ohPriority : Bits"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid ")"
+msgstr ")"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "Apply a mask on x to only keep the bit set from ``requests``."
+msgstr "对x应用掩码以仅保留 ``requests`` 中设置1的位。"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "it start looking in ``requests`` from the ``ohPriority`` position."
+msgstr "它从 ``ohPriority`` 位置开始访问 ``requests`` 。"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid ""
+"For example if ``requests`` is \"1001\" and ``ohPriority`` is \"0010\", the "
+"``roundRobin`` function will start looking in `requests` from its second bit"
+" and will return \"1000\"."
+msgstr ""
+"例如，如果 ``requests`` 为“1001”且 ``ohPriority`` 为“0010”，则 ``roundRobin``"
+" 函数将从第二位开始访问 `requests` 并返回“1000”。"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "MuxOH ("
+msgstr "MuxOH ("
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "oneHot : IndexedSeq[Bool],"
+msgstr "oneHot : IndexedSeq[Bool],"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "inputs : Iterable[T]"
+msgstr "inputs : Iterable[T]"
+
+#: ../../SpinalHDL/Libraries/utils.rst:62
+msgid ""
+"Returns the muxed ``T`` from the ``inputs`` based on the ``oneHot`` vector."
+msgstr "根据 ``oneHot`` 向量从 ``inputs`` 中返回多路复用的 ``T`` 。"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "PriorityMux ("
+msgstr "PriorityMux ("
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "sel: Seq[Bool],"
+msgstr "sel: Seq[Bool],"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "in:  Seq[T]"
+msgstr "in:  Seq[T]"
+
+#: ../../SpinalHDL/Libraries/utils.rst:68
+#: ../../SpinalHDL/Libraries/utils.rst:73
+msgid "Return the first ``in`` element whose ``sel`` is ``True``."
+msgstr "返回第一个其 ``sel`` 为 ``True`` 的 ``in`` 元素。"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "in:  Seq[(Bool, T)]"
+msgstr "in:  Seq[(Bool, T)]"
+
+#: ../../SpinalHDL/Libraries/utils.rst:77
+msgid "State full utilities"
+msgstr "全状态工具"
+
+#: ../../SpinalHDL/Libraries/utils.rst:86
+msgid "Delay(that: T, cycleCount: Int)"
+msgstr "Delay(that: T, cycleCount: Int)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:88
+msgid "Return ``that`` delayed by ``cycleCount`` cycles"
+msgstr "返回延迟了 ``cycleCount`` 周期的 ``that``"
+
+#: ../../SpinalHDL/Libraries/utils.rst:89
+msgid "History(that: T, length: Int[,when : Bool])"
+msgstr "History(that: T, length: Int[,when : Bool])"
+
+#: ../../SpinalHDL/Libraries/utils.rst:90
+msgid "List[T]"
+msgstr "List[T]"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "Return a Vec of ``length`` elements"
+msgstr "返回长度为 ``length`` 的Vec"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid ""
+"The first element is ``that``\\ , the last one is ``that`` delayed by "
+"``length``\\ -1\\"
+msgstr "其第一个元素是 ``that`` ，最后一个元素是延迟了 ``length``\\ -1\\ 的``that``"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "The internal shift register sample when ``when`` is asserted"
+msgstr "内部移位寄存器会在 ``when`` 有效时采样"
+
+#: ../../SpinalHDL/Libraries/utils.rst:94
+msgid "BufferCC(input : T)"
+msgstr "BufferCC(input : T)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:96
+msgid ""
+"Return the input signal synchronized with the current clock domain by using "
+"2 flip flop"
+msgstr "返回利用两个触发器同步到当前时钟域的同步输入信号"
+
+#: ../../SpinalHDL/Libraries/utils.rst:100
+msgid "Counter"
+msgstr "计数器"
+
+#: ../../SpinalHDL/Libraries/utils.rst:102
+msgid "The Counter tool can be used to easily instantiate a hardware counter."
+msgstr "计数器工具可用于轻松实例化硬件计数器。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:108
+msgid "Instantiation syntax"
+msgstr "实例化语法"
+
+#: ../../SpinalHDL/Libraries/utils.rst:109
+#: ../../SpinalHDL/Libraries/utils.rst:152
+msgid "Notes"
+msgstr "备注"
+
+#: ../../SpinalHDL/Libraries/utils.rst:110
+msgid "``Counter(start: BigInt, end: BigInt[, inc : Bool])``"
+msgstr "``Counter(start: BigInt, end: BigInt[, inc : Bool])``"
+
+#: ../../SpinalHDL/Libraries/utils.rst:112
+msgid "``Counter(range : Range[, inc : Bool])``"
+msgstr "``Counter(range : Range[, inc : Bool])``"
+
+#: ../../SpinalHDL/Libraries/utils.rst:113
+msgid "Compatible with the  ``x to y`` ``x until y`` syntaxes"
+msgstr "与 ``x to y`` ``x until y`` 语法兼容"
+
+#: ../../SpinalHDL/Libraries/utils.rst:114
+msgid "``Counter(stateCount: BigInt[, inc : Bool])``"
+msgstr "``Counter(stateCount: BigInt[, inc : Bool])``"
+
+#: ../../SpinalHDL/Libraries/utils.rst:115
+msgid "Starts at zero and ends at ``stateCount - 1``"
+msgstr "从 0 开始，到 ``stateCount - 1`` 结束"
+
+#: ../../SpinalHDL/Libraries/utils.rst:116
+msgid "``Counter(bitCount: BitCount[, inc : Bool])``"
+msgstr "``Counter(bitCount: BitCount[, inc : Bool])``"
+
+#: ../../SpinalHDL/Libraries/utils.rst:117
+msgid "Starts at zero and ends at ``(1 << bitCount) - 1``"
+msgstr "从0开始到 ``(1 << bitCount) - 1`` 结束"
+
+#: ../../SpinalHDL/Libraries/utils.rst:119
+msgid "A counter can be controlled by methods, and wires can be read:"
+msgstr "计数器可以通过方法控制，并且可以连线可以被读取："
+
+#: ../../SpinalHDL/Libraries/utils.rst:135
+msgid ""
+"When a ``Counter`` overflows (reached end value), it restarts the next cycle"
+" to its start value."
+msgstr "当 ``Counter`` 溢出（达到最终值）时，它会重新启动下一个周期并设置为起始值。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:138
+msgid "Currently, only up counter are supported."
+msgstr "目前仅支持向上计数器。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:140
+msgid ""
+"``CounterFreeRun`` builds an always running counter: "
+"``CounterFreeRun(stateCount: BigInt)``."
+msgstr ""
+"``CounterFreeRun`` 构建一个始终运行的计数器： ``CounterFreeRun(stateCount: "
+"BigInt)`` 。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:143
+msgid "Timeout"
+msgstr "超时"
+
+#: ../../SpinalHDL/Libraries/utils.rst:145
+msgid ""
+"The Timeout tool can be used to easily instantiate an hardware timeout."
+msgstr "超时工具可用于方便地实例化一个硬件超时。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:151
+msgid "Instanciation syntax"
+msgstr "实例化语法"
+
+#: ../../SpinalHDL/Libraries/utils.rst:153
+msgid "Timeout(cycles : BigInt)"
+msgstr "Timeout(cycles : BigInt)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:154
+msgid "Tick after ``cycles`` clocks"
+msgstr "在 ``cycles`` 个时钟后标记"
+
+#: ../../SpinalHDL/Libraries/utils.rst:155
+msgid "Timeout(time : TimeNumber)"
+msgstr "Timeout(time : TimeNumber)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:156
+msgid "Tick after a ``time`` duration"
+msgstr "在持续 ``time`` 时间后标记"
+
+#: ../../SpinalHDL/Libraries/utils.rst:157
+msgid "Timeout(frequency : HertzNumber)"
+msgstr "Timeout(frequency : HertzNumber)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:158
+msgid "Tick at an ``frequency`` rate"
+msgstr "以 ``frequency``频率进行标记"
+
+#: ../../SpinalHDL/Libraries/utils.rst:161
+msgid ""
+"There is an example of different syntaxes which could be used with the "
+"Counter tool"
+msgstr "下方是可以与Counter工具一起使用的不同语法句式的示例"
+
+#: ../../SpinalHDL/Libraries/utils.rst:171
+msgid ""
+"If you instantiate an ``Timeout`` with an time or frequency setup, the "
+"implicit ``ClockDomain`` should have an frequency setting."
+msgstr "如果您使用时间或频率设置实例化 ``Timeout`` ，则隐含地 ``ClockDomain`` "
+"应该具有频率设置。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:174
+msgid "ResetCtrl"
+msgstr "复位控制"
+
+#: ../../SpinalHDL/Libraries/utils.rst:176
+msgid "The ResetCtrl provide some utilities to manage resets."
+msgstr "复位控制(ResetCtrl)提供了一些实用工具来管理复位。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:179
+msgid "asyncAssertSyncDeassert"
+msgstr "asyncAssertSyncDeassert"
+
+#: ../../SpinalHDL/Libraries/utils.rst:181
+msgid ""
+"You can filter an asynchronous reset by using an asynchronously asserted "
+"synchronously deaserted logic. To do it you can use the "
+"``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the "
+"filtered value."
+msgstr ""
+"您可以使用异步有效同步无效逻辑来筛选异步复位。为此，您可以使用 ``ResetCtrl."
+"asyncAssertSyncDeassert`` 函数返回筛选后的值。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:187
+msgid "Argument name"
+msgstr "参数名称"
+
+#: ../../SpinalHDL/Libraries/utils.rst:188
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Libraries/utils.rst:190
+msgid "input"
+msgstr "input"
+
+#: ../../SpinalHDL/Libraries/utils.rst:192
+msgid "Signal that should be filtered"
+msgstr "被筛选的信号"
+
+#: ../../SpinalHDL/Libraries/utils.rst:193
+msgid "clockDomain"
+msgstr "clockDomain"
+
+#: ../../SpinalHDL/Libraries/utils.rst:194
+msgid "ClockDomain"
+msgstr "ClockDomain"
+
+#: ../../SpinalHDL/Libraries/utils.rst:195
+msgid "ClockDomain which will use the filtered value"
+msgstr "返回将使用所筛选值的时钟域(ClockDomain)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:196
+msgid "inputPolarity"
+msgstr "inputPolarity"
+
+#: ../../SpinalHDL/Libraries/utils.rst:197
+#: ../../SpinalHDL/Libraries/utils.rst:200
+msgid "Polarity"
+msgstr "Polarity"
+
+#: ../../SpinalHDL/Libraries/utils.rst:198
+msgid "HIGH/LOW (default=HIGH)"
+msgstr "HIGH/LOW (default=HIGH)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:199
+msgid "outputPolarity"
+msgstr "outputPolarity"
+
+#: ../../SpinalHDL/Libraries/utils.rst:201
+msgid "HIGH/LOW (default=clockDomain.config.resetActiveLevel)"
+msgstr "HIGH/LOW (default=clockDomain.config.resetActiveLevel)"
+
+#: ../../SpinalHDL/Libraries/utils.rst:202
+msgid "bufferDepth"
+msgstr "bufferDepth"
+
+#: ../../SpinalHDL/Libraries/utils.rst:203
+#: ../../SpinalHDL/Libraries/utils.rst:220
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Libraries/utils.rst:204
+msgid "Number of register stages used to avoid metastability (default=2)"
+msgstr "防止亚稳态所需的寄存器级数（默认为2）"
+
+#: ../../SpinalHDL/Libraries/utils.rst:207
+msgid ""
+"There is also an ``ResetCtrl.asyncAssertSyncDeassertDrive`` version of tool "
+"which directly assign the ``clockDomain`` reset with the filtered value."
+msgstr ""
+"另外还有一个 ``ResetCtrl.asyncAssertSyncDeassertDrive`` 版本的工具，"
+"它直接使用筛选后的值为 ``clockDomain`` 的复位赋值。"
+
+#: ../../SpinalHDL/Libraries/utils.rst:210
+msgid "Special utilities"
+msgstr "特殊工具"
+
+#: ../../SpinalHDL/Libraries/utils.rst:219
+msgid "LatencyAnalysis(paths : Node*)"
+msgstr "LatencyAnalysis(paths : Node*)"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid ""
+"Return the shortest path, in terms of cycles, that travel through all nodes,"
+msgstr "以周期为单位返回经过所有节点的最短路径，"
+
+#: ../../SpinalHDL/Libraries/utils.rst
+msgid "from the first one to the last one"
+msgstr "第一个节点到最后一个节点"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/vexriscv.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/vexriscv.po
new file mode 100644
index 00000000000..bf4ba7f4c39
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/vexriscv.po
@@ -0,0 +1,89 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-02 16:08+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdllibrariesvexriscv/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:3
+msgid "VexRiscv (RV32IM CPU)"
+msgstr "VexRiscv（RV32IM CPU）"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:5
+msgid ""
+"VexRiscv is an fpga friendly RISC-V ISA CPU implementation with following "
+"features :"
+msgstr "VexRiscv 是一款 fpga 友好的 RISC-V 指令集架构（ISA）的 CPU "
+"实现，具有以下功能："
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:8
+msgid "RV32IM instruction set"
+msgstr "RV32IM指令集"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:9
+msgid "Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)"
+msgstr "分 5 级流水线处理（取指令、解码、执行、内存操作、回写）"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:10
+msgid "1.44 DMIPS/Mhz when all features are enabled"
+msgstr "启用所有功能时其性能为 1.44 DMIPS/Mhz"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:11
+msgid "Optimized for FPGA"
+msgstr "针对 FPGA 进行了优化"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:12
+msgid "Optional MUL/DIV extension"
+msgstr "可选的 MUL/DIV 扩展"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:13
+msgid "Optional instruction and data caches"
+msgstr "指令和数据缓存可选"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:14
+msgid "Optional MMU"
+msgstr "MMU 可选"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:15
+msgid ""
+"Optional debug extension allowing eclipse debugging via an GDB >> openOCD >>"
+" JTAG connection"
+msgstr "具有可选的调试扩展，它允许通过 GDB >> openOCD >> JTAG 连接并进行 Eclipse 调试"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:16
+msgid ""
+"Optional interrupts and exception handling with the Machine and the User "
+"mode from the riscv-privileged-v1.9.1 spec."
+msgstr "支持可选中断和异常处理，用于处理机器和用户模式下的中断、异常。（riscv-"
+"privileged-v1.9.1 规范规定）。"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:17
+msgid ""
+"Two implementation of shift instructions, Single cycle / shiftNumber cycles"
+msgstr "移位指令的两种实现方式，单周期/shiftNumber 周期"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:18
+msgid "Each stage could have bypass or interlock hazard logic"
+msgstr "每个流水线级中都可以有旁路或互锁冒险逻辑"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:19
+msgid "FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV"
+msgstr "FreeRTOS 移植版本在这里 https://github.com/Dolu1990/FreeRTOS-RISCV"
+
+#: ../../source/SpinalHDL/Libraries/vexriscv.rst:21
+msgid ""
+"Much more information there : `https://github.com/SpinalHDL/VexRiscv "
+"<https://github.com/SpinalHDL/VexRiscv>`_"
+msgstr ""
+"更多信息在这里：`https://github.com/SpinalHDL/VexRiscv <https://github.com/"
+"SpinalHDL/VexRiscv>`_"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/analog_inout.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/analog_inout.po
new file mode 100644
index 00000000000..fc77ae3561a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/analog_inout.po	
@@ -0,0 +1,135 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresanalog_inout/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:5 language
+msgid "Analog and inout"
+msgstr "模拟信号和输入输出"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:8 language
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:10 language
+msgid ""
+"You can define native tristate signals by using the ``Analog``/``inout`` "
+"features. These features were added for the following reasons:"
+msgstr "您可以使用 ``Analog``/``inout`` 功能定义三态信号。添加这些功能的原因有："
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:13 language
+msgid ""
+"Being able to add native tristate signals to the toplevel (it avoids having "
+"to manually wrap them with some hand-written VHDL/Verilog)."
+msgstr "能够将三态信号添加到顶层（它避免了必须用一些手写的 VHDL/Verilog 包装它们）。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:14 language
+msgid "Allowing the definition of blackboxes which contain ``inout`` pins."
+msgstr "允许定义包含 ``inout`` 引脚的黑盒。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:15 language
+msgid ""
+"Being able to connect a blackbox's ``inout`` pin through the hierarchy to a "
+"toplevel ``inout`` pin."
+msgstr "能够通过层次结构将黑盒的 ``inout`` 引脚连接到顶级 ``inout`` 引脚。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:17 language
+msgid ""
+"As those features were only added for convenience, please do not try other "
+"fancy stuff with tristate logic just yet."
+msgstr "由于这些功能只是为了方便而添加的，因此请不要尝试使用三态逻辑的其他花哨的东西"
+"。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:19 language
+msgid ""
+"If you want to model a component like a memory-mapped GPIO peripheral, "
+"please use the :ref:`TriState/TriStateArray <section-tristate>` bundles from"
+" the Spinal standard library, which abstract over the true nature of "
+"tristate drivers."
+msgstr ""
+"如果您想对内存映射 GPIO 外设等组件进行建模，请使用 Spinal 标准库中的 :ref:`"
+"TriState/TriStateArray <section-tristate>` 线束，它抽象了三态驱动程序的本质。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:22 language
+msgid "Analog"
+msgstr "模拟信号"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:24 language
+msgid ""
+"``Analog`` is the keyword which allows a signal to be defined as something "
+"analog, which in the digital world could mean ``0``, ``1``, or ``Z`` (the "
+"disconnected, high-impedance state)."
+msgstr ""
+"``Analog`` 是一个关键字，它允许将信号定义为模拟信号，在数字世界中可能意味着 "
+"``0``, ``1``, 或 ``Z`` （断开、高阻状态）。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:26
+#: features/analog_inout.rst:43 features/analog_inout.rst:66 language
+msgid "For instance:"
+msgstr "例如："
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:39 language
+msgid "inout"
+msgstr "输入/出"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:41 language
+msgid ""
+"``inout`` is the keyword which allows you to set an ``Analog`` signal as a "
+"bidirectional (both \"in\" and \"out\") signal."
+msgstr "``inout`` 是允许您将 ``Analog`` 信号设置为双向（“in”和“out”）信号的关键字。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:61 language
+msgid "InOutWrapper"
+msgstr "输入/出包装器"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:63 language
+msgid ""
+"``InOutWrapper`` is a tool which allows you to transform all ``master`` "
+"``TriState``/``TriStateArray``/``ReadableOpenDrain`` bundles of a component "
+"into native ``inout(Analog(...))`` signals. It allows you to keep your "
+"hardware description free of any ``Analog``/``inout`` things, and then "
+"transform the toplevel to make it synthesis ready."
+msgstr ""
+"``InOutWrapper`` 是一个工具，允许您将组件的所有 ``master`` "
+"``TriState``/``TriStateArray``/``ReadableOpenDrain`` 线束转换为 "
+"``inout(Analog(.. .))`` 信号。它允许您保持硬件描述不受任何 "
+"``Analog``/``inout`` 事物的影响，然后转换顶层以备综合。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:80 language
+msgid "Will generate:"
+msgstr "这将生成："
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:100 language
+msgid "Instead of:"
+msgstr "而不是："
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:123 language
+msgid "Manually driving Analog bundles"
+msgstr "手动驱动模拟线束"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:125 language
+msgid ""
+"If an ``Analog`` bundle is not driven, it will default to being high-Z. "
+"Therefore to manually implement a tristate driver (in case the "
+"``InOutWrapper`` type can't be used for some reason) you have to "
+"conditionally drive the signal."
+msgstr ""
+"如果 ``Analog`` "
+"线束没有被驱动，它将默认为高阻态。因此，要手动实现三态驱动程序（"
+"以防因某种原因无法使用 ``InOutWrapper`` 类型），您必须有条件地驱动信号。"
+
+#: ../../source/SpinalHDL/Other features/analog_inout.rst:128 language
+msgid "To manually connect a ``TriState`` signal to an ``Analog`` bundle:"
+msgstr "手动将 ``TriState`` 信号连接到 ``Analog`` 线束："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po
new file mode 100644
index 00000000000..7a3350e4c8f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/assertion.po	
@@ -0,0 +1,85 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresassertion/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:3 language
+msgid "Assertions"
+msgstr "Assertions"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:5 language
+msgid ""
+"In addition to Scala run-time assertions, you can add hardware assertions "
+"using the following syntax:"
+msgstr "除了 Scala 运行时断言之外，您还可以使用以下语法添加硬件断言："
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:7 language
+msgid ""
+"``assert(assertion : Bool, message : String = null, severity: "
+"AssertNodeSeverity = Error)``"
+msgstr ""
+"``assert(assertion : Bool, message : String = null, severity: "
+"AssertNodeSeverity = Error)``"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:9 language
+msgid "Severity levels are:"
+msgstr "严重性等级是："
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:15 language
+msgid "Name"
+msgstr "名称"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:16 language
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:17 language
+msgid "NOTE"
+msgstr "NOTE"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:18 language
+msgid "Used to report an informative message"
+msgstr "用于报告提示性消息"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:19 language
+msgid "WARNING"
+msgstr "WARNING"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:20 language
+msgid "Used to report an unusual case"
+msgstr "用于报告异常情况"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:21 language
+msgid "ERROR"
+msgstr "ERROR"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:22 language
+msgid "Used to report an situation that should not happen"
+msgstr "用于报告不应该发生的情况"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:23 language
+msgid "FAILURE"
+msgstr "FAILURE"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:24 language
+msgid "Used to report a fatal situation and close the simulation"
+msgstr "用于报告致命情况并关闭仿真"
+
+#: ../../source/SpinalHDL/Other features/assertion.rst:27 language
+msgid ""
+"One practical example could be to check that the ``valid`` signal of a "
+"handshake protocol never drops when ``ready`` is low:"
+msgstr "一个实际的例子是检查当 ``ready`` 为低电平时，握手协议的 ``valid`` "
+"信号不应该由高变低："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/index.po
new file mode 100644
index 00000000000..6bf1b8dc3a4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/index.po	
@@ -0,0 +1,83 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Other features/index.rst:3 language
+msgid "Other language features"
+msgstr "其他语言功能"
+
+#: ../../SpinalHDL/Other features/index.rst:5 language
+msgid "The core of the language defines the syntax for many features:"
+msgstr "该语言的核心定义了许多功能性语法："
+
+#: ../../SpinalHDL/Other features/index.rst:7 language
+msgid "Types / Literals"
+msgstr "类型/字面量"
+
+#: ../../SpinalHDL/Other features/index.rst:8 language
+msgid "Register / Clock domains"
+msgstr "寄存器/时钟域"
+
+#: ../../SpinalHDL/Other features/index.rst:9 language
+msgid "Component / Area"
+msgstr "组件/逻辑区"
+
+#: ../../SpinalHDL/Other features/index.rst:10 language
+msgid "RAM / ROM"
+msgstr "随机访问/只读存储器"
+
+#: ../../SpinalHDL/Other features/index.rst:11 language
+msgid "When / Switch / Mux"
+msgstr "When / Switch / Mux"
+
+#: ../../SpinalHDL/Other features/index.rst:12 language
+msgid "BlackBox (to integrate VHDL or Verilog IPs inside Spinal)"
+msgstr "BlackBox（在 Spinal 内部集成 VHDL 或 Verilog IP）"
+
+#: ../../SpinalHDL/Other features/index.rst:13 language
+msgid "SpinalHDL to VHDL converter"
+msgstr "SpinalHDL 到 VHDL 的转换器"
+
+#: ../../SpinalHDL/Other features/index.rst:15 language
+msgid ""
+"Then, by using these features, you can define digital hardware, and also "
+"build powerful libraries and abstractions. It's one of the major advantages "
+"of SpinalHDL over other commonly used HDLs, because you can extend the "
+"language without having knowledge about the compiler."
+msgstr ""
+"然后，通过使用这些功能，您可以定义数字硬件，并构建强大的库和抽象。这也是 "
+"SpinalHDL 相对于其他常用 HDL "
+"的主要优势之一，因为您无需了解编译器内部原理即可扩展该语言。"
+
+#: ../../SpinalHDL/Other features/index.rst:18 language
+msgid ""
+"One good example of this is the :ref:`SpinalHDL lib <lib_introduction>` "
+"which adds many utilities, tools, buses, and methodologies."
+msgstr "一个很好的例子是 :ref:`SpinalHDL lib "
+"<lib_introduction>`，它添加了许多实用程序、工具、总线和方法。"
+
+#: ../../SpinalHDL/Other features/index.rst:20 language
+msgid ""
+"To use features introduced in the following chapter you need to ``import "
+"spinal.core._`` in your sources."
+msgstr "要使用下一章中介绍的功能，您需要在源代码中加入 ``import spinal.core._`` 。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po
new file mode 100644
index 00000000000..64bd56634c6
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po	
@@ -0,0 +1,44 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: 2024-01-26 17:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresreport/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Other features/report.rst:3 language
+msgid "Report"
+msgstr "Report"
+
+#: ../../SpinalHDL/Other features/report.rst:5 language
+msgid "You can add debugging in RTL for simulation, using the following syntax:"
+msgstr "您可以使用以下语法在 RTL 中添加调试以进行仿真："
+
+#: ../../SpinalHDL/Other features/report.rst:21 language
+msgid "It will generate the following Verilog code for example:"
+msgstr "例如，它将生成以下 Verilog 代码："
+
+#: ../../SpinalHDL/Other features/report.rst:27 language
+msgid "Since SpinalHDL 1.4.4, the following syntax is also supported:"
+msgstr "从 SpinalHDL 1.4.4 开始，还支持以下语法："
+
+#: ../../SpinalHDL/Other features/report.rst:33 language
+msgid "You can display the current simulation time using the REPORT_TIME object"
+msgstr "可以使用 REPORT_TIME 对象显示当前仿真时间"
+
+#: ../../SpinalHDL/Other features/report.rst:39 language
+msgid "will result in:"
+msgstr "会导致："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po
new file mode 100644
index 00000000000..dfaecca144e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po	
@@ -0,0 +1,56 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresscope_property/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:4 language
+msgid "ScopeProperty"
+msgstr "ScopeProperty"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:6 language
+msgid ""
+"A scope property is a thing which can store values locally to the current "
+"thread. Its API can be used to set/get that value, but also to apply "
+"modification to the value for a portion of the execution in a stack manner."
+msgstr "范围属性是可以在当前线程本地存储值的东西。它的 API "
+"可用于设置/获取该值，还可以以堆栈方式对部分值进行修改。"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:8 language
+msgid ""
+"In other words it is a alternative to global variable, scala implicit, "
+"ThreadLocal."
+msgstr "换句话说，它是全局变量、scala 隐式变量、线程本地变量（ThreadLocal） "
+"的替代品。"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:10 language
+msgid ""
+"To compare with global variable, It allow to run multiple thread running the"
+" same code indepedently"
+msgstr "与全局变量相比，它允许运行多个线程独立运行相同的代码"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:11 language
+msgid "To compare with scala implicit, it is less intrusive in the code base"
+msgstr "与 scala 隐式变量相比，它与代码库的耦合较小"
+
+#: ../../SpinalHDL/Other features/scope_property.rst:12 language
+msgid ""
+"To compare with ThreadLocal, it has some API to collect all ScopeProperty "
+"and restore them in the same state later on"
+msgstr "与线程本地变量（ThreadLocal） 相比，它有一些 API "
+"可以收集所有范围属性并稍后将它们恢复到相同状态"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po
new file mode 100644
index 00000000000..022c5f37b5c
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po	
@@ -0,0 +1,56 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-03 17:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresstub/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../SpinalHDL/Other features/stub.rst:3 language
+msgid "Stub"
+msgstr "存根（Stub）"
+
+#: ../../SpinalHDL/Other features/stub.rst:5 language
+msgid "You can empty an Component Hierarchy as stub:"
+msgstr "您可以将组件层次结构清空作为一个存根（stub）："
+
+#: ../../SpinalHDL/Other features/stub.rst:20 language
+msgid "It will generate the following Verilog code for example:"
+msgstr "例如，它将生成以下 Verilog 代码："
+
+#: ../../SpinalHDL/Other features/stub.rst:43 language
+msgid "You can also empty the top Component"
+msgstr "您还可以清空顶部组件"
+
+#: ../../SpinalHDL/Other features/stub.rst:49 language
+msgid "What does `stub` do ?"
+msgstr "`stub` 有什么作用？"
+
+#: ../../SpinalHDL/Other features/stub.rst:51 language
+msgid "first walk all the components and find out clock, then keep clock"
+msgstr "首先遍历所有组件并找出时钟，然后保留时钟"
+
+#: ../../SpinalHDL/Other features/stub.rst:52 language
+msgid "then remove all children component"
+msgstr "然后删除所有子组件"
+
+#: ../../SpinalHDL/Other features/stub.rst:53 language
+msgid "then remove all assignment and logic we dont want"
+msgstr "然后删除我们不需要的所有赋值和逻辑"
+
+#: ../../SpinalHDL/Other features/stub.rst:54 language
+msgid "tile 0 to output port"
+msgstr "给输出端口赋值0"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po
new file mode 100644
index 00000000000..aadc0ce5238
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po	
@@ -0,0 +1,397 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresutils/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Other features/utils.rst:4 language
+msgid "Utils"
+msgstr "实用工具"
+
+#: ../../SpinalHDL/Other features/utils.rst:7 language
+msgid "General"
+msgstr "介绍"
+
+#: ../../SpinalHDL/Other features/utils.rst:9 language
+msgid ""
+"Many tools and utilities are present in :ref:`spinal.lib <lib_introduction>`"
+" but some are already present in the SpinalHDL Core."
+msgstr ""
+"许多工具和实用程序都存在于 :ref:`spinal.lib <lib_introduction>` 中，"
+"但有些工具和实用程序已经存在于 SpinalHDL Core 中。"
+
+#: ../../SpinalHDL/Other features/utils.rst:15 language
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Other features/utils.rst:16 language
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Other features/utils.rst:17 language
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Other features/utils.rst:18 language
+msgid "``widthOf(x : BitVector)``"
+msgstr "``widthOf(x : BitVector)``"
+
+#: ../../SpinalHDL/Other features/utils.rst:19 features/utils.rst:22 language
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/Other features/utils.rst:20 language
+msgid "Return the width of a Bits/UInt/SInt signal"
+msgstr "返回 Bits/UInt/SInt 信号的位宽"
+
+#: ../../SpinalHDL/Other features/utils.rst:21 language
+msgid "``log2Up(x : BigInt)``"
+msgstr "``log2Up(x : BigInt)``"
+
+#: ../../SpinalHDL/Other features/utils.rst:23 language
+msgid "Return the number of bits needed to represent ``x`` states"
+msgstr "返回表示 ``x`` 状态所需的位数"
+
+#: ../../SpinalHDL/Other features/utils.rst:24 language
+msgid "``isPow2(x : BigInt)``"
+msgstr "``isPow2(x：BigInt)``"
+
+#: ../../SpinalHDL/Other features/utils.rst:25 language
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../SpinalHDL/Other features/utils.rst:26 language
+msgid "Return true if ``x`` is a power of two"
+msgstr "如果 ``x`` 是 2 的幂，则返回 true"
+
+#: ../../SpinalHDL/Other features/utils.rst:27 language
+msgid "``roundUp(that : BigInt, by : BigInt)``"
+msgstr "``roundUp(that : BigInt, by : BigInt)``"
+
+#: ../../SpinalHDL/Other features/utils.rst:28 language
+msgid "BigInt"
+msgstr "BigInt"
+
+#: ../../SpinalHDL/Other features/utils.rst:29 language
+msgid "Return the first ``by`` multiply from ``that`` (included)"
+msgstr "返回第一个 ``by`` 乘以 ``that``（包含） 的值"
+
+#: ../../SpinalHDL/Other features/utils.rst:30 language
+msgid "``Cat(x: Data*)``"
+msgstr "``Cat(x: Data*)``"
+
+#: ../../SpinalHDL/Other features/utils.rst:31 features/utils.rst:34 language
+msgid "Bits"
+msgstr "位"
+
+#: ../../SpinalHDL/Other features/utils.rst:32 language
+msgid "Concatenate all arguments, from MSB to LSB, see `Cat`_"
+msgstr "连接所有参数，从 MSB 到 LSB，请参阅 `Cat`_"
+
+#: ../../SpinalHDL/Other features/utils.rst:33 language
+msgid "``Cat(x: Iterable[Data])``"
+msgstr "``Cat(x: Iterable[Data])``"
+
+#: ../../SpinalHDL/Other features/utils.rst:35 language
+msgid "Conactenate arguments, from LSB to MSB, see `Cat`_"
+msgstr "连接参数, 从 LSB 到 MSB, 参见 `Cat`_"
+
+#: ../../SpinalHDL/Other features/utils.rst:40 language
+msgid "Cat"
+msgstr "Cat"
+
+#: ../../SpinalHDL/Other features/utils.rst:42 language
+msgid ""
+"As listed above, there are two version of ``Cat``. Both versions concatenate"
+" the signals they contain, with a subtle difference:"
+msgstr "如上所述， ``Cat`` "
+"有两个版本。两个版本都连接了它们包含的信号，但有细微的差别："
+
+#: ../../SpinalHDL/Other features/utils.rst:44 language
+msgid ""
+"``Cat(x: Data*)`` takes an arbitrary number of hardware signals as "
+"parameters. It mimics other HDLs and the leftmost parameter becomes the MSB "
+"of the resulting ``Bits``, the rightmost the LSB side. Said differently: the"
+" input is concatenated in the order as written."
+msgstr ""
+"``Cat(x: Data*)`` 使用任意数量的硬件信号作为参数。"
+"它模拟了其他HDL且MSB变成了结果 ``Bits`` 最左端的参数，最右端是 LSB . "
+"换种说法：输入按照参数顺序拼接."
+
+#: ../../SpinalHDL/Other features/utils.rst:47 language
+msgid ""
+"``Cat(x: Iterable[Data])`` which takes a single Scala iterable collection "
+"(Seq / Set / List / ...) containing hardware signals. This version places "
+"the first element of the list into the LSB, and the last into the MSB."
+msgstr ""
+"``Cat(x: Iterable[Data])`` 接受包含硬件信号的单个 Scala 可迭代集合（Seq / "
+"Set / List / ...）。此版本将列表的第一个元素放入 LSB，最后一个元素放入 MSB。"
+
+#: ../../SpinalHDL/Other features/utils.rst:50 language
+msgid ""
+"This seeming difference comes mostly from the convention that ``Bits`` are "
+"written from the hightest index to the lowest index, while Lists are written"
+" down starting from index 0 to the highest index. ``Cat`` places index 0 of "
+"both conventions at the LSB."
+msgstr ""
+"差异主要在于这样的约定： ``Bits`` 是从最高索引到最低索引写入的，"
+"而列表是从索引 0 开始写入到最高索引的。 所有约定中，``Cat`` 将索引 0 放置在 "
+"LSB 处。"
+
+#: ../../SpinalHDL/Other features/utils.rst:65 language
+msgid "Cloning hardware datatypes"
+msgstr "克隆硬件数据类型"
+
+#: ../../SpinalHDL/Other features/utils.rst:67 language
+msgid ""
+"You can clone a given hardware data type by using the ``cloneOf(x)`` "
+"function. It will return a new instance of the same Scala type and "
+"parameters."
+msgstr "您可以使用 ``cloneOf(x)`` 函数克隆给定的硬件数据类型。它将返回相同 Scala "
+"类型和参数的新实例。"
+
+#: ../../SpinalHDL/Other features/utils.rst:70 language
+msgid "For example:"
+msgstr "例如："
+
+#: ../../SpinalHDL/Other features/utils.rst:84 language
+msgid ""
+"You can get more information about how hardware data types are managed on "
+"the :ref:`Hardware types page <hardware_type>`."
+msgstr "您可以在 :ref:`硬件类型页面 <hardware_type>` "
+"上获取有关如何管理硬件数据类型的更多信息。"
+
+#: ../../SpinalHDL/Other features/utils.rst:87 language
+msgid ""
+"If you use the ``cloneOf`` function on a ``Bundle``, this ``Bundle`` should "
+"be a ``case class`` or should override the clone function internally."
+msgstr ""
+"如果你在 ``Bundle`` 上使用 ``cloneOf`` 函数，这个 ``Bundle`` 应该是一个 ``"
+"case class`` ，否则应该在内部重写clone函数。"
+
+#: ../../SpinalHDL/Other features/utils.rst:105 language
+msgid "Passing a datatype as construction parameter"
+msgstr "将数据类型作为构造函数参数传递"
+
+#: ../../SpinalHDL/Other features/utils.rst:107 language
+msgid ""
+"Many pieces of reusable hardware need to be parameterized by some data type."
+" For example if you want to define a FIFO or a shift register, you need a "
+"parameter to specify which kind of payload you want for the component."
+msgstr "许多可重用硬件需要通过数据类型进行参数化。例如，如果您想定义 FIFO "
+"或移位寄存器，则需要一个参数来指定组件所需的有效负载类型。"
+
+#: ../../SpinalHDL/Other features/utils.rst:110 language
+msgid "There are two similar ways to do this."
+msgstr "有两种类似的方法可以做到这一点。"
+
+#: ../../SpinalHDL/Other features/utils.rst:113 language
+msgid "The old way"
+msgstr "老办法"
+
+#: ../../SpinalHDL/Other features/utils.rst:115 language
+msgid ""
+"A good example of the old way to do this is in this definition of a "
+"``ShiftRegister`` component:"
+msgstr "老方法的一个很好的例子是 ``ShiftRegister`` 组件的定义："
+
+#: ../../SpinalHDL/Other features/utils.rst:127 language
+msgid "And here is how you can instantiate the component:"
+msgstr "以下是实例化该组件的方法："
+
+#: ../../SpinalHDL/Other features/utils.rst:133 language
+msgid ""
+"As you can see, the raw hardware type is directly passed as a construction "
+"parameter. Then each time you want to create an new instance of that kind of"
+" hardware data type, you need to use the ``cloneOf(...)`` function. Doing "
+"things this way is not super safe as it's easy to forget to use ``cloneOf``."
+msgstr ""
+"如您所见，原始硬件类型直接作为构造参数传递。每次你想创建这种硬件数据类型的新"
+"实例时，你需要使用 ``cloneOf(...)`` 函数。以这种方式做事并不是超级安全，"
+"因为很容易忘记使用 ``cloneOf``。"
+
+#: ../../SpinalHDL/Other features/utils.rst:138 language
+msgid "The safe way"
+msgstr "安全的方法"
+
+#: ../../SpinalHDL/Other features/utils.rst:140 language
+msgid ""
+"An example of the safe way to pass a data type parameter is as follows:"
+msgstr "安全的传递数据类型参数方法，示例如下："
+
+#: ../../SpinalHDL/Other features/utils.rst:152 language
+msgid ""
+"And here is how you instantiate the component (exactly the same as before):"
+msgstr "以下是实例化组件的方法（与之前完全相同）："
+
+#: ../../SpinalHDL/Other features/utils.rst:158 language
+msgid ""
+"Notice how the example above uses a ``HardType`` wrapper around the raw data"
+" type ``T``, which is a \"blueprint\" definition of a hardware data type. "
+"This way of doing things is easier to use than the \"old way\", because to "
+"create a new instance of the hardware data type you only need to call the "
+"``apply`` function of that ``HardType`` (or in other words, just add "
+"parentheses after the parameter)."
+msgstr ""
+"请注意，上述示例中使用了一个 ``HardType`` 包装器，它包装了原始数据类型 "
+"``T``，这种做法比“旧方法”更容易使用。因为要创建硬件数据类型的新实例，"
+"只需调用 ``HardType`` 的 ``apply`` 函数（或者换句话说，在类型名后添加括号）。"
+
+#: ../../SpinalHDL/Other features/utils.rst:161 language
+msgid ""
+"Additionally, this mechanism is completely transparent from the point of "
+"view of the user, as a hardware data type can be implicitly converted into a"
+" ``HardType``."
+msgstr "此外，从用户的角度来看，这种机制是完全透明的，因为硬件数据类型可以隐式转换为 "
+"``HardType``。"
+
+#: ../../SpinalHDL/Other features/utils.rst:164 language
+msgid "Frequency and time"
+msgstr "频率和时间"
+
+#: ../../SpinalHDL/Other features/utils.rst:166 language
+msgid "SpinalHDL has a dedicated syntax to define frequency and time values:"
+msgstr "SpinalHDL 有专用语法来定义频率和时间值："
+
+#: ../../SpinalHDL/Other features/utils.rst:177 language
+msgid ""
+"For time definitions you can use following postfixes to get a "
+"``TimeNumber``:"
+msgstr "对于时间定义，您可以使用以下后缀来获取 ``TimeNumber``："
+
+#: ../../SpinalHDL/Other features/utils.rst:178 language
+msgid "``fs``, ``ps``, ``ns``, ``us``, ``ms``, ``sec``, ``mn``, ``hr``"
+msgstr "``fs``、``ps``、``ns``、``us``、``ms``、``sec``、``mn``、``hr``"
+
+#: ../../SpinalHDL/Other features/utils.rst:180 language
+msgid ""
+"For time definitions you can use following postfixes to get a "
+"``HertzNumber``:"
+msgstr "对于时间定义，您可以使用以下后缀来获取 ``HertzNumber``："
+
+#: ../../SpinalHDL/Other features/utils.rst:181 language
+msgid "``Hz``, ``KHz``, ``MHz``, ``GHz``, ``THz``"
+msgstr "``Hz``, ``KHz``, ``MHz``, ``GHz``, ``THz``"
+
+#: ../../SpinalHDL/Other features/utils.rst:183 language
+msgid ""
+"``TimeNumber`` and ``HertzNumber`` are based on the ``PhysicalNumber`` class"
+" which use  scala ``BigDecimal`` to store numbers."
+msgstr ""
+"``TimeNumber`` 和 ``HertzNumber`` 是基于 ``PhysicalNumber`` 类，它使用 scala "
+"``BigDecimal`` 来存储数字。"
+
+#: ../../SpinalHDL/Other features/utils.rst:186 language
+msgid "Binary prefix"
+msgstr "二进制前缀"
+
+#: ../../SpinalHDL/Other features/utils.rst:188 language
+msgid ""
+"SpinalHDL allows the definition of integer numbers using binary prefix "
+"notation according to IEC."
+msgstr "SpinalHDL 允许根据 IEC 使用二进制前缀表示法定义整数。"
+
+#: ../../SpinalHDL/Other features/utils.rst:195 language
+msgid "The following binary prefix notations are available:"
+msgstr "可以使用以下二进制前缀表示法："
+
+#: ../../SpinalHDL/Other features/utils.rst:201 language
+msgid "Binary Prefix"
+msgstr "二进制前缀"
+
+#: ../../SpinalHDL/Other features/utils.rst:202 language
+msgid "Value"
+msgstr "值"
+
+#: ../../SpinalHDL/Other features/utils.rst:203 language
+msgid "Byte, Bytes"
+msgstr "Byte, Bytes"
+
+#: ../../SpinalHDL/Other features/utils.rst:204 language
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Other features/utils.rst:205 language
+msgid "KiB"
+msgstr "KiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:206 language
+msgid "1024 == 1 << 10"
+msgstr "1024 == 1 << 10"
+
+#: ../../SpinalHDL/Other features/utils.rst:207 language
+msgid "MiB"
+msgstr "MiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:208 language
+msgid "1024\\ :sup:`2` == 1 << 20"
+msgstr "1024\\ :sup:`2` == 1 << 20"
+
+#: ../../SpinalHDL/Other features/utils.rst:209 language
+msgid "GiB"
+msgstr "GiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:210 language
+msgid "1024\\ :sup:`3` == 1 << 30"
+msgstr "1024\\ :sup:`3` == 1 << 30"
+
+#: ../../SpinalHDL/Other features/utils.rst:211 language
+msgid "TiB"
+msgstr "TiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:212 language
+msgid "1024\\ :sup:`4` == 1 << 40"
+msgstr "1024\\ :sup:`4` == 1 << 40"
+
+#: ../../SpinalHDL/Other features/utils.rst:213 language
+msgid "PiB"
+msgstr "PiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:214 language
+msgid "1024\\ :sup:`5` == 1 << 50"
+msgstr "1024\\ :sup:`5` == 1 << 50"
+
+#: ../../SpinalHDL/Other features/utils.rst:215 language
+msgid "EiB"
+msgstr "EiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:216 language
+msgid "1024\\ :sup:`6` == 1 << 60"
+msgstr "1024\\ :sup:`6` == 1 << 60"
+
+#: ../../SpinalHDL/Other features/utils.rst:217 language
+msgid "ZiB"
+msgstr "ZiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:218 language
+msgid "1024\\ :sup:`7` == 1 << 70"
+msgstr "1024\\ :sup:`7` == 1 << 70"
+
+#: ../../SpinalHDL/Other features/utils.rst:219 language
+msgid "YiB"
+msgstr "YiB"
+
+#: ../../SpinalHDL/Other features/utils.rst:220 language
+msgid "1024\\ :sup:`8` == 1 << 80"
+msgstr "1024\\ :sup:`8` == 1 << 80"
+
+#: ../../SpinalHDL/Other features/utils.rst:223 language
+msgid ""
+"Of course, BigInt can also be printed as a string in bytes unit. "
+"``BigInt(1024).byteUnit``."
+msgstr "当然，BigInt 可以以字节为单位进行打印。例如，``BigInt(1024).byteUnit``."
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po
new file mode 100644
index 00000000000..45e9d2ecf99
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po	
@@ -0,0 +1,335 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlother-language-featuresvhdl_generation/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:5 language
+msgid "VHDL and Verilog generation"
+msgstr "VHDL 和 Verilog 生成"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:8 language
+msgid "Generate VHDL and Verilog from a SpinalHDL Component"
+msgstr "从 SpinalHDL 组件生成 VHDL 和 Verilog"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:10 language
+msgid ""
+"To generate the VHDL from a SpinalHDL component you just need to call "
+"``SpinalVhdl(new YourComponent)`` in a Scala ``main``."
+msgstr ""
+"要从 SpinalHDL 组件生成 VHDL，您只需在 Scala ``main`` 函数中调用 "
+"``SpinalVhdl(new YourComponent)`` 即可。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:12 language
+msgid ""
+"Generating Verilog is exactly the same, but with ``SpinalVerilog`` in place "
+"of ``SpinalVHDL``"
+msgstr "生成 Verilog 完全相同，但用 ``SpinalVerilog`` 代替 ``SpinalVHDL``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:40 language
+msgid ""
+"``SpinalVhdl`` and ``SpinalVerilog`` may need to create multiple instances "
+"of your component class, therefore the first argument is not a ``Component``"
+" reference, but a function that returns a new component."
+msgstr ""
+"``SpinalVhdl`` 和 ``SpinalVerilog`` 可能需要创建组件类的多个实例，"
+"因此第一个参数不是 ``Component`` 引用，而是返回新组件的函数。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:43 language
+msgid ""
+"The ``SpinalVerilog`` implementation began the 5th of June, 2016. This "
+"backend successfully passes the same regression tests as the VHDL one (RISCV"
+" CPU, Multicore and pipelined mandelbrot, UART RX/TX, Single clock fifo, "
+"Dual clock fifo, Gray counter, ...)."
+msgstr ""
+"``SpinalVerilog`` 实施于 2016 年 6 月 5 日开始。该后端成功通过了与 VHDL "
+"相同的回归测试（RISCV CPU、多核和流水线 Mandelbrot、UART RX/TX、单时钟域 "
+"fifo、双时钟域 fifo、格雷码计数器， ...）。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:46 language
+msgid ""
+"If you have any issues with this new backend, please make a `Github issue "
+"<https://github.com/SpinalHDL/SpinalHDL/issues>`_ describing the problem."
+msgstr ""
+"如果您对这个新后端有任何问题，请创建 `Github 工单 <https://github.com/"
+"SpinalHDL/SpinalHDL/issues>`_ 描述问题。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:49 language
+msgid "Parametrization from Scala"
+msgstr "Scala 的参数化"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:55 language
+msgid "Argument name"
+msgstr "参数名称"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:56 language
+msgid "Type"
+msgstr "类型"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:57 language
+msgid "Default"
+msgstr "默认值"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:58
+#: features/vhdl_generation.rst:292 language
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:59 language
+msgid "``mode``"
+msgstr "``mode``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:60 language
+msgid "SpinalMode"
+msgstr "SpinalMode"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:61 language
+msgid "null"
+msgstr "null"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "Set the SpinalHDL hdl generation mode."
+msgstr "设置 SpinalHDL 生成HDL的模式。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "Can be set to ``VHDL`` or ``Verilog``"
+msgstr "可以设置为 ``VHDL`` 或 ``Verilog``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:64 language
+msgid "``defaultConfigForClockDomains``"
+msgstr "``defaultConfigForClockDomains``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:65 language
+msgid "ClockDomainConfig"
+msgstr "ClockDomainConfig"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "RisingEdgeClock"
+msgstr "RisingEdgeClock"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "AsynchronousReset"
+msgstr "AsynchronousReset"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "ResetActiveHigh"
+msgstr "ResetActiveHigh"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst language
+msgid "ClockEnableActiveHigh"
+msgstr "ClockEnableActiveHigh"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:70 language
+msgid ""
+"Set the clock configuration that will be used as the default value for all "
+"new ``ClockDomain``."
+msgstr "设置将用作所有新 ``ClockDomain``时钟域默认值的配置。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:71 language
+msgid "``onlyStdLogicVectorAtTopLevelIo``"
+msgstr "``onlyStdLogicVectorAtTopLevelIo``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:72 language
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:73 language
+msgid "false"
+msgstr "false"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:74 language
+msgid "Change all unsigned/signed toplevel io into std_logic_vector."
+msgstr "将所有无符号/有符号顶级 io 更改为 std_logic_vector类型。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:75 language
+msgid "``defaultClockDomainFrequency``"
+msgstr "``defaultClockDomainFrequency``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:76 language
+msgid "IClockDomainFrequency"
+msgstr "IClockDomainFrequency"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:77 language
+msgid "UnknownFrequency"
+msgstr "UnknownFrequency"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:78 language
+msgid "Default clock frequency."
+msgstr "默认时钟频率。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:79 language
+msgid "``targetDirectory``"
+msgstr "``targetDirectory``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:80 language
+msgid "String"
+msgstr "String"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:81 language
+msgid "Current directory"
+msgstr "当前目录"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:82 language
+msgid "Directory where files are generated."
+msgstr "生成文件的目录。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:85 language
+msgid "And this is the syntax to specify them:"
+msgstr "这是设置它们的语法："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:98 language
+msgid "Parametrization from shell"
+msgstr "来自 shell 的参数化"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:100 language
+msgid ""
+"You can also specify generation parameters by using command line arguments."
+msgstr "您还可以使用命令行参数指定生成参数。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:108 language
+msgid "The syntax for command line arguments is:"
+msgstr "命令行参数的语法是："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:124 language
+msgid "Generated VHDL and Verilog"
+msgstr "生成的 VHDL 和 Verilog"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:126 language
+msgid ""
+"How a SpinalHDL RTL description is translated into VHDL and Verilog is "
+"important:"
+msgstr "如何将 SpinalHDL RTL 描述转换为 VHDL 和 Verilog 非常重要："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:128 language
+msgid "Names in Scala are preserved in VHDL and Verilog."
+msgstr "Scala 中变量的名称将保留在 VHDL 和 Verilog 中。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:129 language
+msgid "``Component`` hierarchy in Scala is preserved in VHDL and Verilog."
+msgstr "Scala 中的 ``Component`` 组件层次结构会保留在 VHDL 和 Verilog 中。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:130 language
+msgid ""
+"``when`` statements in Scala are emitted as if statements in VHDL and "
+"Verilog."
+msgstr "Scala 中的 ``when`` 语句会生成为 VHDL 和 Verilog 中的 if 语句。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:131 language
+msgid ""
+"``switch`` statements in Scala are emitted as case statements in VHDL and "
+"Verilog in all standard cases."
+msgstr "Scala 中的 ``switch`` 语句在所有标准情况下都生成为 VHDL 和 Verilog 中的 case "
+"语句。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:134 language
+msgid "Organization"
+msgstr "组织"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:136 language
+msgid ""
+"When you use the VHDL generator, all modules are generated into a single "
+"file which contain three sections:"
+msgstr "当您使用 VHDL 生成器时，所有模块都会生成到一个文件中，其中包含三个部分："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:138 language
+msgid "A package that contains the definition of all Enums"
+msgstr "包含所有 Enum 定义的包"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:139 language
+msgid "A package that contains functions used by the architectural elements"
+msgstr "包含架构中所有元素使用函数的包"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:140 language
+msgid "All components needed by your design"
+msgstr "您的设计所需的所有组件"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:142 language
+msgid ""
+"When you use the Verilog generation, all modules are generated into a single"
+" file which contains two sections:"
+msgstr "当您使用 Verilog 生成时，所有模块都会生成到一个文件中，其中包含两个部分："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:144 language
+msgid "All enumeration definitions used"
+msgstr "使用的所有枚举定义"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:145 language
+msgid "All modules needed by your design"
+msgstr "您的设计需要的所有模块"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:148 language
+msgid "Combinational logic"
+msgstr "组合逻辑"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:150
+#: features/vhdl_generation.rst:213 language
+msgid "Scala:"
+msgstr "Scala:"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:178
+#: features/vhdl_generation.rst:238 language
+msgid "VHDL:"
+msgstr "VHDL:"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:211 language
+msgid "Sequential logic"
+msgstr "时序逻辑"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:281 language
+msgid "VHDL and Verilog attributes"
+msgstr "VHDL 和 Verilog 属性"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:283 language
+msgid ""
+"In some situations, it is useful to give attributes for some signals in a "
+"design to modify how they are synthesized."
+msgstr "在某些情况下，为设计中的某些信号提供属性以修改它们的综合方式很有用。"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:285 language
+msgid ""
+"To do that, you can call the following functions on any signals or memories "
+"in the design:"
+msgstr "为此，您可以对设计中的任何信号或存储器调用以下函数："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:291 language
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:293 language
+msgid "``addAttribute(name)``"
+msgstr "``addAttribute(name)``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:294 language
+msgid "Add a boolean attribute with the given ``name`` set to true"
+msgstr "添加一个名为 ``name`` 的布尔属性，并将给定值设置为 true"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:295 language
+msgid "``addAttribute(name, value)``"
+msgstr "``addAttribute(name, value)``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:296 language
+msgid "Add a string attribute with the given ``name`` set to ``value``"
+msgstr "添加一个字符串属性，并将给定的 ``name`` 设置为 ``value``"
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:299 language
+msgid "Example:"
+msgstr "示例："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:306 language
+msgid "Produced declaration in VHDL:"
+msgstr "用 VHDL 生成声明："
+
+#: ../../source/SpinalHDL/Other features/vhdl_generation.rst:314 language
+msgid "Produced declaration in Verilog:"
+msgstr "用 Verilog 生成声明："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po
new file mode 100644
index 00000000000..90b9e177ab1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po
@@ -0,0 +1,274 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 09:29+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsemanticassignments/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:2
+msgid "Assignments"
+msgstr "赋值"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:4
+msgid "There are multiple assignment operators:"
+msgstr "有多个赋值运算符："
+
+#: ../../SpinalHDL/Semantic/assignments.rst:10
+msgid "Symbol"
+msgstr "符号"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:11
+#: ../../SpinalHDL/Semantic/assignments.rst:82
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:12
+msgid "``:=``"
+msgstr "``:=``"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:13
+msgid "Standard assignment, equivalent to ``<=`` in VHDL/Verilog."
+msgstr "标准赋值，相当于 VHDL/Verilog 中的``<=``。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:14
+msgid "``\\=``"
+msgstr "``\\=``"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:15
+msgid ""
+"Equivalent to ``:=`` in VHDL and ``=`` in Verilog. The value is updated "
+"instantly in-place. Only works with combinational signals, does not work "
+"with registers."
+msgstr "相当于 VHDL 中的 ``:=`` 和 Verilog 中的 "
+"``=``。该值会立即就地更新。仅适用于组合信号，不适用于寄存器。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:16
+msgid "``<>``"
+msgstr "``<>``"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:17
+msgid ""
+"Automatic connection between 2 signals or two bundles of the same type. "
+"Direction is inferred by using signal direction (in/out). (Similar behavior "
+"to ``:=``\\ )"
+msgstr "2 个信号或相同类型的两个信号线束之间的自动连接。通过使用信号定义（输入/输出）"
+"来推断方向。 （与 ``:=``\\ 类似的行为）"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:19
+msgid ""
+"When muxing (for instance using ``when``, see :doc:`when_switch`.), the last"
+" valid standard assignment ``:=`` wins. Else, assigning twice to the same "
+"assignee from the same scope results in an assignment overlap.  SpinalHDL "
+"will assume this is a unintentional design error by default and halt "
+"elaboration with error. For special use-cases assignment overlap can be "
+"programatically permitted on a case by case basis. (see :doc:`../Design "
+"errors/assignment_overlap`)."
+msgstr ""
+"当多路复用时（例如使用 ``when``，请参阅 :doc:`when_switch`。），"
+"最后一个有效的赋值 ``:=`` "
+"为准。否则，向同一范围内的同一信号赋值两次会导致重叠错误。 SpinalHDL 默认情况"
+"下会假设这是一个无意的设计错误，并因错误而停止实例细化。对于特殊用例，可以根"
+"据具体情况以编程方式允许重叠赋值。 （参见 :doc:`../Design errors/"
+"assignment_overlap`）。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:45
+msgid ""
+"It also supports Bundle assignment (convert all bit signals into a single "
+"bit-bus of suitable width of type Bits, to then use that wider form in an "
+"assignment expression).  Bundle multiple signals together using ``()`` "
+"(Scala Tuple syntax) on both the left hand side and right hand side of an "
+"assignment expression."
+msgstr ""
+"它还支持线束赋值（将所有位信号转换为适当位宽的 `Bits` "
+"类型的单位总线，然后在赋值表达式中使用更宽的形式）。"
+"在赋值表达式的左侧和右侧使用 ``()`` （Scala 元组语法）将多个信号捆绑在一起。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:62
+msgid ""
+"It is important to understand that in SpinalHDL, the nature of a signal "
+"(combinational/sequential) is defined in its declaration, not by the way it "
+"is assigned. All datatype instances will define a combinational signal, "
+"while a datatype instance wrapped with ``Reg(...)`` will define a sequential"
+" (registered) signal."
+msgstr ""
+"重要的是要理解，在 SpinalHDL 中，信号的性质（组合/时序）是在其声明中定义的，"
+"而不是通过赋值的方式定义的。所有数据类型实例都将定义一个组合信号，而用 "
+"``Reg(...)`` 包装的实例将定义为一个时序信号（寄存器）。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:73
+msgid "Width checking"
+msgstr "位宽检查"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:75
+msgid ""
+"SpinalHDL checks that the bit count of the left side and the right side of "
+"an assignment matches. There are multiple ways to adapt the width of a given"
+" BitVector (``Bits``, ``UInt``, ``SInt``):"
+msgstr ""
+"SpinalHDL 检查赋值左侧和右侧的位数是否匹配。有多种方法可以改变给定 BitVector "
+"（``Bits``, ``UInt``, ``SInt``）的位宽："
+
+#: ../../SpinalHDL/Semantic/assignments.rst:81
+msgid "Resizing techniques"
+msgstr "调整位宽的技术"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:83
+msgid "x := y.resized"
+msgstr "x := y.resized"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:84
+msgid "Assign x with a resized copy of y, size inferred from x."
+msgstr "将 y 改变位宽后的副本分配给 x，其位宽是从 x 推断出来的。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:85
+msgid "x := y.resize(newWidth)"
+msgstr "x := y.resize(newWidth)"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:86
+msgid "Assign x with a resized copy of y :code:`newWidth` bits wide."
+msgstr "为 x 赋值一个 y 变为 newWidth 位宽后的副本。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:87
+msgid "x := y.resizeLeft(newWidth)"
+msgstr "x := y.resizeLeft(newWidth)"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:88
+msgid ""
+"Assign x with a resized copy of y :code:`newWidth` bits wide. Pads at the "
+"LSB if needed."
+msgstr "对 x 赋值 y 变为 newWidth 位宽后的副本。如果需要，可在 LSB 处进行填充。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:91
+msgid ""
+"All resize methods may cause the resulting width to be wider or narrower "
+"than the original width of :code:`y`. When widening occurs the extra bits "
+"are padded with zeros."
+msgstr "所有改变位宽方法都可能导致生成的位宽比 y "
+"的原始位宽更宽或更窄。当发生加宽时，额外的位将用零填充。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:95
+msgid ""
+"The inferred conversion with ``x.resized`` is based on the target width on "
+"the left hand side of the assignment expression being resolved and obeys the"
+" same semantics as ``y.resize(someWidth)``. The expression ``x := "
+"y.resized`` is equivalent to ``x := y.resize(x.getBitsWidth bits)``."
+msgstr ""
+"``x.resized`` 根据赋值表达式左侧的目标位宽推断转换方法，并遵循与 ``y."
+"resize(someWidth)`` 相同的语义。表达式 ``x := y.resized`` 相当于 ``x := y."
+"resize(x.getBitsWidth bits)``。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:99
+msgid ""
+"While the example code snippets show the use of an assignment statement, the"
+" resize family of methods can be chained like any ordinary Scala method."
+msgstr "虽然示例代码片段显示了赋值语句的使用方法，但 resize 系列方法可以像任何普通 "
+"Scala 方法一样进行级联。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:102
+msgid "There is one case where Spinal automatically resizes a value:"
+msgstr "在一种情况下，Spinal 会自动调整位宽的大小："
+
+#: ../../SpinalHDL/Semantic/assignments.rst:109
+msgid ""
+"Because ``U(3)`` is a \"weak\" bit count inferred signal, SpinalHDL widens "
+"it automatically. This can be considered to be functionally equivalent to "
+"``U(3, 2 bits).resized`` However rest reassured SpinalHDL will do the "
+"correct thing and continue to flag an error if the scenario would require "
+"narrowing. An error is reported if the literal required 9 bits (e.g. "
+"``U(0x100)``) when trying to assign into ``myUIntOf_8bits``."
+msgstr ""
+"因为 ``U(3)`` 是一个“弱”位计数推断信号，SpinalHDL 会自动加宽它。"
+"这可以被认为在功能上等同于 ``U(3, 2 bits).resized`` "
+"，但是请放心，如果场景需要缩小范围，SpinalHDL 将做正确的事情并报告错误。"
+"当尝试赋值 ``myUIntOf_8bits``时，如果字面量需要 9 位（例如 "
+"``U(0x100)``），则会报告错误。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:117
+msgid "Combinatorial loops"
+msgstr "组合逻辑环(Combinatorial loops)"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:119
+msgid ""
+"SpinalHDL checks that there are no combinatorial loops (latches) in your "
+"design. If one is detected, it raises an error and SpinalHDL will print the "
+"path of the loop."
+msgstr "SpinalHDL "
+"检查您的设计中是否存在组合逻辑环（锁存器）。如果检测到，会引发错误，并且 "
+"SpinalHDL 将打印造成循环的路径。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:123
+msgid "CombInit"
+msgstr "CombInit"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:125
+msgid ""
+"``CombInit`` can be used to copy a signal and its current combinatorial "
+"assignments. The main use-case is to be able to overwrite the copied later, "
+"without impacting the original signal."
+msgstr "``CombInit`` 可用于复制信号及其当前的组合逻辑赋值。主要用例是能够稍后覆盖复制"
+"后信号，而不影响原始信号。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:149
+msgid ""
+"If we look at the resulting Verilog, ``b`` is not present. Since it is a "
+"copy of ``a`` by reference, these variables designate the same Verilog wire."
+msgstr ""
+"如果我们查看生成的 Verilog，会发现``b`` 不存在。由于它是引用的 ``a`` 的副本，"
+"因此这些变量指代相同的 Verilog 信号。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:168
+msgid ""
+"``CombInit`` is particularly helpful in helper functions to ensure that the "
+"returned value is not referencing an input."
+msgstr "``CombInit`` 在辅助函数中特别有用，可确保返回值不引用输入。"
+
+#: ../../SpinalHDL/Semantic/assignments.rst:181
+msgid ""
+"Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` "
+"and ``a2`` reference the same signal and the zero assignment is also applied"
+" to ``a1``. With ``CombInit`` we have a coherent behaviour whatever the "
+"``c`` value."
+msgstr ""
+"没有 ``CombInit`` 的话，如果 ``c`` == false（而不是 ``c`` == true），``a1`` "
+"和 ``a2`` 会引用相同的信号，并且 ``a1`` 被赋值为零。有了 ``CombInit`` ，无论 "
+"``c`` 的值是多少，我们都有一致的行为（CombInit创建新的信号）。"
+
+#~ msgid ""
+#~ "It also supports Bundle assignment. Bundle multiple signals together using "
+#~ "``()`` to assign and assign to"
+#~ msgstr "它还支持 Bundle 分配。使用“()”将多个信号捆绑在一起进行分配和分配"
+
+#~ msgid "Assignment"
+#~ msgstr "任务"
+
+#~ msgid "Problem"
+#~ msgstr "问题"
+
+#~ msgid "SpinalHDL action"
+#~ msgstr "脊髓HDL作用"
+
+#~ msgid "myUIntOf_8bit := U(3)"
+#~ msgstr "myUIntOf_8bit := U(3)"
+
+#~ msgid ""
+#~ "U(3) creates an UInt of 2 bits, which doesn't match the left side (8 bits)"
+#~ msgstr "U(3) 创建一个 2 位的 UInt，与左侧（8 位）不匹配"
+
+#~ msgid ""
+#~ "Because U(3) is a \"weak\" bit count inferred signal, SpinalHDL resizes it "
+#~ "automatically"
+#~ msgstr "由于 U(3) 是“弱”位计数推断信号，SpinalHDL 会自动调整其大小"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/index.po
new file mode 100644
index 00000000000..2658daa6995
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 09:29+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsemanticindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Semantic/index.rst:5
+msgid "Semantic"
+msgstr "语义"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po
new file mode 100644
index 00000000000..2d9bfb69693
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po
@@ -0,0 +1,245 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsemanticrules/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Semantic/rules.rst:2
+msgid "Rules"
+msgstr "规则"
+
+#: ../../SpinalHDL/Semantic/rules.rst:4
+msgid ""
+"The semantics behind SpinalHDL are important to learn, so that you "
+"understand what is really happening behind the scenes, and how to control "
+"it."
+msgstr "SpinalHDL "
+"背后的语义很重要，这样您就可以了解幕后真正发生的事情以及如何控制它。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:6
+msgid "These semantics are defined by multiple rules:"
+msgstr "这些语义由多个规则定义："
+
+#: ../../SpinalHDL/Semantic/rules.rst:8
+msgid ""
+"Signals and registers are operating concurrently with each other (parallel "
+"behavioral, as in VHDL and Verilog)"
+msgstr "信号和寄存器彼此同时运行（并行行为，如 VHDL 和 Verilog）"
+
+#: ../../SpinalHDL/Semantic/rules.rst:9
+msgid ""
+"An assignment to a combinational signal is like expressing a rule which is "
+"always true"
+msgstr "对组合信号的赋值就像表达一条始终为真的规则"
+
+#: ../../SpinalHDL/Semantic/rules.rst:10
+msgid ""
+"An assignment to a register is like expressing a rule which is applied on "
+"each cycle of its clock domain"
+msgstr "对寄存器的赋值就像表达一条应用于其时钟域的每个周期的规则"
+
+#: ../../SpinalHDL/Semantic/rules.rst:11
+msgid "For each signal, the last valid assignment wins"
+msgstr "对于每个信号，最后一个赋值生效"
+
+#: ../../SpinalHDL/Semantic/rules.rst:12
+msgid ""
+"Each signal and register can be manipulated as an object during hardware "
+"elaboration in a `OOP <https://en.wikipedia.org/wiki/Object-"
+"oriented_programming>`_ manner"
+msgstr ""
+"每个信号和寄存器都可以作为对象在硬件实例细化期间进行操作，用 `OOP <https://en"
+".wikipedia.org/wiki/Object-oriented_programming>`_ 的思想"
+
+#: ../../SpinalHDL/Semantic/rules.rst:15
+msgid "Concurrency"
+msgstr "并发"
+
+#: ../../SpinalHDL/Semantic/rules.rst:17
+msgid ""
+"The order in which you assign each combinational or registered signal has no"
+" behavioral impact."
+msgstr "您对每个组合或时序信号的赋值顺序不会对行为产生影响。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:19
+msgid "For example, both of the following pieces of code are equivalent:"
+msgstr "例如，以下两段代码是等效的："
+
+#: ../../SpinalHDL/Semantic/rules.rst:28
+msgid "This is equivalent to:"
+msgstr "这相当于："
+
+#: ../../SpinalHDL/Semantic/rules.rst:37
+msgid ""
+"More generally, when you use the ``:=`` assignment operator, it's like "
+"specifying an additional new rule for the left side signal/register."
+msgstr "更一般地说，当您使用 ``:=`` "
+"赋值运算符时，就像为左侧信号/寄存器指定一个附加的新规则。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:40
+msgid "Last valid assignment wins"
+msgstr "最后有效赋值生效"
+
+#: ../../SpinalHDL/Semantic/rules.rst:42
+msgid ""
+"If a combinational signal or register is assigned multiple times through the"
+" use of the SpinalHDL ``:=`` operator, the last assignment that may execute "
+"wins (and so gets to set the value as a result for this state)."
+msgstr ""
+"如果通过使用 SpinalHDL ``:=`` 运算符对组合信号或寄存器进行多次分配，则可能执"
+"行的最后一次赋值生效（因此可以将值设置为该状态的结果）。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:46
+msgid ""
+"It could be said that top to bottom evaluation occurs based on the state "
+"that exists at that time.  If your upstream signal inputs are driven from "
+"registers and so have synchronous behaviour, then it could be said that at "
+"each clock cycle the assignments are re-evaluated based on the new state at "
+"the time."
+msgstr ""
+"可以说，自上而下的评估计算是根据当时的状态进行的。如果您的上游信号输入是从寄"
+"存器驱动的，因此具有同步行为，那么可以说，在每个时钟周期，都会根据当时的新状"
+"态重新计算、赋值。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:51
+msgid ""
+"Some reasons why an assignment statement may not get to execute in hardware "
+"this clock cycle, maybe due to it being wrapped in a ``when(cond)`` clause."
+msgstr "在硬件中，赋值语句可能无法在本时钟周期执行的一些原因，可能是由于它被包装在 "
+"``when(cond)`` 子句中。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:54
+msgid ""
+"Another reason maybe that the SpinalHDL code never made it through "
+"elaboration because the feature was paramaterized and disabled during HDL "
+"code-generation, see ``paramIsFalse`` use below."
+msgstr ""
+"另一个原因，可能是 SpinalHDL 代码从未通过实力细化，因为该功能在 HDL "
+"代码生成期间被参数化并禁用，请参阅下面 ``paramIsFalse`` 的案例。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:58
+msgid "As an example:"
+msgstr "举个例子："
+
+#: ../../SpinalHDL/Semantic/rules.rst:78
+msgid "This will produce the following truth table:"
+msgstr "这将产生以下真值表："
+
+#: ../../SpinalHDL/Semantic/rules.rst:83
+msgid "x"
+msgstr "x"
+
+#: ../../SpinalHDL/Semantic/rules.rst:84
+msgid "y"
+msgstr "y"
+
+#: ../../SpinalHDL/Semantic/rules.rst:85
+msgid "=>"
+msgstr "=>"
+
+#: ../../SpinalHDL/Semantic/rules.rst:86
+msgid "result"
+msgstr "结果"
+
+#: ../../SpinalHDL/Semantic/rules.rst:87 ../../SpinalHDL/Semantic/rules.rst:88
+#: ../../SpinalHDL/Semantic/rules.rst:91 ../../SpinalHDL/Semantic/rules.rst:96
+msgid "False"
+msgstr "False"
+
+#: ../../SpinalHDL/Semantic/rules.rst:90 ../../SpinalHDL/Semantic/rules.rst:94
+msgid "1"
+msgstr "1"
+
+#: ../../SpinalHDL/Semantic/rules.rst:92 ../../SpinalHDL/Semantic/rules.rst:95
+#: ../../SpinalHDL/Semantic/rules.rst:99
+#: ../../SpinalHDL/Semantic/rules.rst:100
+msgid "True"
+msgstr "True"
+
+#: ../../SpinalHDL/Semantic/rules.rst:98
+msgid "2"
+msgstr "2"
+
+#: ../../SpinalHDL/Semantic/rules.rst:102
+msgid "3"
+msgstr "3"
+
+#: ../../SpinalHDL/Semantic/rules.rst:106
+msgid ""
+"Signal and register interactions with Scala (OOP reference + Functions)"
+msgstr "信号和寄存器与 Scala 语言的协作（OOP 引用 + 函数）"
+
+#: ../../SpinalHDL/Semantic/rules.rst:108
+msgid ""
+"In SpinalHDL, each hardware element is modeled by a class instance. This "
+"means you can manipulate instances by using their references, such as "
+"passing them as arguments to a function."
+msgstr "在 SpinalHDL 中，每个硬件元素都由一个类实例建模。这意味着您可以通过使用实例的"
+"引用来操作实例，例如将它们作为参数传递给函数。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:110
+msgid ""
+"As an example, the following code implements a register which is incremented"
+" when ``inc`` is True and cleared when ``clear`` is True (``clear`` has "
+"priority over ``inc``) :"
+msgstr ""
+"作为示例，以下代码实现了一个寄存器，当 ``inc`` 为 True 时递增，当 ``clear`` "
+"为 True 时清零（``clear`` 优先于 ``inc``）："
+
+#: ../../SpinalHDL/Semantic/rules.rst:124
+msgid ""
+"You can implement exactly the same functionality by mixing the previous "
+"example with a function that assigns to ``counter``:"
+msgstr "您可以通过将前面的示例与赋值给 ``counter``的函数混合来实现完全相同的功能："
+
+#: ../../SpinalHDL/Semantic/rules.rst:142
+msgid "You can also integrate the conditional check inside the function:"
+msgstr "您还可以将条件检查集成到函数内："
+
+#: ../../SpinalHDL/Semantic/rules.rst:158
+msgid "And also specify what should be assigned to the function:"
+msgstr "并指定函数应实现的赋值："
+
+#: ../../SpinalHDL/Semantic/rules.rst:174
+msgid ""
+"All of the previous examples are strictly equivalent both in their generated"
+" RTL and also in the SpinalHDL compiler's perspective. This is because "
+"SpinalHDL only cares about the Scala runtime and the objects instantiated "
+"there, it doesn't care about the Scala syntax itself."
+msgstr ""
+"前面的所有示例在生成的 RTL 中，从 SpinalHDL 编译器的角度来看都是严格等效的。"
+"这是因为 SpinalHDL 只关心 Scala 运行时实例化的对象，它不关心 Scala 语法本身。"
+
+#: ../../SpinalHDL/Semantic/rules.rst:177
+msgid ""
+"In other words, from a generated RTL generation / SpinalHDL perspective, "
+"when you use functions in Scala which generate hardware, it is like the "
+"function was inlined. This is also true case for Scala loops, as they will "
+"appear in unrolled form in the generated RTL."
+msgstr ""
+"换句话说，从生成的 RTL 生成/SpinalHDL 的角度来看，当您调用 Scala "
+"中生成硬件的函数时，就像该函数被内联了一样。 Scala 循环也是如此，"
+"因为它们将以展开的形式出现在生成的 RTL 中。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
+
+#~ msgid ""
+#~ "If a combinational signal or register is assigned multiple times, the last "
+#~ "valid one wins."
+#~ msgstr "如果组合信号或寄存器被分配多次，则最后一个有效的获胜。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po
new file mode 100644
index 00000000000..a4679541bc6
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po
@@ -0,0 +1,222 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 09:29+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsemanticwhen_switch/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:2
+msgid "When/Switch/Mux"
+msgstr "When/Switch/Mux"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:5
+msgid "When"
+msgstr "When"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:7
+msgid ""
+"As in VHDL and Verilog, signals can be conditionally assigned when a "
+"specified condition is met:"
+msgstr "与 VHDL 和 Verilog 中一样，当满足指定条件时可以有条件地赋值信号："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:21
+msgid ""
+"If the keyword ``otherwise`` is on the same line as the closing bracket "
+"``}`` of the ``when`` condition, no dot is needed."
+msgstr "如果关键字 ``otherwise`` 与 ``when`` 条件的右括号 ``}`` "
+"在同一行，则不需要点。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:31
+msgid "But if ``.otherwise`` is on another line, a dot is **required**:"
+msgstr "但如果 ``.otherwise`` 在另一行，则**需要**一个点："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:43
+msgid "Switch"
+msgstr "Switch"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:45
+msgid ""
+"As in VHDL and Verilog, signals can be conditionally assigned when a signal "
+"has a defined value:"
+msgstr "与 VHDL 和 Verilog 中一样，当信号具有定义的值时，可以有条件地对信号赋值："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:61
+msgid ""
+"``is`` clauses can be factorized (logical OR) by separating them with a "
+"comma ``is(value1, value2)``."
+msgstr "``is`` 子句可以通过用逗号 ``is(value1, value2)`` 分隔来进行分解（逻辑 OR）。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:64
+#: ../../SpinalHDL/Semantic/when_switch.rst:186
+msgid "Example"
+msgstr "示例"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:86
+msgid "is equivalent to"
+msgstr "相当于"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:101
+msgid "Additional options"
+msgstr "其他选项"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:103
+msgid ""
+"By default, SpinalHDL will generate an \"UNREACHABLE DEFAULT STATEMENT\" "
+"error if a ``switch`` contains a ``default`` statement while all the "
+"possible logical values of the ``switch`` are already covered by the ``is`` "
+"statements. You can drop this error reporting by specifying `` "
+"switch(myValue, coverUnreachable = true) { ... }``."
+msgstr ""
+"默认情况下，如果 ``switch`` 包含 ``default`` 语句，而 ``switch`` "
+"的所有可能的逻辑值都已被是 ``is`` 语句“覆盖”，SpinalHDL 将生成“UNREACHABLE "
+"DEFAULT STATEMENT”错误。您可以通过指定 `` switch(myValue, coverUnreachable = "
+"true) { ... }`` 来删除此错误报告。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:117
+msgid ""
+"This check is done on the logical values, not on the physical values. For "
+"instance, if you have a SpinalEnum(A,B,C) encoded in a one-hot manner, "
+"SpinalHDL will only care about the A,B,C values (\"001\" \"010\" \"100\"). "
+"Physical values as \"000\" \"011\" \"101\" \"110\" \"111\" will not be taken"
+" in account."
+msgstr ""
+"此检查是针对逻辑值而不是物理值进行的。例如，如果您有一个以独热编码的 "
+"SpinalEnum(A,B,C)，SpinalHDL 将只关心 A,B,C 值 (\"001\" \"010\" \"100\""
+"）。物理值“000”“011”“101”“110”“111”将不被考虑。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:120
+msgid ""
+"By default, SpinalHDL will generate a \"DUPLICATED ELEMENTS IN SWITCH "
+"IS(...) STATEMENT\" error if a given ``is`` statement provides multiple "
+"times the same value. For instance ``is(42,42) { ... }`` You can drop this "
+"error reporting by specifying ``switch(myValue, strict = true){ ... }``. "
+"SpinalHDL will then take care of removing duplicated values."
+msgstr ""
+"默认情况下，如果给定的 ``is`` 语句多次提供相同的值，SpinalHDL 将生成 "
+"\"DUPLICATED ELEMENTS IN SWITCH IS(...) STATEMENT\" 错误。例如 ``is(42,42) { "
+"... }`` 您可以通过指定 ``switch(myValue, strict = true){ ... }`` "
+"来避免报告此错误。 SpinalHDL 然后将负责删除重复的值。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:133
+msgid "Local declaration"
+msgstr "本地声明"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:135
+msgid "It is possible to define new signals inside a when/switch statement:"
+msgstr "可以在 when/switch 语句中定义新信号："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:152
+msgid ""
+"SpinalHDL checks that signals defined inside a scope are only assigned "
+"inside that scope."
+msgstr "SpinalHDL 会检查范围内定义的信号是否仅在该范围内使用/赋值。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:155
+msgid "Mux"
+msgstr "Mux"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:157
+msgid ""
+"If you just need a ``Mux`` with a ``Bool`` selection signal, there are two "
+"equivalent syntaxes:"
+msgstr "如果您只需要一个带有 ``Bool`` 选择信号的 ``Mux`` ，则有两种等效的语法："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:163
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:164
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:165
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:166
+msgid "Mux(cond, whenTrue, whenFalse)"
+msgstr "Mux(cond, whenTrue, whenFalse)"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:167
+#: ../../SpinalHDL/Semantic/when_switch.rst:170
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:168
+#: ../../SpinalHDL/Semantic/when_switch.rst:171
+msgid "Return ``whenTrue`` when ``cond`` is True, ``whenFalse`` otherwise"
+msgstr "当 ``cond`` 为 True 时返回 ``whenTrue`` ，否则返回 ``whenFalse``"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:169
+msgid "cond ? whenTrue | whenFalse"
+msgstr "cond ? whenTrue | whenFalse"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:181
+msgid "Bitwise selection"
+msgstr "按位选择"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:183
+msgid "A bitwise selection looks like the VHDL ``when`` syntax."
+msgstr "按位选择看起来像 VHDL ``when`` 语法。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:198
+msgid ""
+"``mux`` checks that all possible values are covered to prevent generation of"
+" latches. If all possible values are covered, the default statement must not"
+" be added:"
+msgstr "``mux`` 检查所有可能的值是否都被覆盖以防止锁存器的生成。如果覆盖了所有可能的"
+"值，则不允许添加default语句："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:211
+msgid ""
+"``muxList(...)`` and ``muxListDc(...)`` are alternatives bitwise selectors "
+"that take a sequence of tuples or mappings as input."
+msgstr "``muxList(...)`` 和 ``muxListDc(...)`` "
+"是另一种按位选择器，它们采用元组或映射作为输入。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:213
+msgid ""
+"``muxList`` can be used as a direct replacement for ``mux``, providing a "
+"easier to use interface in code that generates the cases. It has the same "
+"checking behavior as ``mux`` does, requiring full coverage and prohibiting "
+"listing a default if it is not needed."
+msgstr ""
+"``muxList`` 可以用作 ``mux`` "
+"的直接替代品，在生成案例的代码中提供更易于使用的接口。它具有与 ``mux`` "
+"相同的检查行为，它要求完全覆盖并禁止在不需要时列出默认值。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:216
+msgid ""
+"``muxtListDc`` can be used if the uncovered values are not important, they "
+"can be left unassigned by using ``muxListDc``. This will add a default case "
+"if needed. This default case will generate X's during the simulation if ever"
+" encountered. ``muxListDc(...)`` is often a good alternative in generic "
+"code."
+msgstr ""
+"如果未覆盖的值不重要，则可以使用 ``muxtListDc`` ，可以使用 ``muxtListDc`` "
+"将它们保留为未分配状态。如果需要，这将添加默认情况。如果遇到这种默认情况，"
+"将在仿真过程中生成 `X`。``muxListDc(...)`` "
+"通常是一个很好的通用代码的替代方法。"
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:220
+msgid "Below is an example of dividing a ``Bits`` of 128 bits into 32 bits:"
+msgstr "下面是将 128 位的 ``Bits`` 划分为 32 位的示例："
+
+#: ../../SpinalHDL/Semantic/when_switch.rst:238
+msgid ""
+"Example for ``muxListDc`` selecting bits from a configurable width vector:"
+msgstr "下面是 ``muxListDc`` 的案例，从可配置位宽的向量中选择多个位："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/index.po
new file mode 100644
index 00000000000..08fc7e7fa9b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/index.po	
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsequential-logicindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/Sequential logic/index.rst:3
+msgid "Sequential logic"
+msgstr "时序逻辑"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po
new file mode 100644
index 00000000000..93b1d858824
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po	
@@ -0,0 +1,523 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsequential-logicmemory/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:2
+msgid "RAM/ROM Memory"
+msgstr "RAM/ROM存储器"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:4
+msgid ""
+"To create a memory in SpinalHDL, the ``Mem`` class should be used. It allows"
+" you to define a memory and add read and write ports to it."
+msgstr "要在 SpinalHDL 中创建内存，应使用 ``Mem`` "
+"类。它允许您定义内存并向其添加读写端口。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:7
+msgid "The following table shows how to instantiate a memory:"
+msgstr "下表显示了如何实例化存储器："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:13 logic/memory.rst:40
+#: logic/memory.rst:161
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:14 logic/memory.rst:41
+#: logic/memory.rst:140 logic/memory.rst:162 logic/memory.rst:227
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:15
+msgid "``Mem(type : Data, size : Int)``"
+msgstr "``Mem(type : Data, size : Int)``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:16
+msgid "Create a RAM"
+msgstr "创建随机访问存储器"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:17
+msgid "``Mem(type : Data, initialContent : Array[Data])``"
+msgstr "``Mem(type : Data, initialContent : Array[Data])``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:18
+msgid ""
+"Create a ROM. If your target is an FPGA, because the memory can be inferred "
+"as a block ram, you can still create write ports on it."
+msgstr "创建一个 ROM。如果您的目标是 FPGA，因为存储器可以推断为块 "
+"RAM，您仍然可以在其上创建写入端口。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:22
+msgid ""
+"If you want to define a ROM, elements of the ``initialContent`` array should"
+" only be literal values (no operator, no resize functions). There is an "
+"example :ref:`here <sinus_rom>`."
+msgstr ""
+"如果你想定义一个 ROM，``initialContent`` "
+"数组的元素应该只是字面量（无法做运算，无法改变位宽）。这里有一个例子 :ref:`"
+"here <sinus_rom>`。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:25
+msgid "To give a RAM initial values, you can also use the ``init`` function."
+msgstr "要给 RAM 初始值，您还可以使用 ``init`` 函数。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:28
+msgid ""
+"Write mask width is flexible, and subdivide the memory word in as many "
+"slices of equal width as the width of the mask. For instance if you have a "
+"32 bits memory word and provide a 4 bits mask then it will be a byte mask. "
+"If you provide a as many mask bits than you have word bits, then it is a bit"
+" mask."
+msgstr ""
+"掩码位宽是可以灵活设定的，您可以根据掩码的宽度将存储器分成位宽相同的多个片段"
+"。例如，如果您有一个32位内存字，并提供一个4位掩码，那么它将是一个字节掩码。如"
+"果您提供的掩码位数与存储器一个字的位数相同，那么它将是一个位掩码。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:32
+msgid ""
+"Manipulation of ``Mem`` is possible in simulation, see section :ref:`Load "
+"and Store of Memory in Simulation <simulation_of_memory>`."
+msgstr "在仿真时可以对 ``Mem`` 进行操作，请参阅 :ref:`仿真中加载和存储存储器 "
+"<simulation_of_memory>` 部分。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:34
+msgid "The following table show how to add access ports on a memory :"
+msgstr "下表显示了如何在存储器上添加访问端口："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:42
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:43
+msgid "mem(address) := data"
+msgstr "mem(address) := data"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:44
+msgid "Synchronous write"
+msgstr "同步写入"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:46
+msgid "mem(x)"
+msgstr "mem(x)"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:47
+msgid "Asynchronous read"
+msgstr "异步读取"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:48 logic/memory.rst:63
+#: logic/memory.rst:71 logic/memory.rst:84
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.write("
+msgstr "mem.write("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "address"
+msgstr "address"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "data"
+msgstr "data"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "[enable]"
+msgstr "[enable]"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "[mask]"
+msgstr "[mask]"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid ")"
+msgstr ")"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Synchronous write with an optional mask."
+msgstr "使用可选掩码进行同步写入。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid ""
+"If no enable is specified, it's automatically inferred from the conditional "
+"scope where this function is called"
+msgstr "如果未指定使能（enable）条件，则会自动从调用此函数的条件范围（如when语句等）"
+"中推断出条件"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readAsync("
+msgstr "mem.readAsync("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "[readUnderWrite]"
+msgstr "[readUnderWrite]"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:62
+msgid "Asynchronous read with an optional read-under-write policy"
+msgstr "异步读取，具有可选的写入时读取（read-under-write）策略"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readSync("
+msgstr "mem.readSync("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "[clockCrossing]"
+msgstr "[clockCrossing]"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:70
+msgid ""
+"Synchronous read with an optional enable, read-under-write policy, and "
+"``clockCrossing`` mode"
+msgstr "同步读取，具有可选的使能信号、写入间读取策略、跨时钟域（``clockCrossing``）模"
+"式。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readWriteSync("
+msgstr "mem.readWriteSync("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "enable"
+msgstr "enable"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "write"
+msgstr "write"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Infer a read/write port."
+msgstr "推断读/写端口。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "``data`` is written when ``enable && write``."
+msgstr "当 ``enable && write`` 满足时写入 ``data``。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Return the read data, the read occurs when ``enable`` is true"
+msgstr "返回读取的数据，当 ``enable`` 为true时读取"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:88
+msgid ""
+"If for some reason you need a specific memory port which is not implemented "
+"in Spinal, you can always abstract over your memory by specifying a BlackBox"
+" for it."
+msgstr "如果由于某种原因您需要一个未在 Spinal 中实现的特定存储器端口，"
+"您始终可以通过为其指定 BlackBox 来抽象您的存储器。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:91
+msgid ""
+"Memory ports in SpinalHDL are not inferred, but are explicitly defined. You "
+"should not use coding templates like in VHDL/Verilog to help the synthesis "
+"tool to infer memory."
+msgstr "SpinalHDL 中的存储器端口不是推断的，而是明确定义的。您不应使用 VHDL/Verilog "
+"等编码模板来帮助综合工具推断存储器。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:93
+msgid "Here is a example which infers a simple dual port ram (32 bits * 256):"
+msgstr "下面是一个推断简单双端口 RAM（32 位 * 256）的示例："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:111
+msgid "Synchronous enable quirk"
+msgstr "同步使能注意事项"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:113
+msgid ""
+"When enable signals are used in a block guarded by a conditional block like "
+"`when`, only the enable signal will be generated as the access condition: "
+"the `when` condition is ignored."
+msgstr "当使能信号用于由 `when` "
+"等条件块保护的块中时，只会生成用使能信号作为访问条件的电路，也就是说 `when` "
+"条件将被忽略。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:123
+msgid ""
+"In the example above the condition `cond` will not be elaborated. Prefer to "
+"include the condition `cond` in the enable signal directly as below."
+msgstr "上面的例子中条件 `cond` 就不详细说明了。最好直接在使能信号中包含条件 "
+"`cond`，如下所示。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:131
+msgid "Read-under-write policy"
+msgstr "写入时读取策略"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:133
+msgid ""
+"This policy specifies how a read is affected when a write occurs in the same"
+" cycle to the same address."
+msgstr "此策略指定在同一周期内对同一地址发生写入时，读取的值将受到怎样的影响。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:139 logic/memory.rst:226
+msgid "Kinds"
+msgstr "种类"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:141
+msgid "``dontCare``"
+msgstr "``dontCare``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:142
+msgid "Don't care about the read value when the case occurs"
+msgstr "发生这种情况时不用关心读取的值"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:143
+msgid "``readFirst``"
+msgstr "``readFirst``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:144
+msgid "The read will get the old value (before the write)"
+msgstr "读取操作将得到写入之前的值"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:145
+msgid "``writeFirst``"
+msgstr "``writeFirst``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:146
+msgid "The read will get the new value (provided by the write)"
+msgstr "读取操作将得到由写入提供的值"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:150
+msgid ""
+"The generated VHDL/Verilog is always in the ``readFirst`` mode, which is "
+"compatible with ``dontCare`` but not with ``writeFirst``. To generate a "
+"design that contains this kind of feature, you need to enable "
+":ref:`automatic memory blackboxing <automatic_memory_blackboxing>`."
+msgstr ""
+"生成的 VHDL/Verilog 始终处于 ``readFirst`` 模式，该模式与 ``dontCare`` 兼容，"
+"但与 ``writeFirst`` 不兼容。要生成包含此类功能的设计，您需要使能 :ref:`"
+"自动存储器黑盒 <automatic_memory_blackboxing>`。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:153
+msgid "Mixed-width ram"
+msgstr "混合位宽存储器"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:155
+msgid ""
+"You can specify ports that access the memory with a width that is a power of"
+" two fraction of the memory width using these functions:"
+msgstr "您可以使用以下函数指定访问存储器的端口，其位宽为二的幂次："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.writeMixedWidth("
+msgstr "mem.writeMixedWidth("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:168
+msgid "Similar to ``mem.write``"
+msgstr "类似于 ``mem.write``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readAsyncMixedWidth("
+msgstr "mem.readAsyncMixedWidth("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:174
+msgid ""
+"Similar to ``mem.readAsync``, but in place of returning the read value, it "
+"drives the signal/object given as the ``data`` argument"
+msgstr "类似于 ``mem.readAsync``, 会立即返回值，它驱动以 ``data`` "
+"参数的形式传入的信号/对象"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readSyncMixedWidth("
+msgstr "mem.readSyncMixedWidth("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:182
+msgid ""
+"Similar to ``mem.readSync``, but in place of returning the read value, it "
+"drives the signal/object given as the ``data`` argument"
+msgstr "与 ``mem.readSync`` 类似，但它不是返回读取值，而是驱动 ``data`` "
+"参数给出的信号/对象"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "mem.readWriteSyncMixedWidth("
+msgstr "mem.readWriteSyncMixedWidth("
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:192
+msgid "Equivalent to ``mem.readWriteSync``"
+msgstr "相当于 ``mem.readWriteSync``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:196
+msgid ""
+"As for read-under-write policy, to use this feature you need to enable "
+":ref:`automatic memory blackboxing <automatic_memory_blackboxing>`, because "
+"there is no universal VHDL/Verilog language template to infer mixed-width "
+"ram."
+msgstr ""
+"至于写入时读取策略，要使用此功能，您需要启用 :ref:`自动内存黑盒 "
+"<automatic_memory_blackboxing>`，因为没有通用的 VHDL/Verilog "
+"语言模板来推断混合位宽存储器。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:201
+msgid "Automatic blackboxing"
+msgstr "自动黑盒化"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:203
+msgid ""
+"Because it's impossible to infer all ram kinds by using regular "
+"VHDL/Verilog, SpinalHDL integrates an optional automatic blackboxing system."
+" This system looks at all memories present in your RTL netlist and replaces "
+"them with blackboxes. Then the generated code will rely on third party IP to"
+" provide the memory features, such as the read-during-write policy and "
+"mixed-width ports."
+msgstr ""
+"由于使用常规 VHDL/Verilog 不可能推断所有 ram 类型，因此 SpinalHDL "
+"集成了可选的自动黑盒系统。该系统会查看 RTL 网表中存在的所有存储器，并用一个黑"
+"盒替换它们。然后生成的代码将依赖第三方IP来提供内存功能，例如写入时读取策略和"
+"混合位宽端口。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:205
+msgid ""
+"Here is an example of how to enable blackboxing of memories by default:"
+msgstr "这是一个如何缺省使能黑盒化存储器的例子："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:215
+msgid ""
+"If the standard blackboxing tools don't do enough for your design, do not "
+"hesitate to create a `Github issue "
+"<https://github.com/SpinalHDL/SpinalHDL/issues>`_. There is also a way to "
+"create your own blackboxing tool."
+msgstr ""
+"如果标准黑盒工具不足以满足您的设计需求，请毫不犹豫地创建 `Github工单 "
+"<https://github.com/SpinalHDL/SpinalHDL/"
+"issues>`_。还有一种方法，可以创建您自己的黑盒工具。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:218
+msgid "Blackboxing policy"
+msgstr "黑盒策略"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:220
+msgid ""
+"There are multiple policies that you can use to select which memory you want"
+" to blackbox and also what to do when the blackboxing is not feasible:"
+msgstr "您可以使用多种策略来选择要黑盒的内存以及黑盒不可行时要执行的操作："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:228
+msgid "``blackboxAll``"
+msgstr "``blackboxAll``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Blackbox all memory."
+msgstr "黑盒化所有存储器。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Throw an error on unblackboxable memory"
+msgstr "对不可黑盒存储器抛出错误"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:231
+msgid "``blackboxAllWhatsYouCan``"
+msgstr "``blackboxAllWhatsYouCan``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:232
+msgid "Blackbox all memory that is blackboxable"
+msgstr "黑盒所有可黑盒的存储器"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:233
+msgid "``blackboxRequestedAndUninferable``"
+msgstr "``blackboxRequestedAndUninferable``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid ""
+"Blackbox memory specified by the user and memory that is known to be "
+"uninferable (mixed-width, ...)."
+msgstr "用户指定的黑盒存储器和已知不可推断的存储器（混合位宽，...）。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:236
+msgid "``blackboxOnlyIfRequested``"
+msgstr "``blackboxOnlyIfRequested``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst
+msgid "Blackbox memory specified by the user"
+msgstr "用户指定的黑盒存储器"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:241
+msgid ""
+"To explicitly set a memory to be blackboxed, you can use its "
+"``generateAsBlackBox`` function."
+msgstr "要显式地将存储器设置为黑盒，您可以使用其 ``generateAsBlackBox`` 函数。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:248
+msgid ""
+"You can also define your own blackboxing policy by extending the "
+"``MemBlackboxingPolicy`` class."
+msgstr "你可以通过继承 ``MemBlackboxingPolicy`` 类定义你自己的黑盒化策略。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:251
+msgid "Standard memory blackboxes"
+msgstr "标准存储器黑盒"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:253
+msgid ""
+"Shown below are the VHDL definitions of the standard blackboxes used in "
+"SpinalHDL:"
+msgstr "下面显示的是 SpinalHDL 中使用的标准黑盒的 VHDL 定义："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:365
+msgid ""
+"As you can see, blackboxes have a technology parameter. To set it, you can "
+"use the ``setTechnology`` function on the corresponding memory. There are "
+"currently 4 kinds of technologies possible:"
+msgstr "正如你所看到的，黑盒有一个技术参数。要设置它，您可以在相应的内存上使用 "
+"``setTechnology`` 函数。目前有4种可能的技术："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:368
+msgid "``auto``"
+msgstr "``auto``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:369
+msgid "``ramBlock``"
+msgstr "``ramBlock``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:370
+msgid "``distributedLut``"
+msgstr "``distributedLut``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:371
+msgid "``registerFile``"
+msgstr "``registerFile``"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:373
+msgid ""
+"Blackboxing can insert HDL attributes if ``SpinalConfig#setDevice(Device)`` "
+"has been configured for your device-vendor."
+msgstr "如果已为您的设备供应商配置了 ``SpinalConfig#setDevice(Device)`` ，"
+"则黑盒化可以插入 HDL 属性。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:376
+msgid "The resulting HDL attributes might look like:"
+msgstr "生成的 HDL 属性可能如下所示："
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:383
+msgid ""
+"SpinalHDL tries to support many common memory types provided by well known "
+"vendors and devices, however this is an ever moving landscape and project "
+"requirements can be very specific in this area."
+msgstr "SpinalHDL 尝试支持知名供应商和设备提供的许多常见存储器类型，但是这是一个不断"
+"变化的领域，并且该领域的项目要求可能非常具体。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:387
+msgid ""
+"If this is important to your design flow then check the output HDL for the "
+"expected attributes/generic insertion, while consulting your vendor's "
+"platform documentation."
+msgstr "如果这对您的设计流程很重要，请检查输出 HDL "
+"是否有预期的属性/代码，同时查阅供应商的平台文档。"
+
+#: ../../SpinalHDL/Sequential logic/memory.rst:391
+msgid ""
+"HDL attributes can also be added manually using the `addAttribute()` "
+":ref:`addAttribute <vhdl-and-verilog-attributes>` mechanism."
+msgstr ""
+"HDL 属性也可以使用 `addAttribute()` :ref:`addAttribute <vhdl-and-verilog-"
+"attributes>` 机制手动添加。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po
new file mode 100644
index 00000000000..931e529329d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po	
@@ -0,0 +1,244 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsequential-logicregisters/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:4
+msgid "Registers"
+msgstr "寄存器"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:6
+msgid ""
+"Creating registers in SpinalHDL is very different than in VHDL or Verilog."
+msgstr "在 SpinalHDL 中创建寄存器与在 VHDL 或 Verilog 中创建寄存器有很大不同。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:8
+msgid ""
+"In Spinal, there are no process/always blocks. Registers are explicitly "
+"defined at declaration. This difference from traditional event-driven HDL "
+"has a big impact:"
+msgstr "在 Spinal 中，没有 process/always 块。寄存器在声明时明确定义。"
+"这种与传统的事件驱动 HDL 的区别具有很大的影响："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:11
+msgid ""
+"You can assign registers and wires in the same scope, meaning the code "
+"doesn't need to be split between process/always blocks"
+msgstr "您可以在同一范围内赋值寄存器和连线，这意味着代码不需要在 process/always "
+"块之间拆分"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:12
+msgid "It make things much more flexible (see :ref:`Functions <function>`)"
+msgstr "它使事情变得更加灵活（参见 :ref:`Functions <function>`）"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:14
+msgid ""
+"Clocks and resets are handled separately, see the :ref:`Clock domain "
+"<clock_domain>` chapter for details."
+msgstr "时钟和复位是分开处理的，有关详细信息，请参阅 `时钟域 <clock_domain>` 章节。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:17
+msgid "Instantiation"
+msgstr "实例化"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:19
+msgid "There are 4 ways to instantiate a register:"
+msgstr "实例化寄存器有4种方法："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:25
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:26
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:27
+msgid "``Reg(type : Data)``"
+msgstr "``Reg(type : Data)``"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:28
+msgid "Register of the given type"
+msgstr "创建给定类型的寄存器"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:29
+msgid "``RegInit(resetValue : Data)``"
+msgstr "``RegInit(resetValue : Data)``"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:30
+msgid "Register loaded with the given ``resetValue`` when a reset occurs"
+msgstr "当发生复位时，为寄存器加载给定的 ``resetValue``"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:31
+msgid "``RegNext(nextValue : Data)``"
+msgstr "``RegNext(nextValue : Data)``"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:32
+msgid "Register that samples the given ``nextValue`` each cycle"
+msgstr "创建寄存器，且每个周期对给定的 ``nextValue`` 进行采样"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:33
+msgid "``RegNextWhen(nextValue : Data, cond : Bool)``"
+msgstr "``RegNextWhen(nextValue : Data, cond : Bool)``"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:34
+msgid "Register that samples the given ``nextValue`` when a condition occurs"
+msgstr "创建寄存器，当条件发生时对 ``nextValue`` 进行采样"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:36
+msgid "Here is an example declaring some registers:"
+msgstr "这是声明一些寄存器的示例："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:56
+msgid "The code above will infer the following logic:"
+msgstr "上面的代码将推断出以下逻辑："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:62
+msgid ""
+"The ``reg3`` example above shows how you can assign the value of a "
+"``RegInit`` register. It's possible to use the same syntax to assign to the "
+"other register types as well (``Reg``, ``RegNext``, ``RegNextWhen``). Just "
+"like in combinational assignments, the rule is 'Last assignment wins', but "
+"if no assignment is done, the register keeps its value. If the Reg is "
+"declared in a design and does not have suitable assignment and consumption "
+"it is likely to be pruned (removed from design) at some point by EDA flows "
+"after being deemed unnecessary."
+msgstr ""
+"上面 ``reg3`` 示例显示了如何为 ``RegInit`` 创建寄存器赋值。也可以使用相同的语"
+"法赋值其他寄存器类型（“Reg”、“RegNext”、“RegNextWhen”）。就像组合赋值一样，规"
+"则是“最后一个赋值生效”，但如果没有完成赋值，寄存器将保留其值。"
+"如果在设计中声明 Reg 并且没有适当地赋值和使用， EDA "
+"流程中的工具会在它认为该寄存器不必要时裁剪寄存器（从设计中删除）。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:70
+msgid ""
+"Also, ``RegNext`` is an abstraction which is built over the ``Reg`` syntax. "
+"The two following sequences of code are strictly equivalent:"
+msgstr "另外，``RegNext`` 是一个基于 ``Reg`` "
+"语法构建的抽象。下面两个代码序列严格等效："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:84
+msgid ""
+"It is possible to have multiple options at the same time in other ways and "
+"so slightly more advanced compositions built on top of the basic understand "
+"of the above:"
+msgstr "可以通过其他方式同时拥有多个选项，因此可在上述基本理解的基础上构建稍微更高级"
+"的组合："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:125
+msgid "Reset value"
+msgstr "复位值"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:127
+msgid ""
+"In addition to the ``RegInit(value : Data)`` syntax which directly creates "
+"the register with a reset value, you can also set the reset value by calling"
+" the ``init(value : Data)`` function on the register."
+msgstr ""
+"除了直接创建具有复位值的寄存器的 ``RegInit(value : Data)`` 语法之外，"
+"您还可以通过在寄存器上调用 ``init(value : Data)`` 函数来设置复位值。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:135
+msgid ""
+"If you have a register containing a Bundle, you can use the ``init`` "
+"function on each element of the Bundle."
+msgstr "如果您有一个包含线束（Bundle）的寄存器，则可以对线束的每个元素使用 ``init`` "
+"函数。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:148
+msgid "Initialization value for simulation purposes"
+msgstr "用于仿真目的的初始化值"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:150
+msgid ""
+"For registers that don't need a reset value in RTL, but need an "
+"initialization value for simulation (to avoid x-propagation), you can ask "
+"for a random initialization value by calling the ``randBoot()`` function."
+msgstr ""
+"对于在 RTL "
+"中不需要复位值，但需要仿真初始化值（以避免未知状态X传播）的寄存器，"
+"您可以通过调用 ``randBoot()`` 函数来请求随机初始化值。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:158
+msgid "Register vectors"
+msgstr "寄存器组"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:160
+msgid ""
+"As for wires, it is possible to define a vector of registers with ``Vec``."
+msgstr "至于连线，可以使用 ``Vec`` 定义寄存器组。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:167
+msgid ""
+"Initialization can be done with the ``init`` method as usual, which can be "
+"combined with the ``foreach`` iteration on the registers."
+msgstr "初始化可以像往常一样使用 ``init`` 方法完成，它可以与寄存器上的 ``foreach`` "
+"迭代相结合。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:175
+msgid ""
+"In case where the initialization must be deferred since the init value is "
+"not known, use a function as in the example below."
+msgstr "如果由于初始化值未知而必须推迟初始化，请使用如下例所示的函数。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:208
+msgid "Transforming a wire into a register"
+msgstr "将线缆/信号转换为寄存器"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:210
+msgid ""
+"Sometimes it is useful to transform an existing wire into a register. For "
+"instance, when you are using a Bundle, if you want some outputs of the "
+"bundle to be registers, you might prefer to write ``io.myBundle.PORT := "
+"newValue`` without declaring registers with ``val PORT = Reg(...)`` and "
+"connecting their output to the port with ``io.myBundle.PORT := PORT``. To do"
+" this, you just need to use ``.setAsReg()`` on the ports you want to control"
+" as registers:"
+msgstr ""
+"有时将现有的连线转换为寄存器很有用。例如，当您使用线束（Bundle）时，如果您希"
+"望线束的某些输出成为寄存器，您可能更愿意编写 ``io.myBundle.PORT := newValue``"
+" 而不用 ``val PORT = Reg( ...)`` 并将其输出连接到带有 ``io.myBundle.PORT := "
+"PORT`` 的端口。为此，您只需在要实例化为寄存器的端口上使用 ``.setAsReg()``："
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:230
+msgid ""
+"Notice in the code above that you can also specify an initialization value."
+msgstr "请注意，在上面的代码中，您还可以指定初始化值。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:234
+msgid ""
+"The register is created in the clock domain of the wire, and does not depend"
+" on the place where ``.setAsReg()`` is used."
+msgstr "该寄存器是在线路/信号的时钟域中创建的，并且不依赖于使用 ``.setAsReg()`` "
+"的位置。"
+
+#: ../../SpinalHDL/Sequential logic/registers.rst:237
+msgid ""
+"In the example above, the wire is defined in the ``io`` Bundle, in the same "
+"clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` was "
+"written in a ``ClockingArea`` with a different clock domain, the register "
+"would use the clock domain of the component and not the one of the "
+"``ClockingArea``."
+msgstr ""
+"在上面的示例中，线路在 ``io`` 线束中定义，与组件位于同一时钟域中。即使 ``io."
+"apb.PADDR.setAsReg()`` 这条代码写在具有不同时钟域的 ``ClockingArea`` "
+"中，寄存器也将使用组件的时钟域，而不是 ``ClockingArea`` 的时钟域。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po
new file mode 100644
index 00000000000..0ab84974047
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po
@@ -0,0 +1,310 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationbootstraps/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:3
+msgid "Boot a simulation"
+msgstr "启动仿真器"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:6
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:8
+msgid "Below is an example hardware definition + testbench:"
+msgstr "下面是一个硬件定义+测试平台的示例："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:46
+msgid "Configuration"
+msgstr "配置"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:48
+msgid ""
+"``SimConfig`` will return a default simulation configuration instance on "
+"which you can call multiple functions to configure your simulation:"
+msgstr "``SimConfig`` 将返回一个默认的仿真配置实例，您可以在该实例上调用多个函数来配"
+"置您的仿真过程："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:54
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:55
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:56
+msgid "``withWave``"
+msgstr "``withWave``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:57
+msgid "Enable simulation wave capture (default format)"
+msgstr "打开仿真波形捕获与存储（默认格式）"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:58
+msgid "``withVcdWave``"
+msgstr "``withVcdWave``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:59
+msgid "Enable simulation wave capture (VCD text format)"
+msgstr "打开仿真波形捕获与存储（VCD格式）"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:60
+msgid "``withFstWave``"
+msgstr "``withFstWave``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:61
+msgid "Enable simulation wave capture (FST binary format)"
+msgstr "打开仿真波形捕获与存储（FST 二进制格式）"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:62
+msgid "``withConfig(SpinalConfig)``"
+msgstr "``withConfig(SpinalConfig)``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:63
+msgid ""
+"Specify the ``SpinalConfig`` that should be use to generate the hardware"
+msgstr "指定用于生成硬件的 ``SpinalConfig``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:64
+msgid "``allOptimisation``"
+msgstr "``allOptimisation``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:65
+msgid ""
+"Enable all the RTL compilation optimizations to reduce simulation time (will"
+" increase compilation time)"
+msgstr "启用所有 RTL 编译优化以减少仿真时间（会增加编译时间）"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:66
+msgid "``workspacePath(path)``"
+msgstr "``workspacePath(path)``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:67
+msgid "Change the folder where the sim files are generated"
+msgstr "更改生成的仿真文件存放的文件夹"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:68
+msgid "``withVerilator``"
+msgstr "``withVerilator``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:69
+msgid "Use Verilator as simulation backend (default)"
+msgstr "使用 Verilator 作为后台仿真器（默认）"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:70
+msgid "``withGhdl``"
+msgstr "``withGhdl``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:71
+msgid "Use GHDL as simulation backend"
+msgstr "使用GHDL作为后台仿真器"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:72
+msgid "``withIVerilog``"
+msgstr "``withIVerilog``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:73
+msgid "Use Icarus Verilog as simulation backend"
+msgstr "使用 Icarus Verilog 作为后台仿真器"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:74
+msgid "``withVCS``"
+msgstr "``withVCS``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:75
+msgid "Use Synopsys VCS as simulation backend"
+msgstr "使用Synopsys VCS作为后台仿真器"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:77
+msgid ""
+"Then you can call the ``compile(rtl)`` function to compile the hardware and "
+"warm up the simulator. This function will return a ``SimCompiled`` instance."
+msgstr "然后你可以调用 ``compile(rtl)`` 函数来编译硬件并预热仿真器。该函数将返回一个 "
+"``SimCompiled`` 实例。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:80
+msgid ""
+"On this ``SimCompiled`` instance you can run your simulation with the "
+"following functions:"
+msgstr "在此 ``SimCompiled`` 实例上，您可以使用以下函数进行仿真："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:86
+msgid "``doSim[(simName[, seed])]{dut => /* main stimulus code */}``"
+msgstr "``doSim[(simName[, seed])]{dut => /* main stimulus code */}``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:83
+msgid ""
+"Run the simulation until the main thread runs to completion and "
+"exits/returns. It will detect and report an error if the simulation gets "
+"fully stuck. As long as e.g. a clock is running the simulation can continue "
+"forever, it is therefore recommended to use ``SimTimeout(cycles)`` to limit "
+"the possible runtime."
+msgstr ""
+"运行仿真，直到主线程运行完成并退出/返回。如果仿真完全卡住，它将检测并报告错误"
+"。只要例如时钟正在运行，仿真过程可以永远持续下去，因此建议使用 "
+"``SimTimeout(cycles)`` 来限制可能的运行时间。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:91
+msgid "``doSimUntilVoid[(simName[, seed])]{dut => ...}``"
+msgstr "``doSimUntilVoid[(simName[, seed])]{dut => ...}``"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:89
+msgid ""
+"Run the simulation until it is ended by calling either ``simSuccess()`` or "
+"``simFailure()``. The main stimulus thread can continue or exit early. As "
+"long as there are events to process, the simulation will continue. The "
+"simulation will report an error if it gets fully stuck."
+msgstr ""
+"运行仿真，直到通过调用 ``simSuccess()`` 或 ``simFailure()`` 结束。主激励线程"
+"可以继续或提前退出。只要有事件需要处理，仿真就会继续。如果完全卡住，仿真器将"
+"报告错误。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:93
+msgid "The following testbench template will use the following toplevel :"
+msgstr "以下测试平台模板将使用以下顶层设计："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:102
+msgid "Here is a template with many simulation configurations:"
+msgstr "这是一个包含多个仿真配置的模板："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:119
+msgid ""
+"Here is a template where the simulation ends by completing the simulation "
+"main thread execution:"
+msgstr "这是一个模板，其中仿真过程在主仿真线程执行完成后结束："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:130
+msgid ""
+"Here is a template where the simulation ends by explicitly calling "
+"`simSuccess()`:"
+msgstr "这是一个模板，其中仿真过程通过显式调用 `simSuccess()` 结束："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:144
+msgid "Note is it equivalent to:"
+msgstr "注意它是否等同于："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:161
+msgid ""
+"Note that by default, the simulation files will be placed into the "
+"``simWorkspace/xxx`` folders. You can override the simWorkspace location by "
+"setting the ``SPINALSIM_WORKSPACE`` environment variable."
+msgstr ""
+"请注意，默认情况下，仿真文件将放置在 ``simWorkspace/xxx`` 文件夹中。"
+"您可以通过设置 ``SPINALSIM_WORKSPACE`` 环境变量来覆盖 simWorkspace 位置。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:164
+msgid "Running multiple tests on the same hardware"
+msgstr "在同一硬件上运行多个测试"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:179
+msgid "Throw Success or Failure of the simulation from a thread"
+msgstr "从线程中抛出仿真成功或失败结果"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:181
+msgid ""
+"At any moment during a simulation you can call ``simSuccess`` or "
+"``simFailure`` to end it."
+msgstr "在仿真过程中的任何时刻，您都可以调用 ``simSuccess`` 或 ``simFailure`` "
+"来结束它。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:183
+msgid ""
+"It is possible to make a simulation fail when it is too long, for instance "
+"because the test-bench is waiting for a condition which never occurs. To do "
+"so, call ``SimTimeout(maxDuration)`` where ``maxDuration`` is the time (in "
+"simulation units of time) after the which the simulation should be "
+"considered to have failed."
+msgstr ""
+"当仿真时间太长时，可能会导致仿真失败，例如，因为测试平台正在等待从未发生的条"
+"件。为此，请调用 ``SimTimeout(maxDuration)`` 函数设置超时时间，其中 "
+"``maxDuration`` 是仿真应被视为失败的时间（以仿真时间单位表示）。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:185
+msgid ""
+"For instance, to make the simulation fail after 1000 times the duration of a"
+" clock cycle:"
+msgstr "例如，要使仿真在持续 1000 个时钟周期后失败："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:194
+msgid "Capturing wave for a given window before failure"
+msgstr "在失败之前捕获给定时间窗内的波形"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:196
+msgid ""
+"In the case you have a very long simulation, and you don't want to capture "
+"the wave on all of it (too bug, too slow), you have mostly 2 ways to do it."
+msgstr "如果您有一个很长时间的仿真，并且您不想捕获所有波形（太多错误，太慢），那么您"
+"主要有两种方法可以做到这一点。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:198
+msgid ""
+"Either you know already at which ``simTime`` the simulation failed, in which"
+" case you can do the following in your testbench :"
+msgstr "要么您已经知道模拟在哪个 ``simTime`` "
+"失败，在这种情况下您可以在测试平台中执行以下操作："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:205
+msgid ""
+"Or you can run a dual lock-step simulation, with one running a bit delayed "
+"from the the other one, and which will start recording the wave once the "
+"leading simulation had a failure."
+msgstr "或者，您可以运行双步锁仿真，其中一个仿真的运行比另一个仿真的运行稍有延迟，一"
+"旦领先的模拟出现故障，它将开始记录波形。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:207
+msgid ""
+"To do this, you can use the DualSimTracer utility, with parameters for the "
+"compiled hardware, the window of time you want to capture before failure, "
+"and a seed."
+msgstr "为此，您可以使用 DualSimTracer "
+"实用程序，其中包含已编译硬件的参数、故障前要捕获的时间窗大小以及随机种子。"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:209
+msgid "Here is an example :"
+msgstr "这是一个例子："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:214
+msgid "This will generate the following file structure :"
+msgstr "这将生成以下文件结构："
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:216
+msgid ""
+"simWorkspace/Toplevel/explorer/stdout.log : stdout of the simulation which "
+"is ahead"
+msgstr ""
+"simWorkspace/Toplevel/explorer/stdout.log : stdout of the simulation which "
+"is ahead"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:217
+msgid ""
+"simWorkspace/Toplevel/tracer/stdout.log : stdout of the simulation doing the"
+" wave tracing"
+msgstr ""
+"simWorkspace/Toplevel/tracer/stdout.log : stdout of the simulation doing the "
+"wave tracing"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:218
+msgid "simWorkspace/Toplevel/tracer.fst : Waveform of the failure"
+msgstr "simWorkspace/Toplevel/tracer.fst : Waveform of the failure"
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:220
+msgid "The scala terminal will show the explorer simulation stdout."
+msgstr "scala 终端将显示仿真结果到标准输出。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po
new file mode 100644
index 00000000000..9d3759f7ff8
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po
@@ -0,0 +1,350 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationclock/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/clock.rst:2
+msgid "Clock domains"
+msgstr "时钟域"
+
+#: ../../SpinalHDL/Simulation/clock.rst:5
+msgid "Stimulus API"
+msgstr "激励函数API"
+
+#: ../../SpinalHDL/Simulation/clock.rst:7
+msgid "Below is a list of ``ClockDomain`` stimulation functions:"
+msgstr "以下是 ``ClockDomain`` 激励函数的列表："
+
+#: ../../SpinalHDL/Simulation/clock.rst:13
+msgid "ClockDomain stimulus functions"
+msgstr "时钟域激励函数"
+
+#: ../../SpinalHDL/Simulation/clock.rst:14
+#: ../../SpinalHDL/Simulation/clock.rst:48
+#: ../../SpinalHDL/Simulation/clock.rst:84
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Simulation/clock.rst:15
+msgid "``forkStimulus(period)``"
+msgstr "``forkStimulus(period)``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:16
+msgid ""
+"Fork a simulation process to generate the ClockDomain stimulus (clock, "
+"reset, softReset, clockEnable signals)"
+msgstr "分裂一个仿真进程以生成时钟域激励（时钟、复位、softReset、clockEnable 信号）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:17
+msgid "``forkSimSpeedPrinter(printPeriod)``"
+msgstr "``forkSimSpeedPrinter(printPeriod)``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:18
+msgid ""
+"Fork a simulation process which will periodically print the simulation speed"
+" in kilo-cycles per real time second. ``printPeriod`` is in realtime seconds"
+msgstr "分裂一个仿真进程，该进程将定期打印每秒实时千周期的仿真速度。 ``printPeriod`` "
+"是实时计数的秒数"
+
+#: ../../SpinalHDL/Simulation/clock.rst:19
+msgid "``clockToggle()``"
+msgstr "``clockToggle()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:20
+msgid "Toggle the clock signal"
+msgstr "翻转时钟信号"
+
+#: ../../SpinalHDL/Simulation/clock.rst:21
+msgid "``fallingEdge()``"
+msgstr "``fallingEdge()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:22
+msgid "Clear the clock signal"
+msgstr "清除时钟信号"
+
+#: ../../SpinalHDL/Simulation/clock.rst:23
+msgid "``risingEdge()``"
+msgstr "``risingEdge()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:24
+msgid "Set the clock signal"
+msgstr "设置时钟信号"
+
+#: ../../SpinalHDL/Simulation/clock.rst:25
+msgid "``assertReset()``"
+msgstr "``assertReset()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:26
+msgid "Set the reset signal to its active level"
+msgstr "将复位信号设置为有效（电平）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:27
+msgid "``deassertReset()``"
+msgstr "``deassertReset()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:28
+msgid "Set the reset signal to its inactive level"
+msgstr "将复位信号设置为无效（电平）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:29
+msgid "``assertClockEnable()``"
+msgstr "``assertClockEnable()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:30
+#: ../../SpinalHDL/Simulation/clock.rst:32
+msgid "Set the clockEnable signal to its active level"
+msgstr "将时钟使能信号设置为有效（电平）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:31
+msgid "``deassertClockEnable()``"
+msgstr "``deassertClockEnable()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:33
+msgid "``assertSoftReset()``"
+msgstr "``assertSoftReset()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:34
+#: ../../SpinalHDL/Simulation/clock.rst:36
+msgid "Set the softReset signal to its active level"
+msgstr "将软复位信号设置为有效（电平）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:35
+msgid "``deassertSoftReset()``"
+msgstr "``deassertSoftReset()``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:39
+msgid "Wait API"
+msgstr "等待相关API"
+
+#: ../../SpinalHDL/Simulation/clock.rst:41
+#: ../../SpinalHDL/Simulation/clock.rst:77
+msgid ""
+"Below is a list of ``ClockDomain`` utilities that you can use to wait for a "
+"given event from the domain:"
+msgstr "以下是 ``ClockDomain`` "
+"实用工具函数的列表，您可以用它们来等待来自时钟域的给定事件："
+
+#: ../../SpinalHDL/Simulation/clock.rst:47
+msgid "ClockDomain wait functions"
+msgstr "时钟域等待函数"
+
+#: ../../SpinalHDL/Simulation/clock.rst:49
+msgid "``waitSampling([cyclesCount])``"
+msgstr "``waitSampling([cyclesCount])``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:50
+msgid ""
+"Wait until the ``ClockDomain`` makes a sampling, (active clock edge && "
+"deassertReset && assertClockEnable)"
+msgstr "等待 ``ClockDomain`` 进行采样（有效时钟沿 && 无复位 && 时钟使能）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:51
+msgid "``waitRisingEdge([cyclesCount])``"
+msgstr "``waitRisingEdge([cyclesCount])``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:52
+msgid ""
+"Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 cycle "
+"if not otherwise specified. Note, cyclesCount = 0 is legal, and the function"
+" is not sensitive to reset/softReset/clockEnable"
+msgstr ""
+"等待cyclesCount个时钟的上升沿；如果没有另外指定，cycleCount 默认为 1 "
+"个周期。注意，cyclesCount = 0 是合法的，该功能对复位/softReset/clockEnable "
+"不敏感"
+
+#: ../../SpinalHDL/Simulation/clock.rst:53
+msgid "``waitFallingEdge([cyclesCount])``"
+msgstr "``waitFallingEdge([cyclesCount])``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:54
+msgid "Same as ``waitRisingEdge`` but for the falling edge"
+msgstr "与 ``waitRisingEdge`` 相同，但针对下降沿"
+
+#: ../../SpinalHDL/Simulation/clock.rst:55
+msgid "``waitActiveEdge([cyclesCount])``"
+msgstr "``waitActiveEdge([cyclesCount])``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:56
+msgid ""
+"Same as ``waitRisingEdge`` but for the edge level specified by the "
+"``ClockDomainConfig``"
+msgstr "与 ``waitRisingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型"
+
+#: ../../SpinalHDL/Simulation/clock.rst:57
+msgid "``waitRisingEdgeWhere(condition)``"
+msgstr "``waitRisingEdgeWhere(condition)``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:58
+msgid ""
+"Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be "
+"true when the rising edge occurs"
+msgstr "与 ``waitRisingEdge`` 功能相同，但要检查条件，上升沿发生时布尔 ``condition`` "
+"必须为真"
+
+#: ../../SpinalHDL/Simulation/clock.rst:59
+msgid "``waitFallingEdgeWhere(condition)``"
+msgstr "``waitFallingEdgeWhere(condition)``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:60
+msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge"
+msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对的是下降沿"
+
+#: ../../SpinalHDL/Simulation/clock.rst:61
+msgid "``waitActiveEdgeWhere(condition)``"
+msgstr "``waitActiveEdgeWhere(condition)``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:62
+msgid ""
+"Same as ``waitRisingEdgeWhere``, but for the edge level specified by the "
+"``ClockDomainConfig``"
+msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型"
+
+#: ../../SpinalHDL/Simulation/clock.rst:63
+msgid "``waitSamplingWhere(condition) : Boolean``"
+msgstr "``waitSamplingWhere(condition) : Boolean``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:64
+msgid "Wait until a clockdomain sampled and the given condition is true"
+msgstr "等待直到时钟域采样并且给定条件为真"
+
+#: ../../SpinalHDL/Simulation/clock.rst:65
+msgid "``waitSamplingWhere(timeout)(condition) : Boolean``"
+msgstr "``waitSamplingWhere(timeout)(condition) : Boolean``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:66
+msgid ""
+"Same as waitSamplingWhere defined above, but will never block more than "
+"timeout cycles. Return true if the exit condition came from the timeout"
+msgstr "与上面定义的 waitSamplingWhere "
+"相同，但阻塞不会超过timeout个周期。如果退出是因为超时，则返回 true"
+
+#: ../../SpinalHDL/Simulation/clock.rst:70
+msgid ""
+"All the functionality of the wait API can only be called directly from "
+"inside a thread, and not from a callback executed via the Callback API."
+msgstr "等待 API 的所有功能只能直接从线程内部调用，而不能从通过回调函数使用（通过回调"
+"API调用）。"
+
+#: ../../SpinalHDL/Simulation/clock.rst:75
+msgid "Callback API"
+msgstr "回调函数API"
+
+#: ../../SpinalHDL/Simulation/clock.rst:83
+msgid "ClockDomain callback functions"
+msgstr "时钟域回调函数"
+
+#: ../../SpinalHDL/Simulation/clock.rst:85
+msgid "``onNextSampling { callback }``"
+msgstr "``onNextSampling { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:86
+msgid ""
+"Execute the callback code only once on the next ``ClockDomain`` sample "
+"(active edge + reset off + clock enable on)"
+msgstr "仅在下一个 ``ClockDomain`` 样本上执行一次回调代码（有效边沿+无复位+时钟使能）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:87
+msgid "``onSamplings { callback }``"
+msgstr "``onSamplings { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:88
+msgid ""
+"Execute the callback code each time the ``ClockDomain`` sample (active edge "
+"+ reset off + clock enable on)"
+msgstr "每次 ``ClockDomain`` 采样时执行回调代码（有效边沿+无复位+时钟使能）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:89
+msgid "``onActiveEdges { callback }``"
+msgstr "``onActiveEdges { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:90
+msgid ""
+"Execute the callback code each time the ``ClockDomain`` clock generates its "
+"configured edge"
+msgstr "每次 ``ClockDomain`` 时钟符合其配置的边沿的条件时执行回调代码"
+
+#: ../../SpinalHDL/Simulation/clock.rst:91
+msgid "``onEdges { callback }``"
+msgstr "``onEdges { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:92
+msgid ""
+"Execute the callback code each time the ``ClockDomain`` clock generates a "
+"rising or falling edge"
+msgstr "每次 ``ClockDomain`` 时钟出现上升沿或下降沿时执行回调代码"
+
+#: ../../SpinalHDL/Simulation/clock.rst:93
+msgid "``onRisingEdges { callback }``"
+msgstr "``onRisingEdges { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:94
+msgid ""
+"Execute the callback code each time the ``ClockDomain`` clock generates a "
+"rising edge"
+msgstr "每次 ``ClockDomain`` 的时钟出现上升沿时执行回调代码"
+
+#: ../../SpinalHDL/Simulation/clock.rst:95
+msgid "``onFallingEdges { callback }``"
+msgstr "``onFallingEdges { callback }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:96
+msgid ""
+"Execute the callback code each time the ``ClockDomain`` clock generates a "
+"falling edge"
+msgstr "每次 ``ClockDomain`` 中时钟出现下降沿时执行回调代码"
+
+#: ../../SpinalHDL/Simulation/clock.rst:97
+msgid "``onSamplingWhile { callback : Boolean }``"
+msgstr "``onSamplingWhile { callback : Boolean }``"
+
+#: ../../SpinalHDL/Simulation/clock.rst:98
+msgid ""
+"Same as onSampling, but you can stop it (forever) by letting the callback "
+"returning false"
+msgstr "与 onSampling 相同，但您可以通过让回调返回 false 来停止它（永远）"
+
+#: ../../SpinalHDL/Simulation/clock.rst:103
+msgid "Default ClockDomain"
+msgstr "默认时钟域"
+
+#: ../../SpinalHDL/Simulation/clock.rst:105
+msgid ""
+"You can access the default ``ClockDomain`` of your toplevel as shown below:"
+msgstr "您可以访问顶层模块的默认 ``ClockDomain`` ，如下所示："
+
+#: ../../SpinalHDL/Simulation/clock.rst:121
+msgid "Note that you can also directly fork a standard reset/clock process:"
+msgstr "请注意，您还可以直接分裂标准复位/时钟产生进程："
+
+#: ../../SpinalHDL/Simulation/clock.rst:127
+msgid "An example of how to wait for a rising edge on the clock:"
+msgstr "如何等待时钟上升沿的示例："
+
+#: ../../SpinalHDL/Simulation/clock.rst:135
+msgid "New ClockDomain"
+msgstr "新时钟域"
+
+#: ../../SpinalHDL/Simulation/clock.rst:137
+msgid ""
+"If your toplevel defines some clock and reset inputs which aren't directly "
+"integrated into their ``ClockDomain``, you can define their corresponding "
+"``ClockDomain`` directly in the testbench:"
+msgstr ""
+"如果您的顶层模块中定义了一些未直接集成到其 ``ClockDomain`` 中的时钟和复位，"
+"您可以直接在测试平台中定义其相应的 ``ClockDomain`` ："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/engine.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/engine.po
new file mode 100644
index 00000000000..5966b40c026
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/engine.po
@@ -0,0 +1,95 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationengine/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:5
+msgid "Simulation engine"
+msgstr "仿真引擎"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:7
+msgid "This page explains the internals of the simulation engine."
+msgstr "本页介绍了仿真引擎的内部结构。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:9
+msgid ""
+"The simulation engine emulates an event-driven simulator (VHDL/Verilog like)"
+" by applying the following simulation loop on the top of the Verilator C++ "
+"simulation model:"
+msgstr "仿真引擎通过在 Verilator C++ 仿真模型顶部应用以下循环来使用事件驱动仿真器（"
+"类似 VHDL/Verilog）："
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:14
+msgid ""
+"At a low level, the simulation engine manages the following primitives:"
+msgstr "在底层，仿真引擎管理以下原语："
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:16
+msgid ""
+"*Sensitive callbacks*, which allow users to call a function on each "
+"simulation delta cycle."
+msgstr "*敏感回调*，允许用户在每个仿真增量周期中调用函数。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:17
+msgid ""
+"*Delayed callbacks*, which allow users to call a function at a future "
+"simulation time."
+msgstr "*延迟回调*，允许用户在未来的仿真时间调用函数。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:18
+msgid ""
+"*Simulation threads*, which allow users to describe concurrent processes."
+msgstr "*仿真线程*，允许用户描述并发的进程。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:19
+msgid ""
+"*Command buffer*, which allows users to delay write access to the :abbr:`DUT"
+" (Device Under Test)` until the end of the current delta cycle."
+msgstr "*命令缓冲区*，允许用户延迟对 "
+"DUT（被测设备）的写入访问，直到当前仿真增量周期结束。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:21
+msgid "There are some practical uses of those primitives:"
+msgstr "这些原语有一些实际用途："
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:23
+msgid ""
+"Sensitive callbacks can be used to wake up a simulation thread when a given "
+"condition happens, like a rising edge on a clock."
+msgstr "当给定条件发生时，例如时钟的上升沿，敏感回调可用于唤醒仿真线程。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:24
+msgid ""
+"Delayed callbacks can be used to schedule stimuli, such as deasserting a "
+"reset after a given time, or toggling the clock."
+msgstr "延迟回调可用于安排激励，例如在给定时间后取消复位，或翻转时钟。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:25
+msgid ""
+"Both sensitive and delayed callbacks can be used to resume a simulation "
+"thread."
+msgstr "敏感回调和延迟回调都可用于恢复仿真线程。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:26
+msgid ""
+"A simulation thread can be used (for instance) to produce stimulus and check"
+" the DUT's output values."
+msgstr "例如，可以使用仿真线程来产生激励并检查 DUT 的输出值。"
+
+#: ../../source/SpinalHDL/Simulation/engine.rst:27
+msgid ""
+"The command buffer's purpose is mainly to avoid all concurrency issues "
+"between the DUT and the testbench."
+msgstr "命令缓冲区的目的主要是避免 DUT 和测试平台之间的所有并发问题。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/asynchronous.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/asynchronous.po
new file mode 100644
index 00000000000..36722e331c1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/asynchronous.po
@@ -0,0 +1,50 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplesasynchronous/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:4
+msgid "Asynchronous adder"
+msgstr "异步加法器"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:6
+msgid ""
+"This example creates a ``Component`` out of combinational logic that does "
+"some simple arithmetic on 3 operands."
+msgstr "此示例使用组合逻辑创建一个 ``Component`` ，对 3 "
+"个操作数执行一些简单的算术运算。"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:8
+msgid "The test bench performs the following steps 100 times:"
+msgstr "测试平台执行 100 次以下步骤："
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:10
+msgid ""
+"Initialize ``a``, ``b``, and ``c`` to random integers in the 0..255 range."
+msgstr "将 ``a``, ``b``, 和 ``c`` 初始化为 0..255 范围内的随机整数。"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:11
+msgid ""
+"Stimulate the :abbr:`DUT (Device Under Test)`'s matching ``a``, ``b``, ``c``"
+" inputs."
+msgstr "激励 :abbr:`DUT (Device Under Test)` 匹配 ``a``, ``b``, ``c`` 的输入。"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:12
+msgid "Wait 1 simulation timestep (to allow the inputs to propagate)."
+msgstr "等待 1 个仿真步长（以允许输入传播）。"
+
+#: ../../source/SpinalHDL/Simulation/examples/asynchronous.rst:13
+msgid "Check for correct output."
+msgstr "检查输出是否正确。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/dual_clock_fifo.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/dual_clock_fifo.po
new file mode 100644
index 00000000000..43a3119d10d
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/dual_clock_fifo.po
@@ -0,0 +1,55 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplesdual_clock_fifo/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:4
+msgid "Dual clock fifo"
+msgstr "双时钟域FIFO"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:6
+msgid ""
+"This example creates a ``StreamFifoCC``, which is designed for crossing "
+"clock domains, along with 3 simulation threads."
+msgstr "此示例创建了一个专为跨时钟域而设计的 ``StreamFifoCC`` 以及 3 个仿真线程。"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:8
+msgid "The threads handle:"
+msgstr "线程处理："
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:10
+msgid "Management of the two clocks"
+msgstr "两个时钟域的管理"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:11
+msgid "Pushing to the FIFO"
+msgstr "推入 FIFO"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:12
+msgid "Popping from the FIFO"
+msgstr "从 FIFO 弹出"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:14
+msgid "The FIFO push thread randomizes the inputs."
+msgstr "FIFO 推送线程将输入随机化。"
+
+#: ../../source/SpinalHDL/Simulation/examples/dual_clock_fifo.rst:16
+msgid ""
+"The FIFO pop thread handles checking the the :abbr:`DUT (Device Under "
+"Test)`'s outputs against the reference model (an ordinary "
+"``scala.collection.mutable.Queue`` instance)."
+msgstr ""
+"FIFO 弹出线程根据参考模型（普通的 scala.collection.mutable.Queue 实例）检查 "
+":abbr:`DUT (Device Under Test)` 的输出。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/index.po
new file mode 100644
index 00000000000..13185492497
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/index.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-12 09:30+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplesindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/index.rst:3
+msgid "Examples"
+msgstr "示例"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/single_clock_fifo.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/single_clock_fifo.po
new file mode 100644
index 00000000000..e72bc595471
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/single_clock_fifo.po
@@ -0,0 +1,58 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplessingle_clock_fifo/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:4
+msgid "Single clock fifo"
+msgstr "单时钟域FIFO"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:6
+msgid ""
+"This example creates a ``StreamFifo``, and spawns 3 simulation threads. "
+"Unlike the :ref:`Dual clock fifo <sim_example_dual_clock_fifo>` example, "
+"this FIFO does not need complex clock management."
+msgstr ""
+"此示例创建一个 ``StreamFifo``，并生成 3 个仿真线程。与 :ref:`Dual clock fifo "
+"<sim_example_dual_clock_fifo>` 示例不同，此 FIFO 不需要复杂的时钟管理。"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:9
+msgid "The 3 simulation threads handle:"
+msgstr "3个仿真线程处理："
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:11
+msgid "Managing the clock/reset"
+msgstr "管理时钟/复位"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:12
+msgid "Pushing to the FIFO"
+msgstr "推入 FIFO"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:13
+msgid "Popping from the FIFO"
+msgstr "从 FIFO 弹出"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:15
+msgid "The FIFO push thread randomizes the inputs."
+msgstr "FIFO 推送线程将输入随机化。"
+
+#: ../../source/SpinalHDL/Simulation/examples/single_clock_fifo.rst:17
+msgid ""
+"The FIFO pop thread handles checking the the :abbr:`DUT (Device Under "
+"Test)`'s outputs against the reference model (an ordinary "
+"``scala.collection.mutable.Queue`` instance)."
+msgstr ""
+"FIFO 弹出线程根据参考模型（普通的 scala.collection.mutable.Queue 实例）检查 "
+":abbr:`DUT (Device Under Test)` 的输出。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/synchronous.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/synchronous.po
new file mode 100644
index 00000000000..d5861068496
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/synchronous.po
@@ -0,0 +1,61 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplessynchronous/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:4
+msgid "Synchronous adder"
+msgstr "同步加法器"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:6
+msgid ""
+"This example creates a ``Component`` out of sequential logic that does some "
+"simple arithmetic on 3 operands."
+msgstr "这个例子创建了一个由时序逻辑组成的 ``Component`` ，它对 3 "
+"个操作数进行了一些简单的算术运算。"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:8
+msgid "The test bench performs the following steps 100 times:"
+msgstr "测试平台执行 100 次以下步骤："
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:10
+msgid ""
+"Initialize ``a``, ``b``, and ``c`` to random integers in the 0..255 range."
+msgstr "将 ``a``, ``b``, 和 ``c`` 初始化为 0..255 范围内的随机整数。"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:11
+msgid ""
+"Stimulate the :abbr:`DUT (Device Under Test)`'s matching ``a``, ``b``, ``c``"
+" inputs."
+msgstr "激励 :abbr:`DUT (Device Under Test)` 匹配 ``a``, ``b``, ``c`` 的输入。"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:12
+msgid "Wait until the simulation samples the DUT's signals again."
+msgstr "等待直到仿真再次对 DUT 的信号进行采样。"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:13
+msgid "Check for correct output."
+msgstr "检查输出是否正确。"
+
+#: ../../source/SpinalHDL/Simulation/examples/synchronous.rst:15
+msgid ""
+"The main difference between this example and the :ref:`Asynchronous adder "
+"<sim_example_asynchronous_adder>` example is that this ``Component`` has to "
+"use ``forkStimulus`` to generate a clock signal, since it is using "
+"sequential logic internally."
+msgstr ""
+"此示例与异步加法器 :ref:`Asynchronous adder <sim_example_asynchronous_adder>`"
+" 示例之间的主要区别在于，此 ``Component`` 必须使用 ``forkStimulus`` "
+"来生成时钟信号，因为它在内部使用顺序逻辑。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_decoder.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_decoder.po
new file mode 100644
index 00000000000..1e26c8f471c
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_decoder.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplesuart_decoder/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/uart_decoder.rst:3
+msgid "Uart decoder"
+msgstr "串口解码器"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_encoder.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_encoder.po
new file mode 100644
index 00000000000..48aad1701cc
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/examples/uart_encoder.po
@@ -0,0 +1,20 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationexamplesuart_encoder/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/examples/uart_encoder.rst:3
+msgid "Uart encoder"
+msgstr "串口编码器"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/index.po
new file mode 100644
index 00000000000..3e6cb7d81ff
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/index.po
@@ -0,0 +1,233 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/index.rst:3
+msgid "Simulation"
+msgstr "仿真"
+
+#: ../../SpinalHDL/Simulation/index.rst:5
+msgid ""
+"As always, you can use your standard simulation tools to simulate the "
+"VHDL/Verilog generated by SpinalHDL. However, since SpinalHDL 1.0.0, the "
+"language integrates an API to write testbenches and test your hardware "
+"directly in Scala. This API provides the capabilities to read and write the "
+"DUT signals, fork and join simulation processes, sleep and wait until a "
+"given condition is reached. Therefore, using SpinalHDL's simulation API, it "
+"is easy to integrate testbenches with the most common Scala unit-test "
+"frameworks."
+msgstr ""
+"与往常一样，您可以使用标准仿真工具来仿真 SpinalHDL 生成的 VHDL/"
+"Verilog。然而，从 SpinalHDL 1.0.0 开始，该语言集成了一个 API "
+"来编写测试平台并直接在 Scala 中测试您的硬件。该 API 提供了读取和写入 DUT "
+"信号、分裂和合并仿真的进程、休眠和等待直到达到给定条件的功能。因此，使用 "
+"SpinalHDL 的仿真 API，可以轻松地将测试平台与最常见的 Scala "
+"单元测试框架集成起来。"
+
+#: ../../SpinalHDL/Simulation/index.rst:11
+msgid ""
+"To be able to simulate user-defined components, SpinalHDL uses external HDL "
+"simulators as backend. Currently, four simulators are supported:"
+msgstr "为了能够仿真用户定义的组件，SpinalHDL 使用外部 HDL "
+"仿真器作为后台。目前支持四种仿真器："
+
+#: ../../SpinalHDL/Simulation/index.rst:13
+msgid "`Verilator <https://www.veripool.org/verilator/>`_"
+msgstr "`Verilator <https://www.veripool.org/verilator/>`_"
+
+#: ../../SpinalHDL/Simulation/index.rst:14
+msgid ""
+"`GHDL <http://ghdl.free.fr/>`_ **(experimental, since SpinalHDL 1.4.1)**"
+msgstr "`GHDL <http://ghdl.free.fr/>`_ **（实验性，自 SpinalHDL 1.4.1 起）**"
+
+#: ../../SpinalHDL/Simulation/index.rst:15
+msgid ""
+"`Icarus Verilog <https://steveicarus.github.io/iverilog/>`_ **(experimental,"
+" since SpinalHDL 1.4.1)**"
+msgstr ""
+"`Icarus Verilog <https://steveicarus.github.io/iverilog/>`_ **（实验性，自 "
+"SpinalHDL 1.4.1 起）**"
+
+#: ../../SpinalHDL/Simulation/index.rst:16
+msgid ""
+"`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`_ "
+"**(experimental, since SpinalHDL 1.7.0)**"
+msgstr ""
+"`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`_ "
+"**（实验性，自 SpinalHDL 1.7.0 起）**"
+
+#: ../../SpinalHDL/Simulation/index.rst:17
+msgid ""
+"`XSim <https://www.google.com/search?q=site%3Axilinx.com+xsim>`_ "
+"**(experimental, since SpinalHDL 1.7.0)**"
+msgstr ""
+"`XSim <https://www.google.com/search?q=site%3Axilinx.com+xsim>`_ **（实验性，"
+"自 SpinalHDL 1.7.0 起）**"
+
+#: ../../SpinalHDL/Simulation/index.rst:19
+msgid ""
+"With external HDL simulators it is possible to directly test the generated "
+"HDL sources without increasing the SpinalHDL codebase complexity."
+msgstr "使用外部 HDL 仿真器，可以直接测试生成的 HDL 源文件，而不会增加 SpinalHDL "
+"代码库的复杂性。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
+
+#~ msgid "How SpinalHDL simulates the hardware with Verilator backend"
+#~ msgstr "SpinalHDL 如何使用 Verilator 后端模拟硬件"
+
+#~ msgid ""
+#~ "Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model "
+#~ "of the DUT and then uses Verilator to convert it to a C++ cycle-accurate "
+#~ "model."
+#~ msgstr "SpinalHDL 在后台生成 DUT 的 Verilog 等效硬件模型，然后使用 Verilator 将其转换为 C++ 周期精确模型。"
+
+#~ msgid ""
+#~ "The C++ model is compiled into a shared object (.so), which is bound to "
+#~ "Scala via JNR-FFI."
+#~ msgstr "C++ 模型被编译成共享对象（.so），该对象通过 JNR-FFI 绑定到 Scala。"
+
+#~ msgid ""
+#~ "The native Verilator API is abstracted by providing a simulation multi-"
+#~ "threaded API."
+#~ msgstr "通过提供模拟多线程API来抽象本机Verilator API。"
+
+#~ msgid "**Advantages:**"
+#~ msgstr "**优点：**"
+
+#~ msgid ""
+#~ "Since the Verilator backend uses a compiled C++ simulation model, the "
+#~ "simulation speed is fast compared to most of the other commercial and free "
+#~ "simulators."
+#~ msgstr "由于Verilator后端使用编译的C++仿真模型，因此与大多数其他商业和免费模拟器相比，仿真速度很快。"
+
+#~ msgid "**Limitations:**"
+#~ msgstr "**限制：**"
+
+#~ msgid ""
+#~ "Verilator accepts only synthesizable Verilog/System Verilog code. Therefore "
+#~ "special care has to be taken when simulating Verilog blackbox components "
+#~ "that may have non-synthesizable statements."
+#~ msgstr ""
+#~ "Verilator 仅接受可综合的 Verilog/System Verilog 代码。因此，在模拟可能具有不可综合语句的 Verilog "
+#~ "黑盒组件时必须特别小心。"
+
+#~ msgid "VHDL blackboxes cannot be simulated."
+#~ msgstr "VHDL 黑盒无法模拟。"
+
+#~ msgid ""
+#~ "The simulation boot process is slow due to the necessity to compile and link"
+#~ " the generated C++ model"
+#~ msgstr "由于需要编译和链接生成的 C++ 模型，模拟启动过程很慢"
+
+#~ msgid "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend"
+#~ msgstr "SpinalHDL 如何使用 GHDL/Icarus Verilog 后端模拟硬件"
+
+#~ msgid ""
+#~ "Depending on the chosen simulator, SpinalHDL generates a Verilog or VHDL "
+#~ "hardware model of the DUT."
+#~ msgstr "根据所选模拟器，SpinalHDL 生成 DUT 的 Verilog 或 VHDL 硬件模型。"
+
+#~ msgid "The HDL model is loaded in the simulator."
+#~ msgstr "HDL 模型已加载到模拟器中。"
+
+#~ msgid ""
+#~ "The communication between the simulation and the JVM is established through "
+#~ "shared memory. The commands are issued to the simulator using `VPI "
+#~ "<https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_."
+#~ msgstr ""
+#~ "模拟和JVM之间的通信是通过共享内存建立的。使用“VPI "
+#~ "<https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>”向模拟器发出命令。"
+
+#~ msgid "Both GHDL and Icarus Verilog can accept non-synthesizable HDL code."
+#~ msgstr "GHDL 和 Icarus Verilog 都可以接受不可综合的 HDL 代码。"
+
+#~ msgid "The simulation boot process is quite faster compared to Verilator."
+#~ msgstr "与 Verilator 相比，模拟启动过程要快得多。"
+
+#~ msgid ""
+#~ "GHDL accepts VHDL code only. Therefore only VHDL blackboxes can be used with"
+#~ " this simulator."
+#~ msgstr "GHDL 仅接受 VHDL 代码。因此，该模拟器只能使用 VHDL 黑盒。"
+
+#~ msgid ""
+#~ "Icarus Verilog accepts Verilog code only. Therefore only Verilog blackboxes "
+#~ "can be used with this simulator."
+#~ msgstr "Icarus Verilog 仅接受 Verilog 代码。因此，该模拟器只能使用 Verilog 黑盒。"
+
+#~ msgid ""
+#~ "The simulation speed is around one order of magnitude slower compared to "
+#~ "Verilator."
+#~ msgstr "与 Verilator 相比，仿真速度大约慢一个数量级。"
+
+#~ msgid ""
+#~ "Finally, as the native Verilator API is rather crude, SpinalHDL abstracts "
+#~ "over it by providing both single and multi-threaded simulation APIs to help "
+#~ "the user construct testbench implementations."
+#~ msgstr ""
+#~ "最后，由于原生 Verilator API 相当粗糙，SpinalHDL 通过提供单线程和多线程模拟 API 对其进行抽象，以帮助用户构建测试平台实现。"
+
+#~ msgid "How SpinalHDL simulates the hardware with Synopsys VCS backend"
+#~ msgstr "SpinalHDL 如何使用 Synopsys VCS 后端模拟硬件"
+
+#~ msgid ""
+#~ "SpinalHDL generates a Verilog/VHDL (depended on your choice) hardware model "
+#~ "of the DUT."
+#~ msgstr "SpinalHDL 生成 DUT 的 Verilog/VHDL（取决于您的选择）硬件模型。"
+
+#~ msgid "Support all language features of SystemVerilog/Verilog/VHDL."
+#~ msgstr "支持SystemVerilog/Verilog/VHDL的所有语言特性。"
+
+#~ msgid "Support encrypted IP."
+#~ msgstr "支持加密IP。"
+
+#~ msgid "Support FSDB wave format dump."
+#~ msgstr "支持 FSDB 波形格式转储。"
+
+#~ msgid "High Performance of both compilation and simulation."
+#~ msgstr "编译和模拟的高性能。"
+
+#~ msgid ""
+#~ "Synopsys VCS is a **commercial** simulation tool. It is close source and not"
+#~ " free. You have to own the licenses to **legally** use it."
+#~ msgstr "Synopsys VCS 是一款**商业**仿真工具。它是闭源的并且不是免费的。您必须拥有许可证才能**合法**使用它。"
+
+#~ msgid ""
+#~ "Before using VCS as the simulation backend, make sure that you have checked "
+#~ "your system environment as :ref:`VCS environment<vcs_env>`."
+#~ msgstr "在使用 VCS 作为模拟后端之前，请确保您已将系统环境检查为:ref:`VCS 环境<vcs_env>`。"
+
+#~ msgid "Performance"
+#~ msgstr "表现"
+
+#~ msgid ""
+#~ "When a high-performance simulation is required, Verilator should be used as "
+#~ "a backend. On a little SoC like `Murax "
+#~ "<https://github.com/SpinalHDL/VexRiscv>`_, an Intel® Core™ i7-4720HQ is "
+#~ "capable of simulating 1.2 million clock cycles per second. However, when the"
+#~ " DUT is simple and a maximum of few thousands clock cycles have to be "
+#~ "simulated, using GHDL or Icarus Verilog could yield a better result, due to "
+#~ "their lower simulation loading overhead."
+#~ msgstr ""
+#~ "当需要高性能仿真时，应使用Verilator作为后端。在像“Murax "
+#~ "<https://github.com/SpinalHDL/VexRiscv>”这样的小型 SoC 上，英特尔® 酷睿™ i7-4720HQ "
+#~ "能够每秒模拟 120 万个时钟周期。然而，当 DUT 很简单并且需要仿真最多几千个时钟周期时，使用 GHDL 或 Icarus Verilog "
+#~ "可以产生更好的结果，因为它们的仿真负载开销较低。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po
new file mode 100644
index 00000000000..1d7361873f7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po
@@ -0,0 +1,65 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationinstallghdl/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:3
+msgid "Setup and installation of GHDL"
+msgstr "GHDL 的设置和安装"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:6
+msgid ""
+"If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup "
+"<Install>` you can skip the instructions below - but you need to activate "
+"the oss-cad-suite environment."
+msgstr ""
+"如果您在 SpinalHDL :ref:`安装和设置 <Install>` 期间安装了推荐的 oss-cad-"
+"suite，您可以跳过下面的说明 - 但您需要激活 oss-cad-suite 环境。"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:9
+msgid ""
+"Even though GHDL is generally available in linux distributions package "
+"system, SpinalHDL depends on bugfixes of GHDL codebase that were added after"
+" the release of GHDL v0.37. Therefore it is reccomended to install GHDL from"
+" source. The C++ library boost-interprocess, which is contained in the "
+"libboost-dev package in debian-like distributions, has to be installed too. "
+"boost-interprocess is required to generate the shared memory communication "
+"interface."
+msgstr ""
+"尽管 GHDL 在 Linux 发行版软件包系统中普遍可用，但 SpinalHDL 依赖于 GHDL "
+"v0.37 发布后添加的 GHDL 代码库的错误修复。因此，建议从源代码安装 GHDL。"
+"还必须安装 C++ 库 boost-interprocess，它包含在类似 debian 发行版的 libboost-"
+"dev 包中。需要 boost-interprocess 来生成共享内存通信接口。"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:13
+msgid "Linux"
+msgstr "Linux"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:29
+msgid ""
+"Also the openjdk package that corresponds to your Java version has to be "
+"installed."
+msgstr "还必须安装与您的 Java 版本相对应的 openjdk 软件包。"
+
+#: ../../SpinalHDL/Simulation/install/GHDL.rst:31
+msgid ""
+"For more configuration options and Windows installation see "
+"`<https://ghdl.github.io/ghdl/getting.html>`_"
+msgstr "有关更多配置选项和 Windows 安装，请参阅 `<https://ghdl.github.io/ghdl/getting"
+".html>`_"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po
new file mode 100644
index 00000000000..69fc4352aeb
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po	
@@ -0,0 +1,60 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationinstallicarus-verilog/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:3
+msgid "Setup and installation of Icarus Verilog"
+msgstr "Icarus Verilog 的设置和安装"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:6
+msgid ""
+"If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup "
+"<Install>` you can skip the instructions below - but you need to activate "
+"the oss-cad-suite environment."
+msgstr ""
+"如果您在 SpinalHDL :ref:`安装和设置 <Install>` 期间安装了推荐的 oss-cad-"
+"suite，您可以跳过下面的说明 - 但您需要激活 oss-cad-suite 环境。"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:9
+msgid ""
+"In most recent linux distributions, a recent version of Icarus Verilog is "
+"generally available through the package system. The C++ library boost-"
+"interprocess, which is contained in the libboost-dev package in debian-like "
+"distributions, has to be installed too. boost-interprocess is required to "
+"generate the shared memory communication interface."
+msgstr ""
+"在大多数最新的 Linux 发行版中，最新版本的 Icarus Verilog "
+"通常可以通过软件包系统获得。还必须安装 C++ 库 boost-interprocess，"
+"它包含在类似 debian 发行版的 libboost-dev 包中。需要 boost-interprocess "
+"来生成共享内存通信接口。"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:13
+msgid "Linux"
+msgstr "Linux"
+
+#: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:20
+msgid ""
+"Also the openjdk package that corresponds to your Java version has to be "
+"installed. Refer to `<https://iverilog.fandom.com/wiki/Installation_Guide>`_"
+" for more informations about Windows and installation from source."
+msgstr ""
+"还必须安装与您的 Java 版本相对应的 openjdk 软件包。有关 Windows "
+"和从源安装的更多信息，请参阅`<https://iverilog.fandom.com/wiki/"
+"Installation_Guide>`_。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po
new file mode 100644
index 00000000000..9e20aa1c7a7
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po
@@ -0,0 +1,242 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationinstallvcs/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:3
+msgid "VCS Simulation Configuration"
+msgstr "VCS 仿真配置"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:8
+msgid "Environment variable"
+msgstr "环境变量"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:10
+msgid "You should have several environment variables defined before:"
+msgstr "您应该确保提前定义了以下几个环境变量："
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:12
+msgid "``VCS_HOME``: The home path to your VCS installation."
+msgstr "``VCS_HOME``：VCS 安装的主路径。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:13
+msgid "``VERDI_HOME``: The home path to your Verdi installation."
+msgstr "``VERDI_HOME`` ：Verdi安装的主路径。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:14
+msgid "Add ``$VCS_HOME/bin`` and ``$VERDI_HOME/bin`` to your ``PATH``."
+msgstr "将 ``$VCS_HOME/bin`` 和 ``$VERDI_HOME/bin`` 添加到你的 ``PATH`` 中。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:16
+msgid ""
+"Prepend the following paths to your ``LD_LIBRARY_PATH`` to enable PLI "
+"features."
+msgstr "将以下路径添加到 ``LD_LIBRARY_PATH`` 变量的前部以启用 PLI 功能。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:26
+msgid ""
+"If you encounter the ``Compilation of SharedMemIface.cpp failed`` error, "
+"make sure that you have installed C++ boost library correctly. The header "
+"and library files path should be added to ``CPLUS_INCLUDE_PATH``, "
+"``LIBRARY_PATH`` and ``LD_LIBRARY_PATH`` respectively."
+msgstr ""
+"如果您遇到 ``Compilation of SharedMemIface.cpp failed`` 错误，"
+"请确保您已正确安装 C++ boost 库。头文件和库文件路径应分别添加到 "
+"``CPLUS_INCLUDE_PATH``、 ``LIBRARY_PATH`` 和 ``LD_LIBRARY_PATH`` 中。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:30
+msgid "User defined environment setup"
+msgstr "用户定义的环境设置"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:32
+msgid ""
+"Sometimes a VCS environment setup file `synopsys_sim.setup` is required to "
+"run VCS simulation. Also you may want to run some scripts or code to setup "
+"the environment just before VCS starting compilation. You can do this by "
+"`withVCSSimSetup`."
+msgstr ""
+"有时需要 VCS 环境设置文件 `synopsys_sim.setup` 来运行 VCS 仿真。此外，"
+"您可能希望在 VCS 开始编译之前运行一些脚本或代码来设置环境。您可以通过 "
+"`withVCSSimSetup` 来完成此操作。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:47
+msgid ""
+"This method will copy your own `synopsys_sim.setup` file to the VCS work "
+"directory under the `workspacePath` (default as `simWorkspace`) directory, "
+"and run your scripts."
+msgstr ""
+"此方法将您自己的 `synopsys_sim.setup` 文件复制到 `workspacePath` （默认为 "
+"`simWorkspace` ）目录下的VCS工作目录，并运行脚本。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:51
+msgid "VCS Flags"
+msgstr "VCS 标志"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:53
+msgid "The VCS backend follows the three step compilation flow:"
+msgstr "VCS 后台遵循三步编译流程："
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:55
+msgid "Analysis step: analysis the HDL model using ``vlogan`` and ``vhdlan``."
+msgstr "分析步骤：使用 ``vlogan`` 和 ``vhdlan``分析HDL模型。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:57
+msgid ""
+"Elaborate step: elaborate the model using ``vcs`` and generate the "
+"executable hardware model."
+msgstr "实例细化步骤：使用 ``vcs`` 细化模型并生成可执行的硬件模型。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:59
+msgid "Simulation step: run the simulation."
+msgstr "仿真步骤：运行仿真。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:61
+msgid ""
+"In each step, user can pass some specific flags through ``VCSFlags`` to "
+"enable some features like SDF back-annotation or multi-threads."
+msgstr "在每个步骤中，用户可以通过 ``VCSFlags`` 传递一些特定的标志，以启用一些功能，"
+"例如 SDF 反注释或多线程。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:63
+msgid "``VCSFlags`` takes three parameters,"
+msgstr "``VCSFlags`` 采用三个参数，"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:69
+msgid "Name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:70
+msgid "Type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:71
+#: ../../SpinalHDL/Simulation/install/VCS.rst:112
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:72
+msgid "``compileFlags``"
+msgstr "``compileFlags``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:73
+#: ../../SpinalHDL/Simulation/install/VCS.rst:76
+#: ../../SpinalHDL/Simulation/install/VCS.rst:79
+msgid "``List[String]``"
+msgstr "``List[String]``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:74
+msgid "Flags pass to ``vlogan`` or ``vhdlan``."
+msgstr "传递标志到 ``vlogan`` 或 ``vhdlan``。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:75
+msgid "``elaborateFlags``"
+msgstr "``elaborateFlags``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:77
+msgid "Flags pass to ``vcs``."
+msgstr "传递标志到 ``vcs``。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:78
+msgid "``runFlags``"
+msgstr "``runFlags``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:80
+msgid "Flags pass to executable hardware model."
+msgstr "传递标志给可执行硬件模型。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:82
+msgid ""
+"For example, you pass the ``-kdb`` flags to both compilation step and "
+"elaboration step, for Verdi debugging,"
+msgstr "例如，您将 ``-kdb`` 标志传递给编译步骤和细化步骤，以进行 Verdi 调试，"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:101
+msgid "Waveform generation"
+msgstr "波形生成"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:103
+msgid ""
+"VCS backend can generate three waveform format: ``VCD``, ``VPD`` and "
+"``FSDB`` (Verdi required)."
+msgstr "VCS 后端可以生成三种波形格式：``VCD``、``VPD`` 和 ``FSDB``（需要 Verdi）。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:105
+msgid "You can enable them by the following methods of ``SpinalSimConfig``,"
+msgstr "您可以通过 ``SpinalSimConfig`` 的以下方法启用它们，"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:111
+msgid "Method"
+msgstr "方法"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:113
+msgid "``withWave``"
+msgstr "``withWave``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:114
+msgid "Enable ``VCD`` waveform."
+msgstr "生成 ``VCD`` 波形。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:115
+msgid "``withVPDWave``"
+msgstr "``withVPDWave``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:116
+msgid "Enable ``VPD`` waveform."
+msgstr "生成 ``VPD`` 波形。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:117
+msgid "``withFSDBWave``"
+msgstr "``withFSDBWave``"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:118
+msgid "Enable ``FSDB`` waveform."
+msgstr "生成 ``FSDB`` 波形。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:120
+msgid ""
+"Also, you can control the wave trace depth by using ``withWaveDepth(depth: "
+"Int)``."
+msgstr "此外，您可以使用 ``withWaveDepth(depth: Int)`` 来控制波形文件记录的深度。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:123
+msgid "Simulation with ``Blackbox``"
+msgstr "``Blackbox`` 仿真"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:125
+msgid ""
+"Sometimes, IP vendors will provide you with some design entites in "
+"Verilog/VHDL format and you want to integrate them into your SpinalHDL "
+"design. The integration can done by following two ways:"
+msgstr ""
+"有时，您希望将 IP 供应商为您提供的一些 Verilog/VHDL 格式的设计实体集成到您的 "
+"SpinalHDL 设计中。可以通过以下两种方式完成："
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:128
+msgid ""
+"In a ``Blackbox`` definition, use ``addRTLPath(path: String)`` to assign a "
+"external Verilog/VHDL file to this blackbox."
+msgstr ""
+"在 ``Blackbox`` 定义中，使用 ``addRTLPath(path: String)`` 将外部 Verilog/"
+"VHDL 文件分配给该黑盒。"
+
+#: ../../SpinalHDL/Simulation/install/VCS.rst:129
+msgid ""
+"Use the method ``mergeRTLSource(fileName: String=null)`` of "
+"``SpinalReport``."
+msgstr "使用 ``SpinalReport`` 的 ``mergeRTLSource(fileName: String=null)`` 方法。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po
new file mode 100644
index 00000000000..9a91c4ac719
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po
@@ -0,0 +1,153 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationinstallverilator/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:3
+msgid "Setup and installation of Verilator"
+msgstr "Verilator 的设置和安装"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:6
+msgid ""
+"If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup "
+"<Install>` you can skip the instructions below - but you need to activate "
+"the oss-cad-suite environment."
+msgstr ""
+"如果您在 SpinalHDL :ref:`安装和设置 <Install>` 期间安装了推荐的 oss-cad-"
+"suite，您可以跳过下面的说明 - 但您需要激活 oss-cad-suite 环境。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:9
+msgid ""
+"SpinalSim + Verilator is supported on both Linux and Windows platforms."
+msgstr "Linux 和 Windows 平台均支持 SpinalSim + Verilator。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:11
+msgid ""
+"It is recommended that v4.218 is the oldest Verilator version to use.  While"
+" it maybe possible to use older verilator versions, some optional and Scala "
+"source dependent features that SpinalHDL can use (such as Verilog "
+"``$urandom`` support) may not be supported by older Verilator versions and "
+"will cause an error when trying to simulate."
+msgstr ""
+"建议使用的 Verilator 版本最老不低于 v4.218。虽然可以使用较旧的 verilator "
+"版本，但 SpinalHDL 可以使用的一些可选的和 Scala 源文件相关功能（例如 Verilog "
+"``$urandom`` 支持）可能不受旧版本 Verilator "
+"支持，并且会在尝试仿真时会导致错误。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:16
+msgid ""
+"Ideally the latest v4.xxx and v5.xxx is well supported and bug reports "
+"should be opened with any issues you have."
+msgstr "理想情况下，最新的 v4.xxx 和 v5.xxx "
+"得到良好支持，并且应针对您遇到的任何问题打开错误报告工单。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:20
+msgid "Scala"
+msgstr "Scala"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:22
+msgid "Don't forget to add the following in your ``build.sbt`` file:"
+msgstr "不要忘记在 ``build.sbt`` 文件中添加以下内容："
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:28
+msgid ""
+"And you will always need the following imports in your Scala testbench:"
+msgstr "你总是需要在Scala测试平台中加入以下导入代码："
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:36
+msgid "Linux"
+msgstr "Linux"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:38
+msgid "You will also need a recent version of Verilator installed :"
+msgstr "您还需要安装最新版本的 Verilator："
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:56
+msgid "Windows"
+msgstr "Windows"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:58
+msgid ""
+"In order to get SpinalSim + Verilator working on Windows, you have to do the"
+" following:"
+msgstr "为了让 SpinalSim + Verilator 在 Windows 上工作，您必须执行以下操作："
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:60
+msgid "Install `MSYS2 <https://www.msys2.org/>`_"
+msgstr "安装 `MSYS2 <https://www.msys2.org/>`_"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:61
+msgid ""
+"Via MSYS2 get gcc/g++/verilator (for Verilator you can compile it from the "
+"sources)"
+msgstr "通过 MSYS2 获取 gcc/g++/verilator （对于 Verilator，您可以从源代码编译它）"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:62
+msgid ""
+"Add ``bin`` and ``usr\\bin`` of MSYS2 into your windows ``PATH`` (ie : "
+"``C:\\msys64\\usr\\bin;C:\\msys64\\mingw64\\bin``)"
+msgstr ""
+"将 MSYS2 的 ``bin`` 和 ``usr\\bin`` 添加到 Windows ``PATH`` 中（即：``C:"
+"\\msys64\\usr\\bin;C:\\msys64\\mingw64 \\bin``)"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:63
+msgid ""
+"Check that the JAVA_HOME environment variable points to the JDK installation"
+" folder (i.e.: ``C:\\Program Files\\Java\\jdk-13.0.2``)"
+msgstr ""
+"检查 JAVA_HOME 环境变量是否指向 JDK 安装文件夹（即：``C:\\Program Files\\Java"
+"\\jdk-13.0.2``）"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:65
+msgid ""
+"Then you should be able to run SpinalSim + Verilator from your Scala project"
+" without having to use MSYS2 anymore."
+msgstr "然后您应该能够从 Scala 项目运行 SpinalSim + Verilator，而无需再使用 MSYS2。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:67
+msgid ""
+"From a fresh install of MSYS2 MinGW 64-bit, you will have to run the "
+"following commands inside the MSYS2 MinGW 64-bits shell (enter commands one "
+"by one):"
+msgstr "从全新安装 MSYS2 MinGW 64 位开始，您必须在 MSYS2 MinGW 64 位 shell "
+"中运行以下命令："
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:70
+msgid "From the MinGW package manager"
+msgstr "从 MinGW 包管理器安装"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:86
+msgid "From source"
+msgstr "从源码安装"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:114
+msgid ""
+"Be sure that your ``PATH`` environnement variable is pointing to the JDK 1.8"
+" and doesn't contain a JRE installation."
+msgstr "确保您的 ``PATH`` 环境变量指向 JDK 1.8 并且不包含 JRE 安装。"
+
+#: ../../SpinalHDL/Simulation/install/Verilator.rst:117
+msgid ""
+"Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could potentialy"
+" have some side effects. This is why it is safer to add them as the last "
+"elements of the ``PATH`` to reduce their priority."
+msgstr ""
+"将 MSYS2 ``bin`` 文件夹添加到 Windows ``PATH`` 可能会产生一些副作用。"
+"这就是为什么将它们添加为 ``PATH`` "
+"的最后一个元素以降低其优先级，这样会更安全。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/index.po
new file mode 100644
index 00000000000..6c83b3fb74f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/index.po
@@ -0,0 +1,52 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationinstallindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/install/index.rst:2
+msgid "SBT setup for simulation"
+msgstr "用于仿真的 SBT 设置"
+
+#: ../../SpinalHDL/Simulation/install/index.rst:4
+msgid ""
+"To enable SpinalSim, the following lines have to be added in your build.sbt "
+"file :"
+msgstr "要启用 SpinalSim，必须在 build.sbt 文件中添加以下行："
+
+#: ../../SpinalHDL/Simulation/install/index.rst:10
+msgid "Also the following imports have to be added in testbenches sources :"
+msgstr "此外，还必须在测试平台源文件中添加以下导入："
+
+#: ../../SpinalHDL/Simulation/install/index.rst:19
+msgid ""
+"Also, if you need to use gmake instead of make (ex OpenBSD) you can set the "
+"SPINAL_MAKE_CMD environnement variable to \"gmake\""
+msgstr ""
+"另外，如果您要使用 gmake 而不是 make（例如 OpenBSD），您可以将 "
+"SPINAL_MAKE_CMD 环境变量设置为 \"gmake\""
+
+#: ../../SpinalHDL/Simulation/install/index.rst:22
+msgid "Backend-dependent installation instructions"
+msgstr "后台依赖的安装说明"
+
+#~ msgid "Installation instructions"
+#~ msgstr "安装说明"
+
+#~ msgid "Scala"
+#~ msgstr "斯卡拉"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/sensitive.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/sensitive.po
new file mode 100644
index 00000000000..20939cdc264
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/sensitive.po
@@ -0,0 +1,56 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationsensitive/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:4
+msgid "Sensitive API"
+msgstr "敏感API"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:6
+msgid ""
+"You can register callback functions to be called on each delta-cycle of the "
+"simulation:"
+msgstr "您可以注册要在仿真过程中每个仿真增量周期调用的回调函数："
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:12
+msgid "Sensitive functions"
+msgstr "敏感函数"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:13
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:14
+msgid "``forkSensitive { callback }``"
+msgstr "``forkSensitive { callback }``"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:15
+msgid ""
+"Register the callback code to be called at each delta-cycle of the "
+"simulation"
+msgstr "注册要在仿真的每个仿真增量周期调用的回调代码"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:16
+msgid "``forkSensitiveWhile { callback }``"
+msgstr "``forkSensitiveWhile { callback }``"
+
+#: ../../source/SpinalHDL/Simulation/sensitive.rst:17
+msgid ""
+"Register the callback code to be called at each delta-cycle of the "
+"simulation, while the callback return value is true (meaning it should be "
+"rescheduled for the next delta-cycle)"
+msgstr "注册要在仿真过程的每个仿真增量周期调用的回调代码，而回调返回值为 "
+"true（意味着应该为下一个仿真增量周期重新调度）"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/signal.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/signal.po
new file mode 100644
index 00000000000..97d1b04644e
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/signal.po
@@ -0,0 +1,223 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-12 04:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationsignal/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/signal.rst:2
+msgid "Accessing signals of the simulation"
+msgstr "仿真过程中访问信号"
+
+#: ../../SpinalHDL/Simulation/signal.rst:5
+msgid "Read and write signals"
+msgstr "读写信号"
+
+#: ../../SpinalHDL/Simulation/signal.rst:7
+msgid ""
+"Each interface signal of the toplevel can be read and written from Scala:"
+msgstr "顶层模块的每个接口信号都可以从 Scala 程序中读写："
+
+#: ../../SpinalHDL/Simulation/signal.rst:13
+#: ../../SpinalHDL/Simulation/signal.rst:124
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Simulation/signal.rst:14
+#: ../../SpinalHDL/Simulation/signal.rst:125
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Simulation/signal.rst:15
+msgid "``Bool.toBoolean``"
+msgstr "``Bool.toBoolean``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:16
+msgid "Read a hardware ``Bool`` as a Scala ``Boolean`` value"
+msgstr "将硬件 ``Bool`` 读取出来并转换为 Scala ``Boolean`` 值"
+
+#: ../../SpinalHDL/Simulation/signal.rst:17
+msgid "``Bits``/``UInt``/``SInt.toInt``"
+msgstr "``Bits``/``UInt``/``SInt.toInt``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:18
+msgid "Read a hardware ``BitVector`` as a Scala ``Int`` value"
+msgstr "将硬件 ``BitVector`` 读取出来并转换为 Scala的 ``Int`` 值"
+
+#: ../../SpinalHDL/Simulation/signal.rst:19
+msgid "``Bits``/``UInt``/``SInt.toLong``"
+msgstr "``Bits``/``UInt``/``SInt.toLong``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:20
+msgid "Read a hardware ``BitVector`` as a Scala ``Long`` value"
+msgstr "将硬件 ``BitVector`` 读取出来并转换为 Scala的 ``Long`` 值"
+
+#: ../../SpinalHDL/Simulation/signal.rst:21
+msgid "``Bits``/``UInt``/``SInt.toBigInt``"
+msgstr "``Bits``/``UInt``/``SInt.toBigInt``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:22
+msgid "Read a hardware ``BitVector`` as a Scala ``BigInt`` value"
+msgstr "将硬件中的 ``BitVector`` 值读取出来并转换为 Scala中的 ``BigInt`` "
+"值（无限位宽）"
+
+#: ../../SpinalHDL/Simulation/signal.rst:23
+msgid "``SpinalEnumCraft.toEnum``"
+msgstr "``SpinalEnumCraft.toEnum``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:24
+msgid ""
+"Read a hardware ``SpinalEnumCraft`` as a Scala ``SpinalEnumElement`` value"
+msgstr "将硬件中的 ``SpinalEnumCraft`` 读取出来并转换为 Scala 的 "
+"``SpinalEnumElement`` 值"
+
+#: ../../SpinalHDL/Simulation/signal.rst:25
+msgid "``Bool #= Boolean``"
+msgstr "``Bool #= Boolean``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:26
+msgid "Assign a hardware ``Bool`` from an Scala ``Boolean``"
+msgstr "将 Scala 的 ``Boolean`` 值赋值给硬件 ``Bool``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:27
+msgid "``Bits``/``UInt``/``SInt #= Int``"
+msgstr "``Bits``/``UInt``/``SInt #= Int``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:28
+msgid "Assign a hardware ``BitVector`` from a Scala ``Int``"
+msgstr "将 Scala 的 ``Int`` 值赋值给硬件 ``BitVector``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:29
+msgid "``Bits``/``UInt``/``SInt #= Long``"
+msgstr "``Bits``/``UInt``/``SInt #= Long``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:30
+msgid "Assign a hardware ``BitVector`` from a Scala ``Long``"
+msgstr "将 Scala 的 ``Long`` 值赋值给硬件 ``BitVector``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:31
+msgid "``Bits``/``UInt``/``SInt #= BigInt``"
+msgstr "``Bits``/``UInt``/``SInt #= BigInt``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:32
+msgid "Assign a hardware ``BitVector`` from a Scala ``BigInt``"
+msgstr "将 Scala 的 ``BigInt`` 值赋值给硬件 ``BitVector``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:33
+msgid "``SpinalEnumCraft #= SpinalEnumElement``"
+msgstr "``SpinalEnumCraft #= SpinalEnumElement``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:34
+msgid ""
+"Assign a hardware ``SpinalEnumCraft`` from a Scala ``SpinalEnumElement``"
+msgstr "将 Scala 的 ``SpinalEnumElement`` 值赋值给硬件 ``SpinalEnumCraft``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:35
+msgid "``Data.randomize()``"
+msgstr "``Data.randomize()``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:36
+msgid "Assign a random value to a SpinalHDL value."
+msgstr "将随机值赋值给 SpinalHDL 硬件信号。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:48
+msgid "Accessing signals inside the component's hierarchy"
+msgstr "访问组件层次结构内部的信号"
+
+#: ../../SpinalHDL/Simulation/signal.rst:50
+msgid ""
+"To access signals which are inside the component's hierarchy, you have first"
+" to set the given signal as ``simPublic``."
+msgstr "要访问组件层次结构内部的信号，您必须首先将给定信号设置为 ``simPublic``。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:52
+msgid ""
+"You can add this ``simPublic`` tag directly in the hardware description:"
+msgstr "您可以直接在硬件描述中添加此 ``simPublic`` 标签："
+
+#: ../../SpinalHDL/Simulation/signal.rst:76
+msgid ""
+"Or you can add it later, after having instantiated your toplevel for the "
+"simulation:"
+msgstr "或者您可以稍后在实例化仿真的顶层文件中添加它："
+
+#: ../../SpinalHDL/Simulation/signal.rst:108
+msgid "Load and Store of Memory in Simulation"
+msgstr "仿真中内存的加载和存储"
+
+#: ../../SpinalHDL/Simulation/signal.rst:110
+msgid ""
+"It is possible to modify the contents of ``Mem`` hardware interface "
+"components in simulation.  The `data` argument should be a word-width value "
+"with the `address` being the word-address within."
+msgstr "可以在仿真中修改 ``Mem`` 硬件接口组件的内容。 `data` "
+"参数应该是一个字的位宽的值，`address` 是访问的字的地址。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:114
+msgid ""
+"There is no API to convert address and/or individual data bits into units "
+"other than the natural word size."
+msgstr "没有 API 可以将地址和/或单个数据位转换为自然的字位宽以外的单位。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:117
+msgid ""
+"There is no API to mark any memory location with simulation `X` (undefined) "
+"state."
+msgstr "没有 API 可以用仿真中的 `X`（未定义）状态来标记任何内存位置。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:126
+msgid "``Mem.getBigInt(address: Long): BigInt``"
+msgstr "``Mem.getBigInt(address: Long): BigInt``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:127
+msgid "Read a word from simulator at the word-address."
+msgstr "从仿真器的对应地址处读取一个字。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:128
+msgid "``Mem.setBigInt(address: Long, data: BigInt)``"
+msgstr "``Mem.setBigInt(address: Long, data: BigInt)``"
+
+#: ../../SpinalHDL/Simulation/signal.rst:129
+msgid "Write a word to simulator at the word-address."
+msgstr "在地址处向仿真器内的存储器写入一个字。"
+
+#: ../../SpinalHDL/Simulation/signal.rst:131
+msgid "Using this simple example using a memory:"
+msgstr "这是一个简单的使用内存的示例："
+
+#: ../../SpinalHDL/Simulation/signal.rst:138
+msgid "Setting up the simulation we make the memory accessible:"
+msgstr "设置仿真环境后，我们可以这样访问内存："
+
+#: ../../SpinalHDL/Simulation/signal.rst:145
+msgid ""
+"We can read data during simulation, but have to take care that the data is "
+"already available (might be a cycle late due to simulation event ordering):"
+msgstr "我们可以在仿真期间读取数据，但必须注意确保数据可用（由于仿真器是事件驱动的，"
+"这可能会造成一个周期的延迟）："
+
+#: ../../SpinalHDL/Simulation/signal.rst:153
+msgid "And can write to memory like so:"
+msgstr "并且可以像这样写入内存："
+
+#: ../../SpinalHDL/Simulation/signal.rst:160
+msgid ""
+"Care has to be taken that due to event ordering in simulation e.g. the read "
+"depicted above has to be delayed to when the value is actually available in "
+"the memory."
+msgstr "必须注意的是，由于仿真器是事件驱动的，例如上面描述的读取操作必须延迟到该值在"
+"内存中实际可用后进行。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po
new file mode 100644
index 00000000000..ab4460c4603
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po
@@ -0,0 +1,255 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2024-01-13 05:06+0000\n"
+"Last-Translator: tsy0123 <675526215@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationsimulator_specifics/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:3
+msgid "Simulator specific details"
+msgstr "仿真器的具体细节"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:6
+msgid "How SpinalHDL simulates the hardware with Verilator backend"
+msgstr "SpinalHDL 如何使用 Verilator 后端进行硬件仿真"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:8
+msgid ""
+"Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model "
+"of the DUT and then uses Verilator to convert it to a C++ cycle-accurate "
+"model."
+msgstr "SpinalHDL 在后台生成 DUT 的 Verilog 等效硬件模型，然后使用 Verilator "
+"将其转换为 C++ 的周期精确模型。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:9
+msgid ""
+"The C++ model is compiled into a shared object (.so), which is bound to "
+"Scala via JNI-FFI."
+msgstr "C++ 模型被编译为共享对象 (.so)，该对象通过 JNI-FFI 绑定到 Scala。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:10
+msgid ""
+"The native Verilator API is abstracted by providing a simulation multi-"
+"threaded API."
+msgstr "通过提供多线程仿真API来抽象原始的Verilator API。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:12
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:29
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:49
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:69
+msgid "**Advantages:**"
+msgstr "**优点：**"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:14
+msgid ""
+"Since the Verilator backend uses a compiled C++ simulation model, the "
+"simulation speed is fast compared to most of the other commercial and free "
+"simulators."
+msgstr "由于Verilator后端使用编译的C++仿真模型，因此与大多数其他商业和免费模拟器相比"
+"，仿真速度很快。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:16
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:34
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:56
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:73
+msgid "**Limitations:**"
+msgstr "**限制：**"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:18
+msgid ""
+"Verilator accepts only synthesizable Verilog/System Verilog code. Therefore "
+"special care has to be taken when simulating Verilog blackbox components "
+"that may have non-synthesizable statements."
+msgstr ""
+"Verilator 仅接受可综合的 Verilog/System Verilog 代码。因此，"
+"在仿真中使用了包含不可综合语句的 Verilog 黑盒组件时必须特别小心。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:19
+msgid "VHDL blackboxes cannot be simulated."
+msgstr "VHDL 黑盒无法模拟。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:20
+msgid ""
+"The simulation boot process is slow due to the necessity to compile and link"
+" the generated C++ model.  Some support to incrementally compile and link "
+"exists which can provide speedups for subsequent simulations after building "
+"the first."
+msgstr ""
+"由于需要编译和链接生成的 C++ 模型，仿真的启动过程很慢。存在对增量编译和链接的"
+"一些支持，这可以在构建第一个仿真模型后为后续模型仿真提供加速。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:23
+msgid "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend"
+msgstr "SpinalHDL 如何使用 GHDL/Icarus Verilog 后端进行硬件仿真"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:25
+msgid ""
+"Depending on the chosen simulator, SpinalHDL generates a Verilog or VHDL "
+"hardware model of the DUT."
+msgstr "根据所选仿真器，SpinalHDL 生成 DUT 的 Verilog 或 VHDL 硬件模型。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:26
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:46
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:66
+msgid "The HDL model is loaded in the simulator."
+msgstr "HDL 模型加载到仿真器中。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:27
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:47
+msgid ""
+"The communication between the simulation and the JVM is established through "
+"shared memory. The commands are issued to the simulator using `VPI "
+"<https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_."
+msgstr ""
+"仿真器和JVM之间的通信是通过共享内存建立的。使用 `VPI <https://en.wikipedia."
+"org/wiki/Verilog_Procedural_Interface>`_ 向模拟器发出命令。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:31
+msgid "Both GHDL and Icarus Verilog can accept non-synthesizable HDL code."
+msgstr "GHDL 和 Icarus Verilog 都可以接受不可综合的 HDL 代码。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:32
+msgid "The simulation boot process is quite faster compared to Verilator."
+msgstr "与 Verilator 相比，仿真启动过程要快得多。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:36
+msgid ""
+"GHDL accepts VHDL code only. Therefore only VHDL blackboxes can be used with"
+" this simulator."
+msgstr "GHDL 仅接受 VHDL 代码。因此，该仿真器只能使用 VHDL 黑盒。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:37
+msgid ""
+"Icarus Verilog accepts Verilog code only. Therefore only Verilog blackboxes "
+"can be used with this simulator."
+msgstr "Icarus Verilog 仅接受 Verilog 代码。因此，该仿真器只能使用 Verilog 黑盒。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:38
+msgid ""
+"The simulation speed is around one order of magnitude slower compared to "
+"Verilator."
+msgstr "与 Verilator 相比，仿真速度大约慢一个数量级。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:40
+msgid ""
+"Finally, as the native Verilator API is rather crude, SpinalHDL abstracts "
+"over it by providing both single and multi-threaded simulation APIs to help "
+"the user construct testbench implementations."
+msgstr ""
+"最后，由于原生 Verilator API 相当粗糙，SpinalHDL 通过提供单线程和多线程仿真 "
+"API 对其进行抽象，以帮助用户构建测试平台实现。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:43
+msgid "How SpinalHDL simulates the hardware with Synopsys VCS backend"
+msgstr "SpinalHDL 如何使用 Synopsys VCS 后端进行硬件仿真"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:45
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:65
+msgid ""
+"SpinalHDL generates a Verilog/VHDL (depended on your choice) hardware model "
+"of the DUT."
+msgstr "SpinalHDL 生成 DUT 的 Verilog/VHDL（取决于您的选择）硬件模型。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:51
+msgid "Support all language features of SystemVerilog/Verilog/VHDL."
+msgstr "支持SystemVerilog/Verilog/VHDL的所有语言特性。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:52
+msgid "Support encrypted IP."
+msgstr "支持加密IP。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:53
+msgid "Support FSDB wave format dump."
+msgstr "支持 FSDB 波形格式存储。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:54
+msgid "High Performance of both compilation and simulation."
+msgstr "编译和仿真的性能好。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:58
+msgid ""
+"Synopsys VCS is a **commercial** simulation tool. It is close source and not"
+" free. You have to own the licenses to **legally** use it."
+msgstr "Synopsys VCS 是一款 **商用** 仿真工具。它是闭源的并且不是免费的。"
+"您必须拥有许可证才能 **合法** 使用它。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:60
+msgid ""
+"Before using VCS as the simulation backend, make sure that you have checked "
+"your system environment as :ref:`VCS environment<vcs_env>`."
+msgstr "在使用 VCS 作为仿真后台之前，请确保您已将系统环境检查为 :ref:`VCS "
+"环境<vcs_env>`。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:63
+msgid "How SpinalHDL simulates the hardware with Xilinx XSim backend"
+msgstr "SpinalHDL 如何使用 Xilinx XSim 后端进行硬件仿真"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:67
+msgid ""
+"The communication between the simulation and the JVM is established through "
+"shared memory. The commands are issued to the simulator using XSI."
+msgstr "仿真器和JVM之间的通信是通过共享内存建立的。命令使用 XSI 发送到仿真器。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:71
+msgid "Support Xilinx built-in primitives and cores."
+msgstr "支持 Xilinx 内置原语和IP核。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:75
+msgid ""
+"Xilinx XSim is a **commercial** tool installed with Vivado. It is closed "
+"source and subject to licensing terms to use. You have to own the licenses "
+"to **legally** use it."
+msgstr ""
+"Xilinx XSim 是与 Vivado 一起安装的 **商用** "
+"工具。它是闭源的，并受许可条款的使用。您必须拥有许可证才能 **合法** 使用它。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:76
+msgid "Vivado versions prior to 2019.1 do not work properly."
+msgstr "2019.1 之前的 Vivado 版本无法正常工作。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:78
+msgid ""
+"Before using XSim as the simulation backend, make sure that you have done "
+"following steps. 1. Define VIVADO_HOME environment variable to specify where"
+" your vivado located. ex `export VIVADO_HOME=/d/Xilinx/Vivado/2022.1` (under"
+" MSYS2). 2. Make sure two vivado path is inside the PATH. For Windows MSYS2 "
+"user, run shell command like `export "
+"PATH=$PATH:$VIVADO_HOME/bin:$VIVADO_HOME/lib/win64.o`. For Linux user just "
+"source the Vivado's settings64.sh file located at `VIVADO_HOME`."
+msgstr ""
+"在使用 XSim 作为仿真后台之前，请确保您已完成以下步骤。 1. 定义 VIVADO_HOME "
+"环境变量以指定 vivado 所在的位置。例如， `export VIVADO_HOME=/d/Xilinx/"
+"Vivado/2022.1` （在 MSYS2 下）。 2.确保两个vivado路径在PATH内。对于 Windows "
+"MSYS2 用户，运行 shell 命令，如 `export PATH=$PATH:$VIVADO_HOME/bin:$"
+"VIVADO_HOME/lib/win64.o` 。对于 Linux 用户，只需用 `source` 执行位于 "
+"`VIVADO_HOME` 的 settings64.sh 文件。"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:83
+msgid "Performance"
+msgstr "性能"
+
+#: ../../SpinalHDL/Simulation/simulator_specifics.rst:85
+msgid ""
+"When a high-performance simulation is required, Verilator should be used as "
+"a backend. On a little SoC like `Murax "
+"<https://github.com/SpinalHDL/VexRiscv>`_, an Intel® Core™ i7-4720HQ is "
+"capable of simulating 1.2 million clock cycles per second. However, when the"
+" DUT is simple and a maximum of few thousands clock cycles have to be "
+"simulated, using GHDL or Icarus Verilog could yield a better result, due to "
+"their lower simulation loading overhead."
+msgstr ""
+"当需要高性能仿真时，应使用Verilator作为后台。在像 `Murax <https://github.com/"
+"SpinalHDL/VexRiscv>`_ 这样的小型 SoC 上，英特尔® 酷睿™ i7-4720HQ "
+"能够每秒模拟 120 万个时钟周期。然而，当 DUT "
+"很简单并且需要仿真最多几千个时钟周期时，使用 GHDL 或 Icarus Verilog "
+"可以产生更好的结果，因为它们的仿真负载开销较低。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadFull.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadFull.po
new file mode 100644
index 00000000000..cf9f7f557b5
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadFull.po
@@ -0,0 +1,39 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationthreadfull/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/threadFull.rst:2
+msgid "Thread-full API"
+msgstr "全线程API"
+
+#: ../../source/SpinalHDL/Simulation/threadFull.rst:4
+msgid ""
+"In SpinalSim, you can write your testbench by using multiple threads in a "
+"similar way to SystemVerilog, and a bit like VHDL/Verilog process/always "
+"blocks. This allows you to write concurrent tasks and control the simulation"
+" time using a fluent API."
+msgstr ""
+"在 SpinalSim 中，您可以使用多个线程来编写测试平台，方法与 SystemVerilog "
+"类似，有点像 VHDL/Verilog的process/always 块。这允许您使用流畅的 API "
+"编写并发任务并控制仿真时间。"
+
+#: ../../source/SpinalHDL/Simulation/threadFull.rst:9
+msgid "Fork and join simulation threads"
+msgstr "分裂和合并仿真线程"
+
+#: ../../source/SpinalHDL/Simulation/threadFull.rst:22
+msgid "Sleep and waitUntil"
+msgstr "休眠和等待"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadLess.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadLess.po
new file mode 100644
index 00000000000..71fcfb356ff
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/threadLess.po
@@ -0,0 +1,70 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-30 08:06+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlsimulationthreadless/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:2
+msgid "Thread-less API"
+msgstr "无线程API"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:4
+msgid ""
+"There are some functions that you can use to avoid the need for threading, "
+"but which still allow you to control the flow of simulation time."
+msgstr "您可以使用一些函数来避免使用线程，但仍然允许您控制仿真时的流程。"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:10
+msgid "Threadless functions"
+msgstr "无线程函数"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:11
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:12
+msgid "``delayed(delay){ callback }``"
+msgstr "``delayed(delay){ callback }``"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:13
+msgid ""
+"Register the callback code to be called at a simulation time ``delay`` steps"
+" after the current timestep."
+msgstr "注册要在当前时间步 ``delay`` 步之后调用的回调代码。"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:15
+msgid ""
+"The advantages of the ``delayed`` function over using a regular simulation "
+"thread + sleep are:"
+msgstr "与使用常规模拟线程+休眠相比， ``delayed`` 函数的优点是："
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:17
+msgid "Performance (no context switching)"
+msgstr "性能（无上下文切换）"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:18
+msgid "Memory usage (no native JVM thread memory allocation)"
+msgstr "内存使用情况（无本机 JVM 线程内存分配）"
+
+#: ../../source/SpinalHDL/Simulation/threadLess.rst:20
+msgid ""
+"Some other thread-less functions related to ``ClockDomain`` objects are "
+"documented as part of the :ref:`Callback API <sim_clock_threadless>`, and "
+"some others related with the delta-cycle execution process are documented as"
+" part of the :ref:`Sensitive API <sim_sensitive_api>`"
+msgstr ""
+"与 ``ClockDomain`` 对象相关的一些其他无线程函数被设计为 :ref:`Callback API "
+"<sim_clock_threadless>` 的一部分，"
+"而其他一些与仿真增量周期执行过程相关的函数被设计为 :ref:`Sensitive API "
+"<sim_sensitive_api>` 的一部分。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/area.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/area.po
new file mode 100644
index 00000000000..1f721064e34
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/area.po
@@ -0,0 +1,64 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringarea/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/area.rst:2
+msgid "Area"
+msgstr "Area"
+
+#: ../../SpinalHDL/Structuring/area.rst:4
+msgid ""
+"Sometimes, creating a ``Component`` to define some logic is overkill because"
+" you:"
+msgstr "有时，创建一个 ``Component`` 组件来定义某些逻辑是多余的，因为："
+
+#: ../../SpinalHDL/Structuring/area.rst:6
+msgid ""
+"Need to define all construction parameters and IO (verbosity, duplication)"
+msgstr "需要定义所有构造参数和IO（冗长、重复）"
+
+#: ../../SpinalHDL/Structuring/area.rst:7
+msgid "Split your code (more than needed)"
+msgstr "拆分您的代码（超出需求）"
+
+#: ../../SpinalHDL/Structuring/area.rst:9
+msgid ""
+"For this kind of case you can use an ``Area`` to define a group of "
+"signals/logic:"
+msgstr "对于这种情况，您可以使用 ``Area`` 来定义一组信号/逻辑："
+
+#: ../../SpinalHDL/Structuring/area.rst
+msgid ""
+"In VHDL and Verilog, sometimes prefixes are used to separate variables into "
+"logical sections. It is suggested that you use ``Area`` instead  of this in "
+"SpinalHDL."
+msgstr "在 VHDL 和 Verilog 中，有时使用前缀将变量分隔成逻辑部分。建议您在 SpinalHDL "
+"中使用 ``Area`` 代替它。"
+
+#: ../../SpinalHDL/Structuring/area.rst:44
+msgid ""
+"\\ :ref:`ClockingArea <clock_domain>` is a special kind of ``Area`` that "
+"allows you to define chunks of hardware which use a given ``ClockDomain``\\"
+msgstr ""
+"\\ :ref:`ClockingArea <clock_domain>` 是一种特殊的 ``Area`` ，"
+"它允许您在该硬件块中缺省使用指定的 ``ClockDomain`` 时钟域\\"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po
new file mode 100644
index 00000000000..8078b9838ba
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po
@@ -0,0 +1,223 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-19 09:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringblackbox/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:4
+msgid "Instantiate VHDL and Verilog IP"
+msgstr "实例化 VHDL 和 Verilog IP"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:7
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:9
+msgid ""
+"A blackbox allows the user to integrate an existing VHDL/Verilog component "
+"into the design by just specifying its interfaces. It's up to the simulator "
+"or synthesizer to do the elaboration correctly."
+msgstr "黑盒允许用户通过指定其接口将现有的 VHDL/Verilog "
+"组件集成到设计中。正确地进行实力细化取决于仿真器或综合器。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:13
+msgid "Defining an blackbox"
+msgstr "定义一个黑盒"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:15
+msgid "An example of how to define a blackbox is shown below:"
+msgstr "下面示例显示了定义黑盒的方法："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:46
+msgid ""
+"In VHDL, signals of type ``Bool`` will be translated into ``std_logic`` and "
+"``Bits`` into ``std_logic_vector``. If you want to get ``std_ulogic``, you "
+"have to use a ``BlackBoxULogic`` instead of ``BlackBox``."
+msgstr ""
+"在 VHDL 中， ``Bool`` 类型的信号将被转换为 ``std_logic`` ， ``Bits`` "
+"将被转换为 ``std_logic_vector``。如果你想获得 ``std_ulogic``，你必须使用 "
+"``BlackBoxULogic`` 而不是 ``BlackBox``。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:47
+msgid "In Verilog, ``BlackBoxUlogic`` does not change the generated verilog."
+msgstr "在 Verilog 中，``BlackBoxUlogic`` 不会更改生成的 Verilog。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:56
+msgid "Generics"
+msgstr "泛型"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:58
+msgid "There are two different ways to declare generics:"
+msgstr "有两种不同的方式来声明泛型："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:75
+msgid "Instantiating a blackbox"
+msgstr "实例化黑盒"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:77
+msgid ""
+"Instantiating a ``BlackBox`` is just like instantiating a ``Component``:"
+msgstr "实例化一个 ``BlackBox`` 就像实例化一个 ``Component`` 一样："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:115
+msgid "Clock and reset mapping"
+msgstr "时钟和复位信号的映射"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:117
+msgid ""
+"In your blackbox definition you have to explicitly define clock and reset "
+"wires. To map signals of a ``ClockDomain`` to corresponding inputs of the "
+"blackbox you can use the ``mapClockDomain`` or ``mapCurrentClockDomain`` "
+"function. ``mapClockDomain`` has the following parameters:"
+msgstr ""
+"在黑盒定义中，您必须明确定义时钟和复位线。要将 ``ClockDomain`` "
+"的信号映射到黑盒的相应输入，您可以使用 ``mapClockDomain`` 或 "
+"``mapCurrentClockDomain`` 函数。 ``mapClockDomain`` 具有以下参数："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:123
+msgid "name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:124
+msgid "type"
+msgstr "类型"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:125
+msgid "default"
+msgstr "缺省值"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:126
+msgid "description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:127
+msgid "clockDomain"
+msgstr "clockDomain"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:128
+msgid "ClockDomain"
+msgstr "ClockDomain"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:129
+msgid "ClockDomain.current"
+msgstr "ClockDomain.current"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:130
+msgid "Specify the clockDomain which provides the signals"
+msgstr "指定提供信号的clockDomain"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:131
+msgid "clock"
+msgstr "时钟"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:132
+#: ../../SpinalHDL/Structuring/blackbox.rst:136
+#: ../../SpinalHDL/Structuring/blackbox.rst:140
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:133
+#: ../../SpinalHDL/Structuring/blackbox.rst:137
+#: ../../SpinalHDL/Structuring/blackbox.rst:141
+msgid "Nothing"
+msgstr "Nothing"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:134
+msgid "Blackbox input which should be connected to the clockDomain clock"
+msgstr "应连接到clockDomain时钟的黑盒输入"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:135
+msgid "reset"
+msgstr "reset"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:138
+msgid "Blackbox input which should be connected to the clockDomain reset"
+msgstr "黑盒输入应连接到时钟域的复位信号"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:139
+msgid "enable"
+msgstr "enable"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:142
+msgid "Blackbox input which should be connected to the clockDomain enable"
+msgstr "黑盒输入应连接到时钟域的使能信号"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:145
+msgid ""
+"``mapCurrentClockDomain`` has almost the same parameters as "
+"``mapClockDomain`` but without the clockDomain."
+msgstr "``mapCurrentClockDomain`` 具有与 ``mapClockDomain`` "
+"几乎相同的参数，但没有时钟域。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:147
+msgid "For example:"
+msgstr "例如："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:167
+msgid "io prefix"
+msgstr "io前缀"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:169
+msgid ""
+"In order to avoid the prefix \"io\\_\" on each of the IOs of the blackbox, "
+"you can use the function ``noIoPrefix()`` as shown below :"
+msgstr "为了避免黑盒的每个 IO 上都有前缀 \"io\\_\" ，可以使用函数 ``noIoPrefix()`` "
+"，如下所示："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:202
+msgid "Rename all io of a blackbox"
+msgstr "重命名黑盒中的所有io"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:204
+msgid ""
+"IOs of a ``BlackBox`` or ``Component`` can be renamed at compile-time using "
+"the ``addPrePopTask`` function. This function takes a no-argument function "
+"to be applied during compilation, and is useful for adding renaming passes, "
+"as shown in the following example:"
+msgstr ""
+"``BlackBox`` 或 ``Component`` 的 IO 可以在编译时使用 ``addPrePopTask`` 函数重"
+"命名。此函数在编译期间调用一个无参数函数，对于添加重命名通道非常有用，如下所"
+"示："
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:251
+msgid "Add RTL source"
+msgstr "添加 RTL 源"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:253
+msgid ""
+"With the function ``addRTLPath()`` you can associate your RTL sources with "
+"the blackbox. After the generation of your SpinalHDL code you can call the "
+"function ``mergeRTLSource`` to merge all of the sources together."
+msgstr ""
+"使用函数 ``addRTLPath()`` ，您可以将 RTL 源与黑盒关联起来。生成 SpinalHDL "
+"代码后，您可以调用函数 ``mergeRTLSource`` 将所有源合并在一起。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:291
+msgid "VHDL - No numeric type"
+msgstr "VHDL - 无数值类型"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:293
+msgid ""
+"If you want to use only ``std_logic_vector`` in your blackbox component, you"
+" can add the tag ``noNumericType`` to the blackbox."
+msgstr "如果您只想在黑盒组件中使用 ``std_logic_vector`` ，则可以将标签 "
+"``noNumericType`` 添加到黑盒中。"
+
+#: ../../SpinalHDL/Structuring/blackbox.rst:312
+msgid "The code above will generate the following VHDL:"
+msgstr "上面的代码将生成以下 VHDL："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po
new file mode 100644
index 00000000000..9f25d83beee
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po
@@ -0,0 +1,629 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: 2024-01-26 17:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringclock_domain/zh_Hans/>\n"
+"Language: zh_CN\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+"Generated-By: Babel 2.14.0\n"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:4
+msgid "Clock domains"
+msgstr "时钟域"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:7
+msgid "Introduction"
+msgstr "简介"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:9
+msgid ""
+"In SpinalHDL, clock and reset signals can be combined to create a **clock"
+" domain**. Clock domains can be applied to some areas of the design and "
+"then all synchronous elements instantiated into those areas will then "
+"**implicitly** use this clock domain."
+msgstr ""
+"在 SpinalHDL "
+"中，时钟和复位信号可以组合起来创建**时钟域**。时钟域可以应用于设计的某些区域，然后实例化到这些区域中的所有同步元件将**隐式**使用该时钟域。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:11
+msgid ""
+"Clock domain application works like a stack, which means that if you are "
+"in a given clock domain you can still apply another clock domain locally."
+msgstr "时钟域的应用方式类似于堆栈，这意味着当您的设计位于给定时钟域中，您仍然可以将该设计应用到另一个时钟域。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:13
+msgid ""
+"Please note that a register captures its clock domain when the register "
+"is created, not when it is assigned. So please make sure to create them "
+"inside the desired ``ClockingArea``."
+msgstr "请注意，寄存器在创建时捕获其时钟域，而不是在赋值时捕获。因此，请确保在所需的 ``ClockingArea`` 内创建它们。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:18
+msgid "Instantiation"
+msgstr "实例化"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:20
+msgid "The syntax to define a clock domain is as follows (using EBNF syntax):"
+msgstr "定义时钟域的语法如下（使用EBNF语法）："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:33
+msgid "This definition takes five parameters:"
+msgstr "这个定义有五个参数："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:39
+#: ../../SpinalHDL/Structuring/clock_domain.rst:196
+msgid "Argument"
+msgstr "参数"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:40
+#: ../../SpinalHDL/Structuring/clock_domain.rst:197
+#: ../../SpinalHDL/Structuring/clock_domain.rst:338
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:41
+#: ../../SpinalHDL/Structuring/clock_domain.rst:198
+msgid "Default"
+msgstr "默认值"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:42
+msgid "``clock``"
+msgstr "``clock``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:43
+msgid "Clock signal that defines the domain"
+msgstr "定义时钟域中的时钟信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:45
+msgid "``reset``"
+msgstr "``reset``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:46
+msgid ""
+"Reset signal. If a register exists which needs a reset and the clock "
+"domain doesn't provide one, an error message will be displayed"
+msgstr "复位信号。如果存在需要复位的寄存器，而时钟域没有提供复位，则会显示错误消息"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:47
+#: ../../SpinalHDL/Structuring/clock_domain.rst:50
+#: ../../SpinalHDL/Structuring/clock_domain.rst:53
+msgid "null"
+msgstr "null"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:48
+msgid "``softReset``"
+msgstr "``softReset``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:49
+msgid "Reset which infers an additional synchronous reset"
+msgstr "复位意味着额外的同步复位"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:51
+msgid "``clockEnable``"
+msgstr "``clockEnable``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:52
+msgid ""
+"The goal of this signal is to disable the clock on the whole clock domain"
+" without having to manually implement that on each synchronous element"
+msgstr "该信号的目标是禁用整个时钟域上的时钟，而无需在每个同步元件上手动实现"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:54
+#: ../../SpinalHDL/Structuring/clock_domain.rst:214
+msgid "``frequency``"
+msgstr "``frequency``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:55
+msgid ""
+"Allows you to specify the frequency of the given clock domain and later "
+"read it in your design. This parameter does not generate and PLL or other"
+" hardware to control the frequency"
+msgstr "允许您指定给定时钟域的频率，然后在您的设计中读取它。该参数不生成PLL或其他硬件来控制频率"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:57
+#: ../../SpinalHDL/Structuring/clock_domain.rst:216
+msgid "UnknownFrequency"
+msgstr "UnknownFrequency"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:58
+#: ../../SpinalHDL/Structuring/clock_domain.rst:202
+msgid "``config``"
+msgstr "``config``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:59
+msgid "Specify the polarity of signals and the nature of the reset"
+msgstr "指定信号的极性和复位的性质"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:60
+#: ../../SpinalHDL/Structuring/clock_domain.rst:204
+msgid "Current config"
+msgstr "当前配置"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:63
+msgid ""
+"An applied example to define a specific clock domain within the design is"
+" as follows:"
+msgstr "在设计中定义具有指定属性时钟域的示例如下："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:78
+msgid ""
+"When an `Area` is not needed, it is also possible to apply the clock "
+"domain directly. Two syntaxes exist:"
+msgstr "当不需要 `Area` 时，也可以直接应用时钟域。存在两种语法："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:105
+msgid "Configuration"
+msgstr "配置"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:107
+msgid ""
+"In addition to :ref:`constructor parameters "
+"<clock_domain_instantiation>`\\ , the following elements of each clock "
+"domain are configurable via a ``ClockDomainConfig``\\ class:"
+msgstr ""
+"除了 :ref:`构造函数参数 <clock_domain_instantiation>`\\ 之外，每个时钟域的以下元素都可以通过 "
+"``ClockDomainConfig``\\ 类进行配置："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:113
+msgid "Property"
+msgstr "属性"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:114
+msgid "Valid values"
+msgstr "有效值"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:115
+msgid "``clockEdge``"
+msgstr "``clockEdge``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:116
+msgid "``RISING``\\ , ``FALLING``"
+msgstr "``RISING``\\ , ``FALLING``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:117
+msgid "``resetKind``"
+msgstr "``resetKind``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:118
+msgid ""
+"``ASYNC``\\ , ``SYNC``\\ , and ``BOOT`` which is supported by some FPGAs "
+"(where FF values are loaded by the bitstream)"
+msgstr "某些 FPGA 支持的 ``ASYNC``\\ 、 ``SYNC``\\ 和 ``BOOT`` （其中 FF 值由比特流加载）"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:119
+msgid "``resetActiveLevel``"
+msgstr "``resetActiveLevel``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:120
+#: ../../SpinalHDL/Structuring/clock_domain.rst:122
+#: ../../SpinalHDL/Structuring/clock_domain.rst:124
+msgid "``HIGH``\\ , ``LOW``"
+msgstr "``HIGH``\\ , ``LOW``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:121
+msgid "``softResetActiveLevel``"
+msgstr "``softResetActiveLevel``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:123
+msgid "``clockEnableActiveLevel``"
+msgstr "``clockEnableActiveLevel``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:157
+msgid ""
+"By default, a ``ClockDomain`` is applied to the whole design. The "
+"configuration of this default domain is:"
+msgstr "默认情况下， ``ClockDomain`` 应用于整个设计。该默认域的配置为："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:160
+msgid "Clock : rising edge"
+msgstr "Clock：上升沿"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:161
+msgid "Reset : asynchronous, active high"
+msgstr "Reset ：异步，高电平有效"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:162
+msgid "No clock enable"
+msgstr "无时钟使能"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:164
+msgid "This corresponds to the following ``ClockDomainConfig``:"
+msgstr "这对应于以下 ``ClockDomainConfig``："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:175
+msgid "Internal clock"
+msgstr "内部时钟"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:177
+msgid "An alternative syntax to create a clock domain is the following:"
+msgstr "另一种创建时钟域的语法如下："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:190
+msgid "This definition takes six parameters:"
+msgstr "该定义有六个参数："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:199
+msgid "``name``"
+msgstr "``name``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:200
+msgid "Name of `clk` and `reset` signal"
+msgstr "`clk` 和 `reset` 信号的名称"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:203
+msgid "Specify polarity of signals and the nature of the reset"
+msgstr "指定信号的极性和复位的性质"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:205
+msgid "``withReset``"
+msgstr "``withReset``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:206
+msgid "Add a reset signal"
+msgstr "添加复位信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:207
+msgid "true"
+msgstr "true"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:208
+msgid "``withSoftReset``"
+msgstr "``withSoftReset``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:209
+msgid "Add a soft reset signal"
+msgstr "添加软复位信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:210
+#: ../../SpinalHDL/Structuring/clock_domain.rst:213
+msgid "false"
+msgstr "false"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:211
+msgid "``withClockEnable``"
+msgstr "``withClockEnable``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:212
+msgid "Add a clock enable"
+msgstr "添加时钟使能"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:215
+msgid "Frequency of the clock domain"
+msgstr "时钟域频率"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:219
+msgid ""
+"The advantage of this approach is to create clock and reset signals with "
+"a known/specified name instead of an inherited one."
+msgstr "这种方法的优点是使用已知/指定的名称而不是继承的名称来创建时钟和复位信号。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:221
+msgid ""
+"Once created, you have to assign the ``ClockDomain``'s signals, as shown "
+"in the example below:"
+msgstr "创建后，您必须分配 ``ClockDomain`` 的信号，如下例所示："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:253
+msgid ""
+"In other components then the one you created the ClockDomain in, you must"
+" not use ``.clock`` and ``.reset``, but ``.readClockWire`` and "
+"``.readResetWire`` as listed below. For the global ClockDomain you must "
+"always use those ``.readXXX`` functions."
+msgstr ""
+"在您创建时钟域的其他组件中，您不得使用 ``.clock`` 和 ``.reset``，而应使用 ``.readClockWire`` 和 "
+"``.readResetWire`` ，如下所示。对于全局时钟域，您必须始终使用这些 ``.readXXX`` 函数。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:259
+msgid "External clock"
+msgstr "外部时钟"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:261
+msgid ""
+"You can define a clock domain which is driven by the outside anywhere in "
+"your source. It will then automatically add clock and reset wires from "
+"the top level inputs to all synchronous elements."
+msgstr "您可以在源中的任何位置定义由外部驱动的时钟域。然后，它会自动将时钟和复位线从顶层输入添加到所有同步元件。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:274
+msgid ""
+"The arguments to the ``ClockDomain.external`` function are exactly the "
+"same as in the ``ClockDomain.internal`` function. Below is an example of "
+"a design using ``ClockDomain.external``:"
+msgstr ""
+"``ClockDomain.external`` 函数的参数与 ``ClockDomain.internal`` 函数中的参数完全相同。下面是使用"
+" ``ClockDomain.external`` 的设计示例："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:296
+msgid "Signal priorities in HDL generation"
+msgstr "生成 HDL 时的信号优先级"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:298
+msgid ""
+"In the current version, reset and clock enable signals have different "
+"priorities. Their order is : ``asyncReset``, ``clockEnable``, "
+"``syncReset`` and ``softReset``."
+msgstr ""
+"在当前版本中，复位和时钟使能信号具有不同的优先级。它们的顺序是： ``asyncReset``, ``clockEnable``, "
+"``syncReset`` 和 ``softReset``。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:300
+msgid ""
+"Please be careful that clockEnable has a higher priority than syncReset. "
+"If you do a sync reset when the clockEnable is disabled (especially at "
+"the beginning of a simulation), the gated registers will not be reseted."
+msgstr ""
+"请注意，clockEnable "
+"的优先级高于syncReset。如果在禁用clockEnable（尤其是在仿真开始时）时执行同步重置，则门控寄存器将不会重置。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:302
+msgid "Here is an example:"
+msgstr "这是一个例子："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:310
+msgid "It will generate VerilogHDL codes like:"
+msgstr "它将生成 Verilog HDL 代码，例如："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:324
+msgid ""
+"If that behaviour is problematic, one workaround is to use a when "
+"statement as a clock enable instead of using the ClockDomain.enable "
+"feature. This is open for future improvements."
+msgstr "如果该行为有问题，一种解决方法是使用when 语句作为时钟使能，而不是使用ClockDomain.enable 功能。这对于未来的改进是开放的。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:327
+msgid "Context"
+msgstr "语境"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:329
+msgid ""
+"You can retrieve in which clock domain you are by calling "
+"``ClockDomain.current`` anywhere."
+msgstr "您可以通过在任何地方调用 ``ClockDomain.current`` 来检索您所在的时钟域。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:331
+msgid ""
+"The returned ``ClockDomain`` instance has the following functions that "
+"can be called:"
+msgstr "返回的 ``ClockDomain`` 实例具有以下可以调用的函数："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:337
+msgid "name"
+msgstr "名称"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:339
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:340
+msgid "frequency.getValue"
+msgstr "frequency.getValue"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst
+msgid "Return the frequency of the clock domain."
+msgstr "返回时钟域的频率。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst
+msgid "This being the arbitrary value you configured the domain with."
+msgstr "这是您配置域的任意值。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:343
+msgid "Double"
+msgstr "Double"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:344
+msgid "hasReset"
+msgstr "hasReset"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:345
+msgid "Return if the clock domain has a reset signal"
+msgstr "如果时钟域有复位信号则返回"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:346
+#: ../../SpinalHDL/Structuring/clock_domain.rst:349
+#: ../../SpinalHDL/Structuring/clock_domain.rst:352
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:347
+msgid "hasSoftReset"
+msgstr "hasSoftReset"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:348
+msgid "Return if the clock domain has a soft reset signal"
+msgstr "返回时钟域是否有软复位信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:350
+msgid "hasClockEnable"
+msgstr "hasClockEnable"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:351
+msgid "Return if the clock domain has a clock enable signal"
+msgstr "返回时钟域是否有时钟使能信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:353
+msgid "readClockWire"
+msgstr "readClockWire"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:354
+msgid "Return a signal derived from the clock signal"
+msgstr "返回从时钟信号派生的信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:355
+#: ../../SpinalHDL/Structuring/clock_domain.rst:358
+#: ../../SpinalHDL/Structuring/clock_domain.rst:361
+#: ../../SpinalHDL/Structuring/clock_domain.rst:364
+#: ../../SpinalHDL/Structuring/clock_domain.rst:367
+#: ../../SpinalHDL/Structuring/clock_domain.rst:370
+#: ../../SpinalHDL/Structuring/clock_domain.rst:373
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:356
+msgid "readResetWire"
+msgstr "readResetWire"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:357
+msgid "Return a signal derived from the reset signal"
+msgstr "返回一个从复位信号派生的信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:359
+msgid "readSoftResetWire"
+msgstr "readSoftResetWire"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:360
+msgid "Return a signal derived from the soft reset signal"
+msgstr "返回从软复位信号派生的信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:362
+msgid "readClockEnableWire"
+msgstr "readClockEnableWire"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:363
+msgid "Return a signal derived from the clock enable signal"
+msgstr "返回从时钟使能信号派生的信号"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:365
+msgid "isResetActive"
+msgstr "isResetActive"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:366
+msgid "Return True when the reset is active"
+msgstr "当复位有效时返回 True"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:368
+msgid "isSoftResetActive"
+msgstr "isSoftResetActive"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:369
+msgid "Return True when the soft reset is active"
+msgstr "当软复位有效时返回 True"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:371
+msgid "isClockEnableActive"
+msgstr "isClockEnableActive"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:372
+msgid "Return True when the clock enable is active"
+msgstr "当时钟使能有效时返回 True"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:375
+msgid ""
+"An example is included below where a UART controller uses the frequency "
+"specification to set its clock divider:"
+msgstr "下面包含一个示例，其中通过 UART 控制器使用频率来设置其时钟分频器："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:387
+msgid "Clock domain crossing"
+msgstr "跨时钟域设计"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:389
+msgid ""
+"SpinalHDL checks at compile time that there are no unwanted/unspecified "
+"cross clock domain signal reads. If you want to read a signal that is "
+"emitted by another ``ClockDomain`` area, you should add the "
+"``crossClockDomain`` tag to the destination signal as depicted in the "
+"following example:"
+msgstr ""
+"SpinalHDL 在编译时检查是否存在不需要的/未指定的跨时钟域信号读取。如果您想读取另一个 ``ClockDomain`` "
+"逻辑区发出的信号，则应给目标信号增加 ``crossClockDomain`` 标记，如下例所示："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:451
+msgid ""
+"In general, you can use 2 or more flip-flop driven by the destination "
+"clock domain to prevent metastability. The ``BufferCC(input: T, init: T ="
+" null, bufferDepth: Int = 2)`` function provided in ``spinal.lib._`` will"
+" instantiate the necessary flip-flops (the number of flip-flops will "
+"depends on the ``bufferDepth`` parameter) to mitigate the phenomena."
+msgstr ""
+"一般来说，可以使用2个或更多由目标时钟域驱动的触发器来防止亚稳态。 ``spinal.lib._`` 中提供的 ``BufferCC(input:"
+" T, init: T = null, bufferDepth: Int = 2)`` 函数将实例化必要的触发器（触发器的数量将取决于 "
+"``bufferDepth`` 参数）来减轻这种现象。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:475
+msgid ""
+"The ``BufferCC`` function is only for signals of type ``Bit``, or "
+"``Bits`` operating as Gray-coded counters (only 1 bit-flip per clock "
+"cycle), and can not used for multi-bit cross-domain processes. For multi-"
+"bit cases, it is recommended to use ``StreamFifoCC`` for high bandwidth "
+"requirements, or use ``StreamCCByToggle`` to reduce resource usage in "
+"cases where bandwidth is not critical."
+msgstr ""
+"``BufferCC`` 函数仅适用于 ``Bit`` 类型的信号，或作为格雷编码计数器运行的 ``Bits`` 信号（每个时钟周期仅翻转 1 "
+"位），并且不能用于多位跨时钟域信号。对于多位情况，建议使用 ``StreamFifoCC`` 来满足高带宽要求，或者在带宽要求不高的情况下使用 "
+"``StreamCCByToggle`` 来减少资源使用。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:478
+msgid "Special clocking Areas"
+msgstr "特殊计时逻辑区"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:481
+msgid "Slow Area"
+msgstr "慢时钟逻辑区"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:483
+msgid ""
+"A ``SlowArea`` is used to create a new clock domain area which is slower "
+"than the current one:"
+msgstr "``SlowArea`` 用于创建一个逻辑区，使用比当前时钟域慢的新时钟域："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:512
+msgid ""
+"The clock signal used in a SlowArea is the same as the parent one. The "
+"SlowArea add instead a clock-enable signal that will slow down the "
+"sampling rate inside it. In other words, "
+"``ClockDomain.current.readClockWire`` will return the fast (parent "
+"domain) clock. To obtain the clock enable, use "
+"``ClockDomain.current.readClockEnableWire``"
+msgstr ""
+"SlowArea 中使用的时钟信号与父区域相同。而 SlowArea "
+"会添加一个时钟启用信号，以减慢其内部的采样率。换句话说，``ClockDomain.current"
+".readClockWire`` 将返回快速（父域）时钟。要获取时钟使能信号，请使用 "
+"``ClockDomain.current.readClockEnableWire``"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:517
+msgid "BootReset"
+msgstr "启动复位"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:519
+msgid ""
+"`clockDomain.withBootReset()` could specify register's resetKind as BOOT."
+" `clockDomain.withSyncReset()` could specify register's resetKind as SYNC"
+" (sync-reset)."
+msgstr ""
+"`clockDomain.withBootReset()` 可以指定寄存器的resetKind为BOOT。 "
+"`clockDomain.withSyncReset()` 可以指定寄存器的resetKind为SYNC（同步复位）。"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:537
+msgid "ResetArea"
+msgstr "复位时钟域"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:539
+msgid ""
+"A ``ResetArea`` is used to create a new clock domain area where a special"
+" reset signal is combined with the current clock domain reset:"
+msgstr "``ResetArea`` 用于创建一个新的时钟域区域，其使用指定的复位信号与当前时钟域复位相结合进行复位·："
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:559
+msgid "ClockEnableArea"
+msgstr "时钟使能逻辑区"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:561
+msgid ""
+"A ``ClockEnableArea`` is used to add an additional clock enable in the "
+"current clock domain:"
+msgstr "``ClockEnableArea`` 用于在当前时钟域中添加额外的时钟使能信号："
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po
new file mode 100644
index 00000000000..bcb8402f256
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po
@@ -0,0 +1,267 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringcomponents_hierarchy/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:4
+msgid "Components and hierarchy"
+msgstr "组件和层次结构"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:6
+msgid ""
+"Like in VHDL and Verilog, you can define components that can be used to "
+"build a design hierarchy. However, in SpinalHDL, you don't need to bind "
+"their ports at instantiation:"
+msgstr "像在VHDL和Verilog中一样，可以使用组件构建设计层次结构。然而，在SpinalHDL中，"
+"不需要在实例化时绑定它们的端口："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``val io = new Bundle { ... }``"
+msgstr "``val io = new Bundle { ... }``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid ""
+"Declaring external ports in a ``Bundle`` called ``io`` is recommended. If "
+"you name your bundle ``io``, SpinalHDL will check that all of its elements "
+"are defined as inputs or outputs."
+msgstr ""
+"建议在名为 ``io`` 的 ``Bundle`` 中声明外部端口。如果您将线束命名为 ``io``，"
+"SpinalHDL 将检查其所有元素是否定义为输入或输出。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:41
+msgid ""
+"If it is better to your taste, you can use the ``Module`` syntax instead of "
+"``Component`` (they are the same thing)"
+msgstr "如果更符合您的风格，您也可以使用 ``Module`` 语法而不是 ``Component`` "
+"（它们是相同的东西）"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:47
+msgid "Input / output definition"
+msgstr "输入/输出定义"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:49
+msgid "The syntax to define inputs and outputs is as follows:"
+msgstr "定义输入和输出的语法如下："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:55
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:56
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:57
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``in port Bool()``"
+msgstr "``in port Bool()``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``out port Bool()``"
+msgstr "``out port Bool()``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:60
+msgid "Create an input Bool/output Bool"
+msgstr "创建输入 Bool/输出 Bool"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:61
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``in Bits/UInt/SInt[(x bits)]``"
+msgstr "``in Bits/UInt/SInt[(x bits)]``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``out Bits/UInt/SInt[(x bits)]``"
+msgstr "``out Bits/UInt/SInt[(x bits)]``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``in Bits(3 bits)``"
+msgstr "``in Bits(3 bits)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:65
+msgid "Create an input/output of the corresponding type"
+msgstr "创建相应类型的输入/输出端口"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:66
+msgid "Bits/UInt/SInt"
+msgstr "Bits/UInt/SInt"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``in(T)``"
+msgstr "``in(T)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``out(T)``"
+msgstr "``out(T)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``out UInt(7 bits)``"
+msgstr "``out UInt(7 bits)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:70
+msgid ""
+"For all other data types, you may have to add some brackets around it. "
+"Sorry, this is a Scala limitation."
+msgstr "对于所有其他数据类型，您可能需要在其周围添加一些括号。这是 Scala 的限制。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:71
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:77
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``master(T)``"
+msgstr "``master(T)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``slave(T)``"
+msgstr "``slave(T)``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst
+msgid "``master(Bool())``"
+msgstr "``master(Bool())``"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:75
+msgid ""
+"This syntax is provided by the ``spinal.lib`` library (If you annotate your "
+"object with the ``slave`` syntax, then import ``spinal.lib.slave`` instead)."
+" T must extend ``IMasterSlave``. Some documentation is available :ref:`here "
+"<interface_example_apb>`. You may not actually need the brackets, so "
+"``master T`` is fine as well."
+msgstr ""
+"此语法由 ``spinal.lib`` 库提供（如果您使用 ``slave`` 语法标注对象，则应导入 "
+"``spinal.lib.slave``）。 T 必须继承自 ``IMasterSlave``。一些参考文档在 :ref:`"
+"这里 <interface_example_apb>` 。您实际上可能不需要括号，因此写成 ``master T``"
+" 也可以。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:80
+msgid "There are some rules to follow with component interconnection:"
+msgstr "组件之间的互连需要遵循一些规则："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:83
+msgid ""
+"Components can only **read** output and input signals of child components."
+msgstr "组件只能 **读取** 子组件的输出和输入信号。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:84
+msgid "Components can read their own output port values (unlike in VHDL)."
+msgstr "组件可以读取自己的输出端口值（与 VHDL 不同）。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:87
+msgid ""
+"If for some reason you need to read signals from far away in the hierarchy "
+"(such as for debugging or temporal patches), you can do it by using the "
+"value returned by ``some.where.else.theSignal.pull()``"
+msgstr ""
+"如果由于某种原因您需要从层次结构中较深的位置读取信号（例如用于调试或临时补丁"
+"），您可以使用 ``some.where.else.theSignal.pull()`` "
+"函数返回的信号来完成此操作"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:91
+msgid "Pruned signals"
+msgstr "裁剪信号"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:93
+msgid ""
+"SpinalHDL will generate all the named signals and their depedencies, while "
+"all the useless anonymous / zero width ones are removed from the RTL "
+"generation."
+msgstr "SpinalHDL 将生成所有命名信号及其依赖性，而所有无用的匿名/零位宽信号将从 RTL "
+"生成中删除。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:96
+msgid ""
+"You can collect the list of all the removed ans useless signals via the "
+"``printPruned`` and the ``printPrunedIo`` functions on the generated "
+"``SpinalReport`` object:"
+msgstr ""
+"您可以通过生成的 ``SpinalReport`` 对象上的 ``printPruned`` 和 "
+"``printPrunedIo`` 函数收集所有已删除的无用信号列表："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:126
+msgid "Parametrized Hardware (\"Generic\" in VHDL, \"Parameter\" in Verilog)"
+msgstr "参数化硬件（VHDL 中的“Generic”，Verilog 中的“Parameter”）"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:128
+msgid ""
+"If you want to parameterize your component, you can give parameters to the "
+"constructor of the component as follows:"
+msgstr "如果你想参数化你的组件，你可以将参数传递给组件的构造函数，如下所示："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:146
+msgid ""
+"If you have several parameters, it is a good practice to give a specific "
+"configuration class as follows:"
+msgstr "如果您有多个参数，最好给出一个专用的配置类，如下所示："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:159
+msgid ""
+"You can add functions inside the config, along with requirements on the "
+"config attributes:"
+msgstr "您可以在配置中添加功能以及对配置属性的要求："
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:173
+msgid ""
+"This parametrization occurs entirely within the SpinalHDL code-generation "
+"during elaboration.  This generates non-generic HDL code. The methods "
+"described here do not use VHDL generics or Verilog parameters."
+msgstr ""
+"这种参数化完全发生在 SpinalHDL 代码生成的实例细化过程中。生成的 HDL "
+"代码不包含使用HDL语言泛化特性的内容。此处描述的方法不会使用 VHDL 泛型或 "
+"Verilog 参数。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:177
+msgid ""
+"See also :ref:`Blackbox <blackbox>` for more information around support for "
+"that mechanism."
+msgstr "另请参阅 :ref:`Blackbox <blackbox>` 了解有关该机制支持的更多信息。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:182
+msgid "Synthesized component names"
+msgstr "综合后组件名称"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:184
+msgid ""
+"Within a module, each component has a name, called a \"partial name\". The "
+"\"full\" name is built by joining every component's parent name with \"_\", "
+"for example: ``io_clockDomain_reset``. You can use ``setName`` to replace "
+"this convention with a custom name. This is especially useful when "
+"interfacing with external components. The other methods are called "
+"``getName``, ``setPartialName``, and ``getPartialName`` respectively."
+msgstr ""
+"在模块内，每个组件都有一个名称，称为“部分名称”。 “完整”名称是通过将每个组件的"
+"父名称与“_”连接起来构建的，例如：``io_clockDomain_reset``。您可以使用 "
+"``setName`` "
+"将按此约定生成的名称替换为自定义的。这在与外部组件连接时特别有用。"
+"其他方法分别称为 ``getName``、``setPartialName`` 和 ``getPartialName``。"
+
+#: ../../SpinalHDL/Structuring/components_hierarchy.rst:190
+msgid ""
+"When synthesized, each module gets the name of the Scala class defining it. "
+"You can override this as well with ``setDefinitionName``."
+msgstr "综合时，每个模块都会获得定义它的 Scala 类的名称。您也可以调用 "
+"``setDefinitionName`` 函数来覆盖它。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/function.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/function.po
new file mode 100644
index 00000000000..0c6872031f3
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/function.po
@@ -0,0 +1,80 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringfunction/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/function.rst:4
+msgid "Function"
+msgstr "函数"
+
+#: ../../SpinalHDL/Structuring/function.rst:6
+msgid ""
+"The ways you can use Scala functions to generate hardware are radically "
+"different than VHDL/Verilog for many reasons:"
+msgstr "使用 Scala 函数生成硬件的方式与 VHDL/Verilog 完全不同，原因有很多："
+
+#: ../../SpinalHDL/Structuring/function.rst:8
+msgid ""
+"You can instantiate registers, combinational logic, and components inside "
+"them."
+msgstr "您可以实例化寄存器、组合逻辑以及其中的组件。"
+
+#: ../../SpinalHDL/Structuring/function.rst:9
+msgid ""
+"You don't have to play with ``process``\\ /\\ ``@always`` blocks that limit "
+"the scope of assignment of signals."
+msgstr "您不必使用限制信号赋值范围的 ``process``\\ /\\ ``@always`` 块。"
+
+#: ../../SpinalHDL/Structuring/function.rst
+msgid "Everything is passed by reference, which allows easy manipulation."
+msgstr "一切都通过引用传递，这允许简化操作。"
+
+#: ../../SpinalHDL/Structuring/function.rst
+msgid ""
+"For example, you can give a bus to a function as an argument, then the "
+"function can internally read/write to it. You can also return a Component, a"
+" Bus, or anything else from Scala and the Scala world."
+msgstr ""
+"例如，您可以将总线作为参数提供给函数，然后该函数可以在内部对其进行读/写。"
+"您还可以从 Scala 世界（函数、类型等）返回组件、总线或任何其他内容。"
+
+#: ../../SpinalHDL/Structuring/function.rst:14
+msgid "RGB to gray"
+msgstr "RGB信号转灰度信号"
+
+#: ../../SpinalHDL/Structuring/function.rst:16
+msgid ""
+"For example, if you want to convert a Red/Green/Blue color into greyscale by"
+" using coefficients, you can use functions to apply them:"
+msgstr "例如，如果您想使用系数将红/绿/蓝颜色转换为灰度，您可以使用函数来完成："
+
+#: ../../SpinalHDL/Structuring/function.rst:30
+msgid "Valid Ready Payload bus"
+msgstr "Valid Ready Payload 总线"
+
+#: ../../SpinalHDL/Structuring/function.rst:32
+msgid ""
+"For instance, if you define a simple bus with ``valid``, ``ready``, and "
+"``payload`` signals, you can then define some useful functions inside of it."
+msgstr ""
+"例如，如果您定义一个带有 ``valid``, ``ready`` 和 ``payload`` "
+"信号的简单总线，则可以在其中定义一些有用的函数。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po
new file mode 100644
index 00000000000..914268904b1
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po
@@ -0,0 +1,48 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/index.rst:3
+msgid "Structuring"
+msgstr "结构设计"
+
+#: ../../SpinalHDL/Structuring/index.rst:5
+msgid "The chapters below explain:"
+msgstr "各章内容："
+
+#: ../../SpinalHDL/Structuring/index.rst:7
+msgid "how to build reusable components"
+msgstr "如何构建可重用的组件"
+
+#: ../../SpinalHDL/Structuring/index.rst:8
+msgid "alternatives to components to group hardware"
+msgstr "除组件外的其他硬件组合方法"
+
+#: ../../SpinalHDL/Structuring/index.rst:9
+msgid "handling of clock/reset domains"
+msgstr "时钟/复位域的处理"
+
+#: ../../SpinalHDL/Structuring/index.rst:10
+msgid "instantitation of existing VHDL and Verilog IP"
+msgstr "现有 VHDL 和 Verilog IP 的实例化"
+
+#: ../../SpinalHDL/Structuring/index.rst:11
+msgid "how names are assigned in SpinalHDL, and how naming can be influenced"
+msgstr "SpinalHDL 中如何为信号等分配名称，以及如何影响命名"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po
new file mode 100644
index 00000000000..98c7c3a59db
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po
@@ -0,0 +1,276 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringnaming/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/naming.rst:2
+msgid "Preserving names"
+msgstr "保留名称的方法"
+
+#: ../../SpinalHDL/Structuring/naming.rst:4
+msgid ""
+"This page will describe how SpinalHDL propagate names from the scala code to"
+" the generated hardware. Knowing them should enable you to preserve those "
+"names as much as possible to generate understandable netlists."
+msgstr ""
+"本页将描述 SpinalHDL 如何将名称从 scala 代码传播到生成的硬件 "
+"RTL。您应该了解它们，从而尽可能保留这些名称，以生成可理解的网表。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:7
+msgid "Nameable base class"
+msgstr "Nameable 基类"
+
+#: ../../SpinalHDL/Structuring/naming.rst:9
+msgid ""
+"All the things which can be named in SpinalHDL extends the Nameable base "
+"class which."
+msgstr "所有可以在 SpinalHDL 中命名的事物都扩展了 Nameable 基类。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:11
+msgid "So in practice, the following classes extends Nameable :"
+msgstr "因此在实践中，以下类扩展了 Nameable 类："
+
+#: ../../SpinalHDL/Structuring/naming.rst:13
+msgid "Component"
+msgstr "Component"
+
+#: ../../SpinalHDL/Structuring/naming.rst:14
+msgid "Area"
+msgstr "Area"
+
+#: ../../SpinalHDL/Structuring/naming.rst:15
+msgid "Data (UInt, SInt, Bundle, ...)"
+msgstr "Data (UInt, SInt, Bundle, ...)"
+
+#: ../../SpinalHDL/Structuring/naming.rst:18
+msgid "There is a few example of that Nameable API"
+msgstr "有一些 Nameable 类型 API 的示例"
+
+#: ../../SpinalHDL/Structuring/naming.rst:29
+msgid "Will generation :"
+msgstr "会生成："
+
+#: ../../SpinalHDL/Structuring/naming.rst:41
+msgid ""
+"In general, you don't realy need to access that API, unless you want to do "
+"tricky stuff for debug reasons or for elaboration purposes."
+msgstr "一般来说，您实际上并不需要访问该 "
+"API，除非您出于调试原因或出于详细说明的目的想要做一些精巧的工作。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:44
+msgid "Name extraction from Scala"
+msgstr "从 Scala 中提取名称"
+
+#: ../../SpinalHDL/Structuring/naming.rst:46
+msgid ""
+"First, since version 1.4.0, SpinalHDL use a scala compiler plugin which can "
+"provide a call back each time a new val is defined during the construction "
+"of an class."
+msgstr ""
+"首先，从 1.4.0 版本开始，SpinalHDL 使用 scala 编译器插件，"
+"该插件可以在类构造期间在每次定义新 val 时，实现函数回调。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:48
+msgid ""
+"There is a example showing more or less how SpinalHDL itself is implemented "
+":"
+msgstr "这个示例或多或少地展示了 SpinalHDL 本身是如何实现的："
+
+#: ../../SpinalHDL/Structuring/naming.rst:78
+msgid ""
+"Using that ValCallback \"introspection\" feature, SpinalHDL's Component "
+"classes are able to be aware of their content and the content's name."
+msgstr "使用 ValCallback“自省”功能，SpinalHDL 的组件类能够了解其内容和内容的名称。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:80
+msgid ""
+"But this also mean that if you want something to get a name, and you only "
+"rely on this automatic naming feature, the reference to your Data (UInt, "
+"SInt, ...) instances should be stored somewhere in a Component val."
+msgstr ""
+"但这也意味着，如果您希望某些东西获得名称，并且仅依赖于此自动命名功能，则对 "
+"Data (UInt、SInt、...) 实例的引用应存储在组件的某个 val 对象定义中。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:82
+msgid "For instance :"
+msgstr "例如 ："
+
+#: ../../SpinalHDL/Structuring/naming.rst:99
+#: ../../SpinalHDL/Structuring/naming.rst:197
+#: ../../SpinalHDL/Structuring/naming.rst:234
+msgid "Will generate :"
+msgstr "将生成："
+
+#: ../../SpinalHDL/Structuring/naming.rst:115
+msgid "Area in a Component"
+msgstr "组件中的区域"
+
+#: ../../SpinalHDL/Structuring/naming.rst:117
+msgid ""
+"One important aspect in the naming system is that you can define new "
+"namespaces inside components and manipulate"
+msgstr "命名系统的一个重要方面是您可以在组件内定义新的名称空间并进行操作"
+
+#: ../../SpinalHDL/Structuring/naming.rst:119
+msgid "For instance via Area :"
+msgstr "例如通过 Area ："
+
+#: ../../SpinalHDL/Structuring/naming.rst:130
+#: ../../SpinalHDL/Structuring/naming.rst:298
+#: ../../SpinalHDL/Structuring/naming.rst:383
+#: ../../SpinalHDL/Structuring/naming.rst:418
+#: ../../SpinalHDL/Structuring/naming.rst:467
+#: ../../SpinalHDL/Structuring/naming.rst:521
+msgid "Will generate"
+msgstr "会生成"
+
+#: ../../SpinalHDL/Structuring/naming.rst:145
+msgid "Area in a function"
+msgstr "函数中的逻辑区"
+
+#: ../../SpinalHDL/Structuring/naming.rst:147
+msgid ""
+"You can also define function which will create new Area which will provide a"
+" namespace for all its content :"
+msgstr "您还可以定义将创建新逻辑区的函数，该逻辑区将为其所有内容提供命名空间："
+
+#: ../../SpinalHDL/Structuring/naming.rst:163
+msgid "Which will generate :"
+msgstr "这将生成："
+
+#: ../../SpinalHDL/Structuring/naming.rst:179
+msgid "Composite in a function"
+msgstr "函数中的复合区（Composite）"
+
+#: ../../SpinalHDL/Structuring/naming.rst:181
+msgid ""
+"Added in SpinalHDL 1.5.0, Composite which allow you to create a scope which "
+"will use as prefix another Nameable:"
+msgstr "SpinalHDL 1.5.0 中添加了复合区，它允许您创建一个范围，该范围将用作另一个 "
+"Nameable 的前缀："
+
+#: ../../SpinalHDL/Structuring/naming.rst:213
+msgid "Composite chains"
+msgstr "复合区级联链"
+
+#: ../../SpinalHDL/Structuring/naming.rst:215
+msgid "You can also chain composites :"
+msgstr "您还可以级联复合区："
+
+#: ../../SpinalHDL/Structuring/naming.rst:252
+msgid "Composite in a Bundle's function"
+msgstr "在一个线束（Bundle）的函数中的复合区"
+
+#: ../../SpinalHDL/Structuring/naming.rst:255
+msgid ""
+"This behaviour can be very useful when implementing Bundle utilities. For "
+"instance in the spinal.lib.Stream class is defined the following :"
+msgstr "在实现线束工具时，此行为非常有用。例如，在 ``spin.lib.Stream`` 类中定义如下："
+
+#: ../../SpinalHDL/Structuring/naming.rst:288
+msgid "Which allow nested calls while preserving the names :"
+msgstr "这将允许嵌套调用，同时保留名称："
+
+#: ../../SpinalHDL/Structuring/naming.rst:363
+msgid "Unamed signal handling"
+msgstr "未命名信号处理"
+
+#: ../../SpinalHDL/Structuring/naming.rst:365
+msgid ""
+"Since 1.5.0, for signal which end up without name, SpinalHDL will find a "
+"signal which is driven by that unamed signal and propagate its name. This "
+"can produce useful results as long you don't have too large island of unamed"
+" stuff."
+msgstr ""
+"从 1.5.0 开始，对于最终没有名称的信号，SpinalHDL 将找到由该信号驱动的信号并传"
+"播其名称。只要您没有太多未命名的东西，这就可以产生有用的结果。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:367
+msgid ""
+"The name attributed to such unamed signal is : _zz_ + drivenSignal.getName()"
+msgstr "这种未命名信号的名称是：_zz_ +drivenSignal.getName()"
+
+#: ../../SpinalHDL/Structuring/naming.rst:369
+msgid ""
+"Note that this naming pattern is also used by the generation backend when "
+"they need to breakup some specific expressions or long chain of expression "
+"into multiple signals."
+msgstr "请注意，当生成后端需要将某些特定表达式或表达式链分解为多个信号时，也会使用此"
+"命名模式。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:372
+msgid "Verilog expression splitting"
+msgstr "Verilog 表达式分割"
+
+#: ../../SpinalHDL/Structuring/naming.rst:374
+msgid ""
+"There is an instance of expressions (ex : the + operator) that SpinalHDL "
+"need to express in dedicated signals to match the behaviour with the Scala "
+"API :"
+msgstr "下例中， SpinalHDL 需要使用指定信号描述一个表达式（例如：+ 运算符），"
+"以将其行为与 Scala API 相匹配："
+
+#: ../../SpinalHDL/Structuring/naming.rst:404
+msgid "Verilog long expression splitting"
+msgstr "Verilog 长表达式分割"
+
+#: ../../SpinalHDL/Structuring/naming.rst:406
+msgid ""
+"There is a instance of how a very long expression chain will be splited up "
+"by SpinalHDL :"
+msgstr "下例说明了 SpinalHDL 如何分割一个长表达式链："
+
+#: ../../SpinalHDL/Structuring/naming.rst:448
+msgid "When statement condition"
+msgstr "When 语句条件"
+
+#: ../../SpinalHDL/Structuring/naming.rst:450
+msgid ""
+"The `when(cond) { }` statements condition are generated into separated "
+"signals named `when_` + fileName + line. A similar thing will also be done "
+"for switch statements."
+msgstr ""
+"`when(cond) { }` 语句条件生成为名为 `when_` + fileName + line 的单独信号。 "
+"对 switch 语句也会做类似的事情。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:500
+msgid "In last resort"
+msgstr "最后一招"
+
+#: ../../SpinalHDL/Structuring/naming.rst:502
+msgid ""
+"In last resort, if a signal has no name (anonymous signal), SpinalHDL will "
+"seek for a named signal which is driven by the anonymous signal, and use it "
+"as a name postfix :"
+msgstr "最后，如果信号没有名称（匿名信号），SpinalHDL "
+"将寻找由匿名信号驱动的命名信号，并将其用作名称后缀："
+
+#: ../../SpinalHDL/Structuring/naming.rst:542
+msgid ""
+"This last resort naming skim isn't ideal in all cases, but can help out."
+msgstr "最后的命名方法并不适合所有情况，但可以提供帮助。"
+
+#: ../../SpinalHDL/Structuring/naming.rst:544
+msgid ""
+"Note that signal starting with a underscore aren't stored in the Verilator "
+"waves (on purpose)"
+msgstr "请注意，以下划线开头的信号不会存储在 Verilator 波形中（这是故意的）"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po
new file mode 100644
index 00000000000..c33a1b2f00f
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po
@@ -0,0 +1,259 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-24 15:57+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlstructuringparametrization/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:2
+msgid "Parametrization"
+msgstr "参数化"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:4
+msgid "There are multiple aspects to parametrization :"
+msgstr "参数化有多个方面的含义："
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:6
+msgid ""
+"Providing and the management of, elaboration time parameters provided to "
+"SpinalHDL during elaboration of the design"
+msgstr "在设计实例细化（elaboration）过程中向 SpinalHDL "
+"提供细化过程的参数并对其进行管理"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:8
+msgid ""
+"Using the parameter data to allow the designer to perform any kind of "
+"hardware construction, configuration and interconnection task needed in the "
+"design.  Such as optional component generation within the hardware design."
+msgstr "通过使用参数，设计人员可以实现任何类型硬件的构造、配置和互连任务。例如硬件设"
+"计中的可选组件生成。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:13
+msgid ""
+"Parallels exist with the aims of HDL features such as Verilog module "
+"parameters and VHDL generics.  SpinalHDL brings a far richer and more "
+"powerful set of capabilities into this area with the additional protection "
+"of Scala type safety and SpinalHDL built in HDL design rule checking."
+msgstr ""
+"与 HDL 泛化功能（例如 Verilog 模块参数和 VHDL 泛型）的目标类似。 SpinalHDL "
+"通过 Scala 类型安全和内置 HDL "
+"设计规则检查带来额外保护，提供了更丰富、更强大的功能集。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:19
+msgid ""
+"The SpinalHDL mechanisms for parameterization of components is not built on "
+"top of any native HDL mechanism and so is not impeded by HDL language "
+"level/version support or restrictions about what can be achieved in hand "
+"written HDL."
+msgstr ""
+"用于组件参数化的 SpinalHDL 机制不是构建在任何 HDL 机制之上，因此，不会受到 "
+"HDL 语言级别/版本支持或手写 HDL 带来限制的影响。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:24
+msgid ""
+"For readers looking to interoperate with parameterized Verilog or "
+"genericized VHDL using SpinalHDL, please see the section on :ref:`BlackBox "
+"<BlackBox>` IP for those scenarios your project requires."
+msgstr ""
+"对于希望使用 SpinalHDL 与参数化 Verilog 或通用 VHDL 进行互操作的读者，请参阅 "
+":ref:`BlackBox <BlackBox>` IP 中有关您的项目所需场景的部分。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:31
+msgid "Elaboration time parameters"
+msgstr "实例细化时参数"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:33
+msgid ""
+"You can use the whole Scala syntax to provide elaboration time parameters."
+msgstr "您可以使用所有 Scala 语法来提供实例细化时参数。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:35
+msgid ""
+"The whole syntax means you have the entire power and feature set of the "
+"Scala language at your disposal to solve parameterization requirements for "
+"your project at the level of complexity you choose."
+msgstr "所有的语法意味着您可以使用 Scala "
+"语言的全部功能，以按照您选择的复杂程度解决项目的参数化要求。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:39
+msgid ""
+"SpinalHDL does not place any opinionated restrictions on how to achieve your"
+" parameterization goals.  As such there are many Scala design patterns and a"
+" few SpinalHDL helpers that can be used to manage parameters that are suited"
+" to different parameter management scenarios."
+msgstr ""
+"SpinalHDL 不会对如何实现参数化目标施加任何特殊限制。因此，有许多 Scala "
+"设计模式和一些 SpinalHDL 帮助程序可用于管理参数，以适合不同场景。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:44
+msgid "Here are some examples and ideas of the possibilities:"
+msgstr "以下是一些示例和可能的想法："
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:46
+msgid ""
+"Hardwired code and constants (not strictly parameter management at all but "
+"serves to hilight the most basic mechanism, a code change, not a parameter "
+"data change)"
+msgstr "硬连线代码和常量（突出最基本的机制，而不是严格的参数管理，代码上的变更，而不"
+"是数据上的变更）"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:49
+msgid ""
+"Constant values provided from a companion object that are static constants "
+"in Scala."
+msgstr "由伴随对象提供的常量值在 Scala 中是静态常量。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:51
+msgid ""
+"Values provided to Scala class constructor, often a ``case class`` that "
+"causes Scala to capture those constructor argument values as constants."
+msgstr "提供给 Scala 类构造函数的值，通常一个 ``case class`` 会导致 Scala "
+"将这些构造函数的参数值捕获为常量。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:53
+msgid ""
+"Regular Scala flow-control syntax, not limited to but including "
+"conditionals, looping, lambdas/monads, everything."
+msgstr "常规 Scala 流程控制语法，包括但不限于条件、循环、lambda/monad 等。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:55
+msgid ""
+"Config class pattern (examples exist in library items such as "
+"UartCtrlConfig_, SpiMasterCtrlConfig)"
+msgstr "配置类的模式（示例存在于库中，包括 UartCtrlConfig_, SpiMasterCtrlConfig 等）"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:57
+msgid ""
+"Project defined 'Plugin' pattern (examples exist in the VexRiscV_ project to"
+" configure the feature set the resulting CPU IP core is built with)"
+msgstr "项目定义的“插件”模式（在 VexRiscV_ 项目中有示例，用于配置生成的 CPU IP "
+"核所使用的功能集）"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:59
+msgid ""
+"Values and information loaded from a file or network based source, using "
+"standard Scala/JVM libraries and APIs."
+msgstr "使用标准 Scala/JVM 库和 API 从文件或网络源中加载值和信息。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:61
+msgid "`any mechanism you can create`"
+msgstr "“任何你可以创建的机制”"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:63
+msgid ""
+"All of the mechanisms result in a change in resulting elaborated HDL output."
+msgstr "所有机制都会导致实力细化生成的 HDL 输出发生变化。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:65
+msgid ""
+"This could vary from a single constant value change all the way through to "
+"describing the entire bus and interconnection architecture of an entire SoC "
+"all without leaving the Scala programming paradigm."
+msgstr "这可以仅仅使用 Scala 编程就完成设计，支持单个常数值到整个 SoC "
+"的所有总线和互连架构描述的参数化。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:70
+msgid "Here is an example of class parameters"
+msgstr "这是一个类参数的示例"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:84
+msgid ""
+"You can also use global variable defined in Scala objects (companion object "
+"pattern)."
+msgstr "您还可以使用 Scala 对象（伴随对象模式）中定义的全局变量。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:87
+msgid ""
+"A :ref:`ScopeProperty <scopeproperty>` can also be used for configuration."
+msgstr "\\ :ref:`ScopeProperty <scopeproperty>` 也可用于配置。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:90
+msgid "Optional hardware"
+msgstr "可选硬件"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:92
+msgid "So here there is more possibilities."
+msgstr "所以这里还有更多的可能性。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:96
+msgid "For optional signal :"
+msgstr "对于可选信号："
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:106
+msgid ""
+"The ``generate`` method is a mechanism to evaluate the expression that "
+"follows for an optional value.  If the predicate is true, generate will "
+"evaluate the given expression and return the result, otherwise it returns "
+"null."
+msgstr ""
+"``generate`` 函数是一种实现具有可选值的表达式机制。如果谓词为 true，generate "
+"将计算给定表达式并返回结果，否则返回 null。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:111
+msgid ""
+"This may be used in cases to help parameterize the SpinalHDL hardware "
+"description using an elaboration-time conditional expression.  Causing HDL "
+"constructs to be emitted or not-emitted in the resulting HDL. The generate "
+"method can be seen as SpinalHDL syntatic sugar reducing language clutter."
+msgstr ""
+"使用实例细化时条件表达式有助于参数化 SpinalHDL 硬件描述。导致 HDL "
+"结构在生成的 HDL 中存在或不存在。generate函数可以看作是 SpinalHDL "
+"语法糖，减少语言混乱。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:116
+msgid ""
+"Project SpinalHDL code referencing ``mySignal`` would need to ensure it "
+"handles the possiblity of null gracefully.  This is usually not a problem as"
+" those parts of the design can also be omitted dependant on the ``flag`` "
+"value.  Thus the feature of parameterizing this component is demonstrated."
+msgstr ""
+"SpinalHDL 代码中引用 ``mySignal`` 信号将需要确保它优雅地处理 null "
+"的可能性。这通常不是问题，因为实际设计中的这些部分也会根据 ``flag`` "
+"值省略。从而达到了该组件参数化的目的。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:122
+msgid "You can do the same in Bundle."
+msgstr "您也可以在线束（Bundle）中做相同的事。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:124
+msgid "Note that you can also use scala Option."
+msgstr "请注意，您还可以使用 scala 选项类（Option）。"
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:126
+msgid "If you want to disable the generation of a chunk of hardware :"
+msgstr "如果你想禁用某个硬件块的生成："
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:136
+msgid "You can also use scala for loops :"
+msgstr "您还可以使用 scala 中的 for 循环："
+
+#: ../../SpinalHDL/Structuring/parametrization.rst:146
+msgid ""
+"So, you can extends those scala usages at elaboration time as much as you "
+"want, including using the whole scala collections (List, Set, Map, ...) to "
+"build some data model and then converting them into hardware in a procedural"
+" way (ex iterating over those list elements)."
+msgstr ""
+"因此，您可以在实例细化时根据需要扩展这些 scala 用法，包括使用整个 scala 集合"
+"（List、Set、Map...）来构建一些数据模型，然后以程序方式将它们转换为硬件（例如"
+"，迭代这些列表中的元素）。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
+
+#~ msgid "Optionaly generate some hardware"
+#~ msgstr "可选择生成一些硬件"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/chisel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/chisel.po
new file mode 100644
index 00000000000..7b3b4b1a397
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/chisel.po
@@ -0,0 +1,6 @@
+
+msgid ""
+msgstr ""
+"Project-Id-Version:SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding:8bitGenerated-By:Babel 2.13.1"
+
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po
new file mode 100644
index 00000000000..f9403e6b1a8
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po
@@ -0,0 +1,619 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-26 05:04+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlmisceleneacorecore_components/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.4-dev\n"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:8
+msgid "The ``spinal.core`` components"
+msgstr "``spinal.core`` 组件"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:9
+msgid ""
+"The core components of the language are described in this document. It is "
+"part of the general"
+msgstr "本文档描述了该语言的核心组件。它涵盖了大部分情况"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:13
+msgid "The core language components are as follows:"
+msgstr "核心语言组件如下："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:15
+msgid ""
+":ref:`*Clock domains* <core_components_clock_domain_definition>`, which "
+"allow to define and interoperate multiple clock domains within a design"
+msgstr ":ref:`*时钟域* "
+"<core_components_clock_domain_definition>`，允许在设计中定义和操作多个时钟域"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:16
+msgid ""
+"*Memory instantiation*\\ , which permit the automatic instantiation of RAM "
+"and ROM memories."
+msgstr "*存储器实例化*\\ ，允许自动实例化 RAM 和 ROM 存储器。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:17
+msgid "*IP instantiation*\\ , using either existing VHDL or Verilog component."
+msgstr "*IP 实例化*\\ ，使用现有的 VHDL 或 Verilog 组件实例化。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:18
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:160
+msgid "Assignments"
+msgstr "赋值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:19
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:229
+msgid "When / Switch"
+msgstr "When / Switch"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:20
+msgid "Component hierarchy"
+msgstr "组件层次结构"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:21
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:328
+msgid "Area"
+msgstr "Area"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:22
+msgid "Functions"
+msgstr "函数"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:23
+msgid "Utility functions"
+msgstr "实用函数"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:24
+msgid "VHDL generator"
+msgstr "VHDL生成器"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:29
+msgid "Clock domains definitions"
+msgstr "时钟域定义"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:31
+msgid ""
+"In *Spinal*\\ , clock and reset signals can be combined to create a **clock "
+"domain**. Clock domains could be applied to some area of the design and then"
+" all synchronous elements instantiated into this area will then "
+"**implicitly** use this clock domain."
+msgstr ""
+"在 *Spinal*\\ 中，时钟和复位信号可以组合起来创建**时钟域**。时钟域可以应用于"
+"设计的某些区域，该区域的所有实例化的同步元件将**隐式地**使用该时钟域。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:33
+msgid ""
+"Clock domain application work like a stack, which mean, if you are in a "
+"given clock domain, you can still apply another clock domain locally."
+msgstr "时钟域像堆栈一样工作，这意味着，如果您的逻辑位于给定时钟域中，您仍然可以在其"
+"上应用另一个时钟域。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:39
+msgid "Clock domain syntax"
+msgstr "时钟域语法"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:41
+msgid "The syntax to define a clock domain is as follows (using EBNF syntax):"
+msgstr "定义时钟域的语法如下（使用EBNF语法）："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:43
+msgid "``ClockDomain(clock : Bool[,reset : Bool[,enable : Bool]]])``"
+msgstr "``ClockDomain(clock : Bool[,reset : Bool[,enable : Bool]]])``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:45
+msgid "This definition takes three parameters:"
+msgstr "这个定义需要三个参数："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:48
+msgid "The clock signal that defines the domain"
+msgstr "时钟域的时钟信号"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:49
+msgid ""
+"An optional ``reset``\\ signal. If a register which need a reset and his "
+"clock domain didn't provide one, an error message happen"
+msgstr "可选的 ``reset`` "
+"复位信号。如果需要重置的寄存器并且其时钟域没有提供重置，则会出现错误提示"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:50
+msgid ""
+"An optional ``enable`` signal. The goal of this signal is to disable the "
+"clock on the whole clock domain without having to  manually implement that "
+"on each synchronous element."
+msgstr "可选的 ``enable`` 使能信号。该信号的目标是禁用整个时钟域上的时钟，而无需在每"
+"个同步元件上手动实现。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:52
+msgid ""
+"An applied example to define a specific clock domain within the design is as"
+" follows:"
+msgstr "在设计中定义具有指定属性时钟域的示例如下："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:70
+msgid "Clock configuration"
+msgstr "时钟配置"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:72
+msgid ""
+"In addition to the constructor parameters given :ref:`here "
+"<core_componets_clock_constructor>` , the following elements of each clock "
+"domain are configurable via a ``ClockDomainConfig`` class :"
+msgstr ""
+"除了 :ref:`此处 <core_componets_clock_constructor>` 给出的构造函数参数之外，"
+"每个时钟域的以下元素都可以通过 ``ClockDomainConfig`` 类进行配置："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:78
+msgid "Property"
+msgstr "属性"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:79
+msgid "Valid values"
+msgstr "有效值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:80
+msgid "``clockEdge``"
+msgstr "``clockEdge``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:81
+msgid "``RISING``\\ , ``FALLING``"
+msgstr "``RISING``\\ , ``FALLING``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:82
+msgid "``ResetKind``"
+msgstr "``ResetKind``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:83
+msgid "``ASYNC``\\ , ``SYNC``"
+msgstr "``ASYNC``\\ , ``SYNC``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:84
+msgid "``resetActiveHigh``"
+msgstr "``resetActiveHigh``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:85
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:87
+msgid "``true``\\ , ``false``"
+msgstr "``true``\\ , ``false``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:86
+msgid "``clockEnableActiveHigh``"
+msgstr "``clockEnableActiveHigh``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:112
+msgid ""
+"By default, a ClockDomain is applied to the whole design. The configuration "
+"of this one is :"
+msgstr "默认情况下，时钟域应用于整个设计。缺省的配置是："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:115
+msgid "clock : rising edge"
+msgstr "clock ：上升沿触发"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:116
+msgid "reset: asynchronous, active high"
+msgstr "reset：异步，高电平有效"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:117
+msgid "no enable signal"
+msgstr "无使能信号"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:120
+msgid "External clock"
+msgstr "外部时钟"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:122
+msgid ""
+"You can define everywhere a clock domain which is driven by the outside. It "
+"will then automatically add clock and reset wire from the top level inputs "
+"to all synchronous elements."
+msgstr "您可以在任何地方定义由外部驱动的时钟域。然后，它会自动将时钟和复位线从顶层输"
+"入添加到所有同步元件。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:140
+msgid "Cross Clock Domain"
+msgstr "跨时钟域设计"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:142
+msgid ""
+"SpinalHDL checks at compile time that there is no unwanted/unspecified cross"
+" clock domain signal reads. If you want to read a signal that is emitted by "
+"another ``ClockDomain`` area, you should add the ``crossClockDomain`` tag to"
+" the destination signal as depicted in the following example:"
+msgstr ""
+"SpinalHDL 在编译时检查是否存在不需要的/未指定的跨时钟域信号访问。"
+"如果您想读取另一个 ``ClockDomain`` （时钟域）发出的信号，则应给目标信号增加 "
+"``crossClockDomain`` 标记，如下例所示："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:162
+msgid "There are multiple assignment operator :"
+msgstr "有多种赋值运算符："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:168
+msgid "Symbole"
+msgstr "符号"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:169
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:204
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:307
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:488
+msgid "Description"
+msgstr "描述"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:170
+msgid ":="
+msgstr ":="
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "Standard assignment, equivalent to '<=' in VHDL/Verilog"
+msgstr "标准赋值，相当于 VHDL/Verilog 中的“<=”"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "last assignment win, value updated at next delta cycle"
+msgstr "最后一次分配获胜，值在下一个delta周期更新"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:173
+msgid "/="
+msgstr "/="
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "Equivalent to := in VHDL and = in Verilog"
+msgstr "相当于 VHDL 中的 := 和 Verilog 中的 =（不常用）"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "value updated instantly"
+msgstr "值立即更新"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:176
+msgid "<>"
+msgstr "<>"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid ""
+"Automatic connection between 2 signals. Direction is inferred by using "
+"signal direction (in/out)"
+msgstr "2 个信号之间的自动连接。通过输入/输出设置推断信号方向"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "Similar behavioural than :="
+msgstr "与 := 类似的行为"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:197
+msgid ""
+"SpinalHDL check that bitcount of left and right assignment side match. There"
+" is multiple ways to adapt bitcount of BitVector (Bits, UInt, SInt) :"
+msgstr "SpinalHDL 检查左右分配端的位数是否匹配。有多种方法可以改变 BitVector "
+"（Bits、UInt、SInt）的位数："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:203
+msgid "Resizing ways"
+msgstr "改变位宽的方式"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:205
+msgid "x := y.resized"
+msgstr "x := y.resized"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:206
+msgid ""
+"Assign x wit a resized copy of y, resize value is automatically inferred to "
+"match x"
+msgstr "将 y 改变位宽后的副本赋值给 x，自动推断位宽以匹配 x"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:207
+msgid "x := y.resize(newWidth)"
+msgstr "x := y.resize(newWidth)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:208
+msgid "Assign x with a resized copy of y, size is manually calculated"
+msgstr "将 y 改变位宽后的副本分配给 x，大小是手动计算的"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:211
+msgid "There are 2 cases where spinal automaticly resize things :"
+msgstr "有两种情况会导致spinal自动调整位宽："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:217
+msgid "Assignement"
+msgstr "赋值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:218
+msgid "Problem"
+msgstr "问题"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:219
+msgid "SpinalHDL action"
+msgstr "SpinalHDL行为"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:220
+msgid "myUIntOf_8bit := U(3)"
+msgstr "myUIntOf_8bit := U(3)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:221
+msgid "U(3) create an UInt of 2 bits, which don't match with left side"
+msgstr "U(3) 创建一个 2 位的 UInt，与左侧不匹配"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:222
+msgid ""
+"Because  U(3) is a \"weak\" bit inferred signal, SpinalHDL resize it "
+"automatically"
+msgstr "由于 U(3) 是“弱”位推断信号，SpinalHDL 自动调整其位宽"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:223
+msgid "myUIntOf_8bit := U(2 -> False default -> true)"
+msgstr "myUIntOf_8bit := U(2 -> False default -> true)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:224
+msgid ""
+"The right part infer a 3 bit UInt, which doesn't match with the left part"
+msgstr "右侧部分推断出 3 位 UInt，与左侧部分不匹配"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:225
+msgid "SpinalHDL reapply the default value to bit that are missing"
+msgstr "SpinalHDL 将默认值重新应用于丢失的位"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:231
+msgid ""
+"As VHDL and Verilog, wire and register can be conditionally assigned by "
+"using when and switch syntaxes"
+msgstr "与 VHDL 和 Verilog 一样，信号线和寄存器可以通过使用 when 和 switch "
+"语法进行条件赋值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:255
+msgid ""
+"You can also define new signals into a when/switch statement. It's useful if"
+" you want to calculate an intermediate value."
+msgstr "您还可以在when/switch 语句中定义新信号。如果您想计算中间值时，它很有用。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:272
+msgid "Component/Hierarchy"
+msgstr "组件/层次结构"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:274
+msgid ""
+"Like in VHDL and Verilog, you can define components that could be used to "
+"build a design hierarchy.  But unlike them, you don't need to bind them at "
+"instantiation."
+msgstr "与 VHDL 和 Verilog 一样，您可以定义可用于构建设计层次结构的组件。但与它们不同"
+"的是，您不需要在实例化时绑定它们。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:300
+msgid "Syntax to define in/out is the following :"
+msgstr "定义输入/输出的语法如下："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:306
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:487
+msgid "Syntax"
+msgstr "语法"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:308
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:489
+msgid "Return"
+msgstr "返回类型"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:309
+msgid "in/out(x : Data)"
+msgstr "in/out(x : Data)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:310
+msgid "Set x an input/output"
+msgstr "设置 x 为输入/输出"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:311
+msgid "x"
+msgstr "x"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:312
+msgid "in/out Bool()"
+msgstr "in/out Bool()"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:313
+msgid "Create an input/output Bool"
+msgstr "创建输入/输出Bool值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:314
+msgid "Bool"
+msgstr "Bool"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:315
+msgid "in/out Bits/UInt/SInt(x bits)"
+msgstr "in/out Bits/UInt/SInt(x bits)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:316
+msgid "Create an input/output of the corresponding type"
+msgstr "创建相应类型的输入/输出端口"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:317
+msgid "T"
+msgstr "T"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:320
+msgid "There is some rules about component interconnection :"
+msgstr "组件互连有一些规则："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:323
+msgid "Components can only read outputs/inputs signals of children components"
+msgstr "组件只能读取子组件的输出/输入信号值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:324
+msgid "Components can read outputs/inputs ports values"
+msgstr "组件可以读取输出/输入端口值"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:325
+msgid ""
+"If for some reason, you need to read a signals from far away in the "
+"hierarchy (debug, temporal patch) you can do it by using the value returned "
+"by some.where.else.theSignal.pull()."
+msgstr ""
+"如果由于某种原因，您需要从层次结构中的远处读取信号时（调试、临时补丁），"
+"您可以使用 some.where.else.theSignal.pull() 返回的值来实现。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:330
+msgid ""
+"Sometime, creating a component to define some logic is overkill and to much "
+"verbose. For this kind of cases you can use Area :"
+msgstr "有时，创建一个组件来定义某些逻辑是多余的并且过于冗长。对于这种情况，"
+"您可以使用 Area 逻辑区 ："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:360
+msgid "Function"
+msgstr "函数"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:362
+msgid ""
+"The ways you can use Scala functions to generate hardware are radically "
+"different than VHDL/Verilog for many reasons:"
+msgstr "使用 Scala 函数生成硬件的方式与 VHDL/Verilog 完全不同，原因有很多："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:365
+msgid ""
+"You can instantiate register, combinatorial logic and component inside them."
+msgstr "您可以在其中实例化寄存器、组合逻辑和组件。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:366
+msgid ""
+"You don't have to play with ``process``\\ /\\ ``@always`` that limit the "
+"scope of assignment of signals"
+msgstr "您不必使用限制信号分配范围的 ``process``\\ /\\ ``@always``"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid "Everything work by reference, which allow many manipulation."
+msgstr "一切都按参考工作，这允许许多操作。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid ""
+"For example you can give to a function an bus as argument, then the function"
+" can internaly read/write it."
+msgstr "例如，您可以为函数提供总线作为参数，然后可以在该函数内部读取/写入它。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst
+msgid ""
+"You can also return a Component, a Bus, are anything else from scala the "
+"scala world."
+msgstr "您还可以返回一个组件、总线以及 scala 世界中的任何其他内容。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:372
+msgid "RGB to gray"
+msgstr "RGB信号转灰度信号"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:374
+msgid ""
+"For example if you want to convert a Red/Green/Blue color into a gray one by"
+" using coefficient, you can use functions to apply them :"
+msgstr "例如，如果您想使用系数将红/绿/蓝颜色转换为灰色，您可以使用函数来应用它们："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:390
+msgid "Valid Ready Payload bus"
+msgstr "Valid Ready Payload 总线"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:392
+msgid ""
+"For instance if you define a simple Valid Ready Payload bus, you can then "
+"define useful function inside it."
+msgstr "例如，如果您定义一个简单的 Valid Ready Payload "
+"总线，则可以在其中定义有用的函数。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:417
+msgid "VHDL generation"
+msgstr "VHDL生成"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:419
+msgid ""
+"There is a small component and a ``main`` that generate the corresponding "
+"VHDL."
+msgstr "有一个小组件和一个生成相应 VHDL 的 ``main`` 。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:448
+msgid "Instantiate VHDL and Verilog IP"
+msgstr "实例化 VHDL 和 Verilog IP"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:450
+msgid ""
+"In some cases, it could be useful to instantiate a VHDL or a Verilog "
+"component into a SpinalHDL design. To do that, you need to define BlackBox "
+"which is like a Component, but its internal implementation should be "
+"provided by a separate VHDL/Verilog file to the simulator/synthesis tool."
+msgstr ""
+"在某些情况下，将 VHDL 或 Verilog 组件实例化到 SpinalHDL "
+"设计中可能会很有用。为此，您需要定义 BlackBox，它就像一个组件，"
+"但其内部实现应由单独的 VHDL/Verilog 文件提供给仿真/综合工具。"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:479
+msgid "Utils"
+msgstr "实用工具"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:481
+msgid "The SpinalHDL core contain some utils :"
+msgstr "SpinalHDL 核心包含一些实用工具："
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:490
+msgid "log2Up(x : BigInt)"
+msgstr "log2Up(x : BigInt)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:491
+msgid "Return the number of bit needed to represent x states"
+msgstr "返回表示 x 状态所需的位数"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:492
+msgid "Int"
+msgstr "Int"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:493
+msgid "isPow2(x : BigInt)"
+msgstr "isPow2(x : BigInt)"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:494
+msgid "Return true if x is a power of two"
+msgstr "如果 x 是 2 的幂，则返回 true"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:495
+msgid "Boolean"
+msgstr "Boolean"
+
+#: ../../SpinalHDL/miscelenea/core/core_components.rst:498
+msgid "Much more tool and utils are present in spinal.lib"
+msgstr "Spindle.lib 中提供了更多工具和实用程序"
+
+#~ msgid "Memory"
+#~ msgstr "记忆"
+
+#~ msgid "Mem(type : Data,size : Int)"
+#~ msgstr "内存（类型：数据，大小：Int）"
+
+#~ msgid "Create a RAM"
+#~ msgstr "创建内存"
+
+#~ msgid "Mem(type : Data,initialContent : Array[Data])"
+#~ msgstr "Mem(类型：数据，初始内容：数组[数据])"
+
+#~ msgid "Create a ROM"
+#~ msgstr "创建一个ROM"
+
+#~ msgid "mem(x)"
+#~ msgstr "内存（x）"
+
+#~ msgid "Asynchronous read"
+#~ msgstr "异步读取"
+
+#~ msgid "mem(x) := y"
+#~ msgstr "内存(x) := y"
+
+#~ msgid "Synchronous write"
+#~ msgstr "同步写入"
+
+#~ msgid "mem.readSync(address,enable)"
+#~ msgstr "mem.readSync（地址，启用）"
+
+#~ msgid "Synchronous read"
+#~ msgstr "同步读取"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/elements.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/elements.po
new file mode 100644
index 00000000000..bbf56f360c4
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/elements.po
@@ -0,0 +1,132 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlmisceleneacoreelements/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:9
+msgid "Element"
+msgstr "Element"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:11
+msgid "Elements could be defined as follows:"
+msgstr "可以这样定义元素："
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:17
+msgid "Element syntax"
+msgstr "元素语法"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:18
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:44
+msgid "Description"
+msgstr "描述"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:19
+msgid "x : Int -> y : Boolean/Bool"
+msgstr "x : Int -> y : Boolean/Bool"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:20
+msgid "Set bit x with y"
+msgstr "用 y 设置位 x"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:21
+msgid "x : Range -> y : Boolean/Bool"
+msgstr "x : Range -> y : Boolean/Bool"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:22
+msgid "Set each bits in range x with y"
+msgstr "设置 x 范围内的每个位为 y"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:23
+msgid "x : Range -> y : T"
+msgstr "x : Range -> y : T"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:24
+msgid "Set bits in range x with y"
+msgstr "设置 x 范围内的位为y"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:25
+msgid "x : Range -> y : String"
+msgstr "x : Range -> y : String"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst
+msgid "The string format follow same rules than B\"xyz\" one"
+msgstr "字符串格式遵循与 B\"xyz\" 相同的规则"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:28
+msgid "default -> y : Boolean/Bool"
+msgstr "default -> y : Boolean/Bool"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst
+msgid "Set all unconnected bits with the y value."
+msgstr "使用 y 值设置所有未连接的位。"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst
+msgid ""
+"This feature could only be use to do assignments without the B prefix or "
+"with the B prefix combined with the bits specification"
+msgstr "此功能只允许在没有 B 前缀或 B 前缀与位规范相结合的情况下进行赋值"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:35
+msgid "Range"
+msgstr "范围"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:37
+msgid "You can define a Range values"
+msgstr "您可以定义一个范围值"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:43
+msgid "Range syntax"
+msgstr "范围语法"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:45
+msgid "Width"
+msgstr "位宽"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:46
+msgid "(x downto y)"
+msgstr "(x downto y)"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:47
+msgid "[x:y], x >= y"
+msgstr "[x:y], x >= y"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:48
+msgid "x-y+1"
+msgstr "x-y+1"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:49
+msgid "(x to y)"
+msgstr "(x to y)"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:50
+msgid "[x:y], x <= y"
+msgstr "[x:y], x <= y"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:51
+msgid "y-x+1"
+msgstr "y-x+1"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:52
+msgid "(x until y)"
+msgstr "(x until y)"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:53
+msgid "[x:y[, x < y"
+msgstr "[x:y[, x < y"
+
+#: ../../source/SpinalHDL/miscelenea/core/elements.rst:54
+msgid "y-x"
+msgstr "y-x"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po
new file mode 100644
index 00000000000..dc405369f7b
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po
@@ -0,0 +1,119 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-"
+"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME <EMAIL@ADDRESS"
+">Language-Team:LANGUAGE <LL@li.org>MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-18 07:38+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlmisceleneafrequent_errors/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3\n"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:7
+msgid "Frequent Errors"
+msgstr "常见错误"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:9
+msgid ""
+"This page will talk about errors which could happen when people are using "
+"SpinalHDL."
+msgstr "本页将讨论人们在使用 SpinalHDL 时可能出现的错误。"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:12
+msgid "Exception in thread \"main\" java.lang.NullPointerException"
+msgstr "“main”线程中异常 java.lang.NullPointerException"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:14
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:39
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:87
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:114
+msgid "**Console symptoms :**"
+msgstr "**控制台输出：**"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:20
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:45
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:93
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:120
+msgid "**Code Example :**"
+msgstr "**代码示例：**"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:27
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:80
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:107
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:139
+msgid "**Issue explanation :**"
+msgstr "**问题解释：**"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:29
+msgid ""
+"SpinalHDL is not a language, it is an Scala library, which mean, it obey to "
+"the same rules than the Scala general purpose programming language. When you"
+" run your SpinalHDL hardware description to generate the corresponding "
+"VHDL/Verilog RTL, your SpinalHDL hardware description will be executed as a "
+"Scala programm, and b will be a ``null`` reference until the programm "
+"execution come to that line, and it's why you can't use it before."
+msgstr ""
+"SpinalHDL 不是一种语言，它是一个 Scala 库，这意味着它遵循与 Scala "
+"语言相同的通用规则。当您运行 SpinalHDL 硬件描述来生成相应的 VHDL/Verilog RTL "
+"时，您的 SpinalHDL 硬件描述将作为 Scala 程序执行，并且执行程序到该行时， b "
+"将是一个 ``null`` 空引用，这就是为什么你在这之前不能使用它的原因。"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:32
+msgid "Hierarchy violation"
+msgstr "层次违例(Hierarchy violation)"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:34
+msgid ""
+"The SpinalHDL compiler check that all your assignments are legal from an "
+"hierarchy perspective. Multiple cases are elaborated in following chapters"
+msgstr "SpinalHDL "
+"编译器从层次结构的角度检查所有赋值是否合法。后续章节将详细阐述多个案例"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:37
+msgid "Signal X can't be assigned by Y"
+msgstr "Signal X can't be assigned by Y"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:82
+msgid ""
+"You can only assign input signals of subcomponents, else there is an "
+"hierarchy violation. If this issue happend, you probably forgot to specify "
+"the X signal's direction."
+msgstr "您只能给子组件的输入信号赋值，否则会违反层次结构。如果发生这样的问题，"
+"可能是您忘记指定 X 信号的方向。"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:85
+msgid "Input signal X can't be assigned by Y"
+msgstr "Input signal X can't be assigned by Y"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:109
+msgid ""
+"You can only assign an input signals from the parent component, else there "
+"is an hierarchy violation. If this issue happend, you probably mixed signals"
+" direction declaration."
+msgstr "您只能从父组件对输入信号赋值，否则会违反层次结构。如果发生此问题，您可能把声"
+"明的信号方向弄混了。"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:112
+msgid "Output signal X can't be assigned by Y"
+msgstr "Output signal X can't be assigned by Y"
+
+#: ../../SpinalHDL/miscelenea/frequent_errors.rst:141
+msgid ""
+"You can only assign output signals of a component from the inside of it, "
+"else there is an hierarchy violation. If this issue happend, you probably "
+"mixed signals direction declaration."
+msgstr "您只能从组件内部赋值组件的输出信号，否则会违反层次结构。如果发生此问题，您可"
+"能把声明信号的方向弄混了。"
+
+#~ msgid "Introduction"
+#~ msgstr "介绍"
diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/index.po
new file mode 100644
index 00000000000..0b32bcd54e2
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/index.po
@@ -0,0 +1,48 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-"
+"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME "
+"<EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li.org>Plural-"
+"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; "
+"charset=UTF-8\n"
+"PO-Revision-Date: 2023-12-03 17:03+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/spinalhdlmisceleneaindex/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../SpinalHDL/miscelenea/index.rst:3
+msgid "Miscellaneous"
+msgstr "杂项"
+
+#: ../../SpinalHDL/miscelenea/index.rst:5
+msgid "This section includes content that may be:"
+msgstr "本节包含的内容可能是："
+
+#: ../../SpinalHDL/miscelenea/index.rst:7
+msgid "out-of-date"
+msgstr "过时的"
+
+#: ../../SpinalHDL/miscelenea/index.rst:8
+msgid "could be better curated"
+msgstr "可以更好地策划"
+
+#: ../../SpinalHDL/miscelenea/index.rst:9
+msgid ""
+"may contain duplicate information (better found elsewhere here or in another"
+" repo)"
+msgstr "可能包含重复信息（最好在此处或另一个存储库中找到）"
+
+#: ../../SpinalHDL/miscelenea/index.rst:10
+msgid "drafts of documentation and works in progress"
+msgstr "文件草稿和正在进行的工作"
+
+#: ../../SpinalHDL/miscelenea/index.rst:12
+msgid ""
+"So please consider the information in this section with caution and a best "
+"effort on the author to provide documentation."
+msgstr "因此，请谨慎考虑本节中的信息，并尽力让作者提供文档。"
diff --git a/source/locale/zh_CN/LC_MESSAGES/index.po b/source/locale/zh_CN/LC_MESSAGES/index.po
new file mode 100644
index 00000000000..51c10c1952a
--- /dev/null
+++ b/source/locale/zh_CN/LC_MESSAGES/index.po
@@ -0,0 +1,93 @@
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-"
+"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-"
+"Translator:FULL NAME <EMAIL@ADDRESS>Language:zh_CNLanguage-Team:zh_CN <LL@li."
+"org>Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/"
+"plain; charset=UTF-8\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: 2023-12-02 04:39+0000\n"
+"Last-Translator: Readon <xydarcher@qq.com>\n"
+"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
+"spinaldoc-rtd/index/zh_Hans/>\n"
+"Language: zh_CN\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"X-Generator: Weblate 5.3-dev\n"
+
+#: ../../index.rst:2
+msgid "Spinal Hardware Description Language"
+msgstr "Spinal硬件描述语言"
+
+#: ../../index.rst:4
+msgid "Welcome to SpinalHDL's documentation!"
+msgstr "欢迎来到 SpinalHDL 的文档！"
+
+#: ../../index.rst:6
+msgid ""
+"SpinalHDL is an open source high-level hardware description language. It can "
+"be used as an alternative to VHDL or Verilog and has several advantages over "
+"them:"
+msgstr ""
+"SpinalHDL 是一种开源高级硬件描述语言。它可以用作 VHDL 或 Verilog 的替代品，并"
+"且比它们有几个优点："
+
+#: ../../index.rst:9
+msgid ""
+"It focuses on efficient hardware description instead of being event-driven."
+msgstr "它专注于高效的硬件描述而不是事件驱动。"
+
+#: ../../index.rst:10
+msgid ""
+"It is embedded into a general purpose programming language, enabling "
+"powerful hardware generation."
+msgstr "它被嵌入到通用编程语言中，从而具备强大的硬件逻辑生成能力。"
+
+#: ../../index.rst:13
+msgid ""
+"More detailed introduction of the language in :ref:`Introduction/SpinalHDL`"
+msgstr "关于该语言更详细的介绍请参见 :ref:`Introduction/SpinalHDL`"
+
+#: ../../index.rst:15
+msgid "HTML and PDF formats of this documentation are available online:"
+msgstr "本文档的 HTML 和 PDF 格式可在线获取："
+
+#: ../../index.rst:16
+msgid ""
+"> `spinalhdl.github.io/SpinalDoc-RTD <https://spinalhdl.github.io/SpinalDoc-"
+"RTD/master/index.html>`_"
+msgstr ""
+"> `spinalhdl.github.io/SpinalDoc-RTD <https://spinalhdl.github.io/SpinalDoc-"
+"RTD/master/index.html>`_"
+
+#: ../../index.rst:17
+msgid ""
+"(PDF format is accessible from the lower left corner, click ``v:master`` "
+"then PDF)"
+msgstr "（可从左下角访问 PDF 格式文档，点击 ``v:master`` ，然后点击 PDF）"
+
+#: ../../index.rst:18
+msgid "Chinese version of documentation:"
+msgstr "中文版文档："
+
+#: ../../index.rst:19
+msgid ""
+"> `github.com/thuCGRA/SpinalHDL_Chinese_Doc <https://github.com/thuCGRA/"
+"SpinalHDL_Chinese_Doc>`_"
+msgstr ""
+"> `github.com/thuCGRA/SpinalHDL_Chinese_Doc <https://github.com/thuCGRA/"
+"SpinalHDL_Chinese_Doc>`_"
+
+#: ../../index.rst:20
+msgid "You can also find the API documentation:"
+msgstr "您还可以在这里找到 API 文档："
+
+#: ../../index.rst:21
+msgid ""
+"> `spinalhdl.github.io/SpinalHDL <https://spinalhdl.github.io/SpinalHDL/dev/"
+"spinal/index.html>`_"
+msgstr ""
+"> `spinalhdl.github.io/SpinalHDL <https://spinalhdl.github.io/SpinalHDL/dev/"
+"spinal/index.html>`_"