-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1423,7 +1423,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1605,7 +1605,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1418,7 +1418,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1428,7 +1428,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1324,7 +1324,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1799,7 +1799,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1245,7 +1245,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1309,7 +1309,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1474,7 +1474,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1248,7 +1248,7 @@
Auto-range Fixed-point numbers (add,sub,mul support)
Floating-point numbers (experimental support)
Additionaly, if you want to assign a don’t care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so.
+Additionally, if you want to assign a don’t care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so.
diff --git a/master/SpinalHDL/Design errors/clock_crossing_violation.html b/master/SpinalHDL/Design errors/clock_crossing_violation.html index 47a37ef34c9..279ee3a61c3 100644 --- a/master/SpinalHDL/Design errors/clock_crossing_violation.html +++ b/master/SpinalHDL/Design errors/clock_crossing_violation.html @@ -420,7 +420,7 @@@@ -1293,7 +1293,7 @@ diff --git a/master/SpinalHDL/Design errors/assignment_overlap.html b/master/SpinalHDL/Design errors/assignment_overlap.html index f620786f3d0..46c9232ae6c 100644 --- a/master/SpinalHDL/Design errors/assignment_overlap.html +++ b/master/SpinalHDL/Design errors/assignment_overlap.html @@ -420,7 +420,7 @@val myBits = Bits(8 bits) myBits.assignDontCare() // Will assign all the bits to 'x'
- Composite in a function
- Composite chains
- Composite in a Bundle’s function
-- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1309,7 +1309,7 @@
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1374,7 +1374,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1341,7 +1341,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1316,7 +1316,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1375,7 +1375,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1308,7 +1308,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1333,7 +1333,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1299,7 +1299,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1301,7 +1301,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1300,7 +1300,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1309,7 +1309,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1307,7 +1307,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1346,7 +1346,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1331,7 +1331,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1309,7 +1309,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1327,7 +1327,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1369,7 +1369,7 @@
Implementation
BusSlaveFactory
Let’s describe primitives abstract function :
-trait BusSlaveFactory extends Area{ +
trait BusSlaveFactory extends Area { def busDataWidth : Int @@ -1387,13 +1387,13 @@
BusSlaveFactory def nonStopWrite( that : Data, bitOffset : Int = 0) : Unit - //... + // ... }
Then let’s operate the magic to implement all utile based on them :
-trait BusSlaveFactory extends Area{ - //... +
trait BusSlaveFactory extends Are { + // ... def readAndWrite(that : Data, address: BigInt, bitOffset : Int = 0): Unit = { @@ -1422,7 +1422,7 @@
BusSlaveFactory address: BigInt, bitOffset : Int = 0) : Unit = { that.valid := False - onWrite(address){ + onWrite(address) { that.valid := True } nonStopWrite(that.payload,bitOffset) @@ -1452,7 +1452,7 @@
BusSlaveFactory val reg = Reg(that) reg := reg | that read(reg,address,bitOffset) - onRead(address){ + onRead(address) { reg := that } } @@ -1462,7 +1462,7 @@
BusSlaveFactory validBitOffset : Int, payloadBitOffset : Int) : Unit = { that.ready := False - onRead(address){ + onRead(address) { that.ready := True } read(that.valid ,address,validBitOffset) @@ -1484,7 +1484,7 @@
BusSlaveFactory val wordCount = (widthOf(that) - 1) / busDataWidth + 1 for (wordId <- (0 until wordCount)) { write( - that = new DataWrapper{ + that = new DataWrapper { override def getBitsWidth: Int = Math.min(busDataWidth, widthOf(that) - wordId * busDataWidth) @@ -1534,7 +1534,7 @@
BusSlaveFactoryDelayed
Then let’s implement the
-BusSlaveFactoryDelayeditself :trait BusSlaveFactoryDelayed extends BusSlaveFactory{ +
trait BusSlaveFactoryDelayed extends BusSlaveFactory { // elements is an array of all BusSlaveFactoryElement requested val elements = ArrayBuffer[BusSlaveFactoryElement]() @@ -1574,7 +1574,7 @@
BusSlaveFactoryDelayed elements += BusSlaveFactoryNonStopWrite(that,bitOffset) } - //This is the only thing that should be implement by class that extends BusSlaveFactoryDelayed + // This is the only thing that should be implement by class that extends BusSlaveFactoryDelayed def build() : Unit component.addPrePopTask(() => build()) @@ -1624,13 +1624,13 @@
AvalonMMSlaveFactory
- Unnamed signal handling
Operator example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Developers area/bus_slave_factory_impl.html b/master/SpinalHDL/Developers area/bus_slave_factory_impl.html index 730f7331723..077e331995f 100644 --- a/master/SpinalHDL/Developers area/bus_slave_factory_impl.html +++ b/master/SpinalHDL/Developers area/bus_slave_factory_impl.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/width_mismatch.html b/master/SpinalHDL/Design errors/width_mismatch.html index 38fdc7ce20d..cae01bf6513 100644 --- a/master/SpinalHDL/Design errors/width_mismatch.html +++ b/master/SpinalHDL/Design errors/width_mismatch.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Register with only init diff --git a/master/SpinalHDL/Design errors/unreachable_is_statement.html b/master/SpinalHDL/Design errors/unreachable_is_statement.html index 85f2f0f3482..b577cff7b96 100644 --- a/master/SpinalHDL/Design errors/unreachable_is_statement.html +++ b/master/SpinalHDL/Design errors/unreachable_is_statement.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Example 2
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/unassigned_register.html b/master/SpinalHDL/Design errors/unassigned_register.html index a55674049d1..12ed3e904e1 100644 --- a/master/SpinalHDL/Design errors/unassigned_register.html +++ b/master/SpinalHDL/Design errors/unassigned_register.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/spinal_cant_clone.html b/master/SpinalHDL/Design errors/spinal_cant_clone.html index 482a5e414ca..fc53cc18d04 100644 --- a/master/SpinalHDL/Design errors/spinal_cant_clone.html +++ b/master/SpinalHDL/Design errors/spinal_cant_clone.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/scope_violation.html b/master/SpinalHDL/Design errors/scope_violation.html index f9c974768a2..1d436d05a55 100644 --- a/master/SpinalHDL/Design errors/scope_violation.html +++ b/master/SpinalHDL/Design errors/scope_violation.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Specifying exceptions diff --git a/master/SpinalHDL/Design errors/register_defined_as_component_input.html b/master/SpinalHDL/Design errors/register_defined_as_component_input.html index 31afa84e669..9935ab3568d 100644 --- a/master/SpinalHDL/Design errors/register_defined_as_component_input.html +++ b/master/SpinalHDL/Design errors/register_defined_as_component_input.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Issue explanation
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/out_of_range_constant.html b/master/SpinalHDL/Design errors/out_of_range_constant.html index 03788afde0b..1bdedbd006e 100644 --- a/master/SpinalHDL/Design errors/out_of_range_constant.html +++ b/master/SpinalHDL/Design errors/out_of_range_constant.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/nullpointerexception.html b/master/SpinalHDL/Design errors/nullpointerexception.html index 2c58753f125..9c44db98f18 100644 --- a/master/SpinalHDL/Design errors/nullpointerexception.html +++ b/master/SpinalHDL/Design errors/nullpointerexception.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Due to mux
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/no_driver_on.html b/master/SpinalHDL/Design errors/no_driver_on.html index f5078d25e4c..37a1ee0b2ea 100644 --- a/master/SpinalHDL/Design errors/no_driver_on.html +++ b/master/SpinalHDL/Design errors/no_driver_on.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/latch_detected.html b/master/SpinalHDL/Design errors/latch_detected.html index 86048f59bfc..167b61add51 100644 --- a/master/SpinalHDL/Design errors/latch_detected.html +++ b/master/SpinalHDL/Design errors/latch_detected.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Design errors
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/iobundle.html b/master/SpinalHDL/Design errors/iobundle.html index 6d7c59aa0c0..8725c69f18c 100644 --- a/master/SpinalHDL/Design errors/iobundle.html +++ b/master/SpinalHDL/Design errors/iobundle.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/index.html b/master/SpinalHDL/Design errors/index.html index d53f0edcfe2..69681cc42c5 100644 --- a/master/SpinalHDL/Design errors/index.html +++ b/master/SpinalHDL/Design errors/index.html @@ -420,7 +420,7 @@ - Unnamed signal handling
False-positives
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/hierarchy_violation.html b/master/SpinalHDL/Design errors/hierarchy_violation.html index 8dc8a352de4..b70ca05299a 100644 --- a/master/SpinalHDL/Design errors/hierarchy_violation.html +++ b/master/SpinalHDL/Design errors/hierarchy_violation.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Design errors/combinatorial_loop.html b/master/SpinalHDL/Design errors/combinatorial_loop.html index 3ffdb81b20b..47a491ead3b 100644 --- a/master/SpinalHDL/Design errors/combinatorial_loop.html +++ b/master/SpinalHDL/Design errors/combinatorial_loop.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Type cast
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Data types/index.html b/master/SpinalHDL/Data types/index.html index 127186975ca..2099f1b2694 100644 --- a/master/SpinalHDL/Data types/index.html +++ b/master/SpinalHDL/Data types/index.html @@ -420,7 +420,7 @@ - Unnamed signal handling
ComparisonmyBool := color1 === color2 // Compare all elements of the bundle // is equivalent to: -//myBool := color1.r === color2.r && color1.g === color2.g && color1.b === color2.b +// myBool := color1.r === color2.r && color1.g === color2.g && color1.b === color2.b @@ -1462,7 +1462,7 @@
master/slave
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Data types/enum.html b/master/SpinalHDL/Data types/enum.html index 9ea62744319..f94019483bc 100644 --- a/master/SpinalHDL/Data types/enum.html +++ b/master/SpinalHDL/Data types/enum.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Description
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Data types/bundle.html b/master/SpinalHDL/Data types/bundle.html index c01317c8953..41a951197e7 100644 --- a/master/SpinalHDL/Data types/bundle.html +++ b/master/SpinalHDL/Data types/bundle.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Misc diff --git a/master/SpinalHDL/Data types/bool.html b/master/SpinalHDL/Data types/bool.html index 06472655c61..527d56d9eea 100644 --- a/master/SpinalHDL/Data types/bool.html +++ b/master/SpinalHDL/Data types/bool.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1363,7 +1363,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1416,7 +1416,7 @@
example
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Done diff --git a/master/SpinalHDL/Developers area/howtodocument.html b/master/SpinalHDL/Developers area/howtodocument.html index 8bc05c7131a..ebc43695694 100644 --- a/master/SpinalHDL/Developers area/howtodocument.html +++ b/master/SpinalHDL/Developers area/howtodocument.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1348,7 +1348,7 @@
Developers area
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1308,7 +1308,7 @@
Publish locally
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1259,20 +1259,20 @@
mySignal.removeAssignments : Will remove all previous := affecting the given signal
-mySignal.removeStatement : Will void the existance of the signal
+mySignal.removeStatement : Will void the existence of the signal
mySignal.setAsDirectionLess : Will turn a in / out signal into a internal signal
mySignal.setName : Enforce a given name on a signal (there is many other variants)
mySubComponent.mySignal.pull() : Will provide a readable copy of the given signal, even if that signal is somewhere else in the hierarchy
myComponent.rework{ myCode } : Execute myCode in the context of myComponent, allowing modifying it with the user API
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -730,27 +730,27 @@
- Bus @@ -1488,11 +1488,11 @@
Declaration syntaxval myBool := myUInt === U(7 -> true,(6 downto 0) -> false) val myBool := myUInt === U(myUInt.range -> true) -//For assignment purposes, you can omit the B/U/S, which also alow the use of the [default -> ???] feature -myUInt := (default -> true) //Assign myUInt with "11111111" -myUInt := (myUInt.range -> true) //Assign myUInt with "11111111" -myUInt := (7 -> true,default -> false) //Assign myUInt with "10000000" -myUInt := ((4 downto 1) -> true,default -> false) //Assign myUInt with "00011110" +// For assignment purposes, you can omit the B/U/S, which also alow the use of the [default -> ???] feature +myUInt := (default -> true) // Assign myUInt with "11111111" +myUInt := (myUInt.range -> true) // Assign myUInt with "11111111" +myUInt := (7 -> true,default -> false) // Assign myUInt with "10000000" +myUInt := ((4 downto 1) -> true,default -> false) // Assign myUInt with "00011110"
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1319,7 +1319,7 @@
Advanced ones
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1309,7 +1309,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1314,7 +1314,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1270,7 +1270,7 @@
Pinesec
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1244,7 +1244,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1405,14 +1405,14 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1354,32 +1354,32 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1318,7 +1318,7 @@
Intermediates ones
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1368,14 +1368,14 @@
Every 2000 cycles, it sends the switches input value to the UART.
-- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1444,8 +1444,8 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1393,7 +1393,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1241,22 +1241,22 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1308,7 +1308,7 @@
Color summing
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1286,7 +1286,7 @@
Counter with clear
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1289,7 +1289,7 @@
Simple ones
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1284,13 +1284,13 @@
TopLevel definition val pll = new PLL pll.io.clkIn := io.clk100Mhz - //Create a new clock domain named 'core' + // Create a new clock domain named 'core' val coreClockDomain = ClockDomain.internal( name = "core", frequency = FixedFrequency(200 MHz) // This frequency specification can be used ) // by coreClockDomain users to do some calculations - //Drive clock and reset signals of the coreClockDomain previously created + // Drive clock and reset signals of the coreClockDomain previously created coreClockDomain.clock := pll.io.clkOut coreClockDomain.reset := ResetCtrl.asyncAssertSyncDeassert( input = io.aReset || ! pll.io.isLocked, @@ -1298,9 +1298,9 @@
TopLevel definition ) } - //Create a ClockingArea which will be under the effect of the clkCtrl.coreClockDomain + // Create a ClockingArea which will be under the effect of the clkCtrl.coreClockDomain val core = new ClockingArea(clkCtrl.coreClockDomain) { - //Do your stuff which use coreClockDomain here + // Do your stuff which use coreClockDomain here val counter = Reg(UInt(4 bits)) init 0 counter := counter + 1 io.result := counter @@ -1340,7 +1340,7 @@
TopLevel definition
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Carry addera and
b, and aresultoutput. At any time,resultwill be the sum ofaandb(combinatorial). This sum is manually done by a carry adder logic. -diff --git a/master/SpinalHDL/Examples/Simple ones/pll_resetctrl.html b/master/SpinalHDL/Examples/Simple ones/pll_resetctrl.html index 0a94daa62d3..98fd70c81c6 100644 --- a/master/SpinalHDL/Examples/Simple ones/pll_resetctrl.html +++ b/master/SpinalHDL/Examples/Simple ones/pll_resetctrl.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Simple ones/index.html b/master/SpinalHDL/Examples/Simple ones/index.html index 1271db6cc7d..a69f989b3de 100644 --- a/master/SpinalHDL/Examples/Simple ones/index.html +++ b/master/SpinalHDL/Examples/Simple ones/index.html @@ -420,7 +420,7 @@case class CarryAdder(size : Int) extends Component{ +
diff --git a/master/SpinalHDL/Examples/Simple ones/counter_with_clear.html b/master/SpinalHDL/Examples/Simple ones/counter_with_clear.html index 96b4bf1dd79..0bc61f00c1c 100644 --- a/master/SpinalHDL/Examples/Simple ones/counter_with_clear.html +++ b/master/SpinalHDL/Examples/Simple ones/counter_with_clear.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Simple ones/color_summing.html b/master/SpinalHDL/Examples/Simple ones/color_summing.html index d9fd01188b8..cba25a9f25b 100644 --- a/master/SpinalHDL/Examples/Simple ones/color_summing.html +++ b/master/SpinalHDL/Examples/Simple ones/color_summing.html @@ -420,7 +420,7 @@case class CarryAdder(size : Int) extends Component { val io = new Bundle { val a = in UInt(size bits) val b = in UInt(size bits) - val result = out UInt(size bits) //result = a + b + val result = out UInt(size bits) // result = a + b } - var c = False //Carry, like a VHDL variable + var c = False // Carry, like a VHDL variable for (i <- 0 until size) { - //Create some intermediate value in the loop scope. + // Create some intermediate value in the loop scope. val a = io.a(i) val b = io.b(i) - //The carry adder's asynchronous logic + // The carry adder's asynchronous logic io.result(i) := a ^ b ^ c - c \= (a & b) | (a & c) | (b & c); //variable assignment + c \= (a & b) | (a & c) | (b & c); // variable assignment } } @@ -1296,7 +1296,7 @@
Carry adder
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Usage diff --git a/master/SpinalHDL/Examples/Simple ones/carry_adder.html b/master/SpinalHDL/Examples/Simple ones/carry_adder.html index 26958a129e3..8628df4fd0f 100644 --- a/master/SpinalHDL/Examples/Simple ones/carry_adder.html +++ b/master/SpinalHDL/Examples/Simple ones/carry_adder.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1275,7 +1275,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1371,7 +1371,7 @@ diff --git a/master/SpinalHDL/Examples/index.html b/master/SpinalHDL/Examples/index.html index b7981c80f75..c22ee4fbf01 100644 --- a/master/SpinalHDL/Examples/index.html +++ b/master/SpinalHDL/Examples/index.html @@ -420,7 +420,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1263,7 +1263,7 @@
Getting started
@@ -1300,7 +1300,7 @@object MyMainObject { def main(args: Array[String]) { - SpinalVhdl(new TheComponentThatIWantToGenerate(constructionArguments)) //Or SpinalVerilog + SpinalVhdl(new TheComponentThatIWantToGenerate(constructionArguments)) // Or SpinalVerilog } }
Getting started
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Unnamed signal handling
RGB to gray
diff --git a/master/SpinalHDL/Examples/Simple ones/sinus_rom.html b/master/SpinalHDL/Examples/Simple ones/sinus_rom.html index eed7111f9ff..dac4c131ab9 100644 --- a/master/SpinalHDL/Examples/Simple ones/sinus_rom.html +++ b/master/SpinalHDL/Examples/Simple ones/sinus_rom.html @@ -420,7 +420,7 @@case class RgbToGray() extends Component { - val io = new Bundle{ + val io = new Bundle { val clear = in Bool() val r,g,b = in UInt(8 bits) @@ -1297,7 +1297,7 @@
RGB to gray io.wr := True io.data := gray - when(io.clear){ + when(io.clear) { gray := 0 address.clear() io.wr := False @@ -1336,7 +1336,7 @@
RGB to gray
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1243,7 +1243,7 @@
For conciseness, let’s assume that SystemVerilog is a recent revision of Verilog.
When reading this, we should not underestimate how much our attachment for our -favourite HDL will bias our judgement.
+favorite HDL will bias our judgement.
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1276,9 +1276,9 @@
External assertions
import spinal.core._ -//Here is our DUT +// Here is our DUT class LimitedCounter extends Component { - //The value register will always be between [2:10] + // The value register will always be between [2:10] val value = Reg(UInt(4 bits)) init(2) when(value < 10) { value := value + 1 @@ -1339,7 +1339,7 @@
External stimulus
@@ -1525,7 +1525,7 @@class LimitedCounterInc extends Component { - //Only increment the value when the inc input is set + // Only increment the value when the inc input is set val inc = in Bool() val value = Reg(UInt(4 bits)) init(2) when(inc && value < 10) { @@ -1402,7 +1402,7 @@
Assuming memory content // Allow the write anything but value 1 in the ram anyseq(dut.write) - clockDomain.withoutReset() { //As the memory write can occur during reset, we need to ensure the assume apply there too + clockDomain.withoutReset() { // As the memory write can occur during reset, we need to ensure the assume apply there too assume(dut.write.data =/= 1) } @@ -1429,7 +1429,7 @@
Assertions / clock / reset
Specifying the initial value of a signal
-For instance, for the reset signal of the current clockdomain (usefull at the top)
+For instance, for the reset signal of the current clockdomain (useful at the top)
@@ -1445,12 +1445,12 @@ClockDomain.current.readResetWire initial(False)
Memory content (Mem)
// Manual access for(i <- 0 until dut.ram.wordCount) { - assumeInitial(dut.ram(i) =/= X) //No occurence of the word X + assumeInitial(dut.ram(i) =/= X) // No occurrence of the word X } -assumeInitial(!dut.ram.formalContains(X)) //No occurence of the word X +assumeInitial(!dut.ram.formalContains(X)) // No occurrence of the word X -assumeInitial(dut.ram.formalCount(X) === 1) //only one occurence of the word X +assumeInitial(dut.ram.formalCount(X) === 1) // only one occurrence of the word X
Formal primitives
pastValidAfterReset()Bool
Simliar to
pastValid, where only difference is that this would take reset into account. Can be understood aspastValid & past(!reset).Similar to
pastValid, where only difference is that this would take reset into account. Can be understood aspastValid & past(!reset). - Unnamed signal handling
Component and io definition
Horizontal and vertical logic
-The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal syncronization signal as to increment.
-Let’s define
+HVArea, which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical syncronization.The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal synchronization signal as to increment.
+Let’s define
HVArea, which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical synchronization.case class VgaCtrl(rgbConfig: RgbConfig, timingsWidth: Int = 12) extends Component { ... case class HVArea(timingsHV: VgaTimingsHV, enable: Bool) extends Area { @@ -1506,19 +1506,19 @@
Bonus
Let’s add a function to
VgaCtrlthat can be called from the parent component to feedVgaCtrlby using thisStreamofFragmentof RGB.diff --git a/master/SpinalHDL/Foreword/index.html b/master/SpinalHDL/Foreword/index.html index aea7b64968e..65fa340a728 100644 --- a/master/SpinalHDL/Foreword/index.html +++ b/master/SpinalHDL/Foreword/index.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Simple ones/rgb_to_gray.html b/master/SpinalHDL/Examples/Simple ones/rgb_to_gray.html index 7d661a7b145..8c3c3c49fe1 100644 --- a/master/SpinalHDL/Examples/Simple ones/rgb_to_gray.html +++ b/master/SpinalHDL/Examples/Simple ones/rgb_to_gray.html @@ -420,7 +420,7 @@case class VgaCtrl(rgbConfig: RgbConfig, timingsWidth: Int = 12) extends Component { ... - def feedWith(that : Stream[Fragment[Rgb]]): Unit ={ + def feedWith(that : Stream[Fragment[Rgb]]): Unit = { io.pixels << that.toStreamOfFragment val error = RegInit(False) - when(io.error){ + when(io.error) { error := True } - when(that.isLast){ + when(that.isLast) { error := False } io.softReset := error - when(error){ + when(error) { that.ready := True } } @@ -1558,7 +1558,7 @@
Bonus diff --git a/master/SpinalHDL/Examples/Simple ones/apb3.html b/master/SpinalHDL/Examples/Simple ones/apb3.html index 0c81b235871..aa18deb56a1 100644 --- a/master/SpinalHDL/Examples/Simple ones/apb3.html +++ b/master/SpinalHDL/Examples/Simple ones/apb3.html @@ -420,7 +420,7 @@
Why moving away from traditional HDL
@@ -1393,7 +1393,7 @@VHDL and Verilog are so verboseval vgaCtrl = Axi4VgaCtrl(vgaCtrlConfig) // Instantiate an APB3 decoder -// - Drived by the apbBridge +// - Driven by the apbBridge // - Map each peripheral in a memory region val apbDecoder = Apb3Decoder( master = apbBridge.io.apb, @@ -1457,7 +1457,7 @@
Meta Hardware Description capabilities
diff --git a/master/SpinalHDL/Formal verification/index.html b/master/SpinalHDL/Formal verification/index.html index 1413740d8cb..a94729640b6 100644 --- a/master/SpinalHDL/Formal verification/index.html +++ b/master/SpinalHDL/Formal verification/index.html @@ -420,7 +420,7 @@// Define a new state machine -val fsm = new StateMachine{ +val fsm = new StateMachine { // Define all states val stateA, stateB, stateC = new State @@ -1467,14 +1467,14 @@
Meta Hardware Description capabilities // Define a register used into the state machine val counter = Reg(UInt(8 bits)) init (0) - // Define the state machine behaviour for each state + // Define the state machine behavior for each state stateA.whenIsActive (goto(stateB)) stateB.onEntry(counter := 0) stateB.onExit(io.result := True) stateB.whenIsActive { counter := counter + 1 - when(counter === 4){ + when(counter === 4) { goto(stateC) } } @@ -1524,7 +1524,7 @@
Meta Hardware Description capabilities
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
UART configuration enums
Let’s define bundles that will be used as IO elements to setup
UartCtrl.case class UartCtrlFrameConfig(g: UartCtrlGenerics) extends Bundle { - val dataLength = UInt(log2Up(g.dataWidthMax) bits) //Bit count = dataLength + 1 + val dataLength = UInt(log2Up(g.dataWidthMax) bits) // Bit count = dataLength + 1 val stop = UartStopType() val parity = UartParityType() } case class UartCtrlConfig(g: UartCtrlGenerics) extends Bundle { val frame = UartCtrlFrameConfig(g) - val clockDivider = UInt(g.clockDividerWidth bits) //see UartCtrlGenerics.clockDividerWidth for calculation + val clockDivider = UInt(g.clockDividerWidth bits) // see UartCtrlGenerics.clockDividerWidth for calculation def setClockDivider(baudrate: Double, clkFrequency: HertzNumber = ClockDomain.current.frequency.getValue): Unit = { clockDivider := (clkFrequency.toDouble / baudrate / g.rxSamplePerBit).toInt @@ -1520,8 +1520,8 @@
UartCtrlTx io.write.ready := False switch(state) { - is(IDLE){ - when(io.write.valid && clockDivider.tick){ + is(IDLE) { + when(io.write.valid && clockDivider.tick) { state := START } } @@ -1711,7 +1711,7 @@
UartCtrlRx val parity = Reg(Bool()) val shifter = Reg(io.read.payload) - //Parity calculation + // Parity calculation when(bitTimer.tick) { parity := parity ^ sampler.value } @@ -1788,7 +1788,7 @@
UartCtrl val tx = new UartCtrlTx(g) val rx = new UartCtrlRx(g) - //Clock divider used by RX and TX + // Clock divider used by RX and TX val clockDivider = new Area { val counter = Reg(UInt(g.clockDividerWidth bits)) init 0 val tick = counter === 0 @@ -1889,8 +1889,8 @@
Example with test bench
Each time a byte is received from the UART, it writes it on the leds output.
case class UartCtrlUsageExample() extends Component{ - val io = new Bundle{ +
diff --git a/master/SpinalHDL/Examples/Intermediates ones/vga.html b/master/SpinalHDL/Examples/Intermediates ones/vga.html index 15c3300d2c1..b35128d1297 100644 --- a/master/SpinalHDL/Examples/Intermediates ones/vga.html +++ b/master/SpinalHDL/Examples/Intermediates ones/vga.html @@ -420,7 +420,7 @@case class UartCtrlUsageExample() extends Component { + val io = new Bundle { val uart = master(Uart()) val switches = in Bits(8 bits) val leds = out Bits(8 bits) @@ -1899,15 +1899,15 @@
Example with test bench val uartCtrl = new UartCtrl() // set config manually to show that this is still OK uartCtrl.io.config.setClockDivider(921600) - uartCtrl.io.config.frame.dataLength := 7 //8 bits + uartCtrl.io.config.frame.dataLength := 7 // 8 bits uartCtrl.io.config.frame.parity := UartParityType.NONE uartCtrl.io.config.frame.stop := UartStopType.ONE uartCtrl.io.uart <> io.uart - //Assign io.led with a register loaded each time a byte is received + // Assign io.led with a register loaded each time a byte is received io.leds := uartCtrl.io.read.toReg() - //Write the value of switch on the uart each 2000 cycles + // Write the value of switch on the uart each 2000 cycles val write = Stream(Bits(8 bits)) write.valid := CounterFreeRun(2000).willOverflow write.payload := io.switches @@ -1975,7 +1975,7 @@
Bonus: Having fun with Stream
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Bundle definition
And now the implementation. The one below is a very simple one without pipelining / multi-threading.
diff --git a/master/SpinalHDL/Examples/Intermediates ones/uart.html b/master/SpinalHDL/Examples/Intermediates ones/uart.html index 386ba2f9933..715bb3c2cc9 100644 --- a/master/SpinalHDL/Examples/Intermediates ones/uart.html +++ b/master/SpinalHDL/Examples/Intermediates ones/uart.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Intermediates ones/index.html b/master/SpinalHDL/Examples/Intermediates ones/index.html index 2b6189d353e..6543c60afea 100644 --- a/master/SpinalHDL/Examples/Intermediates ones/index.html +++ b/master/SpinalHDL/Examples/Intermediates ones/index.html @@ -420,7 +420,7 @@case class PixelSolver(g: PixelSolverGenerics) extends Component { - val io = new Bundle{ + val io = new Bundle { val cmd = slave Stream(PixelTask(g)) val rsp = master Stream(PixelResult(g)) } import g._ - //Define states + // Define states val x, y = Reg(fixType) init(0) val iteration = Reg(iterationType) init(0) - //Do some shared calculation + // Do some shared calculation val xx = x*x val yy = y*y val xy = x*y - //Apply default assignment + // Apply default assignment io.cmd.ready := False io.rsp.valid := False io.rsp.iteration := iteration when(io.cmd.valid) { - //Is the mandelbrot iteration done ? + // Is the mandelbrot iteration done ? when(xx + yy >= 4.0 || iteration === iterationLimit) { io.rsp.valid := True - when(io.rsp.ready){ + when(io.rsp.ready) { io.cmd.ready := True x := 0 y := 0 @@ -1426,7 +1426,7 @@
Component implementation
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Specificationticks bool can be actived if the corresponding
ticksEnablebit is high. +Each
ticksbool can be activated if the correspondingticksEnablebit is high.clearsEnable
RW
len(clears)
0
16
Each
clearsbool can be actived if the correspondingclearsEnablebit is high.Each
clearsbool can be activated if the correspondingclearsEnablebit is high.limit
RW
Usage } } - //Prescaler is very similar to the timer, it mainly integrates a piece of auto reload logic. + // Prescaler is very similar to the timer, it mainly integrates a piece of auto reload logic. val prescaler = Prescaler(width = 16) val timerA = Timer(width = 32) @@ -1559,7 +1559,7 @@
Usage diff --git a/master/SpinalHDL/Examples/Intermediates ones/fractal.html b/master/SpinalHDL/Examples/Intermediates ones/fractal.html index d638133c420..73e0cc520b0 100644 --- a/master/SpinalHDL/Examples/Intermediates ones/fractal.html +++ b/master/SpinalHDL/Examples/Intermediates ones/fractal.html @@ -420,7 +420,7 @@
For Component
For interfaces implement IMasterSlave
There could be functions in name
+Master/Slave are target interface type, so thatformalAssertsMaster,formalAssertsSlave,formalAssumesMaster,formalAssumesSlaveorformalCovers. -Master/Slave are target interface type, so thatformalAssertsMastercan be understand as “formal verfication assertions for master interface”.formalAssertsMastercan be understand as “formal verification assertions for master interface”. @@ -1585,7 +1585,7 @@For interfaces implement IMasterSlave
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1274,7 +1274,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1275,7 +1275,7 @@
Cheatsheets
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Core diff --git a/master/SpinalHDL/Getting Started/Cheatsheets/index.html b/master/SpinalHDL/Getting Started/Cheatsheets/index.html index a8c7654c264..6dd979ff761 100644 --- a/master/SpinalHDL/Getting Started/Cheatsheets/index.html +++ b/master/SpinalHDL/Getting Started/Cheatsheets/index.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Introduction
Implementation
This implementation avoid the use of Vec. Instead, it use Area which allow to mix signal, registers and logic definitions in each slot.
-Note that the reader API is for SpinalHDL version comming after 1.9.1
+Note that the reader API is for SpinalHDL version coming after 1.9.1
diff --git a/master/SpinalHDL/Getting Started/Cheatsheets/core.html b/master/SpinalHDL/Getting Started/Cheatsheets/core.html index 9fa9fd7ca9f..36b956a589c 100644 --- a/master/SpinalHDL/Getting Started/Cheatsheets/core.html +++ b/master/SpinalHDL/Getting Started/Cheatsheets/core.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Advanced ones/timer.html b/master/SpinalHDL/Examples/Advanced ones/timer.html index 00b110b5015..f3a4ad6461f 100644 --- a/master/SpinalHDL/Examples/Advanced ones/timer.html +++ b/master/SpinalHDL/Examples/Advanced ones/timer.html @@ -420,7 +420,7 @@package spinaldoc.examples.advanced import spinal.core._ @@ -1252,39 +1252,39 @@
Implementationimport scala.language.postfixOps case class SlotsDemo(slotsCount : Int) extends Component { - //... + // ... - //Create the hardware for each slot - //Note each slot is an Area, not a Bundle - val slots = for(i <- 0 until slotsCount) yield new Area{ - //Because the slot is an Area, we can define mix signal, registers, logic definitions - //Here are the registers for each slots + // Create the hardware for each slot + // Note each slot is an Area, not a Bundle + val slots = for(i <- 0 until slotsCount) yield new Area { + // Because the slot is an Area, we can define mix signal, registers, logic definitions + // Here are the registers for each slots val valid = RegInit(False) val address = Reg(UInt(8 bits)) - val age = Reg(UInt(16 bits)) //Will count since how many cycles the slot is valid + val age = Reg(UInt(16 bits)) // Will count since how many cycles the slot is valid - //Here is some hardware behaviour for each slots - //Implement the age logic - when(valid){ + // Here is some hardware behavior for each slots + // Implement the age logic + when(valid) { age := age + 1 } - //removeIt will be used as a slot interface later on + // removeIt will be used as a slot interface later on val removeIt = False - when(removeIt){ + when(removeIt) { valid := False } } - //Logic to allocate a new slot - val insert = new Area{ - val cmd = Stream(UInt(8 bits)) //interface to issue requests + // Logic to allocate a new slot + val insert = new Area { + val cmd = Stream(UInt(8 bits)) // interface to issue requests val free = slots.map(!_.valid) - val freeOh = OHMasking.first(free) //Get the first free slot (on hot mask) - cmd.ready := free.orR //Only allow cmd when there is a free slot - when(cmd.fire){ - //slots.onMask(freeOh)(code) will execute the code for each slot where the corresponding freeOh bit is set + val freeOh = OHMasking.first(free) // Get the first free slot (on hot mask) + cmd.ready := free.orR // Only allow cmd when there is a free slot + when(cmd.fire) { + // slots.onMask(freeOh)(code) will execute the code for each slot where the corresponding freeOh bit is set slots.onMask(freeOh){slot => slot.valid := True slot.address := cmd.payload @@ -1293,21 +1293,21 @@
Implementation } } - //Logic to remove the slots which match a given address (assuming there is not more than one match) - val remove = new Area{ - val cmd = Flow(UInt(8 bits))//interface to issue requests - val oh = slots.map(s => s.valid && s.address === cmd.payload) //oh meaning "one hot" - when(cmd.fire){ + // Logic to remove the slots which match a given address (assuming there is not more than one match) + val remove = new Area { + val cmd = Flow(UInt(8 bits)) // interface to issue requests + val oh = slots.map(s => s.valid && s.address === cmd.payload) // oh meaning "one hot" + when(cmd.fire) { slots.onMask(oh){ slot => slot.removeIt := True } } - val reader = slots.reader(oh) //Create a facility to read the slots using "oh" as index - val age = reader(_.age) //Age of the slot which is selected by "oh" + val reader = slots.reader(oh) // Create a facility to read the slots using "oh" as index + val age = reader(_.age) // Age of the slot which is selected by "oh" } - //... + // ... } object SlotsDemo extends App { @@ -1320,7 +1320,7 @@
Implementation
For instance, this kind of slot pattern is used in Tilelink coherency hub to keep track of all ongoing memory probes in flight:
-As well in the DRAM / SDR / DDR memory controller to implement the handeling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :
+As well in the DRAM / SDR / DDR memory controller to implement the handling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :
As well in the NaxRiscv (out of order CPU) load-store-unit to handle the store-queue / load-queue hardware (a bit too scary to show here in the doc XD)
@@ -1356,7 +1356,7 @@In practice
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
ImplementationApb3UartCtrl component which instantiates a
UartCtrland creates the memory mapping logic between it and the APB3 bus:
diff --git a/master/SpinalHDL/Examples/Advanced ones/slots.html b/master/SpinalHDL/Examples/Advanced ones/slots.html index a7f20373691..d307a2baacf 100644 --- a/master/SpinalHDL/Examples/Advanced ones/slots.html +++ b/master/SpinalHDL/Examples/Advanced ones/slots.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Advanced ones/pinesec.html b/master/SpinalHDL/Examples/Advanced ones/pinesec.html index 89a52376af1..c720c28bf6d 100644 --- a/master/SpinalHDL/Examples/Advanced ones/pinesec.html +++ b/master/SpinalHDL/Examples/Advanced ones/pinesec.html @@ -420,7 +420,7 @@case class Apb3UartCtrl(uartCtrlConfig: UartCtrlGenerics, rxFifoDepth: Int) extends Component { - val io = new Bundle{ + val io = new Bundle { val bus = slave(Apb3(Apb3UartCtrl.getApb3Config)) val uart = master(Uart()) } @@ -1388,7 +1388,7 @@
Implementation
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1274,7 +1274,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1274,7 +1274,7 @@
Symbolic
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Lib diff --git a/master/SpinalHDL/Getting Started/Cheatsheets/symbolic.html b/master/SpinalHDL/Getting Started/Cheatsheets/symbolic.html index c9a3094dbb6..47c0f1b492a 100644 --- a/master/SpinalHDL/Getting Started/Cheatsheets/symbolic.html +++ b/master/SpinalHDL/Getting Started/Cheatsheets/symbolic.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1299,7 +1299,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1633,7 +1633,7 @@
Meta hardware description
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- Unnamed signal handling
Help for VHDL people diff --git a/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.html b/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.html index 5d4b0e1f0f7..ee437d7f0c0 100644 --- a/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.html +++ b/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1243,7 +1243,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1307,7 +1307,7 @@
Linux Installation xzf <file that you downloaded>
- Unnamed signal handling
Entity and architectureIn SpinalHDL, a VHDL entity and architecture are both defined inside a
Component.Here is an example of a component which has 3 inputs (
a,b,c) and an output (result). This component also has anoffsetconstruction parameter (like a VHDL generic).diff --git a/master/SpinalHDL/Getting Started/Install and setup.html b/master/SpinalHDL/Getting Started/Install and setup.html index a35a3fb5573..ab3a240469d 100644 --- a/master/SpinalHDL/Getting Started/Install and setup.html +++ b/master/SpinalHDL/Getting Started/Install and setup.html @@ -420,7 +420,7 @@case class MyComponent(offset: Int) extends Component { - val io = new Bundle{ + val io = new Bundle { val a, b, c = in UInt(8 bits) val result = out UInt(8 bits) } @@ -1445,7 +1445,7 @@
Process blocks
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
JTAG state machine val state = RegNext(stateNext) randBoot() stateNext := state.mux( - default -> (jtag.tms ? RESET | IDLE), //RESET + default -> (jtag.tms ? RESET | IDLE), // RESET IDLE -> (jtag.tms ? DR_SELECT | IDLE), IR_SELECT -> (jtag.tms ? RESET | IR_CAPTURE), IR_CAPTURE -> (jtag.tms ? IR_EXIT1 | IR_SHIFT), @@ -1389,7 +1389,7 @@
JTAG TAP class interfaceJtagTap implement this abstract interface:
-Additions to-class JtagTapdiff --git a/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.html b/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.html index 025227a8e7b..380abc25621 100644 --- a/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.html +++ b/master/SpinalHDL/Getting Started/Help for VHDL people/vhdl_perspective.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Getting Started/Help for VHDL people/index.html b/master/SpinalHDL/Getting Started/Help for VHDL people/index.html index a482b9a6413..2b2870399fa 100644 --- a/master/SpinalHDL/Getting Started/Help for VHDL people/index.html +++ b/master/SpinalHDL/Getting Started/Help for VHDL people/index.html @@ -420,7 +420,7 @@class JtagTap(val jtag: Jtag, ...) extends Area with JtagTapAccess{ +
diff --git a/master/SpinalHDL/Getting Started/Cheatsheets/lib.html b/master/SpinalHDL/Getting Started/Cheatsheets/lib.html index 0f3d7a03c25..26c5e8ee557 100644 --- a/master/SpinalHDL/Getting Started/Cheatsheets/lib.html +++ b/master/SpinalHDL/Getting Started/Cheatsheets/lib.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.html b/master/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.html index 72fc13e9be3..da4b3f470c4 100644 --- a/master/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.html +++ b/master/SpinalHDL/Examples/Advanced ones/memory_mapped_uart.html @@ -420,7 +420,7 @@class JtagTap(val jtag: Jtag, ...) extends Area with JtagTapAccess { ... override def getTdi: Bool = jtag.tdi override def setTdo(value: Bool): Unit = jtag.tdo := value @@ -1574,7 +1574,7 @@
Usage demonstration
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
To use oss-cad-suite in a shell you need to load it’s environment, e.g. via
+souce <path to oss-cad-suite>/environment.To use oss-cad-suite in a shell you need to load it’s environment, e.g. via
source <path to oss-cad-suite>/environment.Mac OS X Installation
@@ -1558,7 +1558,7 @@Using Spinal on SpinalHDL code
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
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- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1277,7 +1277,7 @@ diff --git a/master/SpinalHDL/Getting Started/SBT.html b/master/SpinalHDL/Getting Started/SBT.html index 3e8d17236b2..870daa27082 100644 --- a/master/SpinalHDL/Getting Started/SBT.html +++ b/master/SpinalHDL/Getting Started/SBT.html @@ -420,7 +420,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1339,7 +1339,7 @@ diff --git a/master/SpinalHDL/Getting Started/Scala Guide/basics.html b/master/SpinalHDL/Getting Started/Scala Guide/basics.html index 522dc8f952b..b719aeaf253 100644 --- a/master/SpinalHDL/Getting Started/Scala Guide/basics.html +++ b/master/SpinalHDL/Getting Started/Scala Guide/basics.html @@ -420,7 +420,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1291,7 +1291,7 @@
Variables
var number = 0 //The type of 'number' is inferred as an Int during compilation. +
var number = 0 // The type of 'number' is inferred as an Int during compilation.
However, it’s not very common to use
@@ -1372,7 +1372,7 @@varin Scala. Instead, constant values defined byvalare often used:Apply } val array = new Array() -val value = array(4) //array(4) is interpreted as array.apply(4) and will return 7 +val value = array(4) // array(4) is interpreted as array.apply(4) and will return 7
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+
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- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1409,7 +1409,7 @@
Parameters
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+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1278,7 +1278,7 @@
Introduction
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+
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- Bus @@ -1390,7 +1390,7 @@
Scala elaboration capabilities (if, for, functional programming)
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
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- Composite in a function
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+
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- Verilog expression splitting
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1284,7 +1284,7 @@ diff --git a/master/SpinalHDL/Getting Started/index.html b/master/SpinalHDL/Getting Started/index.html index 97932cb6f16..57faddd1abe 100644 --- a/master/SpinalHDL/Getting Started/index.html +++ b/master/SpinalHDL/Getting Started/index.html @@ -420,7 +420,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1282,7 +1282,7 @@
Getting Started
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
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+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1377,7 +1377,7 @@
Internal logic
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+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1274,7 +1274,7 @@
Contributing
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+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1293,7 +1293,7 @@
Getting in touch
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- Composite in a function
- Composite chains
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-
+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1283,7 +1283,7 @@
License
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
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+
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- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1288,7 +1288,7 @@
Other learning materials
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
General structurehttps://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala> +
More generally, most of the graph checks and transformations done by SpinalHDL are located in <https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala>
Exploring the datamodel
Here is an example that identifies all adders within the netlist without utilizing shortcuts. :
-diff --git a/master/SpinalHDL/Introduction/Other learning materials.html b/master/SpinalHDL/Introduction/Other learning materials.html index 0d47fa2eb25..6c34a2da012 100644 --- a/master/SpinalHDL/Introduction/Other learning materials.html +++ b/master/SpinalHDL/Introduction/Other learning materials.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Introduction/License.html b/master/SpinalHDL/Introduction/License.html index c49e86dcac2..3ca5d8010c8 100644 --- a/master/SpinalHDL/Introduction/License.html +++ b/master/SpinalHDL/Introduction/License.html @@ -420,7 +420,7 @@object FindAllAddersManualy { - class Toplevel extends Component{ +
diff --git a/master/SpinalHDL/Introduction/Getting in touch.html b/master/SpinalHDL/Introduction/Getting in touch.html index 75863ac04aa..d2a60c5cd24 100644 --- a/master/SpinalHDL/Introduction/Getting in touch.html +++ b/master/SpinalHDL/Introduction/Getting in touch.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Introduction/Contributing.html b/master/SpinalHDL/Introduction/Contributing.html index b97bf2eed14..a59491bb0f9 100644 --- a/master/SpinalHDL/Introduction/Contributing.html +++ b/master/SpinalHDL/Introduction/Contributing.html @@ -420,7 +420,7 @@object FindAllAddersManually { + class Toplevel extends Component { val a,b,c = in UInt(8 bits) val result = out(a + b + c) } import spinal.core.internals._ - class PrintBaseTypes(message : String) extends Phase{ + class PrintBaseTypes(message : String) extends Phase { override def impl(pc: PhaseContext) = { println(message) @@ -1308,10 +1308,10 @@
Exploring the datamodel def main(args: Array[String]): Unit = { val config = SpinalConfig() - //Add a early phase + // Add a early phase config.addTransformationPhase(new PrintBaseTypes("Early")) - //Add a late phase + // Add a late phase config.phasesInserters += {phases => phases.insert(phases.indexWhere(_.isInstanceOf[PhaseVerilog]), new PrintBaseTypes("Late")) } @@ -1339,7 +1339,7 @@
Exploring the datamodelPlease note that in many cases, shortcuts are available. All the recursive processes mentioned earlier could have been replaced by a single one. :
diff --git a/master/SpinalHDL/Introduction/A simple example.html b/master/SpinalHDL/Introduction/A simple example.html index 666fc7d337d..e758683cb81 100644 --- a/master/SpinalHDL/Introduction/A simple example.html +++ b/master/SpinalHDL/Introduction/A simple example.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Getting Started/VSCodium.html b/master/SpinalHDL/Getting Started/VSCodium.html index 3773186dacf..c5af6b741b5 100644 --- a/master/SpinalHDL/Getting Started/VSCodium.html +++ b/master/SpinalHDL/Getting Started/VSCodium.html @@ -420,7 +420,7 @@override def impl(pc: PhaseContext) = { println(message) - pc.walkExpression{ + pc.walkExpression { case op: Operator.BitVector.Add => println(s"Found ${op.left} + ${op.right}") case _ => } @@ -1359,25 +1359,25 @@
Modifying a netlist as a user without plugins
For example, the following code can be used to modify a top-level component by adding a three-stage shift register to each input and output of the component. This is particularly useful for synthesis testing.
--def ffIo[T <: Component](c : T): T ={ +
@@ -1849,18 +1849,18 @@@@ -1441,7 +1441,7 @@def ffIo[T <: Component](c : T): T = { def buf1[T <: Data](that : T) = KeepAttribute(RegNext(that)).addAttribute("DONT_TOUCH") def buf[T <: Data](that : T) = buf1(buf1(buf1(that))) - c.rework{ + c.rework { val ios = c.getAllIo.toList ios.foreach{io => - if(io.getName() == "clk"){ - //Do nothing - } else if(io.isInput){ - io.setAsDirectionLess().allowDirectionLessIo //allowDirectionLessIo is to disable the io Bundle linting + if(io.getName() == "clk") { + // Do nothing + } else if(io.isInput) { + io.setAsDirectionLess().allowDirectionLessIo // allowDirectionLessIo is to disable the io Bundle linting io := buf(in(cloneOf(io).setName(io.getName() + "_wrap"))) - } else if(io.isOutput){ + } else if(io.isOutput) { io.setAsDirectionLess().allowDirectionLessIo out(cloneOf(io).setName(io.getName() + "_wrap")) := buf(io) } else ??? @@ -1409,12 +1409,12 @@
Modifying a netlist as a user without pluginsobject key -when(something){ - if(somehow){ +when(something) { + if(somehow) { get(key) := True } } -when(database(key)){ +when(database(key)) { ... }
User space netlist analysis
Enumerating every ClockDomain in use
In this case, this is accomplished after the elaboration process by utilizing the SpinalHDL report.
-@@ -1812,10 +1812,10 @@object MyTopLevelVerilog extends App{ +
diff --git a/master/SpinalHDL/Developers area/types.html b/master/SpinalHDL/Developers area/types.html index ec4316c8a4f..9176048c618 100644 --- a/master/SpinalHDL/Developers area/types.html +++ b/master/SpinalHDL/Developers area/types.html @@ -419,7 +419,7 @@object MyTopLevelVerilog extends App { class MyTopLevel extends Component { val cdA = ClockDomain.external("rawrr") val regA = cdA(RegNext(False)) @@ -1510,7 +1510,7 @@
Enumerating every ClockDomain in use
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
Vecval x,y,z = UInt(8 bits) val myVecOf_xyz_ref = Vec(x,y,z) -for(element <- myVecOf_xyz_ref){ - element := 0 //Assign x,y,z with the value 0 +for(element <- myVecOf_xyz_ref) { + element := 0 // Assign x,y,z with the value 0 } -myVecOf_xyz_ref(1) := 3 //Assign y with the value 3 +myVecOf_xyz_ref(1) := 3 // Assign y with the value 3
Simple example (RGB/VGA)}
And finaly instantiate your Bundles inside the hardware :
-diff --git a/master/SpinalHDL/Getting Started/Scala Guide/interaction.html b/master/SpinalHDL/Getting Started/Scala Guide/interaction.html index 9674ad6cc71..13dccd93bff 100644 --- a/master/SpinalHDL/Getting Started/Scala Guide/interaction.html +++ b/master/SpinalHDL/Getting Started/Scala Guide/interaction.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Getting Started/Scala Guide/index.html b/master/SpinalHDL/Getting Started/Scala Guide/index.html index 090a350570c..d6f4f96da97 100644 --- a/master/SpinalHDL/Getting Started/Scala Guide/index.html +++ b/master/SpinalHDL/Getting Started/Scala Guide/index.html @@ -420,7 +420,7 @@val vgaIn = VGA(8) //Create a RGB instance +
And finally instantiate your Bundles inside the hardware :
+val vgaIn = VGA(8) // Create a RGB instance val vgaOut = VGA(8) -vgaOut := vgaIn //Assign the whole bundle -vgaOut.color.green := 0 //Fix the green to zero -val vgaInRgbIsBlack = vgaIn.rgb.isBlack //Get if the vgaIn rgb is black +vgaOut := vgaIn // Assign the whole bundle +vgaOut.color.green := 0 // Fix the green to zero +val vgaInRgbIsBlack = vgaIn.rgb.isBlack // Get if the vgaIn rgb is black
If you want to specify your bundle as an input or an output of a Component, you have to do it by the following way :
class MyComponent extends Component { val io = Bundle { - val cmd = in(RGB(8)) //Don't forget the bracket around the bundle. + val cmd = in(RGB(8)) // Don't forget the bracket around the bundle. val rsp = out(RGB(8)) } } @@ -1882,7 +1882,7 @@
Simple example (RGB/VGA) val PWRITE = Bool() val PWDATA = Bits(dataWidth bits) val PRDATA = Bits(dataWidth bits) - val PSLVERROR = if(useSlaveError) Bool() else null //This wire is created only when useSlaveError is true + val PSLVERROR = if(useSlaveError) Bool() else null // This wire is created only when useSlaveError is true } // Example of usage : @@ -1900,7 +1900,7 @@
Simple example (RGB/VGA) selWidth : Int, useSlaveError : Boolean) -class APB(val config: APBConfig) extends Bundle { //[val] config, make the configuration public +class APB(val config: APBConfig) extends Bundle { // [val] config, make the configuration public val PADDR = UInt(config.addressWidth bits) val PSEL = Bits(config.selWidth bits) val PENABLE = Bool() @@ -1942,7 +1942,7 @@
Simple example (RGB/VGA) this } - def asSlave(): this.type = this.asMaster().flip() //Flip reverse all in out configuration. + def asSlave(): this.type = this.asMaster().flip() // Flip reverse all in out configuration. } // Example of usage @@ -1963,7 +1963,7 @@
Simple example (RGB/VGA)
An example of an APB bus that implement this IMasterSlave :
-diff --git a/master/SpinalHDL/Getting Started/Scala Guide/coding_conventions.html b/master/SpinalHDL/Getting Started/Scala Guide/coding_conventions.html index 3aa678ce854..ea3da645ad8 100644 --- a/master/SpinalHDL/Getting Started/Scala Guide/coding_conventions.html +++ b/master/SpinalHDL/Getting Started/Scala Guide/coding_conventions.html @@ -420,7 +420,7 @@//You need to import spinal.lib._ to use IMasterSlave +
@@ -2034,7 +2034,7 @@// You need to import spinal.lib._ to use IMasterSlave import spinal.core._ import spinal.lib._ @@ -1980,14 +1980,14 @@
Simple example (RGB/VGA) val PWRITE = Bool() val PWDATA = Bits(dataWidth bits) val PRDATA = Bits(dataWidth bits) - val PSLVERROR = if(useSlaveError) Bool() else null //This wire is created only when useSlaveError is true + val PSLVERROR = if(useSlaveError) Bool() else null // This wire is created only when useSlaveError is true override def asMaster() : Unit = { out(PADDR,PSEL,PENABLE,PWRITE,PWDATA) in(PREADY,PRDATA) if(useSlaveError) in(PSLVERROR) } - //The asSlave is by default the flipped version of asMaster. + // The asSlave is by default the flipped version of asMaster. }
Enum
diff --git a/master/SpinalHDL/Getting Started/IntelliJ.html b/master/SpinalHDL/Getting Started/IntelliJ.html index ea299df4c1d..51d936e31d6 100644 --- a/master/SpinalHDL/Getting Started/IntelliJ.html +++ b/master/SpinalHDL/Getting Started/IntelliJ.html @@ -420,7 +420,7 @@@@ -2112,8 +2112,8 @@val stateNext = UartCtrlTxState() // Or UartCtrlTxState(encoding=encodingOfYouChoice) stateNext := UartCtrlTxState.sIdle -//You can also import the enumeration to have the visibility on its elements +// You can also import the enumeration to have the visibility on its elements import UartCtrlTxState._ stateNext := sIdle
Literals as signal declaration
diff --git a/master/SpinalHDL/Examples/Advanced ones/jtag.html b/master/SpinalHDL/Examples/Advanced ones/jtag.html index f1b1cdd7dd8..4fc3cda2ce6 100644 --- a/master/SpinalHDL/Examples/Advanced ones/jtag.html +++ b/master/SpinalHDL/Examples/Advanced ones/jtag.html @@ -420,7 +420,7 @@val cond = in Bool() val red = in UInt(4 bits) ... -val valid = False //Bool wire which is by default assigned with False -val value = U"0100" //UInt wire of 4 bits which is by default assigned with 4 +val valid = False // Bool wire which is by default assigned with False +val value = U"0100" // UInt wire of 4 bits which is by default assigned with 4 when(cond) { valid := True value := red @@ -2172,7 +2172,7 @@
Continuous Assignment Literals as signal declaration diff --git a/master/SpinalHDL/Examples/Advanced ones/index.html b/master/SpinalHDL/Examples/Advanced ones/index.html index 0a894f7ad50..ca729565695 100644 --- a/master/SpinalHDL/Examples/Advanced ones/index.html +++ b/master/SpinalHDL/Examples/Advanced ones/index.html @@ -420,7 +420,7 @@
This concept is also applicable for Scala
@@ -1520,7 +1520,7 @@object(static)Templates / Type parameterization
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1237,7 +1237,7 @@
Projects using SpinalHDL
-Note that the following lists are very incompletes.
+Note that the following lists are very incomplete.
Repositories
-
@@ -1332,7 +1332,7 @@
Universities
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1347,7 +1347,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1349,7 +1349,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1281,7 +1281,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1331,7 +1331,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1293,7 +1293,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1248,18 +1248,18 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1321,7 +1321,7 @@
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1242,7 +1242,7 @@
Note
This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available -here and offers better perforance/area/features.
+here and offers better performance/area/features. - Unnamed signal handling
pinsec diff --git a/master/SpinalHDL/Legacy/pinsec/introduction.html b/master/SpinalHDL/Legacy/pinsec/introduction.html index cb13a3370ce..9c36ea061b8 100644 --- a/master/SpinalHDL/Legacy/pinsec/introduction.html +++ b/master/SpinalHDL/Legacy/pinsec/introduction.html @@ -420,7 +420,7 @@
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1297,7 +1297,7 @@
OpenOCD/GDB/Eclipse configuration
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1296,7 +1296,7 @@
Documentation
-Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths.
+Optimize instruction/data caches FMax by moving line hit condition forward into combinatorial paths.
- Composite in a function
- Composite chains
- Composite in a Bundle’s function -
- Unamed signal handling
-
+
- Unnamed signal handling
- Verilog expression splitting
- Verilog long expression splitting
- When statement condition @@ -731,27 +731,27 @@
- Bus @@ -1238,8 +1238,8 @@
AHB-Lite3
-- Configuration and instanciation
++ Configuration and instantiation
First each time you want to create a AHB-Lite3 bus, you will need a configuration object. This configuration object is an
AhbLite3Configand has following arguments : - Unnamed signal handling
How to debug
Contact spinalhdl@gmail.com for more information
@@ -1331,7 +1331,7 @@Todo diff --git a/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html b/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html index 5847b8a0157..777e4ead0cc 100644 --- a/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html +++ b/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Introduction
Defining all IO
-val io = new Bundle{ - //Clocks / reset +
val io = new Bundle { + // Clocks / reset val asyncReset = in Bool() val axiClk = in Bool() val vgaClk = in Bool() - //Main components IO + // Main components IO val jtag = slave(Jtag()) val sdram = master(SdramInterface(IS42x320D.layout)) - //Peripherals IO - val gpioA = master(TriStateArray(32 bits)) //Each pin has an individual output enable control + // Peripherals IO + val gpioA = master(TriStateArray(32 bits)) // Each pin has an individual output enable control val gpioB = master(TriStateArray(32 bits)) val uart = master(Uart()) val vga = master(Vga(RgbConfig(5,6,5))) @@ -1326,23 +1326,23 @@
Reset controller val axiResetUnbuffered = False val coreResetUnbuffered = False - //Implement an counter to keep the reset axiResetOrder high 64 cycles + // Implement an counter to keep the reset axiResetOrder high 64 cycles // Also this counter will automaticly do a reset when the system boot. val axiResetCounter = Reg(UInt(6 bits)) init(0) - when(axiResetCounter =/= U(axiResetCounter.range -> true)){ + when(axiResetCounter =/= U(axiResetCounter.range -> true)) { axiResetCounter := axiResetCounter + 1 axiResetUnbuffered := True } - when(BufferCC(io.asyncReset)){ + when(BufferCC(io.asyncReset)) { axiResetCounter := 0 } - //When an axiResetOrder happen, the core reset will as well - when(axiResetUnbuffered){ + // When an axiResetOrder happen, the core reset will as well + when(axiResetUnbuffered) { coreResetUnbuffered := True } - //Create all reset used later in the design + // Create all reset used later in the design val axiReset = RegNext(axiResetUnbuffered) val coreReset = RegNext(coreResetUnbuffered) val vgaReset = BufferCC(axiResetUnbuffered) @@ -1356,7 +1356,7 @@
Clock domain setup for each system
@@ -1563,9 +1563,9 @@val axiClockDomain = ClockDomain( clock = io.axiClk, reset = resetCtrl.axiReset, - frequency = FixedFrequency(50 MHz) //The frequency information is used by the SDRAM controller + frequency = FixedFrequency(50 MHz) // The frequency information is used by the SDRAM controller ) val coreClockDomain = ClockDomain( @@ -1376,7 +1376,7 @@
Clock domain setup for each systemaxi clocked area :
@@ -1410,8 +1410,8 @@val axi = new ClockingArea(axiClockDomain) { - //Here will come the rest of Pinsec + // Here will come the rest of Pinsec }
RISCV CPU dynamicBranchPredictorCacheSizeLog2 = 7 ) - //The CPU has a systems of plugin which allow to add new feature into the core. - //Those extension are not directly implemented into the core, but are kind of additive logic patch defined in a separated area. + // The CPU has a systems of plugin which allow to add new feature into the core. + // Those extension are not directly implemented into the core, but are kind of additive logic patch defined in a separated area. coreConfig.add(new MulExtension) coreConfig.add(new DivExtension) coreConfig.add(new BarrelShifterFullExtension) @@ -1419,14 +1419,14 @@
RISCV CPU val iCacheConfig = InstructionCacheConfig( cacheSize =4096, bytePerLine =32, - wayCount = 1, //Can only be one for the moment + wayCount = 1, // Can only be one for the moment wrappedMemAccess = true, addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32 ) - //There is the instantiation of the CPU by using all those construction parameters + // There is the instantiation of the CPU by using all those construction parameters new RiscvAxi4( coreConfig = coreConfig, iCacheConfig = iCacheConfig, @@ -1446,7 +1446,7 @@
On chip RAM
val ram = Axi4SharedOnChipRam( dataWidth = 32, byteCount = 4 KiB, - idWidth = 4 //Specify the AXI4 ID width. + idWidth = 4 // Specify the AXI4 ID width. )
VGA controller
-val vgaCtrlConfig = Axi4VgaCtrlGenerics( axiAddressWidth = 32, axiDataWidth = 32, - burstLength = 8, //In Axi words - frameSizeMax = 2048*1512*2, //In byte - fifoSize = 512, //In axi words + burstLength = 8, // In Axi words + frameSizeMax = 2048*1512*2, // In byte + fifoSize = 512, // In axi words rgbConfig = RgbConfig(5,6,5), vgaClock = vgaClockDomain ) @@ -1599,7 +1599,7 @@
AXI4 to APB3 bridge
AXI4 crossbar
The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. -The concept of this factory is to create it, then call many function on it to configure it, and finaly call +The concept of this factory is to create it, then call many function on it to configure it, and finally call the
buildfunction to ask the factory to generate the corresponding hardware :val axiCrossbar = Axi4CrossbarFactory() // Where you will have to call function the the axiCrossbar factory to populate its configuration @@ -1635,7 +1635,7 @@
AXI4 crossbarSome documentation could be find there. In short, it’s just some pipelining and interconnection stuff.
diff --git a/master/SpinalHDL/Legacy/riscv.html b/master/SpinalHDL/Legacy/riscv.html index 9e39d76e401..050631e1808 100644 --- a/master/SpinalHDL/Legacy/riscv.html +++ b/master/SpinalHDL/Legacy/riscv.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Legacy/pinsec/software.html b/master/SpinalHDL/Legacy/pinsec/software.html index 0c7cf8e8b96..0cadd9773fd 100644 --- a/master/SpinalHDL/Legacy/pinsec/software.html +++ b/master/SpinalHDL/Legacy/pinsec/software.html @@ -420,7 +420,7 @@//Pipeline the connection between the crossbar and the apbBridge.io.axi +
@@ -1724,7 +1724,7 @@// Pipeline the connection between the crossbar and the apbBridge.io.axi axiCrossbar.addPipelining(apbBridge.io.axi,(crossbar,bridge) => { crossbar.sharedCmd.halfPipe() >> bridge.sharedCmd crossbar.writeData.halfPipe() >> bridge.writeData @@ -1643,7 +1643,7 @@
AXI4 crossbar crossbar.readRsp << bridge.readRsp }) -//Pipeline the connection between the crossbar and the sdramCtrl.io.axi +// Pipeline the connection between the crossbar and the sdramCtrl.io.axi axiCrossbar.addPipelining(sdramCtrl.io.axi,(crossbar,ctrl) => { crossbar.sharedCmd.halfPipe() >> ctrl.sharedCmd crossbar.writeData >/-> ctrl.writeData @@ -1687,7 +1687,7 @@
Misc core.io.interrupt(1) := timerCtrl.io.interrupt core.io.debugResetIn := resetCtrl.axiReset -when(core.io.debugResetOut){ +when(core.io.debugResetOut) { resetCtrl.coreResetUnbuffered := True }
Misc diff --git a/master/SpinalHDL/Legacy/pinsec/index.html b/master/SpinalHDL/Legacy/pinsec/index.html index 4bc5b7ede4e..ad453bed915 100644 --- a/master/SpinalHDL/Legacy/pinsec/index.html +++ b/master/SpinalHDL/Legacy/pinsec/index.html @@ -420,7 +420,7 @@
Introduction
@@ -1302,7 +1302,7 @@Board support
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Generate the RTL
diff --git a/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html b/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html index 7c12745ee4c..6634783b671 100644 --- a/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html +++ b/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html @@ -420,7 +420,7 @@import spinal.lib.soc.pinsec._ -object PinsecMain{ +object PinsecMain { def main(args: Array[String]) { SpinalVhdl(new Pinsec(100 MHz)) SpinalVerilog(new Pinsec(100 MHz)) @@ -1337,7 +1337,7 @@
Generate the RTL
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Legacy diff --git a/master/SpinalHDL/Legacy/pinsec/hardware.html b/master/SpinalHDL/Legacy/pinsec/hardware.html index 5b22a3195ae..83f68e7cb75 100644 --- a/master/SpinalHDL/Legacy/pinsec/hardware.html +++ b/master/SpinalHDL/Legacy/pinsec/hardware.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Introduction
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Legacy/index.html b/master/SpinalHDL/Legacy/index.html index 0a52d115e85..56176e143f8 100644 --- a/master/SpinalHDL/Legacy/index.html +++ b/master/SpinalHDL/Legacy/index.html @@ -420,7 +420,7 @@ - Unnamed signal handling
How to use an unreleased version of SpinalHDL (but committed on git)? diff --git a/master/SpinalHDL/Introduction/index.html b/master/SpinalHDL/Introduction/index.html index 7802aaeb6cd..80d34f0d7f1 100644 --- a/master/SpinalHDL/Introduction/index.html +++ b/master/SpinalHDL/Introduction/index.html @@ -420,7 +420,7 @@
- Unnamed signal handling
Advantages of using SpinalHDL over VHDL / Verilog diff --git a/master/SpinalHDL/Introduction/faq.html b/master/SpinalHDL/Introduction/faq.html index 51c0b945682..0dd271f01c2 100644 --- a/master/SpinalHDL/Introduction/faq.html +++ b/master/SpinalHDL/Introduction/faq.html @@ -420,7 +420,7 @@
- Unnamed signal handling
ComparisonmyBool := vec2 === vec1 // Compare all elements // is equivalent to: -//myBool := vec2(0) === vec1(0) && vec2(1) === vec1(1) +// myBool := vec2(0) === vec1(0) && vec2(1) === vec1(1) @@ -1399,11 +1399,11 @@
Lib helper functions
x.sCount(condition: T => Bool)
Count the number of occurence matching a given condition in the Vec.
Count the number of occurrence matching a given condition in the Vec.
UInt
x.sCount(value: T)
Count the number of occurence of a value in the Vec.
Count the number of occurrence of a value in the Vec.
UInt
x.sExists(condition: T => Bool)
Lib helper functions diff --git a/master/SpinalHDL/Data types/bits.html b/master/SpinalHDL/Data types/bits.html index 1209e9d4f0a..1c7cd72cae7 100644 --- a/master/SpinalHDL/Data types/bits.html +++ b/master/SpinalHDL/Data types/bits.html @@ -420,7 +420,7 @@
diff --git a/master/SpinalHDL/Introduction/SpinalHDL.html b/master/SpinalHDL/Introduction/SpinalHDL.html index 38a3482e58f..d1657272a62 100644 --- a/master/SpinalHDL/Introduction/SpinalHDL.html +++ b/master/SpinalHDL/Introduction/SpinalHDL.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Introduction/Projects using SpinalHDL.html b/master/SpinalHDL/Introduction/Projects using SpinalHDL.html index 01a6743fa5e..8aa549c2adc 100644 --- a/master/SpinalHDL/Introduction/Projects using SpinalHDL.html +++ b/master/SpinalHDL/Introduction/Projects using SpinalHDL.html @@ -420,7 +420,7 @@object AvalonMMSlaveFactory{ +
object AvalonMMSlaveFactory { def getAvalonConfig( addressWidth : Int, dataWidth : Int) = { - AvalonMMConfig.pipelined( //Create a simple pipelined configuration of the Avalon Bus + AvalonMMConfig.pipelined( // Create a simple pipelined configuration of the Avalon Bus addressWidth = addressWidth, dataWidth = dataWidth - ).copy( //Change some parameters of the configuration + ).copy( // Change some parameters of the configuration useByteEnable = false, useWaitRequestn = false ) @@ -1641,7 +1641,7 @@
AvalonMMSlaveFactory
Then, let’s implement the AvalonMMSlaveFactory itself.
-diff --git a/master/SpinalHDL/Developers area/spinalhdl_datamodel.html b/master/SpinalHDL/Developers area/spinalhdl_datamodel.html index 7ae30418450..0a7ffa69335 100644 --- a/master/SpinalHDL/Developers area/spinalhdl_datamodel.html +++ b/master/SpinalHDL/Developers area/spinalhdl_datamodel.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Developers area/mill support.html b/master/SpinalHDL/Developers area/mill support.html index 7a168becbe9..1c64df7886f 100644 --- a/master/SpinalHDL/Developers area/mill support.html +++ b/master/SpinalHDL/Developers area/mill support.html @@ -420,7 +420,7 @@class AvalonMMSlaveFactory(bus : AvalonMM) extends BusSlaveFactoryDelayed{ +
diff --git a/master/SpinalHDL/Developers area/index.html b/master/SpinalHDL/Developers area/index.html index 55b52f98b2f..d6a59ee29bc 100644 --- a/master/SpinalHDL/Developers area/index.html +++ b/master/SpinalHDL/Developers area/index.html @@ -420,7 +420,7 @@diff --git a/master/SpinalHDL/Developers area/howotuselocalspinalclone.html b/master/SpinalHDL/Developers area/howotuselocalspinalclone.html index c1dec816f7a..65b866effd5 100644 --- a/master/SpinalHDL/Developers area/howotuselocalspinalclone.html +++ b/master/SpinalHDL/Developers area/howotuselocalspinalclone.html @@ -420,7 +420,7 @@class AvalonMMSlaveFactory(bus : AvalonMM) extends BusSlaveFactoryDelayed { assert(bus.c == AvalonMMSlaveFactory.getAvalonConfig(bus.c.addressWidth,bus.c.dataWidth)) val readAtCmd = Flow(Bits(bus.c.dataWidth bits)) @@ -1660,10 +1660,10 @@
AvalonMMSlaveFactory case _ => } - for((address,jobs) <- elementsPerAddress){ - when(bus.address === address){ - when(bus.write){ - for(element <- jobs) element match{ + for((address,jobs) <- elementsPerAddress) { + when(bus.address === address) { + when(bus.write) { + for(element <- jobs) element match { case element : BusSlaveFactoryWrite => { element.that.assignFromBits(bus.writeData(element.bitOffset, element.that.getBitsWidth bits)) } @@ -1671,8 +1671,8 @@
AvalonMMSlaveFactory case _ => } } - when(bus.read){ - for(element <- jobs) element match{ + when(bus.read) { + for(element <- jobs) element match { case element : BusSlaveFactoryRead => { readAtCmd.payload(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits } @@ -1726,7 +1726,7 @@
Conclusion
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Logic
diff --git a/master/SpinalHDL/Data types/Vec.html b/master/SpinalHDL/Data types/Vec.html index 328ed9f1c9e..1d6c3bd0c35 100644 --- a/master/SpinalHDL/Data types/Vec.html +++ b/master/SpinalHDL/Data types/Vec.html @@ -420,7 +420,7 @@Note
-Notice the difference in behaviour between
x >> 2(result 2 bit narrower than x) andx >> U(2)(keeping width) +Notice the difference in behavior between
x >> 2(result 2 bit narrower than x) andx >> U(2)(keeping width) due to the Scala type ofy.In the first case “2” is an
Int(which can be seen as an “elaboration integer constant”), and in the second case it is a hardware signal @@ -2239,7 +2239,7 @@fixTo function
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
- Unnamed signal handling
Type cast
- Version: master git~4b921f7d90 2024-07-29 + Version: master git~c1ccbe4bce 2024-08-19
diff --git a/master/SpinalHDL/Data types/Int.html b/master/SpinalHDL/Data types/Int.html index d15acfd3e17..2969f328b9f 100644 --- a/master/SpinalHDL/Data types/Int.html +++ b/master/SpinalHDL/Data types/Int.html @@ -420,7 +420,7 @@ - Unnamed signal handling
Misc diff --git a/master/SpinalHDL/Data types/Floating.html b/master/SpinalHDL/Data types/Floating.html index 2c1239c7d0c..f99c82143c7 100644 --- a/master/SpinalHDL/Data types/Floating.html +++ b/master/SpinalHDL/Data types/Floating.html @@ -420,7 +420,7 @@
- Unnamed signal handling
-
@@ -1496,15 +1496,15 @@