From 93e5bbae85b64e852f8f7ab395ba2ed2249514e2 Mon Sep 17 00:00:00 2001 From: Marc Emery Date: Wed, 26 Jun 2024 23:14:51 +0200 Subject: [PATCH 1/3] Typos --- README.rst | 2 +- source/SpinalHDL/Examples/Simple ones/sinus_rom.rst | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.rst b/README.rst index fcc1b01f6f9..6be0fdd339b 100644 --- a/README.rst +++ b/README.rst @@ -33,7 +33,7 @@ Create a virtual environment with pipenv (will use the Pipfile for installing th python3 -m venv .venv -then you can activate the virtual enviroment (in bash) and install the dependencies +then you can activate the virtual environment (in bash) and install the dependencies .. code:: shell diff --git a/source/SpinalHDL/Examples/Simple ones/sinus_rom.rst b/source/SpinalHDL/Examples/Simple ones/sinus_rom.rst index d28c08468bb..c08d6450749 100644 --- a/source/SpinalHDL/Examples/Simple ones/sinus_rom.rst +++ b/source/SpinalHDL/Examples/Simple ones/sinus_rom.rst @@ -1,9 +1,9 @@ .. _sinus_rom: -Sinus rom +Sinus ROM ========= -Let's imagine that you want to generate a sine wave and also have a filtered version of it (which is completely useless in practical, but let's do it as an example). +Let's imagine that you want to generate a sine wave and also have a filtered version of it (which is completely useless in practice, but let's do it as an example). .. list-table:: :header-rows: 1 From 0516319799d318bbdf6307c53ab7f7ba59dee637 Mon Sep 17 00:00:00 2001 From: Marc Emery Date: Wed, 26 Jun 2024 23:20:40 +0200 Subject: [PATCH 2/3] Update the supported BusSlaveFactory buses Based on implementations present in directory /lib/src/main/scala/spinal/lib/bus of spinalHDL v1.10.2 . --- source/SpinalHDL/Libraries/bus_slave_factory.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/SpinalHDL/Libraries/bus_slave_factory.rst b/source/SpinalHDL/Libraries/bus_slave_factory.rst index 3903c6707ac..50b68ec4287 100644 --- a/source/SpinalHDL/Libraries/bus_slave_factory.rst +++ b/source/SpinalHDL/Libraries/bus_slave_factory.rst @@ -18,7 +18,7 @@ You can find more documentation about the internal implementation of the ``BusSl Functionality ------------- -| There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus. +| There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone, Tilelink, BRAM bus and PipelinedMemoryBus. | Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping : .. list-table:: From c9f61ddcd0e5b3f2eab7511a6baa3c1264a2f503 Mon Sep 17 00:00:00 2001 From: Marc Emery Date: Wed, 26 Jun 2024 23:36:49 +0200 Subject: [PATCH 3/3] Fix underline too short CI warning --- source/SpinalHDL/Semantic/when_switch.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/SpinalHDL/Semantic/when_switch.rst b/source/SpinalHDL/Semantic/when_switch.rst index b896a2092e8..353b388f389 100644 --- a/source/SpinalHDL/Semantic/when_switch.rst +++ b/source/SpinalHDL/Semantic/when_switch.rst @@ -41,7 +41,7 @@ As in VHDL and Verilog, signals can be conditionally assigned when a specified c WhenBuilder ------- +----------- Sometimes we need to generate some parameters for the when condition, and the original structure of when else is not very suitable.