diff --git a/LICENSE b/LICENSE
index 2fc30761a98..a4715202b3c 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-reative Commons Legal Code
+Creative Commons Legal Code
 
 CC0 1.0 Universal
 
diff --git a/source/SpinalHDL/Data types/bits.rst b/source/SpinalHDL/Data types/bits.rst
index 1215988dd6d..537de7661b6 100644
--- a/source/SpinalHDL/Data types/bits.rst	
+++ b/source/SpinalHDL/Data types/bits.rst	
@@ -274,6 +274,7 @@ Misc
      - Int
    * - x.bitsRange
      - Return the range (x.high downto 0)
+     - Range
    * - x.valueRange
      - Return the range (x.minValue downto x.maxValue). Note can't be used for value which overflow the JVM Int capacity.
      - Range
diff --git a/source/SpinalHDL/Libraries/utils.rst b/source/SpinalHDL/Libraries/utils.rst
index 4184307b6e6..e03f46ffac4 100644
--- a/source/SpinalHDL/Libraries/utils.rst
+++ b/source/SpinalHDL/Libraries/utils.rst
@@ -54,7 +54,7 @@ State less utilities
      - | Apply a mask on x to only keep the bit set from ``requests``.
        | it start looking in ``requests`` from the ``ohPriority`` position.
        | For example if ``requests`` is "1001" and ``ohPriority`` is "0010", the ``roundRobin`` function will start looking in `requests` from its second bit and will return "1000".
-   * - | `MuxOH <http://spinalhdl.github.io/SpinalHDL/#spinal.lib.MuxOH$>`_ (
+   * - | MuxOH (
        |   oneHot : IndexedSeq[Bool],
        |   inputs : Iterable[T]
        | )
diff --git a/source/SpinalHDL/miscelenea/frequent_errors.rst b/source/SpinalHDL/miscelenea/frequent_errors.rst
index e5bbd4df3d0..3137d734ddd 100644
--- a/source/SpinalHDL/miscelenea/frequent_errors.rst
+++ b/source/SpinalHDL/miscelenea/frequent_errors.rst
@@ -3,8 +3,8 @@
 .. role:: raw-html-m2r(raw)
    :format: html
 
-Introduction
-------------
+Frequent Errors
+---------------
 
 This page will talk about errors which could happen when people are using SpinalHDL.
 
diff --git a/source/SpinalHDL/miscelenea/index.rst b/source/SpinalHDL/miscelenea/index.rst
new file mode 100644
index 00000000000..03eac2a9707
--- /dev/null
+++ b/source/SpinalHDL/miscelenea/index.rst
@@ -0,0 +1,23 @@
+=============
+Miscellaneous
+=============
+
+This section includes content that may be:
+
+ * out-of-date
+ * could be better curated
+ * may contain duplicate information (better found elsewhere here or in another repo)
+ * drafts of documentation and works in progress
+
+So please consider the information in this section with caution and a best
+effort on the author to provide documentation.
+
+.. toctree::
+   :hidden:
+
+   frequent_errors
+   regular_hdl
+   lib/briey/introduction
+   lib/briey/hardware_toplevel
+   lib/briey/hardware
+   lib/briey/software
diff --git a/source/SpinalHDL/miscelenea/lib/briey/hardware.rst b/source/SpinalHDL/miscelenea/lib/briey/hardware.rst
index 171c4c19244..01fdf66ce16 100644
--- a/source/SpinalHDL/miscelenea/lib/briey/hardware.rst
+++ b/source/SpinalHDL/miscelenea/lib/briey/hardware.rst
@@ -1,8 +1,8 @@
 .. role:: raw-html-m2r(raw)
    :format: html
 
-Introduction
-------------
+Pinsec Hardware Introduction
+----------------------------
 
 There is the Pinsec toplevel hardware diagram :
 
diff --git a/source/SpinalHDL/miscelenea/lib/briey/hardware_toplevel.rst b/source/SpinalHDL/miscelenea/lib/briey/hardware_toplevel.rst
index 7c7c6b94e64..18801706c25 100644
--- a/source/SpinalHDL/miscelenea/lib/briey/hardware_toplevel.rst
+++ b/source/SpinalHDL/miscelenea/lib/briey/hardware_toplevel.rst
@@ -3,8 +3,8 @@
 
 .. _briey_hardware_toplevel:
 
-Introduction
-------------
+Briey Hardware Introduction
+---------------------------
 
 ``Briey`` is a little SoC designed for FPGA. It is available in the SpinalHDL library and some documentation could be find :ref:`there <briey_introduction>`
 
diff --git a/source/SpinalHDL/miscelenea/lib/briey/introduction.rst b/source/SpinalHDL/miscelenea/lib/briey/introduction.rst
index 64e307af952..48f4db3efd3 100644
--- a/source/SpinalHDL/miscelenea/lib/briey/introduction.rst
+++ b/source/SpinalHDL/miscelenea/lib/briey/introduction.rst
@@ -3,8 +3,8 @@
 
 .. _briey_introduction:
 
-Introduction
-------------
+Briey Introduction
+------------------
 
 Briey is the name of a little FPGA SoC fully written in SpinalHDL. Goals of this project are multiple :
 
diff --git a/source/index.rst b/source/index.rst
index 8047b24ac45..4c009fe6a27 100644
--- a/source/index.rst
+++ b/source/index.rst
@@ -20,6 +20,7 @@
    SpinalHDL/Formal verification/index
    SpinalHDL/Examples/index
    SpinalHDL/Legacy/index
+   SpinalHDL/miscelenea/index
    SpinalHDL/Developers area/index
 
 
@@ -122,10 +123,3 @@ Links
    :alt: Join the chat at https://gitter.im/SpinalHDL/SpinalHDL
 
 
-
-.. image:: https://api.travis-ci.org/SpinalHDL/SpinalHDL.svg?branch=master
-   :target: https://travis-ci.org/SpinalHDL/SpinalHDL
-   :alt: Build Status
-
-
-