From 843c6decd5e74fdee12a356986303a9e5061d90d Mon Sep 17 00:00:00 2001 From: GiHub Action Bot Date: Mon, 7 Oct 2024 02:44:48 +0000 Subject: [PATCH] update .pot files --- .../gettext/SpinalHDL/Simulation/clock.pot | 86 +++++--- .../LC_MESSAGES/SpinalHDL/Simulation/clock.po | 200 ++++++++++-------- 2 files changed, 163 insertions(+), 123 deletions(-) diff --git a/source/locale/gettext/SpinalHDL/Simulation/clock.pot b/source/locale/gettext/SpinalHDL/Simulation/clock.pot index c337823e3a3..d267e906be8 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/clock.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/clock.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-08-19 09:12+0000\n" +"POT-Creation-Date: 2024-10-07 02:44+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -34,7 +34,7 @@ msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:14 #: ../../SpinalHDL/Simulation/clock.rst:48 -#: ../../SpinalHDL/Simulation/clock.rst:84 +#: ../../SpinalHDL/Simulation/clock.rst:88 msgid "Description" msgstr "" @@ -125,7 +125,7 @@ msgid "Wait API" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:41 -#: ../../SpinalHDL/Simulation/clock.rst:77 +#: ../../SpinalHDL/Simulation/clock.rst:81 msgid "Below is a list of ``ClockDomain`` utilities that you can use to wait for a given event from the domain:" msgstr "" @@ -166,133 +166,149 @@ msgid "Same as ``waitRisingEdge`` but for the edge level specified by the ``Cloc msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:57 -msgid "``waitRisingEdgeWhere(condition)``" +msgid "``waitInactiveEdge([cyclesCount])``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:58 -msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs" +msgid "Same as ``waitFallingEdge`` but for the edge level specified by the ``ClockDomainConfig``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:59 -msgid "``waitFallingEdgeWhere(condition)``" +msgid "``waitRisingEdgeWhere(condition)``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:60 -msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge" +msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:61 -msgid "``waitActiveEdgeWhere(condition)``" +msgid "``waitFallingEdgeWhere(condition)``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:62 -msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``" +msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:63 -msgid "``waitSamplingWhere(condition) : Boolean``" +msgid "``waitActiveEdgeWhere(condition)``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:64 -msgid "Wait until a clockdomain sampled and the given condition is true" +msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:65 -msgid "``waitSamplingWhere(timeout)(condition) : Boolean``" +msgid "``waitInactiveEdgeWhere(condition)``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:66 -msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout" +msgid "Same as ``waitFallingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``" +msgstr "" + +#: ../../SpinalHDL/Simulation/clock.rst:67 +msgid "``waitSamplingWhere(condition) : Boolean``" +msgstr "" + +#: ../../SpinalHDL/Simulation/clock.rst:68 +msgid "Wait until a clockdomain sampled and the given condition is true" +msgstr "" + +#: ../../SpinalHDL/Simulation/clock.rst:69 +msgid "``waitSamplingWhere(timeout)(condition) : Boolean``" msgstr "" #: ../../SpinalHDL/Simulation/clock.rst:70 +msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout" +msgstr "" + +#: ../../SpinalHDL/Simulation/clock.rst:74 msgid "All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API." msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:75 +#: ../../SpinalHDL/Simulation/clock.rst:79 msgid "Callback API" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:83 +#: ../../SpinalHDL/Simulation/clock.rst:87 msgid "ClockDomain callback functions" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:85 +#: ../../SpinalHDL/Simulation/clock.rst:89 msgid "``onNextSampling { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:86 +#: ../../SpinalHDL/Simulation/clock.rst:90 msgid "Execute the callback code only once on the next ``ClockDomain`` sample (active edge + reset off + clock enable on)" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:87 +#: ../../SpinalHDL/Simulation/clock.rst:91 msgid "``onSamplings { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:88 +#: ../../SpinalHDL/Simulation/clock.rst:92 msgid "Execute the callback code each time the ``ClockDomain`` sample (active edge + reset off + clock enable on)" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:89 +#: ../../SpinalHDL/Simulation/clock.rst:93 msgid "``onActiveEdges { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:90 +#: ../../SpinalHDL/Simulation/clock.rst:94 msgid "Execute the callback code each time the ``ClockDomain`` clock generates its configured edge" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:91 +#: ../../SpinalHDL/Simulation/clock.rst:95 msgid "``onEdges { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:92 +#: ../../SpinalHDL/Simulation/clock.rst:96 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising or falling edge" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:93 +#: ../../SpinalHDL/Simulation/clock.rst:97 msgid "``onRisingEdges { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:94 +#: ../../SpinalHDL/Simulation/clock.rst:98 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising edge" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:95 +#: ../../SpinalHDL/Simulation/clock.rst:99 msgid "``onFallingEdges { callback }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:96 +#: ../../SpinalHDL/Simulation/clock.rst:100 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a falling edge" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:97 +#: ../../SpinalHDL/Simulation/clock.rst:101 msgid "``onSamplingWhile { callback : Boolean }``" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:98 +#: ../../SpinalHDL/Simulation/clock.rst:102 msgid "Same as onSampling, but you can stop it (forever) by letting the callback returning false" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:102 +#: ../../SpinalHDL/Simulation/clock.rst:106 msgid "Default ClockDomain" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:104 +#: ../../SpinalHDL/Simulation/clock.rst:108 msgid "You can access the default ``ClockDomain`` of your toplevel as shown below:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:120 +#: ../../SpinalHDL/Simulation/clock.rst:124 msgid "Note that you can also directly fork a standard reset/clock process:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:126 +#: ../../SpinalHDL/Simulation/clock.rst:130 msgid "An example of how to wait for a rising edge on the clock:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:134 +#: ../../SpinalHDL/Simulation/clock.rst:138 msgid "New ClockDomain" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:136 +#: ../../SpinalHDL/Simulation/clock.rst:140 msgid "If your toplevel defines some clock and reset inputs which aren't directly integrated into their ``ClockDomain``, you can define their corresponding ``ClockDomain`` directly in the testbench:" msgstr "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po index 9d3759f7ff8..053cf731444 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-10-07 02:44+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Simulation/clock.rst:2 msgid "Clock domains" @@ -37,7 +40,7 @@ msgstr "时钟域激励函数" #: ../../SpinalHDL/Simulation/clock.rst:14 #: ../../SpinalHDL/Simulation/clock.rst:48 -#: ../../SpinalHDL/Simulation/clock.rst:84 +#: ../../SpinalHDL/Simulation/clock.rst:88 msgid "Description" msgstr "描述" @@ -57,10 +60,10 @@ msgstr "``forkSimSpeedPrinter(printPeriod)``" #: ../../SpinalHDL/Simulation/clock.rst:18 msgid "" -"Fork a simulation process which will periodically print the simulation speed" -" in kilo-cycles per real time second. ``printPeriod`` is in realtime seconds" -msgstr "分裂一个仿真进程，该进程将定期打印每秒实时千周期的仿真速度。 ``printPeriod`` " -"是实时计数的秒数" +"Fork a simulation process which will periodically print the simulation " +"speed in kilo-cycles per real time second. ``printPeriod`` is in realtime" +" seconds" +msgstr "分裂一个仿真进程，该进程将定期打印每秒实时千周期的仿真速度。 ``printPeriod`` 是实时计数的秒数" #: ../../SpinalHDL/Simulation/clock.rst:19 msgid "``clockToggle()``" @@ -133,12 +136,11 @@ msgid "Wait API" msgstr "等待相关API" #: ../../SpinalHDL/Simulation/clock.rst:41 -#: ../../SpinalHDL/Simulation/clock.rst:77 +#: ../../SpinalHDL/Simulation/clock.rst:81 msgid "" -"Below is a list of ``ClockDomain`` utilities that you can use to wait for a " -"given event from the domain:" -msgstr "以下是 ``ClockDomain`` " -"实用工具函数的列表，您可以用它们来等待来自时钟域的给定事件：" +"Below is a list of ``ClockDomain`` utilities that you can use to wait for" +" a given event from the domain:" +msgstr "以下是 ``ClockDomain`` 实用工具函数的列表，您可以用它们来等待来自时钟域的给定事件：" #: ../../SpinalHDL/Simulation/clock.rst:47 msgid "ClockDomain wait functions" @@ -160,13 +162,12 @@ msgstr "``waitRisingEdge([cyclesCount])``" #: ../../SpinalHDL/Simulation/clock.rst:52 msgid "" -"Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 cycle " -"if not otherwise specified. Note, cyclesCount = 0 is legal, and the function" -" is not sensitive to reset/softReset/clockEnable" +"Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 " +"cycle if not otherwise specified. Note, cyclesCount = 0 is legal, and the" +" function is not sensitive to reset/softReset/clockEnable" msgstr "" -"等待cyclesCount个时钟的上升沿；如果没有另外指定，cycleCount 默认为 1 " -"个周期。注意，cyclesCount = 0 是合法的，该功能对复位/softReset/clockEnable " -"不敏感" +"等待cyclesCount个时钟的上升沿；如果没有另外指定，cycleCount 默认为 1 个周期。注意，cyclesCount = 0 " +"是合法的，该功能对复位/softReset/clockEnable 不敏感" #: ../../SpinalHDL/Simulation/clock.rst:53 msgid "``waitFallingEdge([cyclesCount])``" @@ -187,164 +188,187 @@ msgid "" msgstr "与 ``waitRisingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:57 -msgid "``waitRisingEdgeWhere(condition)``" -msgstr "``waitRisingEdgeWhere(condition)``" +#, fuzzy +msgid "``waitInactiveEdge([cyclesCount])``" +msgstr "``waitActiveEdge([cyclesCount])``" #: ../../SpinalHDL/Simulation/clock.rst:58 +#, fuzzy msgid "" -"Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be " -"true when the rising edge occurs" -msgstr "与 ``waitRisingEdge`` 功能相同，但要检查条件，上升沿发生时布尔 ``condition`` " -"必须为真" +"Same as ``waitFallingEdge`` but for the edge level specified by the " +"``ClockDomainConfig``" +msgstr "与 ``waitRisingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:59 +msgid "``waitRisingEdgeWhere(condition)``" +msgstr "``waitRisingEdgeWhere(condition)``" + +#: ../../SpinalHDL/Simulation/clock.rst:60 +msgid "" +"Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must " +"be true when the rising edge occurs" +msgstr "与 ``waitRisingEdge`` 功能相同，但要检查条件，上升沿发生时布尔 ``condition`` 必须为真" + +#: ../../SpinalHDL/Simulation/clock.rst:61 msgid "``waitFallingEdgeWhere(condition)``" msgstr "``waitFallingEdgeWhere(condition)``" -#: ../../SpinalHDL/Simulation/clock.rst:60 +#: ../../SpinalHDL/Simulation/clock.rst:62 msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge" msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对的是下降沿" -#: ../../SpinalHDL/Simulation/clock.rst:61 +#: ../../SpinalHDL/Simulation/clock.rst:63 msgid "``waitActiveEdgeWhere(condition)``" msgstr "``waitActiveEdgeWhere(condition)``" -#: ../../SpinalHDL/Simulation/clock.rst:62 +#: ../../SpinalHDL/Simulation/clock.rst:64 msgid "" "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the " "``ClockDomainConfig``" msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" -#: ../../SpinalHDL/Simulation/clock.rst:63 +#: ../../SpinalHDL/Simulation/clock.rst:65 +#, fuzzy +msgid "``waitInactiveEdgeWhere(condition)``" +msgstr "``waitActiveEdgeWhere(condition)``" + +#: ../../SpinalHDL/Simulation/clock.rst:66 +#, fuzzy +msgid "" +"Same as ``waitFallingEdgeWhere``, but for the edge level specified by the" +" ``ClockDomainConfig``" +msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" + +#: ../../SpinalHDL/Simulation/clock.rst:67 msgid "``waitSamplingWhere(condition) : Boolean``" msgstr "``waitSamplingWhere(condition) : Boolean``" -#: ../../SpinalHDL/Simulation/clock.rst:64 +#: ../../SpinalHDL/Simulation/clock.rst:68 msgid "Wait until a clockdomain sampled and the given condition is true" msgstr "等待直到时钟域采样并且给定条件为真" -#: ../../SpinalHDL/Simulation/clock.rst:65 +#: ../../SpinalHDL/Simulation/clock.rst:69 msgid "``waitSamplingWhere(timeout)(condition) : Boolean``" msgstr "``waitSamplingWhere(timeout)(condition) : Boolean``" -#: ../../SpinalHDL/Simulation/clock.rst:66 +#: ../../SpinalHDL/Simulation/clock.rst:70 msgid "" "Same as waitSamplingWhere defined above, but will never block more than " "timeout cycles. Return true if the exit condition came from the timeout" -msgstr "与上面定义的 waitSamplingWhere " -"相同，但阻塞不会超过timeout个周期。如果退出是因为超时，则返回 true" +msgstr "与上面定义的 waitSamplingWhere 相同，但阻塞不会超过timeout个周期。如果退出是因为超时，则返回 true" -#: ../../SpinalHDL/Simulation/clock.rst:70 +#: ../../SpinalHDL/Simulation/clock.rst:74 msgid "" "All the functionality of the wait API can only be called directly from " "inside a thread, and not from a callback executed via the Callback API." -msgstr "等待 API 的所有功能只能直接从线程内部调用，而不能从通过回调函数使用（通过回调" -"API调用）。" +msgstr "等待 API 的所有功能只能直接从线程内部调用，而不能从通过回调函数使用（通过回调API调用）。" -#: ../../SpinalHDL/Simulation/clock.rst:75 +#: ../../SpinalHDL/Simulation/clock.rst:79 msgid "Callback API" msgstr "回调函数API" -#: ../../SpinalHDL/Simulation/clock.rst:83 +#: ../../SpinalHDL/Simulation/clock.rst:87 msgid "ClockDomain callback functions" msgstr "时钟域回调函数" -#: ../../SpinalHDL/Simulation/clock.rst:85 +#: ../../SpinalHDL/Simulation/clock.rst:89 msgid "``onNextSampling { callback }``" msgstr "``onNextSampling { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:86 +#: ../../SpinalHDL/Simulation/clock.rst:90 msgid "" "Execute the callback code only once on the next ``ClockDomain`` sample " "(active edge + reset off + clock enable on)" msgstr "仅在下一个 ``ClockDomain`` 样本上执行一次回调代码（有效边沿+无复位+时钟使能）" -#: ../../SpinalHDL/Simulation/clock.rst:87 +#: ../../SpinalHDL/Simulation/clock.rst:91 msgid "``onSamplings { callback }``" msgstr "``onSamplings { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:88 +#: ../../SpinalHDL/Simulation/clock.rst:92 msgid "" -"Execute the callback code each time the ``ClockDomain`` sample (active edge " -"+ reset off + clock enable on)" +"Execute the callback code each time the ``ClockDomain`` sample (active " +"edge + reset off + clock enable on)" msgstr "每次 ``ClockDomain`` 采样时执行回调代码（有效边沿+无复位+时钟使能）" -#: ../../SpinalHDL/Simulation/clock.rst:89 +#: ../../SpinalHDL/Simulation/clock.rst:93 msgid "``onActiveEdges { callback }``" msgstr "``onActiveEdges { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:90 +#: ../../SpinalHDL/Simulation/clock.rst:94 msgid "" -"Execute the callback code each time the ``ClockDomain`` clock generates its " -"configured edge" +"Execute the callback code each time the ``ClockDomain`` clock generates " +"its configured edge" msgstr "每次 ``ClockDomain`` 时钟符合其配置的边沿的条件时执行回调代码" -#: ../../SpinalHDL/Simulation/clock.rst:91 +#: ../../SpinalHDL/Simulation/clock.rst:95 msgid "``onEdges { callback }``" msgstr "``onEdges { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:92 +#: ../../SpinalHDL/Simulation/clock.rst:96 msgid "" -"Execute the callback code each time the ``ClockDomain`` clock generates a " -"rising or falling edge" +"Execute the callback code each time the ``ClockDomain`` clock generates a" +" rising or falling edge" msgstr "每次 ``ClockDomain`` 时钟出现上升沿或下降沿时执行回调代码" -#: ../../SpinalHDL/Simulation/clock.rst:93 +#: ../../SpinalHDL/Simulation/clock.rst:97 msgid "``onRisingEdges { callback }``" msgstr "``onRisingEdges { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:94 +#: ../../SpinalHDL/Simulation/clock.rst:98 msgid "" -"Execute the callback code each time the ``ClockDomain`` clock generates a " -"rising edge" +"Execute the callback code each time the ``ClockDomain`` clock generates a" +" rising edge" msgstr "每次 ``ClockDomain`` 的时钟出现上升沿时执行回调代码" -#: ../../SpinalHDL/Simulation/clock.rst:95 +#: ../../SpinalHDL/Simulation/clock.rst:99 msgid "``onFallingEdges { callback }``" msgstr "``onFallingEdges { callback }``" -#: ../../SpinalHDL/Simulation/clock.rst:96 +#: ../../SpinalHDL/Simulation/clock.rst:100 msgid "" -"Execute the callback code each time the ``ClockDomain`` clock generates a " -"falling edge" +"Execute the callback code each time the ``ClockDomain`` clock generates a" +" falling edge" msgstr "每次 ``ClockDomain`` 中时钟出现下降沿时执行回调代码" -#: ../../SpinalHDL/Simulation/clock.rst:97 +#: ../../SpinalHDL/Simulation/clock.rst:101 msgid "``onSamplingWhile { callback : Boolean }``" msgstr "``onSamplingWhile { callback : Boolean }``" -#: ../../SpinalHDL/Simulation/clock.rst:98 +#: ../../SpinalHDL/Simulation/clock.rst:102 msgid "" -"Same as onSampling, but you can stop it (forever) by letting the callback " -"returning false" +"Same as onSampling, but you can stop it (forever) by letting the callback" +" returning false" msgstr "与 onSampling 相同，但您可以通过让回调返回 false 来停止它（永远）" -#: ../../SpinalHDL/Simulation/clock.rst:103 +#: ../../SpinalHDL/Simulation/clock.rst:106 msgid "Default ClockDomain" msgstr "默认时钟域" -#: ../../SpinalHDL/Simulation/clock.rst:105 +#: ../../SpinalHDL/Simulation/clock.rst:108 msgid "" -"You can access the default ``ClockDomain`` of your toplevel as shown below:" +"You can access the default ``ClockDomain`` of your toplevel as shown " +"below:" msgstr "您可以访问顶层模块的默认 ``ClockDomain`` ，如下所示：" -#: ../../SpinalHDL/Simulation/clock.rst:121 +#: ../../SpinalHDL/Simulation/clock.rst:124 msgid "Note that you can also directly fork a standard reset/clock process:" msgstr "请注意，您还可以直接分裂标准复位/时钟产生进程：" -#: ../../SpinalHDL/Simulation/clock.rst:127 +#: ../../SpinalHDL/Simulation/clock.rst:130 msgid "An example of how to wait for a rising edge on the clock:" msgstr "如何等待时钟上升沿的示例：" -#: ../../SpinalHDL/Simulation/clock.rst:135 +#: ../../SpinalHDL/Simulation/clock.rst:138 msgid "New ClockDomain" msgstr "新时钟域" -#: ../../SpinalHDL/Simulation/clock.rst:137 +#: ../../SpinalHDL/Simulation/clock.rst:140 msgid "" -"If your toplevel defines some clock and reset inputs which aren't directly " -"integrated into their ``ClockDomain``, you can define their corresponding " -"``ClockDomain`` directly in the testbench:" +"If your toplevel defines some clock and reset inputs which aren't " +"directly integrated into their ``ClockDomain``, you can define their " +"corresponding ``ClockDomain`` directly in the testbench:" msgstr "" -"如果您的顶层模块中定义了一些未直接集成到其 ``ClockDomain`` 中的时钟和复位，" -"您可以直接在测试平台中定义其相应的 ``ClockDomain`` ：" +"如果您的顶层模块中定义了一些未直接集成到其 ``ClockDomain`` 中的时钟和复位，您可以直接在测试平台中定义其相应的 " +"``ClockDomain`` ：" +