- Version: master git~7f145307e 2023-08-24 + Version: master git~b2d9e2199 2023-08-27
diff --git a/master/SpinalHDL/Data types/Fix.html b/master/SpinalHDL/Data types/Fix.html index 31e89e154fc..1f79d3951ef 100644 --- a/master/SpinalHDL/Data types/Fix.html +++ b/master/SpinalHDL/Data types/Fix.html @@ -223,7 +223,6 @@- Version: master git~7f145307e 2023-08-24 + Version: master git~b2d9e2199 2023-08-27
diff --git a/master/SpinalHDL/Data types/Int.html b/master/SpinalHDL/Data types/Int.html index f70b122b9ab..474b1eafa39 100644 --- a/master/SpinalHDL/Data types/Int.html +++ b/master/SpinalHDL/Data types/Int.html @@ -223,7 +223,6 @@The UInt/SInt type corresponds to a vector of bits that can be used for signed/unsigned integer arithmetic.
The UInt/SInt types are vectors of bits interpreted as two’s complement unsigned/signed integers.
+They can do what Bits can do, with the addition of unsigned/signed integer arithmetic and comparisons.
The syntax to declare an integer is as follows: (everything between [] is optional)
val myUInt = UInt(8 bits)
-myUInt := U(2,8 bits)
+val myUInt = UInt(8 bit)
+myUInt := U(2, 8 bit)
myUInt := U(2)
myUInt := U"0000_0101" // Base per default is binary => 5
myUInt := U"h1A" // Base could be x (base 16)
@@ -1271,10 +1244,12 @@ DeclarationmyUInt := 2 // You can use a Scala Int as a literal value
val myBool = Bool()
-myBool := myUInt === U(7 -> true,(6 downto 0) -> false)
+myBool := myUInt === U(7 -> true, (6 downto 0) -> false)
+myBool := myUInt === U(8 bit, 7 -> true, default -> false)
myBool := myUInt === U(myUInt.range -> true)
-// For assignment purposes, you can omit the U/S, which also allows the use of the [default -> ???] feature
+// For assignment purposes, you can omit the U/S
+// which also allows the use of "default -> ???"
myUInt := (default -> true) // Assign myUInt with "11111111"
myUInt := (myUInt.range -> true) // Assign myUInt with "11111111"
myUInt := (7 -> true, default -> false) // Assign myUInt with "10000000"
@@ -1370,29 +1345,29 @@ Logic
x.clearAll[()]
Clear all bits
modifies x
x.setAll[()]
Set all bits
modifies x
x.setAllTo(value : Boolean)
Set all bits to the given Boolean value
modifies x
x.setAllTo(value : Bool)
Set all bits to the given Bool value
modifies x
Note
-Notice the difference in behaviour between x >> 2:T(w(x)-2) and x >> U(2):T(w(x))
+
Notice the difference in behaviour between x >> 2 (result 2 bit narrower than x) and x >> U(2) (keeping width)
due to the Scala type of y.
-The difference is that in the first case 2 is an Int (which can be seen as an
+
In the first case “2” is an Int (which can be seen as an
“elaboration integer constant”), and in the second case it is a hardware signal
-(type UInt) that may or may-not be a constant.
+(type UInt) that may or may not be a constant.
val a, b, c = SInt(32 bits)
a := S(5)
@@ -1483,6 +1458,7 @@ Arithmeticval d = a +^ b
assert(d === U"9'x0ff")
+// 0xf0 + 0x20 would overflow, the result therefore saturates
val e = a +| U"8'x20"
assert(e === U"8'xff")
@@ -1592,6 +1568,22 @@ Type castmyUInt.twoComplement(en: Bool)
Generate two’s complement of number if en is True, unchanged otherwise. (en makes result negative)
SInt(w(myUInt) + 1, bits)
mySInt.abs
Return the absolute value as a UInt value
UInt(w(mySInt) bits)
mySInt.abs(en: Bool)
Return the absolute value as a UInt value when en is True, otherwise just reinterpret bits as unsigned
UInt(w(mySInt) bits)
mySInt.absWithSym
Return the absolute value of the UInt value with symmetric, shrink 1 bit
UInt(w(mySInt) - 1 bits)
To cast a Bool, a Bits, or an SInt into a UInt, you can use U(something). To cast things into an SInt, you can use S(something).
@@ -1603,16 +1595,40 @@ Type cast// Cast a Bits to SInt
val mySInt = S(myBits)
+
+// UInt to SInt conversion
+val UInt_30 = U(30, 8 bit)
+
+val SInt_30 = UInt_30.intoSInt
+assert(SInt_30 === S(30, 9 bit))
+
+mySInt := UInt_30.twoComplement(booleanDoInvert)
+ // if booleanDoInvert is True then we get S(-30, 9 bit)
+ // otherwise we get S(30, 9 bit)
+
+// absolute values
+val SInt_n_4 = S(-3, 3 bit)
+val abs_en = SInt_n_3.abs(booleanDoAbs)
+ // if booleanDoAbs is True we get U(3, 3 bit)
+ // otherwise we get U"3'b101" or U(5, 3 bit) (raw bit pattern of -3)
+
+val SInt_n_128 = S(-128, 8 bit)
+val abs = SInt_n_128.abs
+assert(abs === U(128, 8 bit))
+val sym_abs = SInt_n_128.absWithSym
+assert(sym_abs === U(127, 7 bit))
Bit extraction
+All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs
+the extraction operators can also be used to assign a part of a UInt / SInt .
-
Operator
Bit extractionx(y)
Readbit, y : Int/UInt
x(y: Int)
Static bit access of y-th bit
Bool
x(offset, width)
Read bitfield, offset: UInt, width: Int
T(width bits)
x(x: UInt)
Variable bit access of y-th bit
Bool
x(offset: Int, width bits)
Fixed part select of fixed width, offset is LSB index
Bits(width bits)
x(offset: UInt, width bits)
Variable part-select of fixed width, offset is LSB index
Bits(width bits)
x(range: Range)
Access a range of bits. Ex : myBits(4 downto 2)
Bits(range.size bits)
x.subdivideIn(y slices, [strict: Boolean])
Subdivide x into y slices, y: Int
Vec(Bits(…), y)
x(range)
Read a range of bits. Ex : myBits(4 downto 2)
T(range bits)
x.subdivideIn(y bits, [strict: Boolean])
Subdivide x in multiple slices of y bits, y: Int
Vec(Bits(y bit), …)
x(y) := z
Assign bits, y : Int/UInt
x.msb
Access most significant bit of x (highest index, sign bit for SInt)
Bool
x(offset, width) := z
Assign bitfield, offset: UInt, width: Int
T(width bits)
x.lsb
Access lowest significant bit of x (index 0)
Bool
x(range) := z
Assign a range of bit. Ex : myBits(4 downto 2) := U”010”
T(range bits)
mySInt.sign
Access most sign bit, only SInt
Bool
-// get the bit at index 4
+Some basic examples:
+// get the element at the index 4
val myBool = myUInt(4)
+// assign element 1
+myUInt(1) := True
+
+// index dynamically
+val index = UInt(2 bit)
+val indexed = myUInt(index, 2 bit)
-// assign bit 1 to True
-mySInt(1) := True
+// range index
+val myUInt_8bit = myUInt_16bit(7 downto 0)
+val myUInt_7bit = myUInt_16bit(0 to 6)
+val myUInt_6bit = myUInt_16bit(0 until 6)
+// assign to myUInt_16bit(3 downto 0)
+myUInt_8bit(3 downto 0) := myUInt_4bit
+
+// equivalent slices, no reversing occurs
+val a = myUInt_16bit(8 downto 4)
+val b = myUInt_16bit(4 to 8)
+
+// read / assign the msb / leftmost bit / x.high bit
+val isNegative = mySInt_16bit.sign
+myUInt_16bit.msb := False
+
+
+
+Subdivide details
+Both overloads of subdivideIn have an optional parameter strict (i.e. subdivideIn(slices: SlicesCount, strict: Boolean = true)).
+If strict is true an error will be raised if the input could not be divided into equal parts. If set to false the last element may
+be smaller than the other (equal sized) elements.
+// Subdivide
+val sel = UInt(2 bits)
+val myUIntWord = myUInt_128bits.subdivideIn(32 bits)(sel)
+ // sel = 3 => myUIntWord = myUInt_128bits(127 downto 96)
+ // sel = 2 => myUIntWord = myUInt_128bits( 95 downto 64)
+ // sel = 1 => myUIntWord = myUInt_128bits( 63 downto 32)
+ // sel = 0 => myUIntWord = myUInt_128bits( 31 downto 0)
-// Range
-val myUInt_8bits = myUInt_16bits(7 downto 0)
-val myUInt_7bits = myUInt_16bits(0 to 6)
-val myUInt_6bits = myUInt_16Bits(0 until 6)
+ // If you want to access in reverse order you can do:
+ val myVector = myUInt_128bits.subdivideIn(32 bits).reverse
+ val myRevUIntWord = myVector(sel)
-mySInt_8bits(3 downto 0) := mySInt_4bits
+ // We can also assign through subdivides
+ val output8 = UInt(8 bit)
+ val pieces = output8.subdivideIn(2 slices)
+ // assign to output8
+ pieces(0) := 0xf
+ pieces(1) := 0x5
+
Misc
+In contrast to the bit extraction operations listed above it’s not possible
+to use the return values to assign to the original signal.
Comparisonwhen(myBits === 3) {
+ // ...
}
-when(myBits_32 =/= B"32'x44332211") {
-}
+val notMySpecialValue = myBits_32 =/= B"32'x44332211"
@@ -1493,11 +1490,15 @@ Type cast
Bit extraction
+All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs
+the extraction operators can also be used to assign a part of a Bits.
+All of the bit extraction operations can be used to read a bit / group of bits. Like in other HDLs They
+can also be used to select a range of bits to be written.
-
Operator
Bit extractionx(y)
Readbit, y: Int/UInt
x(y: Int)
Static bit access of y-th bit
Bool
x(offset,width bits)
Read bitfield, offset: UInt, width: Int
x(x: UInt)
Variable bit access of y-th bit
Bool
x(offset: Int, width bits)
Fixed part select of fixed width, offset is LSB index
Bits(width bits)
x(range)
Read a range of bit. Ex : myBits(4 downto 2)
Bits(range bits)
x(offset: UInt, width bits)
Variable part-select of fixed width, offset is LSB index
Bits(width bits)
x(y) := z
Assign a single bit, y: Int/UInt
Bool
x(range: Range)
Access a range of bits. Ex : myBits(4 downto 2)
Bits(range.size bits)
x(offset, width bits) := z
Assign bitfield, offset: UInt, width: Int
Bits(width bits)
x.subdivideIn(y slices, [strict: Boolean])
Subdivide x into y slices, y: Int
Vec(Bits(…), y)
x.subdivideIn(y bits, [strict: Boolean])
Subdivide x in multiple slices of y bits, y: Int
Vec(Bits(y bit), …)
x.msb
Access most significant bit of x (highest index)
Bool
x(range) := z
Assign a range of bits. Ex : myBits(4 downto 2) := B”010”
Bits(range bits)
x.lsb
Access lowest significant bit of x (index 0)
Bool
+Some basic examples:
// get the element at the index 4
val myBool = myBits(4)
-
-// assign
+// assign element 1
myBits(1) := True
-// Range
-val myBits_8bits = myBits_16bits(7 downto 0)
-val myBits_7bits = myBits_16bits(0 to 6)
-val myBits_6bits = myBits_16Bits(0 until 6)
+// index dynamically
+val index = UInt(2 bit)
+val indexed = myBits(index, 2 bit)
+
+// range index
+val myBits_8bit = myBits_16bit(7 downto 0)
+val myBits_7bit = myBits_16bit(0 to 6)
+val myBits_6bit = myBits_16bit(0 until 6)
+// assign to myBits_16bit(3 downto 0)
+myBits_8bit(3 downto 0) := myBits_4bit
-myBits_8bits(3 downto 0) := myBits_4bits
+// equivalent slices, no reversing occurs
+val a = myBits_16bit(8 downto 4)
+val b = myBits_16bit(4 to 8)
+
+// read / assign the msb / leftmost bit / x.high bit
+val isNegative = myBits_16bit.msb
+myBits_16bit.msb := False
+
+Subdivide details
+Both overloads of subdivideIn have an optional parameter strict (i.e. subdivideIn(slices: SlicesCount, strict: Boolean = true)).
+If strict is true an error will be raised if the input could not be divided into equal parts. If set to false the last element may
+be smaller than the other (equal sized) elements.
+// Subdivide
+val sel = UInt(2 bits)
+val myBitsWord = myBits_128bits.subdivideIn(32 bits)(sel)
+ // sel = 3 => myBitsWord = myBits_128bits(127 downto 96)
+ // sel = 2 => myBitsWord = myBits_128bits( 95 downto 64)
+ // sel = 1 => myBitsWord = myBits_128bits( 63 downto 32)
+ // sel = 0 => myBitsWord = myBits_128bits( 31 downto 0)
+
+ // If you want to access in reverse order you can do:
+ val myVector = myBits_128bits.subdivideIn(32 bits).reverse
+ val myRevBitsWord = myVector(sel)
+
+ // We can also assign through subdivides
+ val output8 = Bits(8 bit)
+ val pieces = output8.subdivideIn(2 slices)
+ // assign to output8
+ pieces(0) := 0xf
+ pieces(1) := 0x5
+
+
+
Misc
+In contrast to the bit extraction operations listed above it’s not possible
+to use the return values to assign to the original signal.
Misc
Range
x.high
Return the index of the MSB (highest allowed zero-based index for Bits)
Return the index of the MSB (highest allowed zero-based index for x)
Int
x.msb
Return the value of the most significant bit
Bool
x.lsb
Return the value of the least significant bit
Bool
x.reversed
Return a representation of the same instance in reverse bit order,
-MSB<>LSB are mirrored.
Return a copy of x with reverse bit order, MSB<>LSB are mirrored.
Bits(w(x) bits)
x ## y
Concatenate, x->high, y->low
Bits(w(x) + w(y) bits)
x.subdivideIn(y slices)
Subdivide x in y slices, y: Int
Vec(Bits, y)
x.subdivideIn(y bits)
Subdivide x in multiple slices of y bits, y: Int
Vec(Bits, w(x)/y)
x.resize(y)
Return a resized representation of x, if enlarged, it is extended with zero
padding at MSB as necessary, y: Int
Misc
println(myBits_32bits.getWidth) // 32
-myBool := myBits.lsb // Equivalent to myBits(0)
-
// Concatenation
myBits_24bits := bits_8bits_1 ## bits_8bits_2 ## bits_8bits_3
-
-// Subdivide
-val sel = UInt(2 bits)
-val myBitsWord = myBits_128bits.subdivideIn(32 bits)(sel)
- // sel = 0 => myBitsWord = myBits_128bits(127 downto 96)
- // sel = 1 => myBitsWord = myBits_128bits( 95 downto 64)
- // sel = 2 => myBitsWord = myBits_128bits( 63 downto 32)
- // sel = 3 => myBitsWord = myBits_128bits( 31 downto 0)
-
- // If you want to access in reverse order you can do:
- val myVector = myBits_128bits.subdivideIn(32 bits).reverse
- val myBitsWord = myVector(sel)
+// or
+myBits_24bits := Cat(bits_8bits_1, bits_8bits_2, bits_8bits_3)
// Resize
myBits_32bits := B"32'x112233344"
@@ -1662,9 +1686,11 @@ Misc
+
-MaskedLiteral
-MaskedLiteral values are bit vectors with don’t care values denoted with -.
+MaskedLiteral
+MaskedLiteral values are bit vectors with don’t care values denoted with -.
+They can be used for direct comparison or for switch statements and mux es.
val myBits = B"1101"
val test1 = myBits === M"1-01" // True
@@ -1673,7 +1699,6 @@ Misc
-