From 6222df68fc5704ee327f1cac0151a0a6ade952bd Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 10:22:02 +0100
Subject: [PATCH] Proper formatting

---
 source/SpinalHDL/Semantic/assignments.rst | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index aea3079f97e..d4e0c29d111 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -168,15 +168,16 @@ If we look at the resulting Verilog, ``b`` is not present. Since it is a copy of
 ``CombInit`` is particularly helpful in helper functions to ensure that the returned value is not referencing an input.
 
 .. code-block:: scala
-   // note that condition is an elaboration time constant
-   def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }
 
-   val a2 = invertedIf(a1, c)
+    // note that condition is an elaboration time constant
+    def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }
 
-   when(sel) {
-      a2 := 0
-   }
+    val a2 = invertedIf(a1, c)
 
-   // Without CombInit, if c == false (but not if c == true), a1 and a2 reference the same signal and the zero assignment is also applied to a1.
-   // With CombInit we have a coherent behaviour whatever the c value.
+    when(sel) {
+       a2 := 0
+    }
+
+Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` and ``a2`` reference the same signal and the zero assignment is also applied to ``a1``.
+With ``CombInit`` we have a coherent behaviour whatever the ``c`` value.