diff --git a/dev/.buildinfo b/dev/.buildinfo index 01534ac2b8e..515c9ca7841 100644 --- a/dev/.buildinfo +++ b/dev/.buildinfo @@ -1,4 +1,4 @@ # Sphinx build info version 1 # This file hashes the configuration used when building these files. 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Assignment

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Misc

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Type cast

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fixTo function

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Lib helper functions

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Misc

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MaskedBoolean

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master/slave

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Type cast

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Example

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Example

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False-positives

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Example

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Design errors

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Example

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Due to mux

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Example

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Issue explanation

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Specifying exceptions

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Example

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Example

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Example 2

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Register with only init

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Example

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Operator example

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Conclusion

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example

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Developers area

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Publish locally

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Enumerating every ClockDomain in use

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Continuous Assignment Literals as signal declaration

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Advanced ones

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Usage demonstration

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Implementation

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Pinesec

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In practice

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Usage

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Component implementation

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Intermediates ones

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Bonus: Having fun with Stream

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VGA

Introduction

VGA interfaces are becoming an endangered species, but implementing a VGA controller is still a good exercise.

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An explanation about the VGA protocol can be found here.

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Bonus

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Usage

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Carry adder

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Color summing

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Counter with clear

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Simple ones

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TopLevel definition

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RGB to gray

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Getting started

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Meta Hardware Description capabilities

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For interfaces implement IMasterSlave

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Core

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Cheatsheets

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Lib

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Symbolic

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Help for VHDL people

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Meta hardware description

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Process blocks

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Using Spinal on SpinalHDL code

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Templates / Type parameterization

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Parameters

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Introduction

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Scala elaboration capabilities (if, for, functional programming)

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Getting Started

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Internal logic

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Contributing

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Getting in touch

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License

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Other learning materials

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Universities

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Advantages of using SpinalHDL over VHDL / Verilog

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How to use an unreleased version of SpinalHDL (but committed on git)?

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Introduction

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Legacy

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Generate the RTL

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Misc

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pinsec

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Board support

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OpenOCD/GDB/Eclipse configuration

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Todo

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Variations

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Functions and operators

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Functions and operators

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Configuration and instanciation

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Bus

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Configuration and instanciation

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Example WidthAdapter

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Com

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UartCtrl

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Usage

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Usage

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Adding new interface support

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Example

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EDA

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RGB

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Graphics

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VGA controller

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IO

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ReadableOpenDrain

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TriStateArray

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PlicMapping.lig

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Misc

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BigInt enricher

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Functionality

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soon(handle)

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Simulation Support

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Functions

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Notes about the entry state

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Developers Area

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Simulation support

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Special utilities

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VexRiscv (RV32IM CPU)

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Manually driving Analog bundles

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Assertions

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Other language features

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Report

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Stub

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Binary prefix

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Sequential logic

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CombInit

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Signal and register interactions with Scala (OOP reference + Functions)

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Example

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Sequential logic

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Standard memory blackboxes

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Transforming a wire into a register

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Capturing wave for a given window before failure

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New ClockDomain

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Simulation engine

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Examples

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Uart decoder

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Uart encoder

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Simulation

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Linux

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Linux

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Simulation with

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From source

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Backend-dependent installation instructions

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Accessing signals inside the component’s hierarchy

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Performance

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Sleep and waitUntil

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Thread-less API

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Area

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VHDL - No numeric type

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ClockEnableArea

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Synthesized component names

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Valid Ready Payload bus

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Structuring

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In last resort

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Optional hardware

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Utils

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Output signal X can’t be assigned by Y

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Miscellaneous

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Index

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Spinal Hardware Description Language

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- Version: master git~9942e2359a 2023-12-01 + Version: master git~cf595e9ef1 2023-12-18

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