diff --git a/dev/.buildinfo b/dev/.buildinfo index 49298dd287a..f0f595693e6 100644 --- a/dev/.buildinfo +++ b/dev/.buildinfo @@ -1,4 +1,4 @@ # Sphinx build info version 1 # This file hashes the configuration used when building these files. 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    Comparison

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    Type cast

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    fixTo function

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    MaskedBoolean

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    master/slave

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    Type cast

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    Example

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    Example

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    False-positives

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    Example

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    Design errors

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    Example

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    Due to mux

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    Example

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    Issue explanation

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    Example

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    Example

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    Example 2

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    Register with only init diff --git a/master/SpinalHDL/Design errors/unreachable_is_statement.html b/master/SpinalHDL/Design errors/unreachable_is_statement.html index 3c08922ca96..9bae37f5996 100644 --- a/master/SpinalHDL/Design errors/unreachable_is_statement.html +++ b/master/SpinalHDL/Design errors/unreachable_is_statement.html @@ -973,7 +973,6 @@ -
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    Example

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    Operator example

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    Conclusion

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    example

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    Developers area

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    Publish locally

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    Enumerating every ClockDomain used

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    Introduction

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Legacy/index.html b/master/SpinalHDL/Legacy/index.html index 1ddcfe377fa..ee480423105 100644 --- a/master/SpinalHDL/Legacy/index.html +++ b/master/SpinalHDL/Legacy/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1266,7 +1265,7 @@

    Legacy diff --git a/master/SpinalHDL/Legacy/pinsec/hardware.html b/master/SpinalHDL/Legacy/pinsec/hardware.html index c1099788a9d..bc74a15f454 100644 --- a/master/SpinalHDL/Legacy/pinsec/hardware.html +++ b/master/SpinalHDL/Legacy/pinsec/hardware.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1272,7 +1271,7 @@

    Generate the RTL

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html b/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html index e9f253ea2ff..e1d718404a4 100644 --- a/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html +++ b/master/SpinalHDL/Legacy/pinsec/hardware_toplevel.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1659,7 +1658,7 @@

    Misc diff --git a/master/SpinalHDL/Legacy/pinsec/index.html b/master/SpinalHDL/Legacy/pinsec/index.html index 28598300e13..01ef42fe434 100644 --- a/master/SpinalHDL/Legacy/pinsec/index.html +++ b/master/SpinalHDL/Legacy/pinsec/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1256,7 +1255,7 @@

    pinsec diff --git a/master/SpinalHDL/Legacy/pinsec/introduction.html b/master/SpinalHDL/Legacy/pinsec/introduction.html index 4bf0810d034..2158efd5ecf 100644 --- a/master/SpinalHDL/Legacy/pinsec/introduction.html +++ b/master/SpinalHDL/Legacy/pinsec/introduction.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1237,7 +1236,7 @@

    Board support

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Legacy/pinsec/software.html b/master/SpinalHDL/Legacy/pinsec/software.html index add436baf36..b2e421d2562 100644 --- a/master/SpinalHDL/Legacy/pinsec/software.html +++ b/master/SpinalHDL/Legacy/pinsec/software.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1232,7 +1231,7 @@

    OpenOCD/GDB/Eclipse configuration

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Legacy/riscv.html b/master/SpinalHDL/Legacy/riscv.html index 8ef52484622..d2016313ae9 100644 --- a/master/SpinalHDL/Legacy/riscv.html +++ b/master/SpinalHDL/Legacy/riscv.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1266,7 +1265,7 @@

    Todo diff --git a/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html b/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html index 03ca9e12109..d0f17d7063c 100644 --- a/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html +++ b/master/SpinalHDL/Libraries/Bus/amba3/ahblite3.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1280,7 +1279,7 @@

    Variations

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/Bus/amba3/apb3.html b/master/SpinalHDL/Libraries/Bus/amba3/apb3.html index 527e2299157..6d5b2784e52 100644 --- a/master/SpinalHDL/Libraries/Bus/amba3/apb3.html +++ b/master/SpinalHDL/Libraries/Bus/amba3/apb3.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1299,7 +1298,7 @@

    Functions and operators diff --git a/master/SpinalHDL/Libraries/Bus/amba4/axi4.html b/master/SpinalHDL/Libraries/Bus/amba4/axi4.html index 72d0aca0d98..4cb69f9d6b1 100644 --- a/master/SpinalHDL/Libraries/Bus/amba4/axi4.html +++ b/master/SpinalHDL/Libraries/Bus/amba4/axi4.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1383,7 +1382,7 @@

    Functions and operators diff --git a/master/SpinalHDL/Libraries/Bus/avalon/avalonmm.html b/master/SpinalHDL/Libraries/Bus/avalon/avalonmm.html index 0132acade52..38aa7066f3f 100644 --- a/master/SpinalHDL/Libraries/Bus/avalon/avalonmm.html +++ b/master/SpinalHDL/Libraries/Bus/avalon/avalonmm.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1310,7 +1309,7 @@

    Configuration and instanciation

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/Bus/index.html b/master/SpinalHDL/Libraries/Bus/index.html index 45d75e51e0e..9c66efe8bb8 100644 --- a/master/SpinalHDL/Libraries/Bus/index.html +++ b/master/SpinalHDL/Libraries/Bus/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1227,7 +1226,7 @@

    Bus diff --git a/master/SpinalHDL/Libraries/Com/index.html b/master/SpinalHDL/Libraries/Com/index.html index e850adae7ff..a022371569c 100644 --- a/master/SpinalHDL/Libraries/Com/index.html +++ b/master/SpinalHDL/Libraries/Com/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1233,7 +1232,7 @@

    Com diff --git a/master/SpinalHDL/Libraries/Com/uart.html b/master/SpinalHDL/Libraries/Com/uart.html index fd6e392be49..e87dc447293 100644 --- a/master/SpinalHDL/Libraries/Com/uart.html +++ b/master/SpinalHDL/Libraries/Com/uart.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1298,7 +1297,7 @@

    UartCtrl

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/Com/usb_device.html b/master/SpinalHDL/Libraries/Com/usb_device.html index 8c13820c237..cf0d5bd5d07 100644 --- a/master/SpinalHDL/Libraries/Com/usb_device.html +++ b/master/SpinalHDL/Libraries/Com/usb_device.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1173,7 +1172,8 @@

    USB device

    -

    There is a USB device controller in the SpinalHDL library. In a few bullet points it can be resumed to :

    +

    Here exists a USB device controller in the SpinalHDL library.

    +

    A few bullet points to summarise support:

    @@ -1269,7 +1269,8 @@

    ADDRESS (0xFF04)

    INTERRUPT (0xFF08)

    -

    All bits of this register can be cleared by writing ‘1’ in them.

    +

    Individual bits of this register can be cleared by writing ‘1’ in them. +Reading this register returns the current interrupt status.

    @@ -1280,42 +1281,42 @@

    INTERRUPT (0xFF08)

    - + - + - + - + - + - + - + - + - + - + - + - +

    Name

    endpoints

    RC

    W1C

    15-0

    Raised when a enpoint generate a interrupt

    Raised when an endpoint generates an interrupt

    reset

    RC

    W1C

    16

    Raised when a USB reset appeared

    Raised when a USB reset occurs

    ep0Setup

    RC

    W1C

    17

    Raised when endpoint 0 receive a setup transaction

    Raised when endpoint 0 receives a setup transaction

    suspend

    RC

    W1C

    18

    Raised when a USB suspend appeared

    Raised when a USB suspend occurs

    resume

    RC

    W1C

    19

    Raised when a USB resume appeared

    Raised when a USB resume occurs

    disconnect

    RC

    W1C

    20

    Raised when a USB disconnect appeared

    Raised when a USB disconnect occurs

    HALT (0xFF0C)

    -

    This register allow to place a single enpoint in a dormant state in order to ensure atomicity of CPU operations, allowing to do things as read/modify/write on the endpoint registers and descriptors. -The peripheral will return NAK if the given endpoint is addressed by the usb host.

    +

    This register allows placement of a single endpoint into a dormant state in order to ensure atomicity of CPU operations, allowing to do things as read/modify/write on the endpoint registers and descriptors. +The peripheral will return NAK if the given endpoint is addressed by the usb host while halt is enabled and the endpoint is enabled.

    @@ -1333,7 +1334,7 @@

    HALT (0xFF0C)

    - + @@ -1454,19 +1455,19 @@

    ENDPOINTS (0x0000 - 0x003F)

    SETUP_DATA (0x0040 - 0x0047)

    -

    When endpoint 0 receive a SETUP transaction, the data of the transaction will be stored at that place.

    +

    When endpoint 0 receives a SETUP transaction, the data of the transaction will be stored in this location.

    Descriptors

    -

    Descriptors allows to specify how a endpoint need to handle the data phase of IN/OUT transactions. +

    Descriptors allows to specify how an endpoint needs to handle the data phase of IN/OUT transactions. They are stored in the internal ram, can be linked together via their linked lists and need to be aligned on 16 bytes boundaries

    Name

    enable

    WO

    4

    When set halt is active, when clear endpoint is unhalted.

    effective enable

    @@ -1490,7 +1491,7 @@

    Descriptors

    - @@ -1506,13 +1507,13 @@

    Descriptors

    - - @@ -1521,7 +1522,7 @@

    Descriptors

    @@ -1530,7 +1531,7 @@

    Descriptors @@ -1608,7 +1609,7 @@

    Usage diff --git a/master/SpinalHDL/Libraries/Com/usb_ohci.html b/master/SpinalHDL/Libraries/Com/usb_ohci.html index f3db8f60fe8..a0b40cb0359 100644 --- a/master/SpinalHDL/Libraries/Com/usb_ohci.html +++ b/master/SpinalHDL/Libraries/Com/usb_ohci.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1173,16 +1172,17 @@

    USB OHCI

    -

    There is a USB OHCi controller (host) in the SpinalHDL library. In a few bullet points it can be resumed to :

    +

    Here exists a USB OHCi controller (host) in the SpinalHDL library.

    +

    A few bullet points to summarise support:

    • It follow the OpenHCI Open Host Controller Interface Specification for USB specification (OHCI).

    • -
    • It is compatible with the upstream linux / uboot OHCI drivers already. (there is also a OHCI driver on tinyUSB)

    • -
    • This provide USB host full speed and low speed capabilities (12Mbps and 1.5Mbps)

    • +
    • It is compatible with the upstream linux / uboot OHCI drivers already. (there is also an OHCI driver on tinyUSB)

    • +
    • This provides USB host full speed and low speed capabilities (12Mbps and 1.5Mbps)

    • Tested on linux and uboot

    • One controller can host multiple ports (up to 16)

    • Bmb memory interface for DMA accesses

    • Bmb memory interace for the configuration

    • -
    • Require a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz

    • +
    • Requires a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz

    • The controller frequency is not restricted

    • No external phy required

    @@ -1197,7 +1197,7 @@

    USB OHCI
  • Some USB hub (had one so far) do not like having a full speed host with low speed devices attached.

  • Some modern devices will not work on USB full speed (ex : Gbps ethernet adapter)

  • -
  • Require memory coherency with the CPU (or the cpu need to flush his data cache in the driver)

  • +
  • Require memory coherency with the CPU (or the cpu need to be able to flush its data cache in the driver)

  • Deployments :

    -
  • Introduction
  • Getting started
  • @@ -1185,8 +1184,8 @@

    QSysify

    Example

    In the case of a UART controller :

    -
    case class AvalonMMUartCtrl(...) extends Component{
    -  val io = new Bundle{
    +
    case class AvalonMMUartCtrl(...) extends Component {
    +  val io = new Bundle {
         val bus =  slave(AvalonMM(AvalonMMUartCtrl.getAvalonMMConfig))
         val uart = master(Uart())
       }
    @@ -1196,7 +1195,7 @@ 

    Examplemain will generate the Verilog and the QSys TCL script with io.bus as an AvalonMM and io.uart as a conduit :

    -
    object AvalonMMUartCtrl{
    +
    diff --git a/master/SpinalHDL/Libraries/EDA/altera/quartus_flow.html b/master/SpinalHDL/Libraries/EDA/altera/quartus_flow.html index d1ee306e0ef..a1d25db462f 100644 --- a/master/SpinalHDL/Libraries/EDA/altera/quartus_flow.html +++ b/master/SpinalHDL/Libraries/EDA/altera/quartus_flow.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1262,7 +1261,7 @@

    Example diff --git a/master/SpinalHDL/Libraries/EDA/index.html b/master/SpinalHDL/Libraries/EDA/index.html index d92dbe3a680..4e0652d8f20 100644 --- a/master/SpinalHDL/Libraries/EDA/index.html +++ b/master/SpinalHDL/Libraries/EDA/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1230,7 +1229,7 @@

    EDA diff --git a/master/SpinalHDL/Libraries/Graphics/colors.html b/master/SpinalHDL/Libraries/Graphics/colors.html index b249a59d3f1..f698d29420d 100644 --- a/master/SpinalHDL/Libraries/Graphics/colors.html +++ b/master/SpinalHDL/Libraries/Graphics/colors.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1176,11 +1175,11 @@

    Colors

    RGB

    You can use an Rgb bundle to model colors in hardware. This Rgb bundle take as parameter an RgbConfig classes which specify the number of bits for each channels :

    -
    case class RgbConfig(rWidth : Int,gWidth : Int,bWidth : Int){
    +
    case class RgbConfig(rWidth : Int,gWidth : Int,bWidth : Int) {
       def getWidth = rWidth + gWidth + bWidth
     }
     
    -case class Rgb(c: RgbConfig) extends Bundle{
    +case class Rgb(c: RgbConfig) extends Bundle {
       val r = UInt(c.rWidth bits)
       val g = UInt(c.gWidth bits)
       val b = UInt(c.bWidth bits)
    @@ -1225,7 +1224,7 @@ 

    RGB diff --git a/master/SpinalHDL/Libraries/Graphics/index.html b/master/SpinalHDL/Libraries/Graphics/index.html index 2cc74bb634e..1ca901745c0 100644 --- a/master/SpinalHDL/Libraries/Graphics/index.html +++ b/master/SpinalHDL/Libraries/Graphics/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1217,7 +1216,7 @@

    Graphics

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/Graphics/vga.html b/master/SpinalHDL/Libraries/Graphics/vga.html index c3f14500c10..19ecda19558 100644 --- a/master/SpinalHDL/Libraries/Graphics/vga.html +++ b/master/SpinalHDL/Libraries/Graphics/vga.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1176,7 +1175,7 @@

    VGA

    VGA bus

    An VGA bus definition is available via the Vga bundle.

    -
    case class Vga (rgbConfig: RgbConfig) extends Bundle with IMasterSlave{
    +
    case class Vga (rgbConfig: RgbConfig) extends Bundle with IMasterSlave {
       val vSync = Bool()
       val hSync = Bool()
     
    @@ -1210,7 +1209,7 @@ 

    VGA timings

    VGA controller

    -

    An VGA controller is available. It’s definition is the following :

    +

    An VGA controller is available. Its definition is the following :

    case class VgaCtrl(rgbConfig: RgbConfig, timingsWidth: Int = 12) extends Component {
       val io = new Bundle {
         val softReset = in Bool()
    @@ -1263,7 +1262,7 @@ 

    VGA controller

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/IO/index.html b/master/SpinalHDL/Libraries/IO/index.html index d6eac0fbfdb..faf4e292e73 100644 --- a/master/SpinalHDL/Libraries/IO/index.html +++ b/master/SpinalHDL/Libraries/IO/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1213,7 +1212,7 @@

    IO diff --git a/master/SpinalHDL/Libraries/IO/readableOpenDrain.html b/master/SpinalHDL/Libraries/IO/readableOpenDrain.html index a0da6610fce..e901d93c302 100644 --- a/master/SpinalHDL/Libraries/IO/readableOpenDrain.html +++ b/master/SpinalHDL/Libraries/IO/readableOpenDrain.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1174,7 +1173,7 @@

    ReadableOpenDrain

    The ReadableOpenDrain bundle is defined as following :

    -
    case class ReadableOpenDrain[T<: Data](dataType : HardType[T]) extends Bundle with IMasterSlave{
    +
    case class ReadableOpenDrain[T<: Data](dataType : HardType[T]) extends Bundle with IMasterSlave {
       val write,read : T = dataType()
     
       override def asMaster(): Unit = {
    @@ -1186,12 +1185,12 @@ 

    ReadableOpenDrainread signal to read the outside value and use the write to set the value that you want to drive on the output.

    There is an example of usage :

    -
    val io = new Bundle{
    +
         
     
    diff --git a/master/SpinalHDL/Libraries/IO/tristate.html b/master/SpinalHDL/Libraries/IO/tristate.html
    index 31436fd07e4..0d905cc206e 100644
    --- a/master/SpinalHDL/Libraries/IO/tristate.html
    +++ b/master/SpinalHDL/Libraries/IO/tristate.html
    @@ -973,7 +973,6 @@
     
     
     
    -
  • Introduction
  • Getting started
  • @@ -1173,7 +1172,7 @@

    TriState

    -

    Tri-state signals are weird to handle in many cases:

    +

    Tri-state signals are difficult to handle in many cases:

    -
  • Introduction
  • Getting started
  • @@ -1232,7 +1231,7 @@

    PlicMapping.lig diff --git a/master/SpinalHDL/Libraries/Misc/index.html b/master/SpinalHDL/Libraries/Misc/index.html index 9ebf5ad3274..746a357bf7e 100644 --- a/master/SpinalHDL/Libraries/Misc/index.html +++ b/master/SpinalHDL/Libraries/Misc/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1213,7 +1212,7 @@

    Misc diff --git a/master/SpinalHDL/Libraries/binarySystem.html b/master/SpinalHDL/Libraries/binarySystem.html index 5c1275764f4..d0b6e53fe19 100644 --- a/master/SpinalHDL/Libraries/binarySystem.html +++ b/master/SpinalHDL/Libraries/binarySystem.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1372,12 +1371,12 @@

    Int/Long/BigInt to Binary-ListList(0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1)

    -

    align to fix width

    +

    align to a fixed width

    import spinal.core.lib._
     
     $: 39.toBinInts()
     List(1, 1, 1, 0, 0, 1)
    -$: 39.toBinInts(8)    // align to 8 bit fill with 0
    +$: 39.toBinInts(8)    // align to 8 bit zero filled at MSB
     List(1, 1, 1, 0, 0, 1, 0, 0)
     
    @@ -1447,7 +1446,7 @@

    BigInt enricher

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/bus_slave_factory.html b/master/SpinalHDL/Libraries/bus_slave_factory.html index 7dd76bf56e9..28120824dce 100644 --- a/master/SpinalHDL/Libraries/bus_slave_factory.html +++ b/master/SpinalHDL/Libraries/bus_slave_factory.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1181,8 +1180,8 @@

    Introduction

    Functionality

    -
    Currently there is three implementation of the BusSlaveFactory tool : APB3, AXI-lite 3 and Avalon.
    -
    Each implementation of that tool take as argument one instance of the corresponding bus and then offer following functions to map your hardware into the memory mapping :
    +
    There are many implementations of the BusSlaveFactory tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus.
    +
    Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping :

    next

    1

    15-4

    Point the the next descriptor +

    Pointer to the next descriptor 0 => nothing, byte address = this << 4

    length

    interrupt

    2

    17

    If set, the completion of the descriptor will generate a +

    If set, the completion of the descriptor will generate an interrupt.

    completionOnFull

    2

    18

    Normaly, a descriptor completion only occure when a USB transfer +

    Normally, a descriptor completion only occurs when a USB transfer is smaller than the maxPacketSize. But if this field is set, then when the descriptor become full is also a considered as a completion event. (offset == length)

    data

    @@ -1332,7 +1331,7 @@

    Functionality

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/fiber.html b/master/SpinalHDL/Libraries/fiber.html index 014aba9c908..b8c25270fc4 100644 --- a/master/SpinalHDL/Libraries/fiber.html +++ b/master/SpinalHDL/Libraries/fiber.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1172,23 +1171,28 @@

    Fiber framework

    +
    +

    Warning

    +

    This framework is not expected to be used for general RTL generation and targets large system +design management and code generation. It is currently used as toplevel integration tool in SaxonSoC.

    +

    Currently in developpement.

    The Fiber to run the hardware elaboration in a out of order manner, a bit similarly to Makefile, where you can define rules and dependencies which will then be solved when you run a make command. It is very similar to the Scala Future feature.

    -

    Such framework complexify simple things but provide some strong feature for complex cases :

    +

    Using this framework can complicate simple things but provide some strong features for complex cases :

      -
    • You can define things before even knowing all their requirements, ex : instanciating a interruption controller, before knowing how many lines of interrupt you need

    • +
    • You can define things before even knowing all their requirements, ex : +instantiating a interruption controller, before knowing how many interrupt signal lines you need

    • Abstract/lazy/partial SoC architecture definition allowing the creation of SoC template for further specialisations

    • -
    • Automatic requirements negotiation between multiple agents in a decentralized way, ex : between masters and slaves of a memory bus

    • +
    • Automatic requirement negotiation between multiple agents in a decentralized way, ex : between masters and slaves of a memory bus

    The framework is mainly composed of :

      -
    • Handle[T], which can be used later to store a value of type T.

    • -
    • handle.load which allow to set the value of a handle (will reschedule all tasks waiting on it)

    • -
    • handle.get, which return the value of the given handle. Will block the task execution if that handle isn’t loaded yet

    • -
    • Handle{ code }, which fork a new task which will execute the given code. The result of that code will be loaded into the Handle

    • -
    • soon(handle), which allow the current task to announce that soon it will load that handle with a value (used to track which handle will

    • +
    • Handle[T], which can be used later to store a value of type T.

    • +
    • handle.load which allow to set the value of a handle (will reschedule all tasks waiting on it)

    • +
    • handle.get, which return the value of the given handle. Will block the task execution if that handle isn’t loaded yet

    • +
    • Handle{ /*code*/ }, which fork a new task which will execute the given code. The result of that code will be loaded into the Handle

    • +
    • soon(handle), which allows the current task to announce that it will load handle with a value (used for scheduling)

    -

    Warning, this is realy not usual RTL description and aim large system generation. It is currently used as toplevel integration tool in SaxonSoC.

    Simple dummy example

    There is a simple example :

    @@ -1269,7 +1273,7 @@

    soon(handle)

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/flow.html b/master/SpinalHDL/Libraries/flow.html index 1c647b689fb..df51a1abc0b 100644 --- a/master/SpinalHDL/Libraries/flow.html +++ b/master/SpinalHDL/Libraries/flow.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1429,7 +1428,7 @@

    Simulation Support

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/fragment.html b/master/SpinalHDL/Libraries/fragment.html index 75d0d9627de..216acb4415a 100644 --- a/master/SpinalHDL/Libraries/fragment.html +++ b/master/SpinalHDL/Libraries/fragment.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1304,7 +1303,7 @@

    Functions

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/fsm.html b/master/SpinalHDL/Libraries/fsm.html index 8d528fd5b5b..c4009037a00 100644 --- a/master/SpinalHDL/Libraries/fsm.html +++ b/master/SpinalHDL/Libraries/fsm.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1186,7 +1185,7 @@

    Introduction } val fsm = new StateMachine { - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) io.result := False val stateA : State = new State with EntryPoint { @@ -1217,12 +1216,12 @@

    Introduction val result = out Bool() } - val fsm = new StateMachine{ + val fsm = new StateMachine { val stateA = new State with EntryPoint val stateB = new State val stateC = new State - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) io.result := False stateA @@ -1403,7 +1402,7 @@

    States

    StateDelay

    -

    StateDelay allows to create a state which waits for a fixed number of cycles before executing statments in whenCompleted {...}. The preferred way to use it is:

    +

    StateDelay allows you to create a state which waits for a fixed number of cycles before executing statements in whenCompleted {...}. The preferred way to use it is:

    val stateG : State = new StateDelay(cyclesCount=40) {
       whenCompleted {
         goto(stateH)
    @@ -1418,7 +1417,7 @@ 

    StateDelay

    StateFsm

    -

    StateFsm allow to describe a state containing a nested state machine. When the nested state machine is done (exited), statments in whenCompleted { ... } are executed.

    +

    StateFsm allows you to describe a state containing a nested state machine. When the nested state machine is done (exited), statements in whenCompleted { ... } are executed.

    There is an example of StateFsm definition :

    // internalFsm is a function defined below
     val stateC = new StateFsm(fsm=internalFsm()) {
    @@ -1428,7 +1427,7 @@ 

    StateFsm} def internalFsm() = new StateMachine { - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) val stateA : State = new State with EntryPoint { whenIsActive { @@ -1452,10 +1451,10 @@

    StateFsm

    StateParallelFsm

    -

    StateParallelFsm allows to handle multiple nested state machines. When all nested state machine are done, statments in whenCompleted { ... } are executed.

    +

    StateParallelFsm allows you to handle multiple nested state machines. When all nested state machine are done, statements in whenCompleted { ... } are executed.

    Example:

    val stateD = new StateParallelFsm (internalFsmA(), internalFsmB()) {
    -  whenCompleted{
    +  whenCompleted {
         goto(stateE)
       }
     }
    @@ -1534,7 +1533,7 @@ 

    Notes about the entry state

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/index.html b/master/SpinalHDL/Libraries/index.html index 7d546d630e3..4d522e19f75 100644 --- a/master/SpinalHDL/Libraries/index.html +++ b/master/SpinalHDL/Libraries/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1221,7 +1220,7 @@ diff --git a/master/SpinalHDL/Libraries/regIf.html b/master/SpinalHDL/Libraries/regIf.html index c0b0a41fa8f..c42208ff180 100644 --- a/master/SpinalHDL/Libraries/regIf.html +++ b/master/SpinalHDL/Libraries/regIf.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1175,14 +1174,14 @@

    RegIf

    Register Interface Builder

    • Automatic address, fields allocation and conflict detection

    • -
    • 28 Register Access types(Covering the 25 types defined by the UVM standard)

    • +
    • 28 Register Access types (Covering the 25 types defined by the UVM standard)

    • Automatic documentation generation

    Automatic allocation

    Automatic address allocation

    -
    class RegBankExample extends Component{
    -  val io = new Bundle{
    +
    class RegBankExample extends Component {
    +  val io = new Bundle {
         apb = Apb3(Apb3Config(16,32))
       }
       val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte)
    @@ -1214,7 +1213,7 @@ 

    Automatic allocation

    ../../_images/field-auto-allocate.gif -

    confilict detection

    +

    conflict detection

    val M_REG1  = busif.newReg(doc="REG1")
     val r1fd0 = M_REG1.field(Bits(16 bits), RW, doc="fields 1")
     val r1fd2 = M_REG1.field(Bits(18 bits), RW, doc="fields 1")
    @@ -1420,7 +1419,7 @@ 

    Special Access UsageCASE1: RO usage

    RO is different from other types. It does not create registers and requires an external signal to drive it, Attention, please don’t forget to drive it.

    -

    - + - + - + - + - + - +

    InterruptFactory(regNamePre: String, triggers: Bool*)

    creat RAW/FORCE/MASK/STATUS for pulse event

    create RAW/FORCE/MASK/STATUS for pulse event

    InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)

    creat RAW/MASK/STATUS for pulse event

    create RAW/MASK/STATUS for pulse event

    InterruptFactory(regNamePre: String, triggers: Bool*)

    creat MASK/STATUS for level_int merge

    create MASK/STATUS for level_int merge

    InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)

    creat RAW/FORCE/MASK/STATUS for pulse event at addrOffset

    create RAW/FORCE/MASK/STATUS for pulse event at addrOffset

    InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)

    creat RAW/MASK/STATUS for pulse event at addrOffset

    create RAW/MASK/STATUS for pulse event at addrOffset

    InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)

    creat MASK/STATUS for level_int merge at addrOffset

    create MASK/STATUS for level_int merge at addrOffset

    Example

    -
    class RegFileIntrExample extends Component{
    -   val io = new Bundle{
    +
    class RegFileIntrExample extends Component {
    +   val io = new Bundle {
          val apb = slave(Apb3(Apb3Config(16,32)))
          val int_pulse0, int_pulse1, int_pulse2, int_pulse3 = in Bool()
          val int_level0, int_level1, int_level2 = in Bool()
    @@ -1766,7 +1765,7 @@ 

    Developers Area diff --git a/master/SpinalHDL/Libraries/stream.html b/master/SpinalHDL/Libraries/stream.html index 020fd737e2f..32e0a1e8f51 100644 --- a/master/SpinalHDL/Libraries/stream.html +++ b/master/SpinalHDL/Libraries/stream.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1406,7 +1405,7 @@

    Functions
    case class RGB(channelWidth : Int) extends Bundle{
    +../../_images/stream_throw_m2spipe.svg
    case class RGB(channelWidth : Int) extends Bundle {
       val red   = UInt(channelWidth bits)
       val green = UInt(channelWidth bits)
       val blue  = UInt(channelWidth bits)
    @@ -1757,7 +1756,7 @@ 

    StreamArbiter

    StreamJoin

    -

    This utile takes multiple input streams and wait until all of them fire before letting all of them through.

    +

    This utility takes multiple input streams and waits until all of them fire valid before letting all of them through by providing ready.

    val cmdJoin = Stream(Cmd())
     cmdJoin.arbitrationFrom(StreamJoin.arg(cmdABuffer, cmdBBuffer))
     
    @@ -1952,7 +1951,7 @@

    Simulation support

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/utils.html b/master/SpinalHDL/Libraries/utils.html index 4a4c9ae8390..227f5f93210 100644 --- a/master/SpinalHDL/Libraries/utils.html +++ b/master/SpinalHDL/Libraries/utils.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1401,7 +1400,7 @@

    Timeout
    val timeout = Timeout(10 ms)  //Timeout who tick after 10 ms
    -when(timeout){                //Check if the timeout has tick
    +when(timeout) {               //Check if the timeout has tick
         timeout.clear()           //Ask the timeout to clear its flag
     }
     
    @@ -1416,7 +1415,7 @@

    ResetCtrl

    asyncAssertSyncDeassert

    -

    You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ResetCtrl.asyncAssertSyncDeassert function which will return you the filtred value.

    +

    You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ResetCtrl.asyncAssertSyncDeassert function which will return you the filtered value.

    @@ -1452,7 +1451,7 @@

    asyncAssertSyncDeassert

    -

    There is also an ResetCtrl.asyncAssertSyncDeassertDrive version of tool which directly assign the clockDomain reset with the filtred value.

    +

    There is also an ResetCtrl.asyncAssertSyncDeassertDrive version of tool which directly assign the clockDomain reset with the filtered value.

    @@ -1474,7 +1473,7 @@

    Special utilities

    LatencyAnalysis(paths : Node*)

    Int

    -
    Return the shortest path,in therm of cycle, that travel through all nodes,
    +
    Return the shortest path, in terms of cycles, that travel through all nodes,
    from the first one to the last one
    @@ -1513,7 +1512,7 @@

    Special utilities

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Libraries/vexriscv.html b/master/SpinalHDL/Libraries/vexriscv.html index 9830214c570..e95eeee614c 100644 --- a/master/SpinalHDL/Libraries/vexriscv.html +++ b/master/SpinalHDL/Libraries/vexriscv.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1219,7 +1218,7 @@

    VexRiscv (RV32IM CPU) diff --git a/master/SpinalHDL/Other language features/analog_inout.html b/master/SpinalHDL/Other language features/analog_inout.html index 649c22f3eb8..5e25a67c32a 100644 --- a/master/SpinalHDL/Other language features/analog_inout.html +++ b/master/SpinalHDL/Other language features/analog_inout.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1319,7 +1318,7 @@

    Manually driving Analog bundles

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Other language features/assertion.html b/master/SpinalHDL/Other language features/assertion.html index d55ab7183eb..38beecfcb9e 100644 --- a/master/SpinalHDL/Other language features/assertion.html +++ b/master/SpinalHDL/Other language features/assertion.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1249,7 +1248,7 @@

    Assertions

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Other language features/index.html b/master/SpinalHDL/Other language features/index.html index 9c9f77f945b..290b4240c77 100644 --- a/master/SpinalHDL/Other language features/index.html +++ b/master/SpinalHDL/Other language features/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1218,7 +1217,7 @@

    Other language features diff --git a/master/SpinalHDL/Other language features/report.html b/master/SpinalHDL/Other language features/report.html index e2ec47868e5..b38bda88a15 100644 --- a/master/SpinalHDL/Other language features/report.html +++ b/master/SpinalHDL/Other language features/report.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1225,7 +1224,7 @@

    Report diff --git a/master/SpinalHDL/Other language features/scope_property.html b/master/SpinalHDL/Other language features/scope_property.html index 659228e8adb..e2ad948ce56 100644 --- a/master/SpinalHDL/Other language features/scope_property.html +++ b/master/SpinalHDL/Other language features/scope_property.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1172,7 +1171,7 @@

    ScopeProperty

    -

    A scope property is a thing which can store values localy to the current thread. Its API can be used to set/get that value, but also to apply modification to the value for a portion of the execution in a stack manner.

    +

    A scope property is a thing which can store values locally to the current thread. Its API can be used to set/get that value, but also to apply modification to the value for a portion of the execution in a stack manner.

    In other words it is a alternative to global variable, scala implicit, ThreadLocal.

    • To compare with global variable, It allow to run multiple thread running the same code indepedently

    • @@ -1181,12 +1180,12 @@
    object Xlen extends ScopeProperty[Int]
     
    -object ScopePropertyMiaou extends App{
    +object ScopePropertyMiaou extends App {
       Xlen.set(1)
       println(Xlen.get) //1
    -  Xlen(2){
    +  Xlen(2) {
         println(Xlen.get) //2
    -    Xlen(3){
    +    Xlen(3) {
           println(Xlen.get) //3
           Xlen.set(4)
           println(Xlen.get) //4
    @@ -1227,7 +1226,7 @@
         
         
         
         
     
    diff --git a/master/SpinalHDL/Other language features/stub.html b/master/SpinalHDL/Other language features/stub.html
    index d76f8ba0ea5..a8c2e087800 100644
    --- a/master/SpinalHDL/Other language features/stub.html	
    +++ b/master/SpinalHDL/Other language features/stub.html	
    @@ -973,7 +973,6 @@
     
     
     
    -
  • Introduction
  • Getting started
  • @@ -1172,15 +1171,15 @@

    Stub

    -

    You can emtpy an Component Hierarchy as stub:

    -
    class SubSysModule extends Component{
    -   val io = new Bundle{
    +

    You can empty an Component Hierarchy as stub:

    +
    class SubSysModule extends Component {
    +   val io = new Bundle {
          val dx = slave(Stream(Bits(32 bits)))
          val dy = master(Stream(Bits(32 bits)))
        }
        io.dy <-< io.dx
     }
    -class TopLevle extends Component {
    +class TopLevel extends Component {
        val dut = new SubSysModule().stub   //instance an SubSysModule as empty stub
     }
     
    @@ -1205,15 +1204,15 @@

    Stubendmodule

    -

    You can also emtpy the top Compoent

    +

    You can also empty the top Component

    SpinalVerilog(new Pinsec(500 MHz).stub)
     
    -

    what stub do

    +

    What does stub do ?

      -
    • first walk all the component and find out clock ,then keep clock

    • -
    • remove all children component

    • -
    • reomove all assignment and logic we dont wan’t

    • +
    • first walk all the components and find out clock, then keep clock

    • +
    • then remove all children component

    • +
    • then remove all assignment and logic we dont want

    • tile 0 to output port

    @@ -1247,7 +1246,7 @@

    Stub diff --git a/master/SpinalHDL/Other language features/utils.html b/master/SpinalHDL/Other language features/utils.html index b29680e0a01..7318cdaead0 100644 --- a/master/SpinalHDL/Other language features/utils.html +++ b/master/SpinalHDL/Other language features/utils.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1244,7 +1243,7 @@

    Cloning hardware datatypes +
    // An example of a regular 'class' with 'override def clone()' function
    +class MyBundle(ppp : Int) extends Bundle {
    +   val a = UInt(ppp bits)
    +   override def clone = new MyBundle(ppp)
    + }
    + val x = new MyBundle(3)
    + val typeDef = HardType(new MyBundle(3))
    + val y = typeDef()
    +
    + cloneOf(x) // Need clone method, else it errors
    + cloneOf(y) // Is ok
    +
    +

    Passing a datatype as construction parameter

    @@ -1309,12 +1321,12 @@

    The safe way

    Frequency and time

    SpinalHDL has a dedicated syntax to define frequency and time values:

    -
    val frequency = 100 MHz
    -val timeoutLimit = 3 ms
    -val period = 100 us
    +
    val frequency = 100 MHz      // infers type TimeNumber
    +val timeoutLimit = 3 ms      // infers type HertzNumber
    +val period = 100 us          // infers type TimeNumber
     
    -val periodCycles = frequency * period
    -val timeoutCycles = frequency * timeoutLimit
    +val periodCycles = frequency * period             // infers type BigDecimal
    +val timeoutCycles = frequency * timeoutLimit      // infers type BigDecimal
     
    diff --git a/master/SpinalHDL/Semantic/index.html b/master/SpinalHDL/Semantic/index.html index 2da843be4ef..7c5270e05ab 100644 --- a/master/SpinalHDL/Semantic/index.html +++ b/master/SpinalHDL/Semantic/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1232,7 +1231,7 @@ diff --git a/master/SpinalHDL/Semantic/rules.html b/master/SpinalHDL/Semantic/rules.html index b5981536b0b..e5a40c9ed75 100644 --- a/master/SpinalHDL/Semantic/rules.html +++ b/master/SpinalHDL/Semantic/rules.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1360,7 +1359,7 @@

    Signal and register interactions with Scala (OOP reference + Functions) diff --git a/master/SpinalHDL/Semantic/when_switch.html b/master/SpinalHDL/Semantic/when_switch.html index a0975407ecc..2af6334c71e 100644 --- a/master/SpinalHDL/Semantic/when_switch.html +++ b/master/SpinalHDL/Semantic/when_switch.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1423,7 +1422,7 @@

    Example diff --git a/master/SpinalHDL/Sequential logic/index.html b/master/SpinalHDL/Sequential logic/index.html index 32b7c42409f..91965ef43df 100644 --- a/master/SpinalHDL/Sequential logic/index.html +++ b/master/SpinalHDL/Sequential logic/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1225,7 +1224,7 @@

    Sequential logic

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Sequential logic/memory.html b/master/SpinalHDL/Sequential logic/memory.html index 54814273769..ed4f59542f9 100644 --- a/master/SpinalHDL/Sequential logic/memory.html +++ b/master/SpinalHDL/Sequential logic/memory.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1666,7 +1665,7 @@

    Standard memory blackboxes

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Sequential logic/registers.html b/master/SpinalHDL/Sequential logic/registers.html index 7342339c17c..4604ae405a5 100644 --- a/master/SpinalHDL/Sequential logic/registers.html +++ b/master/SpinalHDL/Sequential logic/registers.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1417,7 +1416,7 @@

    Transforming a wire into a register

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/bootstraps.html b/master/SpinalHDL/Simulation/bootstraps.html index 5d2eef10a02..606ce150842 100644 --- a/master/SpinalHDL/Simulation/bootstraps.html +++ b/master/SpinalHDL/Simulation/bootstraps.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1325,7 +1324,7 @@

    Configuration} -

    Note that by default, the simulation files will be placed into the simWorkspace/xxx folders. You can override the simWorkspace location by setting the SPINALSIM_WORKSPACE environnement variable.

    +

    Note that by default, the simulation files will be placed into the simWorkspace/xxx folders. You can override the simWorkspace location by setting the SPINALSIM_WORKSPACE environment variable.

    Running multiple tests on the same hardware

    @@ -1383,7 +1382,7 @@

    Throw Success or Failure of the simulation from a thread

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/clock.html b/master/SpinalHDL/Simulation/clock.html index f4b2fb11aa3..3cfaa914077 100644 --- a/master/SpinalHDL/Simulation/clock.html +++ b/master/SpinalHDL/Simulation/clock.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1187,7 +1186,7 @@

    Stimulus API

    forkStimulus(period)

    -

    Fork a simulation process to generate the clockdomain stimulus (clock, reset, softReset, clockEnable signals)

    +

    Fork a simulation process to generate the ClockDomain stimulus (clock, reset, softReset, clockEnable signals)

    forkSimSpeedPrinter(printPeriod)

    Fork a simulation process which will periodically print the simulation speed in kilo-cycles per real time second. printPeriod is in realtime seconds

    @@ -1267,7 +1266,7 @@

    Wait API

    Warning

    -

    All the functionalities of the wait API can only be called from inside of a thread, and not from a callback.

    +

    All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API.

    @@ -1372,7 +1371,7 @@

    New ClockDomain

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/engine.html b/master/SpinalHDL/Simulation/engine.html index 11bf7b17bbd..52e6de44ba8 100644 --- a/master/SpinalHDL/Simulation/engine.html +++ b/master/SpinalHDL/Simulation/engine.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1225,7 +1224,7 @@

    Simulation engine

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/examples/asynchronous.html b/master/SpinalHDL/Simulation/examples/asynchronous.html index 13a6f0f2a97..858ae093e30 100644 --- a/master/SpinalHDL/Simulation/examples/asynchronous.html +++ b/master/SpinalHDL/Simulation/examples/asynchronous.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1246,7 +1245,7 @@ diff --git a/master/SpinalHDL/Simulation/examples/dual_clock_fifo.html b/master/SpinalHDL/Simulation/examples/dual_clock_fifo.html index 0e1bb8130d6..4bf55e0cd60 100644 --- a/master/SpinalHDL/Simulation/examples/dual_clock_fifo.html +++ b/master/SpinalHDL/Simulation/examples/dual_clock_fifo.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1291,7 +1290,7 @@ diff --git a/master/SpinalHDL/Simulation/examples/index.html b/master/SpinalHDL/Simulation/examples/index.html index cfed2684cc0..202de254d13 100644 --- a/master/SpinalHDL/Simulation/examples/index.html +++ b/master/SpinalHDL/Simulation/examples/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1213,7 +1212,7 @@

    Examples

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/examples/single_clock_fifo.html b/master/SpinalHDL/Simulation/examples/single_clock_fifo.html index dce64d5cf74..7ac4f8ebb0d 100644 --- a/master/SpinalHDL/Simulation/examples/single_clock_fifo.html +++ b/master/SpinalHDL/Simulation/examples/single_clock_fifo.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1269,7 +1268,7 @@ diff --git a/master/SpinalHDL/Simulation/examples/synchronous.html b/master/SpinalHDL/Simulation/examples/synchronous.html index 4bac6eecad8..d6f200d11bf 100644 --- a/master/SpinalHDL/Simulation/examples/synchronous.html +++ b/master/SpinalHDL/Simulation/examples/synchronous.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1248,7 +1247,7 @@ diff --git a/master/SpinalHDL/Simulation/examples/uart_decoder.html b/master/SpinalHDL/Simulation/examples/uart_decoder.html index 6f10af0a68c..6bfbc6a4879 100644 --- a/master/SpinalHDL/Simulation/examples/uart_decoder.html +++ b/master/SpinalHDL/Simulation/examples/uart_decoder.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1229,7 +1228,7 @@

    Uart decoder

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/examples/uart_encoder.html b/master/SpinalHDL/Simulation/examples/uart_encoder.html index 7e2bf61a4b5..0db221ed8de 100644 --- a/master/SpinalHDL/Simulation/examples/uart_encoder.html +++ b/master/SpinalHDL/Simulation/examples/uart_encoder.html @@ -973,7 +973,6 @@ -
  • Introduction
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  • @@ -1228,7 +1227,7 @@

    Uart encoder

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/index.html b/master/SpinalHDL/Simulation/index.html index f43f17ebb7d..c867dbd4c1a 100644 --- a/master/SpinalHDL/Simulation/index.html +++ b/master/SpinalHDL/Simulation/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1174,10 +1173,11 @@

    Simulation -
  • Verilator

  • +
  • Verilator

  • GHDL (experimental, since SpinalHDL 1.4.1)

  • -
  • Icarus Verilog (experimental, since SpinalHDL 1.4.1)

  • +
  • Icarus Verilog (experimental, since SpinalHDL 1.4.1)

  • VCS (experimental, since SpinalHDL 1.7.0)

  • +
  • XSim (experimental, since SpinalHDL 1.7.0)

  • With external HDL simulators it is possible to directly test the generated HDL sources without increasing the SpinalHDL codebase complexity.

    diff --git a/master/SpinalHDL/Simulation/install/GHDL.html b/master/SpinalHDL/Simulation/install/GHDL.html index f897d19e913..a10142980e5 100644 --- a/master/SpinalHDL/Simulation/install/GHDL.html +++ b/master/SpinalHDL/Simulation/install/GHDL.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1222,7 +1221,7 @@

    Linux diff --git a/master/SpinalHDL/Simulation/install/Icarus Verilog.html b/master/SpinalHDL/Simulation/install/Icarus Verilog.html index e7751e1f05c..f1078688b88 100644 --- a/master/SpinalHDL/Simulation/install/Icarus Verilog.html +++ b/master/SpinalHDL/Simulation/install/Icarus Verilog.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1214,7 +1213,7 @@

    Linux diff --git a/master/SpinalHDL/Simulation/install/VCS.html b/master/SpinalHDL/Simulation/install/VCS.html index cd0768a584a..6f091a140ad 100644 --- a/master/SpinalHDL/Simulation/install/VCS.html +++ b/master/SpinalHDL/Simulation/install/VCS.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1332,7 +1331,7 @@

    Simulation with diff --git a/master/SpinalHDL/Simulation/install/Verilator.html b/master/SpinalHDL/Simulation/install/Verilator.html index 3cdc6348828..615e6688854 100644 --- a/master/SpinalHDL/Simulation/install/Verilator.html +++ b/master/SpinalHDL/Simulation/install/Verilator.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1174,6 +1173,12 @@

    Setup and installation of Verilator

    SpinalSim + Verilator is supported on both Linux and Windows platforms.

    +

    It is recommended that v4.218 is the oldest Verilator version to use. While it maybe +possible to use older verilator versions, some optional and Scala source dependent +features that SpinalHDL can use (such as Verilog $urandom support) may not be supported +by older Verilator versions and will cause an error when trying to simulate.

    +

    Ideally the latest v4.xxx and v5.xxx is well supported and bug reports should be opened +with any issues you have.

    Scala

    Don’t forget to add the following in your build.sbt file:

    @@ -1194,9 +1199,9 @@

    Linux unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator -git pull # Make sure we're up-to-date -git checkout v4.218 -autoconf # Create ./configure script +git pull # Make sure we're up-to-date +git checkout v4.218 # Can use newer v4.228 and v5.xxx +autoconf # Create ./configure script ./configure make -j$(nproc) sudo make install @@ -1243,7 +1248,7 @@

    From sourceunset VERILATOR_ROOT cd verilator git pull -git checkout v4.040 +git checkout v4.218 # Can use newer v4.228 and v5.xxx autoconf ./configure export CPLUS_INCLUDE_PATH=/usr/include:$CPLUS_INCLUDE_PATH @@ -1298,7 +1303,7 @@

    From source

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/install/index.html b/master/SpinalHDL/Simulation/install/index.html index d0e9e7a6d5d..54f377b26c6 100644 --- a/master/SpinalHDL/Simulation/install/index.html +++ b/master/SpinalHDL/Simulation/install/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1248,7 +1247,7 @@

    Backend-dependent installation instructions

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/sensitive.html b/master/SpinalHDL/Simulation/sensitive.html index a4227506e6a..09bac6a10a3 100644 --- a/master/SpinalHDL/Simulation/sensitive.html +++ b/master/SpinalHDL/Simulation/sensitive.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1223,7 +1222,7 @@ diff --git a/master/SpinalHDL/Simulation/signal.html b/master/SpinalHDL/Simulation/signal.html index 85b9ac1055e..f51002ba434 100644 --- a/master/SpinalHDL/Simulation/signal.html +++ b/master/SpinalHDL/Simulation/signal.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1265,7 +1264,7 @@

    Accessing signals inside the component’s hierarchy def main(args: Array[String]) { SimConfig.compile { val dut = new TopLevel - dut.counter.simPublic() + dut.counter.simPublic() // Call simPublic() here dut }.doSim{dut => dut.clockDomain.forkStimulus(10) @@ -1311,7 +1310,7 @@

    Accessing signals inside the component’s hierarchy diff --git a/master/SpinalHDL/Simulation/simulator_specifics.html b/master/SpinalHDL/Simulation/simulator_specifics.html index 301605d8e83..d5db9605d3d 100644 --- a/master/SpinalHDL/Simulation/simulator_specifics.html +++ b/master/SpinalHDL/Simulation/simulator_specifics.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1176,7 +1175,7 @@

    Simulator specific details

    1. Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model of the DUT and then uses Verilator to convert it to a C++ cycle-accurate model.

    2. -
    3. The C++ model is compiled into a shared object (.so), which is bound to Scala via JNR-FFI.

    4. +
    5. The C++ model is compiled into a shared object (.so), which is bound to Scala via JNI-FFI.

    6. The native Verilator API is abstracted by providing a simulation multi-threaded API.

    Advantages:

    @@ -1187,7 +1186,7 @@

    How SpinalHDL simulates the hardware with Verilator backend
  • Verilator accepts only synthesizable Verilog/System Verilog code. Therefore special care has to be taken when simulating Verilog blackbox components that may have non-synthesizable statements.

  • VHDL blackboxes cannot be simulated.

  • -
  • The simulation boot process is slow due to the necessity to compile and link the generated C++ model

  • +
  • The simulation boot process is slow due to the necessity to compile and link the generated C++ model. Some support to incrementally compile and link exists which can provide speedups for subsequent simulations after building the first.

  • @@ -1265,7 +1264,7 @@

    Performance

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/threadFull.html b/master/SpinalHDL/Simulation/threadFull.html index 3380be814f9..3d330b561db 100644 --- a/master/SpinalHDL/Simulation/threadFull.html +++ b/master/SpinalHDL/Simulation/threadFull.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1227,7 +1226,7 @@

    Sleep and waitUntil

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Simulation/threadLess.html b/master/SpinalHDL/Simulation/threadLess.html index ecef39849df..6ea87fff01c 100644 --- a/master/SpinalHDL/Simulation/threadLess.html +++ b/master/SpinalHDL/Simulation/threadLess.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1228,7 +1227,7 @@

    Thread-less API

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Structuring/area.html b/master/SpinalHDL/Structuring/area.html index 424598f61ea..ec78d1fc32c 100644 --- a/master/SpinalHDL/Structuring/area.html +++ b/master/SpinalHDL/Structuring/area.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1247,7 +1246,7 @@

    Area diff --git a/master/SpinalHDL/Structuring/blackbox.html b/master/SpinalHDL/Structuring/blackbox.html index 48b0566dbd9..764f59f32c9 100644 --- a/master/SpinalHDL/Structuring/blackbox.html +++ b/master/SpinalHDL/Structuring/blackbox.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1512,7 +1511,7 @@

    VHDL - No numeric type diff --git a/master/SpinalHDL/Structuring/clock_domain.html b/master/SpinalHDL/Structuring/clock_domain.html index 676a8cad25a..7aa1792315c 100644 --- a/master/SpinalHDL/Structuring/clock_domain.html +++ b/master/SpinalHDL/Structuring/clock_domain.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1765,7 +1764,7 @@

    ClockEnableArea

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Structuring/components_hierarchy.html b/master/SpinalHDL/Structuring/components_hierarchy.html index 80a45a2dffd..5d5866f1861 100644 --- a/master/SpinalHDL/Structuring/components_hierarchy.html +++ b/master/SpinalHDL/Structuring/components_hierarchy.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1404,7 +1403,7 @@

    Synthesized component names

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Structuring/function.html b/master/SpinalHDL/Structuring/function.html index 8056d17b93f..dd92b94f7d9 100644 --- a/master/SpinalHDL/Structuring/function.html +++ b/master/SpinalHDL/Structuring/function.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1271,7 +1270,7 @@

    Valid Ready Payload bus diff --git a/master/SpinalHDL/Structuring/index.html b/master/SpinalHDL/Structuring/index.html index 60afd342e0c..c1a976e7491 100644 --- a/master/SpinalHDL/Structuring/index.html +++ b/master/SpinalHDL/Structuring/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1281,7 +1280,7 @@

    Structuring

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Structuring/naming.html b/master/SpinalHDL/Structuring/naming.html index 38912d0b60d..4670a96f069 100644 --- a/master/SpinalHDL/Structuring/naming.html +++ b/master/SpinalHDL/Structuring/naming.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1677,7 +1676,7 @@

    In last resort

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/Structuring/parametrization.html b/master/SpinalHDL/Structuring/parametrization.html index 893e4493bb8..fe29ebc95fa 100644 --- a/master/SpinalHDL/Structuring/parametrization.html +++ b/master/SpinalHDL/Structuring/parametrization.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1241,7 +1240,7 @@

    Elaboration time parametersScopeProperty can also be used for configuration.

    +

    A ScopeProperty can also be used for configuration.

    Optional hardware

    @@ -1317,7 +1316,7 @@

    Optional hardware

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/miscelenea/chisel.html b/master/SpinalHDL/miscelenea/chisel.html index f59acbf30fa..511bd1e828a 100644 --- a/master/SpinalHDL/miscelenea/chisel.html +++ b/master/SpinalHDL/miscelenea/chisel.html @@ -971,7 +971,6 @@ -
  • Introduction
  • Getting started
  • @@ -1198,7 +1197,7 @@ diff --git a/master/SpinalHDL/miscelenea/core/core_components.html b/master/SpinalHDL/miscelenea/core/core_components.html index 7dce32022d9..66ecb1aa465 100644 --- a/master/SpinalHDL/miscelenea/core/core_components.html +++ b/master/SpinalHDL/miscelenea/core/core_components.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1758,7 +1757,7 @@

    Utils diff --git a/master/SpinalHDL/miscelenea/core/elements.html b/master/SpinalHDL/miscelenea/core/elements.html index 539fdf1b620..7867ab79aa9 100644 --- a/master/SpinalHDL/miscelenea/core/elements.html +++ b/master/SpinalHDL/miscelenea/core/elements.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1271,7 +1270,7 @@ diff --git a/master/SpinalHDL/miscelenea/frequent_errors.html b/master/SpinalHDL/miscelenea/frequent_errors.html index 013fc78cbc7..56dcf428689 100644 --- a/master/SpinalHDL/miscelenea/frequent_errors.html +++ b/master/SpinalHDL/miscelenea/frequent_errors.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1310,7 +1309,7 @@

    Output signal X can’t be assigned by Y

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/SpinalHDL/miscelenea/index.html b/master/SpinalHDL/miscelenea/index.html index 4a7284ffcd9..4831d88610e 100644 --- a/master/SpinalHDL/miscelenea/index.html +++ b/master/SpinalHDL/miscelenea/index.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1215,7 +1214,7 @@

    Miscellaneous

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/_sources/SpinalHDL/Data types/Fix.rst.txt b/master/_sources/SpinalHDL/Data types/Fix.rst.txt index 0a8e32d76bc..99ded038b26 100644 --- a/master/_sources/SpinalHDL/Data types/Fix.rst.txt +++ b/master/_sources/SpinalHDL/Data types/Fix.rst.txt @@ -219,7 +219,7 @@ Comparison * - x >= y - Greater than or equal - Bool - * - x > y + * - x < y - Less than - Bool * - x >= y diff --git a/master/_sources/SpinalHDL/Examples/index.rst.txt b/master/_sources/SpinalHDL/Examples/index.rst.txt index a7c7320c31b..dbb892f8d84 100644 --- a/master/_sources/SpinalHDL/Examples/index.rst.txt +++ b/master/_sources/SpinalHDL/Examples/index.rst.txt @@ -15,9 +15,6 @@ Examples .. _example_introduction: -Introduction -============ - Examples are split into three kinds: * Simple examples that could be used to get used to the basics of SpinalHDL. diff --git a/master/_sources/SpinalHDL/Formal verification/index.rst.txt b/master/_sources/SpinalHDL/Formal verification/index.rst.txt index dd3523fe5d0..490c78dd814 100644 --- a/master/_sources/SpinalHDL/Formal verification/index.rst.txt +++ b/master/_sources/SpinalHDL/Formal verification/index.rst.txt @@ -37,7 +37,7 @@ Installing requirements To install the Symbi-Yosys, you have a few options. You can fetch a precompiled package at: - https://github.com/YosysHQ/oss-cad-suite-build/releases -- https://github.com/YosysHQ/fpga-toolchain/releases +- https://github.com/YosysHQ/fpga-toolchain/releases (EOL - superseded by oss-cad-suite) Or you can compile things from scratch : @@ -59,10 +59,10 @@ Here is an example of a simple counter and the corresponding formal testbench. import spinal.core._ //Here is our DUT - class LimitedCounter extends Component{ + class LimitedCounter extends Component { //The value register will always be between [2:10] val value = Reg(UInt(4 bits)) init(2) - when(value < 10){ + when(value < 10) { value := value + 1 } } @@ -94,9 +94,9 @@ If you want you can embed formal statements directly into the DUT: .. code-block:: scala - class LimitedCounterEmbedded extends Component{ + class LimitedCounterEmbedded extends Component { val value = Reg(UInt(4 bits)) init(2) - when(value < 10){ + when(value < 10) { value := value + 1 } @@ -124,11 +124,11 @@ but you can also use the formal `anyseq`, `anyconst`, `allseq`, `allconst` state .. code-block:: scala - class LimitedCounterInc extends Component{ + class LimitedCounterInc extends Component { //Only increment the value when the inc input is set val inc = in Bool() val value = Reg(UInt(4 bits)) init(2) - when(inc && value < 10){ + when(inc && value < 10) { value := value + 1 } } @@ -160,7 +160,7 @@ For instance we can check that the value is counting up (if not already at 10): // Check that the value is incrementing. // hasPast is used to ensure that the past(dut.value) had at least one sampling out of reset - when(pastValid() && past(dut.value) =/= 10){ + when(pastValid() && past(dut.value) =/= 10) { assert(dut.value === past(dut.value) + 1) } }) @@ -172,7 +172,7 @@ Here is an example where we want to prevent the value ``1`` from ever being pres .. code-block:: scala - class DutWithRam extends Component{ + class DutWithRam extends Component { val ram = Mem.fill(4)(UInt(8 bits)) val write = slave(ram.writePort) val read = slave(ram.readAsyncPort) @@ -186,13 +186,13 @@ Here is an example where we want to prevent the value ``1`` from ever being pres assumeInitial(ClockDomain.current.isResetActive) // assume that no word in the ram has the value 1 - for(i <- 0 until dut.ram.wordCount){ + for(i <- 0 until dut.ram.wordCount) { assumeInitial(dut.ram(i) =/= 1) } // Allow the write anything but value 1 in the ram anyseq(dut.write) - clockDomain.withoutReset(){ //As the memory write can occur during reset, we need to ensure the assume apply there too + clockDomain.withoutReset() { //As the memory write can occur during reset, we need to ensure the assume apply there too assume(dut.write.data =/= 1) } @@ -215,7 +215,7 @@ If you want to keep your assertion enabled during reset you can do: .. code-block:: scala - ClockDomain.current.withoutReset(){ + ClockDomain.current.withoutReset() { assert(wuff === 0) } @@ -244,7 +244,7 @@ If you have a Mem in your design, and you want to check its content, you can do .. code-block:: scala // Manual access - for(i <- 0 until dut.ram.wordCount){ + for(i <- 0 until dut.ram.wordCount) { assumeInitial(dut.ram(i) =/= X) //No occurence of the word X } @@ -294,10 +294,10 @@ Formal primitives - Return True when ``that`` transitioned from True to False * - ``changed(that : Bool)`` - Bool - - Return True when ``that`` current value changed between comparred to the last cycle + - Return True when ``that`` current value changed between compared to the last cycle * - ``stable(that : Bool)`` - Bool - - Return True when ``that`` current value didn't changed between comparred to the last cycle + - Return True when ``that`` current value didn't changed between compared to the last cycle * - ``initstate()`` - Bool - Return True the first cycle @@ -306,13 +306,13 @@ Formal primitives - Returns True when the past value is valid (False on the first cycle). Recommended to be used with each application of ``past``, ``rose``, ``fell``, ``changed`` and ``stable``. * - ``pastValidAfterReset()`` - Bool - - Simliar to ``pastValid``, where only difference is that this would take reset into account. Can be understand as ``pastValid & past(!reset)``. + - Simliar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``. Note that you can use the init statement on past: .. code-block:: scala - when(past(enable) init(False)){ ... } + when(past(enable) init(False)) { ... } diff --git a/master/_sources/SpinalHDL/Libraries/Com/usb_device.rst.txt b/master/_sources/SpinalHDL/Libraries/Com/usb_device.rst.txt index f163a4ece01..5cc04e06849 100644 --- a/master/_sources/SpinalHDL/Libraries/Com/usb_device.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/Com/usb_device.rst.txt @@ -1,8 +1,10 @@ USB device -============ +========== -There is a USB device controller in the SpinalHDL library. In a few bullet points it can be resumed to : +Here exists a USB device controller in the SpinalHDL library. + +A few bullet points to summarise support: - Implemented to allow a CPU to configure and manage the endpoints - A internal ram which store the endpoints states and transactions descriptors @@ -27,23 +29,23 @@ Deployments : Architecture --------------- +------------ The controller is composed of : - A few control registers - A internal ram used to store the endpoint status, the transfer descriptors and the endpoint 0 SETUP data. -A linked list of descriptors for each endpoint in order to handle of the USB IN/OUT transactions and data. +A linked list of descriptors for each endpoint in order to handle the USB IN/OUT transactions and data. The endpoint 0 manage the IN/OUT transactions like all the other endpoints but has some additional hardware to manage the SETUP transactions : - Its linked list is cleared on each setup transactions -- The data of the SETUP transaction are stored in a fixed location (SETUP_DATA) +- The data from the SETUP transaction is stored in a fixed location (SETUP_DATA) - It has a specific interrupt flag for SETUP transactions Registers --------------- +--------- Note that all registers and memories of the controller are only accessible in 32 bits word access, bytes access isn't supported. @@ -79,36 +81,37 @@ finalise the SET_ADDRESS sequance. The controller will then automaticaly turn on INTERRUPT (0xFF08) ********************** -All bits of this register can be cleared by writing '1' in them. - -+--------------+------+-----------+------------------------------------------------------------------+ -| Name | Type | Bits | Description | -+==============+======+===========+==================================================================+ -| endpoints | RC | 15-0 | Raised when a enpoint generate a interrupt | -+--------------+------+-----------+------------------------------------------------------------------+ -| reset | RC | 16 | Raised when a USB reset appeared | -+--------------+------+-----------+------------------------------------------------------------------+ -| ep0Setup | RC | 17 | Raised when endpoint 0 receive a setup transaction | -+--------------+------+-----------+------------------------------------------------------------------+ -| suspend | RC | 18 | Raised when a USB suspend appeared | -+--------------+------+-----------+------------------------------------------------------------------+ -| resume | RC | 19 | Raised when a USB resume appeared | -+--------------+------+-----------+------------------------------------------------------------------+ -| disconnect | RC | 20 | Raised when a USB disconnect appeared | -+--------------+------+-----------+------------------------------------------------------------------+ +Individual bits of this register can be cleared by writing '1' in them. +Reading this register returns the current interrupt status. + ++--------------+-------+-----------+------------------------------------------------------------------+ +| Name | Type | Bits | Description | ++==============+=======+===========+==================================================================+ +| endpoints | W1C | 15-0 | Raised when an endpoint generates an interrupt | ++--------------+-------+-----------+------------------------------------------------------------------+ +| reset | W1C | 16 | Raised when a USB reset occurs | ++--------------+-------+-----------+------------------------------------------------------------------+ +| ep0Setup | W1C | 17 | Raised when endpoint 0 receives a setup transaction | ++--------------+-------+-----------+------------------------------------------------------------------+ +| suspend | W1C | 18 | Raised when a USB suspend occurs | ++--------------+-------+-----------+------------------------------------------------------------------+ +| resume | W1C | 19 | Raised when a USB resume occurs | ++--------------+-------+-----------+------------------------------------------------------------------+ +| disconnect | W1C | 20 | Raised when a USB disconnect occurs | ++--------------+-------+-----------+------------------------------------------------------------------+ HALT (0xFF0C) ********************** -This register allow to place a single enpoint in a dormant state in order to ensure atomicity of CPU operations, allowing to do things as read/modify/write on the endpoint registers and descriptors. -The peripheral will return NAK if the given endpoint is addressed by the usb host. +This register allows placement of a single endpoint into a dormant state in order to ensure atomicity of CPU operations, allowing to do things as read/modify/write on the endpoint registers and descriptors. +The peripheral will return NAK if the given endpoint is addressed by the usb host while halt is enabled and the endpoint is enabled. +-------------------------+------+-----------+------------------------------------------------------------------+ | Name | Type | Bits | Description | +=========================+======+===========+==================================================================+ | endpointId | WO | 3-0 | The endpoint you want to put in sleep | +-------------------------+------+-----------+------------------------------------------------------------------+ -| enable | WO | 4 | | +| enable | WO | 4 | When set halt is active, when clear endpoint is unhalted. | +-------------------------+------+-----------+------------------------------------------------------------------+ | effective | RO | 5 | After setting the enable, you need to wait for this bit to be | | enable | | | set by the hardware itself to ensure atomicity | @@ -168,7 +171,7 @@ To get a endpoint responsive you need : - Set its enable flag to 1 Then the there is a few cases : -- Either you have the stall or nack flag set, and so, the controller will always responde with the corresponding responses +- Either you have the stall or nack flag set, and so, the controller will always respond with the corresponding responses - Either, for EP0 setup request, the controller will not use descriptors, but will instead write the data into the SETUP_DATA register, and ACK - Either you have a empty linked list (head==0) in which case it will answer NACK - Either you have at least one descriptor pointed by head, in which case it will execute it and ACK if all was going smooth @@ -176,12 +179,12 @@ Then the there is a few cases : SETUP_DATA (0x0040 - 0x0047) ********************************* -When endpoint 0 receive a SETUP transaction, the data of the transaction will be stored at that place. +When endpoint 0 receives a SETUP transaction, the data of the transaction will be stored in this location. Descriptors ----------------------------- +----------- -Descriptors allows to specify how a endpoint need to handle the data phase of IN/OUT transactions. +Descriptors allows to specify how an endpoint needs to handle the data phase of IN/OUT transactions. They are stored in the internal ram, can be linked together via their linked lists and need to be aligned on 16 bytes boundaries +-------------------+------+-----------+------------------------------------------------------------------+ @@ -191,33 +194,33 @@ They are stored in the internal ram, can be linked together via their linked lis +-------------------+------+-----------+------------------------------------------------------------------+ | code | 0 | 19-16 | 0xF => in progress, 0x0 => success | +-------------------+------+-----------+------------------------------------------------------------------+ -| next | 1 | 15-4 | Point the the next descriptor | +| next | 1 | 15-4 | Pointer to the next descriptor | | | | | 0 => nothing, byte address = this << 4 | +-------------------+------+-----------+------------------------------------------------------------------+ | length | 1 | 31-16 | Number of bytes allocated for the data field | +-------------------+------+-----------+------------------------------------------------------------------+ | direction | 2 | 16 | '0' => OUT, '1' => IN | +-------------------+------+-----------+------------------------------------------------------------------+ -| interrupt | 2 | 17 | If set, the completion of the descriptor will generate a | +| interrupt | 2 | 17 | If set, the completion of the descriptor will generate an | | | | | interrupt. | +-------------------+------+-----------+------------------------------------------------------------------+ -| completionOnFull | 2 | 18 | Normaly, a descriptor completion only occure when a USB transfer | +| completionOnFull | 2 | 18 | Normally, a descriptor completion only occurs when a USB transfer| | | | | is smaller than the maxPacketSize. But if this field is set, | | | | | then when the descriptor become full is also a considered | | | | | as a completion event. (offset == length) | +-------------------+------+-----------+------------------------------------------------------------------+ | data1OnCompletion | 2 | 19 | force the endpoint dataPhase to DATA1 on the completion of the | -| | | | descriptoo | +| | | | descriptor | +-------------------+------+-----------+------------------------------------------------------------------+ | data | ... | ... | | +-------------------+------+-----------+------------------------------------------------------------------+ -Note, if the controller receive a frame where the IN/OUT does not match the descriptor IN/OUT, the frame will be ignored. +Note, if the controller receives a frame where the IN/OUT does not match the descriptor IN/OUT, the frame will be ignored. -Also, to initialise a descriptor, the CPU should set the code field to 0xF +Also, to initialise a descriptor, the CPU should set the code field to 0xF Usage --------------- +----- .. code-block:: scala diff --git a/master/_sources/SpinalHDL/Libraries/Com/usb_ohci.rst.txt b/master/_sources/SpinalHDL/Libraries/Com/usb_ohci.rst.txt index 6587e371d4a..6fd04a987f2 100644 --- a/master/_sources/SpinalHDL/Libraries/Com/usb_ohci.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/Com/usb_ohci.rst.txt @@ -1,17 +1,19 @@ USB OHCI -============ +======== -There is a USB OHCi controller (host) in the SpinalHDL library. In a few bullet points it can be resumed to : +Here exists a USB OHCi controller (host) in the SpinalHDL library. + +A few bullet points to summarise support: - It follow the `OpenHCI Open Host Controller Interface Specification for USB` specification (OHCI). -- It is compatible with the upstream linux / uboot OHCI drivers already. (there is also a OHCI driver on tinyUSB) -- This provide USB host full speed and low speed capabilities (12Mbps and 1.5Mbps) +- It is compatible with the upstream linux / uboot OHCI drivers already. (there is also an OHCI driver on tinyUSB) +- This provides USB host full speed and low speed capabilities (12Mbps and 1.5Mbps) - Tested on linux and uboot - One controller can host multiple ports (up to 16) - Bmb memory interface for DMA accesses - Bmb memory interace for the configuration -- Require a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz +- Requires a clock for the internal phy which is a multiple of 12 Mhz at least 48 Mhz - The controller frequency is not restricted - No external phy required @@ -26,7 +28,7 @@ Limitations : - Some USB hub (had one so far) do not like having a full speed host with low speed devices attached. - Some modern devices will not work on USB full speed (ex : Gbps ethernet adapter) -- Require memory coherency with the CPU (or the cpu need to flush his data cache in the driver) +- Require memory coherency with the CPU (or the cpu need to be able to flush its data cache in the driver) Deployments : @@ -71,7 +73,7 @@ Usage val management = phy.io.management.toIo } - object UsbHostGen extends App{ + object UsbHostGen extends App { val p = UsbOhciParameter( noPowerSwitching = true, powerSwitchingMode = true, diff --git a/master/_sources/SpinalHDL/Libraries/EDA/altera/qsysify.rst.txt b/master/_sources/SpinalHDL/Libraries/EDA/altera/qsysify.rst.txt index 0ae64bcbd5e..dfaae8fa368 100644 --- a/master/_sources/SpinalHDL/Libraries/EDA/altera/qsysify.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/EDA/altera/qsysify.rst.txt @@ -18,8 +18,8 @@ In the case of a UART controller : .. code-block:: scala - case class AvalonMMUartCtrl(...) extends Component{ - val io = new Bundle{ + case class AvalonMMUartCtrl(...) extends Component { + val io = new Bundle { val bus = slave(AvalonMM(AvalonMMUartCtrl.getAvalonMMConfig)) val uart = master(Uart()) } @@ -31,7 +31,7 @@ The following ``main`` will generate the Verilog and the QSys TCL script with i .. code-block:: scala - object AvalonMMUartCtrl{ + object AvalonMMUartCtrl { def main(args: Array[String]) { //Generate the Verilog val toplevel = SpinalVerilog(AvalonMMUartCtrl(UartCtrlMemoryMappedConfig(...))).toplevel diff --git a/master/_sources/SpinalHDL/Libraries/Graphics/colors.rst.txt b/master/_sources/SpinalHDL/Libraries/Graphics/colors.rst.txt index e81e81f2dfa..4826c517a9c 100644 --- a/master/_sources/SpinalHDL/Libraries/Graphics/colors.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/Graphics/colors.rst.txt @@ -9,11 +9,11 @@ You can use an Rgb bundle to model colors in hardware. This Rgb bundle take as p .. code-block:: scala - case class RgbConfig(rWidth : Int,gWidth : Int,bWidth : Int){ + case class RgbConfig(rWidth : Int,gWidth : Int,bWidth : Int) { def getWidth = rWidth + gWidth + bWidth } - case class Rgb(c: RgbConfig) extends Bundle{ + case class Rgb(c: RgbConfig) extends Bundle { val r = UInt(c.rWidth bits) val g = UInt(c.gWidth bits) val b = UInt(c.bWidth bits) diff --git a/master/_sources/SpinalHDL/Libraries/Graphics/vga.rst.txt b/master/_sources/SpinalHDL/Libraries/Graphics/vga.rst.txt index 88d66d5b4a2..08b23a1b7c8 100644 --- a/master/_sources/SpinalHDL/Libraries/Graphics/vga.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/Graphics/vga.rst.txt @@ -11,7 +11,7 @@ An VGA bus definition is available via the Vga bundle. .. code-block:: scala - case class Vga (rgbConfig: RgbConfig) extends Bundle with IMasterSlave{ + case class Vga (rgbConfig: RgbConfig) extends Bundle with IMasterSlave { val vSync = Bool() val hSync = Bool() @@ -46,7 +46,7 @@ VGA timings could be modeled in hardware by using an VgaTimings bundle : VGA controller -------------- -An VGA controller is available. It's definition is the following : +An VGA controller is available. Its definition is the following : .. code-block:: scala diff --git a/master/_sources/SpinalHDL/Libraries/IO/readableOpenDrain.rst.txt b/master/_sources/SpinalHDL/Libraries/IO/readableOpenDrain.rst.txt index 378d3b7c636..31c59bd3934 100644 --- a/master/_sources/SpinalHDL/Libraries/IO/readableOpenDrain.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/IO/readableOpenDrain.rst.txt @@ -6,7 +6,7 @@ The ReadableOpenDrain bundle is defined as following : .. code-block:: scala - case class ReadableOpenDrain[T<: Data](dataType : HardType[T]) extends Bundle with IMasterSlave{ + case class ReadableOpenDrain[T<: Data](dataType : HardType[T]) extends Bundle with IMasterSlave { val write,read : T = dataType() override def asMaster(): Unit = { @@ -21,11 +21,11 @@ There is an example of usage : .. code-block:: scala - val io = new Bundle{ + val io = new Bundle { val dataBus = master(ReadableOpenDrain(Bits(32 bits))) } io.dataBus.write := 0x12345678 - when(io.dataBus.read === 42){ + when(io.dataBus.read === 42) { } diff --git a/master/_sources/SpinalHDL/Libraries/IO/tristate.rst.txt b/master/_sources/SpinalHDL/Libraries/IO/tristate.rst.txt index 7cd8ebfa680..6d9fec861b3 100644 --- a/master/_sources/SpinalHDL/Libraries/IO/tristate.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/IO/tristate.rst.txt @@ -3,7 +3,7 @@ TriState ======== -Tri-state signals are weird to handle in many cases: +Tri-state signals are difficult to handle in many cases: * They are not really kind of digital things * And except for IO, they aren't used for digital design @@ -25,7 +25,7 @@ The TriState bundle is defined as following : .. code-block:: scala - case class TriState[T <: Data](dataType : HardType[T]) extends Bundle with IMasterSlave{ + case class TriState[T <: Data](dataType : HardType[T]) extends Bundle with IMasterSlave { val read,write : T = dataType() val writeEnable = Bool() @@ -42,13 +42,13 @@ There is an example of usage: .. code-block:: scala - val io = new Bundle{ + val io = new Bundle { val dataBus = master(TriState(Bits(32 bits))) } io.dataBus.writeEnable := True io.dataBus.write := 0x12345678 - when(io.dataBus.read === 42){ + when(io.dataBus.read === 42) { } @@ -61,7 +61,7 @@ It is defined as following : .. code-block:: scala - case class TriStateArray(width : BitCount) extends Bundle with IMasterSlave{ + case class TriStateArray(width : BitCount) extends Bundle with IMasterSlave { val read,write,writeEnable = Bits(width) override def asMaster(): Unit = { @@ -76,12 +76,12 @@ There is an example of usage : .. code-block:: scala - val io = new Bundle{ + val io = new Bundle { val dataBus = master(TriStateArray(32 bits) } io.dataBus.writeEnable := 0x87654321 io.dataBus.write := 0x12345678 - when(io.dataBus.read === 42){ + when(io.dataBus.read === 42) { } diff --git a/master/_sources/SpinalHDL/Libraries/binarySystem.rst.txt b/master/_sources/SpinalHDL/Libraries/binarySystem.rst.txt index f9a0bec47fe..3a3f270ee91 100644 --- a/master/_sources/SpinalHDL/Libraries/binarySystem.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/binarySystem.rst.txt @@ -171,7 +171,7 @@ Int/Long/BigInt to Binary-List $: BigInt("123451118", 10).toBinInts List(0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1) -align to fix width +align to a fixed width .. code-block:: scala @@ -179,7 +179,7 @@ align to fix width $: 39.toBinInts() List(1, 1, 1, 0, 0, 1) - $: 39.toBinInts(8) // align to 8 bit fill with 0 + $: 39.toBinInts(8) // align to 8 bit zero filled at MSB List(1, 1, 1, 0, 0, 1, 0, 0) diff --git a/master/_sources/SpinalHDL/Libraries/bus_slave_factory.rst.txt b/master/_sources/SpinalHDL/Libraries/bus_slave_factory.rst.txt index a066d9b6d42..3903c6707ac 100644 --- a/master/_sources/SpinalHDL/Libraries/bus_slave_factory.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/bus_slave_factory.rst.txt @@ -18,8 +18,8 @@ You can find more documentation about the internal implementation of the ``BusSl Functionality ------------- -| Currently there is three implementation of the ``BusSlaveFactory`` tool : APB3, AXI-lite 3 and Avalon. -| Each implementation of that tool take as argument one instance of the corresponding bus and then offer following functions to map your hardware into the memory mapping : +| There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus. +| Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping : .. list-table:: :header-rows: 1 diff --git a/master/_sources/SpinalHDL/Libraries/fiber.rst.txt b/master/_sources/SpinalHDL/Libraries/fiber.rst.txt index 5171533ecc7..c957894b3f3 100644 --- a/master/_sources/SpinalHDL/Libraries/fiber.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/fiber.rst.txt @@ -6,26 +6,29 @@ Fiber framework ==================== +.. warning:: + This framework is not expected to be used for general RTL generation and targets large system + design management and code generation. It is currently used as toplevel integration tool in SaxonSoC. + Currently in developpement. The Fiber to run the hardware elaboration in a out of order manner, a bit similarly to Makefile, where you can define rules and dependencies which will then be solved when you run a make command. It is very similar to the Scala Future feature. -Such framework complexify simple things but provide some strong feature for complex cases : +Using this framework can complicate simple things but provide some strong features for complex cases : -- You can define things before even knowing all their requirements, ex : instanciating a interruption controller, before knowing how many lines of interrupt you need +- You can define things before even knowing all their requirements, ex : + instantiating a interruption controller, before knowing how many interrupt signal lines you need - Abstract/lazy/partial SoC architecture definition allowing the creation of SoC template for further specialisations -- Automatic requirements negotiation between multiple agents in a decentralized way, ex : between masters and slaves of a memory bus +- Automatic requirement negotiation between multiple agents in a decentralized way, ex : between masters and slaves of a memory bus The framework is mainly composed of : -- Handle[T], which can be used later to store a value of type T. -- handle.load which allow to set the value of a handle (will reschedule all tasks waiting on it) -- handle.get, which return the value of the given handle. Will block the task execution if that handle isn't loaded yet -- Handle{ code }, which fork a new task which will execute the given code. The result of that code will be loaded into the Handle -- soon(handle), which allow the current task to announce that soon it will load that handle with a value (used to track which handle will - +- ``Handle[T]``, which can be used later to store a value of type ``T``. +- ``handle.load`` which allow to set the value of a handle (will reschedule all tasks waiting on it) +- ``handle.get``, which return the value of the given handle. Will block the task execution if that handle isn't loaded yet +- ``Handle{ /*code*/ }``, which fork a new task which will execute the given code. The result of that code will be loaded into the Handle +- ``soon(handle)``, which allows the current task to announce that it will load ``handle`` with a value (used for scheduling) -Warning, this is realy not usual RTL description and aim large system generation. It is currently used as toplevel integration tool in SaxonSoC. Simple dummy example -------------------- diff --git a/master/_sources/SpinalHDL/Libraries/fsm.rst.txt b/master/_sources/SpinalHDL/Libraries/fsm.rst.txt index 1c43af18dd4..be70d6ec9a8 100644 --- a/master/_sources/SpinalHDL/Libraries/fsm.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/fsm.rst.txt @@ -29,7 +29,7 @@ Style A: } val fsm = new StateMachine { - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) io.result := False val stateA : State = new State with EntryPoint { @@ -62,12 +62,12 @@ Style B: val result = out Bool() } - val fsm = new StateMachine{ + val fsm = new StateMachine { val stateA = new State with EntryPoint val stateB = new State val stateC = new State - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) io.result := False stateA @@ -235,7 +235,7 @@ Each of them provides the following functions to define the logic associated to StateDelay ^^^^^^^^^^ -``StateDelay`` allows to create a state which waits for a fixed number of cycles before executing statments in ``whenCompleted {...}``. The preferred way to use it is: +``StateDelay`` allows you to create a state which waits for a fixed number of cycles before executing statements in ``whenCompleted {...}``. The preferred way to use it is: .. code-block:: scala @@ -254,7 +254,7 @@ It can also be written in one line: StateFsm ^^^^^^^^ -``StateFsm`` allow to describe a state containing a nested state machine. When the nested state machine is done (exited), statments in ``whenCompleted { ... }`` are executed. +``StateFsm`` allows you to describe a state containing a nested state machine. When the nested state machine is done (exited), statements in ``whenCompleted { ... }`` are executed. There is an example of StateFsm definition : @@ -268,7 +268,7 @@ There is an example of StateFsm definition : } def internalFsm() = new StateMachine { - val counter = Reg(UInt(8 bits)) init (0) + val counter = Reg(UInt(8 bits)) init(0) val stateA : State = new State with EntryPoint { whenIsActive { @@ -292,14 +292,14 @@ In the example above, ``exit()`` makes the state machine jump to the boot state StateParallelFsm ^^^^^^^^^^^^^^^^ -``StateParallelFsm`` allows to handle multiple nested state machines. When all nested state machine are done, statments in ``whenCompleted { ... }`` are executed. +``StateParallelFsm`` allows you to handle multiple nested state machines. When all nested state machine are done, statements in ``whenCompleted { ... }`` are executed. Example: .. code-block:: scala val stateD = new StateParallelFsm (internalFsmA(), internalFsmB()) { - whenCompleted{ + whenCompleted { goto(stateE) } } diff --git a/master/_sources/SpinalHDL/Libraries/regIf.rst.txt b/master/_sources/SpinalHDL/Libraries/regIf.rst.txt index 50c8669b964..9fff129d406 100644 --- a/master/_sources/SpinalHDL/Libraries/regIf.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/regIf.rst.txt @@ -5,7 +5,7 @@ RegIf Register Interface Builder - Automatic address, fields allocation and conflict detection -- 28 Register Access types(Covering the 25 types defined by the UVM standard) +- 28 Register Access types (Covering the 25 types defined by the UVM standard) - Automatic documentation generation Automatic allocation @@ -15,8 +15,8 @@ Automatic address allocation .. code:: scala - class RegBankExample extends Component{ - val io = new Bundle{ + class RegBankExample extends Component { + val io = new Bundle { apb = Apb3(Apb3Config(16,32)) } val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte) @@ -51,7 +51,7 @@ Automatic fileds allocation .. image:: /asset/image/regif/field-auto-allocate.gif -confilict detection +conflict detection .. code:: scala @@ -145,7 +145,7 @@ Attention, please don't forget to drive it. .. code:: scala - val io = new Bundle{ + val io = new Bundle { val cnt = in UInt(8 bit) } @@ -238,7 +238,7 @@ CSTM is only used to generate software interfaces, and does not generate actual val reg = Reg(Bits(16 bit)) init 0 REG.registerAtOnlyReadLogic(0, reg, CSTM("BMRW"), resetValue = 0, "custom field") - when(busif.dowrite){ + when(busif.dowrite) { reg := reg & ~busif.writeData(31 downto 16) | busif.writeData(15 downto 0) & busif.writeData(31 downto 16) } @@ -278,7 +278,7 @@ withStrb Typical Example =============== -Batch creat REG-Address and fields register +Batch create REG-Address and fields register .. code:: scala @@ -292,7 +292,7 @@ Batch creat REG-Address and fields register } val busif = Apb3BusInterface(io.apb, (0x000, 100 Byte), regPre = "AP") - (0 to 9).map{ i => + (0 to 9).map { i => //here use setName give REG uniq name for Docs usage val REG = busif.newReg(doc = s"Register${i}").setName(s"REG${i}") val real = REG.field(SInt(8 bit), AccessType.RW, 0, "Complex real") @@ -365,14 +365,14 @@ Manual writing interruption this is a very tedious and repetitive work, a better way is to use the "factory" paradigm to auto-generate the documentation for each signal. -now th InterruptFactory can do that. +now the InterruptFactory can do that. -Easy Way creat interruption: +Easy Way create interruption: .. code:: scala class EasyInterrupt extends Component { - val io = new Bundle{ + val io = new Bundle { val apb = slave(Apb3(Apb3Config(16,32))) val a, b, c, d, e = in Bool() } @@ -432,24 +432,24 @@ SpinalUsage: Spinal Factory -------------- -=================================================================================== =========================================================== +=================================================================================== ============================================================ BusInterface method Description -=================================================================================== =========================================================== -``InterruptFactory(regNamePre: String, triggers: Bool*)`` creat RAW/FORCE/MASK/STATUS for pulse event -``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)`` creat RAW/MASK/STATUS for pulse event -``InterruptFactory(regNamePre: String, triggers: Bool*)`` creat MASK/STATUS for level_int merge -``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` creat RAW/FORCE/MASK/STATUS for pulse event at addrOffset -``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` creat RAW/MASK/STATUS for pulse event at addrOffset -``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` creat MASK/STATUS for level_int merge at addrOffset -=================================================================================== =========================================================== +=================================================================================== ============================================================ +``InterruptFactory(regNamePre: String, triggers: Bool*)`` create RAW/FORCE/MASK/STATUS for pulse event +``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)`` create RAW/MASK/STATUS for pulse event +``InterruptFactory(regNamePre: String, triggers: Bool*)`` create MASK/STATUS for level_int merge +``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` create RAW/FORCE/MASK/STATUS for pulse event at addrOffset +``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` create RAW/MASK/STATUS for pulse event at addrOffset +``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)`` create MASK/STATUS for level_int merge at addrOffset +=================================================================================== ============================================================ Example ------- .. code:: scala - class RegFileIntrExample extends Component{ - val io = new Bundle{ + class RegFileIntrExample extends Component { + val io = new Bundle { val apb = slave(Apb3(Apb3Config(16,32))) val int_pulse0, int_pulse1, int_pulse2, int_pulse3 = in Bool() val int_level0, int_level1, int_level2 = in Bool() @@ -508,7 +508,7 @@ BusIfVistor give access BusIf.RegInsts to do what you want // lib/src/main/scala/lib/bus/regif/BusIfVistor.scala - trait BusIfVisitor { + trait BusIfVisitor { def begin(busDataWidth : Int) : Unit def visit(descr : FifoDescr) : Unit def visit(descr : RegDescr) : Unit diff --git a/master/_sources/SpinalHDL/Libraries/stream.rst.txt b/master/_sources/SpinalHDL/Libraries/stream.rst.txt index 4ddefecd608..10317bdaa4d 100644 --- a/master/_sources/SpinalHDL/Libraries/stream.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/stream.rst.txt @@ -176,7 +176,7 @@ The following code will create this logic : .. code-block:: scala - case class RGB(channelWidth : Int) extends Bundle{ + case class RGB(channelWidth : Int) extends Bundle { val red = UInt(channelWidth bits) val green = UInt(channelWidth bits) val blue = UInt(channelWidth bits) @@ -459,7 +459,7 @@ When you have multiple Streams and you want to arbitrate them to drive a single StreamJoin ^^^^^^^^^^ -This utile takes multiple input streams and wait until all of them fire before letting all of them through. +This utility takes multiple input streams and waits until all of them fire `valid` before letting all of them through by providing `ready`. .. code-block:: scala diff --git a/master/_sources/SpinalHDL/Libraries/utils.rst.txt b/master/_sources/SpinalHDL/Libraries/utils.rst.txt index 189c159e1e9..f89c60754f9 100644 --- a/master/_sources/SpinalHDL/Libraries/utils.rst.txt +++ b/master/_sources/SpinalHDL/Libraries/utils.rst.txt @@ -163,7 +163,7 @@ There is an example of different syntaxes which could be used with the Counter t .. code-block:: scala val timeout = Timeout(10 ms) //Timeout who tick after 10 ms - when(timeout){ //Check if the timeout has tick + when(timeout) { //Check if the timeout has tick timeout.clear() //Ask the timeout to clear its flag } @@ -178,7 +178,7 @@ The ResetCtrl provide some utilities to manage resets. asyncAssertSyncDeassert ~~~~~~~~~~~~~~~~~~~~~~~ -You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the filtred value. +You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the filtered value. .. list-table:: :header-rows: 1 @@ -204,7 +204,7 @@ You can filter an asynchronous reset by using an asynchronously asserted synchro - Number of register stages used to avoid metastability (default=2) -There is also an ``ResetCtrl.asyncAssertSyncDeassertDrive`` version of tool which directly assign the ``clockDomain`` reset with the filtred value. +There is also an ``ResetCtrl.asyncAssertSyncDeassertDrive`` version of tool which directly assign the ``clockDomain`` reset with the filtered value. Special utilities ----------------- @@ -218,6 +218,6 @@ Special utilities - Description * - LatencyAnalysis(paths : Node*) - Int - - | Return the shortest path,in therm of cycle, that travel through all nodes, + - | Return the shortest path, in terms of cycles, that travel through all nodes, | from the first one to the last one diff --git a/master/_sources/SpinalHDL/Other language features/scope_property.rst.txt b/master/_sources/SpinalHDL/Other language features/scope_property.rst.txt index 7c398819eb8..2059a5000dd 100644 --- a/master/_sources/SpinalHDL/Other language features/scope_property.rst.txt +++ b/master/_sources/SpinalHDL/Other language features/scope_property.rst.txt @@ -3,7 +3,7 @@ ScopeProperty ================== -A scope property is a thing which can store values localy to the current thread. Its API can be used to set/get that value, but also to apply modification to the value for a portion of the execution in a stack manner. +A scope property is a thing which can store values locally to the current thread. Its API can be used to set/get that value, but also to apply modification to the value for a portion of the execution in a stack manner. In other words it is a alternative to global variable, scala implicit, ThreadLocal. @@ -16,12 +16,12 @@ In other words it is a alternative to global variable, scala implicit, ThreadLoc object Xlen extends ScopeProperty[Int] - object ScopePropertyMiaou extends App{ + object ScopePropertyMiaou extends App { Xlen.set(1) println(Xlen.get) //1 - Xlen(2){ + Xlen(2) { println(Xlen.get) //2 - Xlen(3){ + Xlen(3) { println(Xlen.get) //3 Xlen.set(4) println(Xlen.get) //4 diff --git a/master/_sources/SpinalHDL/Other language features/stub.rst.txt b/master/_sources/SpinalHDL/Other language features/stub.rst.txt index 3d37c7d6bd9..688f24589aa 100644 --- a/master/_sources/SpinalHDL/Other language features/stub.rst.txt +++ b/master/_sources/SpinalHDL/Other language features/stub.rst.txt @@ -2,18 +2,18 @@ Stub ====== -You can emtpy an Component Hierarchy as stub: +You can empty an Component Hierarchy as stub: .. code-block:: scala - class SubSysModule extends Component{ - val io = new Bundle{ + class SubSysModule extends Component { + val io = new Bundle { val dx = slave(Stream(Bits(32 bits))) val dy = master(Stream(Bits(32 bits))) } io.dy <-< io.dx } - class TopLevle extends Component { + class TopLevel extends Component { val dut = new SubSysModule().stub //instance an SubSysModule as empty stub } @@ -40,17 +40,17 @@ It will generate the following Verilog code for example: endmodule -You can also emtpy the top Compoent +You can also empty the top Component .. code-block:: scala SpinalVerilog(new Pinsec(500 MHz).stub) -what `stub` do +What does `stub` do ? -* first walk all the component and find out clock ,then keep clock -* remove all children component -* reomove all assignment and logic we dont wan't +* first walk all the components and find out clock, then keep clock +* then remove all children component +* then remove all assignment and logic we dont want * tile 0 to output port diff --git a/master/_sources/SpinalHDL/Other language features/utils.rst.txt b/master/_sources/SpinalHDL/Other language features/utils.rst.txt index cf93bf53b8d..71e2f48646a 100644 --- a/master/_sources/SpinalHDL/Other language features/utils.rst.txt +++ b/master/_sources/SpinalHDL/Other language features/utils.rst.txt @@ -72,7 +72,7 @@ For example: .. code-block:: scala def plusOne(value : UInt) : UInt = { - // Will recreate a UInt with the same width than ``value`` + // Will provide new instance of a UInt with the same width as ``value`` val temp = cloneOf(value) temp := value + 1 return temp @@ -86,6 +86,20 @@ You can get more information about how hardware data types are managed on the :r .. note:: If you use the ``cloneOf`` function on a ``Bundle``, this ``Bundle`` should be a ``case class`` or should override the clone function internally. +.. code-block:: scala + + // An example of a regular 'class' with 'override def clone()' function + class MyBundle(ppp : Int) extends Bundle { + val a = UInt(ppp bits) + override def clone = new MyBundle(ppp) + } + val x = new MyBundle(3) + val typeDef = HardType(new MyBundle(3)) + val y = typeDef() + + cloneOf(x) // Need clone method, else it errors + cloneOf(y) // Is ok + Passing a datatype as construction parameter -------------------------------------------- @@ -153,12 +167,12 @@ SpinalHDL has a dedicated syntax to define frequency and time values: .. code-block:: scala - val frequency = 100 MHz - val timeoutLimit = 3 ms - val period = 100 us + val frequency = 100 MHz // infers type TimeNumber + val timeoutLimit = 3 ms // infers type HertzNumber + val period = 100 us // infers type TimeNumber - val periodCycles = frequency * period - val timeoutCycles = frequency * timeoutLimit + val periodCycles = frequency * period // infers type BigDecimal + val timeoutCycles = frequency * timeoutLimit // infers type BigDecimal | For time definitions you can use following postfixes to get a ``TimeNumber``: | ``fs``, ``ps``, ``ns``, ``us``, ``ms``, ``sec``, ``mn``, ``hr`` @@ -175,8 +189,8 @@ SpinalHDL allows the definition of integer numbers using binary prefix notation .. code-block:: scala - val memSize = 512 MiB - val dpRamSize = 4 KiB + val memSize = 512 MiB // infers type BigInt + val dpRamSize = 4 KiB // infers type BigInt The following binary prefix notations are available: diff --git a/master/_sources/SpinalHDL/Simulation/bootstraps.rst.txt b/master/_sources/SpinalHDL/Simulation/bootstraps.rst.txt index 58ff13cc976..212fb5aad51 100644 --- a/master/_sources/SpinalHDL/Simulation/bootstraps.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/bootstraps.rst.txt @@ -156,7 +156,9 @@ Note is it equivalent to: simThread.suspend() // Avoid the "doSim" completion } -Note that by default, the simulation files will be placed into the ``simWorkspace/xxx`` folders. You can override the simWorkspace location by setting the ``SPINALSIM_WORKSPACE`` environnement variable. +.. _env_SPINALSIM_WORKSPACE: + +Note that by default, the simulation files will be placed into the ``simWorkspace/xxx`` folders. You can override the simWorkspace location by setting the ``SPINALSIM_WORKSPACE`` environment variable. Running multiple tests on the same hardware ------------------------------------------- diff --git a/master/_sources/SpinalHDL/Simulation/clock.rst.txt b/master/_sources/SpinalHDL/Simulation/clock.rst.txt index 70ac36d3f2a..ab594d0bda4 100644 --- a/master/_sources/SpinalHDL/Simulation/clock.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/clock.rst.txt @@ -13,7 +13,7 @@ Below is a list of ``ClockDomain`` stimulation functions: * - ClockDomain stimulus functions - Description * - ``forkStimulus(period)`` - - Fork a simulation process to generate the clockdomain stimulus (clock, reset, softReset, clockEnable signals) + - Fork a simulation process to generate the ClockDomain stimulus (clock, reset, softReset, clockEnable signals) * - ``forkSimSpeedPrinter(printPeriod)`` - Fork a simulation process which will periodically print the simulation speed in kilo-cycles per real time second. ``printPeriod`` is in realtime seconds * - ``clockToggle()`` @@ -67,7 +67,7 @@ Below is a list of ``ClockDomain`` utilities that you can use to wait for a give .. warning:: - All the functionalities of the wait API can only be called from inside of a thread, and not from a callback. + All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API. .. _sim_clock_threadless: diff --git a/master/_sources/SpinalHDL/Simulation/index.rst.txt b/master/_sources/SpinalHDL/Simulation/index.rst.txt index c0ba93e787e..3c9ef8e987a 100644 --- a/master/_sources/SpinalHDL/Simulation/index.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/index.rst.txt @@ -6,10 +6,11 @@ As always, you can use your standard simulation tools to simulate the VHDL/Veril To be able to simulate user-defined components, SpinalHDL uses external HDL simulators as backend. Currently, four simulators are supported: -- `Verilator `_ +- `Verilator `_ - `GHDL `_ **(experimental, since SpinalHDL 1.4.1)** -- `Icarus Verilog `_ **(experimental, since SpinalHDL 1.4.1)** +- `Icarus Verilog `_ **(experimental, since SpinalHDL 1.4.1)** - `VCS `_ **(experimental, since SpinalHDL 1.7.0)** +- `XSim `_ **(experimental, since SpinalHDL 1.7.0)** With external HDL simulators it is possible to directly test the generated HDL sources without increasing the SpinalHDL codebase complexity. diff --git a/master/_sources/SpinalHDL/Simulation/install/Verilator.rst.txt b/master/_sources/SpinalHDL/Simulation/install/Verilator.rst.txt index 329fa324a26..393a205d7e9 100644 --- a/master/_sources/SpinalHDL/Simulation/install/Verilator.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/install/Verilator.rst.txt @@ -5,6 +5,14 @@ Setup and installation of Verilator SpinalSim + Verilator is supported on both Linux and Windows platforms. +It is recommended that v4.218 is the oldest Verilator version to use. While it maybe +possible to use older verilator versions, some optional and Scala source dependent +features that SpinalHDL can use (such as Verilog ``$urandom`` support) may not be supported +by older Verilator versions and will cause an error when trying to simulate. + +Ideally the latest v4.xxx and v5.xxx is well supported and bug reports should be opened +with any issues you have. + Scala ^^^^^ @@ -33,9 +41,9 @@ You will also need a recent version of Verilator installed : unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator - git pull # Make sure we're up-to-date - git checkout v4.218 - autoconf # Create ./configure script + git pull # Make sure we're up-to-date + git checkout v4.218 # Can use newer v4.228 and v5.xxx + autoconf # Create ./configure script ./configure make -j$(nproc) sudo make install @@ -87,7 +95,7 @@ From source unset VERILATOR_ROOT cd verilator git pull - git checkout v4.040 + git checkout v4.218 # Can use newer v4.228 and v5.xxx autoconf ./configure export CPLUS_INCLUDE_PATH=/usr/include:$CPLUS_INCLUDE_PATH diff --git a/master/_sources/SpinalHDL/Simulation/signal.rst.txt b/master/_sources/SpinalHDL/Simulation/signal.rst.txt index 375e74d6c01..cb5e359451f 100644 --- a/master/_sources/SpinalHDL/Simulation/signal.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/signal.rst.txt @@ -88,7 +88,7 @@ Or you can add it later, after having instantiated your toplevel for the simulat def main(args: Array[String]) { SimConfig.compile { val dut = new TopLevel - dut.counter.simPublic() + dut.counter.simPublic() // Call simPublic() here dut }.doSim{dut => dut.clockDomain.forkStimulus(10) diff --git a/master/_sources/SpinalHDL/Simulation/simulator_specifics.rst.txt b/master/_sources/SpinalHDL/Simulation/simulator_specifics.rst.txt index d33ce4daf86..56b9a9f7431 100644 --- a/master/_sources/SpinalHDL/Simulation/simulator_specifics.rst.txt +++ b/master/_sources/SpinalHDL/Simulation/simulator_specifics.rst.txt @@ -6,7 +6,7 @@ How SpinalHDL simulates the hardware with Verilator backend =========================================================== 1. Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model of the DUT and then uses Verilator to convert it to a C++ cycle-accurate model. -2. The C++ model is compiled into a shared object (.so), which is bound to Scala via JNR-FFI. +2. The C++ model is compiled into a shared object (.so), which is bound to Scala via JNI-FFI. 3. The native Verilator API is abstracted by providing a simulation multi-threaded API. **Advantages:** @@ -17,7 +17,7 @@ How SpinalHDL simulates the hardware with Verilator backend * Verilator accepts only synthesizable Verilog/System Verilog code. Therefore special care has to be taken when simulating Verilog blackbox components that may have non-synthesizable statements. * VHDL blackboxes cannot be simulated. -* The simulation boot process is slow due to the necessity to compile and link the generated C++ model +* The simulation boot process is slow due to the necessity to compile and link the generated C++ model. Some support to incrementally compile and link exists which can provide speedups for subsequent simulations after building the first. How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend ===================================================================== diff --git a/master/_sources/SpinalHDL/Structuring/parametrization.rst.txt b/master/_sources/SpinalHDL/Structuring/parametrization.rst.txt index b6a64b3bd88..6e209b4c7b3 100644 --- a/master/_sources/SpinalHDL/Structuring/parametrization.rst.txt +++ b/master/_sources/SpinalHDL/Structuring/parametrization.rst.txt @@ -84,7 +84,7 @@ Here is an example of class parameters You can also use global variable defined in Scala objects (companion object pattern). -A ``ScopeProperty`` can also be used for configuration. +A :ref:`ScopeProperty ` can also be used for configuration. Optional hardware ------------------------------------------ diff --git a/master/artefacts/SpinalHDL_docs-master-SingleHTML.zip b/master/artefacts/SpinalHDL_docs-master-SingleHTML.zip index 10515cab725..5ff733680ba 100644 Binary files a/master/artefacts/SpinalHDL_docs-master-SingleHTML.zip and b/master/artefacts/SpinalHDL_docs-master-SingleHTML.zip differ diff --git a/master/artefacts/SpinalHDL_docs-master.pdf b/master/artefacts/SpinalHDL_docs-master.pdf index b84b0db152f..509d9a58f62 100644 Binary files a/master/artefacts/SpinalHDL_docs-master.pdf and b/master/artefacts/SpinalHDL_docs-master.pdf differ diff --git a/master/genindex.html b/master/genindex.html index 23f2c61c553..9f5fe6919dd 100644 --- a/master/genindex.html +++ b/master/genindex.html @@ -970,7 +970,6 @@ -
  • Introduction
  • Getting started
  • @@ -1174,7 +1173,7 @@

    Index

    diff --git a/master/index.html b/master/index.html index ebe992056bb..9213d77a2fe 100644 --- a/master/index.html +++ b/master/index.html @@ -972,7 +972,6 @@ -
  • Introduction
  • Getting started
  • @@ -1238,7 +1237,7 @@

    Spinal Hardware Description Language

    - Version: master git~b2d9e2199 2023-08-27 + Version: master git~10051d6e2 2023-09-15

    diff --git a/master/objects.inv b/master/objects.inv index d2404196358..e17603427eb 100644 Binary files a/master/objects.inv and b/master/objects.inv differ diff --git a/master/search.html b/master/search.html index 9c5baa0d633..39c056411f3 100644 --- a/master/search.html +++ b/master/search.html @@ -973,7 +973,6 @@ -
  • Introduction
  • Getting started
  • @@ -1181,7 +1180,7 @@ diff --git a/master/searchindex.js b/master/searchindex.js index 51cd44cc08f..4286a3d6b76 100644 --- a/master/searchindex.js +++ b/master/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["SpinalHDL/Data types/AFix", "SpinalHDL/Data types/Fix", "SpinalHDL/Data types/Floating", "SpinalHDL/Data types/Int", "SpinalHDL/Data types/Vec", "SpinalHDL/Data types/bits", "SpinalHDL/Data types/bool", "SpinalHDL/Data types/bundle", "SpinalHDL/Data types/enum", "SpinalHDL/Data types/index", "SpinalHDL/Design errors/assignment_overlap", "SpinalHDL/Design errors/clock_crossing_violation", "SpinalHDL/Design errors/combinatorial_loop", "SpinalHDL/Design errors/hierarchy_violation", "SpinalHDL/Design errors/index", "SpinalHDL/Design errors/iobundle", "SpinalHDL/Design errors/latch_detected", "SpinalHDL/Design errors/no_driver_on", "SpinalHDL/Design errors/nullpointerexception", "SpinalHDL/Design errors/out_of_range_constant", "SpinalHDL/Design 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"SpinalHDL/Getting Started/Scala Guide/coding_conventions", "SpinalHDL/Getting Started/Scala Guide/index", "SpinalHDL/Getting Started/Scala Guide/interaction", "SpinalHDL/Getting Started/VSCodium", "SpinalHDL/Getting Started/index", "SpinalHDL/Introduction/A simple example", "SpinalHDL/Introduction/Contributing", "SpinalHDL/Introduction/Getting in touch", "SpinalHDL/Introduction/License", "SpinalHDL/Introduction/Other learning materials", "SpinalHDL/Introduction/Projects using SpinalHDL", "SpinalHDL/Introduction/SpinalHDL", "SpinalHDL/Introduction/faq", "SpinalHDL/Introduction/index", "SpinalHDL/Legacy/index", "SpinalHDL/Legacy/pinsec/hardware", "SpinalHDL/Legacy/pinsec/hardware_toplevel", "SpinalHDL/Legacy/pinsec/index", "SpinalHDL/Legacy/pinsec/introduction", "SpinalHDL/Legacy/pinsec/software", "SpinalHDL/Legacy/riscv", "SpinalHDL/Libraries/Bus/amba3/ahblite3", "SpinalHDL/Libraries/Bus/amba3/apb3", "SpinalHDL/Libraries/Bus/amba4/axi4", "SpinalHDL/Libraries/Bus/avalon/avalonmm", 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155, 156, 157, 163], "val": [0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 63, 64, 66, 69, 76, 80, 85, 86, 87, 88, 91, 92, 93, 94, 95, 97, 99, 101, 102, 107, 108, 110, 112, 113, 114, 116, 117, 119, 121, 122, 123, 124, 126, 127, 129, 130, 131, 134, 135, 137, 138, 140, 144, 148, 150, 152, 153, 154, 155, 156, 158, 159, 161, 163], "maxvalu": [0, 1, 3], "bigint": [0, 1, 3, 5, 26, 37, 110, 112, 114, 122, 148, 155, 161], "minvalu": [0, 1, 3], "expnumb": [0, 1], "new": [0, 3, 4, 5, 6, 7, 11, 13, 15, 20, 22, 26, 28, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, 51, 52, 58, 59, 60, 62, 63, 64, 66, 69, 75, 79, 80, 87, 92, 93, 95, 96, 99, 101, 102, 107, 108, 110, 112, 113, 116, 121, 122, 123, 126, 127, 129, 130, 131, 134, 135, 137, 138, 148, 150, 152, 153, 154, 155, 156, 158, 159, 161, 163], "2": [0, 1, 3, 4, 5, 8, 9, 14, 19, 24, 27, 31, 37, 40, 41, 49, 52, 58, 59, 62, 63, 64, 76, 80, 85, 92, 93, 105, 107, 112, 113, 114, 120, 122, 124, 126, 127, 129, 139, 145, 148, 149, 154, 155, 158, 161], "16": [0, 1, 3, 4, 5, 27, 30, 31, 36, 37, 40, 41, 42, 48, 63, 76, 80, 92, 93, 105, 112, 113, 116, 122, 129, 148, 153, 154, 158], "The": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 33, 34, 37, 38, 40, 41, 42, 43, 46, 50, 51, 52, 58, 62, 63, 64, 65, 66, 69, 76, 79, 80, 82, 85, 86, 87, 88, 91, 92, 93, 94, 95, 101, 102, 103, 106, 107, 108, 109, 110, 111, 113, 114, 118, 123, 124, 126, 129, 130, 131, 133, 134, 135, 137, 138, 142, 143, 144, 149, 151, 153, 154, 155, 156, 157, 158, 159, 162, 163], "store": [0, 8, 26, 30, 31, 33, 36, 40, 66, 88, 92, 107, 113, 120, 122, 158], "what": [0, 3, 27, 33, 58, 59, 112, 121, 126, 129, 158, 159], "back": [0, 69, 76, 112, 131, 144, 158], "integ": [0, 1, 3, 4, 5, 9, 31, 58, 63, 69, 113, 122, 129, 134, 138], "ar": [0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15, 16, 17, 20, 21, 24, 26, 30, 31, 33, 36, 37, 38, 40, 41, 50, 52, 58, 59, 60, 62, 63, 64, 66, 69, 71, 72, 73, 75, 76, 79, 80, 82, 84, 87, 91, 92, 94, 95, 102, 103, 105, 107, 108, 109, 110, 111, 112, 113, 114, 115, 117, 122, 123, 124, 126, 127, 129, 130, 131, 133, 141, 148, 149, 151, 152, 153, 154, 155, 156, 157, 158, 159, 161, 163, 165], "repres": [0, 1, 41, 42, 49, 51, 66, 69, 108, 110, 113, 122, 161], "true": [0, 3, 5, 6, 16, 19, 26, 30, 31, 33, 36, 37, 38, 40, 41, 42, 48, 51, 52, 58, 59, 63, 66, 69, 80, 87, 88, 92, 93, 102, 108, 109, 110, 113, 114, 116, 122, 123, 126, 127, 129, 130, 132, 135, 137, 139, 140, 145, 146, 147, 154, 158, 159, 161], "after": [0, 5, 30, 36, 60, 69, 92, 107, 110, 112, 113, 114, 122, 130, 131, 133, 142, 148, 151, 153], "multipli": [0, 122, 156, 161], "1": [0, 1, 2, 3, 4, 5, 6, 8, 11, 12, 14, 16, 24, 26, 27, 30, 31, 33, 36, 37, 38, 40, 41, 42, 45, 47, 48, 49, 51, 52, 58, 59, 60, 62, 63, 64, 66, 69, 76, 79, 80, 84, 86, 88, 92, 93, 95, 105, 108, 110, 112, 113, 114, 115, 116, 119, 120, 121, 122, 123, 124, 126, 127, 129, 130, 131, 132, 134, 135, 139, 140, 141, 145, 148, 149, 152, 154, 155, 158, 161, 162, 163], "5": [0, 1, 3, 4, 5, 6, 8, 9, 31, 33, 40, 49, 58, 59, 63, 66, 79, 80, 84, 92, 97, 112, 114, 115, 122, 126, 130, 132, 158], "75": 0, "25": [0, 1, 5, 112, 154], "greater": [0, 1, 3, 7, 31, 113], "allow": [0, 1, 3, 5, 6, 19, 20, 30, 33, 34, 36, 37, 40, 41, 51, 52, 58, 75, 79, 80, 92, 107, 110, 113, 115, 116, 120, 122, 129, 133, 134, 150, 151, 152, 153, 154, 156, 158, 159, 161], "larger": [0, 2, 19], "than": [0, 1, 3, 4, 5, 7, 19, 26, 29, 31, 33, 34, 36, 50, 59, 63, 64, 86, 88, 92, 102, 106, 112, 113, 122, 124, 129, 130, 132, 150, 152, 154, 156, 161, 162, 163], "32": [0, 3, 5, 31, 33, 34, 37, 42, 51, 58, 63, 80, 85, 86, 87, 92, 93, 101, 102, 105, 112, 116, 121, 122, 127, 129, 135, 137, 153, 155], "36": 0, "40": [0, 110, 122], "44": [0, 115], "48": [0, 41, 92, 93], "52": 0, "56": 0, "60": [0, 80, 122], "64": [0, 3, 5, 34, 51, 63, 80, 93, 105, 145, 155, 158], "note": [0, 9, 30, 31, 36, 40, 51, 52, 87, 92, 113, 114, 117, 119, 131, 132, 154, 158, 159], "save": [0, 7, 62, 76, 95], "type": [0, 11, 26, 27, 28, 34, 37, 38, 40, 42, 49, 51, 52, 57, 58, 62, 69, 75, 76, 85, 86, 87, 91, 92, 106, 107, 108, 109, 110, 113, 114, 116, 118, 122, 123, 124, 127, 129, 130, 140, 144, 154, 155, 157, 159, 161, 165], "its": [0, 7, 8, 21, 31, 33, 40, 51, 52, 58, 59, 60, 61, 62, 63, 66, 69, 72, 75, 76, 80, 91, 92, 94, 107, 113, 114, 124, 126, 129, 130, 132, 153, 154, 155, 158, 161], "support": [0, 1, 2, 3, 4, 8, 9, 26, 31, 52, 58, 60, 62, 75, 76, 78, 79, 81, 92, 96, 114, 119, 124, 129, 141, 145, 149, 154, 155, 159], "addit": [0, 1, 3, 6, 7, 9, 13, 31, 33, 40, 44, 52, 58, 61, 64, 76, 80, 92, 102, 105, 113, 117, 125, 126, 130, 154, 159, 161], "subtract": [0, 1, 3, 31], "multipl": [0, 1, 3, 5, 6, 11, 30, 31, 36, 42, 67, 79, 82, 84, 92, 93, 103, 107, 109, 110, 112, 113, 120, 123, 124, 126, 127, 129, 130, 150, 158, 159, 161, 163], "hardwar": [0, 3, 4, 6, 8, 14, 15, 18, 21, 22, 26, 31, 33, 34, 36, 37, 42, 50, 52, 57, 60, 64, 69, 74, 75, 76, 78, 80, 81, 82, 92, 94, 97, 99, 106, 107, 111, 112, 114, 116, 117, 118, 126, 141, 144, 148, 152, 156, 157, 158, 161, 163], "level": [0, 30, 40, 48, 51, 66, 75, 76, 102, 103, 117, 132, 133, 153, 154, 156, 159, 161, 165], "divis": [0, 3, 84], "modulo": [0, 3], "provid": [0, 3, 4, 6, 9, 15, 26, 30, 31, 33, 38, 40, 41, 51, 52, 63, 64, 65, 75, 76, 80, 82, 88, 92, 93, 102, 106, 107, 110, 111, 113, 114, 127, 129, 141, 144, 149, 153, 154, 155, 158, 159, 161, 164], "recommend": [0, 3, 52, 62, 63, 102, 113, 131, 154, 155], "elabor": [0, 3, 6, 7, 30, 39, 51, 62, 107, 124, 126, 129, 144, 153, 155, 157, 158, 163], "regular": [0, 6, 34, 52, 66, 129, 151, 159], "int": [0, 1, 2, 3, 4, 5, 7, 22, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 49, 51, 52, 58, 59, 63, 64, 66, 85, 86, 87, 88, 91, 97, 99, 106, 107, 108, 112, 113, 114, 116, 120, 122, 127, 129, 130, 131, 144, 148, 153, 154, 155, 156, 158, 159, 161, 162], "number": [0, 1, 3, 4, 8, 9, 38, 40, 49, 59, 63, 76, 79, 91, 92, 97, 110, 114, 122, 131, 154, 161], "unsign": [0, 3, 4, 5, 9, 31, 51, 58, 59, 69, 116, 123, 129], "interoper": [0, 75, 80, 159, 161], "There": [0, 7, 11, 30, 31, 51, 52, 58, 72, 75, 79, 80, 83, 85, 86, 87, 91, 92, 93, 101, 102, 106, 107, 110, 113, 114, 122, 124, 129, 130, 133, 151, 153, 155, 158, 159, 161], "differ": [0, 2, 3, 4, 8, 11, 31, 33, 40, 41, 51, 52, 58, 59, 60, 63, 80, 85, 102, 112, 113, 114, 122, 130, 138, 153, 154, 156, 159, 161], "between": [0, 2, 3, 5, 6, 9, 31, 33, 34, 37, 41, 51, 52, 58, 63, 69, 75, 76, 80, 84, 107, 110, 113, 124, 130, 133, 138, 149, 154, 158, 161], "fraction": [0, 1, 129], "expans": 0, "15": [0, 3, 52, 80, 84, 92, 112], "b": [0, 3, 5, 6, 7, 11, 12, 22, 25, 30, 31, 33, 40, 41, 42, 43, 44, 48, 58, 59, 63, 64, 66, 76, 79, 87, 97, 107, 110, 112, 119, 123, 124, 126, 127, 130, 134, 138, 148, 153, 154, 155, 156, 158, 161, 162, 163], "c": [0, 3, 5, 6, 8, 12, 26, 30, 33, 38, 40, 41, 43, 59, 63, 64, 76, 83, 92, 97, 112, 119, 123, 124, 126, 127, 133, 134, 138, 140, 142, 143, 144, 145, 149, 153, 154, 158, 161], "77": 0, "19": [0, 92], "7": [0, 2, 3, 5, 7, 8, 31, 33, 34, 40, 58, 59, 62, 63, 66, 76, 80, 112, 122, 126, 131, 139, 140, 141, 153, 154, 155, 158, 161], "d": [0, 3, 5, 6, 7, 12, 26, 30, 31, 60, 62, 80, 83, 112, 119, 123, 124, 154, 158], "00": [0, 9, 31], "e": [0, 3, 5, 6, 8, 16, 26, 30, 40, 74, 112, 124, 131], "308": 0, "3125": 0, "616": 0, "38": 0, "50": [0, 80, 122, 154], "11": [0, 1, 3, 62], "without": [0, 3, 5, 28, 31, 33, 38, 40, 51, 60, 62, 63, 84, 109, 113, 118, 127, 130, 135, 141, 145, 153, 154, 158, 159, 161, 162], "aa": 0, "bb": [0, 153], "cc": [0, 92], "9": [0, 3, 24, 36, 92, 112, 114, 115, 123, 124], "31": [0, 3, 5, 30, 34, 58, 92, 97, 112, 116, 121, 123], "It": [0, 2, 6, 7, 11, 12, 29, 31, 33, 34, 38, 40, 41, 51, 58, 59, 60, 62, 63, 64, 66, 67, 69, 75, 80, 87, 88, 92, 93, 94, 99, 102, 103, 107, 108, 109, 110, 112, 113, 116, 118, 119, 120, 121, 122, 124, 126, 127, 129, 130, 131, 149, 152, 153, 154, 158, 161, 165], "doe": [0, 4, 5, 6, 40, 41, 58, 75, 82, 84, 92, 112, 113, 127, 130, 134, 137, 138, 153, 159], "select": [0, 3, 5, 33, 36, 61, 113, 123, 125, 129], "align": [0, 3, 26, 92, 105], "maximum": [0, 1, 3, 5, 40, 95, 149], "minimum": [0, 1, 3, 5, 26, 52], "from": [0, 3, 5, 6, 7, 8, 11, 13, 14, 16, 26, 27, 30, 31, 34, 37, 40, 41, 42, 47, 52, 58, 60, 63, 64, 68, 69, 75, 76, 79, 80, 88, 94, 106, 108, 109, 110, 112, 113, 114, 115, 116, 122, 124, 126, 127, 129, 130, 132, 135, 137, 142, 143, 146, 148, 152, 154, 155, 156, 157, 159, 161, 163, 165], "each": [0, 6, 7, 8, 14, 15, 26, 30, 31, 33, 36, 37, 40, 41, 45, 48, 51, 52, 58, 59, 62, 63, 66, 67, 69, 78, 81, 85, 86, 87, 92, 97, 99, 102, 106, 109, 110, 112, 113, 115, 122, 126, 130, 131, 132, 133, 144, 147, 148, 153, 154, 155, 158, 161, 162], "input": [0, 3, 5, 6, 7, 13, 14, 30, 31, 33, 34, 37, 40, 41, 43, 44, 45, 47, 48, 51, 52, 59, 69, 79, 80, 93, 96, 108, 113, 114, 121, 122, 123, 126, 127, 130, 131, 132, 134, 135, 137, 138, 153, 154, 156, 157, 158, 161], "add": [0, 6, 9, 16, 26, 27, 30, 31, 33, 35, 37, 40, 41, 51, 58, 60, 62, 76, 80, 94, 108, 109, 112, 113, 116, 117, 118, 119, 122, 123, 127, 129, 144, 145, 148, 154, 155, 157, 161], "standard": [0, 2, 31, 75, 79, 112, 116, 123, 124, 128, 130, 132, 141, 159, 161], "A": [0, 1, 2, 3, 4, 6, 7, 10, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 33, 37, 60, 61, 62, 64, 67, 73, 74, 77, 79, 82, 92, 95, 102, 109, 110, 113, 114, 120, 122, 123, 127, 133, 153, 154, 158, 159, 161], "out": [0, 8, 13, 14, 15, 17, 23, 30, 31, 33, 36, 37, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 69, 76, 79, 85, 91, 92, 99, 101, 102, 107, 108, 110, 112, 113, 116, 119, 121, 122, 123, 124, 129, 130, 131, 134, 138, 153, 154, 155, 156, 158, 161, 163, 164], "compil": [0, 11, 14, 28, 34, 52, 58, 62, 63, 72, 76, 83, 95, 108, 113, 118, 126, 131, 134, 135, 137, 138, 142, 144, 145, 148, 149, 153, 154, 158, 161, 163], "time": [0, 3, 6, 8, 10, 27, 30, 31, 36, 39, 40, 43, 51, 58, 62, 66, 67, 69, 76, 79, 80, 85, 86, 87, 88, 95, 98, 105, 113, 114, 117, 126, 127, 130, 131, 132, 133, 134, 138, 145, 150, 151, 153, 154, 157, 158, 161, 163], "optim": [0, 38, 115, 131], "decim": [0, 2, 105], "shift": [0, 1, 2, 3, 5, 30, 31, 84, 114, 115, 122], "left": [0, 1, 3, 5, 6, 19, 25, 30, 31, 51, 124, 126, 127, 161, 165], "right": [0, 1, 3, 5, 6, 19, 25, 30, 31, 41, 51, 60, 61, 62, 66, 67, 75, 124, 161], "zero": [0, 3, 4, 5, 6, 31, 34, 37, 40, 59, 63, 76, 92, 113, 114, 124, 155], "remov": [0, 30, 36, 58, 79, 95, 113, 121, 127, 130, 153, 155], "implement": [0, 7, 28, 30, 31, 32, 33, 39, 41, 46, 49, 50, 51, 58, 61, 74, 75, 76, 79, 80, 82, 91, 92, 94, 106, 110, 113, 115, 116, 123, 126, 129, 149, 154, 158, 161], "common": [0, 3, 7, 63, 75, 105, 129, 141], "method": [0, 3, 7, 11, 58, 64, 79, 110, 112, 114, 124, 130, 144, 155, 158, 159], "work": [0, 3, 33, 58, 67, 76, 79, 93, 112, 113, 144, 145, 154, 161, 164], "an": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 16, 17, 19, 20, 22, 23, 26, 29, 30, 31, 33, 34, 36, 37, 40, 41, 42, 44, 47, 48, 49, 51, 52, 58, 59, 63, 64, 66, 68, 69, 75, 79, 80, 83, 84, 85, 86, 87, 88, 91, 94, 96, 97, 99, 101, 102, 106, 108, 109, 110, 112, 113, 114, 115, 116, 117, 121, 122, 124, 126, 127, 129, 130, 131, 132, 133, 135, 137, 141, 148, 149, 152, 154, 155, 156, 157, 158, 159, 161, 163, 165], "helper": [0, 159], "consid": [0, 31, 76, 84, 92, 111, 124, 131, 154, 164], "63": [0, 3, 5], "sat": [0, 3], "mode": [0, 3, 52, 62, 84, 88, 113, 115, 123, 129, 156], "follow": [0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 30, 31, 37, 40, 41, 42, 47, 50, 51, 52, 58, 60, 61, 63, 64, 65, 72, 79, 80, 82, 85, 86, 87, 93, 94, 97, 99, 101, 102, 103, 106, 109, 110, 111, 113, 115, 116, 117, 118, 119, 121, 122, 123, 126, 129, 130, 131, 133, 134, 138, 144, 145, 146, 153, 154, 155, 158, 159, 161, 162, 163], "requir": [0, 20, 21, 22, 26, 27, 31, 38, 40, 51, 61, 63, 76, 80, 92, 93, 94, 107, 112, 113, 124, 127, 129, 130, 142, 143, 144, 149, 154, 155, 159], "floor": [0, 3], "truncat": [0, 1, 2, 5, 31, 38], "ceil": [0, 3, 122], "floortozero": [0, 3], "ceiltoinf": [0, 3], "roundhalfup": [0, 3], "roundhalfdown": [0, 3], "roundhalftozero": [0, 3], "roundhalftoinf": [0, 3], "roundhalftoeven": [0, 3], "roundhalftoodd": [0, 3], "better": [0, 12, 16, 31, 51, 64, 72, 75, 82, 84, 88, 112, 149, 155, 164], "explain": [0, 31, 33, 51, 58, 63, 64, 69, 133, 157, 158], "here": [0, 2, 3, 9, 26, 30, 33, 34, 36, 37, 40, 41, 42, 47, 49, 50, 52, 58, 59, 60, 61, 66, 69, 76, 80, 82, 84, 88, 92, 94, 105, 112, 113, 122, 126, 129, 130, 131, 148, 154, 155, 158, 159, 161, 164], "wikipedia": [0, 1, 3], "result": [0, 1, 3, 4, 5, 7, 17, 18, 19, 23, 24, 25, 30, 31, 38, 43, 44, 47, 51, 58, 59, 66, 76, 107, 109, 110, 122, 124, 126, 129, 131, 134, 138, 149, 154, 155, 158, 159, 161], "If": [0, 1, 3, 5, 7, 8, 12, 13, 20, 26, 27, 30, 31, 40, 41, 52, 60, 63, 71, 72, 76, 92, 106, 113, 114, 116, 122, 123, 124, 126, 127, 129, 130, 132, 144, 153, 154, 155, 159, 161, 163], "tag": [0, 14, 96, 148, 153, 154, 161], "automat": [0, 3, 5, 16, 41, 51, 60, 62, 63, 95, 102, 107, 124, 128, 154, 158, 161], "check": [0, 4, 5, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 21, 23, 24, 25, 26, 30, 31, 52, 58, 61, 62, 67, 75, 76, 95, 110, 114, 117, 125, 126, 127, 129, 131, 133, 134, 135, 137, 138, 145, 149, 154, 155, 159, 161, 163], "expand": [0, 3, 5, 79], "precis": [0, 2], "dure": [0, 16, 30, 52, 60, 63, 66, 75, 110, 126, 127, 129, 131, 132, 153, 155, 158, 159], "By": [0, 26, 75, 110, 127, 154, 161], "default": [0, 3, 5, 6, 8, 16, 30, 31, 33, 38, 41, 52, 59, 60, 64, 69, 84, 85, 86, 87, 110, 112, 113, 114, 116, 123, 124, 127, 129, 131, 144, 153, 154, 161, 162], "error": [0, 1, 3, 5, 10, 13, 15, 16, 18, 19, 21, 22, 27, 41, 60, 62, 69, 75, 99, 112, 117, 124, 127, 129, 131, 144, 145, 154, 161, 165], "anoth": [0, 2, 16, 26, 31, 33, 51, 66, 67, 75, 106, 110, 113, 126, 127, 154, 155, 158, 161, 164], "smaller": [0, 3, 5, 51, 86, 92, 127], "control": [0, 34, 36, 39, 46, 60, 78, 81, 82, 84, 85, 91, 92, 93, 94, 98, 102, 103, 107, 108, 109, 113, 114, 126, 130, 144, 150, 151, 154, 159], "how": [0, 3, 4, 6, 9, 28, 31, 33, 36, 47, 51, 58, 60, 68, 75, 78, 85, 86, 87, 91, 92, 107, 109, 122, 123, 126, 129, 130, 132, 153, 157, 158, 159], "def": [0, 7, 22, 26, 30, 31, 33, 34, 37, 38, 40, 41, 42, 44, 48, 49, 50, 51, 58, 63, 64, 66, 76, 79, 80, 85, 87, 91, 94, 97, 99, 101, 102, 110, 112, 113, 116, 122, 123, 126, 129, 130, 134, 135, 137, 138, 148, 153, 154, 155, 156, 158, 161], "boolean": [0, 3, 5, 6, 31, 33, 40, 42, 51, 58, 63, 66, 86, 87, 88, 113, 122, 123, 129, 132, 148, 153, 154, 159, 161, 162], "fals": [0, 3, 5, 6, 14, 16, 19, 26, 30, 31, 36, 37, 38, 40, 41, 42, 43, 48, 51, 52, 58, 59, 63, 80, 86, 87, 88, 108, 110, 113, 117, 123, 126, 127, 130, 132, 135, 137, 139, 140, 152, 154, 158, 161], "overflow": [0, 3, 37, 58, 112, 114], "roundtyp": [0, 3], "roundup": [0, 3, 122], "rounddown": [0, 3], "roundtozero": [0, 3], "roundtoinf": [0, 3], "roundtoeven": [0, 3], "roundtoodd": [0, 3], "flag": [0, 69, 92, 114, 124, 146, 159], "logic": [0, 11, 27, 30, 31, 33, 34, 36, 37, 39, 40, 43, 47, 51, 52, 58, 75, 80, 103, 110, 113, 114, 115, 116, 117, 121, 127, 130, 134, 138, 152, 155, 156, 158, 161, 165], "datatyp": [0, 22, 26, 51, 58, 63, 64, 101, 102, 106, 113, 124, 130, 135, 137, 155], "alwai": [0, 3, 22, 27, 40, 51, 52, 64, 76, 92, 110, 112, 113, 114, 126, 129, 130, 141, 145, 150, 154, 156, 158, 161], "when": [0, 1, 3, 5, 6, 7, 8, 10, 11, 16, 18, 20, 21, 22, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 45, 48, 51, 52, 58, 59, 61, 62, 66, 69, 75, 80, 85, 86, 87, 92, 99, 101, 102, 106, 107, 108, 109, 110, 112, 113, 114, 115, 116, 117, 118, 123, 124, 125, 126, 129, 130, 131, 132, 133, 149, 152, 154, 155, 157, 163], "more": [0, 1, 7, 11, 26, 30, 36, 41, 51, 58, 60, 62, 63, 64, 69, 75, 76, 84, 88, 102, 106, 113, 115, 122, 123, 126, 130, 132, 142, 143, 152, 154, 155, 158, 159, 161, 165], "one": [0, 1, 2, 6, 8, 10, 11, 12, 13, 19, 23, 26, 30, 31, 33, 36, 37, 38, 40, 41, 48, 51, 52, 58, 60, 63, 66, 67, 69, 72, 75, 76, 80, 84, 86, 87, 91, 92, 93, 99, 106, 109, 110, 112, 113, 114, 118, 123, 124, 127, 130, 135, 145, 149, 154, 161, 162], "lower": [0, 4, 113, 149, 165], "spinalhdl": [1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 33, 34, 36, 37, 50, 51, 52, 53, 55, 56, 58, 59, 62, 63, 64, 65, 67, 68, 69, 71, 72, 73, 77, 79, 80, 82, 84, 85, 86, 87, 92, 93, 94, 102, 107, 110, 112, 113, 115, 118, 119, 122, 124, 126, 127, 129, 130, 141, 142, 144, 148, 152, 153, 154, 155, 157, 158, 159, 161, 163, 165], "onli": [1, 2, 3, 5, 6, 8, 11, 14, 15, 26, 27, 30, 31, 33, 36, 40, 51, 52, 58, 60, 63, 64, 69, 79, 80, 82, 84, 85, 87, 88, 92, 106, 109, 110, 112, 113, 114, 116, 122, 126, 127, 129, 130, 132, 145, 149, 153, 154, 155, 158, 161, 162, 163], "partial": [1, 2, 9, 12, 16, 51, 107, 155], "test": [1, 2, 28, 30, 39, 60, 66, 79, 92, 93, 95, 108, 113, 123, 134, 138, 141, 158], "you": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 19, 20, 22, 23, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 41, 47, 49, 50, 52, 58, 59, 60, 61, 62, 63, 64, 66, 67, 69, 71, 72, 75, 76, 79, 80, 83, 84, 85, 86, 87, 92, 94, 95, 97, 101, 102, 106, 107, 109, 110, 111, 112, 113, 114, 116, 117, 118, 119, 121, 122, 123, 126, 127, 129, 130, 131, 132, 141, 144, 145, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 158, 159, 161, 162, 163, 165], "find": [1, 3, 4, 7, 14, 30, 34, 50, 52, 67, 76, 80, 82, 84, 88, 95, 106, 121, 158, 165], "ani": [1, 2, 4, 5, 6, 7, 30, 31, 33, 41, 43, 59, 60, 75, 76, 92, 109, 113, 116, 123, 124, 131, 145, 159], "bug": [1, 2, 71, 76, 111], "think": [1, 2, 33, 51], "some": [1, 2, 3, 5, 12, 19, 21, 23, 26, 27, 30, 31, 33, 36, 37, 38, 40, 41, 43, 47, 51, 52, 58, 61, 63, 64, 66, 73, 76, 79, 80, 82, 87, 88, 92, 93, 94, 102, 103, 107, 110, 111, 112, 113, 114, 116, 117, 120, 122, 123, 126, 129, 130, 132, 133, 134, 138, 144, 145, 151, 152, 154, 155, 156, 158, 159, 161], "miss": [1, 2, 16, 103, 127, 161], "pleas": [1, 2, 84, 95, 112, 116, 123, 154, 159, 164], "github": [1, 2, 30, 36, 52, 53, 55, 56, 60, 76, 80, 83, 84, 92, 93, 103, 111, 115, 123, 129, 142, 165], "issu": [1, 2, 14, 36, 51, 58, 76, 107, 123, 129, 133, 149, 154, 161, 163], "also": [1, 2, 3, 5, 7, 8, 11, 12, 26, 29, 30, 31, 33, 34, 37, 41, 47, 49, 50, 51, 52, 58, 59, 60, 61, 62, 63, 66, 69, 76, 79, 80, 83, 87, 88, 92, 93, 105, 106, 107, 109, 110, 112, 113, 114, 118, 119, 120, 121, 122, 123, 124, 126, 129, 130, 132, 142, 143, 144, 145, 146, 154, 155, 156, 158, 159, 161, 165], "do": [1, 2, 3, 5, 6, 8, 10, 11, 14, 15, 22, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 47, 49, 51, 52, 58, 60, 61, 62, 63, 66, 67, 72, 76, 80, 86, 87, 92, 93, 105, 106, 107, 109, 110, 111, 112, 114, 116, 121, 122, 123, 124, 127, 129, 130, 131, 135, 144, 145, 153, 154, 155, 158, 159, 161, 162], "undocu": [1, 2], "featur": [1, 2, 6, 27, 31, 51, 58, 59, 60, 71, 73, 75, 76, 78, 79, 80, 82, 88, 94, 103, 107, 110, 111, 115, 116, 126, 129, 130, 144, 149, 154, 158, 159, 162, 165], "your": [1, 2, 3, 6, 7, 8, 11, 14, 22, 27, 30, 31, 33, 47, 49, 50, 51, 52, 58, 60, 61, 62, 63, 66, 67, 72, 75, 76, 79, 80, 94, 95, 106, 110, 111, 112, 113, 116, 118, 123, 124, 126, 129, 131, 132, 141, 142, 143, 144, 145, 146, 148, 149, 150, 152, 153, 154, 155, 158, 159, 163], "correspond": [1, 2, 6, 8, 18, 26, 31, 36, 37, 38, 47, 50, 52, 79, 80, 92, 106, 108, 113, 123, 129, 132, 142, 143, 153, 154, 155, 161, 163], "vector": [1, 3, 4, 5, 31, 44, 110, 114, 127, 128], "syntax": [1, 2, 3, 4, 5, 6, 7, 27, 28, 34, 37, 42, 51, 52, 58, 60, 63, 66, 69, 71, 75, 105, 108, 109, 110, 113, 114, 117, 118, 119, 122, 123, 124, 126, 127, 129, 130, 131, 148, 154, 155, 159, 162], "width": [1, 2, 3, 4, 5, 8, 14, 16, 22, 26, 30, 31, 37, 40, 41, 45, 63, 80, 85, 86, 87, 91, 93, 102, 105, 106, 109, 113, 122, 125, 127, 128, 155, 159, 161, 162], "resolut": [1, 38, 41], "max": [1, 3, 5, 30, 31, 40, 62], "min": [1, 3, 26], "peak": [1, 38], "bitcount": [1, 3, 5, 6, 26, 31, 40, 102, 114, 155, 161], "chosen": [1, 149], "usual": [1, 6, 7, 107, 130, 159], "wai": [1, 2, 3, 8, 14, 22, 30, 31, 33, 37, 40, 41, 49, 51, 52, 58, 60, 62, 63, 64, 67, 84, 106, 107, 110, 112, 113, 124, 127, 129, 130, 144, 150, 153, 156, 159, 161], "defin": [1, 2, 4, 7, 8, 9, 13, 14, 15, 16, 17, 21, 23, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 49, 51, 58, 59, 63, 64, 66, 69, 78, 81, 83, 85, 86, 87, 95, 101, 102, 103, 106, 107, 109, 110, 112, 116, 118, 122, 123, 124, 126, 127, 129, 130, 132, 141, 146, 152, 154, 155, 156, 157, 158, 159, 161, 162], "q": [1, 6, 7], "notat": [1, 122], "inform": [1, 7, 26, 31, 61, 65, 69, 75, 80, 84, 88, 94, 109, 112, 115, 117, 122, 143, 155, 159, 164], "found": [1, 2, 29, 30, 33, 41, 61, 67, 76, 164], "page": [1, 11, 26, 27, 30, 33, 47, 58, 64, 65, 82, 84, 102, 122, 133, 158, 163], "about": [1, 2, 3, 7, 11, 26, 27, 30, 33, 40, 41, 51, 58, 59, 65, 71, 76, 77, 83, 106, 107, 108, 118, 122, 126, 127, 129, 143, 159, 161, 163, 165], "q8": 1, "mean": [1, 3, 5, 13, 18, 30, 31, 36, 41, 59, 76, 80, 108, 113, 116, 126, 130, 147, 154, 158, 159, 161, 163], "where": [1, 3, 4, 5, 6, 14, 26, 31, 36, 37, 41, 52, 58, 59, 61, 62, 69, 79, 80, 92, 107, 113, 123, 124, 129, 130, 131, 154, 155, 161], "natur": [1, 33, 51, 58, 76, 88, 102, 116, 124, 154], "part": [1, 3, 5, 31, 40, 41, 151, 159, 161], "being": [1, 2, 6, 7, 16, 31, 52, 80, 113, 116, 124, 126, 130, 154, 165], "smallest": 1, "power": [1, 40, 66, 75, 76, 92, 113, 118, 122, 129, 159, 161, 165], "two": [1, 2, 3, 6, 8, 11, 22, 31, 37, 40, 41, 58, 63, 66, 69, 72, 75, 76, 79, 84, 102, 103, 107, 110, 113, 115, 122, 123, 124, 126, 127, 129, 130, 135, 144, 153, 154, 158, 161], "To": [1, 3, 5, 23, 31, 34, 37, 40, 42, 49, 50, 51, 52, 58, 60, 62, 66, 74, 79, 80, 83, 87, 92, 95, 106, 110, 111, 114, 116, 118, 120, 123, 129, 130, 131, 141, 146, 148, 153, 161], "make": [1, 3, 6, 10, 12, 19, 23, 26, 27, 31, 33, 34, 40, 64, 72, 75, 76, 80, 106, 107, 110, 113, 116, 123, 130, 131, 132, 142, 144, 145, 148, 149, 154], "less": [1, 3, 15, 31, 51, 63, 80, 87, 88, 113, 120, 158, 161], "prone": 1, "numer": [1, 58, 157], "spinal": [1, 2, 4, 7, 8, 9, 14, 29, 30, 31, 33, 36, 40, 47, 50, 52, 68, 72, 79, 80, 92, 93, 95, 105, 107, 108, 110, 111, 113, 114, 116, 118, 122, 123, 124, 129, 130, 131, 134, 135, 137, 138, 145, 146, 148, 154, 155, 158], "core": [1, 8, 30, 31, 33, 36, 47, 50, 52, 54, 58, 72, 74, 79, 80, 84, 92, 93, 103, 105, 107, 108, 113, 114, 118, 122, 123, 131, 134, 135, 137, 138, 145, 146, 148, 149, 159], "constructor": [1, 4, 6, 130, 154, 155, 159, 161], "conveni": [1, 116], "wrapper": [1, 32, 122], "exist": [1, 6, 29, 30, 96, 107, 126, 130, 153, 154, 157, 159, 161], "form": [1, 124, 126], "sampl": [1, 40, 49, 52, 69, 91, 110, 114, 130, 132, 138, 154], "uq_8_2": 1, "10": [1, 3, 4, 5, 9, 30, 31, 41, 52, 58, 62, 63, 80, 93, 105, 108, 112, 113, 114, 122, 124, 129, 131, 132, 135, 137, 138, 140, 148], "q_8_2": 1, "loss": [1, 3], "sourc": [1, 6, 10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 27, 37, 44, 47, 52, 58, 60, 62, 75, 76, 79, 82, 103, 111, 112, 113, 118, 141, 142, 143, 146, 149, 154, 157, 158, 159, 165], "too": [1, 36, 41, 52, 95, 131, 140, 142, 143, 158], "big": [1, 3, 33, 84, 109, 113, 114, 130], "resiz": [1, 3, 5, 6, 25, 26, 31, 57, 124, 129, 161], "match": [1, 4, 5, 26, 30, 36, 76, 92, 108, 112, 113, 124, 134, 135, 137, 138, 158, 161], "destin": [1, 154, 161], "i16_m2": 1, "i16_0": 1, "i8_m2": 1, "o16_m2": 1, "o16_m0": 1, "o14_m2": 1, "14": [1, 63, 92], "ok": [1, 40], "Not": [1, 3], "target": [1, 30, 52, 83, 84, 103, 123, 124, 129], "o18_m2": 1, "18": [1, 92, 112], "o18_22b": 1, "22": [1, 92], "doubl": [1, 2, 30, 40, 63, 153, 154], "signal": [1, 3, 4, 5, 6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 20, 21, 25, 27, 28, 30, 33, 36, 37, 38, 41, 42, 47, 51, 57, 69, 79, 85, 87, 93, 99, 101, 102, 108, 109, 112, 113, 114, 116, 117, 122, 123, 124, 125, 127, 129, 130, 132, 135, 138, 141, 152, 153, 156, 157, 159, 161], "i4_m2": 1, "Will": [1, 19, 30, 36, 63, 66, 107, 116, 122, 158], "load": [1, 36, 40, 75, 80, 82, 83, 107, 108, 130, 149, 154, 159], "read": [1, 3, 5, 7, 11, 13, 26, 31, 32, 34, 36, 37, 40, 49, 51, 52, 58, 69, 79, 88, 91, 92, 101, 102, 103, 106, 109, 112, 113, 114, 116, 124, 128, 131, 140, 141, 154, 155, 156, 161, 163], "written": [1, 5, 37, 64, 75, 82, 110, 116, 122, 129, 130, 148, 159], "properti": [1, 120, 154, 161], "17": [1, 62, 92, 95], "avail": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 62, 69, 80, 82, 84, 99, 103, 108, 113, 122, 140, 142, 143, 155, 165], "return": [1, 2, 3, 4, 5, 6, 7, 8, 26, 30, 31, 33, 37, 38, 51, 52, 58, 66, 86, 87, 88, 92, 105, 106, 107, 108, 109, 110, 112, 113, 114, 122, 123, 127, 129, 131, 132, 147, 154, 155, 156, 158, 159, 161], "amplitud": 1, "x": [1, 2, 3, 4, 5, 6, 7, 8, 31, 38, 52, 58, 86, 87, 107, 108, 109, 113, 114, 119, 122, 124, 126, 127, 129, 130, 155, 161, 162], "y": [1, 3, 4, 5, 6, 7, 8, 31, 38, 58, 86, 87, 107, 108, 112, 113, 114, 124, 126, 127, 161, 162], "equal": [1, 3, 4, 5, 6, 7, 8, 9, 31, 37, 69, 129], "bool": [1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 16, 21, 26, 28, 30, 33, 34, 37, 40, 41, 42, 45, 47, 48, 51, 52, 58, 59, 66, 69, 80, 85, 86, 91, 95, 99, 102, 108, 109, 110, 112, 113, 114, 116, 117, 122, 123, 126, 127, 130, 148, 153, 154, 155, 156, 158, 159, 161, 162, 163], "inequ": [1, 3, 4, 5, 6, 7, 8, 31], "asbit": [1, 2, 3, 4, 5, 6, 7, 8, 26, 31, 33, 37, 112, 124], "binari": [1, 2, 3, 4, 5, 6, 7, 8, 31, 82, 83, 131], "w": [1, 2, 3, 4, 5, 6, 7, 8, 31, 34, 37, 87, 112], "asuint": [1, 3, 5, 6, 8, 31], "uint": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 64, 66, 69, 80, 85, 86, 97, 99, 108, 110, 112, 113, 114, 122, 123, 124, 126, 127, 130, 131, 134, 138, 148, 152, 153, 154, 155, 156, 158, 159, 161, 163], "assint": [1, 3, 5, 6, 8, 31], "sint": [1, 2, 4, 5, 6, 8, 9, 28, 49, 59, 64, 112, 122, 124, 148, 155, 158, 161], "asbool": [1, 2, 3, 5, 31], "arrai": [1, 2, 3, 5, 26, 30, 31, 36, 50, 51, 58, 59, 63, 79, 94, 123, 129, 134, 135, 137, 138, 148, 153, 154, 155, 161], "vec": [1, 2, 3, 5, 9, 12, 28, 36, 44, 58, 59, 66, 95, 112, 113, 114, 130, 158], "touint": [1, 2], "tosint": [1, 2], "toufix": 1, "tosfix": 1, "name": [1, 3, 4, 6, 7, 8, 26, 27, 30, 31, 34, 37, 38, 40, 41, 42, 47, 48, 49, 60, 63, 64, 69, 75, 76, 80, 82, 85, 86, 87, 88, 91, 92, 95, 106, 110, 112, 113, 114, 117, 123, 130, 144, 153, 154, 157], "storabl": 1, "encod": [2, 31, 127, 136], "second": [2, 3, 6, 51, 76, 82, 84, 114, 122, 132, 149, 161], "recfloat": 2, "help": [2, 6, 66, 68, 75, 95, 129, 149, 158, 159], "simplifi": 2, "design": [2, 6, 7, 11, 12, 17, 19, 23, 27, 30, 51, 52, 59, 60, 63, 64, 65, 66, 67, 74, 75, 76, 80, 102, 110, 111, 112, 113, 123, 124, 129, 130, 135, 139, 144, 153, 154, 155, 159, 161, 165], "edg": [2, 58, 132, 133, 135, 154, 161], "case": [2, 3, 7, 10, 12, 16, 19, 22, 23, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 59, 66, 69, 73, 75, 79, 85, 86, 87, 88, 91, 92, 94, 97, 99, 101, 102, 107, 108, 110, 111, 112, 113, 116, 117, 122, 123, 124, 126, 127, 129, 130, 152, 154, 155, 156, 158, 159, 161, 163], "compos": [2, 92, 107], "field": [2, 3, 92, 112], "mantissa": [2, 30], "de": 2, "facto": 2, "import": [2, 4, 6, 8, 27, 30, 31, 33, 36, 38, 40, 47, 50, 52, 61, 66, 67, 79, 92, 93, 105, 107, 108, 110, 111, 112, 113, 118, 123, 124, 126, 127, 129, 131, 134, 135, 137, 138, 145, 146, 148, 155, 158, 161], "lib": [2, 30, 31, 36, 40, 47, 50, 54, 72, 79, 80, 92, 93, 95, 105, 108, 110, 111, 112, 113, 118, 122, 144, 154, 155, 158, 161], "experiment": [2, 9, 141], "math": [2, 3, 26, 40, 49, 64], "_": [2, 4, 5, 8, 26, 27, 30, 31, 33, 36, 38, 40, 47, 50, 52, 66, 79, 92, 93, 105, 107, 108, 110, 111, 112, 113, 118, 123, 130, 131, 134, 135, 137, 138, 145, 146, 148, 154, 155, 158, 161], "sinc": [2, 36, 69, 76, 119, 130, 138, 141, 149, 158], "ha": [2, 3, 6, 9, 18, 20, 23, 30, 31, 36, 37, 40, 42, 51, 52, 58, 59, 62, 66, 69, 74, 75, 76, 79, 80, 82, 85, 86, 87, 88, 91, 92, 95, 110, 113, 114, 120, 122, 126, 127, 129, 130, 138, 142, 143, 149, 153, 154, 155, 158, 165], "quirk": [2, 128], "special": [2, 3, 9, 27, 63, 102, 124, 149, 152, 157], "berkelei": 2, "propos": [2, 158], "modifi": [2, 3, 5, 28, 60, 80, 92, 113, 123], "so": [2, 3, 12, 18, 20, 27, 30, 33, 36, 37, 40, 49, 52, 60, 62, 69, 72, 73, 75, 92, 93, 107, 110, 113, 126, 130, 131, 149, 154, 155, 158, 159, 164], "treat": 2, "same": [2, 3, 5, 6, 7, 11, 18, 25, 27, 31, 34, 36, 41, 58, 63, 64, 66, 67, 69, 75, 76, 88, 102, 107, 112, 113, 120, 122, 123, 124, 126, 127, 129, 130, 132, 153, 154, 155, 158, 159, 162, 163], "ones": [2, 3, 4, 5, 59, 64, 65, 66, 76, 80, 155], "kept": 2, "unchang": [2, 3], "three": [2, 6, 31, 37, 41, 50, 63, 80, 106, 123, 126, 144, 161], "lead": 2, "set": [2, 3, 5, 6, 7, 8, 31, 33, 34, 36, 37, 40, 41, 51, 52, 60, 63, 65, 66, 69, 76, 80, 91, 92, 95, 101, 102, 107, 108, 112, 113, 114, 115, 116, 120, 122, 123, 124, 126, 129, 130, 131, 132, 139, 148, 154, 159, 161, 162], "first": [2, 3, 4, 6, 7, 14, 26, 27, 31, 33, 34, 36, 41, 44, 49, 52, 62, 66, 69, 76, 80, 82, 84, 85, 86, 87, 105, 109, 110, 112, 113, 114, 121, 122, 123, 135, 145, 148, 158], "becom": [2, 14, 41, 92, 110, 113, 122], "implicit": [2, 22, 57, 69, 110, 114, 120, 132], "107": 2, "plu": [2, 69], "index": [2, 3, 4, 5, 8, 27, 31, 36, 58, 63, 113, 114, 122, 127], "highest": [2, 3, 5, 122], "exactli": [2, 122, 123, 126, 154], "origin": [2, 3, 5, 30, 116, 124], "130": 2, "don": [2, 3, 5, 6, 9, 11, 31, 33, 41, 51, 58, 59, 63, 64, 67, 72, 75, 88, 108, 112, 113, 129, 130, 145, 155, 156, 158, 161], "t": [2, 3, 4, 5, 6, 9, 11, 13, 14, 20, 21, 26, 30, 31, 33, 41, 52, 58, 59, 63, 64, 65, 66, 67, 72, 75, 76, 79, 84, 88, 92, 101, 102, 106, 108, 109, 112, 113, 114, 116, 121, 122, 124, 126, 127, 129, 130, 132, 145, 154, 155, 156, 158, 161, 162], "care": [2, 5, 6, 9, 41, 63, 76, 108, 113, 126, 127, 129, 149, 154], "6": [2, 3, 5, 19, 24, 27, 30, 31, 33, 58, 59, 63, 66, 80, 84, 92, 97, 112, 122, 130], "rest": [2, 80, 103, 124], "exponents": 2, "mantissas": 2, "floating16": 2, "half": 2, "floating32": 2, "singl": [2, 4, 6, 7, 11, 30, 31, 37, 40, 58, 60, 64, 75, 79, 84, 92, 96, 110, 113, 114, 115, 122, 123, 124, 129, 136, 149, 154, 159], "floating64": 2, "floating128": 2, "quad": 2, "recfloating16": 2, "recfloating32": 2, "recfloating64": 2, "recfloating128": 2, "fromuint": 2, "fromsint": 2, "interpret": [3, 5, 33, 42, 63], "complement": 3, "thei": [3, 5, 6, 7, 14, 21, 26, 50, 51, 58, 73, 92, 102, 105, 107, 122, 123, 126, 127, 155, 158], "everyth": [3, 5, 6, 51, 58, 63, 72, 77, 107, 156, 159, 161], "option": [3, 5, 6, 19, 42, 51, 52, 58, 62, 67, 84, 103, 113, 115, 123, 125, 129, 130, 142, 157, 161], "descript": [3, 5, 14, 15, 18, 21, 26, 27, 31, 33, 34, 37, 38, 40, 41, 48, 49, 50, 52, 57, 60, 63, 69, 72, 75, 80, 82, 85, 86, 87, 88, 91, 92, 95, 105, 106, 107, 108, 109, 110, 112, 113, 114, 116, 117, 122, 123, 124, 127, 129, 130, 131, 132, 144, 147, 148, 151, 154, 155, 157, 159, 161, 162, 163], "count": [3, 4, 5, 31, 36, 37, 38, 40, 41, 52, 59, 113, 124, 127, 154, 158], "infer": [3, 5, 16, 31, 58, 59, 75, 87, 102, 124, 129, 130, 154, 161], "assign": [3, 4, 5, 6, 8, 12, 13, 14, 16, 17, 18, 21, 22, 23, 26, 28, 38, 40, 43, 57, 58, 63, 66, 69, 102, 106, 108, 114, 121, 125, 127, 130, 144, 148, 154, 156, 157, 158, 162], "base": [3, 5, 6, 9, 26, 30, 31, 32, 34, 37, 40, 41, 51, 75, 78, 80, 110, 113, 114, 120, 122, 124, 126, 145, 153, 157, 159], "h": [3, 5, 31, 41, 99, 145], "o": [3, 5, 31, 102, 123, 158], "element": [3, 4, 5, 8, 22, 26, 30, 31, 34, 37, 38, 40, 51, 75, 88, 113, 114, 122, 123, 126, 127, 129, 130, 145, 154, 155, 158, 159, 161], "specifi": [3, 5, 7, 11, 14, 26, 27, 28, 30, 31, 37, 38, 41, 58, 59, 61, 63, 76, 80, 86, 87, 91, 92, 94, 95, 97, 107, 109, 113, 122, 123, 126, 127, 129, 130, 131, 132, 153, 154, 163], "myuint": [3, 31, 59], "0000_0101": [3, 31], "per": [3, 26, 31, 40, 42, 113, 132, 149, 154], "h1a": [3, 31], "could": [3, 5, 7, 10, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 31, 33, 40, 42, 49, 50, 51, 52, 64, 66, 79, 80, 82, 83, 84, 86, 88, 91, 97, 99, 108, 109, 111, 113, 114, 115, 116, 117, 126, 145, 149, 154, 159, 161, 162, 163, 164], "scala": [3, 4, 5, 6, 11, 12, 18, 30, 31, 34, 36, 37, 42, 50, 58, 60, 61, 62, 63, 64, 67, 68, 75, 76, 80, 107, 108, 112, 117, 120, 122, 124, 125, 130, 134, 135, 137, 138, 141, 148, 149, 155, 156, 157, 159, 161, 163], "liter": [3, 19, 28, 57, 63, 66, 118, 124, 129], "mybool": [3, 4, 5, 6, 7, 31, 59], "downto": [3, 5, 26, 31, 34, 51, 58, 59, 106, 112, 116, 123, 127, 153, 162], "purpos": [3, 5, 18, 31, 33, 37, 51, 72, 75, 102, 128, 133, 154, 158, 163, 165], "omit": [3, 5, 31, 159], "11111111": [3, 5, 31], "10000000": [3, 5, 31], "00011110": [3, 31], "bitwis": [3, 5, 31, 125], "NOT": [3, 5, 6, 31], "AND": [3, 5, 6, 31], "OR": [3, 5, 6, 25, 31, 127, 153, 158], "xor": [3, 5, 6, 31], "xorr": [3, 5, 31], "reduct": [3, 158], "orr": [3, 5, 31, 36, 37, 158], "andr": [3, 5, 31], "rotateleft": [3, 5, 31], "rotat": [3, 5, 31], "constrain": [3, 51], "log2up": [3, 8, 31, 38, 40, 49, 88, 113, 122, 127, 153, 161], "rotateright": [3, 5], "clearal": [3, 5, 31], "clear": [3, 5, 6, 26, 31, 37, 44, 46, 48, 58, 59, 92, 106, 112, 114, 126, 132, 135], "setal": [3, 5, 31], "setallto": [3, 5, 31], "given": [3, 4, 5, 6, 8, 30, 31, 33, 36, 50, 51, 63, 66, 76, 80, 84, 92, 103, 107, 108, 109, 110, 113, 122, 123, 124, 127, 129, 130, 132, 133, 141, 148, 152, 154, 158, 159, 161], "notic": [3, 122, 130], "behaviour": [3, 31, 36, 51, 126, 154, 158, 161], "narrow": [3, 124], "keep": [3, 5, 30, 36, 37, 41, 52, 69, 80, 92, 113, 114, 116, 121, 123, 130], "due": [3, 14, 31, 58, 76, 126, 130, 149], "In": [3, 5, 6, 7, 8, 9, 13, 16, 19, 20, 22, 23, 30, 32, 40, 41, 52, 58, 59, 60, 61, 63, 67, 68, 69, 75, 76, 79, 80, 92, 93, 94, 102, 105, 106, 107, 110, 112, 113, 117, 120, 123, 126, 129, 130, 132, 143, 144, 145, 150, 152, 153, 154, 157, 161], "seen": [3, 6, 159], "constant": [3, 5, 6, 9, 14, 31, 63, 66, 159], "invers": [3, 5], "assert": [3, 26, 40, 41, 80, 113, 114, 131, 134, 135, 137, 138, 139, 154], "getwidth": [3, 5, 26, 31, 41, 64, 97], "arithshift": 3, "logicshift": 3, "carri": [3, 6, 41, 46, 58, 64, 102, 109, 113, 161], "addend": 3, "satur": 3, "see": [3, 7, 11, 31, 33, 40, 41, 50, 51, 60, 67, 69, 92, 94, 102, 103, 106, 109, 110, 122, 124, 126, 129, 130, 142, 155, 159], "subtrahend": 3, "unari": 3, "One": [3, 31, 33, 37, 40, 42, 66, 80, 82, 84, 93, 117, 118, 158], "compliment": 3, "xf0": 3, "x0f": 3, "xff": [3, 5], "x0ff": 3, "0xf0": 3, "0x20": [3, 158], "would": [3, 6, 40, 41, 51, 52, 67, 69, 109, 114, 124, 130, 159], "therefor": [3, 6, 112, 116, 123, 131, 141, 142, 149], "x20": 3, "simul": [3, 14, 27, 33, 51, 59, 60, 62, 75, 76, 79, 110, 117, 119, 127, 128, 132, 134, 135, 137, 138, 139, 140, 146, 147, 151, 153, 154, 161, 165], "made": [3, 126], "oppos": 3, "previou": [3, 10, 30, 34, 63, 69, 126], "elsewhen": [3, 40, 59, 64, 127, 161], "01": [3, 5], "otherwis": [3, 38, 40, 58, 59, 64, 127, 132, 159, 161], "compar": [3, 4, 7, 9, 19, 31, 52, 62, 108, 113, 120, 149, 158], "wraparound": 3, "behavior": [3, 124, 126, 127], "wrap": [3, 84, 116, 124, 126], "around": [3, 27, 31, 76, 77, 122, 149, 155], "exce": 3, "variabl": [3, 5, 18, 43, 58, 66, 88, 120, 131, 145, 146, 152, 153, 159], "sens": [3, 10, 19, 23, 64], "lsb": [3, 5, 6, 7, 31, 33, 114, 122, 124], "data": [3, 4, 5, 7, 8, 26, 27, 28, 30, 33, 34, 38, 39, 48, 51, 52, 57, 58, 64, 66, 74, 75, 84, 85, 91, 92, 93, 101, 102, 106, 108, 113, 115, 116, 122, 127, 129, 130, 135, 137, 148, 153, 154, 155, 156, 158, 159, 161, 165], "intosint": 3, "convert": [3, 6, 34, 48, 111, 114, 118, 122, 124, 149, 156, 159, 161], "twocompl": 3, "en": [3, 52, 129, 153, 161], "gener": [3, 6, 7, 14, 16, 18, 23, 28, 31, 33, 37, 39, 40, 41, 49, 50, 51, 58, 59, 60, 61, 62, 63, 64, 67, 68, 72, 75, 78, 80, 81, 82, 92, 94, 95, 103, 107, 109, 110, 113, 116, 119, 121, 126, 127, 129, 131, 132, 138, 141, 142, 143, 146, 149, 156, 157, 158, 159, 163, 165], "neg": 3, "mysint": [3, 5, 6], "ab": [3, 59], "absolut": [3, 27], "just": [3, 26, 33, 34, 49, 62, 67, 69, 75, 80, 116, 122, 123, 127, 130, 144, 153, 158], "reinterpret": 3, "abswithsym": 3, "symmetr": 3, "shrink": 3, "someth": [3, 5, 6, 10, 17, 23, 30, 34, 51, 63, 64, 66, 107, 116, 126, 130, 154, 158], "thing": [3, 26, 27, 30, 31, 33, 34, 37, 40, 47, 49, 51, 52, 58, 60, 62, 66, 75, 92, 102, 105, 107, 109, 111, 116, 120, 122, 124, 127, 130, 155, 158, 161], "mybit": [3, 5, 6, 7, 8, 9, 31], "myvec": [3, 5], "convers": [3, 75, 113, 124], "uint_30": 3, "30": [3, 122], "sint_30": 3, "booleandoinvert": 3, "we": [3, 5, 6, 7, 13, 22, 27, 33, 34, 36, 37, 40, 41, 42, 51, 52, 60, 62, 68, 80, 107, 112, 121, 145, 148, 158], "get": [3, 4, 5, 6, 19, 26, 27, 30, 31, 34, 36, 40, 51, 60, 62, 69, 76, 77, 92, 95, 102, 107, 111, 113, 120, 122, 126, 129, 131, 140, 142, 143, 145, 153, 155, 158, 165], "sint_n_4": 3, "abs_en": 3, "sint_n_3": 3, "booleandoab": 3, "b101": 3, "raw": [3, 51, 112, 122], "pattern": [3, 9, 36, 80, 158, 159], "sint_n_128": 3, "128": [3, 4, 58, 93, 113, 127], "sym_ab": 3, "127": [3, 5], "group": [3, 4, 5, 7, 26, 31, 40, 64, 71, 152, 157], "like": [3, 5, 6, 9, 12, 14, 20, 27, 38, 40, 43, 51, 59, 60, 61, 64, 66, 67, 75, 79, 80, 92, 93, 95, 102, 107, 110, 116, 123, 124, 126, 127, 129, 130, 133, 142, 143, 144, 149, 150, 153, 154, 155, 161], "other": [3, 5, 6, 15, 16, 27, 30, 40, 51, 52, 58, 60, 75, 77, 87, 92, 102, 109, 112, 113, 116, 120, 122, 123, 126, 130, 149, 151, 155, 165], "hdl": [3, 5, 6, 7, 33, 50, 62, 76, 82, 105, 118, 122, 123, 126, 129, 130, 141, 144, 149, 155, 157, 159], "static": [3, 5, 8, 19, 58, 63, 75, 84, 159], "access": [3, 5, 13, 18, 26, 30, 34, 37, 50, 51, 52, 58, 63, 69, 80, 92, 93, 103, 109, 129, 132, 133, 158, 165], "th": [3, 5, 112], "offset": [3, 5, 26, 31, 37, 59, 92, 112], "ex": [3, 5, 58, 93, 107, 158, 159], "subdividein": [3, 5, 127], "slice": [3, 5, 129], "strict": [3, 5, 58, 127], "msb": [3, 5, 7, 31, 114, 122], "most": [3, 5, 30, 31, 37, 49, 58, 65, 75, 102, 111, 112, 141, 143, 149, 159], "signific": [3, 5, 31], "lowest": [3, 5, 122], "basic": [3, 4, 5, 7, 14, 37, 50, 51, 94, 103, 130, 159, 161], "dynam": [3, 5, 8, 58, 79, 80, 84], "myuint_8bit": 3, "myuint_16bit": 3, "myuint_7bit": 3, "myuint_6bit": 3, "until": [3, 5, 18, 26, 31, 36, 37, 43, 44, 49, 51, 52, 58, 64, 92, 107, 113, 114, 127, 131, 132, 133, 135, 137, 138, 139, 141, 150, 159, 162, 163], "myuint_4bit": 3, "equival": [3, 4, 5, 6, 7, 8, 29, 31, 51, 57, 63, 108, 122, 124, 126, 127, 129, 130, 131, 140, 149, 159, 161], "revers": [3, 5, 7, 31, 86, 87, 114], "occur": [3, 4, 5, 6, 26, 33, 41, 52, 59, 92, 106, 124, 126, 129, 130, 131, 132, 155], "leftmost": [3, 5, 122], "isneg": [3, 5], "mysint_16bit": 3, "both": [3, 5, 6, 41, 59, 75, 79, 102, 108, 113, 116, 122, 124, 126, 133, 144, 145, 149], "overload": [3, 5], "paramet": [3, 5, 22, 26, 27, 31, 37, 39, 41, 49, 51, 58, 59, 63, 66, 80, 85, 86, 87, 95, 97, 112, 113, 123, 129, 130, 144, 152, 153, 154, 157, 158, 161], "slicescount": [3, 5], "rais": [3, 5, 22, 76, 92, 124], "divid": [3, 5, 34, 40, 58, 91, 113, 127, 154], "last": [3, 5, 6, 31, 40, 52, 63, 69, 79, 94, 109, 113, 114, 122, 124, 125, 130, 145, 157, 161], "sel": [3, 5, 24, 58, 114, 127], "myuintword": 3, "myuint_128bit": 3, "96": [3, 5, 41], "95": [3, 5], "want": [3, 5, 8, 10, 15, 22, 26, 27, 31, 36, 40, 47, 49, 51, 52, 58, 59, 63, 66, 76, 85, 86, 87, 92, 101, 112, 113, 116, 122, 129, 130, 144, 153, 154, 155, 156, 158, 159, 161], "order": [3, 5, 6, 7, 8, 27, 30, 31, 36, 40, 49, 63, 79, 92, 107, 110, 112, 113, 122, 126, 145, 149, 153, 154], "myvector": [3, 5], "myrevuintword": 3, "through": [3, 5, 6, 11, 28, 30, 66, 108, 113, 114, 116, 126, 143, 144, 149, 159], "output8": [3, 5], "piec": [3, 5, 37, 69, 122, 126], "0xf": [3, 5, 92, 130], "0x5": [3, 5], "contrast": [3, 5, 113], "list": [3, 5, 6, 8, 11, 14, 26, 27, 30, 31, 37, 50, 51, 60, 80, 92, 93, 94, 114, 122, 127, 132, 144, 155, 159], "abov": [3, 5, 6, 8, 13, 18, 30, 34, 41, 67, 76, 92, 95, 102, 103, 107, 110, 113, 122, 126, 129, 130, 132, 153], "possibl": [3, 5, 11, 12, 14, 40, 42, 51, 62, 63, 75, 79, 80, 110, 127, 129, 130, 131, 141, 154, 158, 159], "bitsrang": [3, 5], "g": [3, 6, 7, 8, 16, 22, 38, 40, 41, 44, 48, 59, 63, 64, 66, 74, 95, 97, 116, 124, 130, 131, 145, 156, 161], "valuerang": [3, 5], "concaten": [3, 5, 6, 31, 122], "low": [3, 5, 6, 7, 31, 41, 49, 51, 80, 86, 93, 108, 113, 114, 117, 133, 154, 161], "copi": [3, 5, 26, 30, 31, 51, 60, 88, 124, 144, 161], "enlarg": [3, 5], "fill": [3, 4, 26, 31, 52, 93, 105, 106, 130, 135, 137, 155, 161], "version": [3, 5, 29, 31, 36, 49, 60, 73, 79, 84, 112, 113, 114, 122, 142, 143, 145, 154, 158, 159, 165], "need": [3, 4, 5, 6, 7, 8, 16, 20, 22, 26, 27, 31, 33, 34, 38, 40, 41, 52, 58, 59, 60, 61, 62, 63, 64, 67, 69, 75, 76, 80, 83, 85, 86, 87, 88, 92, 93, 99, 102, 106, 107, 110, 111, 118, 122, 123, 124, 127, 129, 130, 137, 145, 151, 152, 154, 155, 158, 159, 161], "getzero": [3, 5, 31], "instanc": [3, 5, 6, 19, 22, 30, 31, 34, 36, 37, 51, 52, 60, 62, 66, 67, 84, 88, 91, 106, 116, 121, 122, 123, 124, 126, 127, 129, 130, 131, 133, 135, 137, 154, 155, 156, 158, 161], "getalltru": [3, 5], "validrang": [3, 5], "fit": [3, 5, 79, 88, 95, 102], "limit": [3, 5, 37, 51, 58, 60, 93, 131, 149, 155, 156, 159, 161], "collect": [3, 5, 26, 66, 120, 122, 135, 137, 155, 159], "immut": [3, 5], "mysint_1": 3, "myuint_32bit": 3, "x112233344": [3, 5], "0x44": [3, 5], "lowest_8bit": 3, "round": [3, 113], "http": [3, 30, 36, 52, 53, 55, 56, 60, 76, 80, 83, 84, 92, 93, 103, 115, 142, 143, 145], "org": [3, 60, 145], "wiki": [3, 83, 143], "mathemat": 3, "algorithm": [3, 12, 51, 75, 105], "n": [3, 8, 27, 31, 40, 80, 84, 112, 114, 122, 131], "ye": [3, 34, 76], "No": [3, 14, 52, 75, 76, 92, 93, 154, 157], "veri": [3, 26, 27, 33, 37, 38, 41, 58, 63, 65, 66, 79, 80, 88, 105, 107, 112, 129, 130, 158], "statist": 3, "accuraci": 3, "concern": [3, 6, 79], "doesn": [3, 58, 59, 64, 65, 76, 79, 102, 109, 124, 126, 130, 145, 154, 161], "them": [3, 7, 26, 31, 40, 41, 51, 52, 58, 60, 63, 66, 75, 80, 87, 92, 95, 106, 110, 113, 116, 120, 123, 126, 127, 129, 131, 140, 144, 145, 154, 156, 158, 159, 161, 165], "yet": [3, 76, 107, 116, 163], "rountoodd": 3, "close": [3, 37, 58, 76, 117, 127, 145, 149], "program": [3, 6, 18, 33, 50, 58, 63, 65, 95, 145, 159, 163, 165], "languag": [3, 9, 18, 27, 31, 36, 65, 66, 68, 70, 73, 75, 77, 108, 110, 129, 141, 149, 159, 161, 163], "comment": [3, 42], "matlab": 3, "infin": 3, "python2": 3, "python3": 3, "even": [3, 30, 37, 40, 51, 72, 75, 107, 110, 113, 130, 142], "roundtoup": 3, "got": [3, 131, 158], "b0": [3, 112, 121, 154, 158], "b1": [3, 4, 158], "simpl": [3, 26, 28, 33, 34, 37, 38, 39, 41, 49, 50, 51, 52, 61, 62, 67, 75, 76, 77, 79, 80, 88, 106, 108, 111, 113, 123, 129, 134, 138, 149, 156, 161], "hw": [3, 60, 112], "chose": 3, "although": [3, 112], "least": [3, 31, 52, 84, 92, 93], "cost": [3, 76, 79, 103, 113], "good": [3, 26, 31, 33, 41, 58, 80, 118, 122, 127, 155, 161], "almost": [3, 58, 62, 153], "perform": [3, 6, 8, 14, 36, 51, 62, 67, 68, 84, 88, 134, 138, 151, 158, 159], "As": [3, 33, 36, 41, 51, 52, 60, 63, 66, 67, 75, 79, 102, 103, 109, 113, 116, 122, 126, 127, 129, 130, 131, 141, 159, 161], "strongli": 3, "product": [3, 75], "posit": [3, 9, 14, 31, 114], "op": [3, 4, 30, 58, 60], "top": [3, 27, 40, 50, 51, 52, 58, 66, 102, 121, 126, 130, 133, 153, 154, 159, 161], "trim": 3, "discard": 3, "symmetri": [3, 51], "valid": [3, 7, 26, 30, 31, 34, 36, 38, 40, 41, 51, 52, 58, 87, 106, 108, 110, 113, 117, 124, 125, 127, 130, 135, 137, 154, 157, 158], "rtl": [3, 18, 58, 59, 72, 78, 81, 96, 107, 110, 119, 123, 126, 129, 130, 131, 135, 137, 155, 157, 163], "handl": [3, 36, 92, 102, 110, 115, 130, 135, 137, 157, 159], "calcul": [3, 39, 40, 47, 49, 107, 156, 161], "manual": [3, 12, 40, 43, 52, 102, 103, 112, 113, 124, 129, 154, 161], "way1": 3, "diagram": [3, 26, 27, 30, 79, 80], "factori": [3, 28, 34, 66, 80], "section": [3, 28, 50, 60, 69, 77, 123, 152, 159, 164], "fixfunct": 3, "sym": 3, "20": [3, 30, 40, 51, 80, 92, 95, 122, 131], "composit": [4, 7, 9, 31, 52, 130, 157], "mix": [4, 31, 33, 36, 58, 80, 126, 128, 163], "myvecofsint": [4, 31], "popul": [4, 80], "myvecofmixeduint": [4, 31], "z": [4, 31, 116, 124, 131, 161], "myvecof_xyz_ref": [4, 31], "iter": [4, 30, 38, 84, 114, 122, 130, 159], "map": [4, 7, 26, 27, 32, 36, 37, 51, 58, 64, 66, 103, 106, 112, 116, 127, 157, 159], "vec2": 4, "vec1": 4, "mybits_16bit": [4, 5], "getbitswidth": [4, 7, 26, 33, 124], "full": [4, 11, 12, 37, 58, 76, 80, 84, 92, 93, 95, 103, 127, 155], "println": [4, 5, 30, 63, 95, 107, 120, 122, 131, 144, 148, 158], "widthof": [4, 26, 106, 122], "put": [4, 6, 27, 41, 92], "scope": [4, 13, 14, 30, 43, 58, 120, 124, 127, 129, 130, 156, 158, 161], "scount": 4, "condit": [4, 30, 58, 59, 64, 69, 84, 126, 127, 129, 130, 131, 132, 133, 141, 157, 159, 161], "sexist": 4, "scontain": 4, "present": [4, 23, 27, 52, 65, 71, 73, 76, 84, 87, 92, 99, 108, 109, 113, 114, 122, 129, 161], "sfindfirst": 4, "reducebalancedtre": 4, "balanc": 4, "reduc": [4, 5, 66, 75, 79, 80, 88, 131, 145, 154, 158, 159], "try": [4, 18, 51, 65, 116, 124], "minim": 4, "depth": [4, 11, 51, 52, 58, 60, 64, 76, 113, 122, 130, 135, 137, 144, 156], "circuit": [4, 75, 112], "should": [4, 6, 7, 12, 14, 26, 31, 33, 37, 51, 58, 59, 61, 62, 63, 64, 66, 67, 76, 85, 92, 94, 102, 113, 114, 117, 122, 126, 129, 131, 144, 145, 147, 149, 153, 154, 158, 161], "commut": 4, "associ": [4, 75, 110, 153], "shuffl": 4, "indexmap": 4, "old": [4, 30, 112, 129], "actual": [4, 62, 112, 155], "somewher": [4, 23, 30, 158], "c1": 4, "mani": [4, 14, 26, 30, 33, 36, 50, 51, 58, 60, 63, 66, 69, 75, 76, 79, 80, 88, 91, 95, 102, 106, 107, 113, 118, 122, 129, 131, 156, 159, 161], "c2": 4, "250": 4, "bigger": [4, 26, 51, 63, 106, 150], "b2": 4, "u1": [4, 16], "u2": 4, "sum": [4, 43, 46, 63, 107, 155, 161], "togeth": [4, 11, 80, 92, 113, 124, 153], "sxxx": 4, "prefix": [4, 9, 31, 152, 157, 158, 162], "disambigu": 4, "respect": [4, 144, 155], "ident": [4, 131], "accept": [4, 27, 51, 112, 113, 149], "lambda": [4, 107, 159], "argument": [4, 6, 62, 66, 83, 85, 86, 87, 88, 106, 107, 114, 122, 123, 126, 129, 130, 153, 154, 156, 158, 159, 161], "convei": [5, 31], "arithmet": [5, 31, 134, 138], "widest": 5, "statement": [5, 6, 14, 16, 23, 30, 31, 51, 52, 59, 63, 64, 66, 110, 123, 124, 126, 127, 149, 154, 157, 161], "construct": [5, 6, 22, 31, 33, 37, 38, 39, 51, 59, 63, 64, 66, 75, 76, 80, 88, 111, 149, 152, 158, 159], "mybits1": 5, "mybits2": 5, "mybits3": 5, "mybits4": 5, "1001_0011": 5, "readabl": [5, 26, 30, 33, 34, 58, 64, 106], "mybits5": 5, "initi": [5, 18, 33, 51, 59, 60, 69, 80, 83, 87, 108, 113, 128, 129, 134, 138], "10111000": 5, "few": [5, 30, 40, 52, 62, 76, 79, 92, 93, 149, 158, 159], "mybits6": 5, "101": [5, 127], "mybits7": 5, "final": [5, 9, 69, 80, 95, 102, 149], "prevent": [5, 20, 52, 76, 127, 154], "mismatch": [5, 14, 154], "below": [5, 7, 11, 14, 31, 38, 51, 69, 110, 113, 126, 127, 129, 130, 131, 132, 153, 154, 157], "1010": 5, "widen": [5, 31, 124], "condxmayb": 5, "110000": 5, "xy": [5, 38], "increas": [5, 75, 76, 131, 141], "all_1": 5, "bits_10bit": 5, "bits_8bit": 5, "shift_8bit": 5, "x42": [5, 13, 21], "cond": [5, 6, 16, 21, 31, 51, 58, 59, 64, 108, 113, 123, 126, 127, 129, 130, 158, 161], "notmyspecialvalu": 5, "mybits_32": 5, "x44332211": 5, "necessari": [5, 27, 31, 63, 130, 154], "retain": [5, 31], "mybits_8bit": 5, "mybits_7bit": 5, "mybits_6bit": 5, "mybits_4bit": 5, "high": [5, 6, 7, 26, 31, 37, 40, 41, 45, 58, 74, 75, 79, 80, 82, 87, 99, 108, 109, 112, 113, 114, 116, 149, 154, 161, 165], "mybitsword": 5, "mybits_128bit": 5, "myrevbitsword": 5, "mirror": 5, "extend": [5, 7, 8, 10, 11, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 63, 64, 66, 69, 85, 86, 87, 91, 92, 93, 94, 97, 99, 101, 102, 106, 108, 110, 112, 113, 116, 117, 118, 119, 120, 121, 122, 123, 127, 129, 130, 131, 134, 138, 148, 152, 153, 154, 155, 156, 158, 159, 161, 163], "pad": [5, 6, 113, 124], "were": [5, 16, 30, 51, 76, 116, 142], "defer": [5, 130], "later": [5, 7, 31, 36, 37, 80, 107, 120, 148, 154, 158], "resizeleft": [5, 31, 124], "place": [5, 6, 7, 22, 26, 31, 40, 50, 63, 92, 106, 109, 113, 122, 123, 124, 129, 130, 131, 159], "mybits_32bit": 5, "mybits_24bit": 5, "bits_8bits_1": 5, "bits_8bits_2": 5, "bits_8bits_3": 5, "cat": [5, 31], "0x11": 5, "denot": 5, "direct": [5, 6, 15, 27, 37, 38, 41, 48, 49, 51, 58, 69, 91, 92, 102, 124, 127, 156, 161, 163], "switch": [5, 8, 14, 24, 30, 33, 40, 51, 58, 59, 110, 113, 118, 123, 124, 125, 151, 158], "mux": [5, 14, 31, 33, 113, 114, 118, 124, 125], "1101": 5, "test1": 5, "m": [5, 9, 31, 60, 80, 114, 122], "test2": 5, "test3": 5, "wire": [6, 31, 37, 51, 52, 58, 69, 75, 80, 112, 114, 123, 126, 128, 153, 154, 155, 158, 161], "similarli": [6, 107], "confus": 6, "describ": [6, 26, 27, 30, 33, 51, 52, 60, 69, 75, 76, 110, 123, 133, 155, 158, 159, 161], "truth": [6, 126], "concept": [6, 51, 58, 63, 65, 80, 102, 109], "rule": [6, 13, 18, 31, 60, 64, 69, 107, 125, 130, 155, 159, 161, 162, 163], "thumb": 6, "understand": [6, 51, 52, 65, 66, 124, 126, 130, 158], "decis": 6, "affect": [6, 30, 129], "execut": [6, 18, 26, 30, 36, 62, 66, 83, 92, 95, 107, 110, 115, 120, 126, 127, 130, 131, 132, 144, 150, 151, 153, 161, 163], "run": [6, 18, 28, 36, 52, 60, 61, 62, 67, 75, 79, 83, 107, 114, 117, 120, 135, 137, 144, 145, 163], "observ": 6, "becaus": [6, 12, 19, 22, 23, 27, 33, 36, 40, 41, 51, 58, 63, 64, 66, 69, 76, 79, 80, 88, 94, 109, 118, 122, 124, 126, 129, 131, 152, 161, 163], "ahead": 6, "gen": [6, 60], "scenario": [6, 124, 159], "might": [6, 60, 61, 113, 129, 130], "pass": [6, 49, 66, 67, 95, 123, 126, 144, 153, 156], "mayb": [6, 126], "act": 6, "parameter": [6, 23, 51, 57, 66, 122, 155, 159], "manipul": [6, 64, 126, 156, 158, 161], "rout": [6, 113], "modul": [6, 29, 37, 51, 80, 82, 84, 95, 121, 123, 153, 155, 158, 159], "compon": [6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 21, 22, 23, 24, 25, 26, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 44, 45, 47, 48, 49, 50, 51, 57, 59, 62, 64, 66, 72, 78, 81, 92, 93, 94, 95, 99, 108, 110, 112, 113, 116, 117, 118, 119, 121, 122, 127, 129, 130, 131, 132, 134, 135, 137, 138, 141, 149, 152, 153, 154, 156, 157, 159, 163], "driven": [6, 13, 41, 52, 75, 102, 116, 126, 130, 133, 154, 158, 161, 165], "connect": [6, 34, 40, 51, 69, 75, 80, 83, 86, 87, 92, 108, 113, 115, 116, 124, 130, 153, 155, 156, 161], "sunk": 6, "manag": [6, 33, 41, 47, 92, 93, 110, 114, 122, 133, 135, 137, 146, 159], "hand": [6, 116, 124, 159], "side": [6, 7, 11, 25, 31, 42, 76, 108, 113, 122, 124, 126, 145, 161], "dictat": 6, "state": [6, 8, 31, 32, 38, 40, 51, 52, 69, 92, 102, 108, 112, 116, 120, 122, 126, 161], "sink": [6, 58, 113, 158], "captur": [6, 26, 113, 131, 135, 154, 159], "normal": [6, 60, 64, 112], "drive": [6, 20, 26, 34, 37, 41, 47, 51, 52, 58, 84, 87, 101, 106, 108, 112, 113, 129], "abl": [6, 22, 26, 34, 41, 63, 76, 87, 88, 94, 116, 141, 145, 158], "appear": [6, 13, 51, 67, 76, 92, 126], "matter": [6, 76], "unlik": [6, 112, 137, 155, 161], "express": [6, 9, 30, 31, 76, 124, 126, 130, 157, 159], "win": [6, 31, 124, 125, 130, 161], "take": [6, 27, 33, 34, 37, 41, 51, 52, 62, 63, 66, 76, 97, 106, 110, 113, 122, 124, 127, 130, 131, 144, 153, 154, 161], "effect": [6, 47, 66, 92, 112, 113, 139, 145], "layout": [6, 80], "ensur": [6, 24, 52, 92, 110, 159], "correct": [6, 31, 75, 95, 102, 124, 134, 138], "preced": [6, 40, 66, 109, 127, 161], "archiv": 6, "relat": [6, 52, 64, 151], "refer": [6, 18, 30, 33, 40, 75, 105, 108, 113, 123, 125, 132, 135, 137, 143, 152, 156, 158, 161, 163], "net": 6, "attach": [6, 51, 74, 93, 103], "explicitli": [6, 59, 129, 130, 131, 153], "mybool_1": 6, "verilog": [6, 8, 14, 18, 30, 37, 60, 62, 66, 67, 68, 79, 94, 110, 116, 118, 119, 121, 124, 126, 127, 129, 130, 131, 133, 141, 144, 146, 150, 152, 156, 157, 159, 163, 165], "mybool_2": 6, "mybool_3": 6, "unit": [6, 7, 26, 30, 31, 33, 36, 40, 41, 42, 51, 58, 63, 85, 87, 91, 101, 102, 112, 116, 122, 123, 126, 130, 131, 132, 134, 135, 137, 138, 141, 150, 153, 156, 158, 161], "none": [6, 40, 127, 161], "setwhen": [6, 31, 37, 41, 112], "clearwhen": [6, 31, 41], "risewhen": 6, "fallwhen": 6, "re": [6, 62, 126, 145], "f": [6, 83, 95, 122, 124], "reginit": [6, 36, 40, 41, 117, 130, 158], "ack": [6, 92], "req": 6, "mind": [6, 113], "regist": [6, 11, 14, 26, 27, 30, 33, 34, 36, 37, 40, 45, 48, 51, 52, 57, 58, 69, 90, 103, 106, 108, 112, 113, 114, 118, 122, 124, 125, 128, 147, 148, 151, 154, 156, 158, 161], "via": [6, 10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 40, 51, 52, 66, 80, 91, 92, 99, 102, 115, 145, 149, 154, 155, 158, 161], "regnext": [6, 11, 20, 22, 30, 33, 40, 48, 49, 58, 80, 130, 138, 154, 161], "delai": [6, 52, 108, 113, 114, 133, 151], "question": [6, 71, 76], "reconfigur": 6, "flip": [6, 31, 113, 114, 154], "flop": [6, 80, 113, 114, 154], "altern": [6, 19, 22, 29, 60, 63, 82, 113, 120, 127, 154, 157, 165], "clk": [6, 30, 51, 58, 112, 116, 121, 123, 129, 153, 154, 158, 161], "seri": 6, "chain": [6, 12, 78, 81, 95, 124, 157], "pin": [6, 26, 33, 40, 80, 91, 92, 95, 102, 113, 116, 153, 154], "inherit": [6, 154], "clockdomain": [6, 7, 11, 28, 40, 47, 52, 58, 80, 92, 93, 94, 108, 113, 114, 123, 131, 135, 137, 138, 148, 151, 152, 153, 154, 161], "combin": [6, 11, 16, 17, 23, 58, 66, 79, 95, 113, 124, 126, 130, 134, 154, 156, 161, 162], "output": [6, 7, 13, 30, 31, 33, 34, 37, 40, 41, 43, 44, 45, 49, 52, 59, 61, 69, 75, 80, 93, 96, 101, 102, 108, 113, 121, 122, 123, 129, 130, 131, 133, 134, 135, 137, 138, 156, 157, 158, 159, 161], "initat": [6, 31], "reset": [6, 31, 33, 40, 41, 46, 51, 58, 59, 69, 78, 81, 83, 92, 96, 110, 112, 114, 116, 121, 123, 124, 128, 132, 133, 135, 137, 139, 152, 154, 157, 158, 161], "rise": [6, 31, 58, 132, 133, 154, 161], "wa": [6, 13, 15, 22, 30, 31, 41, 65, 66, 76, 79, 92, 107, 108, 113, 114, 116, 117, 126, 130, 158], "cycl": [6, 26, 30, 31, 36, 40, 41, 45, 48, 52, 59, 79, 80, 84, 99, 106, 110, 113, 114, 115, 126, 129, 130, 131, 132, 133, 147, 149, 151, 154, 161], "now": [6, 13, 27, 30, 31, 33, 37, 38, 41, 60, 61, 62, 67, 80, 103, 107, 112, 127], "fall": [6, 31, 117, 132, 154, 161], "bundl": [6, 8, 9, 13, 14, 20, 22, 28, 30, 33, 34, 36, 37, 39, 41, 42, 43, 44, 45, 47, 48, 49, 51, 58, 59, 64, 66, 69, 80, 85, 86, 87, 88, 91, 94, 97, 99, 101, 102, 108, 109, 110, 112, 113, 121, 122, 123, 124, 130, 131, 134, 138, 153, 154, 155, 156, 157, 159, 161, 163], "toggl": [6, 112, 113, 132, 133, 135, 158], "booledg": 6, "everi": [6, 11, 27, 28, 40, 52, 58, 66, 113, 126, 130, 155], "edgebundl": 6, "mask": [6, 28, 36, 37, 114, 129], "own": [6, 33, 51, 75, 76, 79, 92, 94, 129, 144, 149, 155], "maskedliter": 6, "model": [7, 26, 31, 61, 75, 97, 99, 105, 116, 126, 133, 135, 137, 144, 149, 159], "structur": [7, 26, 27, 28, 31, 39, 58, 59, 69, 75, 165], "buse": [7, 31, 57, 75, 118], "interfac": [7, 28, 32, 36, 39, 41, 51, 57, 72, 75, 79, 80, 83, 84, 86, 91, 93, 96, 99, 103, 108, 112, 113, 124, 127, 142, 143, 148, 153, 155], "mybundl": [7, 130], "bundleitem0": 7, "anytyp": 7, "bundleitem1": 7, "bundleitemn": 7, "hold": [7, 40], "color": [7, 31, 39, 46, 48, 51, 58, 63, 64, 98, 99, 156, 161], "channelwidth": [7, 31, 44, 59, 113], "r": [7, 22, 34, 37, 41, 44, 48, 59, 63, 64, 66, 79, 87, 97, 112, 130, 156, 161], "apb3": [7, 34, 37, 46, 51, 58, 78, 81, 82, 89, 96, 106, 112, 116, 130], "definit": [7, 11, 15, 16, 17, 20, 22, 23, 24, 31, 36, 39, 46, 51, 57, 59, 63, 67, 69, 75, 80, 90, 94, 99, 107, 110, 111, 116, 122, 123, 129, 131, 144, 153, 154, 157], "among": 7, "condition": [7, 116, 127, 161], "unless": [7, 158], "datawidth": [7, 26, 31, 34, 37, 42, 51, 58, 80, 85, 86, 87, 88, 92, 93, 116, 155], "demonstr": [7, 31, 32, 37, 159], "color1": 7, "color2": 7, "thu": [7, 159], "occupi": 7, "assignfrombit": [7, 8, 26, 31, 33], "view": [7, 60, 122], "hi": [7, 31, 93, 161], "lo": [7, 31], "boundari": [7, 92, 102], "commondatabu": 7, "circular": 7, "buffer": [7, 41, 64, 102, 113, 133, 139, 140], "3rd": 7, "parti": [7, 40, 51, 52, 129], "memori": [7, 26, 30, 32, 36, 48, 51, 62, 66, 74, 80, 84, 92, 93, 103, 106, 107, 108, 113, 115, 116, 123, 128, 142, 143, 149, 151], "format": [7, 31, 60, 123, 130, 131, 144, 149, 162, 165], "testbundl": 7, "addrwr": 7, "datain": [7, 154], "addrrd": 7, "dataout": [7, 154], "mm": 7, "ram3rdparty_1w_1r": 7, "g_data_width": 7, "g_addr_width": 7, "g_vendor": 7, "intel_arria10_m20k": 7, "clk_in": 7, "readclockwir": [7, 154], "clk_out": 7, "addr_wr": 7, "addr_rd": 7, "insid": [7, 13, 31, 37, 40, 58, 59, 62, 63, 64, 66, 91, 99, 110, 113, 118, 126, 127, 132, 145, 154, 155, 156, 158, 161, 163], "go": [7, 30, 33, 50, 60, 69, 75, 92], "obei": [7, 18, 124, 163], "topologi": [7, 79], "imasterslav": [7, 31, 33, 40, 41, 42, 51, 58, 85, 86, 87, 91, 99, 101, 102, 116, 155, 156], "trait": [7, 26, 33, 41, 110, 112], "Then": [7, 26, 31, 33, 34, 37, 41, 42, 44, 49, 51, 58, 59, 63, 66, 67, 69, 76, 80, 84, 92, 101, 106, 118, 122, 129, 131, 145], "asmast": [7, 31, 33, 40, 41, 42, 51, 85, 87, 91, 99, 101, 102, 116, 156], "perspect": [7, 79, 113, 126, 163], "toxxx": 7, "tostream": [7, 34, 40], "flow": [7, 26, 34, 36, 40, 51, 60, 91, 95, 106, 109, 111, 113, 129, 130, 144, 151, 159], "fromxxx": 7, "handshak": [7, 51, 58, 79, 88, 113, 117], "payloadwidth": [7, 156, 161], "readi": [7, 26, 36, 38, 40, 41, 51, 58, 60, 113, 116, 117, 135, 137, 153, 157, 158], "payload": [7, 26, 34, 36, 40, 41, 51, 58, 106, 108, 109, 113, 122, 135, 137, 157, 158], "overrid": [7, 10, 22, 26, 30, 31, 33, 40, 41, 42, 51, 63, 85, 87, 91, 99, 101, 102, 116, 122, 131, 155, 156, 158], "enumer": [8, 28, 31, 40, 110, 123], "object": [8, 11, 26, 30, 31, 33, 34, 36, 40, 42, 43, 50, 51, 52, 58, 66, 67, 75, 79, 80, 85, 86, 87, 88, 91, 92, 93, 94, 95, 108, 113, 119, 120, 123, 126, 129, 130, 131, 134, 135, 137, 138, 148, 149, 151, 153, 155, 158, 159, 161], "element0": 8, "element1": 8, "elementn": 8, "newel": [8, 31, 33, 40, 119], "nativ": [8, 31, 58, 83, 110, 116, 149, 151, 159], "vhdl": [8, 14, 18, 31, 37, 40, 43, 47, 50, 60, 66, 68, 78, 110, 116, 118, 124, 126, 127, 129, 130, 133, 141, 144, 149, 150, 152, 156, 157, 159, 163, 165], "forc": [8, 58, 92, 112, 158], "defaultencod": [8, 31], "encodingofyourchoic": [8, 31], "myenum": 8, "system": [8, 31, 37, 38, 40, 41, 58, 60, 74, 75, 78, 81, 105, 107, 129, 140, 142, 143, 149, 153, 158], "binarysequenti": [8, 40], "statecount": [8, 31, 48, 114], "binaryonehot": [8, 31, 110], "graysequenti": [8, 110], "grai": [8, 11, 46, 114, 123, 154, 157], "myenumstat": 8, "e0": 8, "e1": 8, "e2": 8, "e3": 8, "spinalenumencod": [8, 110], "staticencod": 8, "dynamicencod": 8, "myenumdynam": 8, "uartctrltxstat": [8, 31, 40], "sidl": [8, 31], "sstart": [8, 31], "sdata": [8, 31], "spariti": [8, 31], "sstop": [8, 31], "statenext": [8, 31, 33], "visibl": [8, 31, 41, 64, 80, 148], "enum": [8, 9, 28, 39, 59, 110, 119, 123], "spinalenumel": [8, 148], "spinalenumcraft": [8, 148], "sub": [9, 30, 58, 63, 80], "mul": [9, 30, 79, 82, 84, 115], "float": [9, 48, 52, 63, 156, 161], "bitvector": [9, 28, 30, 114, 122, 124, 148, 161], "contain": [9, 15, 26, 30, 31, 33, 38, 40, 49, 50, 59, 60, 63, 69, 95, 102, 106, 107, 110, 116, 122, 123, 127, 129, 130, 142, 143, 145, 153, 161, 164], "hole": [9, 31], "bitmask": [9, 31], "show": [9, 27, 31, 33, 36, 38, 40, 42, 58, 60, 62, 67, 73, 75, 82, 107, 124, 129, 130, 158], "achiev": [9, 76, 159], "itmatch": [9, 31], "complet": [10, 40, 49, 60, 62, 75, 79, 92, 103, 110, 112, 113, 122, 131], "eras": 10, "toplevel": [10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 30, 46, 52, 59, 78, 79, 81, 82, 94, 95, 107, 110, 116, 117, 119, 123, 129, 131, 132, 148, 153, 154, 155], "42": [10, 12, 16, 17, 18, 19, 23, 58, 59, 63, 66, 101, 102, 127, 130, 148, 150], "66": 10, "throw": [10, 11, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 129], "file": [10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 27, 50, 60, 61, 62, 63, 66, 67, 75, 76, 83, 84, 96, 112, 123, 131, 144, 145, 146, 153, 158, 159, 161], "locat": [10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 60, 92, 131], "stack": [10, 11, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 74, 120, 154, 161], "trace": [10, 11, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 144], "But": [10, 15, 31, 37, 41, 51, 52, 58, 62, 64, 69, 76, 92, 110, 113, 127, 158, 161], "realli": [10, 15, 33, 51, 58, 72, 102, 126], "allowoverrid": 10, "depend": [11, 33, 58, 60, 62, 69, 79, 107, 113, 130, 142, 149, 153, 154, 159], "path": [11, 27, 30, 58, 61, 80, 84, 95, 108, 113, 114, 124, 131, 144, 145], "synchron": [11, 40, 41, 47, 107, 113, 114, 126, 128, 136, 154, 161], "domain": [11, 33, 40, 47, 57, 69, 75, 78, 81, 94, 113, 114, 118, 126, 130, 135, 153, 157], "clka": [11, 135, 153, 154], "extern": [11, 30, 37, 47, 48, 61, 92, 93, 112, 135, 141, 144, 155, 157], "clkb": [11, 135, 153, 154], "rega": [11, 30], "reg": [11, 20, 23, 26, 27, 33, 36, 37, 38, 40, 41, 45, 47, 49, 51, 52, 58, 59, 64, 66, 69, 75, 80, 106, 108, 110, 112, 123, 124, 126, 130, 131, 148, 152, 154, 158, 161], "playdev": [11, 12], "834": [11, 12], "regb": [11, 30], "835": 11, "tmp": [11, 13, 21, 22, 95, 127, 131, 158, 161], "838": 11, "declar": [11, 15, 20, 21, 22, 28, 57, 63, 64, 75, 123, 124, 125, 130, 153, 155, 161, 163], "commun": [11, 61, 76, 109, 142, 143, 149], "alright": 11, "panic": 11, "specif": [11, 19, 21, 28, 32, 33, 39, 46, 47, 62, 75, 87, 91, 92, 93, 94, 112, 129, 144, 153, 154, 155, 158, 161, 162], "addtag": [11, 94, 153, 154, 161], "exchang": 11, "safe": [11, 14, 51, 87, 113], "region": [11, 51, 58], "multi": [11, 38, 74, 144, 149, 154], "risk": 11, "corrupt": 11, "receiv": [11, 38, 40, 91, 92, 109], "asynchron": [11, 43, 47, 107, 114, 123, 129, 135, 136, 138, 154, 161], "detail": [11, 30, 64, 102, 130, 165], "asyncfifo": 11, "poptopushgrai": 11, "ptrwidth": 11, "pushtopopgrai": 11, "pushcc": 11, "clockingarea": [11, 47, 58, 80, 130, 152, 154, 161], "pushclock": [11, 113, 135], "pushptr": 11, "counter": [11, 30, 37, 40, 41, 46, 47, 49, 51, 52, 58, 59, 61, 64, 66, 69, 80, 110, 112, 123, 126, 131, 148, 152, 153, 154, 158, 161], "pushptrgrai": 11, "tograi": [11, 114], "valuenext": [11, 114], "init": [11, 14, 37, 38, 40, 41, 45, 47, 49, 51, 52, 58, 59, 60, 69, 80, 109, 110, 112, 123, 124, 129, 130, 131, 138, 148, 154, 161], "popptrgrai": 11, "isful": 11, "popcc": 11, "popclock": [11, 113, 135], "popptr": 11, "empti": [11, 30, 92, 107, 121], "isempti": 11, "line": [12, 31, 41, 58, 62, 64, 67, 75, 76, 84, 95, 107, 110, 123, 127, 146, 158, 161, 163], "831": 12, "832": 12, "said": [12, 79, 122, 126], "detect": [12, 14, 58, 112, 124, 131, 155, 163], "pessimist": 12, "give": [12, 31, 40, 41, 51, 59, 75, 76, 80, 112, 123, 129, 131, 155, 156, 161], "disabl": [12, 30, 52, 66, 84, 88, 126, 154, 159, 161], "nocombloopcheck": 12, "tool": [12, 26, 29, 30, 34, 37, 51, 58, 60, 62, 72, 75, 76, 78, 81, 94, 95, 102, 106, 107, 110, 111, 114, 116, 118, 122, 129, 141, 149, 161], "veril": [12, 60, 75, 131, 133, 141, 146, 158], "unhappi": 12, "never": [13, 51, 62, 64, 79, 117, 126, 131, 132], "outsid": [13, 21, 58, 63, 64, 66, 101, 102, 113, 154, 161], "current": [13, 26, 30, 33, 40, 41, 52, 62, 79, 92, 93, 94, 102, 106, 107, 109, 110, 111, 112, 113, 114, 120, 123, 129, 133, 141, 151, 153, 154], "directionless": [13, 15], "inout": [13, 15, 102], "child": [13, 20, 155], "io": [13, 14, 20, 22, 30, 31, 33, 34, 37, 38, 39, 40, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 69, 78, 81, 91, 92, 93, 94, 99, 101, 102, 108, 110, 112, 113, 116, 121, 122, 123, 124, 127, 129, 130, 131, 132, 134, 135, 137, 138, 142, 148, 150, 152, 154, 155, 156, 157, 158, 161, 163, 165], "attempt": 13, "io_a": [13, 15, 16, 20], "isn": [13, 20, 21, 22, 51, 84, 92, 107, 158, 163], "sure": [14, 61, 79, 135, 144, 145, 149, 154], "synthesi": [14, 16, 30, 51, 75, 79, 84, 102, 116, 129, 161], "broken": 14, "non": [14, 16, 27, 33, 34, 82, 113, 149, 155], "exhaust": [14, 16], "overlap": [14, 124], "clock": [14, 30, 31, 33, 34, 40, 45, 47, 57, 69, 75, 78, 79, 81, 91, 92, 93, 94, 110, 111, 112, 113, 114, 118, 121, 123, 126, 130, 131, 133, 136, 138, 149, 157], "cross": [14, 58, 65, 75, 111, 113, 135, 157], "hierarchi": [14, 30, 52, 66, 69, 75, 116, 121, 123, 157], "violat": [14, 66], "combinatori": [14, 16, 43, 51, 58, 75, 80, 84, 113, 125, 161], "loop": [14, 43, 51, 58, 66, 75, 125, 126, 133, 159], "latch": [14, 52, 58, 69, 75, 124, 127], "undriven": 14, "unreach": [14, 127], "On": [14, 40, 78, 81, 82, 102, 113, 131, 149, 154], "report": [14, 18, 30, 71, 95, 107, 117, 124, 127, 131, 153, 155], "accur": [14, 149], "look": [14, 33, 62, 114, 127, 129, 158, 159], "overkil": [14, 152, 161], "glanc": [14, 66], "invalu": 14, "soon": 14, "start": [14, 26, 27, 37, 40, 41, 51, 52, 60, 62, 64, 69, 75, 113, 114, 122, 126, 144, 153, 158, 165], "move": [14, 84, 129], "awai": [14, 155, 161], "tradit": [14, 50, 58, 113, 130], "introduct": [14, 27, 28, 32, 39, 46, 57, 78, 81, 157, 165], "crossclockdomain": [14, 154, 161], "setsynchronouswith": 14, "buffercc": [14, 40, 80, 114, 154], "driver": [14, 41, 42, 92, 93, 102, 108, 109, 113, 116], "nullpointerexcept": 14, "explan": [14, 41, 82, 163], "except": [14, 18, 64, 102, 112, 115], "clone": [14, 60, 64, 76, 113, 142, 145], "unassign": [14, 127], "oper": [14, 19, 26, 28, 30, 44, 51, 59, 66, 89, 92, 95, 124, 126, 129, 154, 158, 161], "kind": [15, 30, 36, 41, 50, 51, 58, 64, 66, 76, 80, 102, 107, 110, 122, 129, 152, 159, 161], "meta": [15, 21, 50, 57, 75, 82], "reason": [15, 16, 20, 22, 63, 64, 79, 116, 126, 129, 155, 156, 158, 161], "allowdirectionlessio": [15, 30], "word": [16, 26, 30, 33, 52, 80, 88, 92, 106, 120, 122, 126, 129], "often": [16, 30, 58, 63, 65, 108, 112, 113, 127, 140, 159], "muxlist": [16, 127], "ad": [16, 30, 40, 51, 58, 69, 80, 96, 116, 127, 129, 142, 144, 145, 146, 153, 158], "solut": [16, 22, 50, 51, 66, 76, 79, 80, 158], "muxlistdc": [16, 127], "those": [16, 26, 30, 31, 51, 58, 72, 73, 80, 95, 97, 116, 133, 154, 158, 159], "seq": [16, 37, 103, 113, 114, 119, 122], "impact": [17, 23, 88, 126, 130], "NO": 17, "ON": [17, 95], "runtim": [18, 30, 40, 62, 107, 126, 131], "happen": [18, 22, 26, 80, 92, 106, 117, 126, 133, 161, 163], "befor": [18, 33, 40, 41, 60, 64, 67, 95, 107, 110, 113, 122, 129, 144, 149, 150, 163], "been": [18, 23, 30, 41, 110, 129], "thread": [18, 38, 120, 132, 133, 135, 137, 144, 149], "main": [18, 30, 36, 37, 50, 58, 60, 61, 78, 79, 81, 94, 107, 112, 123, 129, 131, 134, 135, 137, 138, 148, 153, 154, 155, 161], "java": [18, 60, 63, 66, 75, 140, 142, 143, 145], "lang": 18, "librari": [18, 27, 28, 58, 60, 66, 72, 80, 85, 86, 87, 91, 92, 93, 108, 116, 118, 142, 143, 144, 155, 159, 161, 163, 165], "null": [18, 21, 30, 31, 40, 42, 51, 58, 80, 86, 117, 123, 144, 154, 159, 163], "comparison": [19, 28, 57], "wider": [19, 124], "OF": 19, "operand": [19, 25, 51, 134, 138], "101010": [19, 148], "against": [19, 76, 135, 137], "parametr": [19, 31, 80, 157], "known": [19, 129, 130, 154], "whitelist": 19, "allowoutofrangeliter": 19, "whole": [19, 30, 31, 66, 84, 92, 154, 159, 161], "spinalconfig": [19, 30, 40, 52, 123, 129, 131, 154], "behind": [20, 63, 65, 126, 149], "surpris": 20, "tri": [20, 102, 116, 129], "desir": [20, 154], "unregist": 20, "bodi": [20, 30, 107, 150], "AS": 20, "done": [20, 26, 30, 31, 33, 38, 41, 43, 51, 59, 62, 66, 76, 80, 102, 107, 110, 113, 114, 127, 130, 131, 144, 145, 150, 154, 158], "easi": [21, 58, 75, 79, 80, 112, 122, 141, 156], "trigger": [21, 69, 92, 112], "trick": [21, 51], "var": [21, 43, 44, 63, 124, 134, 138, 139, 161], "cloneof": [22, 30, 51, 58, 66, 122], "nearli": 22, "retriev": [22, 66, 113, 154], "itself": [22, 26, 29, 40, 41, 58, 76, 80, 92, 113, 126, 130, 158], "rgb": [22, 28, 39, 46, 51, 59, 64, 98, 99, 113, 129, 157], "stream": [22, 26, 34, 36, 38, 39, 41, 51, 58, 64, 79, 80, 87, 91, 99, 109, 111, 121, 158], "capabl": [22, 65, 75, 82, 88, 93, 106, 141, 149, 159], "tester": [22, 29, 158], "playdevmessag": 22, "solv": [22, 38, 107, 159], "arg": [22, 30, 50, 63, 66, 79, 94, 103, 113, 123, 129, 134, 135, 137, 138, 148, 153, 154, 155, 161], "Or": [22, 31, 50, 52, 79, 110, 123, 148, 161], "self": [22, 158], "xlen": [22, 120], "memoryaddress": 22, "xlenconfig": 22, "address": [22, 26, 34, 36, 37, 42, 48, 52, 75, 79, 80, 84, 85, 86, 88, 90, 106, 112, 129, 161], "debugmemori": 22, "config": [22, 27, 30, 31, 34, 40, 42, 51, 58, 60, 80, 85, 86, 87, 90, 91, 97, 114, 144, 154, 155, 159, 161], "inputaddress": 22, "someaddress": 22, "exept": 22, "debug": [22, 29, 58, 67, 78, 79, 80, 82, 83, 112, 115, 119, 123, 144, 155, 158, 161], "propag": [22, 93, 130, 134, 158], "eventu": 22, "scopeproperti": [22, 159], "somethingels": 23, "ask": [23, 26, 34, 80, 114, 130, 145], "transform": [23, 30, 34, 62, 75, 116, 128], "allowunsetregtoavoidlatch": 23, "reachabl": 24, "duplic": [24, 58, 127, 152, 164], "document": [26, 28, 30, 31, 34, 37, 51, 64, 70, 80, 82, 84, 95, 102, 106, 111, 113, 129, 151, 155, 161, 164, 165], "variant": [26, 30], "abstract": [26, 33, 37, 51, 58, 75, 76, 102, 106, 107, 116, 118, 129, 130, 149], "busdatawidth": [26, 106, 112], "bitoffset": [26, 106], "respons": [26, 85, 88, 92, 106], "write": [26, 32, 34, 36, 37, 40, 41, 48, 51, 52, 58, 59, 63, 66, 75, 79, 87, 88, 91, 92, 101, 102, 106, 108, 112, 113, 116, 128, 130, 133, 141, 150, 156, 161], "onwrit": [26, 106], "dothat": [26, 106], "transact": [26, 36, 38, 79, 87, 92, 99, 106, 108, 109, 113, 135, 137], "onread": [26, 106], "nonstopwrit": [26, 106], "perman": [26, 106], "util": [26, 30, 31, 37, 79, 118, 132, 134, 138, 158], "readandwrit": [26, 106], "writabl": [26, 34, 106], "readmultiword": [26, 106], "writemultiword": [26, 106], "createwriteonli": [26, 106], "createreadwrit": [26, 106], "createanddriveflow": [26, 34, 106], "driveandread": [26, 34, 37, 106], "driveflow": [26, 106], "emit": [26, 91, 106, 123, 154, 159, 161], "readstreamnonblock": [26, 34, 106], "validbitoffset": [26, 34, 106], "payloadbitoffset": [26, 34, 106], "consum": [26, 106, 113], "dobitsaccumulationandclearonread": [26, 106], "intern": [26, 28, 31, 41, 47, 48, 51, 57, 66, 91, 92, 93, 102, 106, 110, 113, 114, 122, 133, 138, 156, 157, 161], "primit": [26, 133, 154], "busslavefactoryel": 26, "datamodel": [26, 28], "hashmap": [26, 30], "link": [26, 30, 80, 92, 149], "end": [26, 33, 40, 41, 47, 51, 58, 91, 112, 113, 114, 116, 123, 129, 131, 133, 153, 154, 158], "callback": [26, 33, 133, 147, 151, 158], "let": [26, 27, 31, 33, 36, 37, 38, 40, 41, 44, 47, 48, 49, 51, 61, 62, 66, 67, 68, 92, 113, 132], "area": [26, 27, 33, 36, 37, 40, 41, 47, 52, 58, 64, 66, 79, 80, 82, 84, 87, 88, 95, 99, 113, 118, 129, 157, 159, 165], "magic": 26, "wordcount": [26, 52, 129, 153, 161], "valuebit": 26, "id": [26, 60, 75, 79, 80, 92, 113], "wordid": 26, "datawrapp": 26, "answer": [26, 92, 108], "busslavefactoryread": 26, "request": [26, 36, 71, 79, 88, 91, 92, 108, 113, 114], "busslavefactorywrit": 26, "busslavefactoryonwrit": 26, "busslavefactoryonread": 26, "constantli": 26, "busslavefactorynonstopwrit": 26, "arraybuff": 26, "elementsperaddress": 26, "mutabl": [26, 30, 135, 137], "privat": [26, 112, 153], "addaddressableel": 26, "getorelseupd": [26, 30], "build": [26, 28, 33, 52, 60, 62, 66, 67, 76, 80, 105, 114, 118, 142, 143, 145, 146, 155, 157, 159, 161], "addprepoptask": [26, 33, 153], "companion": [26, 40, 88, 159], "compat": [26, 30, 79, 93, 114, 129], "avalonmm": [26, 89, 96], "configur": [26, 31, 34, 39, 42, 51, 58, 60, 64, 66, 78, 80, 81, 84, 89, 91, 92, 93, 95, 103, 112, 123, 127, 129, 132, 142, 145, 146, 155, 157, 159], "tabl": [26, 31, 34, 49, 126, 129], "produc": [26, 30, 38, 58, 107, 110, 123, 126, 133, 158], "addresswidth": [26, 31, 34, 37, 42, 51, 58, 80, 85, 86, 87, 88, 92, 93, 155], "byte": [26, 40, 42, 80, 85, 86, 88, 92, 105, 122, 129, 139], "granular": [26, 85, 86], "writedata": [26, 80, 112, 129], "readdatavalid": [26, 88], "respond": [26, 92], "command": [26, 34, 60, 62, 76, 83, 88, 95, 107, 123, 133, 145, 149], "readdata": [26, 129], "getavalonconfig": 26, "avalonmmconfig": [26, 88], "pipelin": [26, 30, 38, 79, 80, 84, 88, 115, 123], "avalon": [26, 84, 88, 94, 106, 111], "usebyteen": [26, 88], "usewaitrequestn": [26, 88], "appli": [26, 33, 38, 40, 52, 58, 64, 74, 104, 108, 110, 113, 114, 120, 122, 126, 131, 133, 153, 154, 156, 158, 161], "readatcmd": 26, "readatrsp": 26, "stage": [26, 30, 34, 40, 75, 79, 80, 84, 108, 113, 114, 115, 154, 161], "job": [26, 33], "That": [26, 51, 52, 65], "apb3slavefactori": [26, 34, 37, 106], "apb3uartctrl": [26, 34, 51, 80], "variat": [26, 60, 79, 89, 106], "probabl": [26, 31, 37, 51, 58, 60, 154, 161, 163], "appropri": 27, "opt": 27, "resampl": 27, "variou": [27, 66, 112], "strictli": [27, 126, 130, 159], "clariti": 27, "sake": 27, "highli": 27, "encourag": 27, "recurs": [27, 30], "tree": [27, 30, 92, 93], "folder": [27, 60, 67, 84, 95, 131, 145], "rst": 27, "tell": 27, "sphinx": 27, "smart": [27, 58, 75], "deduc": 27, "alphanumer": 27, "charact": 27, "consist": [27, 80], "progress": [27, 30, 62, 92, 113, 164], "over": [27, 30, 37, 40, 92, 102, 110, 113, 116, 118, 126, 129, 130, 149, 151, 159, 165], "underlin": 27, "paragraph": 27, "subparagraph": 27, "sphinxcontrib": 27, "plugin": [27, 28, 58, 60, 61, 80, 83, 158, 159], "wavejson": 27, "pclk": 27, "wave": [27, 49, 60, 131, 144, 149, 158], "p": [27, 58, 92, 93, 122], "nclk": 27, "clk0": 27, "phnlphnl": 27, "clk1": 27, "xhlhlhl": 27, "clk2": 27, "hphplnln": 27, "clk3": 27, "nhnhplpl": 27, "clk4": 27, "xlh": 27, "l": [27, 119], "hx": 27, "pdf": [27, 53, 55, 56, 73, 74, 112, 165], "export": [27, 144, 145], "relax": [27, 79], "json": [27, 112], "dialect": 27, "long": [27, 62, 131, 135, 137, 148, 157], "stori": 27, "short": [27, 30, 73, 76, 80, 85, 86, 87, 130], "javascript": 27, "kei": [27, 30, 33, 60, 64], "eg": [27, 75, 103], "stuff": [27, 30, 47, 51, 52, 80, 107, 116, 158], "lane": 27, "suggest": [27, 60, 62, 75, 79, 111, 152], "chees": 27, "toctre": 27, "glob": 27, "includ": [27, 51, 58, 64, 112, 122, 129, 131, 145, 154, 159, 164], "remain": 27, "rel": 27, "prepend": [27, 144], "alphabet": 27, "cheddar": 27, "stilton": 27, "etc": [27, 60, 75, 108, 113], "welcom": [27, 64, 165], "maxdepth": 27, "titlesonli": 27, "semant": [27, 51, 58, 69, 124, 126, 165], "sequenti": [27, 107, 113, 124, 138, 165], "legaci": [27, 69, 165], "up": [27, 37, 40, 41, 52, 59, 60, 67, 80, 92, 93, 114, 131, 133, 145, 153, 158], "bu": [28, 31, 32, 34, 36, 37, 39, 42, 51, 58, 69, 75, 78, 79, 81, 85, 86, 87, 88, 90, 92, 93, 94, 98, 103, 107, 108, 109, 111, 112, 113, 116, 124, 157, 159], "slave": [28, 31, 33, 34, 37, 38, 40, 41, 42, 51, 52, 58, 80, 85, 87, 91, 94, 99, 107, 108, 112, 113, 116, 121, 155, 156, 158], "busslavefactori": [28, 37, 58, 99, 103, 106], "busslavefactorydelai": 28, "avalonmmslavefactori": 28, "conclus": 28, "hack": 28, "titl": [28, 112], "convent": [28, 33, 63, 122, 155], "wavedrom": 28, "integr": [28, 31, 37, 41, 58, 75, 79, 80, 84, 107, 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[91, "uart"]], "Data structures": [[40, "data-structures"], [41, "data-structures"]], "Controller construction parameters": [[40, "controller-construction-parameters"]], "UART interface": [[40, "uart-interface"]], "UART configuration enums": [[40, "uart-configuration-enums"]], "UartCtrl configuration Bundles": [[40, "uartctrl-configuration-bundles"]], "UartCtrlTx": [[40, "uartctrltx"]], "UartCtrlRx": [[40, "uartctrlrx"]], "UartCtrl": [[40, "uartctrl"], [91, "uartctrl"]], "Simple usage": [[40, "simple-usage"]], "Example with test bench": [[40, "example-with-test-bench"]], "Bonus: Having fun with Stream": [[40, "bonus-having-fun-with-stream"]], "VGA": [[41, "vga"], [99, "vga"]], "RGB color": [[41, "rgb-color"]], "VGA bus": [[41, "vga-bus"], [99, "vga-bus"]], "VGA timings": [[41, "vga-timings"], [99, "vga-timings"]], "VGA Controller": [[41, "vga-controller"]], "Component and io definition": [[41, "component-and-io-definition"]], "Horizontal and vertical logic": [[41, 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"event-driven-paradigm-doesn-t-make-any-sense-for-rtl"]], "Recent revisions of VHDL and Verilog aren\u2019t usable": [[51, "recent-revisions-of-vhdl-and-verilog-aren-t-usable"]], "VHDL records, Verilog struct are broken (SystemVerilog is good on this, if you can use it)": [[51, "vhdl-records-verilog-struct-are-broken-systemverilog-is-good-on-this-if-you-can-use-it"]], "VHDL and Verilog are so verbose": [[51, "vhdl-and-verilog-are-so-verbose"]], "Meta Hardware Description capabilities": [[51, "meta-hardware-description-capabilities"]], "Formal verification": [[52, "formal-verification"]], "General": [[52, "general"], [122, "general"]], "Formal backend": [[52, "formal-backend"]], "Installing requirements": [[52, "installing-requirements"]], "External assertions": [[52, "external-assertions"]], "Internal assertions": [[52, "internal-assertions"]], "External stimulus": [[52, "external-stimulus"]], "More assertions / past": [[52, "more-assertions-past"]], "Assuming memory content": [[52, "assuming-memory-content"]], "Utilities and primitives": [[52, "utilities-and-primitives"]], "Assertions / clock / reset": [[52, "assertions-clock-reset"]], "Specifying the initial value of a signal": [[52, "specifying-the-initial-value-of-a-signal"]], "Specifying a initial assumption": [[52, "specifying-a-initial-assumption"]], "Memory content (Mem)": [[52, "memory-content-mem"]], "Specifying assertion in the reset scope": [[52, "specifying-assertion-in-the-reset-scope"]], "Formal primitives": [[52, "formal-primitives"]], "Limitations": [[52, "limitations"]], "Naming polices": [[52, "naming-polices"]], "For Component": [[52, "for-component"]], "For interfaces implement IMasterSlave": [[52, "for-interfaces-implement-imasterslave"]], "Core": [[53, "core"]], "Cheatsheets": [[54, "cheatsheets"]], "Lib": [[55, "lib"]], "Symbolic": [[56, "symbolic"]], "Help for VHDL people": [[57, "help-for-vhdl-people"]], "VHDL comparison": [[58, "vhdl-comparison"]], "Process": [[58, "process"]], "Implicit vs explicit definitions": [[58, "implicit-vs-explicit-definitions"]], "Clock domains": [[58, "clock-domains"], [132, "clock-domains"], [154, "clock-domains"]], "Component\u2019s internal organization": [[58, "component-s-internal-organization"]], "Safety": [[58, "safety"]], "Functions and procedures": [[58, "functions-and-procedures"]], "Buses and Interfaces": [[58, "buses-and-interfaces"]], "Signal declaration": [[58, "signal-declaration"]], "Component instantiation": [[58, "component-instantiation"]], "Casting": [[58, "casting"]], "Resizing": [[58, "resizing"]], "Parameterization": [[58, "parameterization"]], "Meta hardware description": [[58, "meta-hardware-description"]], "VHDL equivalences": [[59, "vhdl-equivalences"]], "Entity and architecture": [[59, "entity-and-architecture"]], "Signal": [[59, "signal"]], "Literals": [[59, "literals"]], "Registers": [[59, "registers"], [92, "registers"], [130, "registers"]], "Process blocks": [[59, "process-blocks"]], "Install and setup": [[60, "install-and-setup"]], "Mandatory requirements": [[60, "mandatory-requirements"]], "Installing SBT in an internet-free environment": [[60, "installing-sbt-in-an-internet-free-environment"]], "Recommended requirements": [[60, "recommended-requirements"]], "Create a SpinalHDL project": [[60, "create-a-spinalhdl-project"]], "The directory structure of a project": [[60, "the-directory-structure-of-a-project"]], "Using Spinal on SpinalHDL code": [[60, "using-spinal-on-spinalhdl-code"]], "Using Spinal from IntelliJ IDEA": [[61, "using-spinal-from-intellij-idea"]], "Using Spinal from CLI with SBT": [[62, "using-spinal-from-cli-with-sbt"]], "Basics": [[63, "basics"]], "Variables": [[63, "variables"]], "Functions": [[63, "functions"], [108, "functions"], [109, "functions"], [113, "functions"]], "Return": [[63, "return"]], "Return type inferation": [[63, "return-type-inferation"]], "Curly braces": [[63, "curly-braces"]], "Function that returns nothing": [[63, "function-that-returns-nothing"]], "Argument default values": [[63, "argument-default-values"]], "Apply": [[63, "apply"]], "Object": [[63, "object"]], "Entry point (main)": [[63, "entry-point-main"]], "Class": [[63, "class"]], "Inheritance": [[63, "inheritance"]], "Case class": [[63, "case-class"]], "Templates / Type parameterization": [[63, "templates-type-parameterization"]], "Coding conventions": [[64, "coding-conventions"]], "class vs case class": [[64, "class-vs-case-class"]], "[case] class": [[64, "case-class"]], "companion object": [[64, "companion-object"]], "function": [[64, "function"]], "instances": [[64, "instances"]], "if / when": [[64, "if-when"]], "switch": [[64, "switch"]], "Parameters": [[64, "parameters"]], "Scala Guide": [[65, "scala-guide"]], "Scala guide": [[65, "id1"]], "Interaction": [[66, "interaction"]], "How SpinalHDL works behind the API": [[66, "how-spinalhdl-works-behind-the-api"]], "Everything is a reference": [[66, "everything-is-a-reference"]], "Hardware types": [[66, "hardware-types"]], "RGB example": [[66, "rgb-example"]], "Names of signals in the generated RTL": [[66, "names-of-signals-in-the-generated-rtl"]], "Scala is for elaboration, SpinalHDL for hardware description": [[66, "scala-is-for-elaboration-spinalhdl-for-hardware-description"]], "Scala elaboration capabilities (if, for, functional programming)": [[66, "scala-elaboration-capabilities-if-for-functional-programming"]], "Using Spinal from VSCodium": [[67, "using-spinal-from-vscodium"]], "Getting Started": [[68, "getting-started"]], "A simple example": [[69, "a-simple-example"]], "Component": [[69, "component"]], "Ports": [[69, "ports"]], "Internal logic": [[69, "internal-logic"]], "Contributing": [[70, "contributing"]], "Getting in touch": [[71, "getting-in-touch"]], "License": [[72, "license"]], "Other learning materials": [[73, "other-learning-materials"]], "Projects using SpinalHDL": [[74, "projects-using-spinalhdl"]], "Repositories": [[74, "repositories"]], "Companies": [[74, "companies"]], "Universities": [[74, "universities"]], "About SpinalHDL": [[75, "about-spinalhdl"]], "What is SpinalHDL?": [[75, "what-is-spinalhdl"]], "What SpinalHDL is not": [[75, "what-spinalhdl-is-not"]], "The Spinal development flow": [[75, "the-spinal-development-flow"]], "Advantages of using SpinalHDL over VHDL / Verilog": [[75, "advantages-of-using-spinalhdl-over-vhdl-verilog"]], "FAQ": [[76, "faq"]], "What is the overhead of SpinalHDL generated RTL compared to human written VHDL/Verilog?": [[76, "what-is-the-overhead-of-spinalhdl-generated-rtl-compared-to-human-written-vhdl-verilog"]], "What if SpinalHDL becomes unsupported in the future?": [[76, "what-if-spinalhdl-becomes-unsupported-in-the-future"]], "Does SpinalHDL keep comments in generated VHDL/verilog?": [[76, "does-spinalhdl-keep-comments-in-generated-vhdl-verilog"]], "Could SpinalHDL scale up to big projects?": [[76, "could-spinalhdl-scale-up-to-big-projects"]], "How SpinalHDL came to be": [[76, "how-spinalhdl-came-to-be"]], "Why develop a new language when there is VHDL/Verilog/SystemVerilog?": [[76, "why-develop-a-new-language-when-there-is-vhdl-verilog-systemverilog"]], "How to use an unreleased version of SpinalHDL (but committed on git)?": [[76, "how-to-use-an-unreleased-version-of-spinalhdl-but-committed-on-git"]], "Legacy": [[78, "legacy"]], "Hardware": [[79, "hardware"]], "RISCV": [[79, "riscv"]], "AXI4": [[79, "axi4"]], "APB3": [[79, "apb3"]], "Generate the RTL": [[79, "generate-the-rtl"]], "SoC toplevel (Pinsec)": [[80, "soc-toplevel-pinsec"]], "Defining all IO": [[80, "defining-all-io"]], "Clock and resets": [[80, "clock-and-resets"]], "Reset controller": [[80, "reset-controller"]], "Clock domain setup for each system": [[80, "clock-domain-setup-for-each-system"]], "Main components": [[80, "main-components"]], "RISCV CPU": [[80, "riscv-cpu"]], "On chip RAM": [[80, "on-chip-ram"]], "SDRAM controller": [[80, "sdram-controller"]], "JTAG controller": [[80, "jtag-controller"]], "Peripherals": [[80, "peripherals"]], "GPIO": [[80, "gpio"]], "UART controller": [[80, "uart-controller"]], "VGA controller": [[80, "vga-controller"], [99, "vga-controller"]], "Bus interconnects": [[80, "bus-interconnects"]], "AXI4 to APB3 bridge": [[80, "axi4-to-apb3-bridge"]], "AXI4 crossbar": [[80, "axi4-crossbar"]], "APB3 decoder": [[80, "apb3-decoder"]], "pinsec": [[81, "pinsec"]], "Board support": [[82, "board-support"]], "Software": [[83, "software"]], "RISCV tool-chain": [[83, "riscv-tool-chain"]], "OpenOCD/GDB/Eclipse configuration": [[83, "openocd-gdb-eclipse-configuration"]], "RiscV": [[84, "riscv"]], "Features": [[84, "features"]], "Base FPGA project": [[84, "base-fpga-project"]], "How to generate the CPU VHDL": [[84, "how-to-generate-the-cpu-vhdl"]], "How to debug": [[84, "how-to-debug"]], "Todo": [[84, "todo"]], "AHB-Lite3": [[85, "ahb-lite3"]], "Configuration and instanciation": [[85, "configuration-and-instanciation"], [86, "configuration-and-instanciation"], [87, "configuration-and-instanciation"], [88, "configuration-and-instanciation"]], "Variations": [[85, "variations"], [87, "variations"]], "Apb3": [[86, "apb3"]], "Functions and operators": [[86, "functions-and-operators"], [87, "functions-and-operators"]], "Axi4": [[87, "axi4"]], "AvalonMM": [[88, "avalonmm"]], "Bus": [[89, "bus"]], "Com": [[90, "com"]], "Bus definition": [[91, "bus-definition"]], "USB device": [[92, "usb-device"]], "Architecture": [[92, "architecture"]], "FRAME (0xFF00)": [[92, "frame-0xff00"]], "ADDRESS (0xFF04)": [[92, "address-0xff04"]], "INTERRUPT (0xFF08)": [[92, "interrupt-0xff08"]], "HALT (0xFF0C)": [[92, "halt-0xff0c"]], "CONFIG (0xFF10)": [[92, "config-0xff10"]], "INFO (0xFF20)": [[92, "info-0xff20"]], "ENDPOINTS (0x0000 - 0x003F)": [[92, "endpoints-0x0000-0x003f"]], "SETUP_DATA (0x0040 - 0x0047)": [[92, "setup-data-0x0040-0x0047"]], "Descriptors": [[92, "descriptors"]], "USB OHCI": [[93, "usb-ohci"]], "QSysify": [[94, "qsysify"]], "tags": [[94, "tags"]], "AvalonMM / APB3": [[94, "avalonmm-apb3"]], "Interrupt input": [[94, "interrupt-input"]], "Reset output": [[94, "reset-output"]], "Adding new interface support": [[94, "adding-new-interface-support"]], "QuartusFlow": [[95, "quartusflow"]], "For a single rtl file": [[95, "for-a-single-rtl-file"]], "Tip": [[95, "tip"]], "For an existing project": [[95, "for-an-existing-project"]], "EDA": [[96, "eda"]], "Colors": [[97, "colors"]], "RGB": [[97, "rgb"]], "Graphics": [[98, "graphics"]], "IO": [[100, "io"]], "ReadableOpenDrain": [[101, "readableopendrain"]], "TriState": [[102, "tristate"], [102, "id1"]], "TriStateArray": [[102, "tristatearray"]], "Plic Mapper": [[103, "plic-mapper"]], "PlicMapper.apply": [[103, "plicmapper-apply"]], "PlicMapping.sifive": [[103, "plicmapping-sifive"]], "PlicMapping.light": [[103, "plicmapping-light"]], "BinarySystem": [[105, "binarysystem"]], "String to Int/Long/BigInt": [[105, "string-to-int-long-bigint"]], "Int/Long/BigInt to String": [[105, "int-long-bigint-to-string"]], "Int/Long/BigInt to Binary-List": [[105, "int-long-bigint-to-binary-list"]], "Binary-List to Int/Long/BigInt": [[105, "binary-list-to-int-long-bigint"]], "BigInt enricher": [[105, "bigint-enricher"]], "Bus Slave Factory": [[106, "bus-slave-factory"]], "Functionality": [[106, "functionality"]], "Fiber framework": [[107, "fiber-framework"]], "Simple dummy example": [[107, "simple-dummy-example"]], "Handle[T]": [[107, "handle-t"]], "soon(handle)": [[107, "soon-handle"]], "Flow": [[108, "flow"]], "Code example": [[108, "code-example"]], "Simulation Support": [[108, "simulation-support"]], "Fragment": [[109, "fragment"]], "State machine": [[110, "state-machine"]], "StateMachine": [[110, "statemachine"]], "Entry point": [[110, "entry-point"]], "Transitions": [[110, "transitions"]], "State encoding": [[110, "state-encoding"]], "States": [[110, "states"]], "StateDelay": [[110, "statedelay"]], "StateFsm": [[110, "statefsm"]], "StateParallelFsm": [[110, "stateparallelfsm"]], "Notes about the entry state": [[110, "notes-about-the-entry-state"]], "Libraries": [[111, "libraries"]], "RegIf": [[112, "regif"]], "Automatic allocation": [[112, "automatic-allocation"]], "28 Access Types": [[112, "access-types"]], "Automatic documentation generation": [[112, "automatic-documentation-generation"]], "Special Access Usage": [[112, "special-access-usage"]], "Byte Mask": [[112, "byte-mask"]], "Typical Example": [[112, "typical-example"]], "Interrupt Factory": [[112, "interrupt-factory"]], "IP level interrupt Factory": [[112, "ip-level-interrupt-factory"]], "SYS level interrupt merge": [[112, "sys-level-interrupt-merge"]], "Spinal Factory": [[112, "spinal-factory"]], "DefaultReadValue": [[112, "defaultreadvalue"]], "Developers Area": [[112, "developers-area"]], "Stream": [[113, "stream"]], "Semantics": [[113, "semantics"]], "Utils": [[113, "utils"], [114, "utils"], [122, "utils"], [161, "utils"]], "StreamFifo": [[113, "streamfifo"]], "StreamFifoCC": [[113, "streamfifocc"]], "StreamCCByToggle": [[113, "streamccbytoggle"]], "StreamWidthAdapter": [[113, "streamwidthadapter"]], "StreamArbiter": [[113, "streamarbiter"]], "StreamJoin": [[113, "streamjoin"]], "StreamFork": [[113, "streamfork"]], "StreamMux": [[113, "streammux"]], "StreamDemux": [[113, "streamdemux"]], "StreamDispatcherSequencial": [[113, "streamdispatchersequencial"]], "StreamTransactionExtender": [[113, "streamtransactionextender"]], "Simulation support": [[113, "simulation-support"]], "State less utilities": [[114, "state-less-utilities"]], "State full utilities": [[114, "state-full-utilities"]], "Counter": [[114, "counter"]], "Timeout": [[114, "timeout"]], "ResetCtrl": [[114, "resetctrl"]], "asyncAssertSyncDeassert": [[114, "asyncassertsyncdeassert"]], "Special utilities": [[114, "special-utilities"]], "VexRiscv (RV32IM CPU)": [[115, "vexriscv-rv32im-cpu"]], "Analog and inout": [[116, "analog-and-inout"]], "Analog": [[116, "analog"]], "inout": [[116, "inout"]], "InOutWrapper": [[116, "inoutwrapper"]], "Manually driving Analog bundles": [[116, "manually-driving-analog-bundles"]], "Assertions": [[117, "assertions"]], "Other language features": [[118, "other-language-features"]], "Report": [[119, "report"]], "ScopeProperty": [[120, "scopeproperty"]], "Stub": [[121, "stub"]], "Cat": [[122, "cat"]], "Cloning hardware datatypes": [[122, "cloning-hardware-datatypes"]], "Passing a datatype as construction parameter": [[122, "passing-a-datatype-as-construction-parameter"]], "The old way": [[122, "the-old-way"]], "The safe way": [[122, "the-safe-way"]], "Frequency and time": [[122, "frequency-and-time"]], "Binary prefix": [[122, "binary-prefix"]], "VHDL and Verilog generation": [[123, "vhdl-and-verilog-generation"]], "Generate VHDL and Verilog from a SpinalHDL Component": [[123, "generate-vhdl-and-verilog-from-a-spinalhdl-component"]], "Parametrization from Scala": [[123, "parametrization-from-scala"]], "Parametrization from shell": [[123, "parametrization-from-shell"]], "Generated VHDL and Verilog": [[123, "generated-vhdl-and-verilog"]], "Organization": [[123, "organization"]], "Combinational logic": [[123, "combinational-logic"]], "Sequential logic": [[123, "sequential-logic"], [128, "sequential-logic"]], "VHDL and Verilog attributes": [[123, "vhdl-and-verilog-attributes"]], "Width checking": [[124, "width-checking"]], "Combinatorial loops": [[124, "combinatorial-loops"]], "Semantic": [[125, "semantic"]], "Rules": [[126, "rules"]], "Concurrency": [[126, "concurrency"]], "Last valid assignment wins": [[126, "last-valid-assignment-wins"]], "Signal and register interactions with Scala (OOP reference + Functions)": [[126, "signal-and-register-interactions-with-scala-oop-reference-functions"]], "When/Switch/Mux": [[127, "when-switch-mux"]], "When": [[127, "when"]], "Switch": [[127, "switch"]], "Additional options": [[127, "additional-options"]], "Local declaration": [[127, "local-declaration"]], "Mux": [[127, "mux"]], "Bitwise selection": [[127, "bitwise-selection"]], "RAM/ROM": [[129, "ram-rom"]], "Synchronous enable quirk": [[129, "synchronous-enable-quirk"]], "Read-under-write policy": [[129, "read-under-write-policy"]], "Mixed-width ram": [[129, "mixed-width-ram"]], "Automatic blackboxing": [[129, "automatic-blackboxing"]], "Blackboxing policy": [[129, "blackboxing-policy"]], "Standard memory blackboxes": [[129, "standard-memory-blackboxes"]], "Instantiation": [[130, "instantiation"], [154, "instantiation"]], "Reset value": [[130, "reset-value"]], "Initialization value for simulation purposes": [[130, "initialization-value-for-simulation-purposes"]], "Register vectors": [[130, "register-vectors"]], "Transforming a wire into a register": [[130, "transforming-a-wire-into-a-register"]], "Boot a simulation": [[131, "boot-a-simulation"]], "Configuration": [[131, "configuration"], [154, "configuration"]], "Running multiple tests on the same hardware": [[131, "running-multiple-tests-on-the-same-hardware"]], "Throw Success or Failure of the simulation from a thread": [[131, "throw-success-or-failure-of-the-simulation-from-a-thread"]], "Stimulus API": [[132, "stimulus-api"]], "Wait API": [[132, "wait-api"]], "Callback API": [[132, "callback-api"]], "Default ClockDomain": [[132, "default-clockdomain"]], "New ClockDomain": [[132, "new-clockdomain"]], "Simulation engine": [[133, "simulation-engine"]], "Asynchronous adder": [[134, "asynchronous-adder"]], "Dual clock fifo": [[135, "dual-clock-fifo"]], "Single clock fifo": [[137, "single-clock-fifo"]], "Synchronous adder": [[138, "synchronous-adder"]], "Uart decoder": [[139, "uart-decoder"]], "Uart encoder": [[140, "uart-encoder"]], "Simulation": [[141, "simulation"]], "Setup and installation of GHDL": [[142, "setup-and-installation-of-ghdl"]], "Linux": [[142, "linux"], [143, "linux"], [145, "linux"]], "Setup and installation of Icarus Verilog": [[143, "setup-and-installation-of-icarus-verilog"]], "VCS Simulation Configuration": [[144, "vcs-simulation-configuration"]], "Environment variable": [[144, "environment-variable"]], "User defined environment setup": [[144, "user-defined-environment-setup"]], "VCS Flags": [[144, "vcs-flags"]], "Waveform generation": [[144, "waveform-generation"]], "Simulation with Blackbox": [[144, "simulation-with-blackbox"]], "Setup and installation of Verilator": [[145, "setup-and-installation-of-verilator"]], "Scala": [[145, "scala"], [146, "scala"]], "Windows": [[145, "windows"]], "From the MinGW package manager": [[145, "from-the-mingw-package-manager"]], "From source": [[145, "from-source"]], "Installation instructions": [[146, "installation-instructions"]], "Backend-dependent installation instructions": [[146, "backend-dependent-installation-instructions"]], "Sensitive API": [[147, "sensitive-api"]], "Accessing signals of the simulation": [[148, "accessing-signals-of-the-simulation"]], "Read and write signals": [[148, "read-and-write-signals"]], "Accessing signals inside the component\u2019s hierarchy": [[148, "accessing-signals-inside-the-component-s-hierarchy"]], "Simulator specific details": [[149, "simulator-specific-details"]], "How SpinalHDL simulates the hardware with Verilator backend": [[149, "how-spinalhdl-simulates-the-hardware-with-verilator-backend"]], "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend": [[149, "how-spinalhdl-simulates-the-hardware-with-ghdl-icarus-verilog-backend"]], "How SpinalHDL simulates the hardware with Synopsys VCS backend": [[149, "how-spinalhdl-simulates-the-hardware-with-synopsys-vcs-backend"]], "Performance": [[149, "performance"]], "Thread-full API": [[150, "thread-full-api"]], "Fork and join simulation threads": [[150, "fork-and-join-simulation-threads"]], "Sleep and waitUntil": [[150, "sleep-and-waituntil"]], "Thread-less API": [[151, "thread-less-api"]], "Area": [[152, "area"], [161, "area"]], "Instantiate VHDL and Verilog IP": [[153, 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63, 80, 85, 102, 112, 113, 114, 122, 130, 138, 153, 154, 156, 159, 161], "between": [0, 2, 3, 5, 6, 9, 31, 33, 34, 37, 41, 51, 52, 58, 63, 69, 75, 76, 80, 84, 107, 110, 113, 124, 130, 133, 138, 149, 154, 158, 161], "fraction": [0, 1, 129], "expans": 0, "15": [0, 3, 52, 80, 84, 92, 112], "b": [0, 3, 5, 6, 7, 11, 12, 22, 25, 30, 31, 33, 40, 41, 42, 43, 44, 48, 58, 59, 63, 64, 66, 76, 79, 87, 97, 107, 110, 112, 119, 123, 124, 126, 127, 130, 134, 138, 148, 153, 154, 155, 156, 158, 161, 162, 163], "c": [0, 3, 5, 6, 8, 12, 26, 30, 33, 38, 40, 41, 43, 59, 63, 64, 76, 83, 92, 97, 112, 119, 123, 124, 126, 127, 133, 134, 138, 140, 142, 143, 144, 145, 149, 153, 154, 158, 161], "77": 0, "19": [0, 92], "7": [0, 2, 3, 5, 7, 8, 31, 33, 34, 40, 58, 59, 62, 63, 66, 76, 80, 112, 122, 126, 131, 139, 140, 141, 153, 154, 155, 158, 161], "d": [0, 3, 5, 6, 7, 12, 26, 30, 31, 60, 62, 80, 83, 112, 119, 123, 124, 154, 158], "00": [0, 9, 31], "e": [0, 3, 5, 6, 8, 16, 26, 30, 40, 74, 112, 124, 131], "308": 0, "3125": 0, "616": 0, "38": 0, "50": [0, 80, 122, 154], "11": [0, 1, 3, 62], "without": [0, 3, 5, 28, 31, 33, 38, 40, 51, 60, 62, 63, 84, 109, 113, 118, 127, 130, 135, 141, 145, 153, 154, 158, 159, 161, 162], "aa": 0, "bb": [0, 153], "cc": [0, 92], "9": [0, 3, 24, 36, 92, 112, 114, 115, 123, 124], "31": [0, 3, 5, 30, 34, 58, 92, 97, 112, 116, 121, 123], "It": [0, 2, 6, 7, 11, 12, 29, 31, 33, 34, 38, 40, 41, 51, 58, 59, 60, 62, 63, 64, 66, 67, 69, 75, 80, 87, 88, 92, 93, 94, 102, 103, 107, 108, 109, 110, 112, 113, 116, 118, 119, 120, 121, 122, 124, 126, 127, 129, 130, 131, 145, 149, 152, 153, 154, 158, 161, 165], "doe": [0, 4, 5, 6, 40, 41, 58, 75, 82, 84, 92, 112, 113, 121, 127, 130, 134, 137, 138, 153, 159], "select": [0, 3, 5, 33, 36, 61, 113, 123, 125, 129], "align": [0, 3, 26, 92, 105], "maximum": [0, 1, 3, 5, 40, 95, 149], "minimum": [0, 1, 3, 5, 26, 52], "from": [0, 3, 5, 6, 7, 8, 11, 13, 14, 16, 26, 27, 30, 31, 34, 37, 40, 41, 42, 47, 52, 58, 60, 63, 64, 68, 69, 75, 76, 79, 80, 88, 92, 94, 106, 108, 109, 110, 112, 113, 114, 115, 116, 122, 124, 126, 127, 129, 130, 132, 135, 137, 142, 143, 146, 148, 152, 154, 155, 156, 157, 159, 161, 163, 165], "each": [0, 6, 7, 8, 14, 15, 26, 30, 31, 33, 36, 37, 40, 41, 45, 48, 51, 52, 58, 59, 62, 63, 66, 67, 69, 78, 81, 85, 86, 87, 92, 97, 99, 102, 106, 109, 110, 112, 113, 115, 122, 126, 130, 131, 132, 133, 144, 147, 148, 153, 154, 155, 158, 161, 162], "input": [0, 3, 5, 6, 7, 13, 14, 30, 31, 33, 34, 37, 40, 41, 43, 44, 45, 47, 48, 51, 52, 59, 69, 79, 80, 93, 96, 108, 113, 114, 121, 122, 123, 126, 127, 130, 131, 132, 134, 135, 137, 138, 153, 154, 156, 157, 158, 161], "add": [0, 6, 9, 16, 26, 27, 30, 31, 33, 35, 37, 40, 41, 51, 58, 60, 62, 76, 80, 94, 108, 109, 112, 113, 116, 117, 118, 119, 122, 123, 127, 129, 144, 145, 148, 154, 155, 157, 161], "standard": [0, 2, 31, 75, 79, 112, 116, 123, 124, 128, 130, 132, 141, 159, 161], "A": [0, 1, 2, 3, 4, 6, 7, 10, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 33, 37, 60, 61, 62, 64, 67, 73, 74, 77, 79, 82, 92, 93, 95, 102, 109, 110, 113, 114, 120, 122, 123, 127, 133, 153, 154, 158, 159, 161], "out": [0, 8, 13, 14, 15, 17, 23, 30, 31, 33, 36, 37, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 69, 76, 79, 85, 91, 92, 99, 101, 102, 107, 108, 110, 112, 113, 116, 119, 121, 122, 123, 124, 129, 130, 131, 134, 138, 153, 154, 155, 156, 158, 161, 163, 164], "compil": [0, 11, 14, 28, 34, 52, 58, 62, 63, 72, 76, 83, 95, 108, 113, 118, 126, 131, 134, 135, 137, 138, 142, 144, 145, 148, 149, 153, 154, 158, 161, 163], "time": [0, 3, 6, 8, 10, 27, 30, 31, 36, 39, 40, 43, 51, 58, 62, 66, 67, 69, 76, 79, 80, 85, 86, 87, 88, 95, 98, 105, 113, 114, 117, 126, 127, 130, 131, 132, 133, 134, 138, 145, 150, 151, 153, 154, 157, 158, 161, 163], "optim": [0, 38, 115, 131], "decim": [0, 2, 105], "shift": [0, 1, 2, 3, 5, 30, 31, 84, 114, 115, 122], "left": [0, 1, 3, 5, 6, 19, 25, 30, 31, 51, 124, 126, 127, 161, 165], "right": [0, 1, 3, 5, 6, 19, 25, 30, 31, 41, 51, 60, 61, 62, 66, 67, 75, 124, 161], "zero": [0, 3, 4, 5, 6, 31, 34, 37, 40, 59, 63, 76, 92, 105, 113, 114, 124, 155], "remov": [0, 30, 36, 58, 79, 95, 113, 121, 127, 130, 153, 155], "implement": [0, 7, 28, 30, 31, 32, 33, 39, 41, 46, 49, 50, 51, 58, 61, 74, 75, 76, 79, 80, 82, 91, 92, 94, 106, 110, 113, 115, 116, 123, 126, 129, 149, 154, 158, 161], "common": [0, 3, 7, 63, 75, 105, 129, 141], "method": [0, 3, 7, 11, 58, 64, 79, 110, 112, 114, 122, 124, 130, 144, 155, 158, 159], "work": [0, 3, 33, 58, 67, 76, 79, 93, 112, 113, 144, 145, 154, 161, 164], "an": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 16, 17, 19, 20, 22, 23, 26, 29, 30, 31, 33, 34, 36, 37, 40, 41, 42, 44, 47, 48, 49, 51, 52, 58, 59, 63, 64, 66, 68, 69, 75, 79, 80, 83, 84, 85, 86, 87, 88, 91, 92, 93, 94, 96, 97, 99, 101, 102, 106, 108, 109, 110, 112, 113, 114, 115, 116, 117, 121, 122, 124, 126, 127, 129, 130, 131, 132, 133, 135, 137, 141, 145, 148, 149, 152, 154, 155, 156, 157, 158, 159, 161, 163, 165], "helper": [0, 159], "consid": [0, 31, 76, 84, 92, 111, 124, 131, 154, 164], "63": [0, 3, 5], "sat": [0, 3], "mode": [0, 3, 52, 62, 84, 88, 113, 115, 123, 129, 156], "follow": [0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 30, 31, 37, 40, 41, 42, 47, 50, 51, 52, 58, 60, 61, 63, 64, 65, 72, 79, 80, 82, 85, 86, 87, 93, 94, 97, 99, 101, 102, 103, 106, 109, 110, 111, 113, 115, 116, 117, 118, 119, 121, 122, 123, 126, 129, 130, 131, 133, 134, 138, 144, 145, 146, 153, 154, 155, 158, 159, 161, 162, 163], "requir": [0, 20, 21, 22, 26, 27, 31, 38, 40, 51, 61, 63, 76, 80, 92, 93, 94, 107, 112, 113, 124, 127, 129, 130, 142, 143, 144, 149, 154, 155, 159], "floor": [0, 3], "truncat": [0, 1, 2, 5, 31, 38], "ceil": [0, 3, 122], "floortozero": [0, 3], "ceiltoinf": [0, 3], "roundhalfup": [0, 3], "roundhalfdown": [0, 3], "roundhalftozero": [0, 3], "roundhalftoinf": [0, 3], "roundhalftoeven": [0, 3], "roundhalftoodd": [0, 3], "better": [0, 12, 16, 31, 51, 64, 72, 75, 82, 84, 88, 112, 149, 155, 164], "explain": [0, 31, 33, 51, 58, 63, 64, 69, 133, 157, 158], "here": [0, 2, 3, 9, 26, 30, 33, 34, 36, 37, 40, 41, 42, 47, 49, 50, 52, 58, 59, 60, 61, 66, 69, 76, 80, 82, 84, 88, 92, 93, 94, 105, 112, 113, 122, 126, 129, 130, 131, 148, 154, 155, 158, 159, 161, 164], "wikipedia": [0, 1, 3], "result": [0, 1, 3, 4, 5, 7, 17, 18, 19, 23, 24, 25, 30, 31, 38, 43, 44, 47, 51, 58, 59, 66, 76, 107, 109, 110, 122, 124, 126, 129, 131, 134, 138, 149, 154, 155, 158, 159, 161], "If": [0, 1, 3, 5, 7, 8, 12, 13, 20, 26, 27, 30, 31, 40, 41, 52, 60, 63, 71, 72, 76, 92, 106, 113, 114, 116, 122, 123, 124, 126, 127, 129, 130, 132, 144, 153, 154, 155, 159, 161, 163], "tag": [0, 14, 96, 148, 153, 154, 161], "automat": [0, 3, 5, 16, 41, 51, 60, 62, 63, 95, 102, 107, 124, 128, 154, 158, 161], "check": [0, 4, 5, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 21, 23, 24, 25, 26, 30, 31, 52, 58, 61, 62, 67, 75, 76, 95, 110, 114, 117, 125, 126, 127, 129, 131, 133, 134, 135, 137, 138, 145, 149, 154, 155, 159, 161, 163], "expand": [0, 3, 5, 79], "precis": [0, 2], "dure": [0, 16, 30, 52, 60, 63, 66, 75, 110, 126, 127, 129, 131, 132, 153, 155, 158, 159], "By": [0, 26, 75, 110, 127, 154, 161], "default": [0, 3, 5, 6, 8, 16, 30, 31, 33, 38, 41, 52, 59, 60, 64, 69, 84, 85, 86, 87, 110, 112, 113, 114, 116, 123, 124, 127, 129, 131, 144, 153, 154, 161, 162], "error": [0, 1, 3, 5, 10, 13, 15, 16, 18, 19, 21, 22, 27, 41, 60, 62, 69, 75, 99, 112, 117, 122, 124, 127, 129, 131, 144, 145, 154, 161, 165], "anoth": [0, 2, 16, 26, 31, 33, 51, 66, 67, 75, 106, 110, 113, 126, 127, 154, 155, 158, 161, 164], "smaller": [0, 3, 5, 51, 86, 92, 127], "control": [0, 34, 36, 39, 46, 60, 78, 81, 82, 84, 85, 91, 92, 93, 94, 98, 102, 103, 107, 108, 109, 113, 114, 126, 130, 144, 150, 151, 154, 159], "how": [0, 3, 4, 6, 9, 28, 31, 33, 36, 47, 51, 58, 60, 68, 75, 78, 85, 86, 87, 91, 92, 107, 109, 122, 123, 126, 129, 130, 132, 153, 157, 158, 159], "def": [0, 7, 22, 26, 30, 31, 33, 34, 37, 38, 40, 41, 42, 44, 48, 49, 50, 51, 58, 63, 64, 66, 76, 79, 80, 85, 87, 91, 94, 97, 99, 101, 102, 110, 112, 113, 116, 122, 123, 126, 129, 130, 134, 135, 137, 138, 148, 153, 154, 155, 156, 158, 161], "boolean": [0, 3, 5, 6, 31, 33, 40, 42, 51, 58, 63, 66, 86, 87, 88, 113, 122, 123, 129, 132, 148, 153, 154, 159, 161, 162], "fals": [0, 3, 5, 6, 14, 16, 19, 26, 30, 31, 36, 37, 38, 40, 41, 42, 43, 48, 51, 52, 58, 59, 63, 80, 86, 87, 88, 108, 110, 113, 117, 123, 126, 127, 130, 132, 135, 137, 139, 140, 152, 154, 158, 161], "overflow": [0, 3, 37, 58, 112, 114], "roundtyp": [0, 3], "roundup": [0, 3, 122], "rounddown": [0, 3], "roundtozero": [0, 3], "roundtoinf": [0, 3], "roundtoeven": [0, 3], "roundtoodd": [0, 3], "flag": [0, 69, 92, 114, 124, 146, 159], "logic": [0, 11, 27, 30, 31, 33, 34, 36, 37, 39, 40, 43, 47, 51, 52, 58, 75, 80, 103, 110, 113, 114, 115, 116, 117, 121, 127, 130, 134, 138, 152, 155, 156, 158, 161, 165], "datatyp": [0, 22, 26, 51, 58, 63, 64, 101, 102, 106, 113, 124, 130, 135, 137, 155], "alwai": [0, 3, 22, 27, 40, 51, 52, 64, 76, 92, 110, 112, 113, 114, 126, 129, 130, 141, 145, 150, 154, 156, 158, 161], "when": [0, 1, 3, 5, 6, 7, 8, 10, 11, 16, 18, 20, 21, 22, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 45, 48, 51, 52, 58, 59, 61, 62, 66, 69, 75, 80, 85, 86, 87, 92, 99, 101, 102, 106, 107, 108, 109, 110, 112, 113, 114, 115, 116, 117, 118, 123, 124, 125, 126, 129, 130, 131, 132, 133, 145, 149, 152, 154, 155, 157, 163], "more": [0, 1, 7, 11, 26, 30, 36, 41, 51, 58, 60, 62, 63, 64, 69, 75, 76, 84, 88, 102, 106, 113, 115, 122, 123, 126, 130, 132, 142, 143, 152, 154, 155, 158, 159, 161, 165], "one": [0, 1, 2, 6, 8, 10, 11, 12, 13, 19, 23, 26, 30, 31, 33, 36, 37, 38, 40, 41, 48, 51, 52, 58, 60, 63, 66, 67, 69, 72, 75, 76, 80, 84, 86, 87, 91, 92, 93, 99, 106, 109, 110, 112, 113, 114, 118, 123, 124, 127, 130, 135, 145, 149, 154, 161, 162], "lower": [0, 4, 113, 149, 165], "spinalhdl": [1, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 33, 34, 36, 37, 50, 51, 52, 53, 55, 56, 58, 59, 62, 63, 64, 65, 67, 68, 69, 71, 72, 73, 77, 79, 80, 82, 84, 85, 86, 87, 92, 93, 94, 102, 107, 110, 112, 113, 115, 118, 119, 122, 124, 126, 127, 129, 130, 141, 142, 144, 145, 148, 152, 153, 154, 155, 157, 158, 159, 161, 163, 165], "onli": [1, 2, 3, 5, 6, 8, 11, 14, 15, 26, 27, 30, 31, 33, 36, 40, 51, 52, 58, 60, 63, 64, 69, 79, 80, 82, 84, 85, 87, 88, 92, 106, 109, 110, 112, 113, 114, 116, 122, 126, 127, 129, 130, 132, 145, 149, 153, 154, 155, 158, 161, 162, 163], "partial": [1, 2, 9, 12, 16, 51, 107, 155], "test": [1, 2, 28, 30, 39, 60, 66, 79, 92, 93, 95, 108, 113, 123, 134, 138, 141, 158], "you": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 19, 20, 22, 23, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 41, 47, 49, 50, 52, 58, 59, 60, 61, 62, 63, 64, 66, 67, 69, 71, 72, 75, 76, 79, 80, 83, 84, 85, 86, 87, 92, 94, 95, 97, 101, 102, 106, 107, 109, 110, 111, 112, 113, 114, 116, 117, 118, 119, 121, 122, 123, 126, 127, 129, 130, 131, 132, 141, 144, 145, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 158, 159, 161, 162, 163, 165], "find": [1, 3, 4, 7, 14, 30, 34, 50, 52, 67, 76, 80, 82, 84, 88, 95, 106, 121, 158, 165], "ani": [1, 2, 4, 5, 6, 7, 30, 31, 33, 41, 43, 59, 60, 75, 76, 92, 109, 113, 116, 123, 124, 131, 145, 159], "bug": [1, 2, 71, 76, 111, 145], "think": [1, 2, 33, 51], "some": [1, 2, 3, 5, 12, 19, 21, 23, 26, 27, 30, 31, 33, 36, 37, 38, 40, 41, 43, 47, 51, 52, 58, 61, 63, 64, 66, 73, 76, 79, 80, 82, 87, 88, 92, 93, 94, 102, 103, 107, 110, 111, 112, 113, 114, 116, 117, 120, 122, 123, 126, 129, 130, 132, 133, 134, 138, 144, 145, 149, 151, 152, 154, 155, 156, 158, 159, 161], "miss": [1, 2, 16, 103, 127, 161], "pleas": [1, 2, 84, 95, 112, 116, 123, 154, 159, 164], "github": [1, 2, 30, 36, 52, 53, 55, 56, 60, 76, 80, 83, 84, 92, 93, 103, 111, 115, 123, 129, 142, 165], "issu": [1, 2, 14, 36, 51, 58, 76, 107, 123, 129, 133, 145, 149, 154, 161, 163], "also": [1, 2, 3, 5, 7, 8, 11, 12, 26, 29, 30, 31, 33, 34, 37, 41, 47, 49, 50, 51, 52, 58, 59, 60, 61, 62, 63, 66, 69, 76, 79, 80, 83, 87, 88, 92, 93, 105, 106, 107, 109, 110, 112, 113, 114, 118, 119, 120, 121, 122, 123, 124, 126, 129, 130, 132, 142, 143, 144, 145, 146, 154, 155, 156, 158, 159, 161, 165], "do": [1, 2, 3, 5, 6, 8, 10, 11, 14, 15, 22, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 47, 49, 51, 52, 58, 60, 61, 62, 63, 66, 67, 72, 76, 80, 86, 87, 92, 93, 105, 106, 107, 109, 110, 111, 112, 114, 116, 121, 122, 123, 124, 127, 129, 130, 131, 135, 144, 145, 153, 154, 155, 158, 159, 161, 162], "undocu": [1, 2], "featur": [1, 2, 6, 27, 31, 51, 58, 59, 60, 71, 73, 75, 76, 78, 79, 80, 82, 88, 94, 103, 107, 110, 111, 115, 116, 126, 129, 130, 144, 145, 149, 154, 158, 159, 162, 165], "your": [1, 2, 3, 6, 7, 8, 11, 14, 22, 27, 30, 31, 33, 47, 49, 50, 51, 52, 58, 60, 61, 62, 63, 66, 67, 72, 75, 76, 79, 80, 94, 95, 106, 110, 111, 112, 113, 116, 118, 123, 124, 126, 129, 131, 132, 141, 142, 143, 144, 145, 146, 148, 149, 150, 152, 153, 154, 155, 158, 159, 163], "correspond": [1, 2, 6, 8, 18, 26, 31, 36, 37, 38, 47, 50, 52, 79, 80, 92, 106, 108, 113, 123, 129, 132, 142, 143, 153, 154, 155, 161, 163], "vector": [1, 3, 4, 5, 31, 44, 110, 114, 127, 128], "syntax": [1, 2, 3, 4, 5, 6, 7, 27, 28, 34, 37, 42, 51, 52, 58, 60, 63, 66, 69, 71, 75, 105, 108, 109, 110, 113, 114, 117, 118, 119, 122, 123, 124, 126, 127, 129, 130, 131, 148, 154, 155, 159, 162], "width": [1, 2, 3, 4, 5, 8, 14, 16, 22, 26, 30, 31, 37, 40, 41, 45, 63, 80, 85, 86, 87, 91, 93, 102, 105, 106, 109, 113, 122, 125, 127, 128, 155, 159, 161, 162], "resolut": [1, 38, 41], "max": [1, 3, 5, 30, 31, 40, 62], "min": [1, 3, 26], "peak": [1, 38], "bitcount": [1, 3, 5, 6, 26, 31, 40, 102, 114, 155, 161], "chosen": [1, 149], "usual": [1, 6, 7, 130, 159], "wai": [1, 2, 3, 8, 14, 22, 30, 31, 33, 37, 40, 41, 49, 51, 52, 58, 60, 62, 63, 64, 67, 84, 106, 107, 110, 112, 113, 124, 127, 129, 130, 144, 150, 153, 156, 159, 161], "defin": [1, 2, 4, 7, 8, 9, 13, 14, 15, 16, 17, 21, 23, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 49, 51, 58, 59, 63, 64, 66, 69, 78, 81, 83, 85, 86, 87, 95, 101, 102, 103, 106, 107, 109, 110, 112, 116, 118, 122, 123, 124, 126, 127, 129, 130, 132, 141, 146, 152, 154, 155, 156, 157, 158, 159, 161, 162], "q": [1, 6, 7], "notat": [1, 122], "inform": [1, 7, 26, 31, 61, 65, 69, 75, 80, 84, 88, 94, 109, 112, 115, 117, 122, 143, 155, 159, 164], "found": [1, 2, 29, 30, 33, 41, 61, 67, 76, 164], "page": [1, 11, 26, 27, 30, 33, 47, 58, 64, 65, 82, 84, 102, 122, 133, 158, 163], "about": [1, 2, 3, 7, 11, 26, 27, 30, 33, 40, 41, 51, 58, 59, 65, 71, 76, 77, 83, 106, 107, 108, 118, 122, 126, 127, 129, 143, 159, 161, 163, 165], "q8": 1, "mean": [1, 3, 5, 13, 18, 30, 31, 36, 41, 59, 76, 80, 108, 113, 116, 126, 130, 147, 154, 158, 159, 161, 163], "where": [1, 3, 4, 5, 6, 14, 26, 31, 36, 37, 41, 52, 58, 59, 61, 62, 69, 79, 80, 92, 107, 113, 123, 124, 129, 130, 131, 154, 155, 161], "natur": [1, 33, 51, 58, 76, 88, 102, 116, 124, 154], "part": [1, 3, 5, 31, 40, 41, 151, 159, 161], "being": [1, 2, 6, 7, 16, 31, 52, 80, 113, 116, 124, 126, 130, 154, 165], "smallest": 1, "power": [1, 40, 66, 75, 76, 92, 113, 118, 122, 129, 159, 161, 165], "two": [1, 2, 3, 6, 8, 11, 22, 31, 37, 40, 41, 58, 63, 66, 69, 72, 75, 76, 79, 84, 102, 103, 107, 110, 113, 115, 122, 123, 124, 126, 127, 129, 130, 135, 144, 153, 154, 158, 161], "To": [1, 3, 5, 23, 31, 34, 37, 40, 42, 49, 50, 51, 52, 58, 60, 62, 66, 74, 79, 80, 83, 87, 92, 95, 106, 110, 111, 114, 116, 118, 120, 123, 129, 130, 131, 141, 146, 148, 153, 161], "make": [1, 3, 6, 10, 12, 19, 23, 26, 27, 31, 33, 34, 40, 64, 72, 75, 76, 80, 106, 107, 110, 113, 116, 123, 130, 131, 132, 142, 144, 145, 148, 149, 154], "less": [1, 3, 15, 31, 51, 63, 80, 87, 88, 113, 120, 158, 161], "prone": 1, "numer": [1, 58, 157], "spinal": [1, 2, 4, 7, 8, 9, 14, 29, 30, 31, 33, 36, 40, 47, 50, 52, 68, 72, 79, 80, 92, 93, 95, 105, 107, 108, 110, 111, 113, 114, 116, 118, 122, 123, 124, 129, 130, 131, 134, 135, 137, 138, 145, 146, 148, 154, 155, 158], "core": [1, 8, 30, 31, 33, 36, 47, 50, 52, 54, 58, 72, 74, 79, 80, 84, 92, 93, 103, 105, 107, 108, 113, 114, 118, 122, 123, 131, 134, 135, 137, 138, 145, 146, 148, 149, 159], "constructor": [1, 4, 6, 130, 154, 155, 159, 161], "conveni": [1, 116], "wrapper": [1, 32, 122], "exist": [1, 6, 29, 30, 92, 93, 96, 107, 126, 130, 149, 153, 154, 157, 159, 161], "form": [1, 124, 126], "sampl": [1, 40, 49, 52, 69, 91, 110, 114, 130, 132, 138, 154], "uq_8_2": 1, "10": [1, 3, 4, 5, 9, 30, 31, 41, 52, 58, 62, 63, 80, 93, 105, 108, 112, 113, 114, 122, 124, 129, 131, 132, 135, 137, 138, 140, 148], "q_8_2": 1, "loss": [1, 3], "sourc": [1, 6, 10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 27, 37, 44, 47, 52, 58, 60, 62, 75, 76, 79, 82, 103, 111, 112, 113, 118, 141, 142, 143, 146, 149, 154, 157, 158, 159, 165], "too": [1, 36, 41, 52, 95, 131, 140, 142, 143, 158], "big": [1, 3, 33, 84, 109, 113, 114, 130], "resiz": [1, 3, 5, 6, 25, 26, 31, 57, 124, 129, 161], "match": [1, 4, 5, 26, 30, 36, 76, 92, 108, 112, 113, 124, 134, 135, 137, 138, 158, 161], "destin": [1, 154, 161], "i16_m2": 1, "i16_0": 1, "i8_m2": 1, "o16_m2": 1, "o16_m0": 1, "o14_m2": 1, "14": [1, 63, 92], "ok": [1, 40, 122], "Not": [1, 3], "target": [1, 30, 52, 83, 84, 103, 107, 123, 124, 129], "o18_m2": 1, "18": [1, 92, 112], "o18_22b": 1, "22": [1, 92], "doubl": [1, 2, 30, 40, 63, 153, 154], "signal": [1, 3, 4, 5, 6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 20, 21, 25, 27, 28, 30, 33, 36, 37, 38, 41, 42, 47, 51, 57, 69, 79, 85, 87, 93, 99, 101, 102, 107, 108, 109, 112, 113, 114, 116, 117, 122, 123, 124, 125, 127, 129, 130, 132, 135, 138, 141, 152, 153, 156, 157, 159, 161], "i4_m2": 1, "Will": [1, 19, 30, 36, 63, 66, 107, 116, 122, 158], "load": [1, 36, 40, 75, 80, 82, 83, 107, 108, 130, 149, 154, 159], "read": [1, 3, 5, 7, 11, 13, 26, 31, 32, 34, 36, 37, 40, 49, 51, 52, 58, 69, 79, 88, 91, 92, 101, 102, 103, 106, 109, 112, 113, 114, 116, 124, 128, 131, 140, 141, 154, 155, 156, 161, 163], "written": [1, 5, 37, 64, 75, 82, 110, 116, 122, 129, 130, 148, 159], "properti": [1, 120, 154, 161], "17": [1, 62, 92, 95], "avail": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 62, 69, 80, 82, 84, 99, 103, 108, 113, 122, 140, 142, 143, 155, 165], "return": [1, 2, 3, 4, 5, 6, 7, 8, 26, 30, 31, 33, 37, 38, 51, 52, 58, 66, 86, 87, 88, 92, 105, 106, 107, 108, 109, 110, 112, 113, 114, 122, 123, 127, 129, 131, 132, 147, 154, 155, 156, 158, 159, 161], "amplitud": 1, "x": [1, 2, 3, 4, 5, 6, 7, 8, 31, 38, 52, 58, 86, 87, 107, 108, 109, 113, 114, 119, 122, 124, 126, 127, 129, 130, 155, 161, 162], "y": [1, 3, 4, 5, 6, 7, 8, 31, 38, 58, 86, 87, 107, 108, 112, 113, 114, 122, 124, 126, 127, 161, 162], "equal": [1, 3, 4, 5, 6, 7, 8, 9, 31, 37, 69, 129], "bool": [1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 16, 21, 26, 28, 30, 33, 34, 37, 40, 41, 42, 45, 47, 48, 51, 52, 58, 59, 66, 69, 80, 85, 86, 91, 95, 99, 102, 108, 109, 110, 112, 113, 114, 116, 117, 122, 123, 126, 127, 130, 148, 153, 154, 155, 156, 158, 159, 161, 162, 163], "inequ": [1, 3, 4, 5, 6, 7, 8, 31], "asbit": [1, 2, 3, 4, 5, 6, 7, 8, 26, 31, 33, 37, 112, 124], "binari": [1, 2, 3, 4, 5, 6, 7, 8, 31, 82, 83, 131], "w": [1, 2, 3, 4, 5, 6, 7, 8, 31, 34, 37, 87, 112], "asuint": [1, 3, 5, 6, 8, 31], "uint": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 64, 66, 69, 80, 85, 86, 97, 99, 108, 110, 112, 113, 114, 122, 123, 124, 126, 127, 130, 131, 134, 138, 148, 152, 153, 154, 155, 156, 158, 159, 161, 163], "assint": [1, 3, 5, 6, 8, 31], "sint": [1, 2, 4, 5, 6, 8, 9, 28, 49, 59, 64, 112, 122, 124, 148, 155, 158, 161], "asbool": [1, 2, 3, 5, 31], "arrai": [1, 2, 3, 5, 26, 30, 31, 36, 50, 51, 58, 59, 63, 79, 94, 123, 129, 134, 135, 137, 138, 148, 153, 154, 155, 161], "vec": [1, 2, 3, 5, 9, 12, 28, 36, 44, 58, 59, 66, 95, 112, 113, 114, 130, 158], "touint": [1, 2], "tosint": [1, 2], "toufix": 1, "tosfix": 1, "name": [1, 3, 4, 6, 7, 8, 26, 27, 30, 31, 34, 37, 38, 40, 41, 42, 47, 48, 49, 60, 63, 64, 69, 75, 76, 80, 82, 85, 86, 87, 88, 91, 92, 95, 106, 110, 112, 113, 114, 117, 123, 130, 144, 153, 154, 157], "storabl": 1, "encod": [2, 31, 127, 136], "second": [2, 3, 6, 51, 76, 82, 84, 114, 122, 132, 149, 161], "recfloat": 2, "help": [2, 6, 66, 68, 75, 95, 129, 149, 158, 159], "simplifi": 2, "design": [2, 6, 7, 11, 12, 17, 19, 23, 27, 30, 51, 52, 59, 60, 63, 64, 65, 66, 67, 74, 75, 76, 80, 102, 107, 110, 111, 112, 113, 123, 124, 129, 130, 135, 139, 144, 153, 154, 155, 159, 161, 165], "edg": [2, 58, 132, 133, 135, 154, 161], "case": [2, 3, 7, 10, 12, 16, 19, 22, 23, 26, 27, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 59, 66, 69, 73, 75, 79, 85, 86, 87, 88, 91, 92, 94, 97, 99, 101, 102, 107, 108, 110, 111, 112, 113, 116, 117, 122, 123, 124, 126, 127, 129, 130, 152, 154, 155, 156, 158, 159, 161, 163], "compos": [2, 92, 107], "field": [2, 3, 92, 112], "mantissa": [2, 30], "de": 2, "facto": 2, "import": [2, 4, 6, 8, 27, 30, 31, 33, 36, 38, 40, 47, 50, 52, 61, 66, 67, 79, 92, 93, 105, 107, 108, 110, 111, 112, 113, 118, 123, 124, 126, 127, 129, 131, 134, 135, 137, 138, 145, 146, 148, 155, 158, 161], "lib": [2, 30, 31, 36, 40, 47, 50, 54, 72, 79, 80, 92, 93, 95, 105, 108, 110, 111, 112, 113, 118, 122, 144, 154, 155, 158, 161], "experiment": [2, 9, 141], "math": [2, 3, 26, 40, 49, 64], "_": [2, 4, 5, 8, 26, 27, 30, 31, 33, 36, 38, 40, 47, 50, 52, 66, 79, 92, 93, 105, 107, 108, 110, 111, 112, 113, 118, 123, 130, 131, 134, 135, 137, 138, 145, 146, 148, 154, 155, 158, 161], "sinc": [2, 36, 69, 76, 119, 130, 138, 141, 149, 158], "ha": [2, 3, 6, 9, 18, 20, 23, 30, 31, 36, 37, 40, 42, 51, 52, 58, 59, 62, 66, 69, 74, 75, 76, 79, 80, 82, 85, 86, 87, 88, 91, 92, 95, 110, 113, 114, 120, 122, 126, 127, 129, 130, 138, 142, 143, 149, 153, 154, 155, 158, 165], "quirk": [2, 128], "special": [2, 3, 9, 27, 63, 102, 124, 149, 152, 157], "berkelei": 2, "propos": [2, 158], "modifi": [2, 3, 5, 28, 60, 80, 92, 113, 123], "so": [2, 3, 12, 18, 20, 27, 30, 33, 36, 37, 40, 49, 52, 60, 62, 69, 72, 73, 75, 92, 93, 107, 110, 113, 126, 130, 131, 149, 154, 155, 158, 159, 164], "treat": 2, "same": [2, 3, 5, 6, 7, 11, 18, 25, 27, 31, 34, 36, 41, 58, 63, 64, 66, 67, 69, 75, 76, 88, 102, 107, 112, 113, 120, 122, 123, 124, 126, 127, 129, 130, 132, 153, 154, 155, 158, 159, 162, 163], "ones": [2, 3, 4, 5, 59, 64, 65, 66, 76, 80, 155], "kept": 2, "unchang": [2, 3], "three": [2, 6, 31, 37, 41, 50, 63, 80, 123, 126, 144, 161], "lead": 2, "set": [2, 3, 5, 6, 7, 8, 31, 33, 34, 36, 37, 40, 41, 51, 52, 60, 63, 65, 66, 69, 76, 80, 91, 92, 95, 101, 102, 107, 108, 112, 113, 114, 115, 116, 120, 122, 123, 124, 126, 129, 130, 131, 132, 139, 148, 154, 159, 161, 162], "first": [2, 3, 4, 6, 7, 14, 26, 27, 31, 33, 34, 36, 41, 44, 49, 52, 62, 66, 69, 76, 80, 82, 84, 85, 86, 87, 105, 109, 110, 112, 113, 114, 121, 122, 123, 135, 145, 148, 149, 158], "becom": [2, 14, 41, 92, 110, 113, 122], "implicit": [2, 22, 57, 69, 110, 114, 120, 132], "107": 2, "plu": [2, 69], "index": [2, 3, 4, 5, 8, 27, 31, 36, 58, 63, 113, 114, 122, 127], "highest": [2, 3, 5, 122], "exactli": [2, 122, 123, 126, 154], "origin": [2, 3, 5, 30, 116, 124], "130": 2, "don": [2, 3, 5, 6, 9, 11, 31, 33, 41, 51, 58, 59, 63, 64, 67, 72, 75, 88, 108, 112, 113, 129, 130, 145, 155, 156, 158, 161], "t": [2, 3, 4, 5, 6, 9, 11, 13, 14, 20, 21, 26, 30, 31, 33, 41, 52, 58, 59, 63, 64, 65, 66, 67, 72, 75, 76, 79, 84, 88, 92, 101, 102, 106, 108, 109, 112, 113, 114, 116, 122, 124, 126, 127, 129, 130, 132, 145, 154, 155, 156, 158, 161, 162], "care": [2, 5, 6, 9, 41, 63, 76, 108, 113, 126, 127, 129, 149, 154], "6": [2, 3, 5, 19, 24, 27, 30, 31, 33, 58, 59, 63, 66, 80, 84, 92, 97, 112, 122, 130], "rest": [2, 80, 103, 124], "exponents": 2, "mantissas": 2, "floating16": 2, "half": 2, "floating32": 2, "singl": [2, 4, 6, 7, 11, 30, 31, 37, 40, 58, 60, 64, 75, 79, 84, 92, 96, 110, 113, 114, 115, 122, 123, 124, 129, 136, 149, 154, 159], "floating64": 2, "floating128": 2, "quad": 2, "recfloating16": 2, "recfloating32": 2, "recfloating64": 2, "recfloating128": 2, "fromuint": 2, "fromsint": 2, "interpret": [3, 5, 33, 42, 63], "complement": 3, "thei": [3, 5, 6, 7, 14, 21, 26, 50, 51, 58, 73, 92, 102, 105, 107, 122, 123, 126, 127, 155, 158], "everyth": [3, 5, 6, 51, 58, 63, 72, 77, 107, 156, 159, 161], "option": [3, 5, 6, 19, 42, 51, 52, 58, 62, 67, 84, 103, 113, 115, 123, 125, 129, 130, 142, 145, 157, 161], "descript": [3, 5, 14, 15, 18, 21, 26, 27, 31, 33, 34, 37, 38, 40, 41, 48, 49, 50, 52, 57, 60, 63, 69, 72, 75, 80, 82, 85, 86, 87, 88, 91, 92, 95, 105, 106, 108, 109, 110, 112, 113, 114, 116, 117, 122, 123, 124, 127, 129, 130, 131, 132, 144, 147, 148, 151, 154, 155, 157, 159, 161, 162, 163], "count": [3, 4, 5, 31, 36, 37, 38, 40, 41, 52, 59, 113, 124, 127, 154, 158], "infer": [3, 5, 16, 31, 58, 59, 75, 87, 102, 122, 124, 129, 130, 154, 161], "assign": [3, 4, 5, 6, 8, 12, 13, 14, 16, 17, 18, 21, 22, 23, 26, 28, 38, 40, 43, 57, 58, 63, 66, 69, 102, 106, 108, 114, 121, 125, 127, 130, 144, 148, 154, 156, 157, 158, 162], "base": [3, 5, 6, 9, 26, 30, 31, 32, 34, 37, 40, 41, 51, 75, 78, 80, 110, 113, 114, 120, 122, 124, 126, 145, 153, 157, 159], "h": [3, 5, 31, 41, 99, 145], "o": [3, 5, 31, 102, 123, 158], "element": [3, 4, 5, 8, 22, 26, 30, 31, 34, 37, 38, 40, 51, 75, 88, 113, 114, 122, 123, 126, 127, 129, 130, 145, 154, 155, 158, 159, 161], "specifi": [3, 5, 7, 11, 14, 26, 27, 28, 30, 31, 37, 38, 41, 58, 59, 61, 63, 76, 80, 86, 87, 91, 92, 94, 95, 97, 107, 109, 113, 122, 123, 126, 127, 129, 130, 131, 132, 153, 154, 163], "myuint": [3, 31, 59], "0000_0101": [3, 31], "per": [3, 26, 31, 40, 42, 113, 132, 149, 154], "h1a": [3, 31], "could": [3, 5, 7, 10, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 31, 33, 40, 42, 49, 50, 51, 52, 64, 66, 79, 80, 82, 83, 84, 86, 88, 91, 97, 99, 108, 109, 111, 113, 114, 115, 116, 117, 126, 145, 149, 154, 159, 161, 162, 163, 164], "scala": [3, 4, 5, 6, 11, 12, 18, 30, 31, 34, 36, 37, 42, 50, 58, 60, 61, 62, 63, 64, 67, 68, 75, 76, 80, 107, 108, 112, 117, 120, 122, 124, 125, 130, 134, 135, 137, 138, 141, 148, 149, 155, 156, 157, 159, 161, 163], "liter": [3, 19, 28, 57, 63, 66, 118, 124, 129], "mybool": [3, 4, 5, 6, 7, 31, 59], "downto": [3, 5, 26, 31, 34, 51, 58, 59, 106, 112, 116, 123, 127, 153, 162], "purpos": [3, 5, 18, 31, 33, 37, 51, 72, 75, 102, 128, 133, 154, 158, 163, 165], "omit": [3, 5, 31, 159], "11111111": [3, 5, 31], "10000000": [3, 5, 31], "00011110": [3, 31], "bitwis": [3, 5, 31, 125], "NOT": [3, 5, 6, 31], "AND": [3, 5, 6, 31], "OR": [3, 5, 6, 25, 31, 127, 153, 158], "xor": [3, 5, 6, 31], "xorr": [3, 5, 31], "reduct": [3, 158], "orr": [3, 5, 31, 36, 37, 158], "andr": [3, 5, 31], "rotateleft": [3, 5, 31], "rotat": [3, 5, 31], "constrain": [3, 51], "log2up": [3, 8, 31, 38, 40, 49, 88, 113, 122, 127, 153, 161], "rotateright": [3, 5], "clearal": [3, 5, 31], "clear": [3, 5, 6, 26, 31, 37, 44, 46, 48, 58, 59, 92, 106, 112, 114, 126, 132, 135], "setal": [3, 5, 31], "setallto": [3, 5, 31], "given": [3, 4, 5, 6, 8, 30, 31, 33, 36, 50, 51, 63, 66, 76, 80, 84, 92, 103, 107, 108, 109, 110, 113, 122, 123, 124, 127, 129, 130, 132, 133, 141, 148, 152, 154, 158, 159, 161], "notic": [3, 122, 130], "behaviour": [3, 31, 36, 51, 126, 154, 158, 161], "narrow": [3, 124], "keep": [3, 5, 30, 36, 37, 41, 52, 69, 80, 92, 113, 114, 116, 121, 123, 130], "due": [3, 14, 31, 58, 76, 126, 130, 149], "In": [3, 5, 6, 7, 8, 9, 13, 16, 19, 20, 22, 23, 30, 32, 40, 41, 52, 58, 59, 60, 61, 63, 67, 68, 69, 75, 76, 79, 80, 94, 102, 105, 106, 107, 110, 112, 113, 117, 120, 123, 126, 129, 130, 132, 143, 144, 145, 150, 152, 153, 154, 157, 161], "seen": [3, 6, 159], "constant": [3, 5, 6, 9, 14, 31, 63, 66, 159], "invers": [3, 5], "assert": [3, 26, 40, 41, 80, 113, 114, 131, 134, 135, 137, 138, 139, 154], "getwidth": [3, 5, 26, 31, 41, 64, 97], "arithshift": 3, "logicshift": 3, "carri": [3, 6, 41, 46, 58, 64, 102, 109, 113, 161], "addend": 3, "satur": 3, "see": [3, 7, 11, 31, 33, 40, 41, 50, 51, 60, 67, 69, 92, 94, 102, 103, 106, 109, 110, 122, 124, 126, 129, 130, 142, 155, 159], "subtrahend": 3, "unari": 3, "One": [3, 31, 33, 37, 40, 42, 66, 80, 82, 84, 93, 117, 118, 158], "compliment": 3, "xf0": 3, "x0f": 3, "xff": [3, 5], "x0ff": 3, "0xf0": 3, "0x20": [3, 158], "would": [3, 6, 40, 41, 51, 52, 67, 69, 109, 114, 124, 130, 159], "therefor": [3, 6, 112, 116, 123, 131, 141, 142, 149], "x20": 3, "simul": [3, 14, 27, 33, 51, 59, 60, 62, 75, 76, 79, 110, 117, 119, 127, 128, 132, 134, 135, 137, 138, 139, 140, 145, 146, 147, 151, 153, 154, 161, 165], "made": [3, 126], "oppos": 3, "previou": [3, 10, 30, 34, 63, 69, 126], "elsewhen": [3, 40, 59, 64, 127, 161], "01": [3, 5], "otherwis": [3, 38, 40, 58, 59, 64, 127, 132, 159, 161], "compar": [3, 4, 7, 9, 19, 31, 52, 62, 108, 113, 120, 149, 158], "wraparound": 3, "behavior": [3, 124, 126, 127], "wrap": [3, 84, 116, 124, 126], "around": [3, 27, 31, 76, 77, 122, 149, 155], "exce": 3, "variabl": [3, 5, 18, 43, 58, 66, 88, 120, 131, 145, 146, 152, 153, 159], "sens": [3, 10, 19, 23, 64], "lsb": [3, 5, 6, 7, 31, 33, 114, 122, 124], "data": [3, 4, 5, 7, 8, 26, 27, 28, 30, 33, 34, 38, 39, 48, 51, 52, 57, 58, 64, 66, 74, 75, 84, 85, 91, 92, 93, 101, 102, 106, 108, 113, 115, 116, 122, 127, 129, 130, 135, 137, 148, 153, 154, 155, 156, 158, 159, 161, 165], "intosint": 3, "convert": [3, 6, 34, 48, 111, 114, 118, 122, 124, 149, 156, 159, 161], "twocompl": 3, "en": [3, 52, 129, 153, 161], "gener": [3, 6, 7, 14, 16, 18, 23, 28, 31, 33, 37, 39, 40, 41, 49, 50, 51, 58, 59, 60, 61, 62, 63, 64, 67, 68, 72, 75, 78, 80, 81, 82, 92, 94, 95, 103, 107, 109, 110, 113, 116, 119, 121, 126, 127, 129, 131, 132, 138, 141, 142, 143, 146, 149, 156, 157, 158, 159, 163, 165], "neg": 3, "mysint": [3, 5, 6], "ab": [3, 59], "absolut": [3, 27], "just": [3, 26, 33, 34, 49, 62, 67, 69, 75, 80, 116, 122, 123, 127, 130, 144, 153, 158], "reinterpret": 3, "abswithsym": 3, "symmetr": 3, "shrink": 3, "someth": [3, 5, 6, 10, 17, 23, 30, 34, 51, 63, 64, 66, 107, 116, 126, 130, 154, 158], "thing": [3, 26, 27, 30, 31, 33, 34, 37, 40, 47, 49, 51, 52, 58, 60, 62, 66, 75, 92, 102, 105, 107, 109, 111, 116, 120, 122, 124, 127, 130, 155, 158, 161], "mybit": [3, 5, 6, 7, 8, 9, 31], "myvec": [3, 5], "convers": [3, 75, 113, 124], "uint_30": 3, "30": [3, 122], "sint_30": 3, "booleandoinvert": 3, "we": [3, 5, 6, 7, 13, 22, 27, 33, 34, 36, 37, 40, 41, 42, 51, 52, 60, 62, 68, 80, 107, 112, 121, 145, 148, 158], "get": [3, 4, 5, 6, 19, 26, 27, 30, 31, 34, 36, 40, 51, 60, 62, 69, 76, 77, 92, 95, 102, 107, 111, 113, 120, 122, 126, 129, 131, 140, 142, 143, 145, 153, 155, 158, 165], "sint_n_4": 3, "abs_en": 3, "sint_n_3": 3, "booleandoab": 3, "b101": 3, "raw": [3, 51, 112, 122], "pattern": [3, 9, 36, 80, 158, 159], "sint_n_128": 3, "128": [3, 4, 58, 93, 113, 127], "sym_ab": 3, "127": [3, 5], "group": [3, 4, 5, 7, 26, 31, 40, 64, 71, 152, 157], "like": [3, 5, 6, 9, 12, 14, 20, 27, 38, 40, 43, 51, 59, 60, 61, 64, 66, 67, 75, 79, 80, 92, 93, 95, 102, 107, 110, 116, 123, 124, 126, 127, 129, 130, 133, 142, 143, 144, 149, 150, 153, 154, 155, 161], "other": [3, 5, 6, 15, 16, 27, 30, 40, 51, 52, 58, 60, 75, 77, 87, 92, 102, 109, 112, 113, 116, 120, 122, 123, 126, 130, 149, 151, 155, 165], "hdl": [3, 5, 6, 7, 33, 50, 62, 76, 82, 105, 118, 122, 123, 126, 129, 130, 141, 144, 149, 155, 157, 159], "static": [3, 5, 8, 19, 58, 63, 75, 84, 159], "access": [3, 5, 13, 18, 26, 30, 34, 37, 50, 51, 52, 58, 63, 69, 80, 92, 93, 103, 109, 129, 132, 133, 158, 165], "th": [3, 5], "offset": [3, 5, 26, 31, 37, 59, 92, 112], "ex": [3, 5, 58, 93, 107, 158, 159], "subdividein": [3, 5, 127], "slice": [3, 5, 129], "strict": [3, 5, 58, 127], "msb": [3, 5, 7, 31, 105, 114, 122], "most": [3, 5, 30, 31, 37, 49, 58, 65, 75, 102, 111, 112, 141, 143, 149, 159], "signific": [3, 5, 31], "lowest": [3, 5, 122], "basic": [3, 4, 5, 7, 14, 37, 50, 51, 94, 103, 130, 159, 161], "dynam": [3, 5, 8, 58, 79, 80, 84], "myuint_8bit": 3, "myuint_16bit": 3, "myuint_7bit": 3, "myuint_6bit": 3, "until": [3, 5, 18, 26, 31, 36, 37, 43, 44, 49, 51, 52, 58, 64, 92, 107, 113, 114, 127, 131, 132, 133, 135, 137, 138, 139, 141, 150, 159, 162, 163], "myuint_4bit": 3, "equival": [3, 4, 5, 6, 7, 8, 29, 31, 51, 57, 63, 108, 122, 124, 126, 127, 129, 130, 131, 140, 149, 159, 161], "revers": [3, 5, 7, 31, 86, 87, 114], "occur": [3, 4, 5, 6, 26, 33, 41, 52, 59, 92, 106, 124, 126, 129, 130, 131, 132, 155], "leftmost": [3, 5, 122], "isneg": [3, 5], "mysint_16bit": 3, "both": [3, 5, 6, 41, 59, 75, 79, 102, 108, 113, 116, 122, 124, 126, 133, 144, 145, 149], "overload": [3, 5], "paramet": [3, 5, 22, 26, 27, 31, 37, 39, 41, 49, 51, 58, 59, 63, 66, 80, 85, 86, 87, 95, 97, 112, 113, 123, 129, 130, 144, 152, 153, 154, 157, 158, 161], "slicescount": [3, 5], "rais": [3, 5, 22, 76, 92, 124], "divid": [3, 5, 34, 40, 58, 91, 113, 127, 154], "last": [3, 5, 6, 31, 40, 52, 63, 69, 79, 94, 109, 113, 114, 122, 124, 125, 130, 145, 157, 161], "sel": [3, 5, 24, 58, 114, 127], "myuintword": 3, "myuint_128bit": 3, "96": [3, 5, 41], "95": [3, 5], "want": [3, 5, 8, 10, 15, 22, 26, 27, 31, 36, 40, 47, 49, 51, 52, 58, 59, 63, 66, 76, 85, 86, 87, 92, 101, 112, 113, 116, 121, 122, 129, 130, 144, 153, 154, 155, 156, 158, 159, 161], "order": [3, 5, 6, 7, 8, 27, 30, 31, 36, 40, 49, 63, 79, 92, 107, 110, 112, 113, 122, 126, 145, 149, 153, 154], "myvector": [3, 5], "myrevuintword": 3, "through": [3, 5, 6, 11, 28, 30, 66, 108, 113, 114, 116, 126, 143, 144, 149, 159], "output8": [3, 5], "piec": [3, 5, 37, 69, 122, 126], "0xf": [3, 5, 92, 130], "0x5": [3, 5], "contrast": [3, 5, 113], "list": [3, 5, 6, 8, 11, 14, 26, 27, 30, 31, 37, 50, 51, 60, 80, 92, 93, 94, 114, 122, 127, 132, 144, 155, 159], "abov": [3, 5, 6, 8, 13, 18, 30, 34, 41, 67, 76, 92, 95, 102, 103, 107, 110, 113, 122, 126, 129, 130, 132, 153], "possibl": [3, 5, 11, 12, 14, 40, 42, 51, 62, 63, 75, 79, 80, 110, 127, 129, 130, 131, 141, 145, 154, 158, 159], "bitsrang": [3, 5], "g": [3, 6, 7, 8, 16, 22, 38, 40, 41, 44, 48, 59, 63, 64, 66, 74, 95, 97, 116, 124, 130, 131, 145, 156, 161], "valuerang": [3, 5], "concaten": [3, 5, 6, 31, 122], "low": [3, 5, 6, 7, 31, 41, 49, 51, 80, 86, 93, 108, 113, 114, 117, 133, 154, 161], "copi": [3, 5, 26, 30, 31, 51, 60, 88, 124, 144, 161], "enlarg": [3, 5], "fill": [3, 4, 26, 31, 52, 93, 105, 106, 130, 135, 137, 155, 161], "version": [3, 5, 29, 31, 36, 49, 60, 73, 79, 84, 112, 113, 114, 122, 142, 143, 145, 154, 158, 159, 165], "need": [3, 4, 5, 6, 7, 8, 16, 20, 22, 26, 27, 31, 33, 34, 38, 40, 41, 52, 58, 59, 60, 61, 62, 63, 64, 67, 69, 75, 76, 80, 83, 85, 86, 87, 88, 92, 93, 99, 102, 106, 107, 110, 111, 118, 122, 123, 124, 127, 129, 130, 137, 145, 151, 152, 154, 155, 158, 159, 161], "getzero": [3, 5, 31], "instanc": [3, 5, 6, 19, 22, 30, 31, 34, 36, 37, 51, 52, 60, 62, 66, 67, 84, 88, 91, 106, 116, 121, 122, 123, 124, 126, 127, 129, 130, 131, 133, 135, 137, 154, 155, 156, 158, 161], "getalltru": [3, 5], "validrang": [3, 5], "fit": [3, 5, 79, 88, 95, 102], "limit": [3, 5, 37, 51, 58, 60, 93, 131, 149, 155, 156, 159, 161], "collect": [3, 5, 26, 66, 120, 122, 135, 137, 155, 159], "immut": [3, 5], "mysint_1": 3, "myuint_32bit": 3, "x112233344": [3, 5], "0x44": [3, 5], "lowest_8bit": 3, "round": [3, 113], "http": [3, 30, 36, 52, 53, 55, 56, 60, 76, 80, 83, 84, 92, 93, 103, 115, 142, 143, 145], "org": [3, 60, 145], "wiki": [3, 83, 143], "mathemat": 3, "algorithm": [3, 12, 51, 75, 105], "n": [3, 8, 27, 31, 40, 80, 84, 112, 114, 122, 131], "ye": [3, 34, 76], "No": [3, 14, 52, 75, 76, 92, 93, 154, 157], "veri": [3, 26, 27, 33, 37, 38, 41, 58, 63, 65, 66, 79, 80, 88, 105, 107, 112, 129, 130, 158], "statist": 3, "accuraci": 3, "concern": [3, 6, 79], "doesn": [3, 58, 59, 64, 65, 76, 79, 102, 109, 124, 126, 130, 145, 154, 161], "them": [3, 7, 26, 31, 40, 41, 51, 52, 58, 60, 63, 66, 75, 80, 87, 92, 95, 106, 110, 113, 116, 120, 123, 126, 127, 129, 131, 140, 144, 145, 154, 156, 158, 159, 161, 165], "yet": [3, 76, 107, 116, 163], "rountoodd": 3, "close": [3, 37, 58, 76, 117, 127, 145, 149], "program": [3, 6, 18, 33, 50, 58, 63, 65, 95, 145, 159, 163, 165], "languag": [3, 9, 18, 27, 31, 36, 65, 66, 68, 70, 73, 75, 77, 108, 110, 129, 141, 149, 159, 161, 163], "comment": [3, 42], "matlab": 3, "infin": 3, "python2": 3, "python3": 3, "even": [3, 30, 37, 40, 51, 72, 75, 107, 110, 113, 130, 142], "roundtoup": 3, "got": [3, 131, 158], "b0": [3, 112, 121, 154, 158], "b1": [3, 4, 158], "simpl": [3, 26, 28, 33, 34, 37, 38, 39, 41, 49, 50, 51, 52, 61, 62, 67, 75, 76, 77, 79, 80, 88, 106, 108, 111, 113, 123, 129, 134, 138, 149, 156, 161], "hw": [3, 60, 112], "chose": 3, "although": [3, 112], "least": [3, 31, 52, 84, 92, 93], "cost": [3, 76, 79, 103, 113], "good": [3, 26, 31, 33, 41, 58, 80, 118, 122, 127, 155, 161], "almost": [3, 58, 62, 153], "perform": [3, 6, 8, 14, 36, 51, 62, 67, 68, 84, 88, 134, 138, 151, 158, 159], "As": [3, 33, 36, 41, 51, 52, 60, 63, 66, 67, 75, 79, 102, 103, 109, 113, 116, 122, 126, 127, 129, 130, 131, 141, 159, 161], "strongli": 3, "product": [3, 75], "posit": [3, 9, 14, 31, 114], "op": [3, 4, 30, 58, 60], "top": [3, 27, 40, 50, 51, 52, 58, 66, 102, 121, 126, 130, 133, 153, 154, 159, 161], "trim": 3, "discard": 3, "symmetri": [3, 51], "valid": [3, 7, 26, 30, 31, 34, 36, 38, 40, 41, 51, 52, 58, 87, 106, 108, 110, 113, 117, 124, 125, 127, 130, 135, 137, 154, 157, 158], "rtl": [3, 18, 58, 59, 72, 78, 81, 96, 107, 110, 119, 123, 126, 129, 130, 131, 135, 137, 155, 157, 163], "handl": [3, 36, 92, 102, 110, 115, 130, 135, 137, 157, 159], "calcul": [3, 39, 40, 47, 49, 107, 156, 161], "manual": [3, 12, 40, 43, 52, 102, 103, 112, 113, 124, 129, 154, 161], "way1": 3, "diagram": [3, 26, 27, 30, 79, 80], "factori": [3, 28, 34, 66, 80], "section": [3, 28, 50, 60, 69, 77, 123, 152, 159, 164], "fixfunct": 3, "sym": 3, "20": [3, 30, 40, 51, 80, 92, 95, 122, 131], "composit": [4, 7, 9, 31, 52, 130, 157], "mix": [4, 31, 33, 36, 58, 80, 126, 128, 163], "myvecofsint": [4, 31], "popul": [4, 80], "myvecofmixeduint": [4, 31], "z": [4, 31, 116, 124, 131, 161], "myvecof_xyz_ref": [4, 31], "iter": [4, 30, 38, 84, 114, 122, 130, 159], "map": [4, 7, 26, 27, 32, 36, 37, 51, 58, 64, 66, 103, 106, 112, 116, 127, 157, 159], "vec2": 4, "vec1": 4, "mybits_16bit": [4, 5], "getbitswidth": [4, 7, 26, 33, 124], "full": [4, 11, 12, 37, 58, 76, 80, 84, 92, 93, 95, 103, 127, 155], "println": [4, 5, 30, 63, 95, 107, 120, 122, 131, 144, 148, 158], "widthof": [4, 26, 106, 122], "put": [4, 6, 27, 41, 92], "scope": [4, 13, 14, 30, 43, 58, 120, 124, 127, 129, 130, 156, 158, 161], "scount": 4, "condit": [4, 30, 58, 59, 64, 69, 84, 126, 127, 129, 130, 131, 132, 133, 141, 157, 159, 161], "sexist": 4, "scontain": 4, "present": [4, 23, 27, 52, 65, 71, 73, 76, 84, 87, 92, 99, 108, 109, 113, 114, 122, 129, 161], "sfindfirst": 4, "reducebalancedtre": 4, "balanc": 4, "reduc": [4, 5, 66, 75, 79, 80, 88, 131, 145, 154, 158, 159], "try": [4, 18, 51, 65, 116, 124, 145], "minim": 4, "depth": [4, 11, 51, 52, 58, 60, 64, 76, 113, 122, 130, 135, 137, 144, 156], "circuit": [4, 75, 112], "should": [4, 6, 7, 12, 14, 26, 31, 33, 37, 51, 58, 59, 61, 62, 63, 64, 66, 67, 76, 85, 92, 94, 102, 113, 114, 117, 122, 126, 129, 131, 144, 145, 147, 149, 153, 154, 158, 161], "commut": 4, "associ": [4, 75, 110, 153], "shuffl": 4, "indexmap": 4, "old": [4, 30, 112, 129], "actual": [4, 62, 112, 155], "somewher": [4, 23, 30, 158], "c1": 4, "mani": [4, 14, 26, 30, 33, 36, 50, 51, 58, 60, 63, 66, 69, 75, 76, 79, 80, 88, 91, 95, 102, 106, 107, 113, 118, 122, 129, 131, 156, 159, 161], "c2": 4, "250": 4, "bigger": [4, 26, 51, 63, 106, 150], "b2": 4, "u1": [4, 16], "u2": 4, "sum": [4, 43, 46, 63, 107, 155, 161], "togeth": [4, 11, 80, 92, 113, 124, 153], "sxxx": 4, "prefix": [4, 9, 31, 152, 157, 158, 162], "disambigu": 4, "respect": [4, 144, 155], "ident": [4, 131], "accept": [4, 27, 51, 112, 113, 149], "lambda": [4, 107, 159], "argument": [4, 6, 62, 66, 83, 85, 86, 87, 88, 106, 107, 114, 122, 123, 126, 129, 130, 153, 154, 156, 158, 159, 161], "convei": [5, 31], "arithmet": [5, 31, 134, 138], "widest": 5, "statement": [5, 6, 14, 16, 23, 30, 31, 51, 52, 59, 63, 64, 66, 110, 123, 124, 126, 127, 149, 154, 157, 161], "construct": [5, 6, 22, 31, 33, 37, 38, 39, 51, 59, 63, 64, 66, 75, 76, 80, 88, 111, 149, 152, 158, 159], "mybits1": 5, "mybits2": 5, "mybits3": 5, "mybits4": 5, "1001_0011": 5, "readabl": [5, 26, 30, 33, 34, 58, 64, 106], "mybits5": 5, "initi": [5, 18, 33, 51, 59, 60, 69, 80, 83, 87, 108, 113, 128, 129, 134, 138], "10111000": 5, "few": [5, 30, 40, 52, 62, 76, 79, 92, 93, 149, 158, 159], "mybits6": 5, "101": [5, 127], "mybits7": 5, "final": [5, 9, 69, 80, 95, 102, 149], "prevent": [5, 20, 52, 76, 127, 154], "mismatch": [5, 14, 154], "below": [5, 7, 11, 14, 31, 38, 51, 69, 110, 113, 126, 127, 129, 130, 131, 132, 153, 154, 157], "1010": 5, "widen": [5, 31, 124], "condxmayb": 5, "110000": 5, "xy": [5, 38], "increas": [5, 75, 76, 131, 141], "all_1": 5, "bits_10bit": 5, "bits_8bit": 5, "shift_8bit": 5, "x42": [5, 13, 21], "cond": [5, 6, 16, 21, 31, 51, 58, 59, 64, 108, 113, 123, 126, 127, 129, 130, 158, 161], "notmyspecialvalu": 5, "mybits_32": 5, "x44332211": 5, "necessari": [5, 27, 31, 63, 130, 154], "retain": [5, 31], "mybits_8bit": 5, "mybits_7bit": 5, "mybits_6bit": 5, "mybits_4bit": 5, "high": [5, 6, 7, 26, 31, 37, 40, 41, 45, 58, 74, 75, 79, 80, 82, 87, 99, 108, 109, 112, 113, 114, 116, 149, 154, 161, 165], "mybitsword": 5, "mybits_128bit": 5, "myrevbitsword": 5, "mirror": 5, "extend": [5, 7, 8, 10, 11, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 63, 64, 66, 69, 85, 86, 87, 91, 92, 93, 94, 97, 99, 101, 102, 106, 108, 110, 112, 113, 116, 117, 118, 119, 120, 121, 122, 123, 127, 129, 130, 131, 134, 138, 148, 152, 153, 154, 155, 156, 158, 159, 161, 163], "pad": [5, 6, 113, 124], "were": [5, 16, 30, 51, 76, 116, 142], "defer": [5, 130], "later": [5, 7, 31, 36, 37, 80, 107, 120, 148, 154, 158], "resizeleft": [5, 31, 124], "place": [5, 6, 7, 22, 26, 31, 40, 50, 63, 106, 109, 113, 122, 123, 124, 129, 130, 131, 159], "mybits_32bit": 5, "mybits_24bit": 5, "bits_8bits_1": 5, "bits_8bits_2": 5, "bits_8bits_3": 5, "cat": [5, 31], "0x11": 5, "denot": 5, "direct": [5, 6, 15, 27, 37, 38, 41, 48, 49, 51, 58, 69, 91, 92, 102, 124, 127, 156, 161, 163], "switch": [5, 8, 14, 24, 30, 33, 40, 51, 58, 59, 110, 113, 118, 123, 124, 125, 151, 158], "mux": [5, 14, 31, 33, 113, 114, 118, 124, 125], "1101": 5, "test1": 5, "m": [5, 9, 31, 60, 80, 114, 122], "test2": 5, "test3": 5, "wire": [6, 31, 37, 51, 52, 58, 69, 75, 80, 112, 114, 123, 126, 128, 153, 154, 155, 158, 161], "similarli": [6, 107], "confus": 6, "describ": [6, 26, 27, 30, 33, 51, 52, 60, 69, 75, 76, 110, 123, 133, 155, 158, 159, 161], "truth": [6, 126], "concept": [6, 51, 58, 63, 65, 80, 102, 109], "rule": [6, 13, 18, 31, 60, 64, 69, 107, 125, 130, 155, 159, 161, 162, 163], "thumb": 6, "understand": [6, 51, 52, 65, 66, 124, 126, 130, 158], "decis": 6, "affect": [6, 30, 129], "execut": [6, 18, 26, 30, 36, 62, 66, 83, 92, 95, 107, 110, 115, 120, 126, 127, 130, 131, 132, 144, 150, 151, 153, 161, 163], "run": [6, 18, 28, 36, 52, 60, 61, 62, 67, 75, 79, 83, 107, 114, 117, 120, 135, 137, 144, 145, 163], "observ": 6, "becaus": [6, 12, 19, 22, 23, 27, 33, 36, 40, 41, 51, 58, 63, 64, 66, 69, 76, 79, 80, 88, 94, 109, 118, 122, 124, 126, 129, 131, 152, 161, 163], "ahead": 6, "gen": [6, 60], "scenario": [6, 124, 159], "might": [6, 60, 61, 113, 129, 130], "pass": [6, 49, 66, 67, 95, 123, 126, 144, 153, 156], "mayb": [6, 126, 145], "act": 6, "parameter": [6, 23, 51, 57, 66, 122, 155, 159], "manipul": [6, 64, 126, 156, 158, 161], "rout": [6, 113], "modul": [6, 29, 37, 51, 80, 82, 84, 95, 121, 123, 153, 155, 158, 159], "compon": [6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 21, 22, 23, 24, 25, 26, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 44, 45, 47, 48, 49, 50, 51, 57, 59, 62, 64, 66, 72, 78, 81, 92, 93, 94, 95, 99, 108, 110, 112, 113, 116, 117, 118, 119, 121, 122, 127, 129, 130, 131, 132, 134, 135, 137, 138, 141, 149, 152, 153, 154, 156, 157, 159, 163], "driven": [6, 13, 41, 52, 75, 102, 116, 126, 130, 133, 154, 158, 161, 165], "connect": [6, 34, 40, 51, 69, 75, 80, 83, 86, 87, 92, 108, 113, 115, 116, 124, 130, 153, 155, 156, 161], "sunk": 6, "manag": [6, 33, 41, 47, 92, 93, 107, 110, 114, 122, 133, 135, 137, 146, 159], "hand": [6, 116, 124, 159], "side": [6, 7, 11, 25, 31, 42, 76, 108, 113, 122, 124, 126, 145, 161], "dictat": 6, "state": [6, 8, 31, 32, 38, 40, 51, 52, 69, 92, 102, 108, 112, 116, 120, 122, 126, 161], "sink": [6, 58, 113, 158], "captur": [6, 26, 113, 131, 135, 154, 159], "normal": [6, 60, 64, 92, 112], "drive": [6, 20, 26, 34, 37, 41, 47, 51, 52, 58, 84, 87, 101, 106, 108, 112, 113, 129], "abl": [6, 22, 26, 34, 41, 63, 76, 87, 88, 93, 94, 116, 141, 145, 158], "appear": [6, 13, 51, 67, 76, 126], "matter": [6, 76], "unlik": [6, 112, 137, 155, 161], "express": [6, 9, 30, 31, 76, 124, 126, 130, 157, 159], "win": [6, 31, 124, 125, 130, 161], "take": [6, 27, 33, 34, 37, 41, 51, 52, 62, 63, 66, 76, 97, 106, 110, 113, 122, 124, 127, 130, 131, 144, 153, 154, 161], "effect": [6, 47, 66, 92, 112, 113, 139, 145], "layout": [6, 80], "ensur": [6, 24, 52, 92, 110, 159], "correct": [6, 31, 75, 95, 102, 124, 134, 138], "preced": [6, 40, 66, 109, 127, 161], "archiv": 6, "relat": [6, 52, 64, 151], "refer": [6, 18, 30, 33, 40, 75, 105, 108, 113, 123, 125, 132, 135, 137, 143, 152, 156, 158, 161, 163], "net": 6, "attach": [6, 51, 74, 93, 103], "explicitli": [6, 59, 129, 130, 131, 153], "mybool_1": 6, "verilog": [6, 8, 14, 18, 30, 37, 60, 62, 66, 67, 68, 79, 94, 110, 116, 118, 119, 121, 124, 126, 127, 129, 130, 131, 133, 141, 144, 145, 146, 150, 152, 156, 157, 159, 163, 165], "mybool_2": 6, "mybool_3": 6, "unit": [6, 7, 26, 30, 31, 33, 36, 40, 41, 42, 51, 58, 63, 85, 87, 91, 101, 102, 112, 116, 122, 123, 126, 130, 131, 132, 134, 135, 137, 138, 141, 150, 153, 156, 158, 161], "none": [6, 40, 127, 161], "setwhen": [6, 31, 37, 41, 112], "clearwhen": [6, 31, 41], "risewhen": 6, "fallwhen": 6, "re": [6, 62, 126, 145], "f": [6, 83, 95, 122, 124], "reginit": [6, 36, 40, 41, 117, 130, 158], "ack": [6, 92], "req": 6, "mind": [6, 113], "regist": [6, 11, 14, 26, 27, 30, 33, 34, 36, 37, 40, 45, 48, 51, 52, 57, 58, 69, 90, 103, 106, 108, 112, 113, 114, 118, 122, 124, 125, 128, 147, 148, 151, 154, 156, 158, 161], "via": [6, 10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 40, 51, 52, 66, 80, 91, 92, 99, 102, 115, 132, 145, 149, 154, 155, 158, 161], "regnext": [6, 11, 20, 22, 30, 33, 40, 48, 49, 58, 80, 130, 138, 154, 161], "delai": [6, 52, 108, 113, 114, 133, 151], "question": [6, 71, 76], "reconfigur": 6, "flip": [6, 31, 113, 114, 154], "flop": [6, 80, 113, 114, 154], "altern": [6, 19, 22, 29, 60, 63, 82, 113, 120, 127, 154, 157, 165], "clk": [6, 30, 51, 58, 112, 116, 121, 123, 129, 153, 154, 158, 161], "seri": 6, "chain": [6, 12, 78, 81, 95, 124, 157], "pin": [6, 26, 33, 40, 80, 91, 92, 95, 102, 113, 116, 153, 154], "inherit": [6, 154], "clockdomain": [6, 7, 11, 28, 40, 47, 52, 58, 80, 92, 93, 94, 108, 113, 114, 123, 131, 135, 137, 138, 148, 151, 152, 153, 154, 161], "combin": [6, 11, 16, 17, 23, 58, 66, 79, 95, 113, 124, 126, 130, 134, 154, 156, 161, 162], "output": [6, 7, 13, 30, 31, 33, 34, 37, 40, 41, 43, 44, 45, 49, 52, 59, 61, 69, 75, 80, 93, 96, 101, 102, 108, 113, 121, 122, 123, 129, 130, 131, 133, 134, 135, 137, 138, 156, 157, 158, 159, 161], "initat": [6, 31], "reset": [6, 31, 33, 40, 41, 46, 51, 58, 59, 69, 78, 81, 83, 92, 96, 110, 112, 114, 116, 121, 123, 124, 128, 132, 133, 135, 137, 139, 152, 154, 157, 158, 161], "rise": [6, 31, 58, 132, 133, 154, 161], "wa": [6, 13, 15, 22, 30, 31, 41, 65, 66, 76, 79, 92, 107, 108, 113, 114, 116, 117, 126, 130, 158], "cycl": [6, 26, 30, 31, 36, 40, 41, 45, 48, 52, 59, 79, 80, 84, 99, 106, 110, 113, 114, 115, 126, 129, 130, 131, 132, 133, 147, 149, 151, 154, 161], "now": [6, 13, 27, 30, 31, 33, 37, 38, 41, 60, 61, 62, 67, 80, 103, 107, 112, 127], "fall": [6, 31, 117, 132, 154, 161], "bundl": [6, 8, 9, 13, 14, 20, 22, 28, 30, 33, 34, 36, 37, 39, 41, 42, 43, 44, 45, 47, 48, 49, 51, 58, 59, 64, 66, 69, 80, 85, 86, 87, 88, 91, 94, 97, 99, 101, 102, 108, 109, 110, 112, 113, 121, 122, 123, 124, 130, 131, 134, 138, 153, 154, 155, 156, 157, 159, 161, 163], "toggl": [6, 112, 113, 132, 133, 135, 158], "booledg": 6, "everi": [6, 11, 27, 28, 40, 52, 58, 66, 113, 126, 130, 155], "edgebundl": 6, "mask": [6, 28, 36, 37, 114, 129], "own": [6, 33, 51, 75, 76, 79, 92, 94, 129, 144, 149, 155], "maskedliter": 6, "model": [7, 26, 31, 61, 75, 97, 99, 105, 116, 126, 133, 135, 137, 144, 149, 159], "structur": [7, 26, 27, 28, 31, 39, 58, 59, 69, 75, 165], "buse": [7, 31, 57, 75, 118], "interfac": [7, 28, 32, 36, 39, 41, 51, 57, 72, 75, 79, 80, 83, 84, 86, 91, 93, 96, 99, 103, 108, 112, 113, 124, 127, 142, 143, 148, 153, 155], "mybundl": [7, 122, 130], "bundleitem0": 7, "anytyp": 7, "bundleitem1": 7, "bundleitemn": 7, "hold": [7, 40], "color": [7, 31, 39, 46, 48, 51, 58, 63, 64, 98, 99, 156, 161], "channelwidth": [7, 31, 44, 59, 113], "r": [7, 22, 34, 37, 41, 44, 48, 59, 63, 64, 66, 79, 87, 97, 112, 130, 156, 161], "apb3": [7, 34, 37, 46, 51, 58, 78, 81, 82, 89, 96, 106, 112, 116, 130], "definit": [7, 11, 15, 16, 17, 20, 22, 23, 24, 31, 36, 39, 46, 51, 57, 59, 63, 67, 69, 75, 80, 90, 94, 99, 107, 110, 111, 116, 122, 123, 129, 131, 144, 153, 154, 157], "among": 7, "condition": [7, 116, 127, 161], "unless": [7, 158], "datawidth": [7, 26, 31, 34, 37, 42, 51, 58, 80, 85, 86, 87, 88, 92, 93, 116, 155], "demonstr": [7, 31, 32, 37, 159], "color1": 7, "color2": 7, "thu": [7, 159], "occupi": 7, "assignfrombit": [7, 8, 26, 31, 33], "view": [7, 60, 122], "hi": [7, 31, 161], "lo": [7, 31], "boundari": [7, 92, 102], "commondatabu": 7, "circular": 7, "buffer": [7, 41, 64, 102, 113, 133, 139, 140], "3rd": 7, "parti": [7, 40, 51, 52, 129], "memori": [7, 26, 30, 32, 36, 48, 51, 62, 66, 74, 80, 84, 92, 93, 103, 106, 107, 108, 113, 115, 116, 123, 128, 142, 143, 149, 151], "format": [7, 31, 60, 123, 130, 131, 144, 149, 162, 165], "testbundl": 7, "addrwr": 7, "datain": [7, 154], "addrrd": 7, "dataout": [7, 154], "mm": 7, "ram3rdparty_1w_1r": 7, "g_data_width": 7, "g_addr_width": 7, "g_vendor": 7, "intel_arria10_m20k": 7, "clk_in": 7, "readclockwir": [7, 154], "clk_out": 7, "addr_wr": 7, "addr_rd": 7, "insid": [7, 13, 31, 37, 40, 58, 59, 62, 63, 64, 66, 91, 99, 110, 113, 118, 126, 127, 132, 145, 154, 155, 156, 158, 161, 163], "go": [7, 30, 33, 50, 60, 69, 75, 92], "obei": [7, 18, 124, 163], "topologi": [7, 79], "imasterslav": [7, 31, 33, 40, 41, 42, 51, 58, 85, 86, 87, 91, 99, 101, 102, 116, 155, 156], "trait": [7, 26, 33, 41, 110, 112], "Then": [7, 26, 31, 33, 34, 37, 41, 42, 44, 49, 51, 58, 59, 63, 66, 67, 69, 76, 80, 84, 92, 101, 106, 118, 122, 129, 131, 145], "asmast": [7, 31, 33, 40, 41, 42, 51, 85, 87, 91, 99, 101, 102, 116, 156], "perspect": [7, 79, 113, 126, 163], "toxxx": 7, "tostream": [7, 34, 40], "flow": [7, 26, 34, 36, 40, 51, 60, 91, 95, 106, 109, 111, 113, 129, 130, 144, 151, 159], "fromxxx": 7, "handshak": [7, 51, 58, 79, 88, 113, 117], "payloadwidth": [7, 156, 161], "readi": [7, 26, 36, 38, 40, 41, 51, 58, 60, 113, 116, 117, 135, 137, 153, 157, 158], "payload": [7, 26, 34, 36, 40, 41, 51, 58, 106, 108, 109, 113, 122, 135, 137, 157, 158], "overrid": [7, 10, 22, 26, 30, 31, 33, 40, 41, 42, 51, 63, 85, 87, 91, 99, 101, 102, 116, 122, 131, 155, 156, 158], "enumer": [8, 28, 31, 40, 110, 123], "object": [8, 11, 26, 30, 31, 33, 34, 36, 40, 42, 43, 50, 51, 52, 58, 66, 67, 75, 79, 80, 85, 86, 87, 88, 91, 92, 93, 94, 95, 108, 113, 119, 120, 123, 126, 129, 130, 131, 134, 135, 137, 138, 148, 149, 151, 153, 155, 158, 159, 161], "element0": 8, "element1": 8, "elementn": 8, "newel": [8, 31, 33, 40, 119], "nativ": [8, 31, 58, 83, 110, 116, 149, 151, 159], "vhdl": [8, 14, 18, 31, 37, 40, 43, 47, 50, 60, 66, 68, 78, 110, 116, 118, 124, 126, 127, 129, 130, 133, 141, 144, 149, 150, 152, 156, 157, 159, 163, 165], "forc": [8, 58, 92, 112, 158], "defaultencod": [8, 31], "encodingofyourchoic": [8, 31], "myenum": 8, "system": [8, 31, 37, 38, 40, 41, 58, 60, 74, 75, 78, 81, 105, 107, 129, 140, 142, 143, 149, 153, 158], "binarysequenti": [8, 40], "statecount": [8, 31, 48, 114], "binaryonehot": [8, 31, 110], "graysequenti": [8, 110], "grai": [8, 11, 46, 114, 123, 154, 157], "myenumstat": 8, "e0": 8, "e1": 8, "e2": 8, "e3": 8, "spinalenumencod": [8, 110], "staticencod": 8, "dynamicencod": 8, "myenumdynam": 8, "uartctrltxstat": [8, 31, 40], "sidl": [8, 31], "sstart": [8, 31], "sdata": [8, 31], "spariti": [8, 31], "sstop": [8, 31], "statenext": [8, 31, 33], "visibl": [8, 31, 41, 64, 80, 148], "enum": [8, 9, 28, 39, 59, 110, 119, 123], "spinalenumel": [8, 148], "spinalenumcraft": [8, 148], "sub": [9, 30, 58, 63, 80], "mul": [9, 30, 79, 82, 84, 115], "float": [9, 48, 52, 63, 156, 161], "bitvector": [9, 28, 30, 114, 122, 124, 148, 161], "contain": [9, 15, 26, 30, 31, 33, 38, 40, 49, 50, 59, 60, 63, 69, 95, 102, 106, 107, 110, 116, 122, 123, 127, 129, 130, 142, 143, 145, 153, 161, 164], "hole": [9, 31], "bitmask": [9, 31], "show": [9, 27, 31, 33, 36, 38, 40, 42, 58, 60, 62, 67, 73, 75, 82, 107, 124, 129, 130, 158], "achiev": [9, 76, 159], "itmatch": [9, 31], "complet": [10, 40, 49, 60, 62, 75, 79, 92, 103, 110, 112, 113, 122, 131], "eras": 10, "toplevel": [10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 30, 46, 52, 59, 78, 79, 81, 82, 94, 95, 107, 110, 116, 117, 119, 121, 123, 129, 131, 132, 148, 153, 154, 155], "42": [10, 12, 16, 17, 18, 19, 23, 58, 59, 63, 66, 101, 102, 127, 130, 148, 150], "66": 10, "throw": [10, 11, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 129], "file": [10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 27, 50, 60, 61, 62, 63, 66, 67, 75, 76, 83, 84, 96, 112, 123, 131, 144, 145, 146, 153, 158, 159, 161], "locat": [10, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 30, 60, 92, 131], "stack": [10, 11, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 74, 120, 154, 161], "trace": [10, 11, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 144], "But": [10, 15, 31, 37, 41, 51, 52, 58, 62, 64, 69, 76, 92, 110, 113, 127, 158, 161], "realli": [10, 15, 33, 51, 58, 72, 102, 126], "allowoverrid": 10, "depend": [11, 33, 58, 60, 62, 69, 79, 107, 113, 130, 142, 145, 149, 153, 154, 159], "path": [11, 27, 30, 58, 61, 80, 84, 95, 108, 113, 114, 124, 131, 144, 145], "synchron": [11, 40, 41, 47, 107, 113, 114, 126, 128, 136, 154, 161], "domain": [11, 33, 40, 47, 57, 69, 75, 78, 81, 94, 113, 114, 118, 126, 130, 135, 153, 157], "clka": [11, 135, 153, 154], "extern": [11, 30, 37, 47, 48, 61, 92, 93, 112, 135, 141, 144, 155, 157], "clkb": [11, 135, 153, 154], "rega": [11, 30], "reg": [11, 20, 23, 26, 27, 33, 36, 37, 38, 40, 41, 45, 47, 49, 51, 52, 58, 59, 64, 66, 69, 75, 80, 106, 108, 110, 112, 123, 124, 126, 130, 131, 148, 152, 154, 158, 161], "playdev": [11, 12], "834": [11, 12], "regb": [11, 30], "835": 11, "tmp": [11, 13, 21, 22, 95, 127, 131, 158, 161], "838": 11, "declar": [11, 15, 20, 21, 22, 28, 57, 63, 64, 75, 123, 124, 125, 130, 153, 155, 161, 163], "commun": [11, 61, 76, 109, 142, 143, 149], "alright": 11, "panic": 11, "specif": [11, 19, 21, 28, 32, 33, 39, 46, 47, 62, 75, 87, 91, 92, 93, 94, 112, 129, 144, 153, 154, 155, 158, 161, 162], "addtag": [11, 94, 153, 154, 161], "exchang": 11, "safe": [11, 14, 51, 87, 113], "region": [11, 51, 58], "multi": [11, 38, 74, 144, 149, 154], "risk": 11, "corrupt": 11, "receiv": [11, 38, 40, 91, 92, 109], "asynchron": [11, 43, 47, 107, 114, 123, 129, 135, 136, 138, 154, 161], "detail": [11, 30, 64, 102, 130, 165], "asyncfifo": 11, "poptopushgrai": 11, "ptrwidth": 11, "pushtopopgrai": 11, "pushcc": 11, "clockingarea": [11, 47, 58, 80, 130, 152, 154, 161], "pushclock": [11, 113, 135], "pushptr": 11, "counter": [11, 30, 37, 40, 41, 46, 47, 49, 51, 52, 58, 59, 61, 64, 66, 69, 80, 110, 112, 123, 126, 131, 148, 152, 153, 154, 158, 161], "pushptrgrai": 11, "tograi": [11, 114], "valuenext": [11, 114], "init": [11, 14, 37, 38, 40, 41, 45, 47, 49, 51, 52, 58, 59, 60, 69, 80, 109, 110, 112, 123, 124, 129, 130, 131, 138, 148, 154, 161], "popptrgrai": 11, "isful": 11, "popcc": 11, "popclock": [11, 113, 135], "popptr": 11, "empti": [11, 30, 92, 107, 121], "isempti": 11, "line": [12, 31, 41, 58, 62, 64, 67, 75, 76, 84, 95, 107, 110, 123, 127, 146, 158, 161, 163], "831": 12, "832": 12, "said": [12, 79, 122, 126], "detect": [12, 14, 58, 112, 124, 131, 155, 163], "pessimist": 12, "give": [12, 31, 40, 41, 51, 59, 75, 76, 80, 112, 123, 129, 131, 155, 156, 161], "disabl": [12, 30, 52, 66, 84, 88, 126, 154, 159, 161], "nocombloopcheck": 12, "tool": [12, 26, 29, 30, 34, 37, 51, 58, 60, 62, 72, 75, 76, 78, 81, 94, 95, 102, 106, 107, 110, 111, 114, 116, 118, 122, 129, 141, 149, 161], "veril": [12, 60, 75, 131, 133, 141, 146, 158], "unhappi": 12, "never": [13, 51, 62, 64, 79, 117, 126, 131, 132], "outsid": [13, 21, 58, 63, 64, 66, 101, 102, 113, 154, 161], "current": [13, 26, 30, 33, 40, 41, 52, 62, 79, 92, 93, 94, 102, 107, 109, 110, 111, 112, 113, 114, 120, 123, 129, 133, 141, 151, 153, 154], "directionless": [13, 15], "inout": [13, 15, 102], "child": [13, 20, 155], "io": [13, 14, 20, 22, 30, 31, 33, 34, 37, 38, 39, 40, 42, 43, 44, 45, 47, 48, 49, 51, 52, 58, 59, 69, 78, 81, 91, 92, 93, 94, 99, 101, 102, 108, 110, 112, 113, 116, 121, 122, 123, 124, 127, 129, 130, 131, 132, 134, 135, 137, 138, 142, 148, 150, 152, 154, 155, 156, 157, 158, 161, 163, 165], "attempt": 13, "io_a": [13, 15, 16, 20], "isn": [13, 20, 21, 22, 51, 84, 92, 107, 158, 163], "sure": [14, 61, 79, 135, 144, 145, 149, 154], "synthesi": [14, 16, 30, 51, 75, 79, 84, 102, 116, 129, 161], "broken": 14, "non": [14, 16, 27, 33, 34, 82, 113, 149, 155], "exhaust": [14, 16], "overlap": [14, 124], "clock": [14, 30, 31, 33, 34, 40, 45, 47, 57, 69, 75, 78, 79, 81, 91, 92, 93, 94, 110, 111, 112, 113, 114, 118, 121, 123, 126, 130, 131, 133, 136, 138, 149, 157], "cross": [14, 58, 65, 75, 111, 113, 135, 157], "hierarchi": [14, 30, 52, 66, 69, 75, 116, 121, 123, 157], "violat": [14, 66], "combinatori": [14, 16, 43, 51, 58, 75, 80, 84, 113, 125, 161], "loop": [14, 43, 51, 58, 66, 75, 125, 126, 133, 159], "latch": [14, 52, 58, 69, 75, 124, 127], "undriven": 14, "unreach": [14, 127], "On": [14, 40, 78, 81, 82, 102, 113, 131, 149, 154], "report": [14, 18, 30, 71, 95, 107, 117, 124, 127, 131, 145, 153, 155], "accur": [14, 149], "look": [14, 33, 62, 114, 127, 129, 158, 159], "overkil": [14, 152, 161], "glanc": [14, 66], "invalu": 14, "soon": 14, "start": [14, 26, 27, 37, 40, 41, 51, 52, 60, 62, 64, 69, 75, 113, 114, 122, 126, 144, 153, 158, 165], "move": [14, 84, 129], "awai": [14, 155, 161], "tradit": [14, 50, 58, 113, 130], "introduct": [14, 27, 28, 32, 39, 46, 57, 78, 81, 157, 165], "crossclockdomain": [14, 154, 161], "setsynchronouswith": 14, "buffercc": [14, 40, 80, 114, 154], "driver": [14, 41, 42, 92, 93, 102, 108, 109, 113, 116], "nullpointerexcept": 14, "explan": [14, 41, 82, 163], "except": [14, 18, 64, 102, 112, 115], "clone": [14, 60, 64, 76, 113, 142, 145], "unassign": [14, 127], "oper": [14, 19, 26, 28, 30, 44, 51, 59, 66, 89, 92, 95, 124, 126, 129, 154, 158, 161], "kind": [15, 30, 36, 41, 50, 51, 58, 64, 66, 76, 80, 102, 107, 110, 122, 129, 152, 159, 161], "meta": [15, 21, 50, 57, 75, 82], "reason": [15, 16, 20, 22, 63, 64, 79, 116, 126, 129, 155, 156, 158, 161], "allowdirectionlessio": [15, 30], "word": [16, 26, 30, 33, 52, 80, 88, 92, 106, 120, 122, 126, 129], "often": [16, 30, 58, 63, 65, 108, 112, 113, 127, 140, 159], "muxlist": [16, 127], "ad": [16, 30, 40, 51, 58, 69, 80, 96, 116, 127, 129, 142, 144, 145, 146, 153, 158], "solut": [16, 22, 50, 51, 66, 76, 79, 80, 158], "muxlistdc": [16, 127], "those": [16, 26, 30, 31, 51, 58, 72, 73, 80, 95, 97, 116, 133, 154, 158, 159], "seq": [16, 37, 103, 113, 114, 119, 122], "impact": [17, 23, 88, 126, 130], "NO": 17, "ON": [17, 95], "runtim": [18, 30, 40, 62, 107, 126, 131], "happen": [18, 22, 26, 80, 92, 106, 117, 126, 133, 161, 163], "befor": [18, 33, 40, 41, 60, 64, 67, 95, 107, 110, 113, 122, 129, 144, 149, 150, 163], "been": [18, 23, 30, 41, 110, 129], "thread": [18, 38, 120, 132, 133, 135, 137, 144, 149], "main": [18, 30, 36, 37, 50, 58, 60, 61, 78, 79, 81, 94, 107, 112, 123, 129, 131, 134, 135, 137, 138, 148, 153, 154, 155, 161], "java": [18, 60, 63, 66, 75, 140, 142, 143, 145], "lang": 18, "librari": [18, 27, 28, 58, 60, 66, 72, 80, 85, 86, 87, 91, 92, 93, 108, 116, 118, 142, 143, 144, 155, 159, 161, 163, 165], "null": [18, 21, 30, 31, 40, 42, 51, 58, 80, 86, 117, 123, 144, 154, 159, 163], "comparison": [19, 28, 57], "wider": [19, 124], "OF": 19, "operand": [19, 25, 51, 134, 138], "101010": [19, 148], "against": [19, 76, 135, 137], "parametr": [19, 31, 80, 157], "known": [19, 129, 130, 154], "whitelist": 19, "allowoutofrangeliter": 19, "whole": [19, 30, 31, 66, 84, 92, 154, 159, 161], "spinalconfig": [19, 30, 40, 52, 123, 129, 131, 154], "behind": [20, 63, 65, 126, 149], "surpris": 20, "tri": [20, 102, 116, 129], "desir": [20, 154], "unregist": 20, "bodi": [20, 30, 107, 150], "AS": 20, "done": [20, 26, 30, 31, 33, 38, 41, 43, 51, 59, 62, 66, 76, 80, 102, 107, 110, 113, 114, 127, 130, 131, 144, 145, 150, 154, 158], "easi": [21, 58, 75, 79, 80, 112, 122, 141, 156], "trigger": [21, 69, 92, 112], "trick": [21, 51], "var": [21, 43, 44, 63, 124, 134, 138, 139, 161], "cloneof": [22, 30, 51, 58, 66, 122], "nearli": 22, "retriev": [22, 66, 113, 154], "itself": [22, 26, 29, 40, 41, 58, 76, 80, 92, 113, 126, 130, 158], "rgb": [22, 28, 39, 46, 51, 59, 64, 98, 99, 113, 129, 157], "stream": [22, 26, 34, 36, 38, 39, 41, 51, 58, 64, 79, 80, 87, 91, 99, 109, 111, 121, 158], "capabl": [22, 65, 75, 82, 88, 93, 106, 141, 149, 159], "tester": [22, 29, 158], "playdevmessag": 22, "solv": [22, 38, 107, 159], "arg": [22, 30, 50, 63, 66, 79, 94, 103, 113, 123, 129, 134, 135, 137, 138, 148, 153, 154, 155, 161], "Or": [22, 31, 50, 52, 79, 110, 123, 148, 161], "self": [22, 158], "xlen": [22, 120], "memoryaddress": 22, "xlenconfig": 22, "address": [22, 26, 34, 36, 37, 42, 48, 52, 75, 79, 80, 84, 85, 86, 88, 90, 106, 112, 129, 161], "debugmemori": 22, "config": [22, 27, 30, 31, 34, 40, 42, 51, 58, 60, 80, 85, 86, 87, 90, 91, 97, 114, 144, 154, 155, 159, 161], "inputaddress": 22, "someaddress": 22, "exept": 22, "debug": [22, 29, 58, 67, 78, 79, 80, 82, 83, 112, 115, 119, 123, 144, 155, 158, 161], "propag": [22, 93, 130, 134, 158], "eventu": 22, "scopeproperti": [22, 159], "somethingels": 23, "ask": [23, 26, 34, 80, 114, 130, 145], "transform": [23, 30, 34, 62, 75, 116, 128], "allowunsetregtoavoidlatch": 23, "reachabl": 24, "duplic": [24, 58, 127, 152, 164], "document": [26, 28, 30, 31, 34, 37, 51, 64, 70, 80, 82, 84, 95, 102, 106, 111, 113, 129, 151, 155, 161, 164, 165], "variant": [26, 30], "abstract": [26, 33, 37, 51, 58, 75, 76, 102, 106, 107, 116, 118, 129, 130, 149], "busdatawidth": [26, 106, 112], "bitoffset": [26, 106], "respons": [26, 85, 88, 92, 106], "write": [26, 32, 34, 36, 37, 40, 41, 48, 51, 52, 58, 59, 63, 66, 75, 79, 87, 88, 91, 92, 101, 102, 106, 108, 112, 113, 116, 128, 130, 133, 141, 150, 156, 161], "onwrit": [26, 106], "dothat": [26, 106], "transact": [26, 36, 38, 79, 87, 92, 99, 106, 108, 109, 113, 135, 137], "onread": [26, 106], "nonstopwrit": [26, 106], "perman": [26, 106], "util": [26, 30, 31, 37, 79, 118, 132, 134, 138, 158], "readandwrit": [26, 106], "writabl": [26, 34, 106], "readmultiword": [26, 106], "writemultiword": [26, 106], "createwriteonli": [26, 106], "createreadwrit": [26, 106], "createanddriveflow": [26, 34, 106], "driveandread": [26, 34, 37, 106], "driveflow": [26, 106], "emit": [26, 91, 106, 123, 154, 159, 161], "readstreamnonblock": [26, 34, 106], "validbitoffset": [26, 34, 106], "payloadbitoffset": [26, 34, 106], "consum": [26, 106, 113], "dobitsaccumulationandclearonread": [26, 106], "intern": [26, 28, 31, 41, 47, 48, 51, 57, 66, 91, 92, 93, 102, 106, 110, 113, 114, 122, 133, 138, 156, 157, 161], "primit": [26, 133, 154], "busslavefactoryel": 26, "datamodel": [26, 28], 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104, 108, 110, 113, 114, 120, 122, 126, 131, 133, 153, 154, 156, 158, 161], "readatcmd": 26, "readatrsp": 26, "stage": [26, 30, 34, 40, 75, 79, 80, 84, 108, 113, 114, 115, 154, 161], "job": [26, 33], "That": [26, 51, 52, 65], "apb3slavefactori": [26, 34, 37, 106], "apb3uartctrl": [26, 34, 51, 80], "variat": [26, 60, 79, 89, 106], "probabl": [26, 31, 37, 51, 58, 60, 154, 161, 163], "appropri": 27, "opt": 27, "resampl": 27, "variou": [27, 66, 112], "strictli": [27, 126, 130, 159], "clariti": 27, "sake": 27, "highli": 27, "encourag": 27, "recurs": [27, 30], "tree": [27, 30, 92, 93], "folder": [27, 60, 67, 84, 95, 131, 145], "rst": 27, "tell": 27, "sphinx": 27, "smart": [27, 58, 75], "deduc": 27, "alphanumer": 27, "charact": 27, "consist": [27, 80], "progress": [27, 30, 62, 92, 113, 164], "over": [27, 30, 37, 40, 92, 102, 110, 113, 116, 118, 126, 129, 130, 149, 151, 159, 165], "underlin": 27, "paragraph": 27, "subparagraph": 27, "sphinxcontrib": 27, "plugin": [27, 28, 58, 60, 61, 80, 83, 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124, 126, 165], "sequenti": [27, 107, 113, 124, 138, 165], "legaci": [27, 69, 165], "up": [27, 37, 40, 41, 52, 59, 60, 67, 80, 92, 93, 114, 131, 133, 145, 153, 158], "bu": [28, 31, 32, 34, 36, 37, 39, 42, 51, 58, 69, 75, 78, 79, 81, 85, 86, 87, 88, 90, 92, 93, 94, 98, 103, 107, 108, 109, 111, 112, 113, 116, 124, 157, 159], "slave": [28, 31, 33, 34, 37, 38, 40, 41, 42, 51, 52, 58, 80, 85, 87, 91, 94, 99, 107, 108, 112, 113, 116, 121, 155, 156, 158], "busslavefactori": [28, 37, 58, 99, 103, 106], "busslavefactorydelai": 28, "avalonmmslavefactori": 28, "conclus": 28, "hack": 28, "titl": [28, 112], "convent": [28, 33, 63, 122, 155], "wavedrom": 28, "integr": [28, 31, 37, 41, 58, 75, 79, 80, 84, 107, 118, 126, 129, 132, 141, 144, 153], "mill": [28, 60], "suit": [28, 52, 159], "app": [28, 30, 36, 40, 42, 43, 52, 67, 92, 93, 108, 113, 120, 131, 158], "publish": [28, 76], "local": [28, 120, 125, 154, 161], "explor": [28, 52, 61, 62, 67], "phase": [28, 49, 92], "netlist": [28, 52, 66, 76, 129, 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132, 145, 154], "maintain": [31, 64, 107], "0001": [31, 123], "jtag": [32, 58, 78, 81, 82, 84, 111, 115], "tap": 32, "machin": [32, 40, 51, 75, 115], "instruct": [32, 51, 79, 82, 84, 115, 127], "idcod": 32, "friendli": [32, 75, 115], "uart": [32, 39, 78, 81, 82, 90, 94, 106, 108, 109, 111, 113, 123, 124, 136, 154], "pinesec": 32, "slot": 32, "timer": [32, 78, 81, 82, 106, 152, 161], "bridg": [32, 51, 78, 81, 82, 84, 111, 113], "goal": [33, 51, 75, 76, 82, 111, 154, 159, 161], "orient": [33, 50, 51, 58, 75], "decoupl": [33, 88], "Of": [33, 122], "cours": [33, 122], "forward": [33, 84], "reusabl": [33, 51, 122, 157], "extens": [33, 58, 60, 67, 80, 82, 84, 112, 115], "tutori": [33, 40, 41, 60, 73], "commonli": [33, 86, 111, 118], "fact": [33, 51, 58, 66, 80], "builder": [33, 112], "bellow": 33, "seem": [33, 52, 66, 122], "plai": [33, 49, 51, 156, 161], "led": [33, 40], "recogn": 33, "uid": 33, "0x87654321": [33, 102], "simplejtagtap": 33, "jtagtap": 33, "idcodearea": 33, "x87654321": 33, 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"MaskedLiteral": [[5, "maskedliteral"]], "Bool": [[6, "bool"], [31, "bool"]], "Edge detection": [[6, "edge-detection"]], "MaskedBoolean": [[6, "maskedboolean"]], "Bundle": [[7, "bundle"], [31, "bundle"]], "Conditional signals": [[7, "conditional-signals"]], "Convert Bits back to Bundle": [[7, "convert-bits-back-to-bundle"]], "IO Element direction": [[7, "io-element-direction"]], "in/out": [[7, "in-out"]], "master/slave": [[7, "master-slave"]], "SpinalEnum": [[8, "spinalenum"]], "Encoding": [[8, "encoding"]], "Types": [[8, "types"], [31, "types"], [63, "types"]], "Data types": [[9, "data-types"], [59, "data-types"]], "Assignment overlap": [[10, "assignment-overlap"]], "Introduction": [[10, "introduction"], [11, "introduction"], [12, "introduction"], [13, "introduction"], [15, "introduction"], [16, "introduction"], [17, "introduction"], [18, "introduction"], [19, "introduction"], [20, "introduction"], [21, "introduction"], [22, "introduction"], [23, "introduction"], [24, "introduction"], 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"io-bundle"]], "Latch detected": [[16, "latch-detected"]], "Due to mux": [[16, "due-to-mux"]], "No driver on": [[17, "no-driver-on"]], "NullPointerException": [[18, "nullpointerexception"]], "Issue explanation": [[18, "issue-explanation"]], "Out of Range Constant": [[19, "out-of-range-constant"]], "Specifying exceptions": [[19, "specifying-exceptions"]], "Register defined as component input": [[20, "register-defined-as-component-input"]], "Scope violation": [[21, "scope-violation"]], "Spinal can\u2019t clone class": [[22, "spinal-can-t-clone-class"]], "Example 1": [[22, "example-1"]], "Example 2": [[22, "example-2"]], "Unassigned register": [[23, "unassigned-register"]], "Register with only init": [[23, "register-with-only-init"]], "Unreachable is statement": [[24, "unreachable-is-statement"]], "Width mismatch": [[25, "width-mismatch"]], "Assignment example": [[25, "assignment-example"]], "Operator example": [[25, "operator-example"]], "Bus Slave Factory Implementation": [[26, "bus-slave-factory-implementation"]], "Specification": [[26, "specification"], [34, "specification"], [37, "specification"], [37, "id3"], [38, "specification"], [40, "specification"], [41, "specification"], [42, "specification"], [105, "specification"], [108, "specification"], [109, "specification"], [113, "specification"]], "Implementation": [[26, "implementation"], [34, "implementation"], [36, "implementation"], [37, "implementation"], [37, "id4"], [40, "implementation"], [42, "implementation"]], "BusSlaveFactory": [[26, "busslavefactory"]], "BusSlaveFactoryDelayed": [[26, "busslavefactorydelayed"]], "AvalonMMSlaveFactory": [[26, "avalonmmslavefactory"]], "Conclusion": [[26, "conclusion"]], "How to HACK this documentation": [[27, "how-to-hack-this-documentation"]], "Title convention": [[27, "title-convention"]], "Wavedrom integration": [[27, "wavedrom-integration"]], "New section": [[27, "new-section"]], "example": [[27, "example"]], "Developers area": [[28, "developers-area"]], "Build through Mill": [[29, "build-through-mill"]], "Compile the library": [[29, "compile-the-library"]], "Run all test suites": [[29, "run-all-test-suites"]], "Run a specified test suite": [[29, "run-a-specified-test-suite"]], "Run a specified App": [[29, "run-a-specified-app"]], "Publish locally": [[29, "publish-locally"]], "SpinalHDL internal datamodel": [[30, "spinalhdl-internal-datamodel"]], "General structure": [[30, "general-structure"]], "Exploring the datamodel": [[30, "exploring-the-datamodel"]], "Compilation Phases": [[30, "compilation-phases"]], "Modifying a netlist as a user without plugins": [[30, "modifying-a-netlist-as-a-user-without-plugins"]], "User space netlist analysis": [[30, "user-space-netlist-analysis"]], "Enumerating every ClockDomain used": [[30, "enumerating-every-clockdomain-used"]], "The BitVector family - (Bits, UInt, SInt)": [[31, "the-bitvector-family-bits-uint-sint"]], "Declaration syntax": [[31, "declaration-syntax"]], "Masked comparison": [[31, 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instruction": [[33, "idcode-instruction"]], "User friendly wrapper": [[33, "user-friendly-wrapper"]], "Usage demonstration": [[33, "usage-demonstration"]], "Memory mapped UART": [[34, "memory-mapped-uart"]], "Pinesec": [[35, "pinesec"]], "Slots": [[36, "slots"]], "In practice": [[36, "in-practice"]], "Timer": [[37, "timer"], [37, "id2"], [80, "timer"]], "Bridging function": [[37, "bridging-function"]], "Usage": [[37, "usage"], [42, "usage"], [92, "usage"], [93, "usage"]], "Fractal calculator": [[38, "fractal-calculator"]], "Elaboration parameters (Generics)": [[38, "elaboration-parameters-generics"]], "Bundle definition": [[38, "bundle-definition"]], "Component implementation": [[38, "component-implementation"]], "Intermediates ones": [[39, "intermediates-ones"]], "UART": [[40, "uart"], [91, "uart"]], "Data structures": [[40, "data-structures"], [41, "data-structures"]], "Controller construction parameters": [[40, "controller-construction-parameters"]], "UART interface": [[40, "uart-interface"]], "UART configuration enums": [[40, "uart-configuration-enums"]], "UartCtrl configuration Bundles": [[40, "uartctrl-configuration-bundles"]], "UartCtrlTx": [[40, "uartctrltx"]], "UartCtrlRx": [[40, "uartctrlrx"]], "UartCtrl": [[40, "uartctrl"], [91, "uartctrl"]], "Simple usage": [[40, "simple-usage"]], "Example with test bench": [[40, "example-with-test-bench"]], "Bonus: Having fun with Stream": [[40, "bonus-having-fun-with-stream"]], "VGA": [[41, "vga"], [99, "vga"]], "RGB color": [[41, "rgb-color"]], "VGA bus": [[41, "vga-bus"], [99, "vga-bus"]], "VGA timings": [[41, "vga-timings"], [99, "vga-timings"]], "VGA Controller": [[41, "vga-controller"]], "Component and io definition": [[41, "component-and-io-definition"]], "Horizontal and vertical logic": [[41, "horizontal-and-vertical-logic"]], "Interconnections": [[41, "interconnections"]], "Bonus": [[41, "bonus"]], "APB3 definition": [[42, "apb3-definition"]], "Carry adder": [[43, "carry-adder"]], "Color summing": [[44, "color-summing"]], "Counter with clear": [[45, "counter-with-clear"]], "Simple ones": [[46, "simple-ones"]], "PLL BlackBox and reset controller": [[47, "pll-blackbox-and-reset-controller"]], "The PLL BlackBox definition": [[47, "the-pll-blackbox-definition"]], "TopLevel definition": [[47, "toplevel-definition"]], "RGB to gray": [[48, "rgb-to-gray"], [156, "rgb-to-gray"], [161, "rgb-to-gray"]], "Sinus rom": [[49, "sinus-rom"]], "Getting started": [[50, "getting-started"]], "Foreword": [[51, "foreword"]], "Why moving away from traditional HDL": [[51, "why-moving-away-from-traditional-hdl"]], "VHDL/Verilog aren\u2019t Hardware Description Languages": [[51, "vhdl-verilog-aren-t-hardware-description-languages"]], "Event driven paradigm doesn\u2019t make any sense for RTL": [[51, "event-driven-paradigm-doesn-t-make-any-sense-for-rtl"]], "Recent revisions of VHDL and Verilog aren\u2019t usable": [[51, "recent-revisions-of-vhdl-and-verilog-aren-t-usable"]], "VHDL records, Verilog struct are broken (SystemVerilog is good on this, if you can use it)": [[51, "vhdl-records-verilog-struct-are-broken-systemverilog-is-good-on-this-if-you-can-use-it"]], "VHDL and Verilog are so verbose": [[51, "vhdl-and-verilog-are-so-verbose"]], "Meta Hardware Description capabilities": [[51, "meta-hardware-description-capabilities"]], "Formal verification": [[52, "formal-verification"]], "General": [[52, "general"], [122, "general"]], "Formal backend": [[52, "formal-backend"]], "Installing requirements": [[52, "installing-requirements"]], "External assertions": [[52, "external-assertions"]], "Internal assertions": [[52, "internal-assertions"]], "External stimulus": [[52, "external-stimulus"]], "More assertions / past": [[52, "more-assertions-past"]], "Assuming memory content": [[52, "assuming-memory-content"]], "Utilities and primitives": [[52, "utilities-and-primitives"]], "Assertions / clock / reset": [[52, "assertions-clock-reset"]], "Specifying the initial value of a signal": [[52, "specifying-the-initial-value-of-a-signal"]], "Specifying a initial assumption": [[52, "specifying-a-initial-assumption"]], "Memory content (Mem)": [[52, "memory-content-mem"]], "Specifying assertion in the reset scope": [[52, "specifying-assertion-in-the-reset-scope"]], "Formal primitives": [[52, "formal-primitives"]], "Limitations": [[52, "limitations"]], "Naming polices": [[52, "naming-polices"]], "For Component": [[52, "for-component"]], "For interfaces implement IMasterSlave": [[52, "for-interfaces-implement-imasterslave"]], "Core": [[53, "core"]], "Cheatsheets": [[54, "cheatsheets"]], "Lib": [[55, "lib"]], "Symbolic": [[56, "symbolic"]], "Help for VHDL people": [[57, "help-for-vhdl-people"]], "VHDL comparison": [[58, "vhdl-comparison"]], "Process": [[58, "process"]], "Implicit vs explicit definitions": [[58, "implicit-vs-explicit-definitions"]], "Clock domains": [[58, "clock-domains"], [132, "clock-domains"], [154, "clock-domains"]], "Component\u2019s internal organization": [[58, "component-s-internal-organization"]], "Safety": [[58, "safety"]], "Functions and procedures": [[58, "functions-and-procedures"]], "Buses and Interfaces": [[58, "buses-and-interfaces"]], "Signal declaration": [[58, "signal-declaration"]], "Component instantiation": [[58, "component-instantiation"]], "Casting": [[58, "casting"]], "Resizing": [[58, "resizing"]], "Parameterization": [[58, "parameterization"]], "Meta hardware description": [[58, "meta-hardware-description"]], "VHDL equivalences": [[59, "vhdl-equivalences"]], "Entity and architecture": [[59, "entity-and-architecture"]], "Signal": [[59, "signal"]], "Literals": [[59, "literals"]], "Registers": [[59, "registers"], [92, "registers"], [130, "registers"]], "Process blocks": [[59, "process-blocks"]], "Install and setup": [[60, "install-and-setup"]], "Mandatory requirements": [[60, "mandatory-requirements"]], "Installing SBT in an internet-free environment": [[60, "installing-sbt-in-an-internet-free-environment"]], "Recommended requirements": [[60, "recommended-requirements"]], "Create a SpinalHDL project": [[60, "create-a-spinalhdl-project"]], "The directory structure of a project": [[60, "the-directory-structure-of-a-project"]], "Using Spinal on SpinalHDL code": [[60, "using-spinal-on-spinalhdl-code"]], "Using Spinal from IntelliJ IDEA": [[61, "using-spinal-from-intellij-idea"]], "Using Spinal from CLI with SBT": [[62, "using-spinal-from-cli-with-sbt"]], "Basics": [[63, "basics"]], "Variables": [[63, "variables"]], "Functions": [[63, "functions"], [108, "functions"], [109, "functions"], [113, "functions"]], "Return": [[63, "return"]], "Return type inferation": [[63, "return-type-inferation"]], "Curly braces": [[63, "curly-braces"]], "Function that returns nothing": [[63, "function-that-returns-nothing"]], "Argument default values": [[63, "argument-default-values"]], "Apply": [[63, "apply"]], "Object": [[63, "object"]], "Entry point (main)": [[63, "entry-point-main"]], "Class": [[63, "class"]], "Inheritance": [[63, "inheritance"]], "Case class": [[63, "case-class"]], "Templates / Type parameterization": [[63, "templates-type-parameterization"]], "Coding conventions": [[64, "coding-conventions"]], "class vs case class": [[64, "class-vs-case-class"]], "[case] class": [[64, "case-class"]], "companion object": [[64, "companion-object"]], "function": [[64, "function"]], "instances": [[64, "instances"]], "if / when": [[64, "if-when"]], "switch": [[64, "switch"]], "Parameters": [[64, "parameters"]], "Scala Guide": [[65, "scala-guide"]], "Scala guide": [[65, "id1"]], "Interaction": [[66, "interaction"]], "How SpinalHDL works behind the API": [[66, "how-spinalhdl-works-behind-the-api"]], "Everything is a reference": [[66, "everything-is-a-reference"]], "Hardware types": [[66, "hardware-types"]], "RGB example": [[66, "rgb-example"]], "Names of signals in the generated RTL": [[66, "names-of-signals-in-the-generated-rtl"]], "Scala is for elaboration, SpinalHDL for hardware description": [[66, "scala-is-for-elaboration-spinalhdl-for-hardware-description"]], "Scala elaboration capabilities (if, for, functional programming)": [[66, "scala-elaboration-capabilities-if-for-functional-programming"]], "Using Spinal from VSCodium": [[67, "using-spinal-from-vscodium"]], "Getting Started": [[68, "getting-started"]], "A simple example": [[69, "a-simple-example"]], "Component": [[69, "component"]], "Ports": [[69, "ports"]], "Internal logic": [[69, "internal-logic"]], "Contributing": [[70, "contributing"]], "Getting in touch": [[71, "getting-in-touch"]], "License": [[72, "license"]], "Other learning materials": [[73, "other-learning-materials"]], "Projects using SpinalHDL": [[74, "projects-using-spinalhdl"]], "Repositories": [[74, "repositories"]], "Companies": [[74, "companies"]], "Universities": [[74, "universities"]], "About SpinalHDL": [[75, "about-spinalhdl"]], "What is SpinalHDL?": [[75, "what-is-spinalhdl"]], "What SpinalHDL is not": [[75, "what-spinalhdl-is-not"]], "The Spinal development flow": [[75, "the-spinal-development-flow"]], "Advantages of using SpinalHDL over VHDL / Verilog": [[75, "advantages-of-using-spinalhdl-over-vhdl-verilog"]], "FAQ": [[76, "faq"]], "What is the overhead of SpinalHDL generated RTL compared to human written VHDL/Verilog?": [[76, "what-is-the-overhead-of-spinalhdl-generated-rtl-compared-to-human-written-vhdl-verilog"]], "What if SpinalHDL becomes unsupported in the future?": [[76, "what-if-spinalhdl-becomes-unsupported-in-the-future"]], "Does SpinalHDL keep comments in generated VHDL/verilog?": [[76, "does-spinalhdl-keep-comments-in-generated-vhdl-verilog"]], "Could SpinalHDL scale up to big projects?": [[76, "could-spinalhdl-scale-up-to-big-projects"]], "How SpinalHDL came to be": [[76, "how-spinalhdl-came-to-be"]], "Why develop a new language when there is VHDL/Verilog/SystemVerilog?": [[76, "why-develop-a-new-language-when-there-is-vhdl-verilog-systemverilog"]], "How to use an unreleased version of SpinalHDL (but committed on git)?": [[76, "how-to-use-an-unreleased-version-of-spinalhdl-but-committed-on-git"]], "Legacy": [[78, "legacy"]], "Hardware": [[79, "hardware"]], "RISCV": [[79, "riscv"]], "AXI4": [[79, "axi4"]], "APB3": [[79, "apb3"]], "Generate the RTL": [[79, "generate-the-rtl"]], "SoC toplevel (Pinsec)": [[80, "soc-toplevel-pinsec"]], "Defining all IO": [[80, "defining-all-io"]], "Clock and resets": [[80, "clock-and-resets"]], "Reset controller": [[80, "reset-controller"]], "Clock domain setup for each system": [[80, "clock-domain-setup-for-each-system"]], "Main components": [[80, "main-components"]], "RISCV CPU": [[80, "riscv-cpu"]], "On chip RAM": [[80, "on-chip-ram"]], "SDRAM controller": [[80, "sdram-controller"]], "JTAG controller": [[80, "jtag-controller"]], "Peripherals": [[80, "peripherals"]], "GPIO": [[80, "gpio"]], "UART controller": [[80, "uart-controller"]], "VGA controller": [[80, "vga-controller"], [99, "vga-controller"]], "Bus interconnects": [[80, "bus-interconnects"]], "AXI4 to APB3 bridge": [[80, "axi4-to-apb3-bridge"]], "AXI4 crossbar": [[80, "axi4-crossbar"]], "APB3 decoder": [[80, "apb3-decoder"]], "pinsec": [[81, "pinsec"]], "Board support": [[82, "board-support"]], "Software": [[83, "software"]], "RISCV tool-chain": [[83, "riscv-tool-chain"]], "OpenOCD/GDB/Eclipse configuration": [[83, "openocd-gdb-eclipse-configuration"]], "RiscV": [[84, "riscv"]], "Features": [[84, "features"]], "Base FPGA project": [[84, "base-fpga-project"]], "How to generate the CPU VHDL": [[84, "how-to-generate-the-cpu-vhdl"]], "How to debug": [[84, "how-to-debug"]], "Todo": [[84, "todo"]], "AHB-Lite3": [[85, "ahb-lite3"]], "Configuration and instanciation": [[85, "configuration-and-instanciation"], [86, "configuration-and-instanciation"], [87, "configuration-and-instanciation"], [88, "configuration-and-instanciation"]], "Variations": [[85, "variations"], [87, "variations"]], "Apb3": [[86, "apb3"]], "Functions and operators": [[86, "functions-and-operators"], [87, "functions-and-operators"]], "Axi4": [[87, "axi4"]], "AvalonMM": [[88, "avalonmm"]], "Bus": [[89, "bus"]], "Com": [[90, "com"]], "Bus definition": [[91, "bus-definition"]], "USB device": [[92, "usb-device"]], "Architecture": [[92, "architecture"]], "FRAME (0xFF00)": [[92, "frame-0xff00"]], "ADDRESS (0xFF04)": [[92, "address-0xff04"]], "INTERRUPT (0xFF08)": [[92, "interrupt-0xff08"]], "HALT (0xFF0C)": [[92, "halt-0xff0c"]], "CONFIG (0xFF10)": [[92, "config-0xff10"]], "INFO (0xFF20)": [[92, "info-0xff20"]], "ENDPOINTS (0x0000 - 0x003F)": [[92, "endpoints-0x0000-0x003f"]], "SETUP_DATA (0x0040 - 0x0047)": [[92, "setup-data-0x0040-0x0047"]], "Descriptors": [[92, "descriptors"]], "USB OHCI": [[93, "usb-ohci"]], "QSysify": [[94, "qsysify"]], "tags": [[94, "tags"]], "AvalonMM / APB3": [[94, "avalonmm-apb3"]], "Interrupt input": [[94, "interrupt-input"]], "Reset output": [[94, "reset-output"]], "Adding new interface support": [[94, "adding-new-interface-support"]], "QuartusFlow": [[95, "quartusflow"]], "For a single rtl file": [[95, "for-a-single-rtl-file"]], "Tip": [[95, "tip"]], "For an existing project": [[95, "for-an-existing-project"]], "EDA": [[96, "eda"]], "Colors": [[97, "colors"]], "RGB": [[97, "rgb"]], "Graphics": [[98, "graphics"]], "IO": [[100, "io"]], "ReadableOpenDrain": [[101, "readableopendrain"]], "TriState": [[102, "tristate"], [102, "id1"]], "TriStateArray": [[102, "tristatearray"]], "Plic Mapper": [[103, "plic-mapper"]], "PlicMapper.apply": [[103, "plicmapper-apply"]], "PlicMapping.sifive": [[103, "plicmapping-sifive"]], "PlicMapping.light": [[103, "plicmapping-light"]], "BinarySystem": [[105, "binarysystem"]], "String to Int/Long/BigInt": [[105, "string-to-int-long-bigint"]], "Int/Long/BigInt to String": [[105, "int-long-bigint-to-string"]], "Int/Long/BigInt to Binary-List": [[105, "int-long-bigint-to-binary-list"]], "Binary-List to Int/Long/BigInt": [[105, "binary-list-to-int-long-bigint"]], "BigInt enricher": [[105, "bigint-enricher"]], "Bus Slave Factory": [[106, "bus-slave-factory"]], "Functionality": [[106, "functionality"]], "Fiber framework": [[107, "fiber-framework"]], "Simple dummy example": [[107, "simple-dummy-example"]], "Handle[T]": [[107, "handle-t"]], "soon(handle)": [[107, "soon-handle"]], "Flow": [[108, "flow"]], "Code example": [[108, "code-example"]], "Simulation Support": [[108, "simulation-support"]], "Fragment": [[109, "fragment"]], "State machine": [[110, "state-machine"]], "StateMachine": [[110, "statemachine"]], "Entry point": [[110, "entry-point"]], "Transitions": [[110, "transitions"]], "State encoding": [[110, "state-encoding"]], "States": [[110, "states"]], "StateDelay": [[110, "statedelay"]], "StateFsm": [[110, "statefsm"]], "StateParallelFsm": [[110, "stateparallelfsm"]], "Notes about the entry state": [[110, "notes-about-the-entry-state"]], "Libraries": [[111, "libraries"]], "RegIf": [[112, "regif"]], "Automatic allocation": [[112, "automatic-allocation"]], "28 Access Types": [[112, "access-types"]], "Automatic documentation generation": [[112, "automatic-documentation-generation"]], "Special Access Usage": [[112, "special-access-usage"]], "Byte Mask": [[112, "byte-mask"]], "Typical Example": [[112, "typical-example"]], "Interrupt Factory": [[112, "interrupt-factory"]], "IP level interrupt Factory": [[112, "ip-level-interrupt-factory"]], "SYS level interrupt merge": [[112, "sys-level-interrupt-merge"]], "Spinal Factory": [[112, "spinal-factory"]], "DefaultReadValue": [[112, "defaultreadvalue"]], "Developers Area": [[112, "developers-area"]], "Stream": [[113, "stream"]], "Semantics": [[113, "semantics"]], "Utils": [[113, "utils"], [114, "utils"], [122, "utils"], [161, "utils"]], "StreamFifo": [[113, "streamfifo"]], "StreamFifoCC": [[113, "streamfifocc"]], "StreamCCByToggle": [[113, "streamccbytoggle"]], "StreamWidthAdapter": [[113, "streamwidthadapter"]], "StreamArbiter": [[113, "streamarbiter"]], "StreamJoin": [[113, "streamjoin"]], "StreamFork": [[113, "streamfork"]], "StreamMux": [[113, "streammux"]], "StreamDemux": [[113, "streamdemux"]], "StreamDispatcherSequencial": [[113, "streamdispatchersequencial"]], "StreamTransactionExtender": [[113, "streamtransactionextender"]], "Simulation support": [[113, "simulation-support"]], "State less utilities": [[114, "state-less-utilities"]], "State full utilities": [[114, "state-full-utilities"]], "Counter": [[114, "counter"]], "Timeout": [[114, "timeout"]], "ResetCtrl": [[114, "resetctrl"]], "asyncAssertSyncDeassert": [[114, "asyncassertsyncdeassert"]], "Special utilities": [[114, "special-utilities"]], "VexRiscv (RV32IM CPU)": [[115, "vexriscv-rv32im-cpu"]], "Analog and inout": [[116, "analog-and-inout"]], "Analog": [[116, "analog"]], "inout": [[116, "inout"]], "InOutWrapper": [[116, "inoutwrapper"]], "Manually driving Analog bundles": [[116, "manually-driving-analog-bundles"]], "Assertions": [[117, "assertions"]], "Other language features": [[118, "other-language-features"]], "Report": [[119, "report"]], "ScopeProperty": [[120, "scopeproperty"]], "Stub": [[121, "stub"]], "Cat": [[122, "cat"]], "Cloning hardware datatypes": [[122, "cloning-hardware-datatypes"]], "Passing a datatype as construction parameter": [[122, "passing-a-datatype-as-construction-parameter"]], "The old way": [[122, "the-old-way"]], "The safe way": [[122, "the-safe-way"]], "Frequency and time": [[122, "frequency-and-time"]], "Binary prefix": [[122, "binary-prefix"]], "VHDL and Verilog generation": [[123, "vhdl-and-verilog-generation"]], "Generate VHDL and Verilog from a SpinalHDL Component": [[123, "generate-vhdl-and-verilog-from-a-spinalhdl-component"]], "Parametrization from Scala": [[123, "parametrization-from-scala"]], "Parametrization from shell": [[123, "parametrization-from-shell"]], "Generated VHDL and Verilog": [[123, "generated-vhdl-and-verilog"]], "Organization": [[123, "organization"]], "Combinational logic": [[123, "combinational-logic"]], "Sequential logic": [[123, "sequential-logic"], [128, "sequential-logic"]], "VHDL and Verilog attributes": [[123, "vhdl-and-verilog-attributes"]], "Width checking": [[124, "width-checking"]], "Combinatorial loops": [[124, "combinatorial-loops"]], "Semantic": [[125, "semantic"]], "Rules": [[126, "rules"]], "Concurrency": [[126, "concurrency"]], "Last valid assignment wins": [[126, "last-valid-assignment-wins"]], "Signal and register interactions with Scala (OOP reference + Functions)": [[126, "signal-and-register-interactions-with-scala-oop-reference-functions"]], "When/Switch/Mux": [[127, "when-switch-mux"]], "When": [[127, "when"]], "Switch": [[127, "switch"]], "Additional options": [[127, "additional-options"]], "Local declaration": [[127, "local-declaration"]], "Mux": [[127, "mux"]], "Bitwise selection": [[127, "bitwise-selection"]], "RAM/ROM": [[129, "ram-rom"]], "Synchronous enable quirk": [[129, "synchronous-enable-quirk"]], "Read-under-write policy": [[129, "read-under-write-policy"]], "Mixed-width ram": [[129, "mixed-width-ram"]], "Automatic blackboxing": [[129, "automatic-blackboxing"]], "Blackboxing policy": [[129, "blackboxing-policy"]], "Standard memory blackboxes": [[129, "standard-memory-blackboxes"]], "Instantiation": [[130, "instantiation"], [154, "instantiation"]], "Reset value": [[130, "reset-value"]], "Initialization value for simulation purposes": [[130, "initialization-value-for-simulation-purposes"]], "Register vectors": [[130, "register-vectors"]], "Transforming a wire into a register": [[130, "transforming-a-wire-into-a-register"]], "Boot a simulation": [[131, "boot-a-simulation"]], "Configuration": [[131, "configuration"], [154, "configuration"]], "Running multiple tests on the same hardware": [[131, "running-multiple-tests-on-the-same-hardware"]], "Throw Success or Failure of the simulation from a thread": [[131, "throw-success-or-failure-of-the-simulation-from-a-thread"]], "Stimulus API": [[132, "stimulus-api"]], "Wait API": [[132, "wait-api"]], "Callback API": [[132, "callback-api"]], "Default ClockDomain": [[132, "default-clockdomain"]], "New ClockDomain": [[132, "new-clockdomain"]], "Simulation engine": [[133, "simulation-engine"]], "Asynchronous adder": [[134, "asynchronous-adder"]], "Dual clock fifo": [[135, "dual-clock-fifo"]], "Single clock fifo": [[137, "single-clock-fifo"]], "Synchronous adder": [[138, "synchronous-adder"]], "Uart decoder": [[139, "uart-decoder"]], "Uart encoder": [[140, "uart-encoder"]], "Simulation": [[141, "simulation"]], "Setup and installation of GHDL": [[142, "setup-and-installation-of-ghdl"]], "Linux": [[142, "linux"], [143, "linux"], [145, "linux"]], "Setup and installation of Icarus Verilog": [[143, "setup-and-installation-of-icarus-verilog"]], "VCS Simulation Configuration": [[144, "vcs-simulation-configuration"]], "Environment variable": [[144, "environment-variable"]], "User defined environment setup": [[144, "user-defined-environment-setup"]], "VCS Flags": [[144, "vcs-flags"]], "Waveform generation": [[144, "waveform-generation"]], "Simulation with Blackbox": [[144, "simulation-with-blackbox"]], "Setup and installation of Verilator": [[145, "setup-and-installation-of-verilator"]], "Scala": [[145, "scala"], [146, "scala"]], "Windows": [[145, "windows"]], "From the MinGW package manager": [[145, "from-the-mingw-package-manager"]], "From source": [[145, "from-source"]], "Installation instructions": [[146, "installation-instructions"]], "Backend-dependent installation instructions": [[146, "backend-dependent-installation-instructions"]], "Sensitive API": [[147, "sensitive-api"]], "Accessing signals of the simulation": [[148, "accessing-signals-of-the-simulation"]], "Read and write signals": [[148, "read-and-write-signals"]], "Accessing signals inside the component\u2019s hierarchy": [[148, "accessing-signals-inside-the-component-s-hierarchy"]], "Simulator specific details": [[149, "simulator-specific-details"]], "How SpinalHDL simulates the hardware with Verilator backend": [[149, "how-spinalhdl-simulates-the-hardware-with-verilator-backend"]], "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend": [[149, "how-spinalhdl-simulates-the-hardware-with-ghdl-icarus-verilog-backend"]], "How SpinalHDL simulates the hardware with Synopsys VCS backend": [[149, "how-spinalhdl-simulates-the-hardware-with-synopsys-vcs-backend"]], "Performance": [[149, "performance"]], "Thread-full API": [[150, "thread-full-api"]], "Fork and join simulation threads": [[150, "fork-and-join-simulation-threads"]], "Sleep and waitUntil": [[150, "sleep-and-waituntil"]], "Thread-less API": [[151, "thread-less-api"]], "Area": [[152, "area"], [161, "area"]], "Instantiate VHDL and Verilog IP": [[153, "instantiate-vhdl-and-verilog-ip"], [161, "instantiate-vhdl-and-verilog-ip"]], "Defining an blackbox": [[153, "defining-an-blackbox"]], "Generics": [[153, "generics"]], "Instantiating a blackbox": [[153, "instantiating-a-blackbox"]], "Clock and reset mapping": [[153, "clock-and-reset-mapping"]], "io prefix": [[153, "io-prefix"]], "Rename all io of a blackbox": [[153, "rename-all-io-of-a-blackbox"]], "Add RTL\u00a0source": [[153, "add-rtl-source"]], "VHDL - No numeric type": [[153, "vhdl-no-numeric-type"]], "Internal clock": [[154, "internal-clock"]], "External clock": [[154, "external-clock"], [161, "external-clock"]], "Signal priorities in HDL generation": [[154, "signal-priorities-in-hdl-generation"]], "Context": [[154, "context"]], "Clock domain crossing": [[154, "clock-domain-crossing"]], "Special clocking Areas": [[154, "special-clocking-areas"]], "Slow\u00a0Area": [[154, "slow-area"]], "BootReset": [[154, "bootreset"]], "ResetArea": [[154, "resetarea"]], "ClockEnableArea": [[154, "clockenablearea"]], "Components and hierarchy": [[155, "components-and-hierarchy"]], "Input / output definition": [[155, "input-output-definition"]], "Pruned signals": [[155, "pruned-signals"]], "Parametrized Hardware (\u201cGeneric\u201d in VHDL, \u201cParameter\u201d in Verilog)": [[155, "parametrized-hardware-generic-in-vhdl-parameter-in-verilog"]], "Synthesized component names": [[155, "synthesized-component-names"]], "Function": [[156, "function"], [161, "function"]], "Valid Ready Payload bus": [[156, "valid-ready-payload-bus"], [161, "valid-ready-payload-bus"]], "Structuring": [[157, "structuring"]], "Preserving names": [[158, "preserving-names"]], "Nameable base class": [[158, "nameable-base-class"]], "Name extraction from Scala": [[158, "name-extraction-from-scala"]], "Area in a Component": [[158, "area-in-a-component"]], "Area in a function": [[158, "area-in-a-function"]], "Composite in a function": [[158, "composite-in-a-function"]], "Composite chains": [[158, "composite-chains"]], "Composite in a Bundle\u2019s function": [[158, "composite-in-a-bundle-s-function"]], "Unamed signal handling": [[158, "unamed-signal-handling"]], "Verilog expression splitting": [[158, "verilog-expression-splitting"]], "Verilog long expression splitting": [[158, "verilog-long-expression-splitting"]], "When statement condition": [[158, "when-statement-condition"]], "In last resort": [[158, "in-last-resort"]], "Parametrization": [[159, "parametrization"]], "Elaboration time parameters": [[159, "elaboration-time-parameters"]], "Optional hardware": [[159, "optional-hardware"]], "The spinal.core components": [[161, "the-spinal-core-components"]], "Clock domains definitions": [[161, "clock-domains-definitions"]], "Clock domain syntax": [[161, "clock-domain-syntax"]], "Clock configuration": [[161, "clock-configuration"]], "Cross Clock Domain": [[161, "cross-clock-domain"]], "When / Switch": [[161, "when-switch"]], "Component/Hierarchy": [[161, "component-hierarchy"]], "VHDL generation": [[161, "vhdl-generation"]], "Memory": [[161, "memory"]], "Element": [[162, "element"]], "Range": [[162, "range"]], "Frequent Errors": [[163, "frequent-errors"]], "Exception in thread \u201cmain\u201d java.lang.NullPointerException": [[163, "exception-in-thread-main-java-lang-nullpointerexception"]], "Signal X can\u2019t be assigned by Y": [[163, "signal-x-can-t-be-assigned-by-y"]], "Input signal X can\u2019t be assigned by Y": [[163, "input-signal-x-can-t-be-assigned-by-y"]], "Output signal X can\u2019t be assigned by Y": [[163, "output-signal-x-can-t-be-assigned-by-y"]], "Miscellaneous": [[164, "miscellaneous"]], "Spinal Hardware Description Language": [[165, "spinal-hardware-description-language"]]}, "indexentries": {}}) \ No newline at end of file diff --git a/v1.3.1/.buildinfo b/v1.3.1/.buildinfo index 977ffb55fbd..6dc3bb3a8b2 100644 --- a/v1.3.1/.buildinfo +++ b/v1.3.1/.buildinfo @@ -1,4 +1,4 @@ # Sphinx build info version 1 # This file hashes the configuration used when building these files. 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