From ca38d9834d8e11d01e884073f817766e2066c727 Mon Sep 17 00:00:00 2001 From: yportne13 Date: Sun, 4 Feb 2024 07:36:52 +0000 Subject: [PATCH 1/2] doc(regif): add description for SpinalEnum resetValue in RegIf field --- source/SpinalHDL/Libraries/regIf.rst | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/source/SpinalHDL/Libraries/regIf.rst b/source/SpinalHDL/Libraries/regIf.rst index f1b4615b24c..d2792b63a67 100644 --- a/source/SpinalHDL/Libraries/regIf.rst +++ b/source/SpinalHDL/Libraries/regIf.rst @@ -17,9 +17,9 @@ Automatic address allocation class RegBankExample extends Component { val io = new Bundle { - apb = Apb3(Apb3Config(16,32)) + apb = slave(Apb3(Apb3Config(16,32))) } - val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte) + val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte)) val M_REG0 = busif.newReg(doc="REG0") val M_REG1 = busif.newReg(doc="REG1") val M_REG2 = busif.newReg(doc="REG2") @@ -269,6 +269,19 @@ example2: interrupt raw reg with foce interface for software val raw = RAW.field(Bool(), AccessType.W1C, resetValue = 0, doc = s"raw, default 0" ) FORCE.parasiteField(raw, AccessType.W1S, resetValue = 0, doc = s"force, write 1 set, debug use" ) +**CASE6:** ``SpinalEnum`` + +When the field type is SpinalEnum, the resetValue specifies the index of the enum elements. + +.. code:: scala + + object UartCtrlTxState extends SpinalEnum(defaultEncoding = binaryOneHot) { + val sIdle, sStart, sData, sParity, sStop = newElement() + } + + val raw = M_REG2.field(UartCtrlTxState(), AccessType.RW, resetValue = 2, doc="state") + // raw will be init to sData + Byte Mask ========= From dfd9df2cb998fc8dd7db4c0098f74e373711c8f1 Mon Sep 17 00:00:00 2001 From: GiHub Action Bot Date: Sun, 4 Feb 2024 07:37:42 +0000 Subject: [PATCH 2/2] update .pot files --- .../gettext/SpinalHDL/Libraries/regIf.pot | 128 +++++----- .../LC_MESSAGES/SpinalHDL/Libraries/regIf.po | 232 +++++++++--------- 2 files changed, 190 insertions(+), 170 deletions(-) diff --git a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot index 57f6c13dabe..d52c35dcd91 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-02-04 07:37+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -62,15 +62,15 @@ msgid "Most of these come from UVM specification" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:75 -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 msgid "AccessType" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:75 -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 -#: ../../SpinalHDL/Libraries/regIf.rst:436 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 +#: ../../SpinalHDL/Libraries/regIf.rst:449 msgid "Description" msgstr "" @@ -79,8 +79,8 @@ msgid "From" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:77 -#: ../../SpinalHDL/Libraries/regIf.rst:402 -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "RO" msgstr "" @@ -117,9 +117,9 @@ msgid "UVM" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:78 -#: ../../SpinalHDL/Libraries/regIf.rst:400 -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:413 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "RW" msgstr "" @@ -192,7 +192,7 @@ msgid "w: clears all bits, r: sets all bits" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:87 -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "W1C" msgstr "" @@ -515,173 +515,181 @@ msgstr "" msgid "example2: interrupt raw reg with foce interface for software" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:273 +#: ../../SpinalHDL/Libraries/regIf.rst:272 +msgid "**CASE6:** ``SpinalEnum``" +msgstr "" + +#: ../../SpinalHDL/Libraries/regIf.rst:274 +msgid "When the field type is SpinalEnum, the resetValue specifies the index of the enum elements." +msgstr "" + +#: ../../SpinalHDL/Libraries/regIf.rst:286 msgid "Byte Mask" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:275 +#: ../../SpinalHDL/Libraries/regIf.rst:288 msgid "withStrb" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:279 +#: ../../SpinalHDL/Libraries/regIf.rst:292 msgid "Typical Example" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:281 +#: ../../SpinalHDL/Libraries/regIf.rst:294 msgid "Batch create REG-Address and fields register" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:321 +#: ../../SpinalHDL/Libraries/regIf.rst:334 msgid "Interrupt Factory" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:323 +#: ../../SpinalHDL/Libraries/regIf.rst:336 msgid "Manual writing interruption" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:366 +#: ../../SpinalHDL/Libraries/regIf.rst:379 msgid "this is a very tedious and repetitive work, a better way is to use the \"factory\" paradigm to auto-generate the documentation for each signal." msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:368 +#: ../../SpinalHDL/Libraries/regIf.rst:381 msgid "now the InterruptFactory can do that." msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:370 +#: ../../SpinalHDL/Libraries/regIf.rst:383 msgid "Easy Way create interruption:" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:394 +#: ../../SpinalHDL/Libraries/regIf.rst:407 msgid "IP level interrupt Factory" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 msgid "Register" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "RAW" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "int raw register, set by int event, clear when bus write 1" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:400 +#: ../../SpinalHDL/Libraries/regIf.rst:413 msgid "FORCE" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:400 +#: ../../SpinalHDL/Libraries/regIf.rst:413 msgid "int force register, for SW debug use" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "MASK" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "int mask register, 1: off; 0: open; defualt 1 int off" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:402 -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "STATUS" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:402 +#: ../../SpinalHDL/Libraries/regIf.rst:415 msgid "int status, Read Only, ``status = raw && ! mask``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:408 -#: ../../SpinalHDL/Libraries/regIf.rst:426 +#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:439 msgid "SpinalUsage:" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:428 msgid "SYS level interrupt merge" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "int status, RO, ``status = int_level && ! mask``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:433 +#: ../../SpinalHDL/Libraries/regIf.rst:446 msgid "Spinal Factory" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:436 +#: ../../SpinalHDL/Libraries/regIf.rst:449 msgid "BusInterface method" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:438 -#: ../../SpinalHDL/Libraries/regIf.rst:440 +#: ../../SpinalHDL/Libraries/regIf.rst:451 +#: ../../SpinalHDL/Libraries/regIf.rst:453 msgid "``InterruptFactory(regNamePre: String, triggers: Bool*)``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:438 +#: ../../SpinalHDL/Libraries/regIf.rst:451 msgid "create RAW/FORCE/MASK/STATUS for pulse event" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:439 +#: ../../SpinalHDL/Libraries/regIf.rst:452 msgid "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:439 +#: ../../SpinalHDL/Libraries/regIf.rst:452 msgid "create RAW/MASK/STATUS for pulse event" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:440 +#: ../../SpinalHDL/Libraries/regIf.rst:453 msgid "create MASK/STATUS for level_int merge" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:441 -#: ../../SpinalHDL/Libraries/regIf.rst:443 +#: ../../SpinalHDL/Libraries/regIf.rst:454 +#: ../../SpinalHDL/Libraries/regIf.rst:456 msgid "``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:441 +#: ../../SpinalHDL/Libraries/regIf.rst:454 msgid "create RAW/FORCE/MASK/STATUS for pulse event at addrOffset" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:442 +#: ../../SpinalHDL/Libraries/regIf.rst:455 msgid "``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:442 +#: ../../SpinalHDL/Libraries/regIf.rst:455 msgid "create RAW/MASK/STATUS for pulse event at addrOffset" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:443 +#: ../../SpinalHDL/Libraries/regIf.rst:456 msgid "create MASK/STATUS for level_int merge at addrOffset" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:447 +#: ../../SpinalHDL/Libraries/regIf.rst:460 msgid "Example" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:479 +#: ../../SpinalHDL/Libraries/regIf.rst:492 msgid "DefaultReadValue" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:481 +#: ../../SpinalHDL/Libraries/regIf.rst:494 msgid "When the software reads a reserved address, the current policy is to return normally, readerror=0. In order to facilitate software debugging, the read back value can be configured, which is 0 by default" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:499 +#: ../../SpinalHDL/Libraries/regIf.rst:512 msgid "Developers Area" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:501 +#: ../../SpinalHDL/Libraries/regIf.rst:514 msgid "You can add your document Type by extending the `BusIfVistor` Trait" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:503 +#: ../../SpinalHDL/Libraries/regIf.rst:516 msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" msgstr "" -#: ../../SpinalHDL/Libraries/regIf.rst:505 +#: ../../SpinalHDL/Libraries/regIf.rst:518 msgid "BusIfVistor give access BusIf.RegInsts to do what you want" msgstr "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po index 456a8b817d2..e29ae140c6b 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-02-04 07:37+0000\n" "PO-Revision-Date: 2024-01-25 03:01+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.14.0\n" #: ../../SpinalHDL/Libraries/regIf.rst:3 msgid "RegIf" @@ -33,7 +36,8 @@ msgstr "自动寻址、字段分配和冲突检测" #: ../../SpinalHDL/Libraries/regIf.rst:8 msgid "" -"28 Register Access types (Covering the 25 types defined by the UVM standard)" +"28 Register Access types (Covering the 25 types defined by the UVM " +"standard)" msgstr "28种寄存器访问类型（涵盖UVM标准定义的25种类型）" #: ../../SpinalHDL/Libraries/regIf.rst:9 @@ -66,15 +70,15 @@ msgid "Most of these come from UVM specification" msgstr "其中大部分来自UVM规范" #: ../../SpinalHDL/Libraries/regIf.rst:75 -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 msgid "AccessType" msgstr "访问类型" #: ../../SpinalHDL/Libraries/regIf.rst:75 -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 -#: ../../SpinalHDL/Libraries/regIf.rst:436 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 +#: ../../SpinalHDL/Libraries/regIf.rst:449 msgid "Description" msgstr "描述" @@ -83,8 +87,8 @@ msgid "From" msgstr "来源" #: ../../SpinalHDL/Libraries/regIf.rst:77 -#: ../../SpinalHDL/Libraries/regIf.rst:402 -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "RO" msgstr "RO" @@ -121,9 +125,9 @@ msgid "UVM" msgstr "UVM" #: ../../SpinalHDL/Libraries/regIf.rst:78 -#: ../../SpinalHDL/Libraries/regIf.rst:400 -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:413 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "RW" msgstr "RW" @@ -196,7 +200,7 @@ msgid "w: clears all bits, r: sets all bits" msgstr "w：清除所有比特，r：置位所有比特" #: ../../SpinalHDL/Libraries/regIf.rst:87 -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "W1C" msgstr "W1C" @@ -315,8 +319,7 @@ msgid "WO1" msgstr "WO1" #: ../../SpinalHDL/Libraries/regIf.rst:101 -msgid "" -"w: first one after hard reset is as-is, other w have no effects, r: error" +msgid "w: first one after hard reset is as-is, other w have no effects, r: error" msgstr "w：硬复位后第一个w保持原样，其他w无影响，r：错误" #: ../../SpinalHDL/Libraries/regIf.rst:102 @@ -407,8 +410,7 @@ msgstr "HTML" #: ../../SpinalHDL/Libraries/regIf.rst:119 msgid "``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``" -msgstr "" -"``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``" +msgstr "``busif.accept(HtmlGenerator(\"regif\", title = \"XXX register file\"))``" #: ../../SpinalHDL/Libraries/regIf.rst:119 #: ../../SpinalHDL/Libraries/regIf.rst:120 @@ -451,8 +453,8 @@ msgid "" "``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", " "Some(\"name\"), Some(\"desc\")))``" msgstr "" -"``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", Some(\"name\")" -", Some(\"desc\")))``" +"``busif.accept(SystemRdlGenerator(\"regif\", \"addrmap_name\", " +"Some(\"name\"), Some(\"desc\")))``" #: ../../SpinalHDL/Libraries/regIf.rst:124 msgid "Latex(pdf)" @@ -486,10 +488,9 @@ msgstr "**案例1：** ``RO`` 用法" #: ../../SpinalHDL/Libraries/regIf.rst:143 msgid "" "``RO`` is different from other types. It does not create registers and " -"requires an external signal to drive it, Attention, please don't forget to " -"drive it." -msgstr "``RO`` 与其他类型不同。它不创建寄存器，需要外部信号来驱动它，注意，请不要忘记" -"驱动它。" +"requires an external signal to drive it, Attention, please don't forget " +"to drive it." +msgstr "``RO`` 与其他类型不同。它不创建寄存器，需要外部信号来驱动它，注意，请不要忘记驱动它。" #: ../../SpinalHDL/Libraries/regIf.rst:175 msgid "**CASE2:** ``ROV`` usage" @@ -497,8 +498,8 @@ msgstr "**案例2：** ``ROV`` 用法" #: ../../SpinalHDL/Libraries/regIf.rst:177 msgid "" -"ASIC design often requires some solidified version information. Unlike RO, " -"it is not expected to generate wire signals" +"ASIC design often requires some solidified version information. Unlike " +"RO, it is not expected to generate wire signals" msgstr "ASIC设计常常需要一些固化的版本信息。与 RO 不同，它不会产生有线信号" #: ../../SpinalHDL/Libraries/regIf.rst:179 @@ -511,22 +512,21 @@ msgstr "新方法：" #: ../../SpinalHDL/Libraries/regIf.rst:194 msgid "" -"**CASE3:** ``HSRW/RWHS`` hardware set type In some cases, such registers are" -" not only configured by software, but also set by hardware signals" -msgstr "**案例3:** ``HSRW/RWHS`` 在某些情况下的硬件设置类型，此类寄存器不仅可以由软件" -"配置，还可以由硬件信号设置" +"**CASE3:** ``HSRW/RWHS`` hardware set type In some cases, such registers " +"are not only configured by software, but also set by hardware signals" +msgstr "**案例3:** ``HSRW/RWHS`` 在某些情况下的硬件设置类型，此类寄存器不仅可以由软件配置，还可以由硬件信号设置" #: ../../SpinalHDL/Libraries/regIf.rst:231 msgid "" "**CASE4:** ``CSTM`` Although SpinalHDL includes 25 register types and 6 " -"extension types, there are still various demands for private register types " -"in practical application. Therefore, we reserve CSTM types for scalability. " -"CSTM is only used to generate software interfaces, and does not generate " -"actual circuits" +"extension types, there are still various demands for private register " +"types in practical application. Therefore, we reserve CSTM types for " +"scalability. CSTM is only used to generate software interfaces, and does " +"not generate actual circuits" msgstr "" -"**案例4:** ``CSTM`` 虽然SpinalHDL包含25种寄存器类型和6种扩展类型，但在实际应" -"用中仍然对私有寄存器类型有各种需求。因此，我们保留CSTM类型以实现可扩展性。 " -"CSTM仅用于生成软件接口，不生成实际电路" +"**案例4:** ``CSTM`` " +"虽然SpinalHDL包含25种寄存器类型和6种扩展类型，但在实际应用中仍然对私有寄存器类型有各种需求。因此，我们保留CSTM类型以实现可扩展性。" +" CSTM仅用于生成软件接口，不生成实际电路" #: ../../SpinalHDL/Libraries/regIf.rst:246 msgid "**CASE5:** ``parasiteField``" @@ -546,189 +546,201 @@ msgstr "示例1：时钟门软件使能" msgid "example2: interrupt raw reg with foce interface for software" msgstr "示例2：使用软件的带强制(force)接口的中断原始(raw)状态寄存器" -#: ../../SpinalHDL/Libraries/regIf.rst:273 +#: ../../SpinalHDL/Libraries/regIf.rst:272 +#, fuzzy +msgid "**CASE6:** ``SpinalEnum``" +msgstr "**案例5：** ``parasiteField``" + +#: ../../SpinalHDL/Libraries/regIf.rst:274 +msgid "" +"When the field type is SpinalEnum, the resetValue specifies the index of " +"the enum elements." +msgstr "" + +#: ../../SpinalHDL/Libraries/regIf.rst:286 msgid "Byte Mask" msgstr "字节掩码" -#: ../../SpinalHDL/Libraries/regIf.rst:275 +#: ../../SpinalHDL/Libraries/regIf.rst:288 msgid "withStrb" msgstr "withStrb" -#: ../../SpinalHDL/Libraries/regIf.rst:279 +#: ../../SpinalHDL/Libraries/regIf.rst:292 msgid "Typical Example" msgstr "典型例子" -#: ../../SpinalHDL/Libraries/regIf.rst:281 +#: ../../SpinalHDL/Libraries/regIf.rst:294 msgid "Batch create REG-Address and fields register" msgstr "批量创建REG-Address和字段寄存器" -#: ../../SpinalHDL/Libraries/regIf.rst:321 +#: ../../SpinalHDL/Libraries/regIf.rst:334 msgid "Interrupt Factory" msgstr "中断生成器" -#: ../../SpinalHDL/Libraries/regIf.rst:323 +#: ../../SpinalHDL/Libraries/regIf.rst:336 msgid "Manual writing interruption" msgstr "手动写中断" -#: ../../SpinalHDL/Libraries/regIf.rst:366 +#: ../../SpinalHDL/Libraries/regIf.rst:379 msgid "" "this is a very tedious and repetitive work, a better way is to use the " "\"factory\" paradigm to auto-generate the documentation for each signal." -msgstr "这是一项非常繁琐且重复的工作，更好的方法是使用“生成器(factory)”范例来自动生成" -"每个信号的文档。" +msgstr "这是一项非常繁琐且重复的工作，更好的方法是使用“生成器(factory)”范例来自动生成每个信号的文档。" -#: ../../SpinalHDL/Libraries/regIf.rst:368 +#: ../../SpinalHDL/Libraries/regIf.rst:381 msgid "now the InterruptFactory can do that." msgstr "现在InterruptFactory可以做到这一点。" -#: ../../SpinalHDL/Libraries/regIf.rst:370 +#: ../../SpinalHDL/Libraries/regIf.rst:383 msgid "Easy Way create interruption:" msgstr "创建中断的简单方法：" -#: ../../SpinalHDL/Libraries/regIf.rst:394 +#: ../../SpinalHDL/Libraries/regIf.rst:407 msgid "IP level interrupt Factory" msgstr "IP级中断生成器" -#: ../../SpinalHDL/Libraries/regIf.rst:397 -#: ../../SpinalHDL/Libraries/regIf.rst:418 +#: ../../SpinalHDL/Libraries/regIf.rst:410 +#: ../../SpinalHDL/Libraries/regIf.rst:431 msgid "Register" msgstr "寄存器" -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "RAW" msgstr "RAW" -#: ../../SpinalHDL/Libraries/regIf.rst:399 +#: ../../SpinalHDL/Libraries/regIf.rst:412 msgid "int raw register, set by int event, clear when bus write 1" msgstr "中断原始状态(int raw)寄存器，由int事件设置，总线写1时清零" -#: ../../SpinalHDL/Libraries/regIf.rst:400 +#: ../../SpinalHDL/Libraries/regIf.rst:413 msgid "FORCE" msgstr "FORCE" -#: ../../SpinalHDL/Libraries/regIf.rst:400 +#: ../../SpinalHDL/Libraries/regIf.rst:413 msgid "int force register, for SW debug use" msgstr "中断强制寄存器，用于软件调试" -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "MASK" msgstr "MASK" -#: ../../SpinalHDL/Libraries/regIf.rst:401 -#: ../../SpinalHDL/Libraries/regIf.rst:420 +#: ../../SpinalHDL/Libraries/regIf.rst:414 +#: ../../SpinalHDL/Libraries/regIf.rst:433 msgid "int mask register, 1: off; 0: open; defualt 1 int off" msgstr "中断掩码寄存器，1：关闭；0：打开；默认1 中断关闭" -#: ../../SpinalHDL/Libraries/regIf.rst:402 -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "STATUS" msgstr "STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:402 +#: ../../SpinalHDL/Libraries/regIf.rst:415 msgid "int status, Read Only, ``status = raw && ! mask``" msgstr "中断状态，只读， ``status = raw && ! mask``" -#: ../../SpinalHDL/Libraries/regIf.rst:408 -#: ../../SpinalHDL/Libraries/regIf.rst:426 +#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:439 msgid "SpinalUsage:" msgstr "Spinal用法：" -#: ../../SpinalHDL/Libraries/regIf.rst:415 +#: ../../SpinalHDL/Libraries/regIf.rst:428 msgid "SYS level interrupt merge" msgstr "SYS级中断合并" -#: ../../SpinalHDL/Libraries/regIf.rst:421 +#: ../../SpinalHDL/Libraries/regIf.rst:434 msgid "int status, RO, ``status = int_level && ! mask``" msgstr "中断状态，RO， ``status = int_level && ! mask``" -#: ../../SpinalHDL/Libraries/regIf.rst:433 +#: ../../SpinalHDL/Libraries/regIf.rst:446 msgid "Spinal Factory" msgstr "Spinal的生成器" -#: ../../SpinalHDL/Libraries/regIf.rst:436 +#: ../../SpinalHDL/Libraries/regIf.rst:449 msgid "BusInterface method" msgstr "总线接口方法" -#: ../../SpinalHDL/Libraries/regIf.rst:438 -#: ../../SpinalHDL/Libraries/regIf.rst:440 +#: ../../SpinalHDL/Libraries/regIf.rst:451 +#: ../../SpinalHDL/Libraries/regIf.rst:453 msgid "``InterruptFactory(regNamePre: String, triggers: Bool*)``" msgstr "``InterruptFactory(regNamePre: String, triggers: Bool*)``" -#: ../../SpinalHDL/Libraries/regIf.rst:438 +#: ../../SpinalHDL/Libraries/regIf.rst:451 msgid "create RAW/FORCE/MASK/STATUS for pulse event" msgstr "为脉冲事件创建RAW/FORCE/MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:439 +#: ../../SpinalHDL/Libraries/regIf.rst:452 msgid "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``" msgstr "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``" -#: ../../SpinalHDL/Libraries/regIf.rst:439 +#: ../../SpinalHDL/Libraries/regIf.rst:452 msgid "create RAW/MASK/STATUS for pulse event" msgstr "为脉冲事件创建RAW/MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:440 +#: ../../SpinalHDL/Libraries/regIf.rst:453 msgid "create MASK/STATUS for level_int merge" msgstr "为level_int合并创建MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:441 -#: ../../SpinalHDL/Libraries/regIf.rst:443 +#: ../../SpinalHDL/Libraries/regIf.rst:454 +#: ../../SpinalHDL/Libraries/regIf.rst:456 msgid "" -"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``" +"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: " +"Bool*)``" msgstr "" -"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``" +"``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: " +"Bool*)``" -#: ../../SpinalHDL/Libraries/regIf.rst:441 +#: ../../SpinalHDL/Libraries/regIf.rst:454 msgid "create RAW/FORCE/MASK/STATUS for pulse event at addrOffset" msgstr "在addrOffset处为脉冲事件创建RAW/FORCE/MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:442 +#: ../../SpinalHDL/Libraries/regIf.rst:455 msgid "" -"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: " -"Bool*)``" +"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, " +"triggers: Bool*)``" msgstr "" -"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: " -"Bool*)``" +"``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, " +"triggers: Bool*)``" -#: ../../SpinalHDL/Libraries/regIf.rst:442 +#: ../../SpinalHDL/Libraries/regIf.rst:455 msgid "create RAW/MASK/STATUS for pulse event at addrOffset" msgstr "在addrOffset处为脉冲事件创建 RAW/MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:443 +#: ../../SpinalHDL/Libraries/regIf.rst:456 msgid "create MASK/STATUS for level_int merge at addrOffset" msgstr "在addrOffset处为level_int合并创建MASK/STATUS" -#: ../../SpinalHDL/Libraries/regIf.rst:447 +#: ../../SpinalHDL/Libraries/regIf.rst:460 msgid "Example" msgstr "示例" -#: ../../SpinalHDL/Libraries/regIf.rst:479 +#: ../../SpinalHDL/Libraries/regIf.rst:492 msgid "DefaultReadValue" msgstr "默认读取值" -#: ../../SpinalHDL/Libraries/regIf.rst:481 +#: ../../SpinalHDL/Libraries/regIf.rst:494 msgid "" -"When the software reads a reserved address, the current policy is to return " -"normally, readerror=0. In order to facilitate software debugging, the read " -"back value can be configured, which is 0 by default" -msgstr "当软件读取保留地址时，当前的策略是正常返回，readerror=0。为了方便软件调试，可" -"以配置回读值，默认为0" +"When the software reads a reserved address, the current policy is to " +"return normally, readerror=0. In order to facilitate software debugging, " +"the read back value can be configured, which is 0 by default" +msgstr "当软件读取保留地址时，当前的策略是正常返回，readerror=0。为了方便软件调试，可以配置回读值，默认为0" -#: ../../SpinalHDL/Libraries/regIf.rst:499 +#: ../../SpinalHDL/Libraries/regIf.rst:512 msgid "Developers Area" msgstr "开发者区域" -#: ../../SpinalHDL/Libraries/regIf.rst:501 +#: ../../SpinalHDL/Libraries/regIf.rst:514 msgid "You can add your document Type by extending the `BusIfVistor` Trait" msgstr "您可以通过扩展 `BusIfVistor` 特征来添加文档类型" -#: ../../SpinalHDL/Libraries/regIf.rst:503 +#: ../../SpinalHDL/Libraries/regIf.rst:516 msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" msgstr "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" -#: ../../SpinalHDL/Libraries/regIf.rst:505 +#: ../../SpinalHDL/Libraries/regIf.rst:518 msgid "BusIfVistor give access BusIf.RegInsts to do what you want" msgstr "BusIfVistor给予访问BusIf.RegInsts的权限来执行您想要的操作" #~ msgid "Interrupt Design Spec" #~ msgstr "中断设计规范" +