From 0516319799d318bbdf6307c53ab7f7ba59dee637 Mon Sep 17 00:00:00 2001 From: Marc Emery Date: Wed, 26 Jun 2024 23:20:40 +0200 Subject: [PATCH] Update the supported BusSlaveFactory buses Based on implementations present in directory /lib/src/main/scala/spinal/lib/bus of spinalHDL v1.10.2 . --- source/SpinalHDL/Libraries/bus_slave_factory.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/SpinalHDL/Libraries/bus_slave_factory.rst b/source/SpinalHDL/Libraries/bus_slave_factory.rst index 3903c6707ac..50b68ec4287 100644 --- a/source/SpinalHDL/Libraries/bus_slave_factory.rst +++ b/source/SpinalHDL/Libraries/bus_slave_factory.rst @@ -18,7 +18,7 @@ You can find more documentation about the internal implementation of the ``BusSl Functionality ------------- -| There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus. +| There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone, Tilelink, BRAM bus and PipelinedMemoryBus. | Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping : .. list-table::