From e56bd5a599e1f0645157bc9f83799cb873b16137 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:19:43 +0100 Subject: [PATCH 01/14] AhbLite3.py: assignment <= is deprecated --- AhbLite3.py | 70 ++++++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 442a9f0..8271947 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -8,14 +8,14 @@ def AhbLite3MasterIdle(ahb): - ahb.HADDR <= 0 - ahb.HWRITE <= 0 - ahb.HSIZE <= 0 - ahb.HBURST <= 0 - ahb.HPROT <= 0 - ahb.HTRANS <= 0 - ahb.HMASTLOCK <= 0 - ahb.HWDATA <= 0 + ahb.HADDR.value = 0 + ahb.HWRITE.value = 0 + ahb.HSIZE.value = 0 + ahb.HBURST.value = 0 + ahb.HPROT.value = 0 + ahb.HTRANS.value = 0 + ahb.HMASTLOCK.value = 0 + ahb.HWDATA.value = 0 @@ -108,14 +108,14 @@ def __init__(self,ahb,transactor,clk,reset): @cocotb.coroutine def stim(self): ahb = self.ahb - ahb.HADDR <= 0 - ahb.HWRITE <= 0 - ahb.HSIZE <= 0 - ahb.HBURST <= 0 - ahb.HPROT <= 0 - ahb.HTRANS <= 0 - ahb.HMASTLOCK <= 0 - ahb.HWDATA <= 0 + ahb.HADDR.value = 0 + ahb.HWRITE.value = 0 + ahb.HSIZE.value = 0 + ahb.HBURST.value = 0 + ahb.HPROT.value = 0 + ahb.HTRANS.value = 0 + ahb.HMASTLOCK.value = 0 + ahb.HWDATA.value = 0 HWDATAbuffer = 0 while True: for trans in self.transactor.getTransactions(): @@ -123,14 +123,14 @@ def stim(self): while int(self.ahb.HREADY) == 0: yield RisingEdge(self.clk) - ahb.HADDR <= trans.HADDR - ahb.HWRITE <= trans.HWRITE - ahb.HSIZE <= trans.HSIZE - ahb.HBURST <= trans.HBURST - ahb.HPROT <= trans.HPROT - ahb.HTRANS <= trans.HTRANS - ahb.HMASTLOCK <= trans.HMASTLOCK - ahb.HWDATA <= HWDATAbuffer + ahb.HADDR.value = trans.HADDR + ahb.HWRITE.value = trans.HWRITE + ahb.HSIZE.value = trans.HSIZE + ahb.HBURST.value = trans.HBURST + ahb.HPROT.value = trans.HPROT + ahb.HTRANS.value = trans.HTRANS + ahb.HMASTLOCK.value = trans.HMASTLOCK + ahb.HWDATA.value = HWDATAbuffer HWDATAbuffer = trans.HWDATA class AhbLite3Terminaison: @@ -145,8 +145,8 @@ def __init__(self,ahb,clk,reset): @cocotb.coroutine def stim(self): randomizer = BoolRandomizer() - self.ahb.HREADY <= 1 - self.ahb.HSEL <= 1 + self.ahb.HREADY.value = 1 + self.ahb.HSEL.value = 1 while True: yield RisingEdge(self.clk) self.randomHREADY = randomizer.get() @@ -159,7 +159,7 @@ def combEvent(self): self.doComb() def doComb(self): - self.ahb.HREADY <= (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1)) + self.ahb.HREADY.value = (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1)) class AhbLite3MasterReadChecker: @@ -210,7 +210,7 @@ def __init__(self,ahb,base,size,clk,reset): @cocotb.coroutine def stimReady(self): randomizer = BoolRandomizer() - self.ahb.HREADYOUT <= 1 + self.ahb.HREADYOUT.value = 1 busy = False while True: yield RisingEdge(self.clk) @@ -222,16 +222,16 @@ def stimReady(self): raise TestFailure("HREADYOUT == 0 but HREADY == 1 ??? " + self.ahb.HREADY._name) busy = busyNew if (busy): - self.ahb.HREADYOUT <= randomizer.get() # make some random delay for NONSEQ and SEQ requests + self.ahb.HREADYOUT.value = randomizer.get() # make some random delay for NONSEQ and SEQ requests else: - self.ahb.HREADYOUT <= 1 # IDLE and BUSY require 0 WS + self.ahb.HREADYOUT.value = 1 # IDLE and BUSY require 0 WS @cocotb.coroutine def stim(self): ahb = self.ahb - ahb.HREADYOUT <= 1 - ahb.HRESP <= 0 - ahb.HRDATA <= 0 + ahb.HREADYOUT.value = 1 + ahb.HRESP.value = 0 + ahb.HRDATA.value = 0 valid = 0 while True: yield RisingEdge(self.clk) @@ -252,7 +252,7 @@ def stim(self): address = int(ahb.HADDR) addressOffset = address % (len(ahb.HWDATA)//8) - ahb.HRDATA <= 0 + ahb.HRDATA.value = 0 if valid == 1: if trans >= 2: if write == 0: @@ -261,4 +261,4 @@ def stim(self): data |= self.ram[address-self.base + idx] << (8*(addressOffset + idx)) # print("read %x with %x" % (address + idx, self.ram[address-self.base + idx])) # print(str(data)) - ahb.HRDATA <= int(data) + ahb.HRDATA.value = int(data) From bf4b5c2334a477c4182a99ad96ef357e89defd97 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:20:52 +0100 Subject: [PATCH 02/14] Apb3.py: assignment <= is deprecated --- Apb3.py | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/Apb3.py b/Apb3.py index 9fe0efb..49fa31e 100644 --- a/Apb3.py +++ b/Apb3.py @@ -20,7 +20,7 @@ def __init__(self, dut, name, clk = None): self.PRDATA = dut.__getattr__(name + "_PRDATA") def idle(self): - self.PSEL <= 0 + self.PSEL.value = 0 @coroutine def delay(self, cycle): @@ -29,16 +29,16 @@ def delay(self, cycle): @coroutine def write(self, address, data, sel = 1): - self.PADDR <= address - self.PSEL <= sel - self.PENABLE <= False - self.PWRITE <= True - self.PWDATA <= data + self.PADDR.value = address + self.PSEL.value = sel + self.PENABLE.value = False + self.PWRITE.value = True + self.PWDATA.value = data yield RisingEdge(self.clk) - self.PENABLE <= True + self.PENABLE.value = True yield waitClockedCond(self.clk, lambda : self.PREADY == True) randSignal(self.PADDR) - self.PSEL <= 0 + self.PSEL.value = 0 randSignal(self.PENABLE) randSignal(self.PWRITE) randSignal(self.PWDATA) @@ -51,16 +51,16 @@ def writeMasked(self, address, data, mask, sel = 1): @coroutine def read(self, address, sel=1): - self.PADDR <= address - self.PSEL <= sel - self.PENABLE <= False - self.PWRITE <= False + self.PADDR.value = address + self.PSEL.value = sel + self.PENABLE.value = False + self.PWRITE.value = False randSignal(self.PWDATA) yield RisingEdge(self.clk) - self.PENABLE <= True + self.PENABLE.value = True yield waitClockedCond(self.clk, lambda: self.PREADY == True) randSignal(self.PADDR) - self.PSEL <= 0 + self.PSEL.value = 0 randSignal(self.PENABLE) randSignal(self.PWRITE) raise ReturnValue(int(self.PRDATA)) From e62262897e00306e2be33754032b943fcda9275c Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:23:33 +0100 Subject: [PATCH 03/14] Axi4.py: assignment <= is deprecated --- Axi4.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Axi4.py b/Axi4.py index cfc21d6..401f6d3 100644 --- a/Axi4.py +++ b/Axi4.py @@ -74,8 +74,8 @@ def __init__(self,name,parent,axi,addressWidth,clk,reset): StreamDriverMaster(axi.w, self.genWriteData, clk, reset) StreamMonitor(axi.r, self.onReadRsp, clk, reset) StreamMonitor(axi.b, self.onWriteRsp, clk, reset) - axi.w.payload.last <= 0 - axi.r.payload.last <= 0 + axi.w.payload.last.value = 0 + axi.r.payload.last.value = 0 def freeReservatedAddresses(self,uut,ref,equal): self.reservedAddresses.pop(ref,None) From 94f7f62e4a5397e70ab8208018d3ba678a35457e Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:23:36 +0100 Subject: [PATCH 04/14] ClockDomain.py: assignment <= is deprecated --- ClockDomain.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index 39bf48b..64068ef 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -50,12 +50,12 @@ def start(self): cocotb.fork(self._waitEndReset()) if self.reset: - self.reset <= self.typeReset + self.reset.value = self.typeReset yield Timer(self.halfPeriod * 5) if self.reset: - self.reset <= int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) + self.reset.value = int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) ########################################################################## @@ -70,9 +70,9 @@ def stop(self): @cocotb.coroutine def _clkGen(self): while True: - self.clk <= 0 + self.clk.value = 0 yield Timer(self.halfPeriod) - self.clk <= 1 + self.clk.value = 1 yield Timer(self.halfPeriod) From be01610e0e6f6a378374cc10ab2f031e356fee25 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:24:04 +0100 Subject: [PATCH 05/14] Spi.py: assignment <= is deprecated --- Spi.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Spi.py b/Spi.py index 7b1d7e3..d991cb0 100644 --- a/Spi.py +++ b/Spi.py @@ -40,22 +40,22 @@ def __init__(self, spi): self.dataWidth = 8 def init(self, cpol, cpha, baudrate, dataWidth = 8): - self.spi.ss <= True + self.spi.ss.value = True self.cpol = cpol self.cpha = cpha self.baudPeriode = baudrate self.dataWidth = dataWidth - self.spi.sclk <= cpol + self.spi.sclk.value = cpol @coroutine def enable(self): - self.spi.ss <= False + self.spi.ss.value = False yield Timer(self.baudPeriode) @coroutine def disable(self): yield Timer(self.baudPeriode) - self.spi.ss <= True + self.spi.ss.value = True yield Timer(self.baudPeriode) @coroutine @@ -63,19 +63,19 @@ def exchange(self, masterData): buffer = "" if not self.cpha: for i in range(self.dataWidth): - self.spi.mosi <= testBit(masterData, self.dataWidth - 1 - i) + self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk <= (not self.cpol) + self.spi.sclk.value = (not self.cpol) yield Timer(self.baudPeriode >> 1) - self.spi.sclk <= (self.cpol) + self.spi.sclk.value = (self.cpol) else: for i in range(self.dataWidth): - self.spi.mosi <= testBit(masterData, self.dataWidth -1 - i) - self.spi.sclk <= (not self.cpol) + self.spi.mosi.value = testBit(masterData, self.dataWidth -1 - i) + self.spi.sclk.value = (not self.cpol) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk <= (self.cpol) + self.spi.sclk.value = (self.cpol) yield Timer(self.baudPeriode >> 1) raise ReturnValue(buffer) From 16fc94399e463ee8a0843ebe53e71808d403ed66 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:24:57 +0100 Subject: [PATCH 06/14] Stream.py: assignment <= is deprecated --- Stream.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Stream.py b/Stream.py index 400489e..d39501e 100644 --- a/Stream.py +++ b/Stream.py @@ -94,11 +94,11 @@ def __init__(self,stream,transactor,clk,reset): @cocotb.coroutine def stim(self): stream = self.stream - stream.valid <= 0 + stream.valid.value = 0 while True: yield RisingEdge(self.clk) if int(stream.valid) == 1 and int(stream.ready) == 1: - stream.valid <= 0 + stream.valid.value = 0 for i in range(nextDelay): yield RisingEdge(self.clk) @@ -112,12 +112,12 @@ def stim(self): nextDelay = trans.nextDelay else: nextDelay = 0 - stream.valid <= 1 + stream.valid.value = 1 for name in stream.payload.nameToElement: if hasattr(trans,name) == False: raise Exception("Missing element in bundle :" + name) - e = stream.payload.nameToElement[name] <= getattr(trans,name) + e = stream.payload.nameToElement[name].value = getattr(trans,name) @@ -132,10 +132,10 @@ def __init__(self,stream,clk,reset): @cocotb.coroutine def stim(self): stream = self.stream - stream.ready <= 1 + stream.ready.value = 1 while True: yield RisingEdge(self.clk) - stream.ready <= self.randomizer.get() + stream.ready.value = self.randomizer.get() def TransactionFromBundle(bundle): From bfb831d6adcc29e4e91a49f712f0bd68bed90ec2 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:26:28 +0100 Subject: [PATCH 07/14] misc.py: assignment <= is deprecated --- misc.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/misc.py b/misc.py index 939e0ab..41a0a17 100644 --- a/misc.py +++ b/misc.py @@ -30,10 +30,10 @@ def randBits(width): return random.getrandbits(width) def randSignal(that): - that <= random.getrandbits(len(that)) + that.value = random.getrandbits(len(that)) def randBoolSignal(that,prob): - that <= (random.random() < prob) + that.value = (random.random() < prob) @coroutine @@ -86,15 +86,15 @@ def sint(signal): @cocotb.coroutine def ClockDomainAsyncReset(clk,reset,period = 1000): if reset: - reset <= 1 - clk <= 0 + reset.value = 1 + clk.value = 0 yield Timer(period) if reset: - reset <= 0 + reset.value = 0 while True: - clk <= 0 + clk.value = 0 yield Timer(period/2) - clk <= 1 + clk.value = 1 yield Timer(period/2) @cocotb.coroutine @@ -154,15 +154,15 @@ def StreamRandomizer(streamName, onNew,handle, dut, clk): ready = getattr(dut, streamName + "_ready") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - valid <= 0 + valid.value = 0 while True: yield RisingEdge(clk) if int(ready) == 1: - valid <= 0 + valid.value = 0 if int(valid) == 0 or int(ready) == 1: if validRandomizer.get(): - valid <= 1 + valid.value = 1 for e in payloads: randSignal(e) yield Timer(1) @@ -181,11 +181,11 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): valid = getattr(dut, streamName + "_valid") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - valid <= 0 + valid.value = 0 while True: yield RisingEdge(clk) if validRandomizer.get(): - valid <= 1 + valid.value = 1 for e in payloads: randSignal(e) yield Timer(1) @@ -198,7 +198,7 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): if onNew: onNew(payload,handle) else: - valid <= 0 + valid.value = 0 @cocotb.coroutine def StreamReader(streamName, onTransaction, handle, dut, clk): @@ -207,10 +207,10 @@ def StreamReader(streamName, onTransaction, handle, dut, clk): ready = getattr(dut, streamName + "_ready") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - ready <= 0 + ready.value = 0 while True: yield RisingEdge(clk) - ready <= validRandomizer.get() + ready.value = validRandomizer.get() if int(valid) == 1 and int(ready) == 1: if len(payloads) == 1 and payloads[0]._name == streamName + "_payload": payload = int(payloads[0]) From d28bc4339de8dd3bd61a937a6068fe401b2d1d14 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:29:22 +0100 Subject: [PATCH 08/14] AhbLite3.py: import local ref change --- AhbLite3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/AhbLite3.py b/AhbLite3.py index 8271947..0d2b31c 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -4,7 +4,7 @@ from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Edge -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals +from .misc import log2Up, BoolRandomizer, assertEquals def AhbLite3MasterIdle(ahb): From f13c70a13aa8b8b553022b3cdbda17dbe187de39 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:32:09 +0100 Subject: [PATCH 09/14] Apb3.py: import local ref change --- Apb3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Apb3.py b/Apb3.py index 49fa31e..dfa2780 100644 --- a/Apb3.py +++ b/Apb3.py @@ -5,7 +5,7 @@ from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal +from .misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal class Apb3: From 72cf46691271d7b79f1fbb316a66656081da970c Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:32:23 +0100 Subject: [PATCH 10/14] Axi4.py: import local ref change --- Axi4.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Axi4.py b/Axi4.py index 401f6d3..a02709e 100644 --- a/Axi4.py +++ b/Axi4.py @@ -1,11 +1,11 @@ import random from queue import Queue -from cocotblib.Phase import PHASE_SIM, Infrastructure -from cocotblib.Scorboard import ScorboardOutOfOrder -from cocotblib.misc import BoolRandomizer, log2Up, randBits +from .Phase import PHASE_SIM, Infrastructure +from .Scorboard import ScorboardOutOfOrder +from .misc import BoolRandomizer, log2Up, randBits -from cocotblib.Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor +from .Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor class Axi4: From 17baf5ed1d674504fbd44c0dfdbfe54646e38ac3 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:34:50 +0100 Subject: [PATCH 11/14] Flow.py: import local ref change --- Flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Flow.py b/Flow.py index 8514594..911fa71 100644 --- a/Flow.py +++ b/Flow.py @@ -1,6 +1,6 @@ import cocotb from cocotb.triggers import RisingEdge, Event -from cocotblib.misc import Bundle +from .misc import Bundle ############################################################################### From 450f8555e91b31d687498746e300c77f4f65c436 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:37:41 +0100 Subject: [PATCH 12/14] Scorboard.py: import local ref change --- Scorboard.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Scorboard.py b/Scorboard.py index 5841904..37c2325 100644 --- a/Scorboard.py +++ b/Scorboard.py @@ -3,7 +3,7 @@ import cocotb from cocotb.result import TestFailure -from cocotblib.Phase import Infrastructure, PHASE_CHECK_SCORBOARDS +from .Phase import Infrastructure, PHASE_CHECK_SCORBOARDS class ScorboardInOrder(Infrastructure): From 2afed892a14466583f061dcff76e105664911df0 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:39:18 +0100 Subject: [PATCH 13/14] Spi.py: import local ref change --- Spi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Spi.py b/Spi.py index d991cb0..68dfed0 100644 --- a/Spi.py +++ b/Spi.py @@ -5,8 +5,8 @@ from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge, Timer -from cocotblib.TriState import TriStateOutput -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, testBit +from .TriState import TriStateOutput +from .misc import log2Up, BoolRandomizer, assertEquals, testBit class SpiMaster: From 1373392c34016807207cf045496e2189f7c57a4f Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:41:42 +0100 Subject: [PATCH 14/14] Stream.py: import local ref change --- Stream.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Stream.py b/Stream.py index d39501e..eff1177 100644 --- a/Stream.py +++ b/Stream.py @@ -3,10 +3,10 @@ import types from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Timer, Event -from cocotblib.Phase import Infrastructure, PHASE_WAIT_TASKS_END -from cocotblib.Scorboard import ScorboardInOrder +from .Phase import Infrastructure, PHASE_WAIT_TASKS_END +from .Scorboard import ScorboardInOrder -from cocotblib.misc import Bundle, BoolRandomizer +from .misc import Bundle, BoolRandomizer class Stream: