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ddr3_training_ip_engine.c
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ddr3_training_ip_engine.c
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/*******************************************************************************
Copyright (C) 2016 Marvell International Ltd.
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the three
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
This program is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation, either version 2 of the License, or any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
********************************************************************************
Marvell GNU General Public License FreeRTOS Exception
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the Lesser
General Public License Version 2.1 plus the following FreeRTOS exception.
An independent module is a module which is not derived from or based on
FreeRTOS.
Clause 1:
Linking FreeRTOS statically or dynamically with other modules is making a
combined work based on FreeRTOS. Thus, the terms and conditions of the GNU
General Public License cover the whole combination.
As a special exception, the copyright holder of FreeRTOS gives you permission
to link FreeRTOS with independent modules that communicate with FreeRTOS solely
through the FreeRTOS API interface, regardless of the license terms of these
independent modules, and to copy and distribute the resulting combined work
under terms of your choice, provided that:
1. Every copy of the combined work is accompanied by a written statement that
details to the recipient the version of FreeRTOS used and an offer by yourself
to provide the FreeRTOS source code (including any modifications you may have
made) should the recipient request it.
2. The combined work is not itself an RTOS, scheduler, kernel or related
product.
3. The independent modules add significant and primary functionality to
FreeRTOS and do not merely extend the existing functionality already present in
FreeRTOS.
Clause 2:
FreeRTOS may not be used for any competitive or comparative purpose, including
the publication of any form of run time or compile time metric, without the
express permission of Real Time Engineers Ltd. (this is the norm within the
industry and is intended to ensure information accuracy).
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ddr3_init.h"
#define PATTERN_1 0x55555555
#define PATTERN_2 0xaaaaaaaa
#define VALIDATE_TRAINING_LIMIT(e1, e2) \
((((e2) - (e1) + 1) > 33) && ((e1) < 67))
u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
HWS_SEARCH_DIR_LIMIT];
u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper function*/
u16 mask_results_dq_reg_map[] = {
RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG,
RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG,
RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG,
RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
#if MAX_BUS_NUM == 9
RESULT_CONTROL_PUP_5_BIT_0_REG, RESULT_CONTROL_PUP_5_BIT_1_REG,
RESULT_CONTROL_PUP_5_BIT_2_REG, RESULT_CONTROL_PUP_5_BIT_3_REG,
RESULT_CONTROL_PUP_5_BIT_4_REG, RESULT_CONTROL_PUP_5_BIT_5_REG,
RESULT_CONTROL_PUP_5_BIT_6_REG, RESULT_CONTROL_PUP_5_BIT_7_REG,
RESULT_CONTROL_PUP_6_BIT_0_REG, RESULT_CONTROL_PUP_6_BIT_1_REG,
RESULT_CONTROL_PUP_6_BIT_2_REG, RESULT_CONTROL_PUP_6_BIT_3_REG,
RESULT_CONTROL_PUP_6_BIT_4_REG, RESULT_CONTROL_PUP_6_BIT_5_REG,
RESULT_CONTROL_PUP_6_BIT_6_REG, RESULT_CONTROL_PUP_6_BIT_7_REG,
RESULT_CONTROL_PUP_7_BIT_0_REG, RESULT_CONTROL_PUP_7_BIT_1_REG,
RESULT_CONTROL_PUP_7_BIT_2_REG, RESULT_CONTROL_PUP_7_BIT_3_REG,
RESULT_CONTROL_PUP_7_BIT_4_REG, RESULT_CONTROL_PUP_7_BIT_5_REG,
RESULT_CONTROL_PUP_7_BIT_6_REG, RESULT_CONTROL_PUP_7_BIT_7_REG,
RESULT_CONTROL_PUP_8_BIT_0_REG, RESULT_CONTROL_PUP_8_BIT_1_REG,
RESULT_CONTROL_PUP_8_BIT_2_REG, RESULT_CONTROL_PUP_8_BIT_3_REG,
RESULT_CONTROL_PUP_8_BIT_4_REG, RESULT_CONTROL_PUP_8_BIT_5_REG,
RESULT_CONTROL_PUP_8_BIT_6_REG, RESULT_CONTROL_PUP_8_BIT_7_REG,
#endif
0xffff
};
u16 mask_results_pup_reg_map[] = {
RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_3_REG,
RESULT_CONTROL_BYTE_PUP_4_REG,
#if MAX_BUS_NUM == 9
RESULT_CONTROL_BYTE_PUP_5_REG, RESULT_CONTROL_BYTE_PUP_6_REG,
RESULT_CONTROL_BYTE_PUP_7_REG, RESULT_CONTROL_BYTE_PUP_8_REG,
#endif
0xffff
};
#if MAX_BUS_NUM == 5
u16 mask_results_dq_reg_map_pup3_ecc[] = {
RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG,
RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG,
RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG
};
#endif
#if MAX_BUS_NUM == 5
u16 mask_results_pup_reg_map_pup3_ecc[] = {
RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_4_REG,
RESULT_CONTROL_BYTE_PUP_4_REG
};
#endif
struct pattern_info pattern_table_64[] = {
/*
* num_of_phases_tx, tx_burst_size;
* delay_between_bursts, num_of_phases_rx,
* start_addr, pattern_len
*/
{0x7, 0x7, 2, 0x7, 0x00000, 8}, /* PATTERN_PBS1 */
{0x7, 0x7, 2, 0x7, 0x00080, 8}, /* PATTERN_PBS2 */
{0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_PBS3 */
{0x7, 0x7, 2, 0x7, 0x00030, 8}, /* PATTERN_TEST */
{0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL */
{0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL2 */
{0x1f, 0xf, 2, 0xf, 0x00680, 32}, /* PATTERN_STATIC_PBS */
{0x1f, 0xf, 2, 0xf, 0x00a80, 32}, /* PATTERN_KILLER_DQ0 */
{0x1f, 0xf, 2, 0xf, 0x01280, 32}, /* PATTERN_KILLER_DQ1 */
{0x1f, 0xf, 2, 0xf, 0x01a80, 32}, /* PATTERN_KILLER_DQ2 */
{0x1f, 0xf, 2, 0xf, 0x02280, 32}, /* PATTERN_KILLER_DQ3 */
{0x1f, 0xf, 2, 0xf, 0x02a80, 32}, /* PATTERN_KILLER_DQ4 */
{0x1f, 0xf, 2, 0xf, 0x03280, 32}, /* PATTERN_KILLER_DQ5 */
{0x1f, 0xf, 2, 0xf, 0x03a80, 32}, /* PATTERN_KILLER_DQ6 */
{0x1f, 0xf, 2, 0xf, 0x04280, 32}, /* PATTERN_KILLER_DQ7 */
{0x1f, 0xf, 2, 0xf, 0x00e80, 32}, /* PATTERN_KILLER_DQ0_64 */
{0x1f, 0xf, 2, 0xf, 0x01680, 32}, /* PATTERN_KILLER_DQ1_64 */
{0x1f, 0xf, 2, 0xf, 0x01e80, 32}, /* PATTERN_KILLER_DQ2_64 */
{0x1f, 0xf, 2, 0xf, 0x02680, 32}, /* PATTERN_KILLER_DQ3_64 */
{0x1f, 0xf, 2, 0xf, 0x02e80, 32}, /* PATTERN_KILLER_DQ4_64 */
{0x1f, 0xf, 2, 0xf, 0x03680, 32}, /* PATTERN_KILLER_DQ5_64 */
{0x1f, 0xf, 2, 0xf, 0x03e80, 32}, /* PATTERN_KILLER_DQ6_64 */
{0x1f, 0xf, 2, 0xf, 0x04680, 32}, /* PATTERN_KILLER_DQ7_64 */
{0x1f, 0xf, 2, 0xf, 0x04a80, 32}, /* PATTERN_KILLER_DQ0_INV */
{0x1f, 0xf, 2, 0xf, 0x05280, 32}, /* PATTERN_KILLER_DQ1_INV */
{0x1f, 0xf, 2, 0xf, 0x05a80, 32}, /* PATTERN_KILLER_DQ2_INV */
{0x1f, 0xf, 2, 0xf, 0x06280, 32}, /* PATTERN_KILLER_DQ3_INV */
{0x1f, 0xf, 2, 0xf, 0x06a80, 32}, /* PATTERN_KILLER_DQ4_INV */
{0x1f, 0xf, 2, 0xf, 0x07280, 32}, /* PATTERN_KILLER_DQ5_INV */
{0x1f, 0xf, 2, 0xf, 0x07a80, 32}, /* PATTERN_KILLER_DQ6_INV */
{0x1f, 0xf, 2, 0xf, 0x08280, 32}, /* PATTERN_KILLER_DQ7_INV */
{0x1f, 0xf, 2, 0xf, 0x04e80, 32}, /* PATTERN_KILLER_DQ0_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x05680, 32}, /* PATTERN_KILLER_DQ1_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x05e80, 32}, /* PATTERN_KILLER_DQ2_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x06680, 32}, /* PATTERN_KILLER_DQ3_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x06e80, 32}, /* PATTERN_KILLER_DQ4_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x07680, 32}, /* PATTERN_KILLER_DQ5_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x07e80, 32}, /* PATTERN_KILLER_DQ6_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x08680, 32}, /* PATTERN_KILLER_DQ7_INV_64 */
{0x1f, 0xf, 2, 0xf, 0x08a80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0 */
{0x1f, 0xf, 2, 0xf, 0x09280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
{0x1f, 0xf, 2, 0xf, 0x09a80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
{0x1f, 0xf, 2, 0xf, 0x0a280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
{0x1f, 0xf, 2, 0xf, 0x0aa80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
{0x1f, 0xf, 2, 0xf, 0x0b280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
{0x1f, 0xf, 2, 0xf, 0x0ba80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
{0x1f, 0xf, 2, 0xf, 0x0c280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
{0x1f, 0xf, 2, 0xf, 0x08e80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0_64 */
{0x1f, 0xf, 2, 0xf, 0x09680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1_64 */
{0x1f, 0xf, 2, 0xf, 0x09e80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2_64 */
{0x1f, 0xf, 2, 0xf, 0x0a680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3_64 */
{0x1f, 0xf, 2, 0xf, 0x0ae80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4_64 */
{0x1f, 0xf, 2, 0xf, 0x0b680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5_64 */
{0x1f, 0xf, 2, 0xf, 0x0be80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6_64 */
{0x1f, 0xf, 2, 0xf, 0x0c680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7_64 */
{0x1f, 0xf, 2, 0xf, 0x0ca80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
{0x1f, 0xf, 2, 0xf, 0x0d280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
{0x1f, 0xf, 2, 0xf, 0x0da80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
{0x1f, 0xf, 2, 0xf, 0x0e280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
{0x1f, 0xf, 2, 0xf, 0x0ea80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
{0x1f, 0xf, 2, 0xf, 0x0f280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
{0x1f, 0xf, 2, 0xf, 0x0fa80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
{0x1f, 0xf, 2, 0xf, 0x10280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
{0x1f, 0xf, 2, 0xf, 0x0ce80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0_64 */
{0x1f, 0xf, 2, 0xf, 0x0d680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1_64 */
{0x1f, 0xf, 2, 0xf, 0x0de80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2_64 */
{0x1f, 0xf, 2, 0xf, 0x0e680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3_64 */
{0x1f, 0xf, 2, 0xf, 0x0ee80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4_64 */
{0x1f, 0xf, 2, 0xf, 0x0f680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5_64 */
{0x1f, 0xf, 2, 0xf, 0x0fe80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6_64 */
{0x1f, 0xf, 2, 0xf, 0x10680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7_64 */
{0x1f, 0xf, 2, 0xf, 0x10a80, 32}, /* PATTERN_ISI_XTALK_FREE */
{0x1f, 0xf, 2, 0xf, 0x10e80, 32}, /* PATTERN_ISI_XTALK_FREE_64 */
{0x1f, 0xf, 2, 0xf, 0x11280, 32}, /* PATTERN_VREF */
{0x1f, 0xf, 2, 0xf, 0x11680, 32}, /* PATTERN_VREF_64 */
{0x1f, 0xf, 2, 0xf, 0x11a80, 32}, /* PATTERN_VREF_INV */
{0x1f, 0xf, 2, 0xf, 0x11e80, 32}, /* PATTERN_FULL_SSO_0T */
{0x1f, 0xf, 2, 0xf, 0x12280, 32}, /* PATTERN_FULL_SSO_1T */
{0x1f, 0xf, 2, 0xf, 0x12680, 32}, /* PATTERN_FULL_SSO_2T */
{0x1f, 0xf, 2, 0xf, 0x12a80, 32}, /* PATTERN_FULL_SSO_3T */
{0x1f, 0xf, 2, 0xf, 0x12e80, 32}, /* PATTERN_RESONANCE_1T */
{0x1f, 0xf, 2, 0xf, 0x13280, 32}, /* PATTERN_RESONANCE_2T */
{0x1f, 0xf, 2, 0xf, 0x13680, 32}, /* PATTERN_RESONANCE_3T */
{0x1f, 0xf, 2, 0xf, 0x13a80, 32}, /* PATTERN_RESONANCE_4T */
{0x1f, 0xf, 2, 0xf, 0x13e80, 32}, /* PATTERN_RESONANCE_5T */
{0x1f, 0xf, 2, 0xf, 0x14280, 32}, /* PATTERN_RESONANCE_6T */
{0x1f, 0xf, 2, 0xf, 0x14680, 32}, /* PATTERN_RESONANCE_7T */
{0x1f, 0xf, 2, 0xf, 0x14a80, 32}, /* PATTERN_RESONANCE_8T */
{0x1f, 0xf, 2, 0xf, 0x14e80, 32} /* PATTERN_RESONANCE_9T */
/* Note: actual start_address is "<< 3" of defined address */
};
#if defined(CONFIG_DDR4)
struct pattern_info pattern_table_16[] = {
/*
* num tx phases, tx burst, delay between, rx pattern,
* start_address, pattern_len
*/
{0x1, 0x1, 2, 0x1, 0x0000, 2}, /* PATTERN_PBS1*/
{0x1, 0x1, 2, 0x1, 0x0080, 2}, /* PATTERN_PBS2*/
{0x1, 0x1, 2, 0x1, 0x0100, 2}, /* PATTERN_PBS3*/
{0x1, 0x1, 2, 0x1, 0x0180, 2}, /* PATTERN_TEST*/
{0x1, 0x1, 2, 0x1, 0x0200, 2}, /* PATTERN_RL*/
{0x1, 0x1, 2, 0x1, 0x0280, 2}, /* PATTERN_RL2*/
{0xf, 0x7, 2, 0x7, 0x0680, 16}, /* PATTERN_STATIC_PBS*/
{0xf, 0x7, 2, 0x7, 0x0A80, 16}, /* PATTERN_KILLER_DQ0*/
{0xf, 0x7, 2, 0x7, 0x0E80, 16}, /* PATTERN_KILLER_DQ1*/
{0xf, 0x7, 2, 0x7, 0x1280, 16}, /* PATTERN_KILLER_DQ2*/
{0xf, 0x7, 2, 0x7, 0x1680, 16}, /* PATTERN_KILLER_DQ3*/
{0xf, 0x7, 2, 0x7, 0x1A80, 16}, /* PATTERN_KILLER_DQ4*/
{0xf, 0x7, 2, 0x7, 0x1E80, 16}, /* PATTERN_KILLER_DQ5*/
{0xf, 0x7, 2, 0x7, 0x2280, 16}, /* PATTERN_KILLER_DQ6*/
{0xf, 0x7, 2, 0x7, 0x2680, 16}, /* PATTERN_KILLER_DQ7*/
{0xf, 0x7, 2, 0x7, 0x2A80, 16}, /* PATTERN_KILLER_DQ0_INV*/
{0xf, 0x7, 2, 0x7, 0x2E80, 16}, /* PATTERN_KILLER_DQ1_INV*/
{0xf, 0x7, 2, 0x7, 0x3280, 16}, /* PATTERN_KILLER_DQ2_INV*/
{0xf, 0x7, 2, 0x7, 0x3680, 16}, /* PATTERN_KILLER_DQ3_INV*/
{0xf, 0x7, 2, 0x7, 0x3A80, 16}, /* PATTERN_KILLER_DQ4_INV*/
{0xf, 0x7, 2, 0x7, 0x3E80, 16}, /* PATTERN_KILLER_DQ5_INV*/
{0xf, 0x7, 2, 0x7, 0x4280, 16}, /* PATTERN_KILLER_DQ6_INV*/
{0xf, 0x7, 2, 0x7, 0x4680, 16}, /* PATTERN_KILLER_DQ7_INV*/
{0xf, 0x7, 2, 0x7, 0x4A80, 16}, /* PATTERN_VREF*/
{0xf, 0x7, 2, 0x7, 0x4E80, 16}, /* PATTERN_VREF_INV*/
{0xf, 0x7, 2, 0x7, 0x5280, 16}, /* PATTERN_FULL_SSO_0T*/
{0xf, 0x7, 2, 0x7, 0x5680, 16}, /* PATTERN_FULL_SSO_1T*/
{0xf, 0x7, 2, 0x7, 0x5A80, 16}, /* PATTERN_FULL_SSO_2T*/
{0xf, 0x7, 2, 0x7, 0x5E80, 16}, /* PATTERN_FULL_SSO_3T*/
{0xf, 0x7, 2, 0x7, 0x6280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ0*/
{0xf, 0x7, 2, 0x7, 0x6680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ1*/
{0xf, 0x7, 2, 0x7, 0x6A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ2*/
{0xf, 0x7, 2, 0x7, 0x6E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ3*/
{0xf, 0x7, 2, 0x7, 0x7280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ4*/
{0xf, 0x7, 2, 0x7, 0x7680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ5*/
{0xf, 0x7, 2, 0x7, 0x7A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ6*/
{0xf, 0x7, 2, 0x7, 0x7E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ7*/
{0xf, 0x7, 2, 0x7, 0x8280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ0*/
{0xf, 0x7, 2, 0x7, 0x8680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ1*/
{0xf, 0x7, 2, 0x7, 0x8A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ2*/
{0xf, 0x7, 2, 0x7, 0x8E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ3*/
{0xf, 0x7, 2, 0x7, 0x9280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ4*/
{0xf, 0x7, 2, 0x7, 0x9680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ5*/
{0xf, 0x7, 2, 0x7, 0x9A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ6*/
{0xf, 0x7, 2, 0x7, 0x9E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ7*/
{0xf, 0x7, 2, 0x7, 0xA280, 16}, /* PATTERN_ISI_XTALK_FREE*/
{0xf, 0x7, 2, 0x7, 0xA680, 16}, /* PATTERN_RESONANCE_1T*/
{0xf, 0x7, 2, 0x7, 0xAA80, 16}, /* PATTERN_RESONANCE_2T*/
{0xf, 0x7, 2, 0x7, 0xAE80, 16}, /* PATTERN_RESONANCE_3T*/
{0xf, 0x7, 2, 0x7, 0xB280, 16}, /* PATTERN_RESONANCE_4T*/
{0xf, 0x7, 2, 0x7, 0xB680, 16}, /* PATTERN_RESONANCE_5T*/
{0xf, 0x7, 2, 0x7, 0xBA80, 16}, /* PATTERN_RESONANCE_6T*/
{0xf, 0x7, 2, 0x7, 0xBE80, 16}, /* PATTERN_RESONANCE_7T*/
{0xf, 0x7, 2, 0x7, 0xC280, 16}, /* PATTERN_RESONANCE_8T*/
{0xf, 0x7, 2, 0x7, 0xC680, 16} /* PATTERN_RESONANCE_9T*/
/* Note: actual start_address is "<< 3" of defined address */
};
struct pattern_info pattern_table_32[] = {
/*
* num tx phases, tx burst, delay between, rx pattern,
* start_address, pattern_len
*/
{0x3, 0x3, 2, 0x3, 0x0000, 4}, /* PATTERN_PBS1*/
{0x3, 0x3, 2, 0x3, 0x0080, 4}, /* PATTERN_PBS2*/
{0x3, 0x3, 2, 0x3, 0x0100, 4}, /* PATTERN_PBS3*/
{0x3, 0x3, 2, 0x3, 0x0180, 4}, /* PATTERN_TEST*/
{0x3, 0x3, 2, 0x3, 0x0200, 4}, /* PATTERN_RL*/
{0x3, 0x3, 2, 0x3, 0x0280, 4}, /* PATTERN_RL2*/
{0x1f, 0xf, 2, 0xf, 0x0680, 32}, /* PATTERN_STATIC_PBS*/
{0x1f, 0xf, 2, 0xf, 0x0A80, 32}, /* PATTERN_KILLER_DQ0*/
{0x1f, 0xf, 2, 0xf, 0x0E80, 32}, /* PATTERN_KILLER_DQ1*/
{0x1f, 0xf, 2, 0xf, 0x1280, 32}, /* PATTERN_KILLER_DQ2*/
{0x1f, 0xf, 2, 0xf, 0x1680, 32}, /* PATTERN_KILLER_DQ3*/
{0x1f, 0xf, 2, 0xf, 0x1A80, 32}, /* PATTERN_KILLER_DQ4*/
{0x1f, 0xf, 2, 0xf, 0x1E80, 32}, /* PATTERN_KILLER_DQ5*/
{0x1f, 0xf, 2, 0xf, 0x2280, 32}, /* PATTERN_KILLER_DQ6*/
{0x1f, 0xf, 2, 0xf, 0x2680, 32}, /* PATTERN_KILLER_DQ7*/
{0x1f, 0xf, 2, 0xf, 0x2A80, 32}, /* PATTERN_KILLER_DQ0_INV*/
{0x1f, 0xf, 2, 0xf, 0x2E80, 32}, /* PATTERN_KILLER_DQ1_INV*/
{0x1f, 0xf, 2, 0xf, 0x3280, 32}, /* PATTERN_KILLER_DQ2_INV*/
{0x1f, 0xf, 2, 0xf, 0x3680, 32}, /* PATTERN_KILLER_DQ3_INV*/
{0x1f, 0xf, 2, 0xf, 0x3A80, 32}, /* PATTERN_KILLER_DQ4_INV*/
{0x1f, 0xf, 2, 0xf, 0x3E80, 32}, /* PATTERN_KILLER_DQ5_INV*/
{0x1f, 0xf, 2, 0xf, 0x4280, 32}, /* PATTERN_KILLER_DQ6_INV*/
{0x1f, 0xf, 2, 0xf, 0x4680, 32}, /* PATTERN_KILLER_DQ7_INV*/
{0x1f, 0xf, 2, 0xf, 0x4A80, 32}, /* PATTERN_VREF*/
{0x1f, 0xf, 2, 0xf, 0x4E80, 32}, /* PATTERN_VREF_INV*/
{0x1f, 0xf, 2, 0xf, 0x5280, 32}, /* PATTERN_FULL_SSO_0T*/
{0x1f, 0xf, 2, 0xf, 0x5680, 32}, /* PATTERN_FULL_SSO_1T*/
{0x1f, 0xf, 2, 0xf, 0x5A80, 32}, /* PATTERN_FULL_SSO_2T*/
{0x1f, 0xf, 2, 0xf, 0x5E80, 32}, /* PATTERN_FULL_SSO_3T*/
{0x1f, 0xf, 2, 0xf, 0x6280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0*/
{0x1f, 0xf, 2, 0xf, 0x6680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1*/
{0x1f, 0xf, 2, 0xf, 0x6A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2*/
{0x1f, 0xf, 2, 0xf, 0x6E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3*/
{0x1f, 0xf, 2, 0xf, 0x7280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4*/
{0x1f, 0xf, 2, 0xf, 0x7680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5*/
{0x1f, 0xf, 2, 0xf, 0x7A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6*/
{0x1f, 0xf, 2, 0xf, 0x7E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7*/
{0x1f, 0xf, 2, 0xf, 0x8280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0*/
{0x1f, 0xf, 2, 0xf, 0x8680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1*/
{0x1f, 0xf, 2, 0xf, 0x8A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2*/
{0x1f, 0xf, 2, 0xf, 0x8E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3*/
{0x1f, 0xf, 2, 0xf, 0x9280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4*/
{0x1f, 0xf, 2, 0xf, 0x9680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5*/
{0x1f, 0xf, 2, 0xf, 0x9A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6*/
{0x1f, 0xf, 2, 0xf, 0x9E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7*/
{0x1f, 0xf, 2, 0xf, 0xA280, 32}, /* PATTERN_ISI_XTALK_FREE*/
{0x1f, 0xf, 2, 0xf, 0xA680, 32}, /* PATTERN_RESONANCE_1T*/
{0x1f, 0xf, 2, 0xf, 0xAA80, 32}, /* PATTERN_RESONANCE_2T*/
{0x1f, 0xf, 2, 0xf, 0xAE80, 32}, /* PATTERN_RESONANCE_3T*/
{0x1f, 0xf, 2, 0xf, 0xB280, 32}, /* PATTERN_RESONANCE_4T*/
{0x1f, 0xf, 2, 0xf, 0xB680, 32}, /* PATTERN_RESONANCE_5T*/
{0x1f, 0xf, 2, 0xf, 0xBA80, 32}, /* PATTERN_RESONANCE_6T*/
{0x1f, 0xf, 2, 0xf, 0xBE80, 32}, /* PATTERN_RESONANCE_7T*/
{0x1f, 0xf, 2, 0xf, 0xC280, 32}, /* PATTERN_RESONANCE_8T*/
{0x1f, 0xf, 2, 0xf, 0xC680, 32} /* PATTERN_RESONANCE_9T*/
/* Note: actual start_address is "<< 3" of defined address */
};
#else /* CONFIG_DDR4 */
struct pattern_info pattern_table_16[] = {
/*
* num tx phases, tx burst, delay between, rx pattern,
* start_address, pattern_len
*/
{1, 1, 2, 1, 0x0080, 2}, /* PATTERN_PBS1 */
{1, 1, 2, 1, 0x00c0, 2}, /* PATTERN_PBS2 */
{1, 1, 2, 1, 0x0380, 2}, /* PATTERN_PBS3 */
{1, 1, 2, 1, 0x0040, 2}, /* PATTERN_TEST */
{1, 1, 2, 1, 0x0100, 2}, /* PATTERN_RL */
{1, 1, 2, 1, 0x0000, 2}, /* PATTERN_RL2 */
{0xf, 0x7, 2, 0x7, 0x0140, 16}, /* PATTERN_STATIC_PBS */
{0xf, 0x7, 2, 0x7, 0x0190, 16}, /* PATTERN_KILLER_DQ0 */
{0xf, 0x7, 2, 0x7, 0x01d0, 16}, /* PATTERN_KILLER_DQ1 */
{0xf, 0x7, 2, 0x7, 0x0210, 16}, /* PATTERN_KILLER_DQ2 */
{0xf, 0x7, 2, 0x7, 0x0250, 16}, /* PATTERN_KILLER_DQ3 */
{0xf, 0x7, 2, 0x7, 0x0290, 16}, /* PATTERN_KILLER_DQ4 */
{0xf, 0x7, 2, 0x7, 0x02d0, 16}, /* PATTERN_KILLER_DQ5 */
{0xf, 0x7, 2, 0x7, 0x0310, 16}, /* PATTERN_KILLER_DQ6 */
{0xf, 0x7, 2, 0x7, 0x0350, 16}, /* PATTERN_KILLER_DQ7 */
{0xf, 0x7, 2, 0x7, 0x04c0, 16}, /* PATTERN_VREF */
{0xf, 0x7, 2, 0x7, 0x03c0, 16}, /* PATTERN_FULL_SSO_1T */
{0xf, 0x7, 2, 0x7, 0x0400, 16}, /* PATTERN_FULL_SSO_2T */
{0xf, 0x7, 2, 0x7, 0x0440, 16}, /* PATTERN_FULL_SSO_3T */
{0xf, 0x7, 2, 0x7, 0x0480, 16}, /* PATTERN_FULL_SSO_4T */
{0xf, 7, 2, 7, 0x6280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
{0xf, 7, 2, 7, 0x6680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
{0xf, 7, 2, 7, 0x6A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
{0xf, 7, 2, 7, 0x6E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
{0xf, 7, 2, 7, 0x7280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
{0xf, 7, 2, 7, 0x7680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
{0xf, 7, 2, 7, 0x7A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
{0xf, 7, 2, 7, 0x7E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
{0xf, 7, 2, 7, 0x8280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
{0xf, 7, 2, 7, 0x8680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
{0xf, 7, 2, 7, 0x8A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
{0xf, 7, 2, 7, 0x8E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
{0xf, 7, 2, 7, 0x9280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
{0xf, 7, 2, 7, 0x9680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
{0xf, 7, 2, 7, 0x9A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
{0xf, 7, 2, 7, 0x9E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
{0xf, 7, 2, 7, 0xA280, 16} /* PATTERN_ISI_XTALK_FREE */
/* Note: actual start_address is "<< 3" of defined address */
};
struct pattern_info pattern_table_32[] = {
/*
* num tx phases, tx burst, delay between, rx pattern,
* start_address, pattern_len
*/
{3, 3, 2, 3, 0x0080, 4}, /* PATTERN_PBS1 */
{3, 3, 2, 3, 0x00c0, 4}, /* PATTERN_PBS2 */
{3, 3, 2, 3, 0x0380, 4}, /* PATTERN_PBS3 */
{3, 3, 2, 3, 0x0040, 4}, /* PATTERN_TEST */
{3, 3, 2, 3, 0x0100, 4}, /* PATTERN_RL */
{3, 3, 2, 3, 0x0000, 4}, /* PATTERN_RL2 */
{0x1f, 0xf, 2, 0xf, 0x0140, 32}, /* PATTERN_STATIC_PBS */
{0x1f, 0xf, 2, 0xf, 0x0190, 32}, /* PATTERN_KILLER_DQ0 */
{0x1f, 0xf, 2, 0xf, 0x01d0, 32}, /* PATTERN_KILLER_DQ1 */
{0x1f, 0xf, 2, 0xf, 0x0210, 32}, /* PATTERN_KILLER_DQ2 */
{0x1f, 0xf, 2, 0xf, 0x0250, 32}, /* PATTERN_KILLER_DQ3 */
{0x1f, 0xf, 2, 0xf, 0x0290, 32}, /* PATTERN_KILLER_DQ4 */
{0x1f, 0xf, 2, 0xf, 0x02d0, 32}, /* PATTERN_KILLER_DQ5 */
{0x1f, 0xf, 2, 0xf, 0x0310, 32}, /* PATTERN_KILLER_DQ6 */
{0x1f, 0xf, 2, 0xf, 0x0350, 32}, /* PATTERN_KILLER_DQ7 */
{0x1f, 0xf, 2, 0xf, 0x04c0, 32}, /* PATTERN_VREF */
{0x1f, 0xf, 2, 0xf, 0x03c0, 32}, /* PATTERN_FULL_SSO_1T */
{0x1f, 0xf, 2, 0xf, 0x0400, 32}, /* PATTERN_FULL_SSO_2T */
{0x1f, 0xf, 2, 0xf, 0x0440, 32}, /* PATTERN_FULL_SSO_3T */
{0x1f, 0xf, 2, 0xf, 0x0480, 32}, /* PATTERN_FULL_SSO_4T */
{0x1f, 0xF, 2, 0xf, 0x6280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0 */
{0x1f, 0xF, 2, 0xf, 0x6680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
{0x1f, 0xF, 2, 0xf, 0x6A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
{0x1f, 0xF, 2, 0xf, 0x6E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
{0x1f, 0xF, 2, 0xf, 0x7280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
{0x1f, 0xF, 2, 0xf, 0x7680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
{0x1f, 0xF, 2, 0xf, 0x7A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
{0x1f, 0xF, 2, 0xf, 0x7E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
{0x1f, 0xF, 2, 0xf, 0x8280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
{0x1f, 0xF, 2, 0xf, 0x8680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
{0x1f, 0xF, 2, 0xf, 0x8A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
{0x1f, 0xF, 2, 0xf, 0x8E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
{0x1f, 0xF, 2, 0xf, 0x9280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
{0x1f, 0xF, 2, 0xf, 0x9680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
{0x1f, 0xF, 2, 0xf, 0x9A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
{0x1f, 0xF, 2, 0xf, 0x9E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
{0x1f, 0xF, 2, 0xf, 0xA280, 32} /* PATTERN_ISI_XTALK_FREE */
/* Note: actual start_address is "<< 3" of defined address */
};
#endif /* CONFIG_DDR4 */
u32 train_dev_num;
enum hws_ddr_cs traintrain_cs_type;
u32 train_pup_num;
enum hws_training_result train_result_type;
enum hws_control_element train_control_element;
enum hws_search_dir traine_search_dir;
enum hws_dir train_direction;
u32 train_if_select;
u32 train_init_value;
u32 train_number_iterations;
enum hws_pattern train_pattern;
enum hws_edge_compare train_edge_compare;
u32 train_cs_num;
u32 train_if_acess, train_if_id, train_pup_access;
#if defined(CONFIG_DDR4)
/* The counter was increased for DDR4 because of A390 DB-GP DDR4 failure */
u32 max_polling_for_done = 100000000;
#else /* CONFIG_DDR4 */
u32 max_polling_for_done = 1000000;
#endif /* CONFIG_DDR4 */
u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search,
enum hws_training_result result_type,
u32 interface_num)
{
u32 *buf_ptr = NULL;
buf_ptr = &training_res
[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search +
interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS];
return buf_ptr;
}
/*
* IP Training search
* Note: for one edge search only from fail to pass, else jitter can
* be be entered into solution.
*/
int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
u32 interface_num,
enum hws_access_type pup_access_type,
u32 pup_num, enum hws_training_result result_type,
enum hws_control_element control_element,
enum hws_search_dir search_dir, enum hws_dir direction,
u32 interface_mask, u32 init_value, u32 num_iter,
enum hws_pattern pattern,
enum hws_edge_compare edge_comp,
enum hws_ddr_cs cs_type, u32 cs_num,
enum hws_training_ip_stat *train_status)
{
u32 mask_dq_num_of_regs, mask_pup_num_of_regs, index_cnt, poll_cnt,
reg_data, pup_id, trigger_reg_addr;
u32 tx_burst_size;
u32 delay_between_burst;
u32 rd_mode;
u32 read_data[MAX_INTERFACE_NUM];
struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (pup_num >= octets_per_if_num) {
DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
("pup_num %d not valid\n", pup_num));
}
if (interface_num >= MAX_INTERFACE_NUM) {
DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
("if_id %d not valid\n",
interface_num));
}
if (train_status == NULL) {
DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
("error param 4\n"));
return MV_BAD_PARAM;
}
/* load pattern */
if (cs_type == CS_SINGLE) {
/* All CSs to CS0 */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
CS_ENABLE_REG, 1 << 3, 1 << 3));
/* All CSs to CS0 */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
ODPG_DATA_CONTROL_REG,
(0x3 | (effective_cs << 26)), 0xc000003));
} else {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
CS_ENABLE_REG, 0, 1 << 3));
/* CS select */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
ODPG_DATA_CONTROL_REG, 0x3 | cs_num << 26,
0x3 | 3 << 26));
}
/* load pattern to ODPG */
ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num,
pattern,
pattern_table[pattern].start_addr);
tx_burst_size = (direction == OPER_WRITE) ?
pattern_table[pattern].tx_burst_size : 0;
delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
rd_mode = (direction == OPER_WRITE) ? 1 : 0;
CHECK_STATUS(ddr3_tip_configure_odpg
(dev_num, access_type, interface_num, direction,
pattern_table[pattern].num_of_phases_tx, tx_burst_size,
pattern_table[pattern].num_of_phases_rx,
delay_between_burst, rd_mode, effective_cs, STRESS_NONE,
DURATION_SINGLE));
reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30);
reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
ODPG_WRITE_READ_MODE_ENABLE_REG, reg_data,
MASK_ALL_BITS));
reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6;
reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ?
(1 << 7) : 0;
/* change from Pass to Fail will lock the result */
if (pup_access_type == ACCESS_TYPE_MULTICAST)
reg_data |= 0xe << 14;
else
reg_data |= pup_num << 14;
if (edge_comp == EDGE_FP) {
/* don't search for readl edge change, only the state */
reg_data |= (0 << 20);
} else if (edge_comp == EDGE_FPF) {
reg_data |= (0 << 20);
} else {
reg_data |= (3 << 20);
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
ODPG_TRAINING_CONTROL_REG,
reg_data | (0x7 << 8) | (0x7 << 11),
(0x3 | (0x3 << 2) | (0x3 << 6) | (1 << 5) | (0x7 << 8) |
(0x7 << 11) | (0xf << 14) | (0x3 << 18) | (3 << 20))));
reg_data = (search_dir == HWS_LOW2HIGH) ? 0 : (1 << 8);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num, ODPG_OBJ1_OPCODE_REG,
1 | reg_data | init_value << 9 | (1 << 25) | (1 << 26),
0xff | (1 << 8) | (0xffff << 9) | (1 << 25) | (1 << 26)));
/*
* Write2_dunit(0x10b4, Number_iteration , [15:0])
* Max number of iterations
*/
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, interface_num,
ODPG_OBJ1_ITER_CNT_REG, num_iter,
0xffff));
if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
direction == OPER_READ) {
/*
* Write2_dunit(0x10c0, 0x5f , [7:0])
* MC PBS Reg Address at DDR PHY
*/
reg_data = 0x5f +
effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET;
} else if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
direction == OPER_WRITE) {
reg_data = 0x1f +
effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET;
} else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
direction == OPER_WRITE) {
/*
* LOOP 0x00000001 + 4*n:
* where n (0-3) represents M_CS number
*/
/*
* Write2_dunit(0x10c0, 0x1 , [7:0])
* ADLL WR Reg Address at DDR PHY
*/
reg_data = 1 + effective_cs * CS_REGISTER_ADDR_OFFSET;
} else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
direction == OPER_READ) {
/* ADLL RD Reg Address at DDR PHY */
reg_data = 3 + effective_cs * CS_REGISTER_ADDR_OFFSET;
} else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
direction == OPER_WRITE) {
/* TBD not defined in 0.5.0 requirement */
} else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
direction == OPER_READ) {
/* TBD not defined in 0.5.0 requirement */
}
reg_data |= (0x6 << 28);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num, CALIB_OBJ_PRFA_REG,
reg_data | (init_value << 8),
0xff | (0xffff << 8) | (0xf << 24) | (u32) (0xf << 28)));
mask_dq_num_of_regs = octets_per_if_num * BUS_WIDTH_IN_BITS;
mask_pup_num_of_regs = octets_per_if_num;
if (result_type == RESULT_PER_BIT) {
for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
index_cnt++) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
mask_results_dq_reg_map[index_cnt], 0,
1 << 24));
}
/* Mask disabled buses */
for (pup_id = 0; pup_id < octets_per_if_num;
pup_id++) {
if (IS_BUS_ACTIVE(tm->bus_act_mask, pup_id) == 1)
continue;
for (index_cnt = (pup_id * 8); index_cnt < (pup_id + 1) * 8; index_cnt++) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type,
interface_num,
mask_results_dq_reg_map
[index_cnt], (1 << 24), 1 << 24));
}
}
for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
index_cnt++) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
mask_results_pup_reg_map[index_cnt],
(1 << 24), 1 << 24));
}
} else if (result_type == RESULT_PER_BYTE) {
/* write to adll */
for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
index_cnt++) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
mask_results_pup_reg_map[index_cnt], 0,
1 << 24));
}
for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
index_cnt++) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, interface_num,
mask_results_dq_reg_map[index_cnt],
(1 << 24), (1 << 24)));
}
}
/* Start Training Trigger */
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
trigger_reg_addr = ODPG_TRAINING_TRIGGER_REG;
else
trigger_reg_addr = ODPG_TRAINING_STATUS_REG;
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, interface_num,
trigger_reg_addr, 1, 1));
/* wait for all RFU tests to finish (or timeout) */
/* WA for 16 bit mode, more investigation needed */
mdelay(1);
/* Training "Done ?" for CPU controlled TIP */
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) >= MV_TIP_REV_3) {
for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, index_cnt);
if (interface_mask & (1 << index_cnt)) {
/* need to check results for this Dunit */
for (poll_cnt = 0; poll_cnt < max_polling_for_done;
poll_cnt++) {
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST,
index_cnt,
ODPG_TRAINING_STATUS_REG,
read_data, MASK_ALL_BITS));
if ((read_data[index_cnt] & 0x2) != 0) {
/*done */
train_status[index_cnt] =
HWS_TRAINING_IP_STATUS_SUCCESS;
break;
}
}
if (poll_cnt == max_polling_for_done) {
train_status[index_cnt] =
HWS_TRAINING_IP_STATUS_TIMEOUT;
}
}
/* Be sure that ODPG done */
CHECK_STATUS(is_odpg_access_done(dev_num, index_cnt));
}
/* Write ODPG done in Dunit */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
ODPG_STATUS_DONE_REG, 0, 0x1));
}
/* wait for all Dunit tests to finish (or timeout) */
/* Training "Done ?" */
/* Training "Pass ?" */
for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, index_cnt);
if (interface_mask & (1 << index_cnt)) {
/* need to check results for this Dunit */
for (poll_cnt = 0; poll_cnt < max_polling_for_done;
poll_cnt++) {
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST,
index_cnt,
trigger_reg_addr,
read_data, MASK_ALL_BITS));
reg_data = read_data[index_cnt];
if ((reg_data & 0x2) != 0) {
/* done */
if ((reg_data & 0x4) == 0) {
train_status[index_cnt] =
HWS_TRAINING_IP_STATUS_SUCCESS;
} else {
train_status[index_cnt] =
HWS_TRAINING_IP_STATUS_FAIL;
}
break;
}
}
if (poll_cnt == max_polling_for_done) {
train_status[index_cnt] =
HWS_TRAINING_IP_STATUS_TIMEOUT;
}
}
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
return MV_OK;
}
/*
* Load expected Pattern to ODPG
*/
int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum hws_pattern pattern,
u32 load_addr)
{
u32 pattern_length_cnt = 0;
struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (pattern_length_cnt = 0;
pattern_length_cnt < pattern_table[pattern].pattern_len;
pattern_length_cnt++) { /* FIXME: the ecc patch below is only for a7040 A0 */
if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)/* || tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK*/) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_DATA_LOW_REG,
pattern_table_get_word(dev_num, pattern,
(u8) (pattern_length_cnt)),
MASK_ALL_BITS));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_DATA_HI_REG,
pattern_table_get_word(dev_num, pattern,
(u8) (pattern_length_cnt)),
MASK_ALL_BITS));
} else {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_DATA_LOW_REG,
pattern_table_get_word(dev_num, pattern,
(u8) (pattern_length_cnt * 2)),
MASK_ALL_BITS));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_DATA_HI_REG,
pattern_table_get_word(dev_num, pattern,
(u8) (pattern_length_cnt * 2 + 1)),
MASK_ALL_BITS));
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_ADDR_REG, pattern_length_cnt,
MASK_ALL_BITS));
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_PATTERN_ADDR_OFFSET_REG, load_addr, MASK_ALL_BITS));
return MV_OK;
}
/*
* Configure ODPG
*/
int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum hws_dir direction, u32 tx_phases,
u32 tx_burst_size, u32 rx_phases,
u32 delay_between_burst, u32 rd_mode, u32 cs_num,
u32 addr_stress_jump, u32 single_pattern)
{
u32 data_value = 0;
int ret;
data_value = ((single_pattern << 2) | (tx_phases << 5) |
(tx_burst_size << 11) | (delay_between_burst << 15) |
(rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) |
(addr_stress_jump << 29));
ret = ddr3_tip_if_write(dev_num, access_type, if_id,
ODPG_DATA_CONTROL_REG, data_value, 0xaffffffc);
if (ret != MV_OK)
return ret;
return MV_OK;
}
int ddr3_tip_process_result(u32 *ar_result, enum hws_edge e_edge,
enum hws_edge_search e_edge_search,
u32 *edge_result)
{
u32 i, res;
int tap_val, max_val = -10000, min_val = 10000;
int lock_success = 1;
for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
res = GET_LOCK_RESULT(ar_result[i]);
if (res == 0) {
lock_success = 0;
break;
}
DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
("lock failed for bit %d\n", i));
}
if (lock_success == 1) {
for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
tap_val = GET_TAP_RESULT(ar_result[i], e_edge);
if (tap_val > max_val)
max_val = tap_val;
if (tap_val < min_val)
min_val = tap_val;
if (e_edge_search == TRAINING_EDGE_MAX)
*edge_result = (u32) max_val;
else
*edge_result = (u32) min_val;
DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
("i %d ar_result[i] 0x%x tap_val %d max_val %d min_val %d Edge_result %d\n",
i, ar_result[i], tap_val,
max_val, min_val,
*edge_result));
}
} else {
return MV_FAIL;
}
return MV_OK;
}
/*
* Read training search result
*/
int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
enum hws_access_type pup_access_type,
u32 pup_num, u32 bit_num,
enum hws_search_dir search,
enum hws_dir direction,
enum hws_training_result result_type,
enum hws_training_load_op operation,
u32 cs_num_type, u32 **load_res,
int is_read_from_db, u8 cons_tap,
int is_check_result_validity)
{
u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg;
u32 *interface_train_res = NULL;
u16 *reg_addr = NULL;
u32 read_data[MAX_INTERFACE_NUM];
u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();