diff --git a/README.md b/README.md index ba292fb..5292cab 100644 --- a/README.md +++ b/README.md @@ -24,9 +24,9 @@ Start in a **new empty directory** with plenty of free disk space - at least 30G 3. Initialise a build directory with example configuration files based on lx2160ardb, and appropriate shell environment variables: - source ./setup-env -m lx2160ardb-rev2 -b build_lx2160acex7-rev2 + source ./setup-env -m lx2160ardb-rev2 -b build_lx2160a-rev2-honeycomb -4. Adapt example configuration files for SolidRun LX2160A CEX7: +4. Adapt example configuration files for SolidRun LX2160A Honeycomb: - edit `build_lx2160acex7-rev2/conf/bblayers.conf`: @@ -36,11 +36,11 @@ Start in a **new empty directory** with plenty of free disk space - at least 30G - edit `build_lx2160acex7/conf/local.conf`: - Set machine to `lx2160acex7-rev2`: + Set machine to `lx2160a-rev2-honeycomb`: ```diff -MACHINE ??= 'lx2160ardb-rev2' - +MACHINE ??= 'lx2160acex7-rev2' + +MACHINE ??= 'lx2160a-rev2-honeycomb' ``` - See below for additional configuration options. @@ -93,10 +93,14 @@ source SOURCE_THIS This Layer supports the following machines: -| Machine | Description | -| ---------------- | ------------------------------------------------------------------------------------------ | -| lx2160acex7 | LX2160A COM-Express 7 on Clearfog-CX / Honeycomb LX2160A Silicon 1.0 (preview version) | -| lx2160acex7-rev2 | LX2160A COM-Express 7 on Clearfog-CX / Honeycomb, LX2160A Silicon 2.0 (production version) | +| Machine | Description | +| ------------------------ | ------------------------------------------------------------------------------ | +| lx2160a-clearfog-cx | LX2160A COM-Express 7 on Clearfog-CX, LX2160A Silicon 1.0 (preview version) | +| lx2160a-honeycomb | LX2160A COM-Express 7 on Honeycomb, LX2160A Silicon 1.0 (preview version) | +| lx2160a-rev2-cex6-evb | SolidRun-internal Evaluation Board, LX2160A Silicon 2.0 (production version) | +| lx2160a-rev2-clearfog-cx | LX2160A COM-Express 7 on Clearfog-CX, LX2160A Silicon 2.0 (production version) | +| lx2160a-rev2-honeycomb | LX2160A COM-Express 7 on Honeycomb, LX2160A Silicon 2.0 (production version) | +| lx2162a-rev2-clearfog | LX2162A SoM on Clearfog | ### DDR Clock @@ -119,6 +123,7 @@ CPU (Cortex A72) Clock can be configured in local.conf using `LX2160A_CPU_SPEED` Bus clock can be configured in local.conf using `LX2160A_BUS_SPEED`, supported values are: +- `650` - `700` only for LX2160A binned 2GHz and higher (default) - `750` (for over-clocking, or for specifically purchased 2.2GHz binned SoC) diff --git a/conf/machine/include/lx2160a-clearfog-cx.inc b/conf/machine/include/lx2160a-clearfog-cx.inc new file mode 100644 index 0000000..b499376 --- /dev/null +++ b/conf/machine/include/lx2160a-clearfog-cx.inc @@ -0,0 +1,17 @@ +# select DTBs +KERNEL_DEVICETREE ?= " \ + freescale/fsl-lx2160a-clearfog-cx.dtb \ + freescale/fsl-lx2160a-honeycomb.dtb \ +" + +# select DPL/DPC (config/lx2160a/LX2160A-/) +# variable consumed in wks files +MC_DPC ?= "clearfog-cx-s1_8-s2_0-dpc.dtb" +MC_DPL ?= "clearfog-cx-s1_8-s2_0-dpl.dtb" + +# select RCW +BOOTTYPE ?= "flexspi_nor sd emmc auto" +RCWXSPI ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_18_5_2_xspi" +RCWSD ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_18_5_2_sdhc" +RCWEMMC ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_18_5_2_sdhc" +RCWAUTO ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_18_5_2_auto" diff --git a/conf/machine/lx2160acex6-rev2.conf b/conf/machine/include/lx2160acex6-rev2.inc similarity index 64% rename from conf/machine/lx2160acex6-rev2.conf rename to conf/machine/include/lx2160acex6-rev2.inc index bbae070..00d6e67 100644 --- a/conf/machine/lx2160acex6-rev2.conf +++ b/conf/machine/include/lx2160acex6-rev2.inc @@ -1,12 +1,12 @@ #@TYPE: Machine -#@NAME: SolidRun LX2160ACEX6 EVB +#@NAME: SolidRun LX2160A CEX-6 #@SOC: LSCH3 -#@DESCRIPTION: Machine configuration for SolidRun LX2160A Rev 2.0 Com-Express Type 6 Internal Evaluation Board +#@DESCRIPTION: Machine configuration for SolidRun Internal LX2160A Rev 2.0 COM-Express Type 6 Module require conf/machine/include/qoriq-arm64.inc -require conf/machine/include/arm/arch-arm64.inc +require conf/machine/include/arm/armv8a/tune-cortexa72.inc -MACHINEOVERRIDES =. "fsl-lsch3:lx2160a:" +MACHINEOVERRIDES =. "lx2160a-cex6:fsl-lsch3:lx2160a:" MACHINE_FEATURES:append = " optee " @@ -16,13 +16,10 @@ KERNEL_IMAGETYPES = "fitImage" DTB_LOAD = "0x90000000" UBOOT_ENTRYPOINT = "0x80080000" -UBOOT_CONFIG ??= "tfa-secure-boot tfa" +UBOOT_CONFIG ?= "tfa-secure-boot tfa" UBOOT_CONFIG[tfa] = "lx2160acex7_tfa_defconfig,,u-boot-dtb.bin" UBOOT_CONFIG[tfa-secure-boot] = "lx2160ardb_tfa_SECURE_BOOT_defconfig,,u-boot-dtb.bin" -KERNEL_DEVICETREE ?= " \ - freescale/fsl-lx2160a-cex6-evb.dtb \ -" KERNEL_DEFCONFIG ?= "defconfig" SERIAL_CONSOLES ?= "115200;ttyS0 115200;ttyS1 115200;ttyAMA0" @@ -33,8 +30,6 @@ LX2160A_CPU_SPEED ?= "2000" LX2160A_DDR_SPEED ?= "2900" UEFI_XSPIBOOT ?= "LX2160ARDB_EFI_NORBOOT.fd" -BOOTTYPE ?= "auto" -RCWAUTO ?= "evb/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_3_3_2_auto" EXTRA_IMAGEDEPENDS += "management-complex mc-utils rcw ls2-phy ddr-phy uefi qoriq-atf inphi" USE_VT = "0" @@ -47,10 +42,5 @@ IMAGE_BOOT_FILES:append = "${KERNEL_DEVICETREE}" # select DPL/DPC source (config/lx2160a/LX2160A-) MC_FLAVOUR ?= "CEX6" -# select DPL/DPC (config/lx2160a/LX2160A-/) -# variable consumed in wks files -MC_DPC ?= "evb-s1_3-s2_0-dpc.dtb" -MC_DPL ?= "evb-s1_3-s2_0-dpl.dtb" - # select rev2 rcw RCW_FOLDER ?= "lx2160acex6_rev2" diff --git a/conf/machine/include/lx2160acex7-rev2.inc b/conf/machine/include/lx2160acex7-rev2.inc new file mode 100644 index 0000000..258a4c5 --- /dev/null +++ b/conf/machine/include/lx2160acex7-rev2.inc @@ -0,0 +1,10 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A CEX-7 +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2160A 2.0 COM-Express Type 7 Module + +# select rev2 rcw +# set before lx2160acex7.inc which uses ?=, too +RCW_FOLDER ?= "lx2160acex7_rev2" + +require conf/machine/include/lx2160acex7.inc diff --git a/conf/machine/lx2160acex7.conf b/conf/machine/include/lx2160acex7.inc similarity index 55% rename from conf/machine/lx2160acex7.conf rename to conf/machine/include/lx2160acex7.inc index 6128d05..774f37b 100644 --- a/conf/machine/lx2160acex7.conf +++ b/conf/machine/include/lx2160acex7.inc @@ -1,12 +1,12 @@ #@TYPE: Machine -#@NAME: SolidRun LX2160ACEX7 +#@NAME: SolidRun LX2160A CEX-7 #@SOC: LSCH3 -#@DESCRIPTION: Machine configuration for SolidRun LX2160A Rev 1.0 Com-Express Type 7 Module +#@DESCRIPTION: Machine configuration for SolidRun LX2160A Rev 1.0 COM-Express Type 7 Module require conf/machine/include/qoriq-arm64.inc -require conf/machine/include/arm/arch-arm64.inc +require conf/machine/include/arm/armv8a/tune-cortexa72.inc -MACHINEOVERRIDES =. "fsl-lsch3:lx2160a:" +MACHINEOVERRIDES =. "lx2160a-cex7:fsl-lsch3:lx2160a:" MACHINE_FEATURES:append = " optee " @@ -16,14 +16,10 @@ KERNEL_IMAGETYPES = "fitImage" DTB_LOAD = "0x90000000" UBOOT_ENTRYPOINT = "0x80080000" -UBOOT_CONFIG ??= "tfa-secure-boot tfa" +UBOOT_CONFIG ?= "tfa-secure-boot tfa" UBOOT_CONFIG[tfa] = "lx2160acex7_tfa_defconfig,,u-boot-dtb.bin" UBOOT_CONFIG[tfa-secure-boot] = "lx2160ardb_tfa_SECURE_BOOT_defconfig,,u-boot-dtb.bin" -KERNEL_DEVICETREE ?= " \ - freescale/fsl-lx2160a-clearfog-cx.dtb \ - freescale/fsl-lx2160a-honeycomb.dtb \ -" KERNEL_DEFCONFIG ?= "defconfig" SERIAL_CONSOLES ?= "115200;ttyS0 115200;ttyS1 115200;ttyAMA0" @@ -34,11 +30,6 @@ LX2160A_CPU_SPEED ?= "2000" LX2160A_DDR_SPEED ?= "2900" UEFI_XSPIBOOT ?= "LX2160ARDB_EFI_NORBOOT.fd" -BOOTTYPE ?= "flexspi_nor sd emmc auto" -RCWXSPI ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_xspi" -RCWSD ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_sdhc" -RCWEMMC ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_sdhc" -RCWAUTO ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_auto" EXTRA_IMAGEDEPENDS += "management-complex mc-utils rcw ls2-phy ddr-phy uefi qoriq-atf inphi" USE_VT = "0" @@ -51,7 +42,4 @@ IMAGE_BOOT_FILES:append = "${KERNEL_DEVICETREE}" # select DPL/DPC source (config/lx2160a/LX2160A-) MC_FLAVOUR ?= "CEX7" -# select DPL/DPC (config/lx2160a/LX2160A-/) -# variable consumed in wks files -MC_DPC ?= "clearfog-cx-s1_8-s2_0-dpc.dtb" -MC_DPL ?= "clearfog-cx-s1_8-s2_0-dpl.dtb" +RCW_FOLDER ?= "lx2160acex7" diff --git a/conf/machine/include/lx2162asom-rev2.inc b/conf/machine/include/lx2162asom-rev2.inc new file mode 100644 index 0000000..2c7a22d --- /dev/null +++ b/conf/machine/include/lx2162asom-rev2.inc @@ -0,0 +1,46 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2162A SoM +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2162A Rev 2.0 System on Module + +require conf/machine/include/qoriq-arm64.inc +require conf/machine/include/arm/armv8a/tune-cortexa72.inc + +MACHINEOVERRIDES =. "lx2162a-som:fsl-lsch3:lx2162a:" + +MACHINE_FEATURES:append = " optee " + +KERNEL_CLASSES = " kernel-fitimage " +KERNEL_IMAGETYPES = "fitImage" + +DTB_LOAD = "0x90000000" +UBOOT_ENTRYPOINT = "0x80080000" + +UBOOT_CONFIG ?= "tfa-secure-boot tfa" +UBOOT_CONFIG[tfa] = "lx2160acex7_tfa_defconfig,,u-boot-dtb.bin" +UBOOT_CONFIG[tfa-secure-boot] = "lx2160ardb_tfa_SECURE_BOOT_defconfig,,u-boot-dtb.bin" + +KERNEL_DEFCONFIG ?= "defconfig" + +SERIAL_CONSOLES ?= "115200;ttyS0 115200;ttyS1 115200;ttyAMA0" +SERIAL_CONSOLES_CHECK ?= "${SERIAL_CONSOLES}" + +LX2160A_BUS_SPEED ?= "650" +LX2160A_CPU_SPEED ?= "2000" +LX2160A_DDR_SPEED ?= "2900" + +UEFI_XSPIBOOT ?= "LX2160ARDB_EFI_NORBOOT.fd" + +EXTRA_IMAGEDEPENDS += "management-complex mc-utils rcw ls2-phy ddr-phy uefi qoriq-atf inphi" +USE_VT = "0" + +# install the vendor-prefixed dtbs +# Note: must keep the non-prefixed versions in place, +# to ensure bootimg-partition.py does not mess with extlinux.conf fdtdir +IMAGE_BOOT_FILES:append = "${KERNEL_DEVICETREE}" + +# select DPL/DPC source (config/lx2162a/LX2162A-) +MC_FLAVOUR ?= "SOM" + +# select rev2 rcw +RCW_FOLDER ?= "lx2162asom_rev2" diff --git a/conf/machine/lx2160a-clearfog-cx.conf b/conf/machine/lx2160a-clearfog-cx.conf new file mode 100644 index 0000000..777283a --- /dev/null +++ b/conf/machine/lx2160a-clearfog-cx.conf @@ -0,0 +1,7 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A Clearfog-CX +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2160A 1.0 Clearfog CX Board + +require conf/machine/include/lx2160acex7.inc +require conf/machine/include/lx2160a-clearfog-cx.inc diff --git a/conf/machine/lx2160a-honeycomb.conf b/conf/machine/lx2160a-honeycomb.conf new file mode 100644 index 0000000..8ffb893 --- /dev/null +++ b/conf/machine/lx2160a-honeycomb.conf @@ -0,0 +1,7 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A Honeycomb +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2160A 1.0 Honeycomb Board + +require conf/machine/include/lx2160acex7.inc +require conf/machine/include/lx2160a-clearfog-cx.inc diff --git a/conf/machine/lx2160a-rev2-cex6-evb.conf b/conf/machine/lx2160a-rev2-cex6-evb.conf new file mode 100644 index 0000000..03ebe3d --- /dev/null +++ b/conf/machine/lx2160a-rev2-cex6-evb.conf @@ -0,0 +1,21 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A CEX-6 EVB +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun Internal LX2160A Rev 2.0 COM-Express Type 6 Evaluation Board + +require conf/machine/include/lx2160acex7.inc +require conf/machine/include/lx2160a-clearfog-cx.inc + +# select DTBs +KERNEL_DEVICETREE ?= " \ + freescale/fsl-lx2160a-cex6-evb.dtb \ +" + +# select DPL/DPC (config/lx2160a/LX2160A-/) +# variable consumed in wks files +MC_DPC ?= "evb-s1_3-s2_0-dpc.dtb" +MC_DPL ?= "evb-s1_3-s2_0-dpl.dtb" + +# select RCW +BOOTTYPE ?= "auto" +RCWAUTO ?= "evb/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_3_3_2_auto" diff --git a/conf/machine/lx2160a-rev2-clearfog-cx.conf b/conf/machine/lx2160a-rev2-clearfog-cx.conf new file mode 100644 index 0000000..21ae7a6 --- /dev/null +++ b/conf/machine/lx2160a-rev2-clearfog-cx.conf @@ -0,0 +1,7 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A Clearfog-CX +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2160A 2.0 Clearfog CX Board + +require conf/machine/include/lx2160acex7-rev2.inc +require conf/machine/include/lx2160a-clearfog-cx.inc diff --git a/conf/machine/lx2160a-rev2-honeycomb.conf b/conf/machine/lx2160a-rev2-honeycomb.conf new file mode 100644 index 0000000..9dd785b --- /dev/null +++ b/conf/machine/lx2160a-rev2-honeycomb.conf @@ -0,0 +1,7 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2160A Honeycomb +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2160A 2.0 Honeycomb Board + +require conf/machine/include/lx2160acex7-rev2.inc +require conf/machine/include/lx2160a-clearfog-cx.inc diff --git a/conf/machine/lx2160acex7-rev2.conf b/conf/machine/lx2160acex7-rev2.conf deleted file mode 100644 index 7a4c798..0000000 --- a/conf/machine/lx2160acex7-rev2.conf +++ /dev/null @@ -1,8 +0,0 @@ -#@TYPE: Machine -#@NAME: SolidRun LX2160ACEX7 -#@SOC: LSCH3 -#@DESCRIPTION: Machine configuration for SolidRun LX2160A 2.0 Com-Express Type 7 Module - -require conf/machine/lx2160acex7.conf - -RCW_FOLDER ?= "lx2160acex7_rev2" diff --git a/conf/machine/lx2162a-rev2-clearfog.conf b/conf/machine/lx2162a-rev2-clearfog.conf new file mode 100644 index 0000000..acfe46a --- /dev/null +++ b/conf/machine/lx2162a-rev2-clearfog.conf @@ -0,0 +1,21 @@ +#@TYPE: Machine +#@NAME: SolidRun LX2162A Clearfog +#@SOC: LSCH3 +#@DESCRIPTION: Machine configuration for SolidRun LX2162A 2.0 Clearfog Board + +require conf/machine/include/lx2162asom-rev2.inc + + +# select DTBs +KERNEL_DEVICETREE ?= " \ + freescale/fsl-lx2162a-clearfog.dtb \ +" + +# select DPL/DPC (config/lx2162a/LX2162A-/) +# variable consumed in wks files +MC_DPC ?= "clearfog-s1_3-s2_9-dpc.dtb" +MC_DPL ?= "clearfog-s1_3-s2_9-dpl.dtb" + +# select RCW +BOOTTYPE ?= "auto" +RCWAUTO ?= "clearfog/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_18_9_0_auto" diff --git a/recipes-bsp/atf/qoriq-atf-2.6/0014-add-separate-platform-for-solidrun-lx2162a-som.patch b/recipes-bsp/atf/qoriq-atf-2.6/0014-add-separate-platform-for-solidrun-lx2162a-som.patch new file mode 100644 index 0000000..0172514 --- /dev/null +++ b/recipes-bsp/atf/qoriq-atf-2.6/0014-add-separate-platform-for-solidrun-lx2162a-som.patch @@ -0,0 +1,597 @@ +From 956be9ce8f365e7f9ac7d7d1f896f1c2a27f6287 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 27 Oct 2024 18:00:11 +0100 +Subject: [PATCH] add separate platform for solidrun lx2162a som + +Signed-off-by: Josua Mayer +--- + plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c | 290 ++++++++++++++++++ + plat/nxp/soc-lx2160a/lx2162asom/plat_def.h | 105 +++++++ + plat/nxp/soc-lx2160a/lx2162asom/platform.c | 29 ++ + plat/nxp/soc-lx2160a/lx2162asom/platform.mk | 61 ++++ + .../nxp/soc-lx2160a/lx2162asom/platform_def.h | 14 + + plat/nxp/soc-lx2160a/lx2162asom/policy.h | 38 +++ + 6 files changed, 537 insertions(+) + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/plat_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.c + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.mk + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform_def.h + create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/policy.h + +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c +new file mode 100644 +index 000000000..2cadab7ba +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c +@@ -0,0 +1,290 @@ ++/* ++ * Copyright 2018-2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "plat_common.h" ++#include ++ ++#ifdef CONFIG_STATIC_DDR ++#error not implemented ++#elif defined(CONFIG_DDR_NODIMM) ++#if CONFIG_DDR_NODIMM == 1 ++/* ++ * SoM Revision 1.1: 9 x K4A8G085WC-BCWE (SDP, 8GB w/ ECC) ++ * ++ * Use in production for units with empty SPD, ++ * and development. ++ */ ++static const struct dimm_params static_dimm = { ++ .mpart = "Fixed DDR Config 1", ++ .n_ranks = 1, ++ .die_density = 0x5, // encoded per spd byte 4, 0b101 = 8Gbit ++ .rank_density = 0x200000000, // 8GB ++ .capacity = 0x200000000, // 8GB ++ .primary_sdram_width = 64, ++ .ec_sdram_width = 8, // 8 bit ecc extension ++ .rdimm = 0, ++ .package_3ds = 0, ++ .device_width = 8, // 8 bit per sdram ++ .rc = 0, ++ ++ .n_row_addr = 16, ++ .n_col_addr = 10, ++ .edc_config = 2, // enable ecc ++ .bank_addr_bits = 0, // 4 banks ++ .bank_group_bits = 2, // 4 bank groups ++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) ++ ++ .mirrored_dimm = 0, ++ ++ // timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200 ++ .mtb_ps = 125, // MTB per SPD spec ++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver ++ .taa_ps = 13750, // min. 13.75ns ++ .tfaw_ps = 21000, // min: max(21ns or 20CK) (this 8Gbit sdram has 1KB pages) ++ ++ .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmax_ps = 1250, // 1600 (CK=800) ++ ++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL) ++ ++ .trcd_ps = 13750, // 13.75ns - CL22-22-22 ++ .trp_ps = 13750, // 13.75ns - CL22-22-22 ++ .tras_ps = 32000, // 32ns ++ ++ .trfc1_ps = 350000, // 350ns ++ .trfc2_ps = 260000, // 260ns ++ .trfc4_ps = 160000, // 160ns ++ .trrds_ps = 3300, // min: max(4CK or 3.3ns) ++ .trrdl_ps = 4900, // min: max(4CK or 6.4ns) ++ .tccdl_ps = 5000, // min: max(5CK or 5ns) ++ .trfc_slr_ps = 0, ++ ++ .trc_ps = 45750, // tras + trp 45.75ns ++ .twr_ps = 15000, // 15ns ++ ++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!) ++ // .extended_op_srt = 0, ++ ++ // .rcw = {}, // only for registered dimm ++ .dq_mapping = { ++ 0x16, // DQ[0:3]: lower nibble, bit order 3120 ++ 0x22, // DQ[4:7]: upper nibble, bit order 4576 ++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031 ++ 0x30, // DQ[12:15]: upper nibble, bit order 6574 ++ 0x14, // DQ[16:19]: lower nibble, bit order 3021 ++ 0x36, // DQ[20:23]: upper nibble, bit order 7564 ++ 0x11, // DQ[24:27]: lower nibble, bit order 2301 ++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547 ++ 0x03, // ECC[0:3]: lower nibble, bit order 0213 ++ 0x22, // ECC[4:7]: upper nibble, bit order 4576 ++ 0x10, // DQ[32:35]: lower nibble, bit order 2130 ++ 0x30, // DQ[36:39]: upper nibble, bit order 6574 ++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031 ++ 0x34, // DQ[44:47]: upper nibble, bit order 7465 ++ 0x14, // DQ[48:51]: lower nibble, bit order 3021 ++ 0x36, // DQ[52:55]: upper nibble, bit order 7564 ++ 0x10, // DQ[56:59]: lower nibble, bit order 2130 ++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746 ++ }, ++ .dq_mapping_ors = 1, ++}; ++#endif /* CONFIG_DDR_NODIMM == 1 */ ++ ++#if CONFIG_DDR_NODIMM == 2 ++/* ++ * SoM Revision 1.1: 9 x K4AAG085WA-BCWE (DDP, 16GB w/ ECC) ++ * ++ * Use in production for units with empty SPD, ++ * and development. ++ */ ++static const struct dimm_params static_dimm = { ++ .mpart = "Fixed DDR Config 2", ++ .n_ranks = 1, ++ .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit ++ // TODO: for DDP memory should have 2 ranks per DIMM + correct density per die? ++ .rank_density = 0x400000000, // 16GB ++ .capacity = 0x400000000, // 16GB ++ .primary_sdram_width = 64, ++ .ec_sdram_width = 8, // 8 bit ecc extension ++ .rdimm = 0, ++ .package_3ds = 0, ++ .device_width = 8, // 8 bit per sdram ++ .rc = 0, ++ ++ .n_row_addr = 17, ++ .n_col_addr = 10, ++ .edc_config = 2, // enable ecc ++ .bank_addr_bits = 0, // 4 banks ++ .bank_group_bits = 2, // 4 bank groups ++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec) ++ ++ .mirrored_dimm = 0, ++ ++ .mtb_ps = 125, // MTB per SPD spec ++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver ++ .taa_ps = 13750, // min. 13.75ns ++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages) ++ ++ .tckmin_x_ps = 625, // 3200 (CK=1600) ++ .tckmax_ps = 1250, // 1600 (CK=800) ++ ++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL) ++ ++ .trcd_ps = 13750, // 13.75ns ++ .trp_ps = 13750, // 13.75ns ++ .tras_ps = 32000, // 32ns ++ ++ .trfc1_ps = 350000, // 350ns, assumed same as 8Gbit SDP module ++ .trfc2_ps = 260000, // 260ns, assumed same as 8Gbit SDP module ++ .trfc4_ps = 160000, // 160ns, assumed same as 8Gbit SDP module ++ .trrds_ps = 5300, // min: max(4CK or 5.3ns) ++ .trrdl_ps = 6400, // min: max(4CK or 6.4ns) ++ .tccdl_ps = 5000, // min: max(5CK or 5ns) ++ .trfc_slr_ps = 0, ++ ++ .trc_ps = 45750, // tras + trp 45.75ns ++ .twr_ps = 15000, // 15ns ++ ++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!) ++ // .extended_op_srt = 0, ++ ++ // .rcw = {}, // only for registered dimm ++ .dq_mapping = { ++ 0x16, // DQ[0:3]: lower nibble, bit order 3120 ++ 0x22, // DQ[4:7]: upper nibble, bit order 4576 ++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031 ++ 0x30, // DQ[12:15]: upper nibble, bit order 6574 ++ 0x14, // DQ[16:19]: lower nibble, bit order 3021 ++ 0x36, // DQ[20:23]: upper nibble, bit order 7564 ++ 0x11, // DQ[24:27]: lower nibble, bit order 2301 ++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547 ++ 0x03, // ECC[0:3]: lower nibble, bit order 0213 ++ 0x22, // ECC[4:7]: upper nibble, bit order 4576 ++ 0x10, // DQ[32:35]: lower nibble, bit order 2130 ++ 0x30, // DQ[36:39]: upper nibble, bit order 6574 ++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031 ++ 0x34, // DQ[44:47]: upper nibble, bit order 7465 ++ 0x14, // DQ[48:51]: lower nibble, bit order 3021 ++ 0x36, // DQ[52:55]: upper nibble, bit order 7564 ++ 0x10, // DQ[56:59]: lower nibble, bit order 2130 ++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746 ++ }, ++ .dq_mapping_ors = 1, ++}; ++#endif /* CONFIG_DDR_NODIMM == 2 */ ++ ++int ddr_get_ddr_params(struct dimm_params *pdimm, ++ struct ddr_conf *conf) ++{ ++ // channel 1 ++ conf->dimm_in_use[0] = 1; ++ memcpy(&pdimm[0], &static_dimm, sizeof(struct dimm_params)); ++ ++ /* 1 module */ ++ return 0x1; ++} ++#endif /* defined(CONFIG_DDR_NODIMM) */ ++ ++int ddr_board_options(struct ddr_info *priv) ++{ ++ struct memctl_opt *popts = &priv->opt; ++ ++ popts->caslat_override = 0; ++ popts->caslat_override_value = 0; ++ popts->auto_self_refresh_en = 1; ++ popts->output_driver_impedance = 0; // 34 Ohm ++ popts->twot_en = 0; ++ popts->threet_en = 0; ++ popts->addt_lat_override = 0; ++ popts->addt_lat_override_value = 0; ++ popts->phy_atx_impedance = 30; ++ popts->skip2d = 0; ++ popts->vref_dimm = U(0x19); /* range 1, 83.4% */ ++ ++ popts->rtt_override = 0; ++ popts->rtt_park = 120U; ++ popts->otf_burst_chop_en = 0; ++ popts->burst_length = DDR_BL8; ++ popts->trwt_override = 1; ++ popts->bstopre = 0; /* auto precharge */ ++ popts->addr_hash = 1; ++ popts->trwt = 0x3; ++ popts->twrt = 0x3; ++ popts->trrt = 0x3; ++ popts->twwt = 0x3; ++ popts->vref_phy = U(0x5D); /* 72% */ ++ popts->odt = 60U; ++ popts->phy_tx_impedance = 28U; ++ ++ return 0; ++} ++ ++#ifdef NXP_WARM_BOOT ++long long init_ddr(uint32_t wrm_bt_flg) ++#else ++long long init_ddr(void) ++#endif ++{ ++ int spd_addr[] = { 0x51 }; ++ struct ddr_info info; ++ struct sysinfo sys; ++ long long dram_size; ++ ++ zeromem(&sys, sizeof(sys)); ++ if (get_clocks(&sys) != 0) { ++ ERROR("System clocks are not set\n"); ++ panic(); ++ } ++ debug("platform clock %lu\n", sys.freq_platform); ++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); ++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); ++ ++ zeromem(&info, sizeof(info)); ++ ++ /* Set two DDRC. Unused DDRC will be removed automatically. */ ++ info.num_ctlrs = NUM_OF_DDRC; ++ info.spd_addr = spd_addr; ++ info.ddr[0] = (void *)NXP_DDR_ADDR; ++ info.ddr[1] = (void *)NXP_DDR2_ADDR; ++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; ++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; ++ info.clk = get_ddr_freq(&sys, 0); ++ info.img_loadr = load_img; ++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER; ++ if (info.clk == 0) { ++ info.clk = get_ddr_freq(&sys, 1); ++ } ++ info.dimm_on_ctlr = DDRC_NUM_DIMM; ++ ++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED; ++ ++ dram_size = dram_init(&info ++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) ++ , NXP_CCN_HN_F_0_ADDR ++#endif ++ ); ++ ++ ++ if (dram_size < 0) { ++ ERROR("DDR init failed.\n"); ++ } ++ ++ return dram_size; ++} +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h +new file mode 100644 +index 000000000..de2d2444a +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h +@@ -0,0 +1,105 @@ ++/* ++ * Copyright 2018-2021 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLAT_DEF_H ++#define PLAT_DEF_H ++ ++#include ++#include ++/* Required without TBBR. ++ * To include the defines for DDR PHY ++ * Images. ++ */ ++#include ++ ++#include ++#include ++ ++#if defined(IMAGE_BL31) ++#define LS_SYS_TIMCTL_BASE 0x2890000 ++#define PLAT_LS_NSTIMER_FRAME_ID 0 ++#define LS_CONFIG_CNTACR 1 ++#endif ++ ++#define NXP_SYSCLK_FREQ 100000000 ++#define NXP_DDRCLK_FREQ 100000000 ++ ++/* UART related definition */ ++#define NXP_CONSOLE_ADDR NXP_UART_ADDR ++#define NXP_CONSOLE_BAUDRATE 115200 ++ ++/* Size of cacheable stacks */ ++#if defined(IMAGE_BL2) ++#if defined(TRUSTED_BOARD_BOOT) ++#define PLATFORM_STACK_SIZE 0x2000 ++#else ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++#elif defined(IMAGE_BL31) ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++ ++/* SD block buffer */ ++#define NXP_SD_BLOCK_BUF_SIZE (0x8000) ++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++ ++#ifdef SD_BOOT ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ ++ - NXP_SD_BLOCK_BUF_SIZE) ++#else ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) ++#endif ++ ++/* IO defines as needed by IO driver framework */ ++#define MAX_IO_DEVICES 4 ++#define MAX_IO_BLOCK_DEVICES 1 ++#define MAX_IO_HANDLES 4 ++ ++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) ++ ++/* ++ * FIP image defines - Offset at which FIP Image would be present ++ * Image would include Bl31 , Bl33 and Bl32 (optional) ++ */ ++#ifdef POLICY_FUSE_PROVISION ++#define MAX_FIP_DEVICES 3 ++#endif ++ ++#ifndef MAX_FIP_DEVICES ++#define MAX_FIP_DEVICES 2 ++#endif ++ ++/* ++ * ID of the secure physical generic timer interrupt used by the BL32. ++ */ ++#define BL32_IRQ_SEC_PHY_TIMER 29 ++ ++#define BL31_WDOG_SEC 89 ++ ++#define BL31_NS_WDOG_WS1 108 ++ ++/* ++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++#define PLAT_LS_G1S_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE) ++ ++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ ++#define NXP_IRQ_SEC_SGI_7 15 ++ ++#define PLAT_LS_G0_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_LEVEL) ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.c b/plat/nxp/soc-lx2160a/lx2162asom/platform.c +new file mode 100644 +index 000000000..7622cf09a +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.c +@@ -0,0 +1,29 @@ ++/* ++ * Copyright 2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#include ++ ++#pragma weak board_enable_povdd ++#pragma weak board_disable_povdd ++ ++bool board_enable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} ++ ++bool board_disable_povdd(void) ++{ ++#ifdef CONFIG_POVDD_ENABLE ++ return true; ++#else ++ return false; ++#endif ++} +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.mk b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk +new file mode 100644 +index 000000000..c1ba077e9 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk +@@ -0,0 +1,61 @@ ++# ++# Copyright 2018-2020 NXP ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++# board-specific build parameters ++ ++BOOT_MODE ?= flexspi_nor ++BOARD ?= lx2162asom ++POVDD_ENABLE := no ++NXP_COINED_BB := no ++ ++ # DDR Compilation Configs ++NUM_OF_DDRC := 1 ++DDRC_NUM_DIMM := 1 ++DDRC_NUM_CS := 2 ++DDR_ECC_EN := yes ++ #enable address decoding feature ++DDR_ADDR_DEC := yes ++APPLY_MAX_CDD := yes ++ ++# Mock SPD: ++# - 0: disable mock spd ++# - 1: 9 x K4A8G085WC-BCWE SoM v1.1 8GB w/ ECC ++# - 2: 9 x K4AAG085WA-BCWE SoM v1.1 16GB w/ ECC ++CONFIG_DDR_NODIMM := 0 ++ ++# I2C Bus Flushing: IIC1 (SPD EEPROM) ++LX2160_FLUSH_IIC := 1, ++ ++# DDR Errata ++ERRATA_DDR_A011396 := 1 ++ERRATA_DDR_A050450 := 1 ++ ++# On-Board Flash Details ++FLASH_TYPE := MT35XU512A ++XSPI_FLASH_SZ := 0x10000000 ++NXP_XSPI_NOR_UNIT_SIZE := 0x20000 ++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 ++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This ++# config is enabled for future use cases. ++FSPI_ERASE_4K := 0 ++ ++# Platform specific features. ++WARM_BOOT := no ++ ++# Adding Platform files build files ++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ ++ ${BOARD_PATH}/platform.c ++ ++SUPPORTED_BOOT_MODE := flexspi_nor \ ++ sd \ ++ emmc \ ++ auto ++ ++# Adding platform board build info ++include plat/nxp/common/plat_make_helper/plat_common_def.mk ++ ++# Adding SoC build info ++include plat/nxp/soc-lx2160a/soc.mk +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h +new file mode 100644 +index 000000000..5fa774e90 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h +@@ -0,0 +1,14 @@ ++/* ++ * Copyright 2018-2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef PLATFORM_DEF_H ++#define PLATFORM_DEF_H ++ ++#include "plat_def.h" ++#include "plat_default_def.h" ++ ++#endif +diff --git a/plat/nxp/soc-lx2160a/lx2162asom/policy.h b/plat/nxp/soc-lx2160a/lx2162asom/policy.h +new file mode 100644 +index 000000000..1095f3840 +--- /dev/null ++++ b/plat/nxp/soc-lx2160a/lx2162asom/policy.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright 2018-2020 NXP ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ */ ++ ++#ifndef POLICY_H ++#define POLICY_H ++ ++/* Following defines affect the PLATFORM SECURITY POLICY */ ++ ++/* set this to 0x0 if the platform is not using/responding to ECC errors ++ * set this to 0x1 if ECC is being used (we have to do some init) ++ */ ++#define POLICY_USING_ECC 0x0 ++ ++/* Set this to 0x0 to leave the default SMMU page size in sACR ++ * Set this to 0x1 to change the SMMU page size to 64K ++ */ ++#define POLICY_SMMU_PAGESZ_64K 0x1 ++ ++/* ++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I ++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7 ++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23 ++ */ ++#define POLICY_PERF_WRIOP 0 ++ ++/* ++ * set this to '1' if the debug clocks need to remain enabled during ++ * system entry to low-power (LPM20) - this should only be necessary ++ * for testing and NEVER set for normal production ++ */ ++#define POLICY_DEBUG_ENABLE 0 ++ ++ ++#endif /* POLICY_H */ +-- +2.43.0 + diff --git a/recipes-bsp/atf/qoriq-atf_2.6.bbappend b/recipes-bsp/atf/qoriq-atf_2.6.bbappend index 6f22fa3..6aa6177 100644 --- a/recipes-bsp/atf/qoriq-atf_2.6.bbappend +++ b/recipes-bsp/atf/qoriq-atf_2.6.bbappend @@ -15,8 +15,9 @@ SRC_URI += "file://0001-plat-nxp-lx2160a-auto-boot.patch \ file://0011-lx2160acex7-flush-i2c-bus-with-spd-eeprom-before-ddr.patch \ file://0012-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch \ file://0013-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch \ + file://0014-add-separate-platform-for-solidrun-lx2162a-som.patch \ " -PLATFORM:lx2160acex6-rev2 = "lx2160acex6" -PLATFORM:lx2160acex7 = "lx2160acex7" -PLATFORM:lx2160acex7-rev2 = "lx2160acex7" +PLATFORM:lx2160a-cex6 = "lx2160acex6" +PLATFORM:lx2160a-cex7 = "lx2160acex7" +PLATFORM:lx2162a-som = "lx2162asom" diff --git a/recipes-bsp/mc-utils/files/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch b/recipes-bsp/mc-utils/files/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch new file mode 100644 index 0000000..550d04b --- /dev/null +++ b/recipes-bsp/mc-utils/files/0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch @@ -0,0 +1,3622 @@ +From 6e7355c062f643227f7d80029bad46f8542048d2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 28 Oct 2024 17:01:33 +0100 +Subject: [PATCH] add configuration for lx2162a som and clearfog board + +Signed-off-by: Josua Mayer +--- + .../LX2160A-CEX7/null-s1_0-s2_0-dpl.dts | 19 + + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts | 119 ++ + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts | 1535 ++++++++++++++ + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts | 127 ++ + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts | 1759 +++++++++++++++++ + 5 files changed, 3559 insertions(+) + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts + create mode 100644 config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts + +diff --git a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +index 9847cc3..8411680 100644 +--- a/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts ++++ b/config/lx2160a/LX2160A-CEX7/null-s1_0-s2_0-dpl.dts +@@ -41,6 +41,16 @@ + type = "dpmcp"; + ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; + }; ++ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; + }; + }; + }; +@@ -150,6 +160,15 @@ + + dpmcp@35 { + }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; + }; + + connections { +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts +new file mode 100644 +index 0000000..0f0ec4b +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpc.dts +@@ -0,0 +1,119 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <64>; ++ }; ++ }; ++ ++ board_info { ++ recycle_ports { ++ recycle@1 { ++ max_rate = "1G"; ++ }; ++ ++ recycle@2 { ++ max_rate = "1G"; ++ }; ++ }; ++ ++ ports { ++ /* Serdes 1 */ ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ /* Serdes 2 */ ++ mac@12 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@13 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@14 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@16 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@18 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +new file mode 100644 +index 0000000..35afac5 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +@@ -0,0 +1,1535 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 1 2 3 4 5 6 7 8 9 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 12 13 14 16 17 18 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 1 2 3 4 5 6 7 8 9 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@1 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@2 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@3 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@4 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@5 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@6 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@7 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@8 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@9 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@16 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@32 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@33 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@34 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@35 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@36 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@37 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@38 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@39 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@40 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@41 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@42 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@43 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@44 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@45 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@46 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@47 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@48 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@49 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@50 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@51 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@52 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@53 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@54 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@55 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@56 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@57 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@58 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@59 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@60 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@61 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@62 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@63 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@64 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@65 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@66 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@67 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@68 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@69 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@70 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@71 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@72 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@73 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@74 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@75 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@76 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@77 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@78 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@79 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@80 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@81 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@82 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@83 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@84 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@85 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@86 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@87 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@88 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@89 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@90 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@91 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@92 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@93 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@94 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@95 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@96 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@97 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@98 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@99 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@100 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@101 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@102 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@103 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@104 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@105 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@106 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@107 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@108 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@109 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@110 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@111 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@112 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@113 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@114 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@115 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@116 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@117 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@118 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@119 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@120 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@121 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@122 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@123 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@124 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@125 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@126 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@127 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@128 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@129 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@130 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@131 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@132 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@133 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@134 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@135 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@136 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@137 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@138 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@139 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@140 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@141 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@142 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@143 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@144 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@145 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@146 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@147 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@148 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@149 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@150 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@151 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@152 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@153 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@154 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@155 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@156 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@157 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@158 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@159 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@12 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@13 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@14 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@16 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@18 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@53 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@54 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@55 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@56 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@57 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@58 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@59 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@60 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@61 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@1 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@2 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@3 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@4 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@5 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@6 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@7 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@8 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@9 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ /*connection@1{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@3"; ++ }; ++ ++ connection@2{ ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@4"; ++ }; ++ ++ connection@3{ ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@5"; ++ }; ++ ++ connection@4{ ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@6"; ++ }; ++ ++ connection@5{ ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@12"; ++ }; ++ ++ connection@6{ ++ endpoint1 = "dpni@5"; ++ endpoint2 = "dpmac@13"; ++ }; ++ ++ connection@7{ ++ endpoint1 = "dpni@6"; ++ endpoint2 = "dpmac@14"; ++ }; ++ ++ connection@8{ ++ endpoint1 = "dpni@7"; ++ endpoint2 = "dpmac@16"; ++ }; ++ ++ connection@9{ ++ endpoint1 = "dpni@8"; ++ endpoint2 = "dpmac@17"; ++ }; ++ ++ connection@10{ ++ endpoint1 = "dpni@9"; ++ endpoint2 = "dpmac@18"; ++ };*/ ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts +new file mode 100644 +index 0000000..5aa4640 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpc.dts +@@ -0,0 +1,127 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ resources { ++ icid_pools { ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <64>; ++ }; ++ }; ++ ++ board_info { ++ recycle_ports { ++ recycle@1 { ++ max_rate = "1G"; ++ }; ++ ++ recycle@2 { ++ max_rate = "1G"; ++ }; ++ }; ++ ++ ports { ++ /* Serdes 1 */ ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ /* Serdes 2 */ ++ mac@11 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@12 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@13 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@14 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@15 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@16 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ ++ mac@18 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +new file mode 100644 +index 0000000..1745da4 +--- /dev/null ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +@@ -0,0 +1,1759 @@ ++/* ++ * Copyright 2020 NXP ++ * Copyright 2022 Josua Mayer ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++/ { ++ dpl-version = <10>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ ++ dprc@1 { ++ compatible = "fsl,dprc"; ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ ++ objects { ++ ++ /* -------------- DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 >; ++ }; ++ ++ /* -------------- DPCONs --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 >; ++ }; ++ ++ /* -------------- DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >; ++ }; ++ ++ /* -------------- DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <3 4 5 6 11 12 13 14 15 16 17 18 >; ++ }; ++ ++ /* -------------- DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 >; ++ }; ++ ++ /* -------------- DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0 1 2 3 4 5 6 7 8 9 10 11 >; ++ }; ++ ++ /* -------------- DPRTCs --------------*/ ++ obj_set@dprtc { ++ type = "dprtc"; ++ ids = <0 >; ++ }; ++ ++ /* -------------- DPSECIs --------------*/ ++ obj_set@dpseci { ++ type = "dpseci"; ++ ids = <0 >; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ dpbp@0 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@1 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@2 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@3 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@4 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@5 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@6 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@7 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@8 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@9 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@10 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpbp@11 { ++ compatible = "fsl,dpbp"; ++ }; ++ ++ dpcon@0 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@16 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@32 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@33 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@34 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@35 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@36 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@37 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@38 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@39 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@40 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@41 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@42 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@43 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@44 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@45 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@46 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@47 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@48 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@49 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@50 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@51 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@52 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@53 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@54 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@55 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@56 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@57 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@58 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@59 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@60 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@61 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@62 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@63 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@64 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@65 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@66 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@67 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@68 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@69 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@70 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@71 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@72 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@73 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@74 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@75 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@76 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@77 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@78 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@79 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@80 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@81 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@82 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@83 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@84 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@85 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@86 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@87 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@88 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@89 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@90 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@91 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@92 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@93 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@94 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@95 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@96 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@97 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@98 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@99 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@100 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@101 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@102 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@103 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@104 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@105 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@106 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@107 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@108 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@109 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@110 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@111 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@112 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@113 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@114 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@115 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@116 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@117 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@118 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@119 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@120 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@121 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@122 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@123 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@124 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@125 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@126 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@127 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@128 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@129 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@130 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@131 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@132 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@133 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@134 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@135 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@136 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@137 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@138 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@139 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@140 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@141 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@142 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@143 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@144 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@145 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@146 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@147 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@148 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@149 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@150 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@151 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@152 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@153 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@154 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@155 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@156 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@157 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@158 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@159 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@160 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@161 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@162 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@163 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@164 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@165 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@166 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@167 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@168 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@169 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@170 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@171 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@172 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@173 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@174 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@175 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@176 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@177 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@178 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@179 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@180 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@181 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@182 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@183 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@184 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@185 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@186 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@187 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@188 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@189 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@190 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@191 { ++ compatible = "fsl,dpcon"; ++ num_priorities = <0x2>; ++ }; ++ ++ dpio@0 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ compatible = "fsl,dpio"; ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpmac@3 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@4 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@5 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@6 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@11 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@12 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@13 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@14 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@15 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@16 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@17 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmac@18 { ++ compatible = "fsl,dpmac"; ++ }; ++ ++ dpmcp@1 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@2 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@3 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@4 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@5 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@6 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@7 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@8 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@9 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@10 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@11 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@12 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@13 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@14 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@15 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@16 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@17 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@18 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@19 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@20 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@21 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@22 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@23 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@24 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@25 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@26 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@27 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@28 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@29 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@30 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@31 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@32 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@33 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@34 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@35 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@36 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@37 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@38 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@39 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@40 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@41 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@42 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@43 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@44 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@45 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@46 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@47 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@48 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@49 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@50 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@51 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@52 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@53 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@54 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@55 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@56 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@57 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@58 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@59 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@60 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@61 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@62 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpmcp@63 { ++ compatible = "fsl,dpmcp"; ++ }; ++ ++ dpni@0 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@1 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@2 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@3 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@4 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@5 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@6 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@7 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@8 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@9 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@10 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dpni@11 { ++ compatible = "fsl,dpni"; ++ type = "DPNI_TYPE_NIC"; ++ num_queues = <16>; ++ num_tcs = <1>; ++ num_cgs = <1>; ++ mac_filter_entries = <16>; ++ vlan_filter_entries = <0>; ++ fs_entries = <64>; ++ qos_entries = <0>; ++ dist_key_size = <56>; ++ num_channels= <1>; ++ num_opr = <0>; ++ }; ++ ++ dprtc@0 { ++ compatible = "fsl,dprtc"; ++ }; ++ ++ dpseci@0 { ++ compatible = "fsl,dpseci"; ++ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ ++ /*connection@1{ ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@3"; ++ }; ++ ++ connection@2{ ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@4"; ++ }; ++ ++ connection@3{ ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@5"; ++ }; ++ ++ connection@4{ ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@6"; ++ }; ++ ++ connection@5{ ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@11"; ++ }; ++ ++ connection@6{ ++ endpoint1 = "dpni@5"; ++ endpoint2 = "dpmac@12"; ++ }; ++ ++ connection@7{ ++ endpoint1 = "dpni@6"; ++ endpoint2 = "dpmac@13"; ++ }; ++ ++ connection@8{ ++ endpoint1 = "dpni@7"; ++ endpoint2 = "dpmac@14"; ++ }; ++ ++ connection@9{ ++ endpoint1 = "dpni@8"; ++ endpoint2 = "dpmac@15"; ++ }; ++ ++ connection@10{ ++ endpoint1 = "dpni@9"; ++ endpoint2 = "dpmac@16"; ++ }; ++ ++ connection@11{ ++ endpoint1 = "dpni@10"; ++ endpoint2 = "dpmac@17"; ++ }; ++ ++ connection@12{ ++ endpoint1 = "dpni@11"; ++ endpoint2 = "dpmac@18"; ++ };*/ ++ }; ++}; +-- +2.43.0 + diff --git a/recipes-bsp/mc-utils/files/0004-lx2162-som-clearfog-enable-dpni-connections.patch b/recipes-bsp/mc-utils/files/0004-lx2162-som-clearfog-enable-dpni-connections.patch new file mode 100644 index 0000000..3f8eb93 --- /dev/null +++ b/recipes-bsp/mc-utils/files/0004-lx2162-som-clearfog-enable-dpni-connections.patch @@ -0,0 +1,188 @@ +From 44dd1bb169ab73e5b4d2d27a441bc52b9295e930 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 30 Oct 2024 18:56:20 +0100 +Subject: [PATCH] lx2162: som: clearfog: enable dpni connections + +Enable the dpni connections so that interfaces are created automatically +during boot. Ordering ensures linux netdev numbers are sorted by dpmac +numbers, i.e. eth0 = dpmac3, eth1=dpmac4, ... + +Signed-off-by: Josua Mayer +--- + .../LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts | 26 ++++++++-------- + .../LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts | 30 +++++++++---------- + 2 files changed, 28 insertions(+), 28 deletions(-) + +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +index 35afac5..b6219e9 100644 +--- a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_7-dpl.dts +@@ -1,6 +1,6 @@ + /* + * Copyright 2020 NXP +- * Copyright 2022 Josua Mayer ++ * Copyright 2024 Josua Mayer + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: +@@ -1482,54 +1482,54 @@ + *****************************************************************/ + connections { + +- /*connection@1{ +- endpoint1 = "dpni@0"; ++ connection@1{ ++ endpoint1 = "dpni@9"; + endpoint2 = "dpmac@3"; + }; + + connection@2{ +- endpoint1 = "dpni@1"; ++ endpoint1 = "dpni@8"; + endpoint2 = "dpmac@4"; + }; + + connection@3{ +- endpoint1 = "dpni@2"; ++ endpoint1 = "dpni@7"; + endpoint2 = "dpmac@5"; + }; + + connection@4{ +- endpoint1 = "dpni@3"; ++ endpoint1 = "dpni@6"; + endpoint2 = "dpmac@6"; + }; + + connection@5{ +- endpoint1 = "dpni@4"; ++ endpoint1 = "dpni@5"; + endpoint2 = "dpmac@12"; + }; + + connection@6{ +- endpoint1 = "dpni@5"; ++ endpoint1 = "dpni@4"; + endpoint2 = "dpmac@13"; + }; + + connection@7{ +- endpoint1 = "dpni@6"; ++ endpoint1 = "dpni@3"; + endpoint2 = "dpmac@14"; + }; + + connection@8{ +- endpoint1 = "dpni@7"; ++ endpoint1 = "dpni@2"; + endpoint2 = "dpmac@16"; + }; + + connection@9{ +- endpoint1 = "dpni@8"; ++ endpoint1 = "dpni@1"; + endpoint2 = "dpmac@17"; + }; + + connection@10{ +- endpoint1 = "dpni@9"; ++ endpoint1 = "dpni@0"; + endpoint2 = "dpmac@18"; +- };*/ ++ }; + }; + }; +diff --git a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +index 1745da4..7acb2e2 100644 +--- a/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts ++++ b/config/lx2162a/LX2162A-SOM/clearfog-s1_3-s2_9-dpl.dts +@@ -1,6 +1,6 @@ + /* + * Copyright 2020 NXP +- * Copyright 2022 Josua Mayer ++ * Copyright 2024 Josua Mayer + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: +@@ -1696,64 +1696,64 @@ + *****************************************************************/ + connections { + +- /*connection@1{ +- endpoint1 = "dpni@0"; ++ connection@1{ ++ endpoint1 = "dpni@11"; + endpoint2 = "dpmac@3"; + }; + + connection@2{ +- endpoint1 = "dpni@1"; ++ endpoint1 = "dpni@10"; + endpoint2 = "dpmac@4"; + }; + + connection@3{ +- endpoint1 = "dpni@2"; ++ endpoint1 = "dpni@9"; + endpoint2 = "dpmac@5"; + }; + + connection@4{ +- endpoint1 = "dpni@3"; ++ endpoint1 = "dpni@8"; + endpoint2 = "dpmac@6"; + }; + + connection@5{ +- endpoint1 = "dpni@4"; ++ endpoint1 = "dpni@7"; + endpoint2 = "dpmac@11"; + }; + + connection@6{ +- endpoint1 = "dpni@5"; ++ endpoint1 = "dpni@6"; + endpoint2 = "dpmac@12"; + }; + + connection@7{ +- endpoint1 = "dpni@6"; ++ endpoint1 = "dpni@5"; + endpoint2 = "dpmac@13"; + }; + + connection@8{ +- endpoint1 = "dpni@7"; ++ endpoint1 = "dpni@4"; + endpoint2 = "dpmac@14"; + }; + + connection@9{ +- endpoint1 = "dpni@8"; ++ endpoint1 = "dpni@3"; + endpoint2 = "dpmac@15"; + }; + + connection@10{ +- endpoint1 = "dpni@9"; ++ endpoint1 = "dpni@2"; + endpoint2 = "dpmac@16"; + }; + + connection@11{ +- endpoint1 = "dpni@10"; ++ endpoint1 = "dpni@1"; + endpoint2 = "dpmac@17"; + }; + + connection@12{ +- endpoint1 = "dpni@11"; ++ endpoint1 = "dpni@0"; + endpoint2 = "dpmac@18"; +- };*/ ++ }; + }; + }; +-- +2.43.0 + diff --git a/recipes-bsp/mc-utils/files/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch b/recipes-bsp/mc-utils/files/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch new file mode 100644 index 0000000..1f1cefc --- /dev/null +++ b/recipes-bsp/mc-utils/files/0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch @@ -0,0 +1,52 @@ +From 35dffd4f4a82a18897bf0b78df8f1402ef5e2d03 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 17:35:21 +0100 +Subject: [PATCH] lx2160acex7: clearfog-cx: configure qsfp ports type phy + +Interface type PHY allows Linux to configure ethernet speed at runtime +for each port, rather than sticking to assignment from serdes protocols. + +This is particularly useful with SD1 protocol 18 which by default drives +just two ports at 25Gbps while QSFP connector has 4. +At protocol 18 Linux can switch any of the 8 ports between 10Gbps and +25Gbps as needed. + +Due to lack of software support, the QSFP ports need to define speed in +device-tree. + +Signed-off-by: Josua Mayer +--- + config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +index dcc376e..9a508d2 100644 +--- a/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts ++++ b/config/lx2160a/LX2160A-CEX7/clearfog-cx-s1_8-s2_0-dpc.dts +@@ -69,19 +69,19 @@ + board_info { + ports { + mac@3 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@4 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@5 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@6 { +- link_type = "MAC_LINK_TYPE_FIXED"; ++ link_type = "MAC_LINK_TYPE_PHY"; + }; + + mac@7 { +-- +2.43.0 + diff --git a/recipes-bsp/mc-utils/mc-utils_%.bbappend b/recipes-bsp/mc-utils/mc-utils_%.bbappend index 352d24c..fbde6d9 100644 --- a/recipes-bsp/mc-utils/mc-utils_%.bbappend +++ b/recipes-bsp/mc-utils/mc-utils_%.bbappend @@ -4,4 +4,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" # Add SolidRun patches SRC_URI += "file://0001-add-solidrun-lx2160-cex7-based-clearfog-cx-dpl-dpc.patch \ file://0002-add-solidrun-lx2160-cex6-based-evaluation-board-dpl-.patch \ + file://0003-add-configuration-for-lx2162a-som-and-clearfog-board.patch \ + file://0004-lx2162-som-clearfog-enable-dpni-connections.patch \ + file://0005-lx2160acex7-clearfog-cx-configure-qsfp-ports-type-ph.patch \ " diff --git a/recipes-bsp/rcw/files/0014-lx2162aqds-re-enable-dpmac11.patch b/recipes-bsp/rcw/files/0014-lx2162aqds-re-enable-dpmac11.patch new file mode 100644 index 0000000..a7d81ae --- /dev/null +++ b/recipes-bsp/rcw/files/0014-lx2162aqds-re-enable-dpmac11.patch @@ -0,0 +1,27 @@ +From 40ea49cde613dad5f63d157f40180ebe4f07f7f9 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 27 May 2023 17:20:22 +0300 +Subject: [PATCH 14/15] lx2162aqds: re-enable dpmac11 + +dpmac11 was unintentionally disabled along with dpmac7-10. +Fix the initializer value of DEVDISR2 to only disable dpmac7-10. + +Signed-off-by: Josua Mayer +--- + lx2162aqds/disable_mac7_10.rcw | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lx2162aqds/disable_mac7_10.rcw b/lx2162aqds/disable_mac7_10.rcw +index ef3edba..d52589c 100644 +--- a/lx2162aqds/disable_mac7_10.rcw ++++ b/lx2162aqds/disable_mac7_10.rcw +@@ -11,5 +11,5 @@ + */ + + .pbi +-write 0x1e00074,0x00007c0 ++write 0x1e00074,0x00003c0 + .end +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch b/recipes-bsp/rcw/files/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch new file mode 100644 index 0000000..83c6cae --- /dev/null +++ b/recipes-bsp/rcw/files/0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch @@ -0,0 +1,532 @@ +From 8aa66ef6694c03231f6432f0d62e40dffa88d3e4 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 27 Oct 2024 18:26:26 +0100 +Subject: [PATCH] add configuration for lx2162a som and clearfog evaluation + board + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/SD1_0.rcwi | 17 +++ + lx2160acex7/include/SD2_0.rcwi | 17 +++ + lx2160acex7/include/SD3_0.rcwi | 20 +++ + lx2160acex7/include/pll_2000_650_xxxx.rcwi | 15 ++ + lx2162asom_rev2/Makefile | 1 + + lx2162asom_rev2/README | 0 + .../rcw_2000_650_2900_18_11_0_auto.rcw | 22 +++ + .../rcw_2000_650_2900_18_7_0_auto.rcw | 22 +++ + .../rcw_2000_650_2900_18_9_0_auto.rcw | 19 +++ + lx2162asom_rev2/include/SD1_18.rcwi | 18 +++ + lx2162asom_rev2/include/SD2_11.rcwi | 25 ++++ + lx2162asom_rev2/include/SD2_7.rcwi | 25 ++++ + lx2162asom_rev2/include/SD2_9.rcwi | 22 +++ + lx2162asom_rev2/include/common.rcwi | 128 ++++++++++++++++++ + lx2162asom_rev2/include/common_pbi.rcwi | 51 +++++++ + 15 files changed, 402 insertions(+) + create mode 100644 lx2160acex7/include/SD1_0.rcwi + create mode 100644 lx2160acex7/include/SD2_0.rcwi + create mode 100644 lx2160acex7/include/SD3_0.rcwi + create mode 100644 lx2160acex7/include/pll_2000_650_xxxx.rcwi + create mode 100644 lx2162asom_rev2/Makefile + create mode 100644 lx2162asom_rev2/README + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw + create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw + create mode 100644 lx2162asom_rev2/include/SD1_18.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_11.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_7.rcwi + create mode 100644 lx2162asom_rev2/include/SD2_9.rcwi + create mode 100644 lx2162asom_rev2/include/common.rcwi + create mode 100644 lx2162asom_rev2/include/common_pbi.rcwi + +diff --git a/lx2160acex7/include/SD1_0.rcwi b/lx2160acex7/include/SD1_0.rcwi +new file mode 100644 +index 0000000..718a441 +--- /dev/null ++++ b/lx2160acex7/include/SD1_0.rcwi +@@ -0,0 +1,17 @@ ++/* Serdes 1 Protocol 0: Disabled */ ++SRDS_PRTCL_S1=0 ++ ++/* Disable Serdes 1 PLLF */ ++SRDS_PLL_PD_PLL1=1 ++ ++/* Disable Serdes 1 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S2=1 ++ ++/* Don't use Serdes 1 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S1=0 ++ ++/* Disable Serdes 1 PLLS */ ++SRDS_PLL_PD_PLL2=1 ++ ++/* Select Serdes 1 PLL Default Fequencies (don't care) */ ++SRDS_PLL_REF_CLK_SEL_S1=0 +diff --git a/lx2160acex7/include/SD2_0.rcwi b/lx2160acex7/include/SD2_0.rcwi +new file mode 100644 +index 0000000..6af65a3 +--- /dev/null ++++ b/lx2160acex7/include/SD2_0.rcwi +@@ -0,0 +1,17 @@ ++/* Serdes 2 Protocol 0: Disabled */ ++SRDS_PRTCL_S2=0 ++ ++/* Disable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=1 ++ ++/* Disable Serdes 2 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S2=1 ++ ++/* Don't use Serdes 2 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* Disable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=1 ++ ++/* Select Serdes 2 PLL Default Fequencies (don't care) */ ++SRDS_PLL_REF_CLK_SEL_S2=0 +diff --git a/lx2160acex7/include/SD3_0.rcwi b/lx2160acex7/include/SD3_0.rcwi +new file mode 100644 +index 0000000..250437c +--- /dev/null ++++ b/lx2160acex7/include/SD3_0.rcwi +@@ -0,0 +1,20 @@ ++/* Serdes 3 Protocol 0: Disabled */ ++SRDS_PRTCL_S3=0 ++ ++/* Disable Serdes 3 PLLF */ ++SRDS_PLL_PD_PLL5=1 ++ ++/* Disable Serdes 3 PLLF reference clock */ ++SRDS_REFCLKF_DIS_S3=1 ++ ++/* Don't use Serdes 3 PLLF as reference for PLLS */ ++SRDS_INTRA_REF_CLK_S3=0 ++ ++/* Disable Serdes 3 PLLS */ ++SRDS_PLL_PD_PLL6=1 ++ ++/* ++ * Select Serdes 3 PLL Default Fequencies (don't care) ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937) ++ */ ++SRDS_PLL_REF_CLK_SEL_S3=0 +diff --git a/lx2160acex7/include/pll_2000_650_xxxx.rcwi b/lx2160acex7/include/pll_2000_650_xxxx.rcwi +new file mode 100644 +index 0000000..0bc7e8b +--- /dev/null ++++ b/lx2160acex7/include/pll_2000_650_xxxx.rcwi +@@ -0,0 +1,15 @@ ++/* ++ * Core and Platform Clocks: ++ * - Platform: 650MHz ++ * - Core: 2000MHz ++ */ ++ ++/* platform clock is system clock mul 13 div 2 = 650 */ ++SYS_PLL_RAT=13 ++ ++/* core clocks are 2000 */ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++/* same as all nxp 2000_650_* */ ++CGB_PLL2_RAT=8 +diff --git a/lx2162asom_rev2/Makefile b/lx2162asom_rev2/Makefile +new file mode 100644 +index 0000000..f77e46b +--- /dev/null ++++ b/lx2162asom_rev2/Makefile +@@ -0,0 +1 @@ ++include ../Makefile.inc +diff --git a/lx2162asom_rev2/README b/lx2162asom_rev2/README +new file mode 100644 +index 0000000..e69de29 +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw +new file mode 100644 +index 0000000..cc1b0e5 +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 11 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#define HAVE_PEX3 ++#define HAVE_PEX4 ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_11.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw +new file mode 100644 +index 0000000..475abbb +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw +@@ -0,0 +1,22 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 7 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#define HAVE_PEX3 ++#define HAVE_PEX4 ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_7.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw +new file mode 100644 +index 0000000..4425597 +--- /dev/null ++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw +@@ -0,0 +1,19 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 9 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 650 MHz ++ * DDR -- 2900 MT/s ++ * ++ */ ++ ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2162asom_rev2/include/common.rcwi> ++#include <../lx2162asom_rev2/include/SD1_18.rcwi> ++#include <../lx2162asom_rev2/include/SD2_9.rcwi> ++#include <../lx2160acex7/include/SD3_0.rcwi> ++#include <../lx2162asom_rev2/include/common_pbi.rcwi> +diff --git a/lx2162asom_rev2/include/SD1_18.rcwi b/lx2162asom_rev2/include/SD1_18.rcwi +new file mode 100644 +index 0000000..34c5be3 +--- /dev/null ++++ b/lx2162asom_rev2/include/SD1_18.rcwi +@@ -0,0 +1,18 @@ ++/* Serdes 1 Protocol 18: 2x10Gbps + 2x25Gbps */ ++SRDS_PRTCL_S1=18 ++ ++/* Enable Serdes 1 PLLF */ ++SRDS_PLL_PD_PLL1=0 ++ ++/* Enable Serdes 1 PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */ ++SRDS_INTRA_REF_CLK_S1=1 ++ ++/* ++ * Select Serdes 1 PLLF frequency 161.1328125MHz for 25GE mode (lanes 2+3): Bit 0 = 0 ++ * Select Serdes 1 PLLS frequency 161.1328125MHz for 10GE mode (not documented in RM): Bit 1 = 1 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 +diff --git a/lx2162asom_rev2/include/SD2_11.rcwi b/lx2162asom_rev2/include/SD2_11.rcwi +new file mode 100644 +index 0000000..9434b7b +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_11.rcwi +@@ -0,0 +1,25 @@ ++/* Serdes 2 Protocol 11: 6x1Gbps & 2x PCI-e x1 Gen 3 */ ++SRDS_PRTCL_S2=11 ++ ++/* Enable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */ ++SRDS_INTRA_REF_CLK_S2=1 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz for PCI: Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Support up to PCI-e Gen 3 */ ++SRDS_DIV_PEX_S2=1 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/SD2_7.rcwi b/lx2162asom_rev2/include/SD2_7.rcwi +new file mode 100644 +index 0000000..eb25a86 +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_7.rcwi +@@ -0,0 +1,25 @@ ++/* Serdes 2 Protocol 7: 2x10Gbps 4x1Gbps & 2x PCI-e x1 Gen 2 */ ++SRDS_PRTCL_S2=7 ++ ++/* Enable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=0 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Don't use Serdes 2 PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S2=0 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz for 1G (and pcie): Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 156.25MHz for 10G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Support up to PCI-e Gen 2 */ ++SRDS_DIV_PEX_S2=2 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/SD2_9.rcwi b/lx2162asom_rev2/include/SD2_9.rcwi +new file mode 100644 +index 0000000..68728ba +--- /dev/null ++++ b/lx2162asom_rev2/include/SD2_9.rcwi +@@ -0,0 +1,22 @@ ++/* Serdes 2 Protocol 9: 8x1Gbps */ ++SRDS_PRTCL_S2=9 ++ ++/* Disable Serdes 2 PLLF */ ++SRDS_PLL_PD_PLL3=1 ++ ++/* Enable Serdes 2 PLLS */ ++SRDS_PLL_PD_PLL4=0 ++ ++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */ ++SRDS_INTRA_REF_CLK_S2=1 ++ ++/* ++ * Select Serdes 2 PLLF frequency 100MHz (don't care): Bit 0 = 0 ++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0 ++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935) ++ */ ++SRDS_PLL_REF_CLK_SEL_S2=0 ++ ++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */ ++EC1_PMUX=1 ++EC2_PMUX=1 +diff --git a/lx2162asom_rev2/include/common.rcwi b/lx2162asom_rev2/include/common.rcwi +new file mode 100644 +index 0000000..35a6db6 +--- /dev/null ++++ b/lx2162asom_rev2/include/common.rcwi +@@ -0,0 +1,128 @@ ++/* ++ * LX2162A SoM Common Configuration ++ */ ++ ++/* C[5:8]_PLL are CG[5:8] div 1 */ ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */ ++HWA_CGA_M1_CLK_SEL=1 ++/* Cluster group B clock is PLL2 div 2 (for DCE) */ ++HWA_CGB_M1_CLK_SEL=6 ++/* ++ * fall-back boot-mode when DCFG boot location pointer registers are null ++ * - 0b10101 (21): OCRAM ++ * - 0b11010 (26): XSPI ++ */ ++BOOT_LOC=21 ++/* SYSCLK is 100MHz */ ++SYSCLK_FREQ=600 ++/* USB-3.0 clock is 100MHz */ ++USB3_CLK_FSEL=39 ++ ++/* IIC1 is I2C */ ++IIC1_PMUX=0 ++/* IIC2 is SD Card-Detect */ ++IIC2_PMUX=6 ++/* IIC3 is I2C */ ++IIC3_PMUX=0 ++/* IIC4 is I2C (unused) */ ++IIC4_PMUX=0 ++/* IIC5 is I2C */ ++IIC5_PMUX=0 ++/* IIC6 is I2C (unused) */ ++IIC6_PMUX=0 ++/* ++ * SDHC1 CMD/CLK/VBUS/DAT[0:3] are SDHC ++ * SPI3_PCS0 is VSEL ++ */ ++SDHC1_BASE_PMUX=0 ++/* SDHC1_DS is GPIO (unused) */ ++SDHC1_DS_PMUX=1 ++/* SDHC1_CMD/DAT0/DAT1_DIR (SPI3_PCS[1:3]) are GPIO1[14:12] */ ++SDHC1_DIR_PMUX=1 ++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */ ++USB_EXT_PMUX=1 ++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */ ++XSPI1_A_BASE_PMUX=0 ++/* XSPI1_A_DATA[3:0] are SPI */ ++XSPI1_A_DATA30_PMUX=0 ++/* XSPI1_A_DATA[7:4] are SPI */ ++XSPI1_A_DATA74_PMUX=0 ++/* ASLEEP is ASLEEP (unused) */ ++ASLEEP_PMUX=0 ++/* EVT[2:0] are GPIO3[14:12] */ ++EVT20_PMUX=1 ++/* EVT[4:3] are GPIO3[16:15] */ ++EVT43_PMUX=1 ++/* CLK_OUT is GPIO (unused) */ ++CLK_OUT_PMUX=1 ++/* IRQ[3:0] are GPIO3[3:0] */ ++IRQ03_00_PMUX=1 ++/* IRQ[7:4] are GPIO3[7:4] */ ++IRQ07_04_PMUX=1 ++/* IRQ[11:8] are GPIO3[11:8] */ ++IRQ11_08_PMUX=1 ++/* EC1_* are RGMII */ ++EC1_PMUX=0 ++/* EC2_* are PTP */ ++EC2_PMUX=2 ++/* EC_GTX_CLK125 is PTP */ ++GTX_CLK_PMUX=0 ++/* UART1_SOUT/SIN are UART1 */ ++UART1_SOUTSIN_PMUX=0 ++/* UART1_RTS/CTS_B are GPIO (unused) */ ++UART1_RTSCTS_PMUX=1 ++/* UART2_SOUT/SIN are UART2 */ ++UART2_SOUTSIN_PMUX=0 ++/* UART2_RTS/CTS_B are GPIO (unused) */ ++UART2_RTSCTS_PMUX=1 ++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */ ++SDHC2_BASE_PMUX=0 ++/* SDHC2_DAT[7:4] are SDHC */ ++SDHC2_DAT74_PMUX=0 ++ ++ ++/* configure IIC1, IIC3, IIC5, IIC6 pins for i2c */ ++IIC1_PMUX=0 ++IIC3_PMUX=0 ++IIC5_PMUX=0 ++IIC6_PMUX=0 ++ ++/* ++ * Configure GPIOs: ++ * EVT0_B: GPIO3_DAT12 ++ * EVT1_B: GPIO3_DAT13 (SFP 25 upper LED) ++ * EVT2_B: GPIO3_DAT14 (SFP 25 lower LED) ++ * EVT3_B: GPIO3_DAT15 (SFP 25 lower MODABS) ++ * EVT4_B: GPIO3_DAT16 (SFP 10 upper MODABS) ++ * PROC_IRQ0: GPIO3_DAT00 ++ * PROC_IRQ1: GPIO3_DAT01 (SFP 10 lower MODABS) ++ * PROC_IRQ2: GPIO3_DAT02 ++ * PROC_IRQ3: GPIO3_DAT03 ++ * PROC_IRQ4: GPIO3_DAT04 ++ * PROC_IRQ5: GPIO3_DAT05 (SFP 10 upper LED) ++ * PROC_IRQ6: GPIO3_DAT06 ++ * PROC_IRQ7: GPIO3_DAT07 ++ * PROC_IRQ8: GPIO3_DAT08 ++ * PROC_IRQ9: GPIO3_DAT09 ++ * PROC_IRQ10: GPIO3_DAT10 (SFP 25 upper MODABS) ++ * PROC_IRQ11: GPIO3_DAT11 (SFP 10 lower LED) ++ */ ++EVT20_PMUX=1 ++EVT43_PMUX=1 ++IRQ03_00_PMUX=1 ++IRQ07_04_PMUX=1 ++IRQ11_08_PMUX=1 ++ ++/* Configure USB1 Pins for USB */ ++USB_EXT_PMUX=0 ++ ++ ++/* ++ * Original SolidRun Settings in LSDK-21.08 ++ * ++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock ++ */ +diff --git a/lx2162asom_rev2/include/common_pbi.rcwi b/lx2162asom_rev2/include/common_pbi.rcwi +new file mode 100644 +index 0000000..05f19fc +--- /dev/null ++++ b/lx2162asom_rev2/include/common_pbi.rcwi +@@ -0,0 +1,51 @@ ++/* ++ * LX2162A SoM Common Configuration ++ */ ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* PCIe Errata A-009531, A-008851 */ ++#ifdef HAVE_PEX1 ++#include <../lx2160asi/a009531_PEX1.rcw> ++#include <../lx2160asi/a008851_PEX1.rcw> ++#endif ++#ifdef HAVE_PEX3 ++#include <../lx2160asi/a009531_PEX3.rcw> ++#include <../lx2160asi/a008851_PEX3.rcw> ++#endif ++#ifdef HAVE_PEX4 ++#include <../lx2160asi/a009531_PEX4.rcw> ++#include <../lx2160asi/a008851_PEX4.rcw> ++#endif ++ ++/* SerDes Errata A-050479 */ ++#include <../lx2160asi/a050479.rcw> ++ ++/* PEX2/5/6 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_pci2_5_6.rcw> ++ ++/* USB2 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_usb2.rcw> ++ ++/* MAC7 to MAC10 clock disable (not available on LX2162) */ ++#include <../lx2162aqds/disable_mac7_10.rcw> ++ ++/* DDR2 clock disable*/ ++#include <../lx2162aqds/disable_ddr2.rcw> ++ ++/* Errata A-050426 */ ++#include <../lx2160asi/a050426.rcw> ++ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ ++#if defined(LX_BOOTSOURCE_SDHC) ++#include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#else ++#include <../lx2160asi/bootlocptr_auto.rcw> ++#endif ++ +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch b/recipes-bsp/rcw/files/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch new file mode 100644 index 0000000..fb6688f --- /dev/null +++ b/recipes-bsp/rcw/files/0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch @@ -0,0 +1,2000 @@ +From c9c51751856fabca518d364ef344f5e1470f6669 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 16:01:27 +0100 +Subject: [PATCH] lx2160acex7: clearfog-cx: add configuration for serdes 1 + protocol 18 + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + lx2160acex7/include/SD1_18.rcwi | 24 ++++++++++++++++++ + lx2160acex7/include/SD1_8.rcwi | 4 +-- + .../rcw_2000_700_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2400_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2600_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2900_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_3200_18_5_2_xspi.rcw | 25 +++++++++++++++++++ + 62 files changed, 1486 insertions(+), 2 deletions(-) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7/include/SD1_18.rcwi + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..9e95ac8 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..470237f +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..a13d207 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..ff8a674 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..8d73b20 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..c6595d2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..3c2f588 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4671e9a +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..91e4908 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..978d3a6 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..1d1a869 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..3f96225 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..732ca38 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..de60fca +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..1b44c27 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..f69abb1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..09c62dc +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..f1c0c96 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2b75335 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..7839ab2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..901b323 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..951a9eb +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4d6aec0 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..eb909ee +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..b430f80 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..c935b09 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..b1f39b4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..d0736c2 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..6410353 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..daa99df +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/include/SD1_18.rcwi b/lx2160acex7/include/SD1_18.rcwi +new file mode 100644 +index 0000000..cf67395 +--- /dev/null ++++ b/lx2160acex7/include/SD1_18.rcwi +@@ -0,0 +1,24 @@ ++/* ++ * Serdes 1 Reference Clocks: ++ * - PLLF = 161.1328125MHz ++ * - PLLS = 100MHz ++ */ ++ ++/* Serdes 1 Protocol 18: 6x10Gbps + 2x25Gbps */ ++SRDS_PRTCL_S1=18 ++ ++/* Enable PLLF */ ++SRDS_PLL_PD_PLL1=0 ++ ++/* Use PLLF for PLLS */ ++SRDS_INTRA_REF_CLK_S1=1 ++ ++/* Enable PLLS */ ++SRDS_PLL_PD_PLL2=0 ++ ++/* ++ * Select PLLF frequency 161.1328125MH for 25G mode: Bit 0 = 0 ++ * Select PLLS frequency 161.1328125MHz for 10G mode: Bit 1 = 1 ++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933) ++ */ ++SRDS_PLL_REF_CLK_SEL_S1=2 +diff --git a/lx2160acex7/include/SD1_8.rcwi b/lx2160acex7/include/SD1_8.rcwi +index 87ce260..1646de8 100644 +--- a/lx2160acex7/include/SD1_8.rcwi ++++ b/lx2160acex7/include/SD1_8.rcwi +@@ -1,7 +1,7 @@ + /* + * Serdes 1 Reference Clocks: +- * - PLLF = 100MHz +- * - PLLS = 161.1328125MHz ++ * - PLLF = 161.1328125MHz ++ * - PLLS = 100MHz + */ + + /* Serdes 1 Protocol 8: 8x10Gbps */ +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..6f454ad +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..a3bc9c9 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..144f54b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2a11587 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..bb3437e +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..90eacf6 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..af17640 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..4dd1b96 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..d9c8671 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..2a23f78 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..cf44444 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..f93ef7f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..0067b24 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..290ebb1 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..e9e5e99 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +new file mode 100644 +index 0000000..02b2961 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..1fa9e1f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..12f62c1 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +new file mode 100644 +index 0000000..f951e53 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..227510c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..4a30d7f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +new file mode 100644 +index 0000000..86b272d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..03d233f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..8321f14 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +new file mode 100644 +index 0000000..4444769 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..fc1ad2d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..311d2df +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +new file mode 100644 +index 0000000..3665618 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +new file mode 100644 +index 0000000..49b4d42 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +new file mode 100644 +index 0000000..bdfe337 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 18 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_18.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.43.0 + diff --git a/recipes-bsp/rcw/rcw_git.bbappend b/recipes-bsp/rcw/rcw_git.bbappend index f654584..0368225 100644 --- a/recipes-bsp/rcw/rcw_git.bbappend +++ b/recipes-bsp/rcw/rcw_git.bbappend @@ -15,8 +15,11 @@ SRC_URI += "file://0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.pat file://0011-lx2160acex7-enable-A-050426-workaround-for-silicon-o.patch \ file://0012-lx2160acex6-enable-pci-errata-workarounds-for-all-ac.patch \ file://0013-lx2160acex6-add-configuration-for-2.2GHz-binned-soc.patch \ + file://0014-lx2162aqds-re-enable-dpmac11.patch \ + file://0015-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch \ + file://0016-lx2160acex7-clearfog-cx-add-configuration-for-serdes.patch \ " -BOARD_TARGETS:lx2160acex6-rev2 = "lx2160acex6_rev2" -BOARD_TARGETS:lx2160acex7 = "lx2160acex7 lx2160acex7_rev2" -BOARD_TARGETS:lx2160acex7-rev2 = "lx2160acex7 lx2160acex7_rev2" +BOARD_TARGETS:lx2160a-cex6 = "lx2160acex6_rev2" +BOARD_TARGETS:lx2160a-cex7 = "lx2160acex7 lx2160acex7_rev2" +BOARD_TARGETS:lx2162a-som = "lx2162asom_rev2" diff --git a/recipes-bsp/u-boot/2022.04-solidrun/lx2160acex7-honeycomb-fdtfile.cfg b/recipes-bsp/u-boot/2022.04-solidrun/lx2160acex7-honeycomb-fdtfile.cfg new file mode 100644 index 0000000..d7f96ae --- /dev/null +++ b/recipes-bsp/u-boot/2022.04-solidrun/lx2160acex7-honeycomb-fdtfile.cfg @@ -0,0 +1 @@ +CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-honeycomb.dtb" diff --git a/recipes-bsp/u-boot/2022.04-solidrun/lx2162asom-clearfog-fdtfile.cfg b/recipes-bsp/u-boot/2022.04-solidrun/lx2162asom-clearfog-fdtfile.cfg new file mode 100644 index 0000000..b370d50 --- /dev/null +++ b/recipes-bsp/u-boot/2022.04-solidrun/lx2162asom-clearfog-fdtfile.cfg @@ -0,0 +1 @@ +CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2162a-clearfog.dtb" diff --git a/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend b/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend index 2575a7d..ad85ecc 100644 --- a/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend +++ b/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend @@ -11,7 +11,10 @@ SRC_URI += "file://0001-add-solidrun-lx2160-cex7-board-support.patch \ " # Override default fdtfile for boards without dedicated uboot config -SRC_URI:append:lx2160acex6-rev2 = " file://lx2160acex6-evb-fdtfile.cfg" +SRC_URI:append:lx2160a-rev2-cex6-evb = " file://lx2160acex6-evb-fdtfile.cfg" +SRC_URI:append:lx2160a-honeycomb = " file://lx2160acex7-honeycomb-fdtfile.cfg" +SRC_URI:append:lx2160a-rev2-honeycomb = " file://lx2160acex7-honeycomb-fdtfile.cfg" +SRC_URI:append:lx2162a-rev2-clearfog = " file://lx2162asom-clearfog-fdtfile.cfg" # do_configure step requires merge_config.sh in the path, provided by kern-tools-native package. # While poky/meta/recipes-bsp/u-boot/u-boot-configure.inc lists this dependency, it is missing a space and does not take effect. diff --git a/recipes-dpaa2/management-complex/management-complex_10.37.0.bb b/recipes-dpaa2/management-complex/management-complex_10.37.0.bb new file mode 100644 index 0000000..c683654 --- /dev/null +++ b/recipes-dpaa2/management-complex/management-complex_10.37.0.bb @@ -0,0 +1,41 @@ +SUMMARY = "DPAA2 Management Complex Firmware" +LICENSE = "NXP-Binary-EULA" +LIC_FILES_CHKSUM = "file://LICENSE;md5=481d6288552113961a835bbabceb0c33" + +inherit deploy + +INHIBIT_DEFAULT_DEPS = "1" + +SRC_URI = "git://github.com/nxp/qoriq-mc-binary;protocol=https;nobranch=1" +SRCREV = "bb19f586b87b97878b4bd0d3e57da2ca40c5c69f" + +S = "${WORKDIR}/git" + +REGLEX:ls2088a = "ls2088a" +REGLEX:ls2080a = "ls2080a" +REGLEX:ls1088a = "ls1088a" +REGLEX:lx2160a = "lx216xa" +REGLEX:lx2162a = "lx216xa" + +do_install () { + install -d ${D}/boot + install -m 755 ${S}/${REGLEX}/*.itb ${D}/boot +} + +do_deploy () { + install -d ${DEPLOYDIR}/mc_app + install -m 755 ${S}/${REGLEX}/*.itb ${DEPLOYDIR}/mc_app + # make a symlink to the latest binary + for mc_binary in `find ${DEPLOYDIR}/mc_app -type f -printf "%f\n" |sort`;do + ln -sfT ${mc_binary} ${DEPLOYDIR}/mc_app/mc.itb + done +} +addtask deploy before do_build after do_install + +PACKAGES += "${PN}-image" +FILES:${PN}-image += "/boot" + +INHIBIT_PACKAGE_STRIP = "1" + +COMPATIBLE_MACHINE = "(qoriq-arm64)" +PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/recipes-kernel/linux/5.15-solidrun/0011-arm64-dts-lx2160a-describe-the-SerDes-block-2.patch b/recipes-kernel/linux/5.15-solidrun/0011-arm64-dts-lx2160a-describe-the-SerDes-block-2.patch new file mode 100644 index 0000000..58523b3 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0011-arm64-dts-lx2160a-describe-the-SerDes-block-2.patch @@ -0,0 +1,44 @@ +From a545f3d8edbada16407853e8c4f2f735c85132f4 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 1 Oct 2023 12:32:56 +0200 +Subject: [PATCH 11/15] arm64: dts: lx2160a: describe the SerDes block #2 + +Add description for the LX2160A second SerDes block. +It is functionally identical to the first one already added in +commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes +block #1"). + +The SerDes driver currently updates the registers of all 8 lanes by +default during probe. Because currently this driver only supports +configuration of network protocols, this can lead to problems with +certain configurations. +Set status property to "disabled" by default so that existing boards are +not impacted. + +Signed-off-by: Josua Mayer +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +index 2db9d95b2b9c..46dc12115bfc 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +@@ -619,6 +619,13 @@ serdes_1: phy@1ea0000 { + #phy-cells = <1>; + }; + ++ serdes_2: phy@1eb0000 { ++ compatible = "fsl,lynx-28g"; ++ reg = <0x0 0x1eb0000 0x0 0x1e30>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0012-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch b/recipes-kernel/linux/5.15-solidrun/0012-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch new file mode 100644 index 0000000..e9e7aca --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0012-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch @@ -0,0 +1,522 @@ +From 2ccd70bcf2f44415f2f1571a21ee5fb5b841d384 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 1 Oct 2023 12:32:59 +0200 +Subject: [PATCH 12/15] arm64: dts: freescale: Add support for LX2162 SoM & + Clearfog Board + +Add support for the SolidRun LX2162A System on Module (SoM), and the +Clearfog evaluation board. + +The SoM has few software-controllable features: +- AR8035 Ethernet PHY +- eMMC +- SPI Flash +- fan controller +- various eeproms + +The Clearfog evaluation board provides: +- microSD connector +- USB-A +- 2x 10Gbps SFP+ +- 2x 25Gbps SFP+ with a retimer +- 8x 2.5Gbps RJ45 +- 2x mPCI (assembly option / disables 2xRJ45) + +The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580 +supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps. + +However 2500 speed is untested due to documentation and drivier +limitations. To avoid confusion the phy nodes have been explicitly +limited to 1000 for now. + +The PCI nodes are disabled, but explicitly added to mark that this board +can have pci. +It is expected that the bootloader will patch the status property +"okay" and disable 2x RJ45 ports, according to active serdes configuration. + +Signed-off-by: Josua Mayer +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/Makefile | 1 + + .../dts/freescale/fsl-lx2162a-clearfog.dts | 376 ++++++++++++++++++ + .../dts/freescale/fsl-lx2162a-sr-som.dtsi | 73 ++++ + 3 files changed, 450 insertions(+) + create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts + create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index 810ba23bf1b2..b544e2d0daa4 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb ++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb + + fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +new file mode 100644 +index 000000000000..9f88583aa25e +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +@@ -0,0 +1,376 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++// ++// Device Tree file for LX2162A Clearfog ++// ++// Copyright 2023 Josua Mayer ++ ++/dts-v1/; ++ ++#include "fsl-lx2160a.dtsi" ++#include "fsl-lx2162a-sr-som.dtsi" ++ ++/ { ++ model = "SolidRun LX2162A Clearfog"; ++ compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; ++ ++ aliases { ++ crypto = &crypto; ++ i2c0 = &i2c0; ++ i2c1 = &i2c2; ++ i2c2 = &i2c4; ++ i2c3 = &sfp_i2c0; ++ i2c4 = &sfp_i2c1; ++ i2c5 = &sfp_i2c2; ++ i2c6 = &sfp_i2c3; ++ i2c7 = &mpcie1_i2c; ++ i2c8 = &mpcie0_i2c; ++ i2c9 = &pcieclk_i2c; ++ mmc0 = &esdhc0; ++ mmc1 = &esdhc1; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_sfp_at: led-sfp-at { ++ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ ++ default-state = "off"; ++ }; ++ ++ led_sfp_ab: led-sfp-ab { ++ gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ ++ default-state = "off"; ++ }; ++ ++ led_sfp_bt: led-sfp-bt { ++ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ ++ default-state = "off"; ++ }; ++ ++ led_sfp_bb: led-sfp-bb { ++ gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ ++ default-state = "off"; ++ }; ++ }; ++ ++ sfp_at: sfp-at { ++ compatible = "sff,sfp"; ++ i2c-bus = <&sfp_i2c0>; ++ mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */ ++ maximum-power-milliwatt = <2000>; ++ }; ++ ++ sfp_ab: sfp-ab { ++ compatible = "sff,sfp"; ++ i2c-bus = <&sfp_i2c1>; ++ mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */ ++ maximum-power-milliwatt = <2000>; ++ }; ++ ++ sfp_bt: sfp-bt { ++ compatible = "sff,sfp"; ++ i2c-bus = <&sfp_i2c2>; ++ mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */ ++ maximum-power-milliwatt = <2000>; ++ }; ++ ++ sfp_bb: sfp-bb { ++ compatible = "sff,sfp"; ++ i2c-bus = <&sfp_i2c3>; ++ mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */ ++ maximum-power-milliwatt = <2000>; ++ }; ++}; ++ ++&dpmac3 { ++ sfp = <&sfp_at>; ++ managed = "in-band-status"; ++ phys = <&serdes_1 7>; ++}; ++ ++&dpmac4 { ++ sfp = <&sfp_ab>; ++ managed = "in-band-status"; ++ phys = <&serdes_1 6>; ++}; ++ ++&dpmac5 { ++ sfp = <&sfp_bt>; ++ managed = "in-band-status"; ++ phys = <&serdes_1 5>; ++}; ++ ++&dpmac6 { ++ sfp = <&sfp_bb>; ++ managed = "in-band-status"; ++ phys = <&serdes_1 4>; ++}; ++ ++&dpmac11 { ++ phys = <&serdes_2 0>; ++ phy-handle = <ðernet_phy3>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac12 { ++ phys = <&serdes_2 1>; ++ phy-handle = <ðernet_phy1>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac13 { ++ phys = <&serdes_2 6>; ++ phy-handle = <ðernet_phy6>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac14 { ++ phys = <&serdes_2 7>; ++ phy-handle = <ðernet_phy8>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac15 { ++ phys = <&serdes_2 4>; ++ phy-handle = <ðernet_phy4>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac16 { ++ phys = <&serdes_2 5>; ++ phy-handle = <ðernet_phy2>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac17 { ++ /* override connection to on-SoM phy */ ++ /delete-property/ phy-handle; ++ /delete-property/ phy-connection-type; ++ ++ phys = <&serdes_2 2>; ++ phy-handle = <ðernet_phy5>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&dpmac18 { ++ phys = <&serdes_2 3>; ++ phy-handle = <ðernet_phy7>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&emdio1 { ++ ethernet_phy1: ethernet-phy@8 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <8>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy2: ethernet-phy@9 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <9>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy3: ethernet-phy@10 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <10>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy4: ethernet-phy@11 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <11>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy5: ethernet-phy@12 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <12>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy6: ethernet-phy@13 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <13>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy7: ethernet-phy@14 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <14>; ++ max-speed = <1000>; ++ }; ++ ++ ethernet_phy8: ethernet-phy@15 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <15>; ++ max-speed = <1000>; ++ }; ++}; ++ ++&esdhc0 { ++ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ sd-uhs-sdr25; ++ sd-uhs-sdr12; ++ status = "okay"; ++}; ++ ++ðernet_phy0 { ++ /* ++ * SoM has a phy at address 1 connected to SoC Ethernet Controller 1. ++ * It competes for WRIOP MAC17, and no connector has been wired. ++ */ ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ /* retimer@18 */ ++ ++ i2c-mux@70 { ++ compatible = "nxp,pca9546"; ++ reg = <0x70>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c-mux-idle-disconnect; ++ ++ sfp_i2c0: i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ sfp_i2c1: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ sfp_i2c2: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ sfp_i2c3: i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ }; ++ ++ i2c-mux@71 { ++ compatible = "nxp,pca9546"; ++ reg = <0x71>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c-mux-idle-disconnect; ++ ++ mpcie1_i2c: i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ mpcie0_i2c: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ pcieclk_i2c: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ /* clock-controller@6b */ ++ }; ++ }; ++}; ++ ++&pcie3 { ++ status = "disabled"; ++}; ++ ++&pcie4 { ++ status = "disabled"; ++}; ++ ++&pcs_mdio3 { ++ status = "okay"; ++}; ++ ++&pcs_mdio4 { ++ status = "okay"; ++}; ++ ++&pcs_mdio5 { ++ status = "okay"; ++}; ++ ++&pcs_mdio6 { ++ status = "okay"; ++}; ++ ++&pcs_mdio11 { ++ status = "okay"; ++}; ++ ++&pcs_mdio12 { ++ status = "okay"; ++}; ++ ++&pcs_mdio13 { ++ status = "okay"; ++}; ++ ++&pcs_mdio14 { ++ status = "okay"; ++}; ++ ++&pcs_mdio15 { ++ status = "okay"; ++}; ++ ++&pcs_mdio16 { ++ status = "okay"; ++}; ++ ++&pcs_mdio17 { ++ status = "okay"; ++}; ++ ++&pcs_mdio18 { ++ status = "okay"; ++}; ++ ++&serdes_1 { ++ status = "okay"; ++}; ++ ++&serdes_2 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&usb0 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +new file mode 100644 +index 000000000000..0580ea30cfbc +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +@@ -0,0 +1,73 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++// ++// Device Tree file for LX2162A-SOM ++// ++// Copyright 2021 Rabeeh Khoury ++// Copyright 2023 Josua Mayer ++ ++&crypto { ++ status = "okay"; ++}; ++ ++&dpmac17 { ++ phy-handle = <ðernet_phy0>; ++ phy-connection-type = "rgmii-id"; ++}; ++ ++&emdio1 { ++ status = "okay"; ++ ++ ethernet_phy0: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&esdhc1 { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ status = "okay"; ++}; ++ ++&fspi { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ m25p,fast-read; ++ spi-max-frequency = <50000000>; ++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ ++ spi-rx-bus-width = <8>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ fan-controller@18 { ++ compatible = "ti,amc6821"; ++ reg = <0x18>; ++ }; ++ ++ ddr_spd: eeprom@51 { ++ compatible = "st,24c02", "atmel,24c02"; ++ reg = <0x51>; ++ read-only; ++ }; ++ ++ config_eeprom: eeprom@57 { ++ compatible = "st,24c02", "atmel,24c02"; ++ reg = <0x57>; ++ }; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ ++ variable_eeprom: eeprom@54 { ++ compatible = "st,24c2048", "atmel,24c2048"; ++ reg = <0x54>; ++ }; ++}; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0013-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch b/recipes-kernel/linux/5.15-solidrun/0013-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch new file mode 100644 index 0000000..af59949 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0013-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch @@ -0,0 +1,34 @@ +From 7b39c2662471603555dce8e7acdf7c2ec968907a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 12 Mar 2024 20:56:54 +0100 +Subject: [PATCH 13/15] arm64: dts: fsl-lx2162a-som: add description for rtc + +SolidRun LX2162A SoM has an RTC on bus IIC6 (dts i2c5). +Enable this bus and add description for the rtc. + +Signed-off-by: Josua Mayer +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +index 0580ea30cfbc..e914291e63a1 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +@@ -71,3 +71,12 @@ variable_eeprom: eeprom@54 { + reg = <0x54>; + }; + }; ++ ++&i2c5 { ++ status = "okay"; ++ ++ rtc@6f { ++ compatible = "microchip,mcp7940x"; ++ reg = <0x6f>; ++ }; ++}; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0014-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch b/recipes-kernel/linux/5.15-solidrun/0014-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch new file mode 100644 index 0000000..d3e8014 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0014-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch @@ -0,0 +1,32 @@ +From eb6f770c0b1774289cc75cbf8b142d8d23cebfd7 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 12 Mar 2024 20:56:55 +0100 +Subject: [PATCH 14/15] arm64: dts: fsl-lx2162a-clearfog: add alias for i2c bus + iic6 + +SoM dts has enabled i2c bus IIC6 (dts i2c5), but defines no aliases. + +LX2162A Clearfog dts has aliases for all i2c buses to ensure predictable +numbering for userspace. Add an additional alias for this extra bus. + +Signed-off-by: Josua Mayer +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +index 9f88583aa25e..eafef8718a0f 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +@@ -25,6 +25,7 @@ aliases { + i2c7 = &mpcie1_i2c; + i2c8 = &mpcie0_i2c; + i2c9 = &pcieclk_i2c; ++ i2c10 = &i2c5; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0015-arm64-dts-lx2162a-sr-som-enable-optee-os.patch b/recipes-kernel/linux/5.15-solidrun/0015-arm64-dts-lx2162a-sr-som-enable-optee-os.patch new file mode 100644 index 0000000..4974edd --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0015-arm64-dts-lx2162a-sr-som-enable-optee-os.patch @@ -0,0 +1,41 @@ +From 61a2a998be708c6c865154f6308f1577fcf5d4ec Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 28 Oct 2024 17:09:55 +0100 +Subject: [PATCH 15/15] arm64: dts: lx2162a-sr-som: enable optee-os + +Signed-off-by: Josua Mayer +--- + .../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +index e914291e63a1..fffdc517b583 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +@@ -5,6 +5,23 @@ + // Copyright 2021 Rabeeh Khoury + // Copyright 2023 Josua Mayer + ++/ { ++ firmware { ++ /* ++ * This is counter-intuitive: ++ * ++ * U-Boot by default patches OS DTB adding /firmware/optee, ++ * and updates /reserved-memory/optee. ++ * ++ * When OS DTB already has /firmware/optee node however, ++ * U-Boot does nothing. ++ * ++ * Enable optee by deleting the /firmware/optee node. ++ */ ++ /delete-node/ optee; ++ }; ++}; ++ + &crypto { + status = "okay"; + }; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0016-phy-lynx-28g-configure-more-equalization-params-for-.patch b/recipes-kernel/linux/5.15-solidrun/0016-phy-lynx-28g-configure-more-equalization-params-for-.patch new file mode 100644 index 0000000..04d4487 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0016-phy-lynx-28g-configure-more-equalization-params-for-.patch @@ -0,0 +1,31 @@ +From 407de483856e9f24b857589992869debc547e50b Mon Sep 17 00:00:00 2001 +From: Ioana Ciornei +Date: Wed, 5 Apr 2023 16:32:49 +0300 +Subject: [PATCH 16/18] phy: lynx-28g: configure more equalization params for + 10GBASER + +We discovered that not all the equalization parameters for a lane were +configured upon an interface change. Configure the extra 2 registers +with the appropriate values for 10GBASE-R. + +Signed-off-by: Ioana Ciornei +--- + drivers/phy/freescale/phy-fsl-lynx-28g.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c +index 85574f808eb9..a84192555b1a 100644 +--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c ++++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c +@@ -326,6 +326,8 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) + iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); + iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id)); + iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); ++ iowrite32(0x80000000, priv->base + LYNX_28G_LNaRCCR0(lane->id)); ++ iowrite32(0x00408000, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); + } + + static int lynx_28g_power_off(struct phy *phy) +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0017-phy-lynx-28g-add-support-for-25GBASER.patch b/recipes-kernel/linux/5.15-solidrun/0017-phy-lynx-28g-add-support-for-25GBASER.patch new file mode 100644 index 0000000..ca85661 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0017-phy-lynx-28g-add-support-for-25GBASER.patch @@ -0,0 +1,231 @@ +From 7d62d489eaa5073602836bb4a0b02aaea21f3a8f Mon Sep 17 00:00:00 2001 +From: Ioana Ciornei +Date: Wed, 5 Apr 2023 16:33:54 +0300 +Subject: [PATCH 17/18] phy: lynx-28g: add support for 25GBASER + +Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver. +This mainly means being able to determine if a PLL is able to support +the new interface type, to determine at probe time if a lane is +configured from RCW with this interface and to be able to reconfigure a +lane. + +Signed-off-by: Ioana Ciornei +--- + drivers/phy/freescale/phy-fsl-lynx-28g.c | 93 ++++++++++++++++++++++-- + 1 file changed, 87 insertions(+), 6 deletions(-) + +diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c +index a84192555b1a..e7a9a6499fd0 100644 +--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c ++++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c +@@ -22,7 +22,12 @@ + #define LYNX_28G_PCCC_USXGMII 0x1 + #define LYNX_28G_PCCC_SXGMII_DIS 0x0 + ++#define LYNX_28G_PCCD 0x10b4 ++#define LYNX_28G_PCCD_25GBASER 0x1 ++#define LYNX_28G_PCCD_25GBASER_DIS 0x0 ++ + #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) ++#define LYNX_28G_LNa_PCCD_OFFSET(lane) (4 * (lane->id)) + + /* Per PLL registers */ + #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) +@@ -42,6 +47,7 @@ + #define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0 + #define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000 + #define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000 ++#define LYNX_28G_PLLnCR1_FRATE_12G_25GVCO 0x16000000 + + /* Per SerDes lane registers */ + /* Lane a General Control Register */ +@@ -49,9 +55,11 @@ + #define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3) + #define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8 + #define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50 ++#define LYNX_28G_LNaGCR0_PROTO_SEL_25G 0xD0 + #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0) + #define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0 + #define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2 ++#define LYNX_28G_LNaGCR0_IF_WIDTH_40_BIT 0x4 + + /* Lane a Tx Reset Control Register */ + #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) +@@ -67,6 +75,7 @@ + #define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0 + #define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000 + #define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000 ++#define LYNX_28G_LNaTGCR0_N_RATE_DOUBLE 0x3000000 + #define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24) + + #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) +@@ -87,6 +96,7 @@ + #define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0 + #define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000 + #define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000 ++#define LYNX_28G_LNaRGCR0_N_RATE_DOUBLE 0x3000000 + #define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24) + + #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) +@@ -95,12 +105,17 @@ + #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) + #define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58) + ++#define LYNX_28G_LNaRCCR0(lane) (0x800 + (lane) * 0x100 + 0x68) ++ + #define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) + ++#define LYNX_28G_LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80) ++ + #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) + #define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24) + #define LYNX_28G_LNaPSS_TYPE_SGMII 0x4 + #define LYNX_28G_LNaPSS_TYPE_XFI 0x28 ++#define LYNX_28G_LNaPSS_TYPE_25G 0x68 + + #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) + #define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11) +@@ -216,6 +231,16 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane, + break; + } + break; ++ case LYNX_28G_PLLnCR1_FRATE_12G_25GVCO: ++ switch (intf) { ++ case PHY_INTERFACE_MODE_25GBASER: ++ lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_DOUBLE, N_RATE_MSK); ++ lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_DOUBLE, N_RATE_MSK); ++ break; ++ default: ++ break; ++ } ++ break; + default: + break; + } +@@ -235,21 +260,35 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane, + + static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane) + { +- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); + struct lynx_28g_priv *priv = lane->priv; ++ u32 lane_offset; + +- /* Cleanup the protocol configuration registers of the current protocol */ + switch (lane->interface) { + case PHY_INTERFACE_MODE_10GBASER: ++ /* Cleanup the protocol configuration registers */ ++ lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); + lynx_28g_rmw(priv, LYNX_28G_PCCC, + LYNX_28G_PCCC_SXGMII_DIS << lane_offset, + GENMASK(3, 0) << lane_offset); + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: ++ /* Cleanup the protocol configuration registers */ ++ lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); + lynx_28g_rmw(priv, LYNX_28G_PCC8, + LYNX_28G_PCC8_SGMII_DIS << lane_offset, + GENMASK(3, 0) << lane_offset); ++ ++ /* Disable the SGMII PCS */ ++ lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); ++ ++ break; ++ case PHY_INTERFACE_MODE_25GBASER: ++ /* Cleanup the protocol configuration registers */ ++ lane_offset = LYNX_28G_LNa_PCCD_OFFSET(lane); ++ lynx_28g_rmw(priv, LYNX_28G_PCCD, ++ LYNX_28G_PCCD_25GBASER_DIS << lane_offset, ++ GENMASK(2, 0) << lane_offset); + break; + default: + break; +@@ -316,9 +355,6 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) + /* Choose the portion of clock net to be used on this lane */ + lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER); + +- /* Disable the SGMII PCS */ +- lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); +- + /* Configure the appropriate equalization parameters for the protocol */ + iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id)); + iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); +@@ -330,6 +366,41 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) + iowrite32(0x00408000, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); + } + ++static void lynx_28g_lane_set_25gbaser(struct lynx_28g_lane *lane) ++{ ++ u32 lane_offset = LYNX_28G_LNa_PCCD_OFFSET(lane); ++ struct lynx_28g_priv *priv = lane->priv; ++ struct lynx_28g_pll *pll; ++ ++ lynx_28g_cleanup_lane(lane); ++ ++ /* Enable the E25G lane */ ++ lynx_28g_rmw(priv, LYNX_28G_PCCD, ++ LYNX_28G_PCCD_25GBASER << lane_offset, ++ GENMASK(2, 0) << lane_offset); ++ ++ /* Setup the protocol select and SerDes parallel interface width */ ++ lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_25G, PROTO_SEL_MSK); ++ lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_40_BIT, IF_WIDTH_MSK); ++ ++ /* Switch to the PLL that works with this interface type */ ++ pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_25GBASER); ++ lynx_28g_lane_set_pll(lane, pll); ++ ++ /* Choose the portion of clock net to be used on this lane */ ++ lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_25GBASER); ++ ++ /* Configure the appropriate equalization parameters for 25GBASE-R */ ++ iowrite32(0x20828700, priv->base + LYNX_28G_LNaTECR0(lane->id)); ++ iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); ++ iowrite32(0x00000085, priv->base + LYNX_28G_LNaRECR0(lane->id)); ++ iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); ++ iowrite32(0xa1000023, priv->base + LYNX_28G_LNaRECR2(lane->id)); ++ iowrite32(0x00002020, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); ++ iowrite32(0x8f000000, priv->base + LYNX_28G_LNaRCCR0(lane->id)); ++ iowrite32(0x00008001, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); ++} ++ + static int lynx_28g_power_off(struct phy *phy) + { + struct lynx_28g_lane *lane = phy_get_drvdata(phy); +@@ -408,6 +479,9 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode) + case PHY_INTERFACE_MODE_10GBASER: + lynx_28g_lane_set_10gbaser(lane); + break; ++ case PHY_INTERFACE_MODE_25GBASER: ++ lynx_28g_lane_set_25gbaser(lane); ++ break; + default: + err = -EOPNOTSUPP; + goto out; +@@ -492,8 +566,12 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv) + /* 10.3125GHz clock net */ + __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported); + break; ++ case LYNX_28G_PLLnCR1_FRATE_12G_25GVCO: ++ /* 12.890625GHz clock net */ ++ __set_bit(PHY_INTERFACE_MODE_25GBASER, pll->supported); ++ break; + default: +- /* 6GHz, 12.890625GHz, 8GHz */ ++ /* 6GHz, 8GHz */ + break; + } + } +@@ -542,6 +620,9 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane) + case LYNX_28G_LNaPSS_TYPE_XFI: + lane->interface = PHY_INTERFACE_MODE_10GBASER; + break; ++ case LYNX_28G_LNaPSS_TYPE_25G: ++ lane->interface = PHY_INTERFACE_MODE_25GBASER; ++ break; + default: + lane->interface = PHY_INTERFACE_MODE_NA; + } +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0018-net-dpaa2-mac-add-25gbase-r-support.patch b/recipes-kernel/linux/5.15-solidrun/0018-net-dpaa2-mac-add-25gbase-r-support.patch new file mode 100644 index 0000000..3124898 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0018-net-dpaa2-mac-add-25gbase-r-support.patch @@ -0,0 +1,53 @@ +From 5d3fec396e8bfb535e4efbe120ef8206b4f5124d Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 16 Jun 2023 14:14:14 +0300 +Subject: [PATCH 18/18] net: dpaa2-mac: add 25gbase-r support + +Layerscape MACs support 25Gbps network speed with dpmac "CAUI" mode. +Add the mappings between DPMAC_ETH_IF_* and HY_INTERFACE_MODE_*, as well +as the 25000 mac capability. + +Tested on SolidRun LX2162a Clearfog, serdes 1 protocol 18. + +Signed-off-by: Josua Mayer +Reviewed-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +index ed4cac00fba6..55f08c84b3dc 100644 +--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c ++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +@@ -55,6 +55,9 @@ static int phy_mode(enum dpmac_eth_if eth_if, phy_interface_t *if_mode) + case DPMAC_ETH_IF_XFI: + *if_mode = PHY_INTERFACE_MODE_10GBASER; + break; ++ case DPMAC_ETH_IF_CAUI: ++ *if_mode = PHY_INTERFACE_MODE_25GBASER; ++ break; + default: + return -EINVAL; + } +@@ -80,6 +83,8 @@ static enum dpmac_eth_if dpmac_eth_if_mode(phy_interface_t if_mode) + return DPMAC_ETH_IF_XFI; + case PHY_INTERFACE_MODE_1000BASEX: + return DPMAC_ETH_IF_1000BASEX; ++ case PHY_INTERFACE_MODE_25GBASER: ++ return DPMAC_ETH_IF_CAUI; + default: + return DPMAC_ETH_IF_MII; + } +@@ -411,7 +416,7 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) + + mac->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | + MAC_10FD | MAC_100FD | MAC_1000FD | MAC_2500FD | MAC_5000FD | +- MAC_10000FD; ++ MAC_10000FD | MAC_25000FD; + + dpaa2_mac_set_supported_interfaces(mac); + +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0019-net-phy-marvell10g-add-initial-support-for-88x2580.patch b/recipes-kernel/linux/5.15-solidrun/0019-net-phy-marvell10g-add-initial-support-for-88x2580.patch new file mode 100644 index 0000000..6114bb6 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0019-net-phy-marvell10g-add-initial-support-for-88x2580.patch @@ -0,0 +1,93 @@ +From 6e31ab1d913c7504737876ffec434672ce07a171 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 3 Nov 2022 17:12:18 +0200 +Subject: [PATCH] net: phy: marvell10g: add initial support for 88x2580 + +Signed-off-by: Josua Mayer +--- + drivers/net/phy/marvell10g.c | 35 +++++++++++++++++++++++++++++++++++ + include/linux/marvell_phy.h | 1 + + 2 files changed, 36 insertions(+) + +diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c +index df33637c5269..2b8dc1984f10 100644 +--- a/drivers/net/phy/marvell10g.c ++++ b/drivers/net/phy/marvell10g.c +@@ -942,6 +942,13 @@ static void mv2111_init_supported_interfaces(unsigned long *mask) + __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); + } + ++static void mv2580_init_supported_interfaces(unsigned long *mask) ++{ ++ __set_bit(PHY_INTERFACE_MODE_SGMII, mask); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); ++ __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); ++} ++ + static const struct mv3310_chip mv3310_type = { + .init_supported_interfaces = mv3310_init_supported_interfaces, + .get_mactype = mv3310_get_mactype, +@@ -982,6 +989,16 @@ static const struct mv3310_chip mv2111_type = { + #endif + }; + ++static const struct mv3310_chip mv2580_type = { ++ .init_supported_interfaces = mv2580_init_supported_interfaces, ++ .get_mactype = mv2110_get_mactype, ++ .init_interface = mv2110_init_interface, ++ ++#ifdef CONFIG_HWMON ++ .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, ++#endif ++}; ++ + static int mv3310_get_number_of_ports(struct phy_device *phydev) + { + int ret; +@@ -1192,6 +1209,23 @@ static struct phy_driver mv3310_drivers[] = { + .remove = mv3310_remove, + .set_loopback = genphy_c45_loopback, + }, ++ { ++ .phy_id = MARVELL_PHY_ID_88E2580, ++ .phy_id_mask = MARVELL_PHY_ID_MASK, ++ .name = "mv88e2580", ++ .driver_data = &mv2580_type, ++ .probe = mv3310_probe, ++ .suspend = mv3310_suspend, ++ .resume = mv3310_resume, ++ .config_init = mv3310_config_init, ++ .config_aneg = mv3310_config_aneg, ++ .aneg_done = mv3310_aneg_done, ++ .read_status = mv3310_read_status, ++ .get_tunable = mv3310_get_tunable, ++ .set_tunable = mv3310_set_tunable, ++ .remove = mv3310_remove, ++ .set_loopback = genphy_c45_loopback, ++ }, + }; + + module_phy_driver(mv3310_drivers); +@@ -1199,6 +1233,7 @@ module_phy_driver(mv3310_drivers); + static struct mdio_device_id __maybe_unused mv3310_tbl[] = { + { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, + { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, ++ { MARVELL_PHY_ID_88E2580, MARVELL_PHY_ID_MASK }, + { }, + }; + MODULE_DEVICE_TABLE(mdio, mv3310_tbl); +diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h +index 0f06c2287b52..aa3367fa6f8d 100644 +--- a/include/linux/marvell_phy.h ++++ b/include/linux/marvell_phy.h +@@ -24,6 +24,7 @@ + #define MARVELL_PHY_ID_88E3016 0x01410e60 + #define MARVELL_PHY_ID_88X3310 0x002b09a0 + #define MARVELL_PHY_ID_88E2110 0x002b09b0 ++#define MARVELL_PHY_ID_88E2580 0x002b0bc3 + #define MARVELL_PHY_ID_88X2222 0x01410f10 + + /* Marvel 88E1111 in Finisar SFP module with modified PHY ID */ +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0020-phy-add-of_phy_get_by_index.patch b/recipes-kernel/linux/5.15-solidrun/0020-phy-add-of_phy_get_by_index.patch new file mode 100644 index 0000000..c95d1e5 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0020-phy-add-of_phy_get_by_index.patch @@ -0,0 +1,79 @@ +From 761fde5d51c7c0f26f12a684d479836a9590f9ea Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 23 Nov 2022 13:23:03 +0200 +Subject: [PATCH 20/23] phy: add of_phy_get_by_index + +Support getting a phy by index directly. +This is mostly useful for hardware specifying multiple similar +generic phys using the "phys" and "phy-names" properties. + +Current user is dpaa2 driver that can have a phy object for each serdes +lane, and additionally 2 retimer channels (tx&rx). + +Signed-off-by: Josua Mayer +--- + drivers/phy/phy-core.c | 11 +++++++++-- + include/linux/phy/phy.h | 6 ++++++ + 2 files changed, 15 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c +index 688b204fcf36..a0f6b5cbbaaa 100644 +--- a/drivers/phy/phy-core.c ++++ b/drivers/phy/phy-core.c +@@ -579,12 +579,19 @@ static struct phy *_of_phy_get(struct device_node *np, int index) + */ + struct phy *of_phy_get(struct device_node *np, const char *con_id) + { +- struct phy *phy = NULL; + int index = 0; + + if (con_id) + index = of_property_match_string(np, "phy-names", con_id); + ++ return of_phy_get_by_index(np, index); ++} ++EXPORT_SYMBOL_GPL(of_phy_get); ++ ++struct phy *of_phy_get_by_index(struct device_node *np, int index) ++{ ++ struct phy *phy = NULL; ++ + phy = _of_phy_get(np, index); + if (IS_ERR(phy)) + return phy; +@@ -596,7 +603,7 @@ struct phy *of_phy_get(struct device_node *np, const char *con_id) + + return phy; + } +-EXPORT_SYMBOL_GPL(of_phy_get); ++EXPORT_SYMBOL_GPL(of_phy_get_by_index); + + /** + * of_phy_put() - release the PHY +diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h +index 980a2427cc33..300829b8bc62 100644 +--- a/include/linux/phy/phy.h ++++ b/include/linux/phy/phy.h +@@ -259,6 +259,7 @@ void of_phy_put(struct phy *phy); + void phy_put(struct device *dev, struct phy *phy); + void devm_phy_put(struct device *dev, struct phy *phy); + struct phy *of_phy_get(struct device_node *np, const char *con_id); ++struct phy *of_phy_get_by_index(struct device_node *np, int index); + struct phy *of_phy_simple_xlate(struct device *dev, + struct of_phandle_args *args); + struct phy *phy_create(struct device *dev, struct device_node *node, +@@ -472,6 +473,11 @@ static inline struct phy *of_phy_get(struct device_node *np, const char *con_id) + return ERR_PTR(-ENOSYS); + } + ++static inline struct phy *of_phy_get_by_index(struct device_node *np, int index) ++{ ++ return ERR_PTR(-ENOSYS); ++} ++ + static inline struct phy *of_phy_simple_xlate(struct device *dev, + struct of_phandle_args *args) + { +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0021-net-dpaa2-add-support-for-retimer-phys.patch b/recipes-kernel/linux/5.15-solidrun/0021-net-dpaa2-add-support-for-retimer-phys.patch new file mode 100644 index 0000000..788d516 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0021-net-dpaa2-add-support-for-retimer-phys.patch @@ -0,0 +1,212 @@ +From b6696f279d83e889c92a82bd1d3268d6b101a64e Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 16 Apr 2023 14:32:28 +0300 +Subject: [PATCH 21/23] net: dpaa2: add support for retimer phys + +To support network speeds greater than 10Gbps retimers may be connected +on tx & rx lines between the SoC and external phy. + +Add support for dynamic configuration of retimers modeles as generic phy +ojects, and reconfigure them on interface type change. + +In order to extract multiple different types of phy objects, i.e. serdes +& retimer, the existing code using of_phy_get is replaced by a loop +handling both serdes & retimer phys. + +In the future to support 40G & 100G interface speeds, the number of +supported phys might need to be increased from the current maximum of +one serdes and 2 retimer phys. + +Signed-off-by: Josua Mayer +--- + .../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 108 ++++++++++++++---- + .../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 1 + + 2 files changed, 85 insertions(+), 24 deletions(-) + +diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +index 55f08c84b3dc..3d4c0f9206fb 100644 +--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c ++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +@@ -166,6 +166,7 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode, + struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config); + struct dpmac_link_state *dpmac_state = &mac->state; + int err; ++ int i; + + if (state->an_enabled) + dpmac_state->options |= DPMAC_LINK_OPT_AUTONEG; +@@ -178,18 +179,27 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode, + netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n", + __func__, err); + +- if (!mac->serdes_phy) +- return; ++ if (mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE && mac->serdes_phy) { ++ /* This happens only if we support changing of protocol at runtime */ ++ err = dpmac_set_protocol(mac->mc_io, 0, mac->mc_dev->mc_handle, ++ dpmac_eth_if_mode(state->interface)); ++ if (err) ++ netdev_err(mac->net_dev, "dpmac_set_protocol() = %d\n", err); + +- /* This happens only if we support changing of protocol at runtime */ +- err = dpmac_set_protocol(mac->mc_io, 0, mac->mc_dev->mc_handle, +- dpmac_eth_if_mode(state->interface)); +- if (err) +- netdev_err(mac->net_dev, "dpmac_set_protocol() = %d\n", err); ++ err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface); ++ if (err) ++ netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err); ++ } + +- err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface); +- if (err) +- netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err); ++ /* always configure retimers */ ++ for (i = 0; i < sizeof(mac->retimer_phys)/sizeof(mac->retimer_phys[0]); i++) { ++ if (!mac->retimer_phys[i]) ++ continue; ++ ++ err = phy_set_mode_ext(mac->retimer_phys[i], PHY_MODE_ETHERNET, state->interface); ++ if (err) ++ netdev_err(mac->net_dev, "phy_set_mode_ext() on retimer = %d\n", err); ++ } + } + + static void dpaa2_mac_link_up(struct phylink_config *config, +@@ -345,23 +355,45 @@ static void dpaa2_mac_set_supported_interfaces(struct dpaa2_mac *mac) + + void dpaa2_mac_start(struct dpaa2_mac *mac) + { ++ int i; ++ + if (mac->serdes_phy) + phy_power_on(mac->serdes_phy); ++ ++ for (i = 0; i < sizeof(mac->retimer_phys)/sizeof(mac->retimer_phys[0]); i++) { ++ if (!mac->retimer_phys[i]) ++ continue; ++ ++ phy_power_on(mac->retimer_phys[i]); ++ } + } + + void dpaa2_mac_stop(struct dpaa2_mac *mac) + { ++ int i; ++ + if (mac->serdes_phy) + phy_power_off(mac->serdes_phy); ++ ++ for (i = 0; i < sizeof(mac->retimer_phys)/sizeof(mac->retimer_phys[0]); i++) { ++ if (!mac->retimer_phys[i]) ++ continue; ++ ++ phy_power_off(mac->retimer_phys[i]); ++ } + } + + int dpaa2_mac_connect(struct dpaa2_mac *mac) + { + struct net_device *net_dev = mac->net_dev; + struct fwnode_handle *dpmac_node; +- struct phy *serdes_phy = NULL; ++ struct phy *phy = NULL; + struct phylink *phylink; ++ const char *phy_name; + int err; ++ int phy_count; ++ int retimer_phy_count = 0; ++ int i; + + mac->if_link_type = mac->attr.link_type; + +@@ -376,19 +408,41 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) + return -EINVAL; + mac->if_mode = err; + +- if (mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE && +- !phy_interface_mode_is_rgmii(mac->if_mode) && +- is_of_node(dpmac_node)) { +- serdes_phy = of_phy_get(to_of_node(dpmac_node), NULL); +- +- if (serdes_phy == ERR_PTR(-ENODEV)) +- serdes_phy = NULL; +- else if (IS_ERR(serdes_phy)) +- return PTR_ERR(serdes_phy); +- else +- phy_init(serdes_phy); +- } +- mac->serdes_phy = serdes_phy; ++ /* parse serdes & retimer phys, if any */ ++ phy_count = of_count_phandle_with_args(to_of_node(dpmac_node), "phys", "#phy-cells"); ++ if (phy_count >= 0) { ++ for (i = 0; i < phy_count; i++) { ++ phy = of_phy_get_by_index(to_of_node(dpmac_node), i); ++ if (IS_ERR(phy)) ++ return PTR_ERR(phy); ++ ++ err = of_property_read_string_index(to_of_node(dpmac_node), "phy-names", i, &phy_name); ++ if (err || !strcmp("serdes", phy_name)) { ++ if (phy_interface_mode_is_rgmii(mac->if_mode)) { ++ netdev_err(net_dev, "rgmii ports don't support serdes phys\n"); ++ return -EINVAL; ++ } ++ ++ if (mac->serdes_phy) { ++ netdev_warn(net_dev, "unsupported number of serdes phys\n"); ++ continue; ++ } ++ ++ phy_init(phy); ++ mac->serdes_phy = phy; ++ } else if (!strcmp("retimer", phy_name)) { ++ if (retimer_phy_count >= sizeof(mac->retimer_phys)/sizeof(mac->retimer_phys[0])) { ++ netdev_warn(net_dev, "unsupported number of retimer phys\n"); ++ continue; ++ } ++ ++ phy_init(phy); ++ mac->retimer_phys[retimer_phy_count++] = phy; ++ } else { ++ netdev_warn(net_dev, "unsupported phy \"%s\"\n", phy_name); ++ } ++ } ++ } + + /* The MAC does not have the capability to add RGMII delays so + * error out if the interface mode requests them and there is no PHY +@@ -449,6 +503,8 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) + + void dpaa2_mac_disconnect(struct dpaa2_mac *mac) + { ++ int i; ++ + if (!mac->phylink) + return; + +@@ -458,6 +514,10 @@ void dpaa2_mac_disconnect(struct dpaa2_mac *mac) + phylink_destroy(mac->phylink); + dpaa2_pcs_destroy(mac); + of_phy_put(mac->serdes_phy); ++ for (i = 0; i < sizeof(mac->retimer_phys)/sizeof(mac->retimer_phys[0]); i++) { ++ of_phy_put(mac->retimer_phys[i]); ++ mac->retimer_phys[i] = NULL; ++ } + mac->serdes_phy = NULL; + } + +diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h +index cf94475c5e94..35ab362bdcf6 100644 +--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h ++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h +@@ -30,6 +30,7 @@ struct dpaa2_mac { + + int phy_req_state; + struct phy *serdes_phy; ++ struct phy *retimer_phys[2]; + }; + + bool dpaa2_mac_is_type_fixed(struct fsl_mc_device *dpmac_dev, +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0022-net-phy-create-driver-for-ds250df4x10-retimer.patch b/recipes-kernel/linux/5.15-solidrun/0022-net-phy-create-driver-for-ds250df4x10-retimer.patch new file mode 100644 index 0000000..5663e99 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0022-net-phy-create-driver-for-ds250df4x10-retimer.patch @@ -0,0 +1,424 @@ +From 04b3f07ac09c89adaad35af3dd3025e9ae4b43f3 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 12 Oct 2022 18:46:09 +0300 +Subject: [PATCH 22/23] net: phy: create driver for ds250df4x10 retimer + +Create driver for the TI DS250DF410 and DS250DF810 retimers. +Both variants feature either 4 or 8 channels to be configured +individually from 20.2752 to 25.8Gbps, while also supporting subrates by +dividing either with 2 or 4. + +Configuration is provided to other drivers by implementing a generic phy +with support for set_mode. + +For now only 2 of the standard configurations are supported, to support +10 & 25Gbps ethernet modes: +- PHY_INTERFACE_MODE_10GBASER: 10.3125Gbps +- PHY_INTERFACE_MODE_25GBASER: 25.78125Gbps + +The driver also hardcodes signal conditioning parameters. +Future revisions shall read those from device-tree instead. + +Signed-off-by: Josua Mayer +--- + drivers/phy/ti/Kconfig | 9 + + drivers/phy/ti/Makefile | 1 + + drivers/phy/ti/phy-ti-ds250dfx10.c | 354 +++++++++++++++++++++++++++++ + 3 files changed, 364 insertions(+) + create mode 100644 drivers/phy/ti/phy-ti-ds250dfx10.c + +diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig +index 15a3bcf32308..7117e819cdfd 100644 +--- a/drivers/phy/ti/Kconfig ++++ b/drivers/phy/ti/Kconfig +@@ -84,6 +84,15 @@ config TI_PIPE3 + This driver interacts with the "OMAP Control PHY Driver" to power + on/off the PHY. + ++config PHY_DS250DFX10 ++ tristate "Texas Instruments DS250DFX10 Retimer" ++ depends on OF ++ select GENERIC_PHY ++ help ++ Enable to support runtime configuration of DS250DFX10 retimers. ++ The retimers are modeled as generic PHYs, ++ currently supporting 10 & 25 GBASER link speeds. ++ + config PHY_TUSB1210 + tristate "TI TUSB1210 ULPI PHY module" + depends on USB_ULPI_BUS +diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile +index dcba2571c9bd..718db2aadcdd 100644 +--- a/drivers/phy/ti/Makefile ++++ b/drivers/phy/ti/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o + obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o + obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o + obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o ++obj-$(CONFIG_PHY_DS250DFX10) += phy-ti-ds250dfx10.o + obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o + obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o + obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o +diff --git a/drivers/phy/ti/phy-ti-ds250dfx10.c b/drivers/phy/ti/phy-ti-ds250dfx10.c +new file mode 100644 +index 000000000000..bfbbf35c430c +--- /dev/null ++++ b/drivers/phy/ti/phy-ti-ds250dfx10.c +@@ -0,0 +1,354 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Driver for the TI DS250DF410 Retimer ++ * ++ * Copyright (C) 2022-2023 Josua Mayer ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define DS250DF410_REG_CHAN_CONFIG_ID 0xEF ++#define DS250DF410_MASK_CHAN_CONFIG_ID GENMASK(3, 0) ++#define DS250DF410_REG_VERSION 0xF0 ++#define DS250DF410_REG_DEVICE_ID 0xF1 ++#define DS250DF410_REG_CHAN_VERSION 0xF3 ++#define DS250DF410_MASK_CHAN_VERSION GENMASK(7, 4) ++#define DS250DF410_MASK_SHARE_VERSION GENMASK(3, 0) ++ ++struct ds250dfx10_phy_priv { ++ struct i2c_client *client; ++ uint8_t channel; ++}; ++ ++struct ds250dfx10_priv { ++ struct phy *phy[8]; ++ struct phy_provider *provider; ++}; ++ ++static int ds250dfx10_read_register(struct i2c_client *client, uint8_t address, uint8_t *value, ++ uint8_t mask) ++{ ++ s32 res; ++ ++ res = i2c_smbus_read_byte_data(client, address); ++ if (res < 0) { ++ dev_err(&client->dev, "failed to read register %#04x: %d\n", address, ++ res); ++ return -EIO; ++ } ++ ++ *value = res & mask; ++ return 0; ++} ++ ++static int ds250dfx10_write_register(struct i2c_client *client, uint8_t address, uint8_t value, ++ uint8_t mask) ++{ ++ int ret; ++ uint8_t tmp; ++ s32 res; ++ ++ // combine with current value according to mask ++ if (mask != 0xFF) { ++ ret = ds250dfx10_read_register(client, address, &tmp, ~mask); ++ if (ret) ++ return ret; ++ ++ value = (value & mask) | tmp; ++ } ++ ++ // write new value ++ res = i2c_smbus_write_byte_data(client, address, value); ++ if (res < 0) { ++ dev_err(&client->dev, "failed to write register %#04x=%#04x: %d\n", ++ address, value, res); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static void ds250dfx10_config_10g(struct i2c_client *client, uint8_t channel) ++{ ++ int ret = 0; ++ ++ // enable smbus access to single channel ++ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03); ++ ++ // select channel ++ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF); ++ ++ // reset channel registers ++ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04); ++ ++ // assert cdr ++ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C); ++ ++ // select 10.3125 rate ++ ret |= ds250dfx10_write_register(client, 0x2F, 0x00, 0xF0); ++ ++ // enable pre- and post-fir ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80); ++ ++ // set main cursor magnitude +15 ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F); ++ ++ // set pre cursor magnitude -4 ++ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F); ++ ++ // set post cursor magnitude -4 ++ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F); ++ ++ // deassert cdr ++ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C); ++ ++ if (!ret) ++ dev_info(&client->dev, "configured channel %u for 10G\n", channel); ++} ++ ++static void ds250dfx10_config_25g(struct i2c_client *client, uint8_t channel) ++{ ++ int ret = 0; ++ ++ // enable smbus access to single channel ++ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03); ++ ++ // select channel ++ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF); ++ ++ // reset channel registers ++ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04); ++ ++ // assert cdr ++ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C); ++ ++ // select 25.78125 rate ++ ret |= ds250dfx10_write_register(client, 0x2F, 0x50, 0xF0); ++ ++ // enable pre- and post-fir ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80); ++ ++ // set main cursor magnitude +15 ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F); ++ ++ // set pre cursor magnitude -4 ++ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F); ++ ++ // set post cursor magnitude -4 ++ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40); ++ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F); ++ ++ // deassert cdr ++ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C); ++ ++ if (!ret) ++ dev_info(&client->dev, "configured channel %u for 25G\n", channel); ++} ++ ++static int ds250dfx10_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) ++{ ++ struct ds250dfx10_phy_priv *priv = phy_get_drvdata(phy); ++ ++ if (mode != PHY_MODE_ETHERNET) ++ return -EOPNOTSUPP; ++ ++ switch (submode) { ++ case PHY_INTERFACE_MODE_10GBASER: ++ ds250dfx10_config_10g(priv->client, priv->channel); ++ break; ++ case PHY_INTERFACE_MODE_25GBASER: ++ ds250dfx10_config_25g(priv->client, priv->channel); ++ break; ++ default: ++ dev_err(&priv->client->dev, "unsupported interface submode %i\n", ++ submode); ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static const struct phy_ops ds250dfx10_phy_ops = { ++ .set_mode = ds250dfx10_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static struct phy *ds250dfx10_of_xlate(struct device *dev, struct of_phandle_args *args) ++{ ++ struct ds250dfx10_priv *phy_priv = dev_get_drvdata(dev); ++ int channel; ++ ++ if (args->args_count != 1) { ++ dev_err(phy_priv->provider->dev, "DT did not pass correct no of args\n"); ++ return ERR_PTR(-ENODEV); ++ } ++ ++ channel = args->args[0]; ++ if (WARN_ON(channel >= ARRAY_SIZE(phy_priv->phy)) ++ || !phy_priv->phy[channel]) ++ return ERR_PTR(-ENODEV); ++ ++ return phy_priv->phy[channel]; ++} ++ ++static int ds250dfx10_probe(struct i2c_client *client) ++{ ++ struct ds250dfx10_priv *priv; ++ struct ds250dfx10_phy_priv *phy_priv; ++ struct device_node *child; ++ uint8_t chan_config_id, device_id, version, chan_version, share_version, channels; ++ uint8_t reg; ++ int ret, i; ++ ++ priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ ret = -ENOMEM; ++ goto no_phys; ++ } ++ i2c_set_clientdata(client, priv); ++ ++ /* read device identification */ ++ ret = ds250dfx10_read_register(client, DS250DF410_REG_DEVICE_ID, ®, 0xFF); ++ if (ret) ++ goto no_phys; ++ device_id = reg; ++ ++ /* read device version */ ++ ret = ds250dfx10_read_register(client, DS250DF410_REG_VERSION, ®, 0xFF); ++ if (ret) ++ goto no_phys; ++ version = reg; ++ ++ // report device id ++ dev_info(&client->dev, "device id %#04x version %#04x\n", device_id, version); ++ ++ switch (device_id) { ++ case 0x10: ++ break; ++ default: ++ dev_warn(&client->dev, "unknown device id, expect problems!\n"); ++ } ++ ++ // read channel config id ++ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_CONFIG_ID, ®, ++ DS250DF410_MASK_CHAN_CONFIG_ID); ++ if (ret) ++ goto no_phys; ++ chan_config_id = reg; ++ ++ switch (chan_config_id) { ++ case 0xC: ++ channels = 8; ++ break; ++ case 0xE: ++ channels = 4; ++ break; ++ default: ++ dev_err(&client->dev, "unknown channel configuration id %#03x\n", chan_config_id); ++ ret = -EINVAL; ++ goto no_phys; ++ } ++ dev_info(&client->dev, "%u channels\n", channels); ++ ++ // read channel version ++ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_VERSION, ®, 0xFF); ++ if (ret) ++ goto no_phys; ++ chan_version = (reg & DS250DF410_MASK_CHAN_VERSION) >> 4; ++ share_version = reg & DS250DF410_MASK_SHARE_VERSION; ++ ++ dev_info(&client->dev, "channel version %#03x share version %#03x\n", ++ chan_version, share_version); ++ ++ // create PHY objects for all channels ++ for (i = 0; i < channels; i++) { ++ priv->phy[i] = devm_phy_create(&client->dev, child, &ds250dfx10_phy_ops); ++ if (IS_ERR(priv->phy[i])) { ++ ret = PTR_ERR(priv->phy[i]); ++ priv->phy[i] = NULL; ++ of_node_put(child); ++ goto no_provider; ++ } ++ ++ phy_priv = devm_kzalloc(&client->dev, sizeof(*phy_priv), GFP_KERNEL); ++ if (!phy_priv) { ++ ret = -ENOMEM; ++ goto no_provider; ++ } ++ phy_set_drvdata(priv->phy[i], phy_priv); ++ ++ phy_priv->client = client; ++ phy_priv->channel = i; ++ ++ dev_info(&client->dev, "created phy for channel %u\n", i); ++ } ++ of_node_put(child); ++ ++ // register self as phy provider with generic lookup function ++ priv->provider = devm_of_phy_provider_register(&client->dev, ds250dfx10_of_xlate); ++ ++ return 0; ++ ++ devm_of_phy_provider_unregister(&client->dev, priv->provider); ++no_provider: ++ for (i = 0; i < 8; i++) { ++ if (priv->phy[i]) ++ devm_phy_destroy(&client->dev, priv->phy[i]); ++ } ++no_phys: ++ return ret; ++} ++ ++static int ds250dfx10_remove(struct i2c_client *client) ++{ ++ struct ds250dfx10_priv *priv = i2c_get_clientdata(client); ++ int i; ++ ++ for (i = 0; i < 8; i++) ++ if (priv->phy[i]) ++ devm_phy_destroy(&client->dev, priv->phy[i]); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id ds250dfx10_dt_ids[] = { ++ { .compatible = "ti,ds250df410", }, ++ { .compatible = "ti,ds250df810", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ds250dfx10_dt_ids); ++#endif ++ ++static struct i2c_device_id ds250dfx10_idtable[] = { ++ { "ds250df410", 0 }, ++ { "ds250df810", 1 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(i2c, ds250dfx10_idtable); ++ ++static struct i2c_driver ds250dfx10_driver = { ++ .driver = { ++ .name = "ds250dfx10", ++ .of_match_table = of_match_ptr(ds250dfx10_dt_ids), ++ }, ++ ++ .id_table = ds250dfx10_idtable, ++ .probe_new = ds250dfx10_probe, ++ .remove = ds250dfx10_remove, ++}; ++ ++module_i2c_driver(ds250dfx10_driver); ++ ++MODULE_AUTHOR("Josua Mayer "); ++MODULE_DESCRIPTION("TI DS250DFX10 Retimer Driver"); ++MODULE_LICENSE("GPL"); +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0023-arm64-dts-lx2162-clearfog-add-description-for-retime.patch b/recipes-kernel/linux/5.15-solidrun/0023-arm64-dts-lx2162-clearfog-add-description-for-retime.patch new file mode 100644 index 0000000..6c6d3f1 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0023-arm64-dts-lx2162-clearfog-add-description-for-retime.patch @@ -0,0 +1,52 @@ +From 51928756a380284f232f1ca4d15c1d00ef7d84c7 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 16 Apr 2023 13:24:31 +0300 +Subject: [PATCH 23/23] arm64: dts: lx2162-clearfog: add description for + retimer + +LX2162 Clearfog has a retimer on 2x SFP+ connectors. +Add a node for the retimer and link it to the appropriate mac nodes. + +Signed-off-by: Josua Mayer +--- + .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +index eafef8718a0f..1758e91fdbcf 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +@@ -103,13 +103,15 @@ &dpmac4 { + &dpmac5 { + sfp = <&sfp_bt>; + managed = "in-band-status"; +- phys = <&serdes_1 5>; ++ phys = <&serdes_1 5>, <&retimer 2>, <&retimer 3>; ++ phy-names = "serdes", "retimer", "retimer"; + }; + + &dpmac6 { + sfp = <&sfp_bb>; + managed = "in-band-status"; +- phys = <&serdes_1 4>; ++ phys = <&serdes_1 4>, <&retimer 0>, <&retimer 1>; ++ phy-names = "serdes", "retimer", "retimer"; + }; + + &dpmac11 { +@@ -241,7 +243,11 @@ ðernet_phy0 { + &i2c2 { + status = "okay"; + +- /* retimer@18 */ ++ retimer: retimer@18 { ++ compatible = "ti,ds250df410"; ++ reg = <0x18>; ++ #phy-cells = <1>; ++ }; + + i2c-mux@70 { + compatible = "nxp,pca9546"; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0024-arm64-dts-lx2160a-clearfog-itx-set-fixed-link-for-qs.patch b/recipes-kernel/linux/5.15-solidrun/0024-arm64-dts-lx2160a-clearfog-itx-set-fixed-link-for-qs.patch new file mode 100644 index 0000000..3904761 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0024-arm64-dts-lx2160a-clearfog-itx-set-fixed-link-for-qs.patch @@ -0,0 +1,119 @@ +From 8e334669fa98d99e21f7c17a3d6bbbd48878a2b2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 17:14:25 +0100 +Subject: [PATCH 24/25] arm64: dts: lx2160a-clearfog-itx: set fixed link for + qsfp ports + +As QSFP is not currenly supported in the Linux kernel no attempt is made +to model this detail of Honeycomb and Clearfog-CX boards. + +Vendor bootloader used to set up the ethernet ports which are routed to +qsfp connector as fixed links in MC firmware depending on selected +serdes protocol. +These firmware side fixed links worked on linux side without any +explicit configuration. + +The LX2160A also supports runtime configuration of network protocols on +ethernet ports and serdes lanes using generic phys. This requires +changing the interface type on firmware side to type "PHY". + +The standard SFP ports on Honeycomb / Clearfog-CX already rely on +interface type "PHY" to report link and switch ethernet protocol at +runtime based on SFP module properties. + +When interface type is on firmware side is "PHY", dpaa2 driver +configures ethernet ports based on runtime information such as SFP +modules properties and reported link status, or a dedicated phy on mdio +bus. + +In lack of actual QSFP support set up the affected ethernet ports for +fixed 10Gbps link, and enable their respective pcs nodes. +This ensures that when firmware set interface type "PHY", the port and +serdes lanes are configured properly to allow TX and RX of packets. + +It also simplifies configuration for users by allowing selection of +interface speed (e.g. 10 or 25Gbps with serdes 1 protocol 18) in +device-tree rather than firmware. + +Signed-off-by: Josua Mayer +--- + .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 56 +++++++++++++++++++ + 1 file changed, 56 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +index f43d6a90e162..11a99d4efe93 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +@@ -60,6 +60,46 @@ sfp3: sfp-3 { + }; + }; + ++&dpmac3 { ++ phys = <&serdes_1 7>; ++ phy-connection-type = "10gbase-r"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ }; ++}; ++ ++&dpmac4 { ++ phys = <&serdes_1 6>; ++ phy-connection-type = "10gbase-r"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ }; ++}; ++ ++&dpmac5 { ++ phys = <&serdes_1 5>; ++ phy-connection-type = "10gbase-r"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ }; ++}; ++ ++&dpmac6 { ++ phys = <&serdes_1 4>; ++ phy-connection-type = "10gbase-r"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ }; ++}; ++ + &dpmac7 { + sfp = <&sfp0>; + managed = "in-band-status"; +@@ -104,6 +144,22 @@ &pcie5 { + status = "okay"; + }; + ++&pcs_mdio3 { ++ status = "okay"; ++}; ++ ++&pcs_mdio4 { ++ status = "okay"; ++}; ++ ++&pcs_mdio5 { ++ status = "okay"; ++}; ++ ++&pcs_mdio6 { ++ status = "okay"; ++}; ++ + &pcs_mdio7 { + status = "okay"; + }; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/0025-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch b/recipes-kernel/linux/5.15-solidrun/0025-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch new file mode 100644 index 0000000..5a364d0 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/0025-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch @@ -0,0 +1,83 @@ +From 678cee596a136c8dd9d91ce62ae9702cb3da82b1 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Thu, 31 Oct 2024 15:46:16 +0100 +Subject: [PATCH 25/25] arm64: dts: lx2160a-clearfog-cx: add description for + retimers + +SolidRun Clearfog-CX (unlike Honeycomb) has QSFP connector driven by +retimers to support long copper wires. + +Add descriptions for both retimers and link them to the relevant +ethernet interfaces. + +Retimers were added with board revision 1.3, earlier baords can use the +honeycomb dts. + +Signed-off-by: Josua Mayer +--- + .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 +- + .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 38 +++++++++++++++++++ + 2 files changed, 39 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +index 024a119bcb7a..503e346f4d86 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +@@ -155,7 +155,7 @@ regulator@5c { + }; + }; + +- i2c@3 { ++ i2c_smb: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +index 86a9b771428d..60151fccd198 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +@@ -13,3 +13,41 @@ / { + compatible = "solidrun,clearfog-cx", + "solidrun,lx2160a-cex7", "fsl,lx2160a"; + }; ++ ++&dpmac3 { ++ phys = <&serdes_1 7>, <&retimer0 3>, <&retimer1 3>; ++ phy-names = "serdes", "retimer", "retimer"; ++}; ++ ++&dpmac4 { ++ phys = <&serdes_1 6>, <&retimer0 2>, <&retimer1 2>; ++ phy-names = "serdes", "retimer", "retimer"; ++}; ++ ++&dpmac5 { ++ phys = <&serdes_1 5>, <&retimer0 1>, <&retimer1 1>; ++ phy-names = "serdes", "retimer", "retimer"; ++}; ++ ++&dpmac6 { ++ phys = <&serdes_1 4>, <&retimer0 0>, <&retimer1 0>; ++ phy-names = "serdes", "retimer", "retimer"; ++}; ++ ++&i2c_smb { ++ status = "okay"; ++ ++ /* tx direction */ ++ retimer0: retimer@22 { ++ compatible = "ti,ds250df410"; ++ reg = <0x22>; ++ #phy-cells = <1>; ++ }; ++ ++ /* rx direction */ ++ retimer1: retimer@23 { ++ compatible = "ti,ds250df410"; ++ reg = <0x23>; ++ #phy-cells = <1>; ++ }; ++}; +-- +2.43.0 + diff --git a/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.cfg b/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.cfg new file mode 100644 index 0000000..189cab3 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.cfg @@ -0,0 +1 @@ +CONFIG_PHY_DS250DFX10=y diff --git a/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.scc b/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.scc new file mode 100644 index 0000000..1adaab6 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/lx2160acex7-clearfog-cx-drivers.scc @@ -0,0 +1,4 @@ +define KFEATURE_DESCRIPTION "Enable Drivers for SolidRun LX2160A CEX7 Clearfog-CX Board" +define KFEATURE_COMPATIBILITY board + +kconf hardware lx2160acex7-clearfog-cx-drivers.cfg diff --git a/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.cfg b/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.cfg new file mode 100644 index 0000000..a114540 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.cfg @@ -0,0 +1,2 @@ +CONFIG_MARVELL_10G_PHY=y +CONFIG_PHY_DS250DFX10=y diff --git a/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.scc b/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.scc new file mode 100644 index 0000000..a07c707 --- /dev/null +++ b/recipes-kernel/linux/5.15-solidrun/lx2162asom-clearfog-drivers.scc @@ -0,0 +1,4 @@ +define KFEATURE_DESCRIPTION "Enable Drivers for SolidRun LX2162A SoM Clearfog Board" +define KFEATURE_COMPATIBILITY board + +kconf hardware lx2162asom-clearfog-drivers.cfg diff --git a/recipes-kernel/linux/linux-qoriq_5.15.bbappend b/recipes-kernel/linux/linux-qoriq_5.15.bbappend index 41ef3b4..615053d 100644 --- a/recipes-kernel/linux/linux-qoriq_5.15.bbappend +++ b/recipes-kernel/linux/linux-qoriq_5.15.bbappend @@ -12,12 +12,35 @@ SRC_URI += "file://0001-arm64-dts-lx2160a-cex7-add-gpio-hog-for-fan-controll.pat file://0008-arm64-dts-lx2160a-cex6-evb-update-spi-bus-descriptio.patch \ file://0009-arm64-dts-lx2160a-cex6-enable-optee-os.patch \ file://0010-arm64-dts-lx2160a-cex7-enable-optee-os.patch \ + file://0011-arm64-dts-lx2160a-describe-the-SerDes-block-2.patch \ + file://0012-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch \ + file://0013-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch \ + file://0014-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch \ + file://0015-arm64-dts-lx2162a-sr-som-enable-optee-os.patch \ + file://0016-phy-lynx-28g-configure-more-equalization-params-for-.patch \ + file://0017-phy-lynx-28g-add-support-for-25GBASER.patch \ + file://0018-net-dpaa2-mac-add-25gbase-r-support.patch \ + file://0019-net-phy-marvell10g-add-initial-support-for-88x2580.patch \ + file://0020-phy-add-of_phy_get_by_index.patch \ + file://0021-net-dpaa2-add-support-for-retimer-phys.patch \ + file://0022-net-phy-create-driver-for-ds250df4x10-retimer.patch \ + file://0023-arm64-dts-lx2162-clearfog-add-description-for-retime.patch \ + file://0024-arm64-dts-lx2160a-clearfog-itx-set-fixed-link-for-qs.patch \ + file://0025-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch \ " # Enable non-default kernel configs SRC_URI:append = " file://amdgpu.scc" SRC_URI:append = " file://lx2160acex6-drivers.scc" +SRC_URI:append = " file://lx2160acex7-clearfog-cx-drivers.scc" +SRC_URI:append = " file://lx2162asom-clearfog-drivers.scc" # linux-qoriq_5.15.bb does not support scc style fragments, add to DELTA_KERNEL_DEFCONFIG instead. -SRC_URI:append = " file://amdgpu.cfg file://lx2160acex6-drivers.cfg" -DELTA_KERNEL_DEFCONFIG:append = " amdgpu.cfg lx2160acex6-drivers.cfg " +SRC_URI:append = " file://amdgpu.cfg" +SRC_URI:append = " file://lx2160acex6-drivers.cfg" +SRC_URI:append = " file://lx2160acex7-clearfog-cx-drivers.cfg" +SRC_URI:append = " file://lx2162asom-clearfog-drivers.cfg" +DELTA_KERNEL_DEFCONFIG:append = " amdgpu.cfg " +DELTA_KERNEL_DEFCONFIG:append = " lx2160acex6-drivers.cfg " +DELTA_KERNEL_DEFCONFIG:append = " lx2160acex7-clearfog-cx-drivers.cfg " +DELTA_KERNEL_DEFCONFIG:append = " lx2162asom-clearfog-drivers.cfg " diff --git a/recipes-security/optee/optee-os-qoriq_%.bbappend b/recipes-security/optee/optee-os-qoriq_%.bbappend index e99a26b..60ec4de 100644 --- a/recipes-security/optee/optee-os-qoriq_%.bbappend +++ b/recipes-security/optee/optee-os-qoriq_%.bbappend @@ -1,3 +1,3 @@ -PLATFORM_FLAVOR:lx2160acex6-rev2 = "lx2160ardb" -PLATFORM_FLAVOR:lx2160acex7 = "lx2160ardb" -PLATFORM_FLAVOR:lx2160acex7-rev2 = "lx2160ardb" +PLATFORM_FLAVOR:lx2160a-cex6 = "lx2160ardb" +PLATFORM_FLAVOR:lx2160a-cex7 = "lx2160ardb" +PLATFORM_FLAVOR:lx2162a-som = "lx2160ardb"