diff --git a/Documentation/cpu-freq/governors.txt b/Documentation/cpu-freq/governors.txt index c15aa75f52275b..0cf9a6bff6a548 100644 --- a/Documentation/cpu-freq/governors.txt +++ b/Documentation/cpu-freq/governors.txt @@ -28,6 +28,7 @@ Contents: 2.3 Userspace 2.4 Ondemand 2.5 Conservative +2.6 Interactive 3. The Governor Interface in the CPUfreq Core @@ -218,6 +219,91 @@ a decision on when to decrease the frequency while running in any speed. Load for frequency increase is still evaluated every sampling rate. +2.6 Interactive +--------------- + +The CPUfreq governor "interactive" is designed for latency-sensitive, +interactive workloads. This governor sets the CPU speed depending on +usage, similar to "ondemand" and "conservative" governors, but with a +different set of configurable behaviors. + +The tunable values for this governor are: + +above_hispeed_delay: When speed is at or above hispeed_freq, wait for +this long before raising speed in response to continued high load. +The format is a single delay value, optionally followed by pairs of +CPU speeds and the delay to use at or above those speeds. Colons can +be used between the speeds and associated delays for readability. For +example: + + 80000 1300000:200000 1500000:40000 + +uses delay 80000 uS until CPU speed 1.3 GHz, at which speed delay +200000 uS is used until speed 1.5 GHz, at which speed (and above) +delay 40000 uS is used. If speeds are specified these must appear in +ascending order. Default is 20000 uS. + +boost: If non-zero, immediately boost speed of all CPUs to at least +hispeed_freq until zero is written to this attribute. If zero, allow +CPU speeds to drop below hispeed_freq according to load as usual. +Default is zero. + +boostpulse: On each write, immediately boost speed of all CPUs to +hispeed_freq for at least the period of time specified by +boostpulse_duration, after which speeds are allowed to drop below +hispeed_freq according to load as usual. Its a write-only file. + +boostpulse_duration: Length of time to hold CPU speed at hispeed_freq +on a write to boostpulse, before allowing speed to drop according to +load as usual. Default is 80000 uS. + +go_hispeed_load: The CPU load at which to ramp to hispeed_freq. +Default is 99%. + +hispeed_freq: An intermediate "high speed" at which to initially ramp +when CPU load hits the value specified in go_hispeed_load. If load +stays high for the amount of time specified in above_hispeed_delay, +then speed may be bumped higher. Default is the maximum speed allowed +by the policy at governor initialization time. + +io_is_busy: If set, the governor accounts IO time as CPU busy time. + +min_sample_time: The minimum amount of time to spend at the current +frequency before ramping down. Default is 80000 uS. + +target_loads: CPU load values used to adjust speed to influence the +current CPU load toward that value. In general, the lower the target +load, the more often the governor will raise CPU speeds to bring load +below the target. The format is a single target load, optionally +followed by pairs of CPU speeds and CPU loads to target at or above +those speeds. Colons can be used between the speeds and associated +target loads for readability. For example: + + 85 1000000:90 1700000:99 + +targets CPU load 85% below speed 1GHz, 90% at or above 1GHz, until +1.7GHz and above, at which load 99% is targeted. If speeds are +specified these must appear in ascending order. Higher target load +values are typically specified for higher speeds, that is, target load +values also usually appear in an ascending order. The default is +target load 90% for all speeds. + +timer_rate: Sample rate for reevaluating CPU load when the CPU is not +idle. A deferrable timer is used, such that the CPU will not be woken +from idle to service this timer until something else needs to run. +(The maximum time to allow deferring this timer when not running at +minimum speed is configurable via timer_slack.) Default is 20000 uS. + +timer_slack: Maximum additional time to defer handling the governor +sampling timer beyond timer_rate when running at speeds above the +minimum. For platforms that consume additional power at idle when +CPUs are running at speeds greater than minimum, this places an upper +bound on how long the timer will be deferred prior to re-evaluating +load and dropping speed. For example, if timer_rate is 20000uS and +timer_slack is 10000uS then timers will be deferred for up to 30msec +when not at lowest speed. A value of -1 means defer timers +indefinitely at all speeds. Default is 80000 uS. + 3. The Governor Interface in the CPUfreq Core ============================================= diff --git a/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt b/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt new file mode 100644 index 00000000000000..cb3e96775284b7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt @@ -0,0 +1,23 @@ +ION Memory Manager (ION) + +ION is a memory manager that allows for sharing of buffers between different +processes and between user space and kernel space. ION manages different +memory spaces by separating the memory spaces into "heaps". + +Required properties for Ion + +- compatible: "fsl,mxc-ion" + + +All child nodes of a fsl,mxc-ion node are interpreted as Ion heap +configurations. + +Required properties for Ion heaps + +- fsl,heap-id: The ID of the ION heap. + +Example: + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt index 6949e50f1f1696..120792d1366913 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt @@ -10,7 +10,7 @@ Required properties: Example: dcp@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; + compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <52 53>; status = "okay"; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index adeca34c5a33b4..f6e6fba9140bd2 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -395,6 +395,15 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: Definition: LP register offset. default it is 0x34. + - clocks + Usage: optional + Value type: + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. + EXAMPLE sec_mon_rtc_lp@1 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt index 96ec5179c8a001..99e4b1a0e25642 100644 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ b/Documentation/devicetree/bindings/display/mxsfb.txt @@ -7,6 +7,12 @@ Required properties: - interrupts: Should contain lcdif interrupts - display : phandle to display node (see below for details) +Optional properties: +- disp-dev: Display device driver name +- disp-videomode: Display device video mode name; this is used if the panel + supports multiple video modes, in order to chose the right one (see below for + examples) + * display node Required properties: @@ -47,3 +53,46 @@ lcdif@80030000 { }; }; }; + +Examples - optional properties: + +Snippet from imx7d-sdb-mipi-dsi.dts: + +&lcdif { + disp-dev = "mipi_dsi_samsung"; + disp-videomode = "TRUULY-WVGA-SYNC-LOW"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +In the above example, the panel supports 2 video modes (snippet from +drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c): + +#define ACTIVE_HIGH_NAME "TRUULY-WVGA-SYNC-HIGH" +#define ACTIVE_LOW_NAME "TRUULY-WVGA-SYNC-LOW" + +static struct fb_videomode truly_lcd_modedb[] = { + { + ACTIVE_HIGH_NAME, 50, 480, 854, 41042, + 40, 60, + 3, 3, + 8, 4, + 0x0, + FB_VMODE_NONINTERLACED, + 0, + }, { + ACTIVE_LOW_NAME, 50, 480, 854, 41042, + 40, 60, + 3, 3, + 8, 4, + FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, + 0, + }, +}; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 191d7bd8a6fefd..fc4eb68f50f2df 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -9,6 +9,7 @@ group, DMAMUX0 or DMAMUX1, but not both. Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC + - "nxp,imx7ulp-edma" for eDMA used similar to that on NXP i.MX7ULP SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 3c9a57a8443b25..ccc6c0873f6309 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -50,6 +50,7 @@ The full ID of peripheral types can be found below. 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI + 25 HDMI Audio The third cell specifies the transfer priority as below. diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt index af0b903de293a0..dfc14f71e81fb3 100644 --- a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt +++ b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt @@ -5,7 +5,10 @@ connected to a GPIO pin. Required properties: - compatible: Should be "linux,extcon-usb-gpio" + +Either one of id-gpio or vbus-gpio must be present. Both can be present as well. - id-gpio: gpio for USB ID pin. See gpio binding. +- vbus-gpio: gpio for USB VBUS pin. Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below: extcon_usb1 { diff --git a/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt b/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt new file mode 100644 index 00000000000000..b8d27ef108fe38 --- /dev/null +++ b/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt @@ -0,0 +1,105 @@ +* FSL IPUv3 Display/FB + +The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics +subsystem in an application processor. The goal of the IPU is to provide +comprehensive support for the flow of data from an image sensor or/and to a +display device. + +Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC. +Each IPU unit has two display interfaces. + +Required properties for IPU: +- bypass_reset :Bypass reset to avoid display channel being. + stopped by probe since it may start to work in bootloader: 0 or 1. +- compatible : should be "fsl,imx6q-ipu". +- reg : the register address range. +- interrupts : the error and sync interrupts request. +- clocks : the clock sources that it depends on. +- clock-names: the related clock names. +- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in + Documentation/devicetree/bindings/reset/ for details. + +Required properties for fb: +- compatible : should be "fsl,mxc_sdc_fb". +- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi". +- mode_str : "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel, + "1920x1080M@60" for hdmi. +- default_bpp : default bits per pixel: 8/16/24/32 +- int_clk : use internal clock as pixel clock: 0 or 1 +- late_init : to avoid display channel being re-initialized + as we've probably setup the channel in bootloader: 0 or 1 +- interface_pix_fmt : display interface pixel format as below: + RGB666 IPU_PIX_FMT_RGB666 + RGB565 IPU_PIX_FMT_RGB565 + RGB24 IPU_PIX_FMT_RGB24 + BGR24 IPU_PIX_FMT_BGR24 + GBR24 IPU_PIX_FMT_GBR24 + YUV444 IPU_PIX_FMT_YUV444 + YUYV IPU_PIX_FMT_YUYV + UYVY IPU_PIX_FMT_UYVY + YVYV IPU_PIX_FMT_YVYU + VYUY IPU_PIX_FMT_VYUY + +Required properties for display: +- compatible : should be "fsl,lcd" for lcd panel +- reg : the register address range if necessary to have. +- interrupts : the error and sync interrupts if necessary to have. +- clocks : the clock sources that it depends on if necessary to have. +- clock-names: the related clock names if necessary to have. +- ipu_id : ipu id for the first display device: 0 or 1 +- disp_id : display interface id for the first display interface: 0 or 1 +- default_ifmt : save as above display interface pixel format for lcd +- pinctrl-names : should be "default" +- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the + IPU connected. +- gpr : the mux controller for the display engine's display interfaces and the display encoder + (only valid for mipi dsi now). +- disp-power-on-supply : the regulator to control display panel's power. + (only valid for mipi dsi now). +- resets : the gpio pin to reset the display device(only valid for mipi display panel now). +- lcd_panel : the video mode name for the display device(only valid for mipi display panel now). +- dev_id : the display engine's identity within the system, which intends to replace ipu_id + (only valid for mipi dsi now). + +Example for IPU: + ipu1: ipu@02400000 { + compatible = "fsl,imx6q-ipu"; + reg = <0x02400000 0x400000>; + interrupts = <0 6 0x4 0 5 0x4>; + clocks = <&clks 130>, <&clks 131>, <&clks 132>, + <&clks 39>, <&clks 40>, + <&clks 135>, <&clks 136>; + clock-names = "bus", "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; + resets = <&src 2>; + bypass_reset = <0>; + }; + +Example for fb: + fb0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + +Example for mipi dsi display: + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks 138>, <&clks 204>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + dev_id = <0>; + disp_id = <0>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on> + resets = <&mipi_dsi_reset>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt new file mode 100644 index 00000000000000..49c7d321e2bfbb --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt @@ -0,0 +1,38 @@ +Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over +rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver +needed to get/set gpio status from M4 side by rpmsg. + +Required properties: +- compatible : Should be "fsl,imx-rpmsg-gpio". +- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1. +- gpio-controller : Mark the device node as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; +}; + +rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; +}; + +rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt new file mode 100644 index 00000000000000..1710abcdfa9d20 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt @@ -0,0 +1,23 @@ +* Freescale Low Power Inter IC (LPI2C) for i.MX + +Required properties: +- compatible : + - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc +- reg : address and length of the lpi2c master registers +- interrupt-parent : core interrupt controller +- interrupts : lpi2c interrupt +- clocks : lpi2c clock specifier + +Examples: + +lpi2c4: lpi2c4@402B0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402B0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index fbbad6446741e5..8877fa6a3df145 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -42,6 +42,8 @@ domintech,dmard09 DMARD09: 3-axis Accelerometer epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +fsl,fxas2100x FXAS2100X: Gyroscope sensor +fsl,fxos8700 FXOS8700: Accelerometer + Magnetometer Combo fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer diff --git a/Documentation/devicetree/bindings/input/rpmsg-keys.txt b/Documentation/devicetree/bindings/input/rpmsg-keys.txt new file mode 100644 index 00000000000000..af4e798fa55339 --- /dev/null +++ b/Documentation/devicetree/bindings/input/rpmsg-keys.txt @@ -0,0 +1,32 @@ +Device-Tree bindings for input/keyboard/rpmsg-keys.c keys driver over +rpmsg. On i.mx7ULP keys are connected on M4 side, so rpmsg-keys driver +needed to get the key status from M4 side by rpmsg. + +Required properties: + - compatible = "fsl,rpmsg-keys"; + +Each button/key looked as the sub node: +Required properties: + - label: the key name + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - rpmsg-key,wakeup: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + rpmsg-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + rpmsg-key,wakeup; + linux,code = ; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt new file mode 100644 index 00000000000000..8e5257db88f6f0 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt @@ -0,0 +1,48 @@ +FocalTech touch controller + +The focaltech controller is connected to host processor via i2c. +The controller generates interrupts when the user touches the panel. +The host controller is expected to read the touch coordinates over +i2c and pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "focaltech,fts" + - reg : i2c slave address of the device, should be <0x38> + - interrupt-parent : parent of interrupt + - interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge. + - focaltech,irq-gpio : irq gpio, same as "interrupts" node. + - focaltech,reset-gpio : reset gpio + - focaltech,num-max-touches : maximum number of touches support + - focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + +Optional properties: + - focaltech,have-key : specify if virtual keys are supported + - focaltech,key-number : number of keys + - focaltech,keys : virtual key codes mapping to the coords + - focaltech,key-y-coord : constant y coordinate of keys, depends on the y resolution + - focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution + - focaltech,swap-xy : swap x-y coordinates + - focaltech,panel-type : set panel type, default is FT5416 panel + - focaltech,scaling-down-half : scale down the x-y coordiantes to half + + +Example: + i2c@f9927000 { + focaltech@38{ + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 1920>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,swap-xy; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt index c98757a69110db..421b7d5ef29c7d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt @@ -5,6 +5,7 @@ Required properties: - compatible : Should be "goodix,gt911" or "goodix,gt9110" or "goodix,gt912" + or "goodix,gt9157" or "goodix,gt927" or "goodix,gt9271" or "goodix,gt928" @@ -18,6 +19,10 @@ Optional properties: - irq-gpios : GPIO pin used for IRQ. The driver uses the interrupt gpio pin as output to reset the device. - reset-gpios : GPIO pin used for reset + - esd-recovery-timeout-ms : ESD poll time (in milli seconds) for the driver to + check if ESD occurred and in that case reset the + device. ESD is disabled if this property is not set + or is set to 0. - touchscreen-inverted-x : X axis is inverted (boolean) - touchscreen-inverted-y : Y axis is inverted (boolean) diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt index 820fee4b77b601..ce85ee508238f2 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt @@ -18,6 +18,8 @@ Optional properties: - touchscreen-inverted-y : See touchscreen.txt - touchscreen-swapped-x-y : See touchscreen.txt - silead,max-fingers : maximum number of fingers the touchscreen can detect +- vddio-supply : regulator phandle for controller VDDIO +- avdd-supply : regulator phandle for controller AVDD Example: diff --git a/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt new file mode 100644 index 00000000000000..a41a0b9930064f --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt @@ -0,0 +1,18 @@ +* VTL Touchscreen Controller + +Required properties: +- compatible: must be "vtl,ct365" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- gpios: the gpio pin to be used for reset + +Example: + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 408f768686f1e9..a438909b5cc6b9 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -13,9 +13,10 @@ Required properties: - compatible: Should contain "syscon". - reg: the register region can be accessed from syscon -Optional property: +Optional properties: - reg-io-width: the size (in bytes) of the IO accesses that should be performed on the device. +- clocks: clock used for accessing the regmap Examples: gpr: iomuxc-gpr@020e0000 { diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 3e29050ec76965..de3270b0aec0b3 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -35,6 +35,8 @@ Optional properties: This property allows user to change the tuning step to more than one delay cells which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning retries. +- wifi-host : assigned as a wifi host. + This is required for Broadcom BCM WiFi cards to do card detect Examples: diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 8a377827695bd2..e654b50771171a 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -12,6 +12,8 @@ Only one of the properties in this section should be supplied: - broken-cd: There is no card detection available; polling must be used. - cd-gpios: Specify GPIOs for card detection, see gpio binding - non-removable: non-removable slot (like eMMC); assume always present. + - cd-post: postone card detect from start host for non-removable cards + and let client driver to start it when ready Optional properties: - bus-width: Number of data lines, can be <1>, <4>, or <8>. The default @@ -74,6 +76,9 @@ Optional SDIO properties: - keep-power-in-suspend: Preserves card power during a suspend/resume cycle - wakeup-source: Enables wake up of host system on SDIO IRQ assertion (Legacy property supported: "enable-sdio-wakeup") +- pm-ignore-notify: Ignore mmc PM notify. This will prevent MMC core automatically + to re-detect cards after sysem resume back. + MMC power --------- diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt index c34aa6f8a42445..951655466a1110 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt @@ -1,5 +1,11 @@ * Freescale Quad Serial Peripheral Interface(QuadSPI) +The QuadSPI controller acts as the SPI master. It is described with a node +for the controller and a set of child nodes for each SPI NOR flash. + +Part I - The DT node for the controller: +------------------------------ + Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", @@ -24,6 +30,16 @@ Optional properties: (Please check the board's schematic.) - big-endian : That means the IP register is big endian +Part II - The DT nodes for each SPI NOR flash +------------------------------ +Required properties: +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt + If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR + quad read feature for the driver. + Example: qspi0: quadspi@40044000 { diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index d02acaff3c35e9..2b7133639fd820 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -4,7 +4,8 @@ The GPMI nand controller provides an interface to control the NAND flash chips. Required properties: - - compatible : should be "fsl,-gpmi-nand" + - compatible : should be "fsl,-gpmi-nand", the chip should be imx23, + imx28, imx6q, imx6qp, imx6sx, imx6ul, imx7d or imx6ull. - reg : should contain registers location and length for gpmi and bch. - reg-names: Should contain the reg names "gpmi-nand" and "bch" - interrupts : BCH interrupt number. @@ -35,6 +36,10 @@ Optional properties: partitions written from Linux with this feature turned on may not be accessible by the BootROM code. + - fsl,legacy-bch-geometry: Use legacy bch geometry(ECC scheme) that + compatible with 3.10 kernel. Without the property, + software may use ECC strength according to NAND chip + spec, e.g. ONFI standard. The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt new file mode 100644 index 00000000000000..aba4d54233d226 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt @@ -0,0 +1,7 @@ +This file defines some DT properties for specific SPI NOR flash features. +The SPI NOR controller drivers may refer to this file, such as fsl-quadspi.txt + +Optional properties: + - spi-nor,ddr-quad-read-dummy: The dummy cycles used by the DDR Quad read. + Please refer to the chip's datasheet. This + property can be 4 or 6 which is less then 8. diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 56d6cc336e1cb2..00ff7d6c9f646f 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -17,6 +17,16 @@ Optional properties: - clock-frequency : The oscillator frequency driving the flexcan device - xceiver-supply: Regulator that powers the CAN transceiver +- stop-mode: register bits of stop mode control, the format is + <&gpr req_gpr req_bit ack_gpr ack_bit>. + gpr is the phandle to general purpose register node. + req_gpr is the gpr register offset of CAN stop request. + req_bit is the bit offset of CAN stop request. + ack_gpr is the gpr register offset of CAN stop acknowledge. + ack_bit is the bit offset of CAN stop acknowledge. +- trx_en_gpio : enable gpio +- trx_stby_gpio : standby gpio +- trx_nerr_gpio : NERR gpio Example: diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index a1e3693cca1601..555731a9eeceaa 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -5,6 +5,13 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain fec interrupt - phy-mode : See ethernet.txt file in the same directory +- clock-name: Should be the names of the clocks + - "ipg" for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing + - "ahb" for MAC ipg_clk, ipg_clk_mac that are bus clock + - "ptp" for IEEE1588 timer clock + - "enet_clk_ref" for MAC transmit/receiver reference clock + - "enet_out" output clock for external device +- clocks: Phandles to input clocks. Optional properties: - phy-reset-gpios : Should specify the gpio for phy reset @@ -30,6 +37,12 @@ Optional properties: - fsl,err006687-workaround-present: If present indicates that the system has the hardware workaround for ERR006687 applied and does not need a software workaround. +- fsl,wakeup_irq : The property define the wakeup irq index in enet irq source. +- stop-mode : If present, indicates soc need to set gpr bit to request stop + mode. +- fsl,ar8031-phy-fixup : If present, indicates board need to do phy fixup setting. +- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board + design, otherwise mutiple MACs share one MDIO bus to reduce Pins utilize. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes diff --git a/Documentation/devicetree/bindings/net/ti,wilink-st.txt b/Documentation/devicetree/bindings/net/ti,wilink-st.txt new file mode 100644 index 00000000000000..b1a421e2fde366 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,wilink-st.txt @@ -0,0 +1,41 @@ +TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices + +TI WiLink devices have a UART interface for providing Bluetooth, FM radio, +and GPS over what's called "shared transport". The shared transport is +standard BT HCI protocol with additional channels for the other functions. + +These devices also have a separate WiFi interface as described in +wireless/ti,wlcore.txt. + +This bindings follows the UART slave device binding in +../serial/slave-device.txt. + +Required properties: + - compatible: should be one of the following: + "ti,wl1271-st" + "ti,wl1273-st" + "ti,wl1281-st" + "ti,wl1283-st" + "ti,wl1285-st" + "ti,wl1801-st" + "ti,wl1805-st" + "ti,wl1807-st" + "ti,wl1831-st" + "ti,wl1835-st" + "ti,wl1837-st" + +Optional properties: + - enable-gpios : GPIO signal controlling enabling of BT. Active high. + - vio-supply : Vio input supply (1.8V) + - vbat-supply : Vbat input supply (2.9-4.8V) + +Example: + +&serial0 { + compatible = "ns16550a"; + ... + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 83aeb1f5a645ce..1f8db0b1ecef59 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -12,6 +12,7 @@ Required properties: - "msi": The interrupt that is asserted when an MSI is received - clock-names: Must include the following additional entries: - "pcie_phy" +- ext_osc: use the external oscillator or not. Optional properties: - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index 1d25b04cd05e17..415dc0d05805aa 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -7,6 +7,8 @@ Required properties: * "fsl,imx6sl-usbphy" for imx6sl * "fsl,vf610-usbphy" for Vybrid vf610 * "fsl,imx6sx-usbphy" for imx6sx + * "fsl,imx6ul-usbphy" for imx6ul + * "fsl,imx7ulp-usbphy" for imx7ulp "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt @@ -21,6 +23,9 @@ Optional properties: that terminates the DP output signal. Default: 45 - fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of the 17.78mA TX reference current. Default: 100 +- tx-d-cal: Try to adjust this value to improve signal quality, and pass + USB Certification, the value is from 0x0 to 0xf, and the register offset + is 0x10 (USBPHY_TX). Example: usbphy1: usbphy@020c9000 { @@ -28,4 +33,5 @@ usbphy1: usbphy@020c9000 { reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; fsl,anatop = <&anatop>; + tx-d-cal = <0x5>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644 index 00000000000000..541aead6260776 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -0,0 +1,33 @@ +* Freescale i.MX7ULP IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7ulp-iomuxc-0" or "fsl,imx7ulp-iomuxc-1" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = , PIN_FUNC_ID is a + pin working on a specific function, CONFIG is the pad setting value like + pull-up for this pin. Please refer to imx7ulp datasheet for the valid pad + config settings. + +NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and +config register as follows: + + +CONFIG bits definition: +PAD_CTL_OBE (1 << 17) +PAD_CTL_IBE (1 << 16) +PAD_CTL_LK (1 << 15) +PAD_CTL_DSE_HIGH (1 << 6) +PAD_CTL_DSE_STD (0 << 6) +PAD_CTL_ODE_OPEN_DRAIN (1 << 5) +PAD_CTL_ODE_PUSH_PULL (0 << 5) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_STD (0 << 2) +PAD_CTL_PE_PULL (1 << 1) +PAD_CTL_PS_UP (1 << 0) +PAD_CTL_PS_DOWN (0 << 0) + +Refer to imx7ulp-pinfunc.h in device tree source folder for all available +imx7ulp PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index b73c96d24f5924..05ede5f4509a8e 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -71,6 +71,13 @@ pinctrl-names: The list of names to assign states. List entry 0 defines the name for integer state ID 0, list entry 1 for state ID 1, and so on. +pinctrl-assert-gpios: + List of phandles, each pointing at a GPIO which is used by some + board design to steer pins between two peripherals on the board. + It plays like a board level pin multiplexer to choose different + functions for given pins by pulling up/down the GPIOs. See + bindings/gpio/gpio.txt for details of how to specify GPIO. + For example: /* For a client device requiring named states */ diff --git a/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt new file mode 100644 index 00000000000000..c6bfb731d31d36 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt @@ -0,0 +1,17 @@ +NXP TPM PWM controller + +Required properties: +- compatible: should be "nxp,tpm-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: should be 2. See pwm.txt in this directory for a description of + the cells format. +- nxp,pwm-number: the number of PWM devices + +Example: + +pwm0: tpm@40250000 { + compatible = "nxp,tpm-pwm"; + reg = <0x40250000 0x1000>; + nxp,pwm-number = <6>; + #pwm-cells = <2>; +}; diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt index 37c4ea076f88e6..03ea26d9ccbabf 100644 --- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt @@ -14,6 +14,7 @@ Optional properties: - anatop-delay-bit-shift: Bit shift for the step time register - anatop-delay-bit-width: Number of bits used in the step time register - vin-supply: The supply for this regulator +- anatop-enable-bit: Regulator output offset bit, only for 3p0, 2p5, and 1p1. Any property defined as part of the core regulator binding, defined in regulator.txt, can also be used. @@ -35,4 +36,5 @@ Example: anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; }; diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index 9b40db88f637bd..997174a46518cc 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -3,6 +3,8 @@ PFUZE100 family of regulators Required properties: - compatible: "fsl,pfuze100", "fsl,pfuze200", "fsl,pfuze3000" - reg: I2C slave address +- fsl,lpsr-mode: some registers need to be saved and restored in lpsr mode + for pfuze3000 Required child node: - regulators: This is the list of child nodes that specify the regulator diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt new file mode 100644 index 00000000000000..bca5348a513111 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt @@ -0,0 +1,35 @@ +GPIO reset controller +===================== + +A GPIO reset controller controls a single GPIO that is connected to the reset +pin of a peripheral IC. Please also refer to reset.txt in this directory for +common reset controller binding usage. + +Required properties: +- compatible: Should be "gpio-reset" +- reset-gpios: A gpio used as reset line. The gpio specifier for this property + depends on the gpio controller that provides the gpio. +- #reset-cells: 0, see below + +Optional properties: +- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for + this duration to reset. +- initially-in-reset: boolean. If not set, the initial state should be a + deasserted reset line. If this property exists, the + reset line should be kept in reset. + +example: + +sii902x_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + initially-in-reset; + #reset-cells = <0>; +}; + +/* Device with nRESET pin connected to GPIO5_0 */ +sii902x@39 { + /* ... */ + resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */ +}; diff --git a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt new file mode 100644 index 00000000000000..27d710274ec3f8 --- /dev/null +++ b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt @@ -0,0 +1,19 @@ +i.MX RPMSG platform implementations + +Required properties: +- compatible : "fsl,imx7d-rpmsg", "fsl,imx6sx-rpmsg" +- vdev-nums : The number of the remote virtual devices. +- reg : The reserved DDR phisical memory used to store + vring descriptors. + +Example: +rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + status = "disabled"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt b/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt new file mode 100644 index 00000000000000..e74d1b6547cd3d --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt @@ -0,0 +1,14 @@ +NXP Semiconductors PCF8523 Real Time Clock + +Required properties: +- compatible: should be: "nxp,pcf8523" +- reg: i2c address +- nxp,12p5_pf: force autodetection to start at 12.5 pf instead of 7pf + +Example: + +rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + nxp,12p5_pf; +}; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005efbcb870..4450498ec5abc2 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,14 +6,21 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : should contain: "ipg" - the uart clock +- clock-names : should contain: "ipg" - the uart peripheral register accessing + clock source, if "per" clock missing, the "ipg" clock also is the uart module + clock. Optional properties: - dmas: A list of two dma specifiers, one for each entry in dma-names. - dma-names: should contain "tx" and "rx". +- clocks : phandle + clock specifier pairs, one for each entry in clock-names +- clock-names : "per" - the uart module clock. + clock. Note: Optional properties for DMA support. Write them both or both not. diff --git a/Documentation/devicetree/bindings/soc/fsl/gpc.txt b/Documentation/devicetree/bindings/soc/fsl/gpc.txt new file mode 100644 index 00000000000000..a7d29282f8e3fe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/gpc.txt @@ -0,0 +1,56 @@ +* General Power Controller (GPC) +------------------------------------------- +The General Power Controller (GPC) module controls the following functions: + - Provide low power mode control for A7 and M4 platform + - Provide Power domain management all ARM and SOC power domain + - Provide domain control mechanism based on A7 and M4 CPU domain + - Provide handshake with CCM for clock management in low power mode + - Provide handshake with SRC for power down and power up sequence + - Provide handshake with Analog for Deep Sleep Mode control + +Required properties: + - reg : Offset and length of the register set of the GPC block. + - compatible : Must contain a chip-specific GPC block compatible string + and (if applicable) may contain a chassis-version GPC compatible + string. Chip-specific strings are of the form "fsl,-gpc", + such as: + * "fsl,imx7d-gpc" + * "fsl,imx7s-gpc" + - interrupt-controller : Specifies that this is an interrupt controller + +Example: +The GPC node for imx7d: + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; + +* Power Gating Controller (PGC) +------------------------------------------- +The Power Gating Controller (PGC) is a power management component that controls the +power-down and power-up sequencing of individual subsystems. +The PGC block is found inside GPC, and share the same register. + +Required properties: + - compatible : Must contain a chip-specific PGC block compatible string + and (if applicable) may contain a chassis-version PGC compatible + string. Chip-specific strings are of the form "fsl,-pgc", + such as: + * "fsl,imx7d-pgc" + * "fsl,imx7s-pgc" + - *-supply : Specifies the regulators that can be managed by this PGC. For exampe: + * "mipi-phy-supply = <®_1p0d>;" + +Example: +The PGC node for imx7d: + pgc { + compatible = "fsl,imx7d-pgc"; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index cd3ee5d84f030f..733c0a633c1336 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -46,6 +46,10 @@ Required properties: will be in use as default, or the big endian mode will be in use for all the device registers. + - fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Example: esai: esai@02024000 { diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.txt b/Documentation/devicetree/bindings/sound/fsl,mqs.txt new file mode 100644 index 00000000000000..7c288461e9ce7e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.txt @@ -0,0 +1,22 @@ +fsl,mqs audio CODEC + +Required properties: + + - compatible : must contain one of "fsl,imx6sx-mqs" and "fsl,codec-mqs" + + - clocks : a list of phandles + clock-specifiers, one for each entry in + clock-names + + - clock-names : must contain "mclk" + + - gpr : the gpr node. + +Example: + +mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt new file mode 100644 index 00000000000000..f38cf9d9050083 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt @@ -0,0 +1,20 @@ +Freescale rpmsg i2s interface. + +The rpmsg i2s is based on RPMSG that used communicating with M4 core, +which provides a synchronous audio interface that supports fullduplex +serial interfaces with frame synchronization such as I2S. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx7ulp-rpmsg-i2s". + + - fsl,audioindex : This is an index indicating the audio device index in + the M4 side. + +Example: +rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 4ca39ddc04172b..58b966b7a2af0e 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -37,6 +37,10 @@ Required properties: will be in use as default, or the big endian mode will be in use for all the device registers. + - fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Example: spdif: spdif@02004000 { diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt index 5b76be45d18bfe..3ad10966d3a5b8 100644 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt @@ -62,6 +62,10 @@ Optional properties: "ac97-slave" - AC97 mode, SSI is clock slave "ac97-master" - AC97 mode, SSI is clock master +- fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Child 'codec' node required properties: - compatible: Compatible list, contains the name of the codec diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt new file mode 100644 index 00000000000000..af746c4c81df21 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt @@ -0,0 +1,25 @@ +Freescale i.MX audio complex with CS42888 codec + +Required properties: +- compatible : "fsl,imx-audio-cs42888" +- model : The user-visible name of this sound complex +- esai-controller : The phandle of the i.MX SSI controller +- audio-codec : The phandle of the CS42888 audio codec + +Optional properties: +- asrc-controller : The phandle of the i.MX ASRC controller +- audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names could be power + supplies, CS42888 pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "cs42888-audio"; + esai-controller = <&esai>; + asrc-controller = <&asrc_p2p>; + audio-codec = <&codec>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt new file mode 100644 index 00000000000000..8e05abdc157355 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt @@ -0,0 +1,17 @@ +Freescale i.MX audio complex with mqs codec + +Required properties: +- compatible : "fsl,imx-audio-mqs" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX sai controller +- audio-codec : The phandle of the mqs audio codec + +Example: + +sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt new file mode 100644 index 00000000000000..3f015974ffebca --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt @@ -0,0 +1,13 @@ +Freescale i.MX audio complex with rpmsg devices + +Required properties: +- compatible : "fsl,imx-audio-rpmsg" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX rpmsg i2s device. + +Example: +sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt new file mode 100644 index 00000000000000..53cd34afe6b897 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt @@ -0,0 +1,24 @@ +Freescale i.MX audio complex with si476x codec + +Required properties: +- compatible : "fsl,imx-audio-si476x" +- model : The user-visible name of this sound complex +- ssi-controller : The phandle of the i.MX SSI controller + +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) +- mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Example: + +sound { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si476x"; + + ssi-controller = <&ssi1>; + mux-int-port = <2>; + mux-ext-port = <5>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt index acea71bee34fbf..06bc12d4cc76ee 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt @@ -6,7 +6,7 @@ Required properties: - model : The user-visible name of this sound complex - - ssi-controller : The phandle of the i.MX SSI controller + - cpu-dai : The phandle of CPU DAI - audio-codec : The phandle of the WM8962 audio codec @@ -31,13 +31,19 @@ Required properties: Note: The AUDMUX port numbering should start at 1, which is consistent with hardware manual. +Optional properties: +- hp-det-gpios : The gpio pin to detect plug in/out event that happens to + Headphone jack. +- mic-det-gpios: The gpio pin to detect plug in/out event that happens to + Microphone jack. + Example: sound { compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -50,4 +56,6 @@ sound { "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; }; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt b/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt new file mode 100644 index 00000000000000..ed55891bca96f9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with Freescale DAI transceiver. +Currently supports Freescale SAI or ESAI digital audio interface. + +Required properties: + + - compatible : "fsl,imx-audio-xtor" + + - model : The user-visible name of this sound complex + + - cpu-dai : The phandle of the i.MX DAI, currently supports + SAI or ESAI controller + +Optional properties: + + - asrc-controller : The phandle of the i.MX ASRC controller associated with DAI. + +Examples: + +sound-xtor-sai { + compatible = "fsl,imx-audio-xtor"; + model = "xtor-audio-sai"; + cpu-dai = <&sai0>; + asrc-controller = <&asrc0>; +}; + +sound-xtor-esai { + compatible = "fsl,imx-audio-xtor"; + model = "xtor-audio-esai"; + cpu-dai = <&esai0>; +}; diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 5666da7b86059f..7a73a9d62015ec 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt @@ -26,6 +26,15 @@ Optional properties: If this node is not mentioned or the value is unknown, then the value is set to 1.25V. +- lrclk-strength: the LRCLK pad strength. Possible values are: +0, 1, 2 and 3 as per the table below: + +VDDIO 1.8V 2.5V 3.3V +0 = Disable +1 = 1.66 mA 2.87 mA 4.02 mA +2 = 3.33 mA 5.74 mA 8.03 mA +3 = 4.99 mA 8.61 mA 12.05 mA + Example: codec: sgtl5000@0a { diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt index 7f82b59ec8f947..d15b9c82fd15b3 100644 --- a/Documentation/devicetree/bindings/sound/wm8962.txt +++ b/Documentation/devicetree/bindings/sound/wm8962.txt @@ -13,6 +13,14 @@ Optional properties: of R51 (Class D Control 2) gets set, indicating that the speaker is in mono mode. + - amic-mono: This is a boolean property. If present, indicating that the + analog micphone is hardware mono input, the driver would enable monomix + for it. + + - dmic-mono: This is a boolean property. If present, indicating that the + digital micphone is hardware mono input, the driver would enable monomix + for it. + - mic-cfg : Default register value for R48 (Additional Control 4). If absent, the default should be the register default. diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 8bc95e2fc47fad..31b5b21598ff57 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -23,6 +23,12 @@ See the clock consumer binding, Obsolete properties: - fsl,spi-num-chipselects : Contains the number of the chipselect +Optional properties: +- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register +controlling the SPI_READY handling. Note that to enable the DRCTL consideration, +the SPI_READY mode-flag needs to be set too. +Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). + Example: ecspi@70010000 { @@ -35,4 +41,5 @@ ecspi@70010000 { <&gpio3 25 0>; /* GPIO3_25 */ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; + fsl,spi-rdy-drctl = <1>; }; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 0e03344e2e8bb3..db7bc373b528f8 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -84,8 +84,20 @@ i.mx specific properties - over-current-active-high: over current signal polarity is high active, typically over current signal polarity is low active. - external-vbus-divider: enables off-chip resistor divider for Vbus +- imx6-usb-charger-detection: enable imx6 usb charger detect function, + only set it when the user wants SoC usb charger detection capabilities. + If the user wants to use charger IC's usb charger detection capabilities, + please do not set it. +- fsl,anatop: phandle for anatop module, anatop module is only existed + at imx6 SoC series. +- pinctrl-names: for names of hsic pin group +- pinctrl-0: hsic "idle" pin group +- pinctrl-1: hsic "active" pin group +- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock + and release the clock to the digital logic inside the analog block, + 0 <= osc-clkgate-delay <= 7. -Example: +Examples: usb@f7ed0000 { compatible = "chipidea,usb2"; @@ -103,3 +115,21 @@ Example: extcon = <0>, <&usb_id>; phy-clkgate-delay-us = <400>; }; + + usb@02184000 { /* USB OTG */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + disable-over-current; + external-vbus-divider; + imx6-usb-charger-detection; + fsl,anatop = <&anatop>; + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_1>; + pinctrl-1 = <&pinctrl_usbh2_2>; + osc-clkgate-delay = <0x3>; + maximum-speed = "full-speed"; + tpl-support; + }; diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt index f1e27faf528e7e..fe37ac11e873da 100644 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt @@ -7,6 +7,8 @@ Required properties: "fsl,vf610-usbmisc" for Vybrid vf610 "fsl,imx6sx-usbmisc" for imx6sx "fsl,imx7d-usbmisc" for imx7d + "fsl,imx6ul-usbmisc" for imx6ul + "fsl,imx7ulp-usbmisc" for imx7ulp - reg: Should contain registers location and length Examples: diff --git a/Documentation/input/goodix.txt b/Documentation/input/goodix.txt new file mode 100644 index 00000000000000..f9be1e20cd6ecc --- /dev/null +++ b/Documentation/input/goodix.txt @@ -0,0 +1,84 @@ +Goodix touchscreen driver +===================================== + +How to update configuration firmware +===================================== + +Goodix touchscreen devices have a set of registers that specify configuration +information for the device. The configuration information has a specific format +described in the Goodix datasheet. It includes X/Y resolution, maximum +supported touch points, interrupt flags, various sesitivity factors and +settings for advanced features (like gesture recognition). + +The devices have an initial default configuration that can be read through +the sysfs interface (/sys/class/input/inputX/device/dump_config). This default +configuration can be used as a starting point for creating a new configuration +firmware file. At init, the driver will read the configuration firmware file +and update the device configuration. + +This configuration can be accesed only if both interrupt and reset gpio pins +are connected and properly configured through ACPI _DSD/DT properties. + +Below are instructions on how to generate a valid configuration starting from +the device default configuration. + +1. Dump the default configuration of the device to a file: + $ cat /sys/class/input/inputX/device/dump_config > goodix__cfg + +2. Make the needed changes to the configuration (e.g. change resolution of +x/y axes, maximum reported touch points, switch X,Y axes, etc.). For more +details check the Goodix datasheet for format of Configuration Registers. + +3. Generate a valid configuration starting from goodix__cfg. +After making changes, you need to recompute the checksum of the entire +configuration data, set Config_Fresh to 1 and generate the binary config +firmware image. This can be done using a helper script similar to the +one below: + +#!/bin/bash + +if [[ $# -lt 1 ]]; then + echo "$0 fw_filename" + exit 1 +fi + +file_in="$1" +file_out_bin=${file_in}.bin + +print_val () +{ + val="$1" + printf "0x%.2x" "$val" | xxd -r -p >> ${file_out_bin} +} + +rm -f ${file_out_bin} + +size=`cat ${file_in} | wc -w` + +checksum=0 +i=1 +for val in `cat ${file_in}`; do + val="0x$val" + if [[ $i == $size ]]; then + # Config_Fresh + print_val 0x01 + elif [[ $i == $((size-1)) ]]; then + # Config_Chksum + checksum=$(( (~ checksum + 1) & 0xFF)) + print_val $checksum + else + checksum=$((checksum + val)) + print_val $val + fi + i=$((i+1)) +done + +echo "Wrote ${file_out_bin}" + +4. Copy the binary config firmware in the appropriate location +(e.g. /lib/firmware), using the name goodix__cfg.bin (e.g. for gt911, +use goodix_911_cfg.bin). + +5. Check that the new firmware was successfully written to the device +after reboot. Config_Fresh is reset to 0 after a successful update of the +configuration. diff --git a/Documentation/tda1997x b/Documentation/tda1997x new file mode 100644 index 00000000000000..79fad72965aca2 --- /dev/null +++ b/Documentation/tda1997x @@ -0,0 +1,31 @@ +The NXP TDA19971/19972 are HDMI receiver devices that decode HDMI +input signals and present a configurable parallel video output bus and +audio output bus. The internal video bus is 36bits while the output bus +differs per device. These devices offer High Definition (HD) video resolutions +up to 1080p50/60 or WUXGA and HD audio formats up to 8 channels such as DTS HD +and Dolby True HD. The chips optionally include an HDCP 1.4 engine with +pre-programmed keys stored into an internal NV memory. Additionally the chips +also supports several HDMI 1.4b options such as 3D formats up to 1080p50/60, +Deep Colors up to 36bpp and extended colorimetry. + +The TDA19971 has one HDMI input (HDMI-A) and 24bit output bus and the TDA19972 +has two HDMI inputs (HDMI-A/B) and a 36bit video output bus. + +Driver Details: +--------------- + +The chips respond to two i2c slave addresses, the first allows access to +HDMI input, audio, and video status and configuration and the second allows +access to CEC. + +The tda1997x-core driver attaches to the i2c slave that controls the device. +It also manages the 2nd i2c slave for CEC. The platform data structure +provides details about the desired video output bus configuration and the +desired audio output bus configuration. An ASoC codec driver is also provided +however this is merely a skeleton driver as the audio output format cannot +be changed and is dependent upon the HDMI input signal. A separate platform +specific device video driver can interact with the core to obtain information +about the video data format which is dependent upon the HDMI input signal. A +separate platform specific ASoC SoC DAI driver can interact with the core +to obtain information about the audio data format which is dependent upon +the HDMI input signal. diff --git a/Documentation/usb/chipidea.txt b/Documentation/usb/chipidea.txt index edf7cdfddc88a1..2b0c435f4cc9b4 100644 --- a/Documentation/usb/chipidea.txt +++ b/Documentation/usb/chipidea.txt @@ -32,7 +32,10 @@ cat /sys/kernel/debug/ci_hdrc.0/registers B-device should take host role and enumrate A-device. 4) A-device switch back to host. - On B-device: + On A-device: + echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req + + or, on B-device: echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req or, by introducing HNP polling, B-Host can know when A-peripheral wish @@ -74,6 +77,14 @@ cat /sys/kernel/debug/ci_hdrc.0/registers "On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification July 27, 2012 Revision 2.0 version 1.1a" +1.4 OTG compliance test +---------------------- +Only below 3 popular gadget drivers are declared to be USB OTG and EH 2.0 +compliant(with otg descriptor comply with USB OTG and EH 2.0 as a peripheral): +- mass storage +- ether +- serial + 2. How to enable USB as system wakeup source ----------------------------------- Below is the example for how to enable USB as system wakeup source diff --git a/MAINTAINERS b/MAINTAINERS index 63cefa62324cd1..d0ce98efe60ed9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10608,6 +10608,14 @@ S: Maintained F: Documentation/devicetree/bindings/serial/ F: drivers/tty/serial/ +SERIAL DEVICE BUS +M: Rob Herring +L: linux-serial@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/serial/slave-device.txt +F: drivers/tty/serdev/ +F: include/linux/serdev.h + STI CEC DRIVER M: Benjamin Gaignard L: kernel@stlinux.com diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5d529fdffab28..52af0ba2a41e0f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1206,6 +1206,16 @@ config ARM_ERRATA_825619 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable and Device/Strongly-Ordered loads and stores might cause deadlock +config ARM_ERRATA_814220 + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" + depends on CPU_V7 + help + The v7 ARM states that all cache and branch predictor maintenance operations + that do not specify an address execute, relative to each other, in program order. + However, because of this erratum, an L2 set/way cache maintenance operation can + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 @@ -1738,6 +1748,7 @@ config FORCE_MAX_ZONEORDER int "Maximum zone order" default "12" if SOC_AM33XX default "9" if SA1111 || ARCH_EFM32 + default "14" if ARCH_MXC default "11" help The kernel memory allocator divides physically contiguous memory diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index d83f7c369e514d..6d449e5d545010 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -405,6 +405,13 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6SL. + config DEBUG_IMX6SLL_UART + bool "i.MX6SLL Debug UART" + depends on SOC_IMX6SLL + help + Say Y here if you want kernel low-level debugging support + on i.MX6SLL. + config DEBUG_IMX6SX_UART bool "i.MX6SX Debug UART" depends on SOC_IMX6SX @@ -1350,6 +1357,7 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX53_UART || \ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ + DEBUG_IMX6SLL_UART || \ DEBUG_IMX6SX_UART || \ DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART @@ -1404,6 +1412,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ + DEBUG_IMX6SLL_UART || \ DEBUG_IMX6SX_UART || \ DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7037201c5e3a7d..28d30d0befca0b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -312,6 +312,7 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-babbage.dtb \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-nitrogen51_vm.dtb \ imx51-ts4800.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ @@ -325,12 +326,20 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-a.dtb \ + imx6dl-acl.dtb \ + imx6dl-ap.dtb \ imx6dl-apf6dev.dtb \ imx6dl-aristainetos_4.dtb \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-ash.dtb \ + imx6dl-ash2.dtb \ + imx6dl-bt.dtb \ imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ @@ -340,14 +349,41 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw552x.dtb \ imx6dl-gw553x.dtb \ imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ + imx6dl-hl.dtb \ + imx6dl-hp.dtb \ + imx6dl-lshore.dtb \ + imx6dl-mcs.dtb \ + imx6dl-mtp.dtb \ + imx6dl-neol.dtb \ imx6dl-nit6xlite.dtb \ + imx6dl-nit6xlite-access.dtb \ + imx6dl-nitrogen6_max.dtb \ + imx6dl-nitrogen6_som2.dtb \ + imx6dl-nitrogen6_vm.dtb \ + imx6dl-nitrogen6_vm-magstripe.dtb \ + imx6dl-nitrogen6_vm-pt.dtb \ imx6dl-nitrogen6x.dtb \ + imx6dl-per.dtb \ imx6dl-phytec-pbab01.dtb \ + imx6dl-rc.dtb \ imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-enetirq.dtb \ + imx6dl-sabreauto-flexcan1.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ + imx6dl-sabresd-btwifi.dtb \ + imx6dl-sabresd-hdcp.dtb \ + imx6dl-sabresd-ldo.dtb \ + imx6dl-sp.dtb \ imx6dl-ts4900.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ @@ -357,18 +393,45 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-tx6u-811x.dtb \ imx6dl-tx6u-81xx-mb7.dtb \ imx6dl-udoo.dtb \ + imx6dl-sabresd-enetirq.dtb \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ + imx6dqscm-1gb-qwks-rev2-fix-ldo.dtb \ + imx6dqscm-1gb-qwks-rev2-interleave-android-ldo.dtb \ + imx6dqscm-1gb-qwks-rev2-wifi-fix-ldo.dtb \ + imx6dqscm-1gb-qwks-rev2-hdcp-fix-ldo.dtb \ + imx6dqscm-1gb-evb-fix-ldo.dtb \ + imx6dqscm-1gb-evb-interleave-android-ldo.dtb \ + imx6dqscm-1gb-evb-btwifi-fix-ldo.dtb \ + imx6dqscm-1gb-evb-enetirq-fix-ldo.dtb \ + imx6dqscm-1gb-evb-hdcp-fix-ldo.dtb \ + imx6dqscm-1gb-qwks-rev3-fix-ldo.dtb \ + imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dtb \ + imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dtb \ + imx6q-acl.dtb \ + imx6q-ap.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ + imx6q-arm2-hsic.dtb \ imx6q-b450v3.dtb \ imx6q-b650v3.dtb \ imx6q-b850v3.dtb \ + imx6q-pop-arm2.dtb \ + imx6q-bt.dtb \ + imx6q-bt2.dtb \ + imx6q-cid.dtb \ + imx6q-cid_tab.dtb \ imx6q-cm-fx6.dtb \ + imx6q-cnt.dtb \ + imx6q-cob.dtb \ + imx6q-cob2.dtb \ imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ imx6q-dfi-fs700-m60.dtb \ imx6q-dmo-edmqmx6.dtb \ + imx6q-eo.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ @@ -380,18 +443,53 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw552x.dtb \ imx6q-gw553x.dtb \ imx6q-h100.dtb \ + imx6q-h4.dtb \ + imx6q-hp.dtb \ imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ imx6q-icore-rqs.dtb \ + imx6q-insp.dtb \ + imx6q-ioc.dtb \ + imx6q-jlm.dtb \ + imx6q-ls.dtb \ imx6q-marsboard.dtb \ + imx6q-mcs.dtb \ + imx6q-mtp.dtb \ + imx6q-neol.dtb \ + imx6q-neol-test.dtb \ imx6q-nitrogen6x.dtb \ + imx6q-nitrogen6x-st7789.dtb \ + imx6q-nitrogen6x-careview.dtb \ imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_max-apex.dtb \ + imx6q-nitrogen6_max-lantech.dtb \ + imx6q-nitrogen6_max-st7789.dtb \ + imx6q-nitrogen6_som2.dtb \ + imx6q-nitrogen6_som2-ta.dtb \ imx6q-novena.dtb \ + imx6q-nw2.dtb \ + imx6q-per.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ + imx6q-s.dtb \ imx6q-sabreauto.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-enetirq.dtb \ + imx6q-sabreauto-flexcan1.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ + imx6q-sabresd-btwifi.dtb \ + imx6q-sabresd-hdcp.dtb \ + imx6q-sabresd-ldo.dtb \ + imx6q-sabresd-enetirq.dtb \ imx6q-sbc6x.dtb \ + imx6q-snap.dtb \ + imx6q-ta.dtb \ imx6q-tbs2910.dtb \ imx6q-ts4900.dtb \ imx6q-tx6q-1010.dtb \ @@ -402,36 +500,173 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-tx6q-1110.dtb \ imx6q-tx6q-11x0-mb7.dtb \ imx6q-udoo.dtb \ + imx6q-usd.dtb \ + imx6q-usd_mr2.dtb \ + imx6q-utc.dtb \ imx6q-utilite-pro.dtb \ + imx6q-vp.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ + imx6qp-mtp.dtb \ imx6qp-nitrogen6_max.dtb \ + imx6qp-nitrogen6_som2.dtb \ imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-flexcan1.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ + imx6qp-sabresd-btwifi.dtb \ + imx6qp-sabresd-hdcp.dtb \ + imx6qp-sabresd-ldo.dtb \ + imx6qp-sabresd-ldo-pcie-cert.dtb \ imx6qp-sabresd.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-evk-btwifi.dtb \ + imx6sl-evk-ldo.dtb \ + imx6sl-evk-csi.dtb \ + imx6sl-evk-uart.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-14x14-arm2.dtb \ + imx6sx-nitrogen6_scm.dtb \ imx6sx-nitrogen6sx.dtb \ + imx6sx-nitrogen6sx-m4.dtb \ imx6sx-sabreauto.dtb \ + imx6sx-sabreauto-m4.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb + imx6sx-sdb-reva-ldo.dtb \ + imx6sx-sdb.dtb \ + imx6sx-sdb-btwifi.dtb \ + imx6sx-sdb-emmc.dtb \ + imx6sx-sdb-lcdif1.dtb \ + imx6sx-sdb-ldo.dtb \ + imx6sx-sdb-m4.dtb \ + imx6sx-sdb-mqs.dtb \ + imx6sx-sdb-sai.dtb \ + imx6sx-ys.dtb \ + imx6sx-ys-m4.dtb \ + imx6sx-19x19-arm2.dtb \ + imx6sx-19x19-arm2-ldo.dtb \ + imx6sx-19x19-arm2-csi.dtb \ + imx6sx-19x19-arm2-gpmi-weim.dtb \ + imx6sxscm-1gb-evb-ldo.dtb \ + imx6sxscm-1gb-evb-lcdif1-ldo.dtb \ + imx6sxscm-1gb-evb-m4-ldo.dtb \ + imx6sxscm-1gb-evb-mqs-ldo.dtb \ + imx6sxscm-1gb-evb-sai-ldo.dtb \ + imx6sxscm-1gb-evb-btwifi-ldo.dtb \ + imx6sxscm-epop-evb-ldo.dtb \ + imx6sxscm-epop-evb-m4-ldo.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-14x14-evk-btwifi.dtb \ + imx6ul-14x14-evk-btwifi-oob.dtb \ + imx6ul-14x14-evk-csi.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ + imx6ul-14x14-evk-usb-certi.dtb \ imx6ul-geam-kit.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb + imx6ul-tx6ul-mainboard.dtb \ + imx6ul-14x14-ddr3-arm2.dtb \ + imx6ul-14x14-ddr3-arm2-emmc.dtb \ + imx6ul-14x14-ddr3-arm2-flexcan2.dtb \ + imx6ul-14x14-ddr3-arm2-gpmi-weim.dtb \ + imx6ul-14x14-ddr3-arm2-mqs.dtb \ + imx6ul-14x14-ddr3-arm2-spdif.dtb \ + imx6ul-14x14-ddr3-arm2-wm8958.dtb \ + imx6ul-14x14-lpddr2-arm2.dtb \ + imx6ul-14x14-evk-pf1550.dtb \ + imx6ul-9x9-evk.dtb \ + imx6ul-9x9-evk-btwifi.dtb \ + imx6ul-9x9-evk-btwifi-oob.dtb \ + imx6ul-9x9-evk-csi.dtb \ + imx6ul-9x9-evk-ldo.dtb +dtb-$(CONFIG_SOC_IMX6ULL) += \ + imx6ull-14x14-ddr3-arm2.dtb \ + imx6ull-14x14-ddr3-arm2-adc.dtb \ + imx6ull-14x14-ddr3-arm2-cs42888.dtb \ + imx6ull-14x14-ddr3-arm2-ecspi.dtb \ + imx6ull-14x14-ddr3-arm2-emmc.dtb \ + imx6ull-14x14-ddr3-arm2-epdc.dtb \ + imx6ull-14x14-ddr3-arm2-flexcan2.dtb \ + imx6ull-14x14-ddr3-arm2-gpmi-weim.dtb \ + imx6ull-14x14-ddr3-arm2-lcdif.dtb \ + imx6ull-14x14-ddr3-arm2-ldo.dtb \ + imx6ull-14x14-ddr3-arm2-qspi.dtb \ + imx6ull-14x14-ddr3-arm2-qspi-all.dtb \ + imx6ull-14x14-ddr3-arm2-tsc.dtb \ + imx6ull-14x14-ddr3-arm2-uart2.dtb \ + imx6ull-14x14-ddr3-arm2-usb.dtb \ + imx6ull-14x14-ddr3-arm2-wm8958.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-btwifi.dtb \ + imx6ull-14x14-evk-btwifi-oob.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ull-14x14-evk-usb-certi.dtb \ + imx6ull-9x9-evk.dtb \ + imx6ull-9x9-evk-btwifi.dtb \ + imx6ull-9x9-evk-btwifi-oob.dtb \ + imx6ull-9x9-evk-ldo.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-lpddr2-arm2.dtb \ + imx6sll-lpddr3-arm2.dtb \ + imx6sll-lpddr3-arm2-csi.dtb \ + imx6sll-lpddr3-arm2-ecspi.dtb \ + imx6sll-lpddr3-arm2-spdif.dtb \ + imx6sll-evk.dtb \ + imx6sll-evk-reva.dtb \ + imx6sll-evk-btwifi.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ + imx7d-nitrogen7-m4.dtb \ imx7d-sbc-imx7.dtb \ - imx7d-sdb.dtb \ imx7s-colibri-eval-v3.dtb \ - imx7s-warp.dtb + imx7s-warp.dtb \ + imx7d-12x12-lpddr3-arm2.dtb \ + imx7d-12x12-lpddr3-arm2-m4.dtb \ + imx7d-12x12-ddr3-arm2.dtb \ + imx7d-12x12-lpddr3-arm2-ecspi.dtb \ + imx7d-12x12-lpddr3-arm2-enet2.dtb \ + imx7d-12x12-lpddr3-arm2-flexcan.dtb \ + imx7d-12x12-lpddr3-arm2-mipi_dsi.dtb \ + imx7d-12x12-lpddr3-arm2-qspi.dtb \ + imx7d-12x12-lpddr3-arm2-sai.dtb \ + imx7d-12x12-lpddr3-arm2-mqs.dtb \ + imx7d-12x12-lpddr3-arm2-pcie.dtb \ + imx7d-19x19-lpddr2-arm2.dtb \ + imx7d-sdb.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-m4.dtb \ + imx7d-sdb-qspi.dtb \ + imx7d-sdb-mipi-dsi.dtb \ + imx7d-sdb-reva.dtb \ + imx7d-sdb-reva-epdc.dtb \ + imx7d-sdb-reva-gpmi-weim.dtb \ + imx7d-sdb-reva-hdmi-audio.dtb \ + imx7d-sdb-reva-m4.dtb \ + imx7d-sdb-reva-qspi.dtb \ + imx7d-sdb-reva-touch.dtb \ + imx7d-sdb-reva-wm8960.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-14x14-arm2.dtb \ + imx7ulp-evk.dtb \ + imx7ulp-evk-emmc.dtb \ + imx7ulp-evk-emmc-qspi.dtb \ + imx7ulp-evk-ft5416.dtb \ + imx7ulp-evk-sd1.dtb \ + imx7ulp-evk-lpuart.dtb \ + imx7ulp-evk-qspi.dtb \ + imx7ulp-evk-wm8960.dtb \ + imx7ulp-evk-hdmi.dtb \ + imx7ulp-evk-sensors-to-i2c5.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/imx51-nitrogen51_vm.dts b/arch/arm/boot/dts/imx51-nitrogen51_vm.dts new file mode 100644 index 00000000000000..50d5ff861be1ec --- /dev/null +++ b/arch/arm/boot/dts/imx51-nitrogen51_vm.dts @@ -0,0 +1,952 @@ +/* + * Copyright 2016 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx51.dtsi" +#include +#include +#include +#include + +#define USE_SAS + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen51_vm: iomuxc-imx6q-nitrogen51-vmgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen51_vm { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0xa5 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0xa5 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 +#define GP_ECSPI1_PMIC <&gpio4 24 GPIO_ACTIVE_HIGH> + MX51_PAD_CSPI1_SS0__GPIO4_24 0xe5 +#define GP_ECSPI1_FLASH <&gpio4 25 GPIO_ACTIVE_LOW> + MX51_PAD_CSPI1_SS1__GPIO4_25 0xe5 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 +#define GP_ESDHC1_CD <&gpio1 0 GPIO_ACTIVE_LOW> + MX51_PAD_GPIO1_0__GPIO1_0 0x1e5 +#define GP_ESDHC1_WP <&gpio1 1 GPIO_ACTIVE_HIGH> + MX51_PAD_GPIO1_1__GPIO1_1 0x1e5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + MX51_PAD_UART1_RTS__GPIO4_30 0x1e5 /* spare */ + MX51_PAD_UART1_CTS__GPIO4_31 0x1e5 /* sdio_int */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x01f5 + MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x2180 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x2004 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x2004 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x0180 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x0180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x20a4 + MX51_PAD_EIM_CS5__FEC_CRS 0x0180 + MX51_PAD_NANDF_RB2__FEC_COL 0x0180 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x0085 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x0085 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x0085 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < +#define GP_GPIOKEYS_1 <&gpio3 7 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_WP_B__GPIO3_7 0x1e5 +#define GP_GPIOKEYS_2 <&gpio3 8 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_RB0__GPIO3_8 0x1e5 +#define GP_GPIOKEYS_3 <&gpio3 9 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_RB1__GPIO3_9 0x1e5 +#define GP_GPIOKEYS_4 <&gpio3 16 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_CS0__GPIO3_16 0x1e5 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < +#define GP_GPIOLEDS_1 <&gpio3 3 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_WE_B__GPIO3_3 0xe5 +#define GP_GPIOLEDS_2 <&gpio3 4 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_RE_B__GPIO3_4 0xe5 +#define GP_GPIOLEDS_3 <&gpio1 4 GPIO_ACTIVE_LOW> + MX51_PAD_GPIO1_4__GPIO1_4 0xe5 +#define GP_GPIOLEDS_4 <&gpio3 6 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_CLE__GPIO3_6 0xe5 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP27 <&gpio3 17 GPIO_ACTIVE_LOW> + MX51_PAD_NANDF_CS1__GPIO3_17 0x1e5 +#define GP_ADC_TRIG <&gpio4 13 GPIO_ACTIVE_HIGH> + MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1e5 + >; + }; + + pinctrl_hs_i2c1: hs-i2c1grp { + fsl,pins = < + MX51_PAD_I2C1_CLK__I2C1_CLK 0x400001ed + MX51_PAD_I2C1_DAT__I2C1_DAT 0x400001ed + >; + }; + + pinctrl_hs_i2c1_scl_gpio: hs-i2c1-scl-gpiogrp { + fsl,pins = < +#define GP_HS_I2C1_SCL <&gpio4 16 GPIO_ACTIVE_HIGH> + MX51_PAD_I2C1_CLK__GPIO4_16 0x400001ed + >; + }; + + pinctrl_hs_i2c1_sda_gpio: hs-i2c1-sda-gpiogrp { + fsl,pins = < +#define GP_HS_I2C1_SDA <&gpio4 17 GPIO_ACTIVE_HIGH> + MX51_PAD_I2C1_DAT__GPIO4_17 0x400001ed + >; + }; + + pinctrl_hs_i2c1_pic16f616: hs-i2c1-pic16f616grp { + fsl,pins = < +#define GPIRQ_PIC16F616 <&gpio2 1 IRQ_TYPE_LEVEL_LOW> +#define GP_PIC16F616 <&gpio2 1 GPIO_ACTIVE_LOW> + MX51_PAD_EIM_D17__GPIO2_1 0x85 /* No pullup option */ + >; + }; + + pinctrl_hs_i2c1_tfp410: hs-i2c1-tfp410grp { + fsl,pins = < +#define GPIRQ_DVI <&gpio3 28 IRQ_TYPE_EDGE_FALLING> + MX51_PAD_NANDF_D12__GPIO3_28 0x1e5 +#define GP_TFP410_I2C_SEL <&gpio3 5 GPIO_ACTIVE_HIGH> + MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0xc5 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed + MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < +#define GP_SGTL5000_HP_MUTE <&gpio2 17 GPIO_ACTIVE_LOW> + MX51_PAD_EIM_A23__GPIO2_17 0xc5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_i2c2_ov5642: i2c2-ov5642grp { /* parallel camera */ + fsl,pins = < + MX51_PAD_CSI1_D8__CSI1_D8 0x85 + MX51_PAD_CSI1_D9__CSI1_D9 0x85 + MX51_PAD_CSI1_D10__CSI1_D10 0x0 + MX51_PAD_CSI1_D11__CSI1_D11 0x0 + MX51_PAD_CSI1_D12__CSI1_D12 0x0 + MX51_PAD_CSI1_D13__CSI1_D13 0x0 + MX51_PAD_CSI1_D14__CSI1_D14 0x0 + MX51_PAD_CSI1_D15__CSI1_D15 0x0 + MX51_PAD_CSI1_D16__CSI1_D16 0x0 + MX51_PAD_CSI1_D17__CSI1_D17 0x0 + MX51_PAD_CSI1_D18__CSI1_D18 0x0 + MX51_PAD_CSI1_D19__CSI1_D19 0x0 + MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x0 + MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x0 + MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x0 + MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x85 + MX51_PAD_CSI2_D12__GPIO4_9 0x85 + MX51_PAD_CSI2_D13__GPIO4_10 0x85 +#define GP_OV5642_RESET <&gpio4 14 GPIO_ACTIVE_LOW> + MX51_PAD_CSI2_HSYNC__GPIO4_14 0xe5 +#define GP_OV5642_POWER_DOWN <&gpio4 15 GPIO_ACTIVE_HIGH> + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0xe5 + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < +#if 0 + MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK 0x85 + MX51_PAD_DI1_PIN15__DI1_PIN15 0x5 +#endif + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + >; + }; + + pinctrl_ipu_disp2: ipudisp2grp { + fsl,pins = < + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + MX51_PAD_DI_GP4__DI2_PIN15 0x5 + MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 + MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 + MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 + MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 + MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 + MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 + MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 + MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 + MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 + MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 + MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 + MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 + MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 + MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 + MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 + MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < +#define GPIRQ_PMIC <&gpio1 8 IRQ_TYPE_LEVEL_HIGH> + MX51_PAD_GPIO1_8__GPIO1_8 0x1e5 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX51_PAD_GPIO1_2__PWM1_PWMO 0xc5 + >; + }; + + pinctrl_reg3p3v: reg3p3vgrp { + fsl,pins = < +#define GP_REG3P3V_EN <&gpio2 6 GPIO_ACTIVE_HIGH> + MX51_PAD_EIM_D22__GPIO2_6 0x85 + >; + }; + + pinctrl_reg_usbotg: usbotggrp { + fsl,pins = < + MX51_PAD_EIM_D26__KEY_COL7 0xe5 /* high is off */ + >; + }; + + pinctrl_reg_usbotg_enable5v: usbotg-enable5vgrp { + fsl,pins = < + MX51_PAD_EIM_D26__KEY_COL7 0xc5 /* low is on */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 +#define GP_USBH1_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX51_PAD_EIM_D21__GPIO2_5 0xc5 + >; + }; +}; + +/ { + model = "Boundary Devices i.MX51 nitrogen51_vm Board"; + compatible = "fsl,imx51-nitrogen51_vm", "fsl,imx51"; + +/* #define USE_DRM */ + + aliases { + backlight_lcd = &backlight_lcd; + fb_lcd = &fb_lcd; + fb_lcd2 = &fb_lcd2; +#ifdef USE_DRM + lcd = &fb_lcd; + lcd2 = &fb_lcd2; +#else + lcd = &lcd; + lcd2 = &lcd2; +#endif + mmc0 = &esdhc1; + mmc1 = &esdhc2; +#ifndef USE_DRM + mxcfb0 = &fb_lcd; + mxcfb1 = &fb_lcd2; +#endif + pwm_lcd = &pwm1; + serial0 = &uart1; + serial1 = &uart3; + serial2 = &uart2; +#ifdef USE_DRM + t_lcd = &lcd_timings; + t_lcd2 = &lcd2_timings; +#endif + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>, <&fb_lcd2>; + pwms = <&pwm1 0 500000>; + }; + + clocks { + ckih1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + clk_26M: codec_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + fb_lcd: display@di0 { +#ifdef USE_DRM + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + display-timings { + native-mode = <&lcd_timings>; + lcd_timings: dvi { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; +#else + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#endif + }; + + fb_lcd2: display@di1 { +#ifdef USE_DRM + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 1>; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp2>; + status = "disabled"; + display-timings { + native-mode = <&lcd2_timings>; + lcd2_timings: claawvga { + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; +#else + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#endif + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEYS_1; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEYS_2; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEYS_3; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEYS_4; + linux,code = ; + gpio-key,wakeup; + }; + + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "led1"; + gpios = GP_GPIOLEDS_1; + }; + + led2 { + label = "led2"; + gpios = GP_GPIOLEDS_2; + }; + + led3 { + label = "led3"; + gpios = GP_GPIOLEDS_3; + }; + + led4 { + label = "led4"; + gpios = GP_GPIOLEDS_4; + }; + }; + +#ifndef USE_DRM + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + status = "disabled"; + }; + lcd2: lcd@1 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <1>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp2>; + status = "disabled"; + }; +#endif + memory { + reg = <0x90000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + +#if 1 + reg_3p3vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg3p3v>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG3P3V_EN; + enable-active-high; + regulator-always-on; + }; +#endif + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default", "disable", "enable"; + pinctrl-0 = <&pinctrl_reg_usbotg>; + pinctrl-1 = <&pinctrl_reg_usbotg>; + pinctrl-2 = <&pinctrl_reg_usbotg_enable5v>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + reserved-memory { + linux,cma { + size = <0x2000000>; + }; + }; + +#ifdef USE_SAS + sas: sas@73fc0000 { + clocks = <&clks 30>, <&clks 31>; + clock-names = "ipg", "per"; + compatible = "boundary,imx51-sas"; + interrupt-parent = <&tzic>; + interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + reg = <0x73fc0000 0x4000>; + }; +#endif + + sound { + compatible = "fsl,imx51-nitrogen51_vm-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + mute-gpios = GP_SGTL5000_HP_MUTE; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <2>; + cs-gpios = GP_ECSPI1_PMIC, GP_ECSPI1_FLASH; + status = "okay"; + + pmic: mc13892@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13892"; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupts-extended = GPIRQ_PMIC; + fsl,mc13xxx-uses-touch; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + }; + + flash: m25p80@1 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = GP_ESDHC1_CD; + wp-gpios = GP_ESDHC1_WP; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; +}; + +&hs_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "scl-gpio", "sda-gpio"; + pinctrl-0 = <&pinctrl_hs_i2c1>; + pinctrl-1 = <&pinctrl_hs_i2c1_scl_gpio>; + pinctrl-2 = <&pinctrl_hs_i2c1_sda_gpio>; + scl-gpios = GP_HS_I2C1_SCL; + sda-gpios = GP_HS_I2C1_SDA; + status = "okay"; + + mma7660: mma7660@4c { + compatible = "mma7660"; + reg = <0x4c>; + }; + + pic16f616: pic16f616@22 { + compatible = "Pic16F616-ts"; + interrupts-extended = GPIRQ_PIC16F616; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hs_i2c1_pic16f616>; + reg = <0x22>; + wakeup-gpios = GP_PIC16F616; + }; + + /* hs i2c should not use addresses 0x01,0x21,0x41,0x61 */ + reserve@21 { + compatible = "reserve"; + reg = <0x21>; + }; + + reserve@41 { + compatible = "reserve"; + reg = <0x41>; + }; + + reserve@61 { + compatible = "reserve"; + reg = <0x61>; + }; +#if 0 + tfp410: tfp410@38 { + compatible = "tfp410"; + display_id = "???lcdif2"; + i2c_sel-gpios = GP_TFP410_I2C_SEL; + interrupts-extended = GPIRQ_DVI; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hs_i2c1_tfp410>; + reg = <0x38>; + }; +#endif +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clk_26M>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +#if 0 + ov5642: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5642>; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; +#endif +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +#ifdef USE_SAS +&sas { + baud = <19200>; + flush_on_mark = <0>; + interbyte_delay = <5>; + maxtxmsg = <512>; + rxbufsize = <4096>; + status = "okay"; + txbufsize = <4096>; +}; +#endif + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +#ifndef USE_SAS +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +#endif + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + fsl,usbphy = <&usbphy0>; + phy_type = "ulpi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USBH1_RESET; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/imx51-pinfunc.h index 82eae3c8a3ce26..9d613984f63e5e 100644 --- a/arch/arm/boot/dts/imx51-pinfunc.h +++ b/arch/arm/boot/dts/imx51-pinfunc.h @@ -395,9 +395,9 @@ #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 #define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 +#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x10 0x0 #define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 -#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 +#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x10 0x0 #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 @@ -596,7 +596,9 @@ #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 #define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 +#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK 0x0 0x730 0x000 0x0 0x0 #define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN15__DI1_PIN15 0x0 0x738 0x000 0x0 0x0 #define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 #define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 #define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 @@ -678,7 +680,7 @@ #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 #define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 #define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 -#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 +#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x10 0x0 #define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 #define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 #define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 @@ -716,7 +718,7 @@ #define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 #define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 #define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 -#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 +#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x10 0x0 #define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 #define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 #define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index f46fe9bf0bcb37..85a6996b0cec23 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -26,6 +26,7 @@ gpio3 = &gpio4; i2c0 = &i2c1; i2c1 = &i2c2; + ipu0 = &ipu; mmc0 = &esdhc1; mmc1 = &esdhc2; mmc2 = &esdhc3; @@ -131,9 +132,12 @@ interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; + <&clks IMX5_CLK_IPU_DI1_GATE>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>; + clock-names = "bus", "di0", "di1", "di0_sel", "di1_sel"; resets = <&src 2>; + bypass_reset = <0>; ipu_di0: port@2 { reg = <2>; @@ -201,6 +205,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; + dmas = <&sdma 6 7 0>, <&sdma 7 7 0>; + dma-names = "rx", "tx"; reg = <0x70010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, @@ -247,6 +253,17 @@ bus-width = <4>; status = "disabled"; }; + + hs_i2c1: hs-i2c@70038000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-hsi2c"; + reg = <0x70038000 0x4000>; + interrupts = <64>; + clocks = <&clks IMX5_CLK_HSI2C_IPG_GATE>, <&clks IMX5_CLK_HSI2C_GATE>; + clock-names = "ipg", "serial"; + status = "disabled"; + }; }; usbotg: usb@73f80000 { diff --git a/arch/arm/boot/dts/imx6dl-a.dts b/arch/arm/boot/dts/imx6dl-a.dts new file mode 100644 index 00000000000000..a3c6f4fd85e2b3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-a.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-a.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite a Board"; + compatible = "fsl,imx6dl-a", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-acl.dts b/arch/arm/boot/dts/imx6dl-acl.dts new file mode 100644 index 00000000000000..aace3fb6689882 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-acl.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-acl.dtsi" + +/ { + model = "Boundary Devices i.MX6 Solo ACL Board"; + compatible = "boundary,imx6dl-acl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-ap.dts b/arch/arm/boot/dts/imx6dl-ap.dts new file mode 100644 index 00000000000000..33f8d88d23c3b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-ap.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2017 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-ap.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite ap Board"; + compatible = "fsl,imx6dl-ap", "fsl,imx6dl"; +}; + +&hdmi_core { + ipu_id = <0>; +}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index d4c4a22db48882..926e4ee13c1e00 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -3,6 +3,8 @@ * * Copyright (C) 2014 Heiko Schocher * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -30,39 +32,19 @@ memory { reg = <0x10000000 0x40000000>; }; +}; - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 480x800p60 { - native-mode; - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <59>; - hback-porch = <10>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; +&mxcfb1 { + status = "okay"; +}; - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - }; +&lcd { + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; }; &ecspi2 { @@ -80,10 +62,6 @@ status = "okay"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 15203f0e9725cb..bad1e22b6bd772 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -3,6 +3,8 @@ * * Copyright (C) 2014 Heiko Schocher * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -20,38 +22,6 @@ reg = <0x10000000 0x40000000>; }; - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <33246000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <88>; - hback-porch = <88>; - hsync-len = <80>; - vback-porch = <10>; - vfront-porch = <10>; - vsync-len = <25>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm3 0 3000>; @@ -62,6 +32,19 @@ }; }; +&mxcfb1 { + status = "okay"; +}; + +&lcd { + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -69,10 +52,6 @@ status = "okay"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &pwm3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-ash.dts b/arch/arm/boot/dts/imx6dl-ash.dts new file mode 100644 index 00000000000000..6f202f5bfe3495 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-ash.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2016 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-ash.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite Ash Board"; + compatible = "fsl,imx6dl-ash", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-ash2.dts b/arch/arm/boot/dts/imx6dl-ash2.dts new file mode 100644 index 00000000000000..64cacdde26e9cd --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-ash2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2016 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-ash2.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite Ash2 Board"; + compatible = "fsl,imx6dl-ash2", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-bt.dts b/arch/arm/boot/dts/imx6dl-bt.dts new file mode 100644 index 00000000000000..d2c9e9da96e1a5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-bt.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-bt.dtsi" + +/ { + model = "Freescale i.MX6 DualLite BT Board"; + compatible = "fsl,imx6dl-bt", "fsl,imx6dl"; +}; + +&gs2971 { + ipu = <0>; +}; + +&pinctrl_gs2971 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0xb0b1 + MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0xb0b1 + MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0xb0b1 + MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0xb0b1 + MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0xb0b1 + MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0xb0b1 + MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0xb0b1 + MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0xb0b1 + MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0xb0b1 + MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0xb0b1 + MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0xb0b1 + MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0xb0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0xb0b0 /* DATA_EN not used */ + >; +}; + +&pinctrl_gs2971_cea861 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; + +&v4l2_cap_0 { + ipu_id = <0>; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts new file mode 100644 index 00000000000000..35887eacf886f9 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts new file mode 100644 index 00000000000000..98c9ba8260c022 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts index 2a43917d048e8a..bddd0194c3944a 100644 --- a/arch/arm/boot/dts/imx6dl-cubox-i.dts +++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts @@ -41,7 +41,12 @@ /dts-v1/; #include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif / { model = "SolidRun Cubox-i Solo/DualLite"; diff --git a/arch/arm/boot/dts/imx6dl-hl.dts b/arch/arm/boot/dts/imx6dl-hl.dts new file mode 100644 index 00000000000000..a416887238cb89 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hl.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-hl.dtsi" + +/ { + model = "Freescale i.MX6 hl Board"; + compatible = "fsl,imx6dl-hl", "fsl,imx6dl", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hp.dts b/arch/arm/boot/dts/imx6dl-hp.dts new file mode 100644 index 00000000000000..1d45484e4b54d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hp.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2016 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-hp.dtsi" + +/ { + model = "Freescale i.MX6 DualLite hp Board"; + compatible = "fsl,imx6dl-hp", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts new file mode 100644 index 00000000000000..48bb5f4d3f4dbc --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts new file mode 100644 index 00000000000000..c5ca8d5f909f21 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index d5c96603196270..2093bbcb8a89f7 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -42,7 +42,12 @@ /dts-v1/; #include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif / { model = "SolidRun HummingBoard Solo/DualLite"; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts new file mode 100644 index 00000000000000..f14bcf491926df --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,59 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts new file mode 100644 index 00000000000000..2d0b6feccabe77 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts @@ -0,0 +1,58 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/imx6dl-hummingboard2.dts new file mode 100644 index 00000000000000..2ff27b932306c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-hummingboard2.dts @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-lshore.dts b/arch/arm/boot/dts/imx6dl-lshore.dts new file mode 100644 index 00000000000000..870af214fe19e0 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-lshore.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-lshore.dtsi" + +/ { + model = "Freescale i.MX6 Solo L-Shore Board"; + compatible = "fsl,imx6dl-lshore", "fsl,imx6dl", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mcs.dts b/arch/arm/boot/dts/imx6dl-mcs.dts new file mode 100644 index 00000000000000..2d4ebed2619d16 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mcs.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-mcs.dtsi" + +/ { + model = "Freescale i.MX6 DualLite MCS Board"; + compatible = "fsl,imx6dl-mcs", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mtp.dts b/arch/arm/boot/dts/imx6dl-mtp.dts new file mode 100644 index 00000000000000..9344ed4eea1c92 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mtp.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-mtp.dtsi" + +/ { + model = "Freescale i.MX6 DualLite MTP Board"; + compatible = "fsl,imx6dl-mtp", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-neol.dts b/arch/arm/boot/dts/imx6dl-neol.dts new file mode 100644 index 00000000000000..fac8e04145936c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-neol.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-neol.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite neol Board"; + compatible = "fsl,imx6dl-neol", "fsl,imx6dl"; +}; + +&hdmi_core { + ipu_id = <0>; +}; diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite-access.dts b/arch/arm/boot/dts/imx6dl-nit6xlite-access.dts new file mode 100644 index 00000000000000..318e24061e8c9e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nit6xlite-access.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nit6xlite.dtsi" + +/ { + model = "Freescale i.MX6 Solo Nit6x-Lite access control Board"; + compatible = "fsl,imx6dl-nit6xlite", "fsl,imx6dl", "fsl,imx6q"; +}; + +ðphy { + /delete-property/ reg; +}; \ No newline at end of file diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts new file mode 100644 index 00000000000000..5fe14bba2bd6da --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6 Max Board"; + compatible = "fsl,imx6dl-nitrogen6_max", "fsl,imx6dl"; +}; + +&hdmi_core { + ipu_id = <0>; +}; + +&ov5640 { + ipu_id = <0>; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_som2.dts new file mode 100644 index 00000000000000..04c7579e856a99 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_som2.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6 som2 Board"; + compatible = "fsl,imx6dl-nitrogen6_som2", "fsl,imx6dl"; +}; + +&hdmi_core { + ipu_id = <0>; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_vm-magstripe.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_vm-magstripe.dts new file mode 100644 index 00000000000000..9b0963c6374f20 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_vm-magstripe.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_vm.dtsi" + +/ { + model = "Freescale i.MX6 Solo Nitrogen6_vm Board with Magstripe reader"; + compatible = "fsl,imx6dl-nitrogen6_vm", "fsl,imx6dl", "fsl,imx6q"; +}; + +&magstripe { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_vm-pt.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_vm-pt.dts new file mode 100644 index 00000000000000..c7769b53e33384 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_vm-pt.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_vm.dtsi" + +/ { + model = "Freescale i.MX6 Solo Nitrogen6_vm Board"; + compatible = "fsl,imx6dl-nitrogen6_vm", "fsl,imx6dl", "fsl,imx6q"; + sas: sas@021ec000 { + compatible = "boundary,sas"; + reg = <0x021ec000 0x4000>; + interrupt-parent = <&gpc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + status = "okay"; + baud = <19200>; + interbyte_delay = <5>; + rxbufsize = <4096>; + txbufsize = <4096>; + maxtxmsg = <512>; + flush_on_mark = <0>; + }; +}; + +&magstripe { + status = "okay"; +}; + +&uart3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_vm.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_vm.dts new file mode 100644 index 00000000000000..7b1f06387bcadc --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_vm.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_vm.dtsi" + +/ { + model = "Freescale i.MX6 Solo Nitrogen6_vm Board"; + compatible = "fsl,imx6dl-nitrogen6_vm", "fsl,imx6dl", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts index 8398f979b9129a..d19614e72a9779 100644 --- a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts @@ -42,6 +42,8 @@ */ /dts-v1/; + +#include #include "imx6dl.dtsi" #include "imx6qdl-nitrogen6x.dtsi" @@ -49,3 +51,54 @@ model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; }; + +&adv7180 { + ipu_id = <0>; + csi_id = <1>; +}; + +&hdmi_core { + ipu_id = <0>; +}; + +&ov5640 { + ipu_id = <0>; +}; + +&pinctrl_i2c3_adv7180 { + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + >; +}; + +&pinctrl_i2c3_adv7180_cea861 { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-per.dts b/arch/arm/boot/dts/imx6dl-per.dts new file mode 100644 index 00000000000000..6dd1fa1c95c616 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-per.dts @@ -0,0 +1,61 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-per.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Per Board"; + compatible = "fsl,imx6dl-per", "fsl,imx6dl"; +}; + +&gs2971 { + ipu = <0>; +}; + +&pinctrl_gs2971 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0xb0b1 + MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0xb0b1 + MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0xb0b1 + MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0xb0b1 + MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0xb0b1 + MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0xb0b1 + MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0xb0b1 + MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0xb0b1 + MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0xb0b1 + MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0xb0b1 + MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0xb0b1 + MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0xb0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0xb0b1 /* DATA_EN not used */ + >; +}; + +&pinctrl_gs2971_cea861 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-rc.dts b/arch/arm/boot/dts/imx6dl-rc.dts new file mode 100644 index 00000000000000..e9708a32044508 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-rc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-rc.dtsi" + +/ { + model = "Freescale i.MX6 DualLite RC Board"; + compatible = "fsl,imx6dl-rc", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 75d73437adf7ee..1e7437c9ca309c 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -1,6 +1,8 @@ /* * Copyright 2014 Iain Paton * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -15,6 +17,10 @@ model = "RIoTboard i.MX6S"; compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; + aliases { + mxcfb0 = &mxcfb1; + }; + memory { reg = <0x10000000 0x40000000>; }; @@ -82,6 +88,17 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -101,8 +118,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -220,6 +244,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c4 { diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..45ae162836277e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts b/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts new file mode 100644 index 00000000000000..906d1d9bcda0ce --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mlb { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..f101f7c7b7b0df --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..ad2e937d4ffaac --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index a6ce7b487ad72f..bd13b359209117 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -15,3 +15,17 @@ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts new file mode 100644 index 00000000000000..814c93530a76c5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts b/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts new file mode 100644 index 00000000000000..ff4144113d5a04 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x04>, <&gpc 0 119 0x04>; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts new file mode 100644 index 00000000000000..2c7f04456cbbad --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts b/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts new file mode 100644 index 00000000000000..e5c623d85e4e35 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 1e45f2f9d0b6bc..fb402e56f9757a 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,3 +15,138 @@ model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; + +&battery { + offset-charger = <1485>; + offset-discharger = <1464>; + offset-usb-charger = <1285>; +}; + +&iomuxc { + epdc { + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000 + MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000 + MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000 + MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000 + MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000 + MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000 + MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000 + MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000 + MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000 + MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000 + MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000 + MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000 + MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000 + MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000 + MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000 + MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000 + MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000 + MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000 + MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000 + MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000 + >; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&i2c3 { + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <1>; + vpos_pwrup = <2>; + gvdd_pwrup = <1>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <1>; + vneg_pwrdn = <1>; + SENSOR-supply = <®_sensor>; + gpio_pmic_pwrgood = <&gpio2 21 0>; + gpio_pmic_vcom_ctrl = <&gpio3 17 0>; + gpio_pmic_wakeup = <&gpio3 20 0>; + gpio_pmic_v3p3 = <&gpio2 20 0>; + gpio_pmic_intr = <&gpio2 25 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-sp.dts b/arch/arm/boot/dts/imx6dl-sp.dts new file mode 100644 index 00000000000000..79efa5511c23cd --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-sp.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-sp.dtsi" + +/ { + model = "Freescale i.MX6 Solo SP Board"; + compatible = "fsl,imx6dl-sp", "fsl,imx6dl", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index 063fe7510da5f7..c6eba8ff33c71a 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 0>; @@ -73,39 +69,15 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; + }; }; &can1 { @@ -116,10 +88,6 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index b7a72840b7f0c7..34cb356b85f65c 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6U-801x Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; @@ -73,135 +69,14 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; + }; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 7aa120fbdc71ea..722d8e18f9b503 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -43,9 +43,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -59,10 +63,60 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@00900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, + <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, + <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m"; + interrupts = <0 107 0x04>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x0 0x0>, <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + power-domains = <&gpc 1>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; @@ -71,14 +125,28 @@ compatible = "fsl,imx6dl-iomuxc"; }; + dcic2: dcic@020e8000 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; + }; + pxp: pxp@020f0000 { + compatible = "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { + compatible = "fsl,imx6dl-epdc"; reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "epdc_axi", "epdc_pix"; + status = "disabled"; }; lcdif: lcdif@020f8000 { @@ -88,6 +156,16 @@ }; aips2: aips-bus@02100000 { + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; @@ -173,14 +251,31 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel", + "choice0", "choice1", + "choice2", "choice3", + "di0_pll", "di1_pll"; }; &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; + +&vpu_fsl { + iramsize = <0>; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-btwifi-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-btwifi-fix-ldo.dts new file mode 100644 index 00000000000000..d29e57254a5458 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-btwifi-fix-ldo.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-evb-fix-ldo.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-enetirq-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-enetirq-fix-ldo.dts new file mode 100644 index 00000000000000..a6630d32e71f3e --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-enetirq-fix-ldo.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-evb-fix-ldo.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x04>, <&intc 0 119 0x04>; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts new file mode 100644 index 00000000000000..1013cf7d399754 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-fix-ldo.dts @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd-ldo.dts" + +/ { + model = "Freescale i.MX6D SCM EVB"; + compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; + memory: memory { + linux,usable-memory = <0x10000000 0x20000000 + 0x80000000 0x20000000>; + }; + soc { + busfreq { + fsl,max_ddr_freq = <400000000>; + status = "okay"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 140>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "mmdc"; + }; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 0>; + internal_scm_flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + ov564x: ov564x@3c { + DOVDD-supply = <&sw4_reg>; /* 1.8v */ + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH1_AXI>; +}; + +&i2c2 { + pmic: pfuze100@08 { + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ov564x_mipi: ov564x_mipi@3c { + DOVDD-supply = <&sw4_reg>; /* 1.8v */ + }; + +}; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabresd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-hdcp-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-hdcp-fix-ldo.dts new file mode 100644 index 00000000000000..4bb67eab0aaa19 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-hdcp-fix-ldo.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-evb-fix-ldo.dts" + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts new file mode 100644 index 00000000000000..5136cd77ed4b12 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-evb-interleave-android-ldo.dts @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd-ldo.dts" + +/ { + model = "Freescale i.MX6D SCM EVB"; + compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; + soc { + busfreq { + fsl,max_ddr_freq = <400000000>; + status = "okay"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 140>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "mmdc"; + }; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 0>; + internal_scm_flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + ov564x: ov564x@3c { + DOVDD-supply = <&sw4_reg>; /* 1.8v */ + }; +}; + +&i2c2 { + pmic: pfuze100@08 { + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ov564x_mipi: ov564x_mipi@3c { + DOVDD-supply = <&sw4_reg>; /* 1.8v */ + }; + +}; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabresd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + }; +}; + diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-fix.dtsi b/arch/arm/boot/dts/imx6dqscm-1gb-fix.dtsi new file mode 100644 index 00000000000000..606d361aae180e --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-fix.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + memory: memory { + linux,usable-memory = <0x10000000 0x20000000 + 0x80000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-interleave-android.dtsi b/arch/arm/boot/dts/imx6dqscm-1gb-interleave-android.dtsi new file mode 100644 index 00000000000000..6edda09a996757 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-interleave-android.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + memory: memory { + linux,usable-memory = <0x10000000 0x40000000>; + }; + +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts new file mode 100644 index 00000000000000..436a90d8045d3c --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dqscm-qwks-rev2.dtsi" +#include "imx6dqscm-1gb-fix.dtsi" + +/ { + model = "Freescale i.MX6DQ SCM QWKS"; + compatible = "fsl,imx6q"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-hdcp-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-hdcp-fix-ldo.dts new file mode 100644 index 00000000000000..4aafc0deb1628b --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-hdcp-fix-ldo.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-qwks-rev2-fix-ldo.dts" + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-interleave-android-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-interleave-android-ldo.dts new file mode 100644 index 00000000000000..65734218691c59 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-interleave-android-ldo.dts @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dqscm-qwks-rev2.dtsi" +#include "imx6dqscm-1gb-interleave-android.dtsi" + +/ { + model = "Freescale i.MX6DQ SCM QWKS"; + compatible = "fsl,imx6q"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-wifi-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-wifi-fix-ldo.dts new file mode 100644 index 00000000000000..16171a23fa2716 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-wifi-fix-ldo.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-qwks-rev2-fix-ldo.dts" +#include "imx6dqscm-qwks-wifi.dtsi" diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts new file mode 100644 index 00000000000000..d376141dcb7a7f --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-qwks-rev3-fix-ldo.dts" +#include "imx6dqscm-qwks-rev3-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts new file mode 100644 index 00000000000000..3a42eaa538ef8e --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-qwks-rev2-fix-ldo.dts" + +/ { + regulators { + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + enable-active-high; + }; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; +}; + +&i2c2 { + ov564x_mipi: ov564x_mipi@3c { + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 201>; + clock-names = "csi_mclk"; + DOVDD-supply = <&sw4_reg>; + AVDD-supply = <&vgen3_reg>; + DVDD-supply = <&vgen2_reg>; + pwn-gpios = <&gpio1 19 1>; + rst-gpios = <&gpio1 20 0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam>; + }; + + pmic: pfuze100@08 { + regulators { + vgen5_reg: vgen5 { + regulator-max-microvolt = <2500000>; + }; + }; + }; +}; + +&i2c3 { + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + wakeup-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&mipi_csi { + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +}; + +&usdhc3 { + cd-gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 12 0>; + fsl,magic-packet; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF >; + assigned-clock-rates = <50000000>; + status = "okay"; +}; + +&iomuxc { + imx6dqscm-cam { + pinctrl_cam: camgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13069 + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x13069 + >; + }; + }; + + imx6qdl-sabresd { + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x17059 + >; + }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts new file mode 100644 index 00000000000000..1a789fe21858a4 --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dqscm-1gb-qwks-rev3-fix-ldo.dts" + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-qwks-rev2.dtsi b/arch/arm/boot/dts/imx6dqscm-qwks-rev2.dtsi new file mode 100644 index 00000000000000..361fe62d067aac --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-qwks-rev2.dtsi @@ -0,0 +1,610 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + soc { + busfreq { + fsl,max_ddr_freq = <400000000>; + status = "okay"; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + }; + }; + + chosen { + stdout-path = &uart1; + }; + + memory: memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + }; + }; + +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_pu { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH1_AXI>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 30 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 2>; + wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + }; + +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <7 2>; + wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabresd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + >; + }; + + pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 + >; + }; + + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi b/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi new file mode 100644 index 00000000000000..dc41db6b1517cb --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio6 5 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + gpios = <&gpio6 4 0>; /* WL_HOST_WAKE */ + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4 + &pinctrl_bt>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; +}; + +&iomuxc { + imx6dqscm-murata-v2 { + pinctrl_bt: btgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x13069 + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x13069 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x13069 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x13069 + >; + }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1f0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1f0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dqscm-qwks-wifi.dtsi b/arch/arm/boot/dts/imx6dqscm-qwks-wifi.dtsi new file mode 100644 index 00000000000000..bafca7465bb22a --- /dev/null +++ b/arch/arm/boot/dts/imx6dqscm-qwks-wifi.dtsi @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 30 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + }; +}; + +&iomuxc { + imx6qdl-sabresd-murata-v2 { + /* add MUXing entry for SD2 4-bit interface + * and configure control pins + */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x13069 + >; + }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1f0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1f0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x13069 + >; + }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /*pinctrl-0 = <&pinctrl_uart2dte>; */ +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; +}; diff --git a/arch/arm/boot/dts/imx6q-acl.dts b/arch/arm/boot/dts/imx6q-acl.dts new file mode 100644 index 00000000000000..cf032f375b93f6 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-acl.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-acl.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad ACL Board"; + compatible = "boundary,imx6q-acl", "fsl,imx6q"; +}; + +&iomuxc_imx6q_acl { + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 + MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x000b1 +#define GP_ECSPI5_NOR_CS <&gpio1 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x0b0b1 + >; + }; +}; + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI5_NOR_CS; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-ap.dts b/arch/arm/boot/dts/imx6q-ap.dts new file mode 100644 index 00000000000000..d490f196be9405 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ap.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2017 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-ap.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad ap Board"; + compatible = "fsl,imx6q-ap", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-arm2-hsic.dts b/arch/arm/boot/dts/imx6q-arm2-hsic.dts new file mode 100644 index 00000000000000..10c95ad9676147 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-arm2-hsic.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q-arm2.dts" + +&fec { + status = "disabled"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_1>; + pinctrl-1 = <&pinctrl_usbh2_2>; + osc-clkgate-delay = <0x3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 4989d0bff10f16..7793d73839e690 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -62,6 +62,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; status = "disabled"; /* gpmi nand conflicts with SD */ + nand-on-flash-bbt; }; &iomuxc { @@ -140,6 +141,32 @@ >; }; + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -194,6 +221,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-bt.dts b/arch/arm/boot/dts/imx6q-bt.dts new file mode 100644 index 00000000000000..072656308326d0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bt.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-bt.dtsi" + +/ { + model = "Freescale i.MX6 Quad BT Board"; + compatible = "fsl,imx6q-bt", "fsl,imx6q"; +}; + +&gs2971 { + ipu = <1>; +}; + +&pinctrl_gs2971 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0xb0b1 + MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0xb0b1 + MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0xb0b1 + MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0xb0b1 + MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0xb0b1 + MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0xb0b1 + MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0xb0b1 + MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0xb0b1 + MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0xb0b1 + MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0xb0b1 + MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0xb0b1 + MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0xb0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0xb0b0 /* DATA_EN not used */ + >; +}; + +&pinctrl_gs2971_cea861 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&v4l2_cap_0 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-bt2.dts b/arch/arm/boot/dts/imx6q-bt2.dts new file mode 100644 index 00000000000000..7e11d3eff9e24e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bt2.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-bt2.dtsi" + +/ { + model = "Freescale i.MX6 Quad BT2 Board"; + compatible = "fsl,imx6q-bt", "fsl,imx6q"; +}; + +&gs2971 { + ipu = <1>; +}; + +&pinctrl_ecspi3_gs2971 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0xb0b1 + MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0xb0b1 + MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0xb0b1 + MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0xb0b1 + MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0xb0b1 + MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0xb0b1 + MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0xb0b1 + MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0xb0b1 + MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0xb0b1 + MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0xb0b1 + MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0xb0b1 + MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0xb0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0xb0b0 /* DATA_EN not used */ + >; +}; + +&pinctrl_ecspi3_gs2971_cea861 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&v4l2_cap_0 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-cid.dts b/arch/arm/boot/dts/imx6q-cid.dts new file mode 100644 index 00000000000000..72b2a57cde6ebc --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cid.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-cid.dtsi" + +/ { + model = "Freescale i.MX6 Quad CID Board"; + compatible = "fsl,imx6q-cid", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-cid_tab.dts b/arch/arm/boot/dts/imx6q-cid_tab.dts new file mode 100644 index 00000000000000..de3539207395cf --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cid_tab.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" + +&iomuxc { + iomuxc_imx6q_cid_tab: iomuxc-imx6q-cid_tabgrp { + }; +}; + +&iomuxc_imx6q_cid_tab { + pinctrl_i2c2_ov5640: i2c2-ov5640grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x1b0b0 + MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x1b0b0 +/* Also used with ov5640 mipi */ +/* MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 */ +#define GP_OV5640_STROBE <&gpio2 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x030b0 +#define GP_OV5640_POWER_DOWN <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0b0b0 +#define GP_OV5640_RESET <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x030b0 + >; + }; +}; + +#include "imx6qdl-cid_tab.dtsi" +/ { + model = "Freescale i.MX6 Quad CID TAB Board"; + compatible = "fsl,imx6q-cid_tab", "fsl,imx6q"; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&v4l2_cap_1 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-cnt.dts b/arch/arm/boot/dts/imx6q-cnt.dts new file mode 100644 index 00000000000000..d47925199aa589 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cnt.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-cnt.dtsi" + +/ { + model = "Freescale i.MX6 Quad CNT Board"; + compatible = "fsl,imx6q-cnt", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-cob.dts b/arch/arm/boot/dts/imx6q-cob.dts new file mode 100644 index 00000000000000..a87e2a1e287e80 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cob.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-cob.dtsi" + +/ { + model = "Freescale i.MX6 Quad Cob Board"; + compatible = "fsl,imx6q-cob", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-cob2.dts b/arch/arm/boot/dts/imx6q-cob2.dts new file mode 100644 index 00000000000000..14c5a56c0d7a9c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cob2.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-cob2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Cob2 Board"; + compatible = "boundary,imx6q-cob2", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts new file mode 100644 index 00000000000000..9e652f11d677c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts new file mode 100644 index 00000000000000..65ad5e6e77605c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts index 353425edcdf4d4..212915fae478cb 100644 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ b/arch/arm/boot/dts/imx6q-cubox-i.dts @@ -41,7 +41,13 @@ /dts-v1/; #include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-cubox-i.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-cubox-i-vendor.dtsi" +#endif + / { model = "SolidRun Cubox-i Dual/Quad"; diff --git a/arch/arm/boot/dts/imx6q-eo.dts b/arch/arm/boot/dts/imx6q-eo.dts new file mode 100644 index 00000000000000..5a37e34a7cafdd --- /dev/null +++ b/arch/arm/boot/dts/imx6q-eo.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-eo.dtsi" + +/ { + model = "Freescale i.MX6 Quad EO Board"; + compatible = "fsl,imx6q-eo", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index b715deb4ea4666..b27b8aad987cc2 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -1,6 +1,8 @@ /* * Copyright (C) 2013 Philipp Zabel * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. @@ -14,6 +16,10 @@ model = "Zealz GK802"; compatible = "zealz,imx6q-gk802", "fsl,imx6q"; + aliases { + mxcfb0 = &mxcfb1; + }; + chosen { stdout-path = &uart4; }; @@ -47,10 +53,28 @@ wakeup-source; }; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -74,6 +98,11 @@ pinctrl-0 = <&pinctrl_i2c3>; clock-frequency = <100000>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 747bc104ad00b8..7c39985dd72964 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -1,6 +1,8 @@ /* * Copyright 2013 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -30,6 +32,7 @@ spi0 = &ecspi1; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -129,6 +132,17 @@ mux-int-port = <1>; mux-ext-port = <4>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -159,8 +173,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -332,6 +353,11 @@ VDDIO-supply = <®_3p3v>; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 65e66f994f8881..73839f3c10004d 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -42,8 +42,8 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" / { model = "Auvidea H100"; diff --git a/arch/arm/boot/dts/imx6q-h4.dts b/arch/arm/boot/dts/imx6q-h4.dts new file mode 100644 index 00000000000000..791acf2a6198c9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-h4.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-h4.dtsi" + +/ { + model = "Freescale i.MX6 Quad H4 Board"; + compatible = "fsl,imx6q-h4", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-hp.dts b/arch/arm/boot/dts/imx6q-hp.dts new file mode 100644 index 00000000000000..351ad7a10770f7 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hp.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2016 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-hp.dtsi" + +/ { + model = "Freescale i.MX6 Quad hp Board"; + compatible = "fsl,imx6q-hp", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts new file mode 100644 index 00000000000000..d9f5bf438d57c5 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts new file mode 100644 index 00000000000000..17051c6a2598c9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts index 1884c16784e2fd..6f230265854a04 100644 --- a/arch/arm/boot/dts/imx6q-hummingboard.dts +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -42,7 +42,12 @@ /dts-v1/; #include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" #include "imx6qdl-hummingboard.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-vendor.dtsi" +#endif / { model = "SolidRun HummingBoard Dual/Quad"; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts new file mode 100644 index 00000000000000..72f6f76f07dc6d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,67 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts new file mode 100644 index 00000000000000..314c2fed2e8a0b --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts @@ -0,0 +1,66 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/imx6q-hummingboard2.dts new file mode 100644 index 00000000000000..464b993ba33c03 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard2.dts @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" +#ifdef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard2-vendor.dtsi" +#endif + +/ { + model = "SolidRun HummingBoard2 Dual/Quad"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/imx6q-insp.dts b/arch/arm/boot/dts/imx6q-insp.dts new file mode 100644 index 00000000000000..d8d057eaaa3914 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-insp.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-insp.dtsi" + +/ { + model = "Freescale i.MX6 Quad INSP Board"; + compatible = "fsl,imx6q-insp", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-ioc.dts b/arch/arm/boot/dts/imx6q-ioc.dts new file mode 100644 index 00000000000000..1d0940749dd093 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ioc.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-ioc.dtsi" + +/ { + model = "Freescale i.MX6 Quad IOC Board"; + compatible = "fsl,imx6q-ioc", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&ov5640_mipi { + ipu_id = <1>; + csi_id = <0>; +}; + +&sata { + status = "okay"; +}; + +/* ov5640_mipi */ +&v4l2_cap_1 { + ipu_id = <1>; + csi_id = <0>; + mipi_camera = <1>; +}; + +/* */ +&v4l2_cap_2 { + ipu_id = <1>; + csi_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-jlm.dts b/arch/arm/boot/dts/imx6q-jlm.dts new file mode 100644 index 00000000000000..0d1d751c7e4d3c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-jlm.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-jlm.dtsi" + +/ { + model = "Freescale i.MX6 Quad jlm Board"; + compatible = "fsl,imx6q-jlm", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-ls.dts b/arch/arm/boot/dts/imx6q-ls.dts new file mode 100644 index 00000000000000..f860eb9511e3a8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ls.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-ls.dtsi" + +/ { + model = "Freescale i.MX6 Quad LS Board"; + compatible = "fsl,imx6q-ls", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-mcs.dts b/arch/arm/boot/dts/imx6q-mcs.dts new file mode 100644 index 00000000000000..342ebfa9572f84 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mcs.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-mcs.dtsi" + +/ { + model = "Freescale i.MX6 Quad MCS Board"; + compatible = "fsl,imx6q-mcs", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-mtp.dts b/arch/arm/boot/dts/imx6q-mtp.dts new file mode 100644 index 00000000000000..a482acfc526214 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mtp.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-mtp.dtsi" + +/ { + model = "Freescale i.MX6 Quad MTP Board"; + compatible = "fsl,imx6q-mtp", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-neol-test.dts b/arch/arm/boot/dts/imx6q-neol-test.dts new file mode 100644 index 00000000000000..9444da4f779e23 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-neol-test.dts @@ -0,0 +1,123 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-neol.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad neol test Board"; + compatible = "fsl,imx6q-neol", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&pinctrl_hog { + fsl,pins = < +#define GP_5V_DLP_EN <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130b0 +#define GP_STDBY_MODE <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 +#define GP_DLPC_BOOTED <&gpio2 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_INIT_DONE <&gpio2 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_RESET <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_KILL <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +#define GP_MICRO_RESET <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + +#define GP_KEY_IO01 <&gpio4 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +#define GP_KEY_IO02 <&gpio4 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +#define GP_KEY_IO03 <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + +#define GP_KEY_IO07 <&gpio1 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GP_KEY_IO08 <&gpio2 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 +#define GP_KEY_IO09 <&gpio6 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 +#define GP_KEY_IO10 <&gpio2 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_KEY_IO11 <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + +#define GP_TP71 <&gpio1 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP72 <&gpio1 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP76 <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +#define GP_TP113 <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_TP114 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_TP116 <&gpio2 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_TP118 <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +#define GP_TP121 <&gpio3 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 +#define GP_TP122 <&gpio1 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x1b0b0 + + /* extra taken from disabled devices */ +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 +#define GP_I2C2_J14_PIN3 <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_I2C2_J14_PIN4 <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +#define GP_I2C2_J14_PIN5 <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +#define GP_UART4_TXD <&gpio5 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 +#define GP_UART4_RXD <&gpio5 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + +#define GP_ESCPI2_MISO <&gpio5 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x100b0 +#define GP_ESCPI2_MOSI <&gpio5 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x100b0 +#define GP_ESCPI2_SCLK <&gpio5 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x100b0 +#define GP_ECSPI2_CS0 <&gpio5 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; +}; + +&ecspi2 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-neol.dts b/arch/arm/boot/dts/imx6q-neol.dts new file mode 100644 index 00000000000000..34a51334e18822 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-neol.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-neol.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad neol Board"; + compatible = "fsl,imx6q-neol", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max-apex.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max-apex.dts new file mode 100644 index 00000000000000..182939b234a645 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max-apex.dts @@ -0,0 +1,172 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 Max-apex Board"; + compatible = "fsl,imx6q-nitrogen6_max", "fsl,imx6q"; +}; + +&iomuxc_imx6q_nitrogen6_max { + pinctrl_i2c2a_gt911: i2c2a_gt911grp { + fsl,pins = < +#define GPIRQ_GT911_2A <&gpio1 16 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT911_IRQ_2A <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +#define GP_GT911_RESET_2A <&gpio1 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x030b0 + >; + }; + + pinctrl_i2c2a_lp8860: i2c2a_lp8860grp { + fsl,pins = < +#define GP_LVDS2_LP8860_RESET <&gpio2 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x030b0 + >; + }; + + pinctrl_i2c3_gt911: i2c3_gt911grp { + fsl,pins = < +#define GPIRQ_GT911 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT911_IRQ <&gpio1 9 GPIO_ACTIVE_HIGH> +/* MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 */ +#undef GP_GT911_RESET +#define GP_GT911_RESET <&gpio1 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x030b0 + >; + }; + + pinctrl_i2c3_lp8860: i2c3_lp8860grp { + fsl,pins = < +#define GP_LVDS_LP8860_RESET <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x030b0 + >; + }; + +}; + +&backlight_lvds2 { + status = "disabled"; +}; + +&fb_hdmi { + status = "okay"; +}; + +&fb_lcd { + status = "okay"; +}; + +&fb_lvds { + status = "okay"; +}; + +&i2c2a { + /delete-node/ ft5x06_ts@38; + gt911@5d { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2a_gt911>; + reg = <0x5d>; + substitute-i2c-address = <0x2c>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911_2A; + irq-gpios = GP_GT911_IRQ_2A; + reset-gpios = GP_GT911_RESET_2A; + }; + + lp8860_backlight_lvds2@2d { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "lp8860-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2a_lp8860>; + reg = <0x2d>; + reset-gpios = GP_LVDS2_LP8860_RESET; + }; + +}; + +&i2c3 { + /delete-node/ atmel_maxtouch@4a; + /delete-node/ egalax_ts@04; + /delete-node/ ft5x06_ts@38; + /delete-node/ gt911@14; + /delete-node/ ili210x@41; + /delete-node/ tsc2004@48; + gt911@5d { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x5d>; + substitute-i2c-address = <0x2c>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; + + lp8860_backlight_lvds@2d { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "lp8860-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_lp8860>; + reg = <0x2d>; + reset-gpios = GP_LVDS_LP8860_RESET; + }; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&pwm2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max-lantech.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max-lantech.dts new file mode 100644 index 00000000000000..89b333c06a1c75 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max-lantech.dts @@ -0,0 +1,181 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6 Max lantech Board"; + compatible = "fsl,imx6q-nitrogen6_max", "fsl,imx6q"; +}; + +&iomuxc_imx6q_nitrogen6_max { + pinctrl_i2c1_dac: i2c1_dacgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1b_isl28022: i2c1b_isl28022 { + fsl,pins = < +#define GPIRQ_ISL28022 <&gpio5 28 IRQ_TYPE_LEVEL_LOW> +#define GP_ISL28022 <&gpio5 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1f0b0 + >; + }; +}; + +/ { + i2cmux@4 { + compatible = "i2c-mux-pinctrl"; + i2c-parent = <&i2c1>; + + pinctrl-names = "std", "dac"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_dac>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C3MUX_A; + idle-state = <0>; + + i2c1a: i2c1@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1b: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + regulators { + reg_isl76534: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "reg_isl76534"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + regulator-always-on; + }; + }; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&i2c1 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + /delete-node/ sgtl5000@0a; + /delete-node/ rv4162@68; +}; + +&i2c1a { + clock-frequency = <100000>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c1b { + clock-frequency = <10000>; + status = "okay"; + + isl28022@40 { + compatible = "isl28022"; + interrupts-extended = GPIRQ_ISL28022; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1b_isl28022>; + reg = <0x40>; + bus-voltage-max = <16>; /* 16/32/60 Volts for full range */ + shunt-voltage-max = <320>; /* 40/80/160/320 mV */ + bus-adc-cfg = <2>; /* 2 means 14-bit, 258 uSec */ + shunt-adc-cfg = <2>; /* 2 means 14-bit, 258 uSec */ + rshunt = <10>; /* ohms */ + }; + + isl76534@74 { + compatible = "isl76534"; + reg = <0x74>; + vref-supply = <®_isl76534>; + }; +}; + +&i2c2a { + /delete-node/ ov5642@3c; +}; + +&i2c2b { + /delete-node/ ov5640_mipi@3c; + /delete-node/ tc358743_mipi@0f; +}; + +&i2c3 { + /delete-node/ atmel_maxtouch@4a; + /delete-node/ egalax_ts@04; + /delete-node/ ft5x06_ts@38; + /delete-node/ gt911@14; + /delete-node/ gt911@5d; + /delete-node/ ili210x@41; + /delete-node/ ov5640@3c; + /delete-node/ tsc2004@48; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max-st7789.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max-st7789.dts new file mode 100644 index 00000000000000..9dc707fed4d562 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max-st7789.dts @@ -0,0 +1,136 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +&iomuxc_imx6q_nitrogen6_max { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +#define GP_ECSPI2_DISPLAY_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_ecspi2_st7789: ecspi2_st7789grp { + fsl,pins = < +#define GPIRQ_ST7789_TEARING_EFFECT <&gpio5 30 IRQ_TYPE_EDGE_RISING> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x0b0b1 + >; + }; + + pinctrl_ecspi2_read: ecspi2_readgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x108b1 /* ODE, so that display can drive low */ + >; + }; + + pinctrl_ecspi2_write: ecspi2_writegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 /* Can write faster without ODE */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 + >; + }; +}; + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 Max st7789 Board"; + compatible = "fsl,imx6q-nitrogen6_max", "fsl,imx6q"; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_DISPLAY_CS; + pinctrl-names = "default", "write", "read"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_write>; + pinctrl-1 = <&pinctrl_ecspi2_write>; + pinctrl-2 = <&pinctrl_ecspi2_read>; + status = "okay"; +#if 0 + dma-names = "", ""; +#endif + + st7789h2@0{ + bpp = <16>; /* 16 or 24 */ + buswidth = <9>; + compatible = "sitronix,st7789v"; + display_fps = <40>; + height = <204>; +#if 1 + interrupts-extended = GPIRQ_ST7789_TEARING_EFFECT; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_st7789>; + reg = <0>; + regwidth = <8>; + rotate = <0>; + /* SCLK - write cycle 16 ns(62.5Mhz), read cycle 150 ns(6.6 MHz) */ + spi-max-frequency = <40000000>; + spi-max-read-frequency = <6600000>; + te-line = <320>; + txbufcnt = <4>; + txbuflen = <27648>; + width = <240>; + }; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&i2c2 { + /delete-node/ ov5642@3d; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts index d417457ca6dbea..d021fbc36a4b07 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts @@ -48,6 +48,35 @@ compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; }; +&hdmi_core { + ipu_id = <1>; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + &sata { status = "okay"; }; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2-ta.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2-ta.dts new file mode 100644 index 00000000000000..f60c22c36748b6 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2-ta.dts @@ -0,0 +1,347 @@ +/* + * Copyright 2015 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 SOM2 ta Board"; + compatible = "fsl,imx6q-nitrogen6_som2", "fsl,imx6q"; + /delete-node/ sound; + /delete-node/ gpio-keys; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; + +&iomuxc_imx6q_nitrogen6_som2 { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 + +#undef GP_ECSPI2_SS0 +#define GP_ECSPI2_SS0 <&gpio5 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + +#define GP_ECSPI2_MUX0 <&gpio3 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x030b0 +#define GP_ECSPI2_MUX1 <&gpio3 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x030b0 +#define GP_ECSPI2_MUX2 <&gpio3 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x030b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_MOTOR1 <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_MOTOR2 <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_MOTOR3 <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_MOTOR4 <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* LCD Display (4 Lines x 20 Characters) using GPIO */ +#define GP_DISP_DB0 <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b0 +#define GP_DISP_DB1 <&gpio3 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 +#define GP_DISP_DB2 <&gpio3 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x0b0b0 +#define GP_DISP_DB3 <&gpio3 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x0b0b0 +#define GP_DISP_DB4 <&gpio3 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x0b0b0 +#define GP_DISP_DB5 <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x0b0b0 +#define GP_DISP_DB6 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x0b0b0 +#define GP_DISP_DB7 <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x0b0b0 +#define GP_DISP_E <&gpio3 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x0b0b0 +#define GP_DISP_RS <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x0b0b0 +#define GP_DISP_RWn <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0b0b0 + + /* Stepper Motor Control Digital I/O */ +#define GP_MOTOR_START <&gpio2 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b0 +#define GP_MOTOR_STOPL <&gpio2 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0b0b0 +#define GP_MOTOR_STOPR <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0b0b0 +#define GP_MOTOR_N <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x0b0b0 + +#define GP_MOTOR_DIRECTION <&gpio3 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x0b0b0 +#define GP_MOTOR_HOME <&gpio3 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b0 +#define GP_MOTOR_FULL_STEP <&gpio3 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0b0b0 + + /* Heater Control Digital I/O */ +#define GP_HEATER_A_1 <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x0b0b0 +#define GP_HEATER_A_2 <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 +#define GP_HEATER_B_1 <&gpio1 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0b0b0 +#define GP_HEATER_B_2 <&gpio1 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x0b0b0 +#define GP_HEATER_C_1 <&gpio5 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x0b0b0 +#define GP_HEATER_C_2 <&gpio5 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0b0b0 + + /* Gas Valve Control Digital I/O */ +#define GP_GAS_PURGE <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x0b0b0 + + /* Status LEDs Digital I/O */ +#define GP_LED_RED <&gpio5 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0b0b0 +#define GP_LED_GREEN <&gpio5 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x0b0b0 +#define GP_LED_YELLOW <&gpio5 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0b0b0 + + /* Auto Feeder Digital I/O */ +#define GP_AF_1 <&gpio6 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0b0b0 +#define GP_AF_2 <&gpio6 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x0b0b0 +#define GP_AF_3 <&gpio6 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x0b0b0 +#define GP_AF_4 <&gpio6 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0b0b0 +#define GP_AF_5 <&gpio6 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x0b0b0 +#define GP_AF_6 <&gpio6 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0b0b0 +#define GP_AF_7 <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b0 +#define GP_AF_EN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b0 + MX6QDL_PAD_KEY_COL4__KEY_COL4 0x1b0b0 + MX6QDL_PAD_GPIO_0__KEY_COL5 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x1b0b0 + MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x1b0b0 + >; + }; + + pinctrl_keypad_sleep: keypad_sleepgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x030b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x030b0 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x030b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x030b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x030b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x030b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x030b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + +}; + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + event1 { + label = "event1"; + gpios = GP_GPIOKEY_MOTOR1; + linux,code = ; + gpio-key,wakeup; + }; + + event2 { + label = "event2"; + gpios = GP_GPIOKEY_MOTOR2; + linux,code = ; + gpio-key,wakeup; + }; + + event3 { + label = "event3"; + gpios = GP_GPIOKEY_MOTOR3; + linux,code = ; + gpio-key,wakeup; + }; + + event4 { + label = "event4"; + gpios = GP_GPIOKEY_MOTOR4; + linux,code = ; + gpio-key,wakeup; + }; + }; + +}; + +&ecspi2 { + cs-gpios = GP_ECSPI2_MUX0, GP_ECSPI2_MUX1, GP_ECSPI2_MUX2, GP_ECSPI2_SS0; + fsl,spi-num-chipselects = <4>; + idle-state = <15>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <1>; + }; + spidev@2 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <2>; + }; + spidev@3 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <3>; + }; + spidev@4 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <4>; + }; + spidev@5 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <5>; + }; + spidev@6 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <6>; + }; +}; + +&i2c1 { + /delete-node/ sgtl5000@0a; + /delete-node/ rv4162@68; +#if 0 + max5813@1f { + /* adc converter, To do */ + compatible = "max5813"; + reg = <0x1f>; + }; +#endif +}; + +&i2c2 { + status = "disabled"; + /delete-node/ edid@50; + /delete-node/ ov5640_mipi@3d; + /delete-node/ ov5642@3e; + /delete-node/ tc358743_mipi@0f; +}; + +&i2c3 { + /delete-node/ gt911@14; + /delete-node/ gt911@5d; + /delete-node/ ili210x@41; + /delete-node/ tsc2004@48; +}; + +&pcie { + status = "disabled"; +}; + +&kpp { + compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; + clocks = <&clks IMX6QDL_CLK_IPG>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_keypad>; + pinctrl-1 = <&pinctrl_keypad_sleep>; + linux,keymap = < + 0x05030201 /* KEY_NUMERIC_1(0x201) */ + 0x05040202 /* KEY_NUMERIC_2 */ + 0x05050203 /* KEY_NUMERIC_3 */ + 0x05060204 /* KEY_NUMERIC_4 */ + 0x06030205 /* KEY_NUMERIC_5 */ + 0x06040206 /* KEY_NUMERIC_6 */ + 0x06050207 /* KEY_NUMERIC_7 */ + 0x06060208 /* KEY_NUMERIC_8 */ + 0x07030209 /* KEY_NUMERIC_9 */ + 0x07040200 /* KEY_NUMERIC_0 */ + 0x07050001 /* KEY_ESC */ + 0x0706001c /* KEY_ENTER(28)(0x1c) */ + >; + status = "okay"; +}; + +&uart3 { + status = "disabled"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + /delete-property/ reset-gpios; +}; + +&usbotg { + disable-over-current; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts new file mode 100644 index 00000000000000..210b22c62efece --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2015 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 som2 Board"; + compatible = "fsl,imx6q-nitrogen6_som2", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x-careview.dts b/arch/arm/boot/dts/imx6q-nitrogen6x-careview.dts new file mode 100644 index 00000000000000..1d2d801a123c3a --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6x-careview.dts @@ -0,0 +1,167 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6x Board"; + compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&adv7180 { + ipu_id = <1>; + csi_id = <1>; +}; + +&fb_hdmi { + status = "disabled"; +}; + +&fb_lcd { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "adv739x"; + interface_pix_fmt = "BT656"; + mode_str ="BT656-NTSC"; + default_bpp = <16>; + di_msb = <7>; + int_clk = <0>; + late_init = <0>; + status = "okay"; +}; + +&fb_lvds { + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&ov5640_mipi { + ipu_id = <1>; + csi_id = <0>; +}; + +&iomuxc_imx6q_nitrogen6x { + pinctrl_i2c3_adv7391: i2c3-adv7391grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* Pixclk */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + >; + }; + + pinctrl_i2c3_adv7391_off: i2c3-adv7391-offgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0b0b0 /* Pixclk */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0b0b0 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0b0b0 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0b0 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b0b0 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0b0b0 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0b0b0 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0b0b0 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0b0b0 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x0b0b0 + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x0b0b0 +#define GP_ADV7391_RESET <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x030b0 /* reset */ + >; + }; +}; + +&i2c3 { + adv7391: adv7391@2a { + compatible = "adv,mxc_adv739x"; + reg = <0x2a>; + pinctrl-names = "default", "enable"; + pinctrl-0 = <&pinctrl_i2c3_adv7391_off>; + pinctrl-1 = <&pinctrl_i2c3_adv7391>; + rst-gpios = GP_ADV7391_RESET; + ipu_id = <0>; + disp_id = <0>; + }; +}; + +&lcd { + status = "disabled"; +}; + +&pinctrl_i2c3_adv7180 { + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + >; +}; + +&pinctrl_i2c3_adv7180_cea861 { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +/* ov5640_mipi */ +&v4l2_cap_1 { + ipu_id = <1>; + csi_id = <0>; + mipi_camera = <1>; +}; + +/* adv7180, ov5640 */ +&v4l2_cap_2 { + ipu_id = <1>; + csi_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x-st7789.dts b/arch/arm/boot/dts/imx6q-nitrogen6x-st7789.dts new file mode 100644 index 00000000000000..14dd7d1dd3e84e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6x-st7789.dts @@ -0,0 +1,190 @@ +/* + * Copyright 2013-2016 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +&iomuxc_imx6q_nitrogen6x { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 +#define GP_ECSPI2_DISPLAY_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_ecspi2_st7789: ecspi2_st7789grp { + fsl,pins = < +#define GPIRQ_ST7789_TEARING_EFFECT <&gpio5 30 IRQ_TYPE_EDGE_RISING> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x0b0b1 + >; + }; + + pinctrl_ecspi2_read: ecspi2_readgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x108b1 /* ODE, so that display can drive low */ + >; + }; + + pinctrl_ecspi2_write: ecspi2_writegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 /* Can write faster without ODE */ + >; + }; + + pinctrl_enet_gpio6: enet_gpio6grp { + fsl,pins = < +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /* Spare */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* Spare */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 + >; + }; +}; + +/ { + model = "Freescale i.MX6 Quad Nitrogen6x-st7789 Board"; + compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&adv7180 { + ipu_id = <1>; + csi_id = <1>; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_DISPLAY_CS; + pinctrl-names = "default", "write", "read"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_write>; + pinctrl-1 = <&pinctrl_ecspi2_write>; + pinctrl-2 = <&pinctrl_ecspi2_read>; + status = "okay"; +#if 0 + dma-names = "", ""; +#endif + + st7789h2@0{ + bpp = <16>; /* 16 or 24 */ + buswidth = <9>; + compatible = "sitronix,st7789v"; + display_fps = <40>; + height = <204>; +#if 1 + interrupts-extended = GPIRQ_ST7789_TEARING_EFFECT; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_st7789>; + reg = <0>; + regwidth = <8>; + rotate = <0>; + /* SCLK - write cycle 16 ns(62.5Mhz), read cycle 150 ns(6.6 MHz) */ + spi-max-frequency = <40000000>; + spi-max-read-frequency = <6600000>; + te-line = <320>; + txbufcnt = <4>; + txbuflen = <27648>; + width = <240>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_gpio6>; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&i2c2 { + /delete-node/ ov5642@3d; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&ov5640_mipi { + ipu_id = <1>; + csi_id = <0>; +}; + +&pinctrl_i2c3_adv7180 { + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + >; +}; + +&pinctrl_i2c3_adv7180_cea861 { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +/* ov5640_mipi */ +&v4l2_cap_1 { + ipu_id = <1>; + csi_id = <0>; + mipi_camera = <1>; +}; + +/* adv7180, ov5640 */ +&v4l2_cap_2 { + ipu_id = <1>; + csi_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts index d1686339dc480b..ba184ace4c03c3 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts @@ -1,5 +1,5 @@ /* - * Copyright 2013 Boundary Devices, Inc. + * Copyright 2013-2016 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * @@ -42,6 +42,8 @@ */ /dts-v1/; + +#include #include "imx6q.dtsi" #include "imx6qdl-nitrogen6x.dtsi" @@ -50,6 +52,75 @@ compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; }; +&adv7180 { + ipu_id = <1>; + csi_id = <1>; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&ov5640_mipi { + ipu_id = <1>; + csi_id = <0>; +}; + +&pinctrl_i2c3_adv7180 { + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + >; +}; + +&pinctrl_i2c3_adv7180_cea861 { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + &sata { status = "okay"; }; + +/* ov5640_mipi */ +&v4l2_cap_1 { + ipu_id = <1>; + csi_id = <0>; + mipi_camera = <1>; +}; + +/* adv7180, ov5640 */ +&v4l2_cap_2 { + ipu_id = <1>; + csi_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-nw2.dts b/arch/arm/boot/dts/imx6q-nw2.dts new file mode 100644 index 00000000000000..f69eb093a2d3ac --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nw2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-nw2.dtsi" + +/ { + model = "Freescale i.MX6 Quad NW2 Board"; + compatible = "fsl,imx6q-nw2", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-per.dts b/arch/arm/boot/dts/imx6q-per.dts new file mode 100644 index 00000000000000..d65ceaf9b0496b --- /dev/null +++ b/arch/arm/boot/dts/imx6q-per.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-per.dtsi" + +/ { + model = "Freescale i.MX6 Quad Per Board"; + compatible = "fsl,imx6q-per", "fsl,imx6q"; +}; + +&gs2971 { + ipu = <1>; +}; + +&pinctrl_gs2971 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0xb0b1 + MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0xb0b1 + MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0xb0b1 + MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0xb0b1 + MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0xb0b1 + MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0xb0b1 + MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0xb0b1 + MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0xb0b1 + MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0xb0b1 + MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0xb0b1 + MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0xb0b1 + MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0xb0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0xb0b1 /* DATA_EN not used */ + >; +}; + +&pinctrl_gs2971_cea861 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-pop-arm2.dts b/arch/arm/boot/dts/imx6q-pop-arm2.dts new file mode 100644 index 00000000000000..df6e2a329aa904 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pop-arm2.dts @@ -0,0 +1,437 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-pop-arm2", "fsl,imx6q"; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + }; + + pwm-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + power-supply = <®_lvds_3p3v>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 30 1>; + linux,code = <116>; + gpio-key,wakeup; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + linux,usable-memory = <0x10000000 0x20000000>, + <0x80000000 0x20000000>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str = "1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_lvds_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "LVDS-3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; +}; + +&cpu0 { + fsl,arm-soc-shared = <1>; +}; + +&busfreq { + fsl,max_ddr_freq = <400000000>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio3>; + interrupts = <31 2>; + wakeup-gpios = <&gpio3 31 0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + max7310_a: gpio@1b { + compatible = "maxim,max7310"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@1f { + compatible = "maxim,max7310"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu2-di0"; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + wp-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-s.dts b/arch/arm/boot/dts/imx6q-s.dts new file mode 100644 index 00000000000000..39bbf0e1daacd1 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-s.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-s.dtsi" + +/ { + model = "Freescale i.MX6 Quad s Board"; + compatible = "fsl,imx6q-s", "fsl,imx6q"; +}; + +&hdmi_core { + ipu_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..3cf99ed9be6b0c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts b/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts new file mode 100644 index 00000000000000..7acb794fbaa604 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mlb { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..71dd589448013f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..579aeb26e05dfd --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 334b9247e78cef..a321a20832df26 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -20,6 +20,26 @@ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; +&mxcfb3 { + status = "okay"; +}; +&mxcfb4 { + status = "okay"; +}; &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 66d10d8d534cca..0b79d7b2dc9f12 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -1,5 +1,6 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * This file is dual-licensed: you can use it either under the terms @@ -41,6 +42,8 @@ */ /dts-v1/; + +#include #include "imx6q.dtsi" #include "imx6qdl-sabrelite.dtsi" @@ -49,6 +52,75 @@ compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; }; +&adv7180 { + ipu_id = <1>; + csi_id = <1>; +}; + +&hdmi_core { + ipu_id = <1>; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&ov5640_mipi { + ipu_id = <1>; + csi_id = <0>; +}; + +&pinctrl_i2c3_adv7180 { + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + >; +}; + +&pinctrl_i2c3_adv7180_cea861 { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + &sata { status = "okay"; }; + +/* ov5640_mipi */ +&v4l2_cap_1 { + ipu_id = <1>; + csi_id = <0>; + mipi_camera = <1>; +}; + +/* adv7180, ov5640 */ +&v4l2_cap_2 { + ipu_id = <1>; + csi_id = <1>; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts new file mode 100644 index 00000000000000..af65f3ad76f8c1 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts b/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts new file mode 100644 index 00000000000000..69da4046a75b16 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x04>, <&gpc 0 119 0x04>; +}; + +&i2c3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts new file mode 100644 index 00000000000000..3116e3efb835fa --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2012-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd-ldo.dts b/arch/arm/boot/dts/imx6q-sabresd-ldo.dts new file mode 100644 index 00000000000000..8363302dca3548 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 9cbdfe7a0931ff..a63e1b66a6bb21 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012=2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -20,6 +20,38 @@ compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; +&battery { + offset-charger = <1900>; + offset-discharger = <1694>; + offset-usb-charger = <1685>; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-snap.dts b/arch/arm/boot/dts/imx6q-snap.dts new file mode 100644 index 00000000000000..a708ea1a787892 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-snap.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-snap.dtsi" + +/ { + model = "Freescale i.MX6 Quad Snap Board"; + compatible = "fsl,imx6q-snap", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-ta.dts b/arch/arm/boot/dts/imx6q-ta.dts new file mode 100644 index 00000000000000..f9297a01266df5 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ta.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-ta.dtsi" + +/ { + model = "Freescale i.MX6 Quad TA Board"; + compatible = "fsl,imx6q-ta", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 06f492e17ca70e..43ff8f5b04fe6f 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -1,6 +1,8 @@ /* * Copyright 2014 Soeren Moch * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a @@ -55,6 +57,10 @@ model = "TBS2910 Matrix ARM mini PC"; compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; + aliases { + mxcfb0 = &mxcfb1; + }; + chosen { stdout-path = &uart1; }; @@ -131,6 +137,17 @@ spdif-controller = <&spdif>; spdif-out; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -145,10 +162,21 @@ status = "okay"; }; -&hdmi { +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -174,6 +202,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index 65e95ae7509a45..2a129af46c737e 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 0>; @@ -73,39 +69,15 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; + }; }; &can1 { @@ -116,10 +88,6 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index 20cd0e7b3e2102..48e6d08f7a367f 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6Q-1010 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; @@ -73,135 +69,14 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; + }; - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 9ed243b704ff5c..51d8b010bafcd5 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 0>; @@ -73,39 +69,15 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; + }; }; &can1 { @@ -124,10 +96,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index 347b531d37637a..a3a87cc41295a1 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -47,10 +47,6 @@ model = "Ka-Ro electronics TX6Q-1020 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - aliases { - display = &display; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; @@ -73,133 +69,15 @@ default-brightness-level = <50>; }; - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; + }; }; &ds1339 { @@ -210,10 +88,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6q-usd.dts b/arch/arm/boot/dts/imx6q-usd.dts new file mode 100644 index 00000000000000..93da4528e985a0 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-usd.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2016 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-usd.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad usd Board"; + compatible = "fsl,imx6q-usd", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-usd_mr2.dts b/arch/arm/boot/dts/imx6q-usd_mr2.dts new file mode 100644 index 00000000000000..328de234e2b48f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-usd_mr2.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-usd_mr2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad usd_mr2 Board"; + compatible = "fsl,imx6q-usd_mr2", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-utc.dts b/arch/arm/boot/dts/imx6q-utc.dts new file mode 100644 index 00000000000000..d97868cb69b662 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-utc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-utc.dtsi" + +/ { + model = "Freescale i.MX6 Quad UTC Board"; + compatible = "fsl,imx6q-utc", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-vp.dts b/arch/arm/boot/dts/imx6q-vp.dts new file mode 100644 index 00000000000000..06bd587929c1f2 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-vp.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-vp.dtsi" + +/ { + model = "Freescale i.MX6 Quad VP Board"; + compatible = "fsl,imx6q-vp", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e9a5d0b8c7b059..c43b9a9ee7c14c 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -48,9 +48,15 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>, + <&clks IMX6QDL_CLK_VPU_AXI_PODF>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src", + "vpu_axi_podf"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -78,10 +84,58 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@00900000 { + busfreq: busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; + interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + fsl,max_ddr_freq = <528000000>; + }; + + gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; + reg = <0x00905000 0x3B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; @@ -107,6 +161,18 @@ }; }; + aips-bus@02100000 { /* AIPS2 */ + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + }; + sata: sata@02200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; @@ -137,9 +203,21 @@ <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, + <&clks IMX6QDL_CLK_LDB_DI1>, + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", + "540m", "video_pll"; + resets = <&src 4>; + bypass_reset = <0>; ipu2_csi0: port@0 { reg = <0>; @@ -267,13 +345,26 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel", + "choice0", "choice1", + "choice2", "choice3", + "di0_pll", "di1_pll"; lvds-channel@0 { port@2 { diff --git a/arch/arm/boot/dts/imx6qdl-a.dtsi b/arch/arm/boot/dts/imx6qdl-a.dtsi new file mode 100644 index 00000000000000..01392cde49761a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-a.dtsi @@ -0,0 +1,475 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_a: iomuxc-imx6q-agrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_a { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_S0_FACTORY_RESET <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +#define GP_J57_INPUT <&gpio6 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 +#define GP_S1_LOOPBACK <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_S1_DIAG1 <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +#define GP_S1_DIAG2 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +#define GP_S1_INPUT <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 /* Spare */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* Spare */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x130b0 /* Led0 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x130b0 /* Led1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 /* LedRed */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x130b0 /* Led2 */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* rxact */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* txact */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 15 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 +#define GP_UART3_RX_EN <&gpio2 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x030b0 /* RS485 RX Enable: pull down */ +#define GP_UART3_TX_EN <&gpio2 17 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x030b0 /* RS485 DEN: pull down */ +#define GP_UART3_RS485_EN <&gpio2 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x030b0 /* RS485/!RS232 Select: pull down (rs232) */ +#define GP_UART3_AON <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x030b0 /* ON: pull down */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 +#define GP_AX88772A_RESET <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0b0b0 +#define GP_MODEM_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b0 +#define GP_MODEM_OFF <&gpio2 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; +}; + +/ { + aliases { + i2c0 = &i2c2; + mmc0 = &usdhc4; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + factory_reset { + label = "factory reset"; + gpios = GP_S0_FACTORY_RESET; + linux,code = ; + }; + + j57_input { + label = "j57 input"; + gpios = GP_J57_INPUT; + linux,code = ; + }; + + s1_loop { + label = "s1 loop"; + gpios = GP_S1_LOOPBACK; + linux,code = ; + }; + + s1_diag { + label = "s1 diag"; + gpios = GP_S1_DIAG1; + linux,code = ; + gpio-key,wakeup; + }; + + s2_diag { + label = "s2 diag"; + gpios = GP_S1_DIAG2; + linux,code = ; + }; + + s1_input { + label = "s1 input"; + gpios = GP_S1_INPUT; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + control-gpios = GP_UART3_RX_EN, GP_UART3_TX_EN, GP_UART3_RS485_EN, GP_UART3_AON; +#define M_RX_EN 1 +#define M_TX_EN 2 +#define M_RS485 4 +#define M_AON 8 + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = ; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0xd>; + rs485_txen_mask = <0x3>; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; /* 1 to enable */ + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET, GP_AX88772A_RESET, GP_MODEM_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-acl.dtsi b/arch/arm/boot/dts/imx6qdl-acl.dtsi new file mode 100644 index 00000000000000..f2960ea3f90735 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-acl.dtsi @@ -0,0 +1,735 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_acl: iomuxc-imx6q-aclgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_acl { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_MOTOR0 <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 +#define GP_ECSPI2_MOTOR1 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b1 +#define GP_ECSPI2_OPTICS <&gpio1 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x0b0b0 + >; + }; + + pinctrl_ecspi2_lmp90079: ecspi2_lmp90079grp { + fsl,pins = < +#define GPIRQ_LMP90079 <&gpio7 1 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0b0b1 +#define GP_ECSPI4_DUMMY_CS0 <&gpio3 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Buzzer */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* Fan */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x130b0 + /* Motors */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x130b0 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x130b0 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x130b0 + /* motor control for CS0, STEP1_RESET */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b8b0 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x130b0 + /* motor control for CS1, STEP2_RESET */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b8b0 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x130b0 + /* Printer */ +#define GP_PRT_MOTOR_BDCAY <&gpio2 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_PRT_MOTOR_ADCAY <&gpio2 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_PRT_MOTOR_TOFF <&gpio2 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_PRT_MOTOR_ATE <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_PRT_MOTOR_SLEEP <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 +#define GP_PRT_MOTOR_B1 <&gpio2 17 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b0 +#define GP_PRT_MOTOR_B2 <&gpio2 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 +#define GP_PRT_MOTOR_A1 <&gpio6 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 +#define GP_PRT_MOTOR_A2 <&gpio5 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 +#define GP_PRT_STROBE1 <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 +#define GP_PRT_STROBE2 <&gpio3 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 +#define GP_PRT_STROBE3 <&gpio3 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GP_PRT_STROBE4 <&gpio3 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_PRT_STROBE5 <&gpio3 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GP_PRT_STROBE6 <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_PRT_LATCH <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 +#define GP_PRT_TRQ0 <&gpio5 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 +#define GP_PRT_TRQ1 <&gpio5 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +#define GP_PRT_MOTOR_FAULT <&gpio5 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 +#define GP_PRT_DOUT <&gpio1 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 +#define GP_PRT_PAPER_OUT <&gpio1 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 +#define GP_STAT_LED1 <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 +#define GP_STAT_LED2 <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x130b0 + /* Scanner */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x130b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x130b0 + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x130b0 + /* Solenoids */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_adc081c: i2c2-adc081cgrp { + fsl,pins = < +#define GPIRQ_PRINT_ALERT <&gpio5 20 IRQ_TYPE_EDGE_BOTH> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_ads7924: i2c3_ads7924grp { + fsl,pins = < +#define GPIRQ_ADC_INTR <&gpio3 14 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 +#define GP_ADC_RESET <&gpio3 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x130b0 + >; + }; + + pinctrl_i2c3_adt75: i2c3_adt75grp { + fsl,pins = < +#define GPIRQ_TEMP_ALERT <&gpio4 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c3_gslx680: i2c3_gslx680grp { + fsl,pins = < +#define GPIRQ_GSLX680 <&gpio4 10 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x130b0 +#define GP_GSLX680_POWER <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_lcd; + pwm_lcd = &pwm3; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm3 0 5000000>; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str = "ASIT500MA6F5D"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "enabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_adc_vref: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "adc_vref"; + regulator-min-microvolt = <4096000>; + regulator-max-microvolt = <4096000>; + }; + + reg_usbotg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <3>; + cs-gpios = GP_ECSPI2_MOTOR0, GP_ECSPI2_MOTOR1, GP_ECSPI2_OPTICS; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <1>; + }; + + spidev@2 { + compatible = "lmp90079"; + interrupts-extended = GPIRQ_LMP90079; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_lmp90079>; + spi-max-frequency = <2000000>; + reg = <2>; + vref-supply = <®_adc_vref>; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI4_DUMMY_CS0; + status = "okay"; + + ftp628@0 { + compatible = "fujitsu,ftp628"; + spi-max-frequency = <1000000>; + reg = <0>; + latch-gpio = GP_PRT_LATCH; + mt-ab-gpios = GP_PRT_MOTOR_A1, GP_PRT_MOTOR_A2, + GP_PRT_MOTOR_B1, GP_PRT_MOTOR_B2; + mt-ate-gpio = GP_PRT_MOTOR_ATE; + mt-fault-gpio = GP_PRT_MOTOR_FAULT; + mt-dcay-gpios = GP_PRT_MOTOR_ADCAY, GP_PRT_MOTOR_BDCAY; + mt-sleep-gpio = GP_PRT_MOTOR_SLEEP; + mt-toff-gpio = GP_PRT_MOTOR_TOFF; + mt-trq-gpios = GP_PRT_TRQ0, GP_PRT_TRQ1; + paper-out-gpio = GP_PRT_PAPER_OUT; + strobe-gpios = GP_PRT_STROBE1, GP_PRT_STROBE2, GP_PRT_STROBE3, + GP_PRT_STROBE4, GP_PRT_STROBE5, GP_PRT_STROBE6; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + adc081c@54 { + samples-per-sec = <400>; + compatible = "ti,adc081c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_adc081c>; + reg = <0x54>; + vref-supply = <®_3p3v>; + interrupts-extended = GPIRQ_PRINT_ALERT; + }; + + gslx680_ts@40 { + compatible = "silead,gsl1680"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gslx680>; + reg = <0x40>; + interrupts-extended = GPIRQ_GSLX680; + power-gpios = GP_GSLX680_POWER; + touchscreen-size-x = <480>; /* swapped below */ + touchscreen-size-y = <800>; + touchscreen-swapped-x-y; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + ads7924_adc@48 { + compatible = "ti,ads7924"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ads7924>; + reg = <0x48>; + vref-supply = <®_3p3v>; + reset-gpios = GP_ADC_RESET; + interrupts-extended = GPIRQ_ADC_INTR; + adc-irq-mode = /bits/ 8 <0x00>; /* IRQ for alarms */ + adc-mode = /bits/ 8 <0x3B>; /* Auto Scan w/ Sleep */ + adc-sleep-ms = <320>; + }; + + adt75_temp@49 { + compatible = "adt75"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_adt75>; + reg = <0x49>; + interrupts-extended = GPIRQ_TEMP_ALERT; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ap.dtsi b/arch/arm/boot/dts/imx6qdl-ap.dtsi new file mode 100644 index 00000000000000..e1dc7431f0e753 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ap.dtsi @@ -0,0 +1,989 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_ap: iomuxc-imx6q-apgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ap { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_SEARCH <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio7 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi-cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_GPIO_1 <&gpio4 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b0 +#define GP_GPIO_2 <&gpio4 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 +#define GP_GPIO_3 <&gpio4 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 +#define GP_GPIO_4 <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 +#define GP_GPIO_5 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 +#define GP_GPIO_6 <&gpio4 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +#define GP_GPIO_7 <&gpio1 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +#define GP_GPIO_8 <&gpio4 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 +#define GP_GPIO_9 <&gpio5 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 +#define GP_GPIO_10 <&gpio5 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b0 +#define GP_GPIO_11 <&gpio5 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 +#define GP_GPIO_12 <&gpio5 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 +#define GP_GPIO_13 <&gpio5 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 +#define GP_GPIO_14 <&gpio5 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 +#define GP_GPIO_15 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 +#define GP_GPIO_16 <&gpio5 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 + +#define GP_BT_CLK_REQ <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 +#define GP_BT_HOST_WAKE <&gpio6 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 +#define GP_WIFI_QOW <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 +#define GP_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP101 <&gpio3 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 +#define GP_TP102 <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio1 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c1_wm8960: i2c1-wm8960grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* aud_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +#define GP_SER2_GPIO5 <&gpio2 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_SER2_GPIO6 <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_SER2_FAN_OK <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GPIRQ_SER2 <&gpio2 31 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gt911: i2c2_gt911grp { + fsl,pins = < +#define GPIRQ_I2C2_SER2_TOUCH <&gpio1 16 IRQ_TYPE_LEVEL_HIGH> /* GP0 */ +#define GP_I2C2_SER2_TOUCH <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x130b0 +#define GP_I2C2_GT911_RESET <&gpio1 19 GPIO_ACTIVE_HIGH> /* GP3 */ + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x030b0 + >; + }; + + pinctrl_i2c2_lp8860: i2c2_lp8860grp { + fsl,pins = < +#define GP_LVDS2_LP8860_RESET <&gpio2 23 GPIO_ACTIVE_LOW> /* GP1 */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GP_SER1_GPIO5 <&gpio2 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_SER1_GPIO6 <&gpio2 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_SER1_FAN_OK <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GPIRQ_SER1 <&gpio2 30 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gt911: i2c3_gt911grp { + fsl,pins = < +#define GPIRQ_I2C3_SER1_TOUCH <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> /* GP0 */ +#define GP_I2C3_SER1_TOUCH <&gpio1 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x130b0 +#define GP_I2C3_GT911_RESET <&gpio1 18 GPIO_ACTIVE_HIGH> /* GP3 */ + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x030b0 + >; + }; + + pinctrl_i2c3_lp8860: i2c3_lp8860grp { + fsl,pins = < +#define GP_LVDS_LP8860_RESET <&gpio2 0 GPIO_ACTIVE_LOW> /* GP1 */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x030b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x030b0 +#define GP_PCIE_DISABLE <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 +#define GP_UART4_TX_EN <&gpio4 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x030b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +#define GP_UART5_RX_EN <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x030b0 /* RS485 RX Enable: pull down */ +#define GP_UART5_TX_EN <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x030b0 /* RS485 DEN: pull down */ +#define GP_UART5_RS485_EN <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x030b0 /* RS485/!RS232 Select: pull down (rs232) */ +#define GP_UART5_AON <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 /* ON: pull down */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x130b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WIFI <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 +#define GP_WIFI_WAKE <&gpio6 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + fb_lvds = &fb_lvds; + fb_lvds2 = &fb_lvds2; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lvds2; + mxcfb2 = &fb_hdmi; + pwm_lvds = &pwm4; + pwm_lvds2 = &pwm2; + t_lvds = &t_lvds; + t_lvds2 = &t_lvds2; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "bt_rfkill"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + reset-gpios = GP_BT_RFKILL_RESET; + type = <2>; /* bluetooth */ + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + default_bpp = <16>; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds2: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + default_bpp = <16>; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + default_bpp = <32>; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + int_clk = <0>; + late_init = <0>; + mode_str ="1280x720M@60"; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + search { + label = "Search Button"; + gpios = GP_GPIOKEY_SEARCH; + linux,code = ; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "1P8V"; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-always-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "2P5V"; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3P3V"; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_USBOTG; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + reg = <3>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_WLAN_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + reg = <4>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "wlan-en"; + startup-delay-us = <70000>; + }; + }; + + sound { + compatible = "fsl,imx6q-ap-wm8960", + "fsl,imx-audio-wm8960"; +#ifdef USE_ASRC + asrc-controller = <&asrc>; +#endif + audio-codec = <&wm8960>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB" +#ifdef USE_ASRC + ,"CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture" +#endif + ; + codec-master; + cpu-dai = <&ssi1>; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + model = "wm8960-audio"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + model = "imx-audio-hdmi"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = GP_ECSPI1_NOR_CS; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + interrupts-extended = GPIRQ_ENET_PHY; + reg = <6>; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_cksymtx = <0x800d>; + fsl,phy_reg_vlev = <0x0294>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + interrupts-extended = GPIRQ_RTC_RV4162; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + }; + + wm8960: wm8960@1a { + assigned-clocks = <&clks IMX6QDL_CLK_CKO>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "mclk"; + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "wlf,wm8960"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_wm8960>; + reg = <0x1a>; + wlf,shared-lrclk; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + gt911@5d { + compatible = "goodix,gt911"; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_I2C2_SER2_TOUCH; + irq-gpios = GP_I2C2_SER2_TOUCH; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_gt911>; + reg = <0x5d>; + reset-gpios = GP_I2C2_GT911_RESET; + substitute-i2c-address = <0x2c>; + }; + + lp8860_backlight_lvds2@2d { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "lp8860-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_lp8860>; + reg = <0x2d>; + reset-gpios = GP_LVDS2_LP8860_RESET; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + gt911@5d { + compatible = "goodix,gt911"; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_I2C3_SER1_TOUCH; + irq-gpios = GP_I2C3_SER1_TOUCH; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x5d>; + reset-gpios = GP_I2C3_GT911_RESET; + substitute-i2c-address = <0x2c>; + }; + + lp8860_backlight_lvds@2d { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "lp8860-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_lp8860>; + reg = <0x2d>; + reset-gpios = GP_LVDS_LP8860_RESET; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + /* TFC_A9700LTWV35TC_C1 values may be changed in bootscript */ + clock-frequency = <29232073>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + }; + }; + }; + + lvds-channel@1 { + crtc = "ipu1-di0"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + t_lvds2: t_lvds2_default { + /* TFC_A9700LTWV35TC_C1 values may be changed in bootscript */ + clock-frequency = <29232073>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + control-gpios = GP_UART4_TX_EN; + off_levels = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rs232_levels = <0>; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0>; + rs485_txen_mask = <0x1>; + rs485_txen_levels = <1>; + rs485-mode = <1>; + rxact_mask = <0>; + rxact_levels = <0>; + status = "okay"; + uart-has-rs485-half-duplex; +}; + +&uart5 { + control-gpios = GP_UART5_RX_EN, GP_UART5_TX_EN, GP_UART5_RS485_EN, GP_UART5_AON; + off_levels = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +#define M_RX_EN 1 +#define M_TX_EN 2 +#define M_RS485 4 +#define M_AON 8 + rs232_levels = ; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0xd>; + rs485_txen_mask = <0x3>; + rs485_txen_levels = ; + rs485-mode = <1>; /* 1 to enable */ + rxact_mask = <0>; + rxact_levels = <0>; + status = "okay"; + uart-has-rs485-half-duplex; +}; + +&usbh1 { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; + vbus-supply = <®_usbotg_vbus>; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + status = "okay"; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WIFI; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + status = "okay"; + vmmc-supply = <®_3p3v>; +}; + +&usdhc4 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; + vmmc-supply = <®_1p8v>; + vqmmc-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index 54f4f0193f2b26..d8e1bfb89f6155 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -3,6 +3,8 @@ * * Copyright (C) 2014 Heiko Schocher * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -12,6 +14,13 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -55,6 +64,53 @@ regulator-max-microvolt = <5000000>; }; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + status = "disabled"; + }; }; &audmux { diff --git a/arch/arm/boot/dts/imx6qdl-ash.dtsi b/arch/arm/boot/dts/imx6qdl-ash.dtsi new file mode 100644 index 00000000000000..313296c2819077 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ash.dtsi @@ -0,0 +1,923 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_ash: iomuxc-imx6q-ashgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ash { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_SW1 <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 +#define GP_GPIOKEY_SW2 <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_GPIOKEY_SW3 <&gpio2 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_GPIOKEY_SW4 <&gpio2 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_GPIOKEY_SW5 <&gpio2 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_GPIOKEY_POWER <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_GPIOKEY_CH_ON_RBL <&gpio5 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 +#define GP_GPIOKEY_SG_ON_RBL <&gpio5 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 +#define GP_GPIOKEY_DOOR_CLOSED <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_USDHC3_POWER_EN <&gpio1 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_HOG_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_HOG_TP84 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_HOG_TP85 <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 +#define GP_HOG_TP86 <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_8BIT_LVDS <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 +#define GP_POWER_OFF <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x030b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio7 12 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_TDA7491P_GAIN0 <&gpio5 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x030b0 +#define GP_TDA7491P_GAIN1 <&gpio6 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x030b0 +#define GP_TDA7491P_STBY <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 +#define GP_TDA7491P_MUTE <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x030b0 +#define GPIRQ_MIC_DET <&gpio7 8 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ar1021: i2c2-ar1021grp { + fsl,pins = < +#define GPIRQ_AR1021 <&gpio1 7 IRQ_TYPE_LEVEL_HIGH> +#define GP_AR1021 <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x130b0 +#define GP_AR1021_5WIRE <&gpio1 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J6 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J6 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J6 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x030b0 +#define GP_PCIE_DISABLE <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x0b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +#define GP_UART1_RX_EN <&gpio3 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* RS485 RX Enable: pull down */ +#define GP_UART1_TX_EN <&gpio3 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x030b0 /* RS485 DEN: pull down */ +#define GP_UART1_RS485_EN <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 /* RS485/!RS232 Select: pull down (rs232) */ +#define GP_UART1_AON <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x030b0 /* ON: pull down */ +#define GP_UART1_RS485_TERM <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x030b0 /* pull down */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + mxcfb2 = &fb_lcd; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + serial2 = &uart4; + serial3 = &uart3; + t_lvds = &t_lvds; + uart1 = &uart1; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <10 9 8 7 6 5 4 3 2 1 0>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 200000>; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + sw1 { + label = "sw1"; + gpios = GP_GPIOKEY_SW1; + linux,code = ; + }; + + sw2 { + label = "sw2"; + gpios = GP_GPIOKEY_SW2; + linux,code = ; + }; + + sw3 { + label = "sw3"; + gpios = GP_GPIOKEY_SW3; + linux,code = ; + }; + + sw4 { + label = "sw4"; + gpios = GP_GPIOKEY_SW4; + linux,code = ; + }; + + sw5 { + label = "sw5"; + gpios = GP_GPIOKEY_SW5; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + ch_on_rbl { + label = "ch_on_rbl"; + gpios = GP_GPIOKEY_CH_ON_RBL; + linux,code = ; + }; + + sg_on_rbl { + label = "sg_on_rbl"; + gpios = GP_GPIOKEY_SG_ON_RBL; + linux,code = ; + }; + + door_closed { + label = "door_closed"; + gpios = GP_GPIOKEY_DOOR_CLOSED; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + poweroff: poweroff { + compatible = "gpio-poweroff"; + gpios = GP_POWER_OFF; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-ash-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_TDA7491P_MUTE; + amp-standby-gpios = GP_TDA7491P_STBY; + amp-gain-gpios = GP_TDA7491P_GAIN1, GP_TDA7491P_GAIN0; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + inter-byte-delay = <170>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + stop-delay = <30>; + + ar1021@4d { + compatible = "ar1020_i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ar1021>; + reg = <0x4d>; + interrupts-extended = GPIRQ_AR1021; + wakeup-gpios = GP_AR1021; + }; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <37714285>; + hactive = <800>; + vactive = <480>; + hback-porch = <220>; + hfront-porch = <18>; + vback-porch = <21>; + vfront-porch = <14>; + hsync-len = <18>; + vsync-len = <10>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + control-gpios = GP_UART1_RX_EN, GP_UART1_TX_EN, GP_UART1_RS485_EN, GP_UART1_AON, GP_UART1_RS485_TERM; +#define M_RX_EN 1 +#define M_TX_EN 2 +#define M_RS485 4 +#define M_AON 8 +#define M_TERM 0x10 + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = ; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0x0d>; /* 0x1d to enable termination */ + rs485_txen_mask = <0x3>; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <0>; /* 1 to enable */ + status = "okay"; +}; + + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ash2.dtsi b/arch/arm/boot/dts/imx6qdl-ash2.dtsi new file mode 100644 index 00000000000000..89892e73dacc5d --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ash2.dtsi @@ -0,0 +1,904 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_ash: iomuxc-imx6q-ashgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ash { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_SW1 <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 +#define GP_GPIOKEY_SW2 <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_GPIOKEY_SW3 <&gpio2 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_GPIOKEY_SW4 <&gpio2 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_GPIOKEY_SW5 <&gpio2 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_GPIOKEY_SW6 <&gpio2 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b0 +#define GP_GPIOKEY_POWER <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_GPIOKEY_CH_ON_RBL <&gpio5 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 +#define GP_GPIOKEY_SG_ON_RBL <&gpio5 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 +#define GP_GPIOKEY_DOOR_CLOSED <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_USDHC3_POWER_EN <&gpio1 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_HOG_TP_R5 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_HOG_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_HOG_TP84 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_HOG_TP85 <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 +#define GP_HOG_TP86 <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_8BIT_LVDS <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 +#define GP_POWER_OFF <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x030b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio7 12 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_TDA7491P_GAIN0 <&gpio5 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x030b0 +#define GP_TDA7491P_GAIN1 <&gpio6 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x030b0 +#define GP_TDA7491P_STBY <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 +#define GP_TDA7491P_MUTE <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x030b0 +#define GPIRQ_MIC_DET <&gpio7 8 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ar1021: i2c2-ar1021grp { + fsl,pins = < +#define GPIRQ_AR1021 <&gpio1 7 IRQ_TYPE_LEVEL_HIGH> +#define GP_AR1021 <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x130b0 +#define GP_AR1021_5WIRE <&gpio1 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J6 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J6 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J6 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio2 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x0b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 +#define GP_UART1_RX_EN <&gpio3 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* RS485 RX Enable: pull down */ +#define GP_UART1_TX_EN <&gpio3 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x030b0 /* RS485 DEN: pull down */ +#define GP_UART1_RS485_EN <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 /* RS485/!RS232 Select: pull down (rs232) */ +#define GP_UART1_AON <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x030b0 /* ON: pull down */ +#define GP_UART1_RS485_TERM <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x030b0 /* pull down */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WIFI <&gpio6 14 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 +#define GP_WIFI_WAKE <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_WIFI_QOW <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_BT_HOST_WAKE <&gpio6 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 +#define GP_BT_CLK_REQ <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + uart1 = &uart1; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <10 9 8 7 6 5 4 3 2 1 0>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 200000>; + }; + + bt_rfkill: bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + status = "okay"; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + sw1 { + label = "sw1"; + gpios = GP_GPIOKEY_SW1; + linux,code = ; + }; + + sw2 { + label = "sw2"; + gpios = GP_GPIOKEY_SW2; + linux,code = ; + }; + + sw3 { + label = "sw3"; + gpios = GP_GPIOKEY_SW3; + linux,code = ; + }; + + sw4 { + label = "sw4"; + gpios = GP_GPIOKEY_SW4; + linux,code = ; + }; + + sw5 { + label = "sw5"; + gpios = GP_GPIOKEY_SW5; + linux,code = ; + }; + + sw6 { + label = "sw6"; + gpios = GP_GPIOKEY_SW6; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + ch_on_rbl { + label = "ch_on_rbl"; + gpios = GP_GPIOKEY_CH_ON_RBL; + linux,code = ; + }; + + sg_on_rbl { + label = "sg_on_rbl"; + gpios = GP_GPIOKEY_SG_ON_RBL; + linux,code = ; + }; + + door_closed { + label = "door_closed"; + gpios = GP_GPIOKEY_DOOR_CLOSED; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + poweroff: poweroff { + compatible = "gpio-poweroff"; + gpios = GP_POWER_OFF; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_WLAN_EN; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + }; + + sound { + compatible = "fsl,imx6q-ash-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_TDA7491P_MUTE; + amp-standby-gpios = GP_TDA7491P_STBY; + amp-gain-gpios = GP_TDA7491P_GAIN1, GP_TDA7491P_GAIN0; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + inter-byte-delay = <170>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + stop-delay = <30>; + + ar1021@4d { + compatible = "ar1020_i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ar1021>; + reg = <0x4d>; + interrupts-extended = GPIRQ_AR1021; + wakeup-gpios = GP_AR1021; + }; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <37714285>; + hactive = <800>; + vactive = <480>; + hback-porch = <220>; + hfront-porch = <18>; + vback-porch = <21>; + vfront-porch = <14>; + hsync-len = <18>; + vsync-len = <10>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + control-gpios = GP_UART1_RX_EN, GP_UART1_TX_EN, GP_UART1_RS485_EN, GP_UART1_AON, GP_UART1_RS485_TERM; +#define M_RX_EN 1 +#define M_TX_EN 2 +#define M_RS485 4 +#define M_AON 8 +#define M_TERM 0x10 + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = ; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0x0d>; /* 0x1d to enable termination */ + rs485_txen_mask = <0x3>; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <0>; /* 1 to enable */ + status = "okay"; +}; + + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-bt.dtsi b/arch/arm/boot/dts/imx6qdl-bt.dtsi new file mode 100644 index 00000000000000..6770c7e65c1a63 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-bt.dtsi @@ -0,0 +1,830 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_bt: iomuxc-imx6q-btgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_bt { + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_BT_GPIO1 <&gpio2 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* BGPIO1 */ +#define GP_BT_GPIO2 <&gpio2 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x1b0b0 /* BGPIO2 */ +#define GP_BT_GPIO3 <&gpio2 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 /* BGPIO3 */ +#define GP_BT_GPIO4 <&gpio2 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* BGPIO4 */ +#define GP_BT_GPIO5 <&gpio2 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* BGPIO5 */ +#define GP_BT_GPIO6 <&gpio2 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* BGPIO6 */ +#define GP_BT_GPIO7 <&gpio2 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* BGPIO7 */ +#define GP_BT_GPIO8 <&gpio2 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* BGPIO8 */ +#define GP_BT_GPIO9 <&gpio7 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x1b0b0 /* BGPIO9 */ +#define GP_BT_GPIO10 <&gpio7 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0 /* BGPIO10 */ +#define GP_BT_GPIO11 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* BGPIO11 */ +#define GP_BT_GPIO12 <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* BGPIO12 */ +#define GP_BT_GPIO13 <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 /* BGPIO13 */ +#define GP_BT_GPIO14 <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* BGPIO14 */ +#define GP_BT_GPIO15 <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* BGPIO15 */ +#define GP_BT_GPIO16 <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 /* BGPIO16 */ +#define GP_BT_GPIO17 <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* BGPIO17 */ +#define GP_BT_GPIO18 <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 /* BGPIO18 */ +#define GP_BT_GPIO19 <&gpio6 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /* BGPIO19 */ +#define GP_BT_GPIO20 <&gpio6 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /* BGPIO20 */ +#define GP_BT_GPIO21 <&gpio6 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* BGPIO21 */ +#define GP_BT_GPIO22 <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* BGPIO22 */ +#define GP_BT_GPIO23 <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* BGPIO23 */ +#define GP_BT_GPIO24 <&gpio6 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* BGPIO24 */ +#define GP_BT_GPIO25 <&gpio6 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* BGPIO25 */ +#define GP_BT_GPIO26 <&gpio6 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 /* BGPIO26 */ +#define GP_BT_GPIO27 <&gpio5 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 /* BGPIO27 */ +#define GP_BT_GPIO28 <&gpio5 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 /* BGPIO28 */ +#define GP_BT_GPIO29 <&gpio5 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 /* BGPIO29 */ +#define GP_BT_GPIO30 <&gpio5 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x1b0b0 /* BGPIO30 */ +#define GP_BT_GPIO31 <&gpio6 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0 /* BGPIO31 */ +#define GP_BT_GPIO32 <&gpio6 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 /* BGPIO32 */ +#define GP_BT_GPIO33 <&gpio6 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0 /* BGPIO33 */ +#define GP_BT_GPIO34 <&gpio6 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 /* BGPIO34 */ +#define GP_BT_GPIO35 <&gpio5 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* BGPIO35 */ +#define GP_BT_GPIO36 <&gpio3 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 /* BGPIO36 */ +#define GP_BT_GPIO37 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 /* BGPIO37 */ +#define GP_BT_GPIO38 <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 /* BGPIO38 */ +#define GP_BT_GPIO39 <&gpio5 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 /* BGPIO39 */ +#define GP_BT_GPIO40 <&gpio5 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 /* BGPIO40 */ + +#define GP_PWR_J1 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x4000b0b0 /* J1 Power enable */ +#define GP_PWR_J2 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x4000b0b0 /* J2 */ +#define GP_PWR_J3 <&gpio2 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x4000b0b0 /* J3 */ +#define GP_PWR_J4 <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x4000b0b0 /* J4 */ +#define GP_PWR_J6 <&gpio2 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x4000b0b0 /* J6 */ +#define GP_PWR_J7 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x4000b0b0 /* J7 */ + + /* J92 pins */ +#define GP_J92_PIN7 <&gpio3 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0b0b0 /* OUT_1 - Dry contact to J92 pin 7 */ +#define GP_J92_PIN9 <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x030b0 /* OUT_2 - Dry contact to J92 pin 9 */ +#define GP_J92_PIN10 <&gpio5 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x0b0b0 /* GPI_1 - J92 - pin 10 */ +#define GP_J92_PIN12 <&gpio5 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0b0b0 /* GPI_2 - J92 - pin 12 */ + >; + }; + + pinctrl_adv7391: adv7391grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* Pixclk */ + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_adv7391_off: adv7391grp-2 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0b0b0 /* Pixclk */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0b0b0 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0b0b0 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0b0b0 +#define GP_ADV7391_RESET <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 /* reset */ + >; + }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* Audio - GS2971 */ + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x1b070 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1b070 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1b070 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_GS2971_CS <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0b0b0 /* GS2971 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gs2971: gs2971grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_gs2971_cea861: gs2971_cea861grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_gs2971_no_cea861: gs2971_no_cea861grp { /* parallel camera */ + /* sav/eav codes are used, not hsync/vsync */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b0 /* HSYNC */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b0 /* VSYNC */ + >; + }; + + pinctrl_gs2971_gpios: gs2971_gpiosgrp { + fsl,pins = < +#define GPIO_INPUT 2 +#define GP_GS2971_STANDBY <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 /* 1 - pin K2 - Standby */ +#define GP_GS2971_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x000b0 /* 0 - pin C7 - reset */ +#define GP_GS2971_RC_BYPASS <&gpio4 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x000b0 /* 0 - pin G3 - RC bypass - output is buffered(low) */ +#define GP_GS2971_IOPROC_EN <&gpio4 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x000b0 /* 0 - pin H8 - io(A/V) processor enable */ +#define GP_GS2971_AUDIO_EN <&gpio4 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x000b0 /* 0 - pin H3 - Audio Enable */ +#define GP_GS2971_TIM_861 <&gpio4 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x000b0 /* 0 - pin H5 - TIM861 timing format, 1-use HSYNC/VSYNC */ +#define GP_GS2971_SW_EN <&gpio4 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x000b0 /* 0 - pin D7 - SW_EN - line lock enable */ +#define GP_GS2971_DVB_ASI <&gpio5 5 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b0 /* pin G8 i/o DVB_ASI */ +#define GP_GS2971_SMPTE_BYPASS <&gpio2 24 GPIO_INPUT> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 /* pin G7 - i/o SMPTE bypass */ +#define GP_GS2971_DVI_LOCK <&gpio3 14 GPIO_INPUT> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 /* pin B6 - stat3 - DVI_LOCK */ +#define GP_GS2971_DATA_ERR <&gpio3 15 GPIO_INPUT> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 /* pin C6 - stat5 - DATA error */ +#define GP_GS2971_LB_CONT <&gpio3 20 GPIO_INPUT> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 /* pin A3 - LB control - float, analog input */ +#define GP_GS2971_Y_1ANC <&gpio4 26 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* pin C5 - stat4 - 1ANC - Y signal detect */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x000b0 /* pcie reset */ + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 11 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_sc16is7xx: sc16is7xxgrp { + fsl,pins = < +#define GPIRQ_SC16IS752 <&gpio4 10 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { /* UART1 - J2 - PTT connector */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { /* UART2 - debug console */ + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { /* UART3 */ + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { /* UART4 */ + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { /* UART5 - J6 data connector */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USB_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset for USB2512 4 port hub */ +#define GP_AX88772A_RESET <&gpio5 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +#define GP_USB_OTG_PWR <&gpio3 22 0> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0b0b0 /* otg power en */ + >; + }; + + /* full size SD card */ + pinctrl_usdhc1_50mhz: usdhc1grp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +#define GP_USDHC1_CD <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +#define GP_USDHC1_WP <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_USDHC1_1P8V_SEL <&gpio7 13 GPIO_ACTIVE_LOW> /* low 1.8V, high 3.3V */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + pinctrl_usdhc1_100mhz: usdhc1grp-2 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + >; + }; + pinctrl_usdhc1_200mhz: usdhc1grp-3 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + >; + }; + + /* micro SD card */ + pinctrl_usdhc2_50mhz: usdhc2grp-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +#define GP_USDHC2_CD <&gpio3 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + >; + }; + + /* eMMC */ + pinctrl_usdhc3_50mhz: usdhc3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0b0b0 + >; + }; + +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lcd; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG_PWR; + enable-active-high; + }; + + }; + + reserved-memory { + linux,cma { + size = <0x18000000>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "adv739x"; + interface_pix_fmt = "BT656"; + mode_str ="BT656-NTSC"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + v4l2_cap_0: v4l2_cap_0 { + /* gs2971 */ + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <1>; + device_id = <8>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI3_GS2971_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + gs2971: gs2971@0 { + compatible = "gn,gs2971"; + reg = <0>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_gs2971>, <&pinctrl_gs2971_gpios>; + pinctrl-1 = <&pinctrl_gs2971_no_cea861>; + pinctrl-2 = <&pinctrl_gs2971_cea861>; + mclk = <27000000>; + csi = <1>; + cea861 = <0>; + spi-max-frequency = <6000000>; + standby-gpios = GP_GS2971_STANDBY; /* 1 - powerdown */ + rst-gpios = GP_GS2971_RESET; /* 0 - reset */ + tim_861-gpios = GP_GS2971_TIM_861; /* 0 - TIM861 timing format sav/eav codes */ + /* enable on power up */ + ioproc_en-gpios = GP_GS2971_IOPROC_EN; /* 0 - io(A/V) processor disabled */ + sw_en-gpios = GP_GS2971_SW_EN; /* 0 - line lock disabled */ + rc_bypass-gpios = GP_GS2971_RC_BYPASS; /* 0 - RC bypass - output is buffered(low) */ + audio_en-gpios = GP_GS2971_AUDIO_EN; /* 0 - audio disabled */ + dvb_asi-gpios = GP_GS2971_DVB_ASI; /* 0 - dvs_asi disabled */ + smpte_bypass-gpios = GP_GS2971_SMPTE_BYPASS; /* in */ + dvi_lock-gpios = GP_GS2971_DVI_LOCK; /* in */ + data_err-gpios = GP_GS2971_DATA_ERR; /* in */ + lb_cont-gpios = GP_GS2971_LB_CONT; /* in */ + y_1anc-gpios = GP_GS2971_Y_1ANC; /* in */ + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + sc16is7xx@49 { + compatible = "nxp,sc16is7xx-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sc16is7xx>; + reg = <0x49>; + interrupts-extended = GPIRQ_SC16IS752; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + adv7391: adv7391@2a { + compatible = "adv,mxc_adv739x"; + reg = <0x2a>; + pinctrl-names = "default", "enable"; + pinctrl-0 = <&pinctrl_adv7391_off>; + pinctrl-1 = <&pinctrl_adv7391>; + rst-gpios = GP_ADV7391_RESET; + ipu_id = <0>; + disp_id = <0>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USB_HUB_RESET, GP_AX88772A_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC1_CD; + wp-gpios = GP_USDHC1_WP; + power-sel-gpios = GP_USDHC1_1P8V_SEL; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC2_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + reset-gpios = GP_EMMC_RESET; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-bt2.dtsi b/arch/arm/boot/dts/imx6qdl-bt2.dtsi new file mode 100644 index 00000000000000..3375a5dc8941ac --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-bt2.dtsi @@ -0,0 +1,840 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_bt: iomuxc-imx6q-btgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_bt { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* Audio - GS2971 */ + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x1b070 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1b070 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1b070 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_GS2971_CS <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0b0b0 /* GS2971 */ + >; + }; + + pinctrl_ecspi3_gs2971: ecspi3-gs2971grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ecspi3_gs2971_cea861: ecspi3-gs2971_cea861grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ecspi3_gs2971_no_cea861: ecspi3-gs2971-no-cea861grp { /* parallel camera */ + /* sav/eav codes are used, not hsync/vsync */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b0 /* HSYNC */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b0 /* VSYNC */ + >; + }; + + pinctrl_ecspi3_gs2971_gpios: ecspi3-gs2971-gpiosgrp { + fsl,pins = < +#define GPIO_INPUT 2 +#define GP_GS2971_STANDBY <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x0b0b0 /* 1 - pin K2 - Standby */ +#define GP_GS2971_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 /* 0 - pin C7 - reset */ +#define GP_GS2971_RC_BYPASS <&gpio4 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x000b0 /* 0 - pin G3 - RC bypass - output is buffered(low) */ +#define GP_GS2971_IOPROC_EN <&gpio4 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x000b0 /* 0 - pin H8 - io(A/V) processor enable */ +#define GP_GS2971_AUDIO_EN <&gpio4 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x000b0 /* 0 - pin H3 - Audio Enable */ +#define GP_GS2971_TIM_861 <&gpio4 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x000b0 /* 0 - pin H5 - TIM861 timing format, 1-use HSYNC/VSYNC */ +#define GP_GS2971_SW_EN <&gpio4 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x000b0 /* 0 - pin D7 - SW_EN - line lock enable */ +#define GP_GS2971_DVB_ASI <&gpio5 5 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b0 /* pin G8 i/o DVB_ASI */ +#define GP_GS2971_SMPTE_BYPASS <&gpio2 24 GPIO_INPUT> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 /* pin G7 - i/o SMPTE bypass */ +#define GP_GS2971_DVI_LOCK <&gpio3 14 GPIO_INPUT> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 /* pin B6 - stat3 - DVI_LOCK */ +#define GP_GS2971_DATA_ERR <&gpio3 15 GPIO_INPUT> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 /* pin C6 - stat5 - DATA error */ +#define GP_GS2971_LB_CONT <&gpio3 20 GPIO_INPUT> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 /* pin A3 - LB control - float, analog input */ +#define GP_GS2971_Y_1ANC <&gpio4 26 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* pin C5 - stat4 - 1ANC - Y signal detect */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_PWR_J1 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x4000b0b0 /* SION */ +#define GP_PWR_J2 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x4000b0b0 +#define GP_PWR_J3 <&gpio2 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x4000b0b0 +#define GP_PWR_J4 <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x4000b0b0 +#define GP_PWR_J5V <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x4000b0b0 +#define GP_PWR_J12V <&gpio2 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x4000b0b0 + +#define GP_TW6869_MIC_BIAS_EN <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 + + /* J92 pins */ +#define GP_J92_PIN7 <&gpio3 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0b0b0 /* OUT_1 - Dry contact to J92 pin 7 */ +#define GP_J92_PIN9 <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x030b0 /* OUT_2 - Dry contact to J92 pin 9 */ +#define GP_J92_PIN10 <&gpio5 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x0b0b0 /* GPI_1 - J92 - pin 10 */ +#define GP_J92_PIN12 <&gpio5 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0b0b0 /* GPI_2 - J92 - pin 12 */ + +#define GP_TP77 <&gpio5 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 +#define GP_TP81 <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +#define GP_TP82 <&gpio1 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 11 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7391_on: i2c3-adv7391-ongrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* Pixclk */ + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_i2c3_adv7391_off: i2c3-adv7391-offgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0b0b0 /* Pixclk */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0b0b0 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0b0b0 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0b0b0 +#define GP_ADV7391_RESET <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x030b0 /* reset */ + >; + }; + + pinctrl_i2c3_max_7w: i2c3_max_7wgrp { + fsl,pins = < +#define GP_GPS_RESET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x030b0 + +#define GP_GPS_RXD <&gpio5 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 /* imx6 uart4 tx */ +#define GP_GPS_TXD <&gpio5 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 /* imx6 uart4 rx */ +#define GP_GPS_TIMEPULSE <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GPIRQ_GPS_EXT <&gpio2 31 IRQ_TYPE_EDGE_FALLING> +#define GP_GPS_EXT <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x000b0 /* pcie reset */ + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { /* UART1 - J1 - PTT connector */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { /* UART2 - debug console */ + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { /* UART3 - J2 */ + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { /* UART4 - J3 */ + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { /* UART5 - J4 */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USB_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset for USB2512 4 port hub */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + /* full size SD card */ + pinctrl_usdhc1_50mhz: usdhc1-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +#define GP_USDHC1_CD <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +#define GP_USDHC1_WP <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* full size SD card */ + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 +#define GP_USDHC2_CD <&gpio3 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 +#define GP_USDHC2_WP <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + /* eMMC */ + pinctrl_usdhc3_50mhz: usdhc3-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10031 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17031 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17031 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17031 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17031 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17031 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17031 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17031 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17031 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0b0b0 + >; + }; + + /* Broadcom GB863021 */ + pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 +#define GPIRQ_WL1271 <&gpio6 10 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lcd; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "adv739x"; + interface_pix_fmt = "BT656"; + mode_str ="BT656-NTSC"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + reserved-memory { + linux,cma { + size = <0x18000000>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0: v4l2_cap_0 { + /* gs2971 */ + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <1>; + device_id = <8>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI3_GS2971_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + gs2971: gs2971@0 { + compatible = "gn,gs2971"; + reg = <0>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_ecspi3_gs2971>, <&pinctrl_ecspi3_gs2971_gpios>; + pinctrl-1 = <&pinctrl_ecspi3_gs2971_no_cea861>; + pinctrl-2 = <&pinctrl_ecspi3_gs2971_cea861>; + mclk = <27000000>; + csi = <1>; + cea861 = <0>; + spi-max-frequency = <6000000>; + standby-gpios = GP_GS2971_STANDBY; /* 1 - powerdown */ + rst-gpios = GP_GS2971_RESET; /* 0 - reset */ + tim_861-gpios = GP_GS2971_TIM_861; /* 0 - TIM861 timing format sav/eav codes */ + /* enable on power up */ + ioproc_en-gpios = GP_GS2971_IOPROC_EN; /* 0 - io(A/V) processor disabled */ + sw_en-gpios = GP_GS2971_SW_EN; /* 0 - line lock disabled */ + rc_bypass-gpios = GP_GS2971_RC_BYPASS; /* 0 - RC bypass - output is buffered(low) */ + audio_en-gpios = GP_GS2971_AUDIO_EN; /* 0 - audio disabled */ + dvb_asi-gpios = GP_GS2971_DVB_ASI; /* 0 - dvs_asi disabled */ + smpte_bypass-gpios = GP_GS2971_SMPTE_BYPASS; /* in */ + dvi_lock-gpios = GP_GS2971_DVI_LOCK; /* in */ + data_err-gpios = GP_GS2971_DATA_ERR; /* in */ + lb_cont-gpios = GP_GS2971_LB_CONT; /* in */ + y_1anc-gpios = GP_GS2971_Y_1ANC; /* in */ + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162: rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + /* clock provider */ + #clock-cells = <1>; + clock-frequency = <32678>; + clock-output-names = "rv4162-sqw"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + adv7391: adv7391@2a { + compatible = "adv,mxc_adv739x"; + reg = <0x2a>; + pinctrl-names = "default", "enable"; + pinctrl-0 = <&pinctrl_i2c3_adv7391_off>; + pinctrl-1 = <&pinctrl_i2c3_adv7391_on>; + rst-gpios = GP_ADV7391_RESET; + ipu_id = <0>; + disp_id = <0>; + }; + + max-7w@42 { + compatible = "ublox,max-7w"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_max_7w>; + reset-gpios = GP_GPS_RESET; + /* + * TXD - 6 + * RXD - 7 + * TIMEPULSE - 11 + * EXTINT - 13 + * ANT_ON - 16 + * SDA - 9 + * SCL - 8 + */ + int-pio = <13>; + interrupts-extended = GPIRQ_GPS_EXT; + wakeup-gpios = GP_GPS_EXT; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "j3"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USB_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC1_CD; + wp-gpios = GP_USDHC1_WP; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC2_CD; + wp-gpios = GP_USDHC2_WP; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-1-8-v; + keep-power-in-suspend; + reset-gpios = GP_EMMC_RESET; + status = "okay"; +}; + +&usdhc4 { /* Broadcom GB863021 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cid.dtsi b/arch/arm/boot/dts/imx6qdl-cid.dtsi new file mode 100644 index 00000000000000..5820faad48f063 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cid.dtsi @@ -0,0 +1,1340 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_cid: iomuxc-imx6q-cidgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_cid { + pinctrl_audmux3: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + pinctrl_audmux4: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_backlight_mipi: backlight-mipigrp { + fsl,pins = < +#define GP_BACKLIGHT_MIPI_EN <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 + /* Goes low when USB_OTG_VBUS goes high */ +#define GP_GPIOKEY_OTG_VBUS_STATUS <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Regulators */ +#define GP_3P7_BYPASS_EN <&gpio2 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 +#define GP_3P7_EN <&gpio5 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + /* TODO Wireless control pins */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* main power on/ use pmic_on_req instead */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + /* TP68 */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + /* TP71 */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + /* TP72 */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* TP74 */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + /* TP84 */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + /* TP85 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + /* TP86 */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 + /* TP87 */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + /* TP91 */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + /* TP92 */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + /* TP93 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b0 + /* TP94 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 + /* TP95 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 + /* TP96 */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + /* TP97 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 + /* TP105 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + /* TP106 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 + /* TP110 */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + /* Let max77818 control this directly by turning on/off CHGIN */ + /* + * TP111 on rev 1, + * power enable on rev 0 that should not be used, so keep pull down + */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + /* TP131 */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_pca9546: i2c1_pca9546grp { + fsl,pins = < + /* Select addr 0x70 for pca9546 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x030b0 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 +#define GP_I2C1MUX_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 + >; + }; + + pinctrl_i2c1a_wm8960: i2c1-wm8960grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +#define GP_WM8960_MIC_DET <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +#define GP_WM8960_HP_DET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_i2c1b_mpu9250: i2c3_mpu9250grp { + fsl,pins = < +#define GPIRQ_MPU9250_INT <&gpio6 11 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + >; + }; + + pinctrl_i2c1c_finger_sensor: i2c1-finger-sensorgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +#define GP_FP_CSI0_RESET_N <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b0 +#define GP_FP_SENSOR_STAT <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x0b0b0 +#define GP_FP_LE_EN <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0b0b0 + >; + }; + + pinctrl_i2c1d_ov5640_mipi: i2c1-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_eeprom: i2c2-eepromgrp { + fsl,pins = < +#define GPIRQ_EEPROM_INTR <&gpio2 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 +#define GP_EEPROM_ADDRESS <&gpio2 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x030b0 + >; + }; + + pinctrl_i2c2_rtc: i2c2-rtcgrp { + fsl,pins = < +#define GPIRQ_RTC <&gpio1 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +#define GPIRQ_TAMPER <&gpio4 18 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c2_touch: i2c2-touchgrp { + fsl,pins = < +#define GPIRQ_TOUCH <&gpio4 15 IRQ_TYPE_EDGE_FALLING> +#define GP_TOUCH_IRQ <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +#define GP_TOUCH_RESET <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_lm3643: i2c3_lm3643grp { + fsl,pins = < +#define GP_FLASH_STROBE <&gpio6 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0b0b0 +#define GP_FLASH_HW_EN <&gpio5 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0b0b0 +#define GP_TORCH_EN <&gpio5 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0b0b0 +#define GP_FLASH_TX <&gpio4 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0b0b0 + >; + }; + + pinctrl_i2c3_max77818: i2c3_max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_WCHG_VALID_INT <&gpio2 22 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GPIRQ_MAX77818_WCHG_VALID <&gpio2 21 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GPIRQ_MAX77818_CHG_INT <&gpio2 20 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_LED_VIBRATOR <&gpio5 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x030b0 + /* Blue Led */ +#define GP_STAT_LED1 <&gpio4 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* Green Led */ +#define GP_STAT_LED2 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 + /* Red Led */ +#define GP_STAT_LED3 <&gpio4 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_mipi_dsi_reset: mipi-dsi-resetgrp { + fsl,pins = < +#define GP_MIPI_DSI_RESET <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x030b1 +/* Tearing effect input from the display */ +#define GP_MIPI_TE <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b1 +#define GP_MIPI_ID <&gpio2 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x030b1 + >; + }; + + /* Backlight (MIPI display)*/ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + /* Fingerprint MCLK */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_reg_gps_en: reg-gps-engrp { + fsl,pins = < +#define GP_REG_GPS_EN <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0b0b0 + >; + }; + + pinctrl_reg_nfc: reg-nfcgrp { + fsl,pins = < +#define GP_NFC_PWR_EN <&gpio4 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_reg_2p8v: reg-2p8vgrp { + fsl,pins = < +#define GP_REG_2P8V_EN <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x030b0 + >; + }; + + pinctrl_reg_csi_3p3v: reg-csi-3p3grp { + fsl,pins = < +#define GP_REG_CSI_3P3V_EN <&gpio2 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x030b0 + >; + }; + + pinctrl_reg_csi_5v: reg-csi-5vgrp { + fsl,pins = < +#define GP_REG_CSI_5V_EN <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + /* GPS - MAX-7W */ +#define GP_GPS_HEARTBEAT <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_GPS_INT <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < +#define GPIRQ_WLAN <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_wwan_rfkill: wwan_rfkillgrp { + fsl,pins = < + /* HL7588 - Modem pins */ +#define GP_MODEM_RESET <&gpio4 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x030b0 +/* + * This signal can only turn the modem on, + * pull low for 2 seconds, then release, + * when signal goes low again, the device is ready. + * Use AT*PSCPOF to power off. + */ +#define GP_MODEM_PULSE_ON <&gpio4 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x4001b8b0 /* Open drain, bidirectional signal */ +#define GP_SLEEP_STAT <&gpio4 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 + /* SIM */ +#define GP_SIM_DETECT <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_mipi_dsi = &backlight_mipi_dsi; + fb_mipi_dsi = &fb_mipi_dsi; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_mipi_dsi; + pwm_mipi_dsi = &pwm1; + }; + + backlight_mipi_dsi: backlight_mipi_dsi { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_mipi_dsi>; + enable-gpios = GP_BACKLIGHT_MIPI_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_mipi>; + pwms = <&pwm1 0 30000>; + }; + + bt_rfkill: bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + status = "okay"; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_mipi_dsi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "mipi_dsi"; + interface_pix_fmt = "RGB24"; + mode_str ="OSD050T2844"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + otg_vbus_status { + label = "OTG VBUS status"; + gpios = GP_GPIOKEY_OTG_VBUS_STATUS; + linux,code = ; + gpio-key,wakeup; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + blue { + gpios = GP_STAT_LED1; + default-state = "off"; + }; + + green { + gpios = GP_STAT_LED2; + default-state = "off"; + }; + + red { + gpios = GP_STAT_LED3; + default-state = "off"; + }; + + vibrator { + gpios = GP_LED_VIBRATOR; + default-state = "off"; + linux,default-trigger = "transient"; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + fp_mclk: fp_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "fp_mclk"; + pwms = <&pwm2 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_2p8v: regulator@2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_2P8V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_2p8v>; + reg = <2>; + regulator-name = "2P8V"; + startup-delay-us = <2000>; + }; + + reg_3p3v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_csi_3p3v: regulator@4 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_CSI_3P3V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi_3p3v>; + reg = <4>; + regulator-name = "csi_3p3vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_csi_5v: regulator@5 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_CSI_5V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi_5v>; + reg = <5>; + regulator-name = "csi_5vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_gps_en: regulator@6 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_GPS_EN; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_gps_en>; + regulator-name = "gps-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_nfc: regulator@7 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_NFC_PWR_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_nfc>; + reg = <7>; + regulator-name = "nfc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wlan_en: regulator@8 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_WLAN_EN; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + }; + + sound { + compatible = "fsl,imx6q-cid-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&ssi1>; + audio-codec = <&wm8960>; +#ifdef USE_ASRC + asrc-controller = <&asrc>; +#endif + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB" +#ifdef USE_ASRC + ,"CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture" +#endif + ; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + /* finger_sensor */ + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <0>; + mclk_source = <0>; + status = "okay"; + }; + + /* ov5640_mipi */ + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wwan_rfkill: wwan_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wwan_rfkill>; + name = "wwan_rfkill"; + type = <5>; /* WWAN */ + reset-gpios = GP_MODEM_RESET; + pulse-on-gpios = GP_MODEM_PULSE_ON; + pulse-duration = <2000>; + status = "okay"; + }; +}; + +#ifdef USE_ASRC +&asrc { + status = "okay"; +}; +#endif + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>, <&pinctrl_audmux4>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + i2cmux@70 { + compatible = "pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = GP_I2C1MUX_RESET; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c1@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1b: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1c: i2c1@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1d: i2c1@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + +}; + +&i2c1a { + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1a_wm8960>; + reg = <0x1a>; + clock-names = "mclk"; + wlf,shared-lrclk; + clocks = <&clks IMX6QDL_CLK_CKO>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>; + }; +}; + +&i2c1b { + mpu9250@69 { + compatible = "invn,mpu9250"; + reg = <0x69>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1b_mpu9250>; + inven,vdd_ana-supply = <®_3p3v>; + inven,vcc_i2c-supply = <®_3p3v>; + axis_map_x = <1>; + negate_x = <1>; + axis_map_y = <0>; + negate_y = <0>; + axis_map_z = <2>; + negate_z = <0>; + inven,aux_type = "none"; + inven,secondary_type = "compass"; + inven,secondary_name = "ak8963"; + inven,secondary_reg = <0x0c>; + inven,secondary_axis_map_x = <1>; + inven,secondary_negate_x = <0>; + inven,secondary_axis_map_y = <0>; + inven,secondary_negate_y = <0>; + inven,secondary_axis_map_z = <2>; + inven,secondary_negate_z = <1>; + interrupts-extended = GPIRQ_MPU9250_INT; + }; +}; + +&i2c1c { +#if 0 + finger-sensor@33 { + /* TODO */ + compatible = "dummy_i2c_device"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1c_finger_sensor>; + /* not really 0x33, chose this to let i2cdetect probe the real addresses(0x37/0x60) */ + reg = <0x33>; + clocks = <&fp_mclk>; + clock-names = "fp_mclk"; + c1-supply = <®_csi_3p3v>; + c2-supply = <®_csi_5v>; + reset-gpios = GP_FP_CSI0_RESET_N; + enable-gpios = GP_FP_LE_EN; + }; +#endif +}; + +&i2c1d { + ov5640_mipi: ov5640-mipi@3c { + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1d_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + eeprom@50 { + compatible = "microchip,eeprom"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_eeprom>; + interrupts-extended = GPIRQ_EEPROM_INTR; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rtc>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC; + }; + + atmel_maxtouch@4a { + compatible = "atmel,maxtouch"; + interrupts-extended = GPIRQ_TOUCH; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_touch>; + reg = <0x4a>; + reset-gpios = GP_TOUCH_RESET; + wakeup-gpios = GP_TOUCH_IRQ; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + fan53526@60 { + /* TODO */ + compatible = "fan53526"; + reg = <0x60>; + }; + + lm3643@63 { + compatible = "ti,leds-lm3643"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_lm3643>; + reg = <0x63>; + flash-gpios = GP_FLASH_TX; + hwen-gpios = GP_FLASH_HW_EN; + strobe-gpios = GP_FLASH_STROBE; + torch-gpios = GP_TORCH_EN; + }; + + max77818@66 { + compatible = "maxim,max77823"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_max77818>; + reg = <0x66>; + interrupts-extended = GPIRQ_MAX77818_CHG_INT; + max77823,irq-gpio = GPIRQ_MAX77818_CHG_INT; + max77823,wakeup = <1>; + + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; +}; + +&max77823_battery { + status = "okay"; + battery,vendor = "SDI SDI"; + battery,charger_name = "max77823-charger"; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,bat_irq_attr = <0x3>; + + battery,chip_vendor = "QCOM"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + + battery,polling_time = <10 30 30 30 3600>; + + battery,adc_check_count = <6>; + + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_check; + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + + battery,temp_check_type = <0>; /* SEC_BATTERY_TEMP_CHECK_NONE */ + battery,temp_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_soc = <97>; + battery,full_condition_vcell = <4350000>; + + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <98>; + battery,recharge_condition_vcell = <4350000>; + + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + boost = <1>; + battery,chg_gpio_en = <0>; + battery,chg_polarity_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_status = <0>; + battery,chg_float_voltage = <4400>; + battery,ovp_uvlo_check_type = <4>; /* SEC_BATTERY_OVP_UVLO_CHGINT */ + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 760 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 900 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 2100>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + + regulators { + reg_usbotg_vbus: otg { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&max77823_fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + fuelgauge,capacity_mAh = <6400>; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,fuel_alert_soc = <1>; + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + /* fuelgauge,repeated_fuelalert; */ + temp-disabled; + temp-calibration = <0 (-6763) 9858>; + /* if temp-calibration defined, temp-calibration-data not used */ + temp-calibration-data = <250 0x7cde + 255 0x7c50 + 260 0x7aa0 + 265 0x792e + 270 0x788e + 275 0x7714 + 280 0x761a + 285 0x7536 + 290 0x73ca + 295 0x7326 + 300 0x726c + 305 0x71cc + 310 0x71b2 + 315 0x70a4 + 320 0x6f6a + 325 0x6eae + 330 0x6a2e + 335 0x6800 + 340 0x673c + 345 0x665a + 350 0x65b4 + 355 0x6478 + 360 0x6318 + 365 0x6270 + 370 0x614e + 375 0x5f56 + 380 0x5ed2 + 385 0x5d9e + 390 0x5b38 + 395 0x5ae0 + 400 0x59ce + 405 0x57b2 + 410 0x55f2 + 415 0x53c2 + 420 0x505a>; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <0>; + disp-power-on-supply = <®_2p8v>; + lcd_panel = "OSD050T2844"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-names = "default"; + reset-delay-us = <50>; + reset-gpios = GP_MIPI_DSI_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + /* USB Modem */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + /* GPS - max-7w */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; + id = <1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cid_tab.dtsi b/arch/arm/boot/dts/imx6qdl-cid_tab.dtsi new file mode 100644 index 00000000000000..822ab17581f345 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cid_tab.dtsi @@ -0,0 +1,1433 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_cid_tab: iomuxc-imx6q-cid_tabgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_cid_tab { + + /* Goes to the WM8960 */ + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + /* Goes to the WWAN USB Modem */ + pinctrl_audmux4: audmux4grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_backlight_lvds: backlight-lvdsgrp { + fsl,pins = < +#define GP_BACKLIGHT_LVDS_EN <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x030b0 +#define GP_BACKLIGHT_LVDS_PWM1 <&gpio1 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x030b0 +#define GP_LVDS_LED_EN <&gpio4 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x030b0 +#define GP_LVDS_BIST <&gpio5 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x030b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_RGMII_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio3 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio3 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_GPIO_A <&gpio3 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 +#define GP_GPIO_B <&gpio4 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 + /* WWAN 3.7V Regulator */ +#define GP_3P7_EN <&gpio5 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 +#define GP_3P7_BYPASS_EN <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + +#define GPIRQ_TAMPER <&gpio4 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + /* TODO Wireless control pins */ +#define GP_BT_CLK_REQ <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 +#define GP_BT_HOST_WAKE <&gpio6 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 +#define GP_WIFI_QOW <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* TP68 */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + /* TP71 */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + /* TP72 */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* TP73 */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* TP74 */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + /* TP78 */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + /* TP85 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + /* TP86 */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 + /* TP90 */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* TP91 */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + /* TP92 */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + /* TP97 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* TP104 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 + /* TP131 */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + /* TP_R368 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_pca9546: i2c1_pca9546grp { + fsl,pins = < + /* Select addr 0x70 for pca9546 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x030b0 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 +#define GP_I2C1MUX_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 + >; + }; + + pinctrl_i2c1a_wm8960: i2c1a-wm8960grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 +#define GP_WM8960_MIC_DET <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +#define GP_WM8960_HP_DET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_i2c1b_mpu9250: i2c1b_mpu9250grp { + fsl,pins = < +#define GPIRQ_MPU9250_INT <&gpio6 11 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + >; + }; + + pinctrl_i2c1c_finger_sensor: i2c1-finger-sensorgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 +#define GP_FP_RESET_N <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 +#define GP_FP_SENSOR_STAT <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b0 +#define GP_FP_LE_EN <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x0b0b0 + >; + }; + + pinctrl_i2c1d_ov5640_mipi: i2c1d-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gt928: i2c2_gt928grp { + fsl,pins = < +#define GPIRQ_GT928 <&gpio4 15 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT928_IRQ <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 +#define GP_GT928_RESET <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x030b0 + >; + }; + + pinctrl_i2c2_lightsensor: i2c2-lightsensorgrp { + fsl,pins = < +#define GPIRQ_LIGHTSENSOR <&gpio3 0 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2_rtc: i2c2-rtcgrp { + fsl,pins = < +#define GPIRQ_RTC <&gpio1 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_lm3643: i2c3_lm3643grp { + fsl,pins = < +#define GP_FLASH_STROBE <&gpio2 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 +#define GP_FLASH_HW_EN <&gpio5 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0b0b0 +#define GP_TORCH_EN <&gpio5 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0b0b0 +#define GP_FLASH_TX <&gpio4 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0b0b0 + >; + }; + + pinctrl_i2c3_max77818: i2c3_max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_INOK <&gpio5 13 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 +#define GPIRQ_MAX77818_WCINOK <&gpio3 2 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GPIRQ_MAX77818 <&gpio3 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_LED_VIBRATOR <&gpio5 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x030b0 + /* Blue Led */ +#define GP_STAT_LED1 <&gpio4 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* Green Led */ +#define GP_STAT_LED2 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 + /* Red Led */ +#define GP_STAT_LED3 <&gpio4 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + /* Fingerprint MCLK */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + /* Backlight (LVDS display)*/ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_2p8v: reg-2p8vgrp { + fsl,pins = < +#define GP_REG_2P8V_EN <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x030b0 + >; + }; + + pinctrl_reg_fp_3p3v: reg-fp-3p3grp { + fsl,pins = < +#define GP_REG_FP_3P3V_EN <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 + >; + }; + + pinctrl_reg_fp_5v: reg-fp-5vgrp { + fsl,pins = < +#define GP_REG_FP_5V_EN <&gpio6 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_vbus4: reg-vbus4grp { + fsl,pins = < +#define GP_REG_VBUS4 <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + /* GPS - MAX-7W */ +#define GP_GPS_HEARTBEAT <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_GPS_INT <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0b0b0 +#define GP_GPS_RESET <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x030b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x130b0 + >; + }; + + /* Wifi */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 +#define GPIRQ_WLAN <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 +#define GP_WIFI_WAKE <&gpio2 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + + pinctrl_wwan_rfkill: wwan_rfkillgrp { + fsl,pins = < + /* HL7588 - Modem pins */ +#define GP_MODEM_RESET <&gpio4 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x030b0 +/* + * This signal can only turn the modem on, + * pull low for 2 seconds, then release, + * when signal goes low again, the device is ready. + * Use AT*PSCPOF to power off. + */ +#define GP_MODEM_PULSE_ON <&gpio4 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x4001b8b0 /* Open drain, bidirectional signal */ +#define GP_SLEEP_STAT <&gpio4 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 +#define GP_SIM_DETECT <&gpio3 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 +#define GP_SIM_IO <&gpio5 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm3; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + enable-gpios = GP_BACKLIGHT_LVDS_EN, GP_BACKLIGHT_LVDS_PWM1, GP_LVDS_LED_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds>; + pwms = <&pwm3 0 50000>; + }; + + bt_rfkill: bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "bt_rfkill"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + reset-gpios = GP_BT_RFKILL_RESET; + status = "okay"; + type = <2>; /* bluetooth */ + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + default_bpp = <16>; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + linux,code = ; + gpios = GP_GPIOKEY_POWER; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + linux,code = ; + gpios = GP_GPIOKEY_VOL_DN; + }; + + volume-up { + label = "Volume Up"; + linux,code = ; + gpios = GP_GPIOKEY_VOL_UP; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + blue { + gpios = GP_STAT_LED1; + default-state = "off"; + }; + + green { + gpios = GP_STAT_LED2; + default-state = "off"; + }; + + red { + gpios = GP_STAT_LED3; + default-state = "off"; + }; + + vibrator { + gpios = GP_LED_VIBRATOR; + default-state = "off"; + linux,default-trigger = "transient"; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + fp_mclk: fp_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "fp_mclk"; + pwms = <&pwm2 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "1P8V"; + }; + + reg_2p8v: regulator@1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_2P8V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_2p8v>; + reg = <1>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "2P8V"; + startup-delay-us = <2000>; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3P3V"; + }; + + reg_fp_3p3v: regulator@3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_FP_3P3V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_fp_3p3v>; + reg = <3>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "csi_3p3vbus"; + }; + + reg_fp_5v: regulator@4 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_FP_5V_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_fp_5v>; + reg = <4>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "csi_5vbus"; + }; + + reg_usbotg_vbus: regulator@5 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_USBOTG; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + reg = <5>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; + }; + + reg_vbus4: regulator@6 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_VBUS4; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vbus4>; + reg = <6>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vbus4"; + }; + + reg_wlan_en: regulator@7 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_WLAN_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + reg = <7>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "wlan-en"; + startup-delay-us = <70000>; + }; + }; + + sim_clk: sim_clk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <2500000>; + clock-output-names = "sim_clk"; + pwms = <&pwm4 0 400>; /* 1 / 400 ns = 2.5 MHz */ + }; + + sound { + compatible = "fsl,imx6q-cid-tab-wm8960", + "fsl,imx-audio-wm8960"; +#ifdef USE_ASRC + asrc-controller = <&asrc>; +#endif + audio-codec = <&wm8960>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB" +#ifdef USE_ASRC + ,"CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture" +#endif + ; + codec-master; + cpu-dai = <&ssi1>; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + model = "wm8960-audio"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + /* finger_sensor */ + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <0>; + ipu_id = <0>; + mclk_source = <0>; + mipi_camera = <0>; + status = "okay"; + }; + + /* ov5640 */ + v4l2_cap_1: v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <1>; + ipu_id = <0>; + mclk_source = <0>; + mipi_camera = <0>; + status = "okay"; + }; + + /* ov5640_mipi */ + v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <1>; + ipu_id = <0>; + mclk_source = <0>; + mipi_camera = <1>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wwan_rfkill: wwan_rfkill { + compatible = "net,rfkill-gpio"; + name = "wwan_rfkill"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wwan_rfkill>; + pulse-duration = <2000>; + pulse-on-gpios = GP_MODEM_PULSE_ON; + reset-gpios = GP_MODEM_RESET; + status = "okay"; + type = <5>; /* WWAN */ + }; +}; + +#ifdef USE_ASRC +&asrc { + status = "okay"; +}; +#endif + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>, <&pinctrl_audmux4>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = GP_ECSPI1_NOR_CS; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + cs-gpios = GP_ECSPI2_CS; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_RGMII_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + interrupts-extended = GPIRQ_ENET_PHY; + reg = <6>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + i2cmux@70 { + compatible = "pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = GP_I2C1MUX_RESET; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c1@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1b: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1c: i2c1@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1d: i2c1@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + +}; + +&i2c1a { + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "mclk"; + clocks = <&clks IMX6QDL_CLK_CKO>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1a_wm8960>; + reg = <0x1a>; + wlf,shared-lrclk; + }; +}; + +&i2c1b { + mpu9250@69 { + compatible = "invn,mpu9250"; + axis_map_x = <1>; + negate_x = <1>; + axis_map_y = <0>; + negate_y = <1>; + axis_map_z = <2>; + negate_z = <1>; + interrupts-extended = GPIRQ_MPU9250_INT; + inven,aux_type = "none"; + inven,secondary_type = "compass"; + inven,secondary_name = "ak8963"; + inven,secondary_reg = <0x0c>; + inven,secondary_axis_map_x = <0>; + inven,secondary_negate_x = <1>; + inven,secondary_axis_map_y = <1>; + inven,secondary_negate_y = <1>; + inven,secondary_axis_map_z = <2>; + inven,secondary_negate_z = <0>; + inven,vdd_ana-supply = <®_3p3v>; + inven,vcc_i2c-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1b_mpu9250>; + reg = <0x69>; + }; +}; + +&i2c1c { +#if 1 + finger-sensor@33 { + /* TODO */ + compatible = "dummy_i2c_device"; + c1-supply = <®_fp_3p3v>; + c2-supply = <®_fp_5v>; + clock-names = "fp_mclk"; + clocks = <&fp_mclk>; + enable-gpios = GP_FP_LE_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1c_finger_sensor>; + /* not really 0x33, chose this to let i2cdetect probe the real addresses(0x37/0x60) */ + reg = <0x33>; + reset-gpios = GP_FP_RESET_N; + }; +#endif +}; + +&i2c1d { + ov5640_mipi: ov5640-mipi@3c { + compatible = "ovti,ov5640_mipi"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + AVDD-supply = <®_2p8v>; + clock-names = "csi_mclk"; + clocks = <&clks IMX6QDL_CLK_CKO2>; + csi_id = <1>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + ipu_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1d_ov5640_mipi>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + reg = <0x3c>; + rst-gpios = GP_OV5640_MIPI_RESET; + mirror = <0>; + vflip = <1>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + gt928@14 { + compatible = "goodix,gt928"; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT928; + irq-gpios = GP_GT928_IRQ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_gt928>; + reg = <0x14>; + reset-gpios = GP_GT928_RESET; + touchscreen-swapped-x-y; + }; + + lightsensor@29 { + compatible = "apds9300"; + interrupts-extended = GPIRQ_LIGHTSENSOR; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_lightsensor>; + reg = <0x29>; + }; + + ov5640: ov5640@3c { + compatible = "ov5640_int"; + AVDD-supply = <®_2p8v>; + csi_id = <1>; + clock-names = "csi_mclk"; + clocks = <&clks IMX6QDL_CLK_CKO2>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640>; + pwn-gpios = GP_OV5640_POWER_DOWN; + reg = <0x3c>; + rst-gpios = GP_OV5640_RESET; + mirror = <0>; + vflip = <1>; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + interrupts-extended = GPIRQ_RTC; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rtc>; + reg = <0x68>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + /* VCC - 1.2V - VDDARM / VDDSOC */ + fan53526@60 { + compatible = "fan53526"; + reg = <0x60>; + }; + + lm3643@63 { + compatible = "ti,leds-lm3643"; + flash-gpios = GP_FLASH_TX; + hwen-gpios = GP_FLASH_HW_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_lm3643>; + reg = <0x63>; + strobe-gpios = GP_FLASH_STROBE; + torch-gpios = GP_TORCH_EN; + }; + + max77818@66 { + compatible = "maxim,max77823"; + interrupts-extended = GPIRQ_MAX77818; + max77823,irq-gpio = GPIRQ_MAX77818; + max77823,wakeup = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_max77818>; + reg = <0x66>; + + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <72000000>; + hactive = <1280>; + hback-porch = <48>; + hfront-porch = <80>; + hsync-len = <32>; + vactive = <800>; + vback-porch = <15>; + vfront-porch = <2>; + vsync-len = <6>; + }; + }; + }; +}; + +&max77823_battery { + battery,adc_check_count = <6>; + battery,bat_irq_attr = <0x3>; + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,charger_name = "max77823-charger"; + battery,charging_reset_time = <0>; + battery,charging_total_time = <21600>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + battery,check_count = <0>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + battery,chip_vendor = "QCOM"; + battery,event_check; + battery,event_waiting_time = <600>; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,full_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_condition_soc = <97>; + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_vcell = <4350000>; + battery,monitor_initial_count = <3>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,polling_time = <10 30 30 30 3600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,recharge_check_count = <1>; + battery,recharge_condition_soc = <98>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_vcell = <4350000>; + battery,recharging_total_time = <5400>; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + battery,temp_check_count = <1>; + battery,temp_check_type = <0>; /* SEC_BATTERY_TEMP_CHECK_NONE */ + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + battery,vendor = "SDI SDI"; + status = "okay"; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + battery,chg_float_voltage = <4400>; + battery,chg_gpio_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_en = <0>; + battery,chg_polarity_status = <0>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 2100 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 2100>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 4000 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,ovp_uvlo_check_type = <4>; /* SEC_BATTERY_OVP_UVLO_CHGINT */ + boost = <1>; + + regulators { + otg { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&max77823_fuelgauge { + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,capacity_mAh = <8000>; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,fuel_alert_soc = <1>; + temp-calibration = <0 (-6763) 9858>; + /* if temp-calibration defined, temp-calibration-data not used */ + temp-calibration-data = <250 0x7cde + 255 0x7c50 + 260 0x7aa0 + 265 0x792e + 270 0x788e + 275 0x7714 + 280 0x761a + 285 0x7536 + 290 0x73ca + 295 0x7326 + 300 0x726c + 305 0x71cc + 310 0x71b2 + 315 0x70a4 + 320 0x6f6a + 325 0x6eae + 330 0x6a2e + 335 0x6800 + 340 0x673c + 345 0x665a + 350 0x65b4 + 355 0x6478 + 360 0x6318 + 365 0x6270 + 370 0x614e + 375 0x5f56 + 380 0x5ed2 + 385 0x5d9e + 390 0x5b38 + 395 0x5ae0 + 400 0x59ce + 405 0x57b2 + 410 0x55f2 + 415 0x53c2 + 420 0x505a>; + /* fuelgauge,repeated_fuelalert; */ + temp-disabled; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + /* TP138, TP139 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&uart2 { + /* J61, J65, pins 14, 15 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + /* Bluetooth */ + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + /* J65, pins 10, 11 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + /* GPS - max-7w */ + control-gpios = GP_GPS_RESET; +#define M_RESET 1 + off_levels = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + rs232_levels = ; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; + vbus-supply = <®_vbus4>; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; + vbus-supply = <®_usbotg_vbus>; +}; + +&usdhc2 { + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + status = "okay"; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; +}; + +&usdhc3 { + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + status = "okay"; + vmmc-supply = <®_3p3v>; +}; + +&usdhc4 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + reset-gpios = GP_EMMC_RESET; + status = "okay"; + vmmc-supply = <®_1p8v>; + vqmmc-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cnt.dtsi b/arch/arm/boot/dts/imx6qdl-cnt.dtsi new file mode 100644 index 00000000000000..bc7c0a7ad252c0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cnt.dtsi @@ -0,0 +1,537 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_cnt: iomuxc-imx6q-cntgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_cnt { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ +#define GP_FAKE_POWEROFF <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_mma8653: i2c2_mma8653grp { + fsl,pins = < +#define GPIRQ_MMA8653 <&gpio2 3 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_i2c2_nfc: i2c2_nfcgrp { + fsl,pins = < +#define GP_NFC_ENABLE <&gpio2 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GPIRQ_NFC <&gpio2 2 IRQ_TYPE_NONE> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_maxtouch: i2c3_maxtouchgrp { + fsl,pins = < +#define GPIRQ_MAXTOUCH <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_MAXTOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ +#define GP_MAXTOUCH_RESET <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + pwms = <&pwm4 0 50000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fake_poweroff { + compatible = "fake-poweroff"; + gpios = GP_FAKE_POWEROFF; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-cnt-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + accelerometer@1d { + compatible = "fsl,mma8653"; + reg = <0x1d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_mma8653>; + position = <0>; + interrupts-extended = GPIRQ_MMA8653; + interrupt-route = <1>; + }; + + nfc@28 { + compatible = "nxp,pn547"; + reg = <0x28>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_nfc>; + clock-frequency = <400000>; + interrupt-gpios = GPIRQ_NFC; + enable-gpios = GP_NFC_ENABLE; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_maxtouch>; + interrupts-extended = GPIRQ_MAXTOUCH; + atmel,reset-gpio = GP_MAXTOUCH_RESET; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + cd-gpios = GP_USDHC4_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cob.dtsi b/arch/arm/boot/dts/imx6qdl-cob.dtsi new file mode 100644 index 00000000000000..1082f28d396810 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cob.dtsi @@ -0,0 +1,569 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_cob: iomuxc-imx6q-cobgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_cob { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEYS_MENU <&gpio1 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +#define GP_GPIOKEYS_HOME <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_GPIOKEYS_PB1_I <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GP_GPIOKEYS_PB2_I <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < +#define GP_GPIOLEDS_1 <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0b0b0 +#define GP_GPIOLEDS_2 <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HEATER_EN <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 +#define GP_LCD_DAY_BACKLIGHT_EN <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0b0b0 +#define GP_LCD_NIGHT_BACKLIGHT_EN <&gpio4 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x0b0b0 + +#define GP_TX <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_RX <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + +#define GP_HEATER_FAULT <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + +#define GP_DA1_OUTA <&gpio3 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 +#define GP_DA1_OUTB <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 +#define GP_DB1_OUTA <&gpio3 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GP_DB1_OUTB <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_DA2_OUTA <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GP_DA2_OUTB <&gpio3 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_DB2_OUTA <&gpio3 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_DB2_OUTB <&gpio3 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 + +#define GP_HOG_TP5 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +#define GP_HOG_TP6 <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +#define GP_HOG_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_HOG_TP72 <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +#define GP_HOG_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 +#define GP_HOG_TP75 <&gpio1 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 +#define GP_HOG_TP76 <&gpio1 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x1b0b0 +#define GP_HOG_TP78 <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +#define GP_HOG_TP79 <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_crtouch: i2c3-crtouchgrp { + fsl,pins = < +#define GPIRQ_I2C3_CRTOUCH <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_CRTOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + +#define GP_I2C3_CRTOUCH_WAKE <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_I2C3_CRTOUCH_RESET <&gpio2 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x130b0 + + >; + }; + + pinctrl_lcd0: lcd0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_SOURCE <&gpio2 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 +#define GP_USBH1_FP_OC <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd_day; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc4; + mxcfb0 = &fb_lcd; + pwm_lcd = &pwm1; + }; + + backlight_lcd_day: backlight_lcd_day { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + default-brightness-level = <5>; + compatible = "pwm-backlight"; + display = <&fb_lcd>; + pwms = <&pwm1 0 3333333>; + }; + + backlight_lcd_night { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + default-brightness-level = <0>; + compatible = "pwm-backlight"; + display = <&fb_lcd>; + pwms = <&pwm2 0 3333333>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + menu { + label = "Menu"; + gpios = GP_GPIOKEYS_MENU; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEYS_HOME; + linux,code = ; + }; + + pb1 { + label = "PB1_I"; + gpios = GP_GPIOKEYS_PB1_I; + linux,code = ; + }; + + pb2 { + label = "PB2_I"; + gpios = GP_GPIOKEYS_PB2_I; + linux,code = ; + }; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + led1 { + gpios = GP_GPIOLEDS_1; + retain-state-suspended; + default-state = "off"; + }; + led2 { + gpios = GP_GPIOLEDS_2; + retain-state-suspended; + default-state = "off"; + }; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str ="DC050WX"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ads1000@49 { + compatible = "ti,ads1000"; + reg = <0x49>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + crtouch@49 { + compatible = "crtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_crtouch>; + reg = <0x49>; +#if 0 + interrupts-extended = GPIRQ_I2C3_CRTOUCH; + wakeup-gpios = GP_I2C3_CRTOUCH; +#endif + reset-gpios = GP_I2C3_CRTOUCH_RESET; + wake-gpios = GP_I2C3_CRTOUCH_WAKE; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USBH1_SOURCE; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cob2.dtsi b/arch/arm/boot/dts/imx6qdl-cob2.dtsi new file mode 100644 index 00000000000000..02110841ba979b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cob2.dtsi @@ -0,0 +1,801 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_cob2: iomuxc-imx6q-cob2grp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_cob2 { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x100b1 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x100b1 +#define GP_ECSPI5_CS0 <&gpio5 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 +#define GP_ECSPI5_CS1 <&gpio5 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEYS_MENU <&gpio1 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +#define GP_GPIOKEYS_HOME <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_GPIOKEYS_PB1_I <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GP_GPIOKEYS_PB2_I <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +#define GP_GPIOKEYS_SW2 <&gpio3 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 +#define GP_GPIOKEYS_A <&gpio3 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b0 +#define GP_GPIOKEYS_B <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 +#define GP_GPIOKEYS_EXP_RDY <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 +#define GP_GPIOKEYS_DAY_BL_OPEN <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_GPIOKEYS_DAY_BL_SHORT <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_GPIOKEYS_NIGHT_BL_OPEN <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 +#define GP_GPIOKEYS_NIGHT_BL_SHORT <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < +#define GP_GPIOLEDS_1 <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0b0b0 +#define GP_GPIOLEDS_2 <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HEATER_EN <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 +#define GP_LCD_DAY_BACKLIGHT_EN <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0b0b0 +#define GP_LCD_NIGHT_BACKLIGHT_EN <&gpio4 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x0b0b0 +#define GP_EXPAN_EN <&gpio3 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x030b0 + +#define GP_TX <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_RX <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + +#define GP_HEATER_FAULT <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + +#define GP_DA1_OUTA <&gpio3 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 +#define GP_DA1_OUTB <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 +#define GP_DB1_OUTA <&gpio3 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GP_DB1_OUTB <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_DA2_OUTA <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GP_DA2_OUTB <&gpio3 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_DB2_OUTA <&gpio3 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_DB2_OUTB <&gpio3 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 +#define GP_DIS_FPGA_RESET <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 +#define GP_I2C_DIG_SEL <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +#define GP_FPGA_READY <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + +#define GP_HOG_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_HOG_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 +#define GP_HOG_TP78 <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +#define GP_TP79 <&gpio7 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b0 +#define GP_TP80 <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 +#define GP_TP81 <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_crtouch: i2c3-crtouchgrp { + fsl,pins = < +#define GPIRQ_I2C3_CRTOUCH <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_CRTOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + +#define GP_I2C3_CRTOUCH_WAKE <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_I2C3_CRTOUCH_RESET <&gpio2 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x130b0 + + >; + }; + + pinctrl_lcd0: lcd0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x100b0 + >; + }; + + pinctrl_uart2_j57: uart2-j57grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x100b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_SOURCE <&gpio2 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 +#define GP_USBH1_FP_OC <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USBH1_HUB_RESET <&gpio2 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x130b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd_day; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc4; + mxcfb0 = &fb_lcd; + pwm_lcd = &pwm1; + }; + + backlight_lcd_day: backlight_lcd_day { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <5>; + display = <&fb_lcd>; + pwms = <&pwm1 0 3333333>; + }; + + backlight_lcd_night { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <0>; + display = <&fb_lcd>; + pwms = <&pwm2 0 3333333>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + menu { + gpios = GP_GPIOKEYS_MENU; + label = "Menu"; + linux,code = ; + }; + + home { + gpios = GP_GPIOKEYS_HOME; + label = "Home"; + linux,code = ; + }; + + pb1 { + gpios = GP_GPIOKEYS_PB1_I; + label = "PB1_I"; + linux,code = ; + }; + + pb2 { + gpios = GP_GPIOKEYS_PB2_I; + label = "PB2_I"; + linux,code = ; + }; + + sw2 { + gpios = GP_GPIOKEYS_SW2; + label = "sw2"; + linux,code = ; + }; + + a { + gpios = GP_GPIOKEYS_A; + label = "a"; + linux,code = ; + }; + + b { + gpios = GP_GPIOKEYS_B; + label = "b"; + linux,code = ; + }; + + exp_rdy { + gpios = GP_GPIOKEYS_EXP_RDY; + label = "exp_rdy"; + linux,code = ; + }; + + day_bl_open { + gpios = GP_GPIOKEYS_DAY_BL_OPEN; + label = "day_bl_open"; + linux,code = ; + }; + + day_bl_short { + gpios = GP_GPIOKEYS_DAY_BL_SHORT; + label = "day_bl_short"; + linux,code = ; + }; + + night_bl_open { + gpios = GP_GPIOKEYS_NIGHT_BL_OPEN; + label = "night_bl_open"; + linux,code = ; + }; + + night_bl_short { + gpios = GP_GPIOKEYS_NIGHT_BL_SHORT; + label = "night_bl_short"; + linux,code = ; + }; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + default-state = "off"; + gpios = GP_GPIOLEDS_1; + retain-state-suspended; + }; + led2 { + default-state = "off"; + gpios = GP_GPIOLEDS_2; + retain-state-suspended; + }; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + default_bpp = <16>; + disp_dev = "lcd"; + int_clk = <0>; + interface_pix_fmt = "RGB24"; + late_init = <0>; + mode_str ="DC050WX"; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + default_ifmt = "RGB24"; + disp_id = <0>; + ipu_id = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "1P8V"; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "2P5V"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3P3V"; + }; + + reg_usbotg_vbus: regulator-usbotg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_REG_USBOTG; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + cs-gpios = GP_ECSPI1_NOR_CS; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + reg = <0>; + spi-max-frequency = <20000000>; + + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi5 { + cs-gpios = GP_ECSPI5_CS0, GP_ECSPI5_CS1; + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ads1000@49 { + compatible = "ti,ads1000"; + reg = <0x49>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + crtouch@49 { + compatible = "crtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_crtouch>; + reg = <0x49>; +#if 0 + interrupts-extended = GPIRQ_I2C3_CRTOUCH; + wakeup-gpios = GP_I2C3_CRTOUCH; +#endif + reset-gpios = GP_I2C3_CRTOUCH_RESET; + wake-gpios = GP_I2C3_CRTOUCH_WAKE; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default", "alt1"; + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-1 = <&pinctrl_uart2_j57>; + status = "okay"; +}; + +&uart3 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USBH1_HUB_RESET, GP_USBH1_SOURCE; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; + vbus-supply = <®_usbotg_vbus>; +}; + +&usdhc2 { /* uSDHC2, sdio */ + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + status = "okay"; + vmmc-supply = <®_3p3v>; +}; + +&usdhc4 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + reset-gpios = GP_EMMC_RESET; + status = "okay"; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i-vendor.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i-vendor.dtsi new file mode 100644 index 00000000000000..9ccad4cba87c8a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-cubox-i-vendor.dtsi @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + mxcfb0 = &mxcfb1; + }; + + chosen { + bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 9 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_ir>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_key>; + pinctrl-names = "default"; + + button_0 { + label = "Button 0"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_hdmi>; + status = "okay"; +}; + +&i2c2 { + ddc@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + nxp,12p5_pf; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index ff41f83551de6e..ae735d941e75e3 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -38,8 +38,6 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" #include #include @@ -64,38 +62,36 @@ }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; }; sound-spdif { @@ -139,7 +135,7 @@ status = "okay"; - rtc: pcf8523@68 { + rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; @@ -243,21 +239,25 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usbh1>; - vbus-supply = <®_usbh1_vbus>; + vbus-supply = <&v_usb2>; status = "okay"; }; &usbotg { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usbotg>; - vbus-supply = <®_usbotg_vbus>; + vbus-supply = <&v_usb1>; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&vcc_3v3 { + vin-supply = <&v_5v0>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-eo.dtsi b/arch/arm/boot/dts/imx6qdl-eo.dtsi new file mode 100644 index 00000000000000..8172a80fde1b4a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-eo.dtsi @@ -0,0 +1,747 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_eo: iomuxc-imx6q-eogrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_eo { + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_ACC_INT2 <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x000b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3MUX_A <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x030b0 /* pcie i2c enable */ + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 /* pcie reset */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + backlight_lvds2 = &backlight_lvds2; + fb_lvds = &fb_lvds; + fb_lvds2 = &fb_lvds2; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb1 = &fb_lvds; + mxcfb3 = &fb_lvds2; + pwm_lvds = &pwm4; + pwm_lvds2 = &pwm2; + t_lvds = &t_lvds; + t_lvds2 = &t_lvds2; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + debug; + }; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds2: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + backlight_pwm1: backlight_pwm1 { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + backlight_lvds2: backlight_lvds2 { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds2>; + pwms = <&pwm2 0 5000000>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + i2cmux@3 { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C3MUX_A; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3a: i2c3@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; +}; + +&ldb { + split-mode = <1>; + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lvds1080p values may be changed in bootscript */ + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>; + hfront-porch = <88>; + vback-porch = <36>; + vfront-porch = <4>; + hsync-len = <44>; + vsync-len = <5>; + }; + lg1280x800: lp101wx1 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + crtc = "ipu1-di0"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + t_lvds2: t_lvds2_default { + /* lg1280x800_2 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600_2: okaya7x0WP_2 { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar_2: hsd100pxn1_2 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index afec2c7628ef5d..02cab60f133a7b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2013 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -19,6 +21,7 @@ nand = &gpmi; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -89,6 +92,17 @@ enable-active-high; }; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &fec { @@ -105,8 +119,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -165,6 +186,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &pcie { diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index a7100f99123e95..45ef098793beb4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2013 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -21,6 +23,7 @@ ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -124,6 +127,17 @@ }; }; + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + sound { compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -180,8 +194,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -249,6 +270,11 @@ VDDIO-supply = <®_3p3v>; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 8953eba0573daa..452ba93a3e2c4e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2013 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -22,6 +24,7 @@ ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -138,6 +141,17 @@ mux-int-port = <1>; mux-ext-port = <4>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -173,8 +187,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -242,6 +263,11 @@ VDDIO-supply = <®_3p3v>; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 6ac41c7ed32e03..4c6c1b92b5a671 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2013 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -22,6 +24,7 @@ ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -128,6 +131,17 @@ mux-int-port = <1>; mux-ext-port = <4>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -163,8 +177,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -333,6 +354,11 @@ VDDIO-supply = <®_3p3v>; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 805e23674a9472..ff0da13f649a19 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2014 Gateworks Corporation * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -20,6 +22,7 @@ nand = &gpmi; usb0 = &usbh1; usb1 = &usbotg; + mxcfb0 = &mxcfb1; }; chosen { @@ -87,6 +90,17 @@ regulator-always-on; }; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &gpmi { @@ -95,8 +109,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c3>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -155,6 +176,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &pcie { diff --git a/arch/arm/boot/dts/imx6qdl-h4.dtsi b/arch/arm/boot/dts/imx6qdl-h4.dtsi new file mode 100644 index 00000000000000..1ffa66f0348563 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-h4.dtsi @@ -0,0 +1,903 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_h4: iomuxc-imx6q-h4grp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_h4 { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_audmux5: audmux5grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +#define GP_ECSPI2_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_GPIOKEY_1 <&gpio3 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 +#define GP_GPIOKEY_2 <&gpio3 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 +#define GP_GPIOKEY_3 <&gpio3 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 +#define GP_VBUS_GOOD <&gpio3 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 +#define GP_SPARE <&gpio1 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_MAIN_POWER_EN <&gpio1 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 +#define GP_TP4 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 +#define GP_TP5 <&gpio4 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 +#define GP_TP6 <&gpio1 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x1b0b0 +#define GP_TP7 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP8 <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 +#define GP_TP9 <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 +#define GP_TP10 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_wm8960: i2c1-wm8960grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_tc358743_mipi: i2c2-tc358743_mipigrp { + fsl,pins = < +#define GP_TC3587_RESET <&gpio6 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x030b0 +#define GPIRQ_TC3587 <&gpio6 0 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0b0b0 +#define GP_HDMI_POWER_DET <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_J8 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_J8 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 +#define GP_J8_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_max77818: i2c3_max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_INOKB <&gpio3 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GPIRQ_MAX77818_WCINOKB <&gpio3 5 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GPIRQ_MAX77818_INTB <&gpio3 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + /* lcd backlight */ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + /* spi lcd backlight */ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_reg_5v: reg-5vgrp { + fsl,pins = < +#define GP_REG_5V <&gpio3 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x030b0 + >; + }; + + pinctrl_reg_usbh1_vbus: reg-usbh1-vbusgrp { + fsl,pins = < +#define GP_REG_USBH1 <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + /* Murata wifi */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < +#define GPIRQ_WLAN <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x100b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + mxcfb0 = &fb_lcd; + pwm_lcd = &pwm1; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_spi_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm3 0 5000000>; + }; +/* + backlight_spare: backlight_spare { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + pwms = <&pwm2 0 5000000>; + }; +*/ + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_5v>; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_5V; + enable-active-high; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbh1_vbus>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBH1; + enable-active-high; + }; + + reg_usbotg_vbus: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-h4-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&ssi1>; + audio-codec = <&wm8960>; +#ifdef USE_ASRC + asrc-controller = <&asrc>; +#endif + codec-master; + hp-det = <4 0>; + audio-routing = + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN" +#ifdef USE_ASRC + ,"CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture" +#endif + ; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wlan { + compatible = "murata"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupts-extended = GPIRQ_WLAN; + }; +}; + +#ifdef USE_ASRC +&asrc { + status = "okay"; +}; +#endif + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_IPU2_SEL>, <&clks IMX6QDL_CLK_IPU2_PODF>, <&clks IMX6QDL_CLK_CKO2_PODF>, <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD1_540M>, <&clks IMX6QDL_CLK_IPU2_SEL>, <&clks IMX6QDL_CLK_CKO2_SEL>, <&clks IMX6QDL_CLK_IPU2>; + assigned-clock-rates = <0>, <135000000>, <27000000>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_wm8960>; + reg = <0x1a>; + clock-names = "mclk"; + wlf,shared-lrclk; + clocks = <&clks IMX6QDL_CLK_CKO>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO1_SEL>, <&clks IMX6QDL_CLK_CKO1_PODF>, <&clks IMX6QDL_CLK_CKO>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, <&clks IMX6QDL_CLK_CKO1_SEL>, <&clks IMX6QDL_CLK_CKO1>; + assigned-clock-rates = <0>, <12000000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_tc358743_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = GP_TC3587_RESET; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_J8; + wakeup-gpios = GP_J8; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_J8; + wakeup-gpios = GP_J8; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_J8; + wakeup-gpios = GP_J8; + }; + + max77818@66 { + compatible = "maxim,max77823"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_max77818>; + reg = <0x66>; + interrupts-extended = GPIRQ_MAX77818_INTB; + max77823,irq-gpio = GPIRQ_MAX77818_INTB; + max77823,wakeup = <1>; + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; +}; + +&max77823_battery { + status = "okay"; + battery,vendor = "SDI SDI"; + battery,charger_name = "max77823-charger"; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,bat_irq_attr = <0x3>; + + battery,chip_vendor = "QCOM"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + + battery,polling_time = <10 30 30 30 3600>; + + battery,adc_check_count = <6>; + + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_check; + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + + battery,temp_check_type = <0>; /* SEC_BATTERY_TEMP_CHECK_NONE */ + battery,temp_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_soc = <97>; + battery,full_condition_vcell = <4350000>; + + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <98>; + battery,recharge_condition_vcell = <4350000>; + + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + battery,chg_gpio_en = <0>; + battery,chg_polarity_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_status = <0>; + battery,chg_float_voltage = <4400>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 760 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 900 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 1000>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + usbotg-supply = <®_usbotg_vbus>; +}; + +&max77823_fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,fuel_alert_soc = <1>; + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + /* fuelgauge,repeated_fuelalert; */ + temp-disabled; + temp-calibration = <0 (-6763) 9858>; + /* if temp-calibration defined, temp-calibration-data not used */ + temp-calibration-data = <250 0x7cde + 255 0x7c50 + 260 0x7aa0 + 265 0x792e + 270 0x788e + 275 0x7714 + 280 0x761a + 285 0x7536 + 290 0x73ca + 295 0x7326 + 300 0x726c + 305 0x71cc + 310 0x71b2 + 315 0x70a4 + 320 0x6f6a + 325 0x6eae + 330 0x6a2e + 335 0x6800 + 340 0x673c + 345 0x665a + 350 0x65b4 + 355 0x6478 + 360 0x6318 + 365 0x6270 + 370 0x614e + 375 0x5f56 + 380 0x5ed2 + 385 0x5d9e + 390 0x5b38 + 395 0x5ae0 + 400 0x59ce + 405 0x57b2 + 410 0x55f2 + 415 0x53c2 + 420 0x505a>; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; +/* +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; +*/ + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, wlan */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hl.dtsi b/arch/arm/boot/dts/imx6qdl-hl.dtsi new file mode 100644 index 00000000000000..0eaf26d115ad9a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hl.dtsi @@ -0,0 +1,807 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_hl: iomuxc-imx6q-hlgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_hl { + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO - J4 outputs are inverted */ +#define GP_J4_PIN1 <&gpio3 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x130b0 +#define GP_J4_PIN2 <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x130b0 +#define GP_J4_PIN3 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x130b0 +#define GP_J4_PIN4 <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130b0 +#define GP_J4_PIN5 <&gpio3 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x130b0 +#define GP_J4_PIN6 <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x130b0 + +#define GP_J2_PIN1 <&gpio3 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x130b0 +#define GP_J2_PIN2 <&gpio3 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x130b0 +#define GP_J2_PIN3 <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x130b0 +#define GP_J2_PIN4 <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x130b0 +#define GP_J2_PIN5 <&gpio3 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x130b0 +#define GP_J2_PIN6 <&gpio3 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x130b0 + +#define GP_TP71 <&gpio4 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x130b0 +#define GP_TP72 <&gpio4 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x130b0 +#define GP_TP73 <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x130b0 +#define GP_TP74 <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x130b0 +#define GP_TP75 <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 +#define GP_TP_SD3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 /* mclk */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_LEVEL_LOW> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* J7 pin 4 - I2C3 */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_rv4162: i2c3-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_ipu1_di0: ipu1_di0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lvds: ipu1_lvdsgrp { + fsl,pins = < +#define GP_LVDS_J6_PIN19 <&gpio7 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_J8_POWER_ON <&gpio3 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 /* J8 pin 8/9(dry contact) */ +#define GP_J46_PIN2_I <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 /* J46 pin 2 - gp(inverted) */ +#define GP_J46_PIN3_I <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 /* J46 pin 3 - gp(inverted) */ + >; + }; + + /* PWM1 - J7 - touchscreen connector */ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + /* PWM3 - Backlight on RGB connector: J15 */ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + /* PWM4 on LVDS connector: J6 */ + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + /* USDHC3 - micro sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + pwm_lcd = &pwm3; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_j7 { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + pwms = <&pwm1 0 100000>; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 70 75 80 83 85 87 90 93 97 100>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm3 0 500000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str = "okaya_480x272"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_di0>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + j8 { + gpios = GP_J8_POWER_ON; + retain-state-suspended; + default-state = "off"; + }; + + j46-pin2 { + gpios = GP_J46_PIN2_I; + retain-state-suspended; + default-state = "off"; + }; + + j46-pin3 { + gpios = GP_J46_PIN3_I; + retain-state-suspended; + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + v4l2_cap_0: v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* hannstar7 values may be changed in bootscript */ + clock-frequency = <71108582>; + hactive = <1280>; + vactive = <800>; + hback-porch = <80>; + hfront-porch = <48>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +/* I2c3(J7) pwm */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +/* LCD(J33) backlight */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +/* LVDS(J6) backlight */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-names = "default"; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hp.dtsi b/arch/arm/boot/dts/imx6qdl-hp.dtsi new file mode 100644 index 00000000000000..2325a736c084a8 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hp.dtsi @@ -0,0 +1,1061 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_hp: iomuxc-imx6q-hpgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_hp { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_audmux4: audmux4grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +#define GP_ECSPI2_SS0 <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 +#define GP_ECSPI2_SS1 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_UART <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0b0b0 /* XR20M1170IL16-F : uart */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 +#define GPIRQ_SPI_UART <&gpio2 1 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_SPI_UART_RESET <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x030b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPI_5 <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x100b0 +#define GP_GPI_6 <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x100b0 +#define GP_GPI_7 <&gpio3 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x100b0 +#define GP_GPI_8 <&gpio3 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x100b0 +#define GP_GPI_9 <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x100b0 +#define GP_GPI_10 <&gpio4 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x100b0 +#define GP_GPI_11 <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b0 +#define GP_GPI_12 <&gpio4 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x100b0 +#define GP_GPI_13 <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x100b0 +#define GP_GPI_14 <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b0 +#define GP_GPI_15 <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100b0 +#define GP_GPI_16 <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b0 +#define GP_GPI_EN_N <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_GPO_1 <&gpio3 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 +#define GP_GPO_2 <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 +#define GP_GPO_3 <&gpio3 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GP_GPO_4 <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_GPO_5 <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GP_GPO_6 <&gpio3 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_GPO_7 <&gpio3 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_GPO_8 <&gpio3 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 +#define GP_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP72 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 +#define GP_TP73 <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP84 <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +#define GP_TP88 <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_TP89 <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +#define GP_TP95 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_LVDS_CTRL <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +#define GPIRQ_LIGHT_SENSOR <&gpio7 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J6 <&gpio7 13 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J6 <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_I2C3_J6_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 +#define GP_PCIE_DISABLE <&gpio2 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio2 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x1b0b1 +#define GP_UART1_TX_EN <&gpio7 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x030b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 +#define GP_UART3_TX_EN <&gpio3 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x030b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 +#define GP_UART4_TX_EN <&gpio6 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x030b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b1 +#define GP_UART5_TX_EN <&gpio6 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x030b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 +// MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 +#define GP_USDHC1_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10031 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17031 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17031 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17031 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17031 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17031 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc2_wlan:wlangrp { + fsl,pins = < +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 +#define GP_WIFI_QOW <&gpio2 3 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x100b0 +#define GP_WIFI_CLK_REQ <&gpio2 4 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x100b0 +#define GPIRQ_BT_HOST_WAKE <&gpio6 10 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x100b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc1; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_j55 { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + pwms = <&pwm1 0 5000000>; + status = "disabled"; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + pwms = <&pwm2 0 1667>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + enable-gpios = GP_GPI_EN_N; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + gpi5 { + label = "gpi5"; + gpios = GP_GPI_5; + linux,code = ; + }; + + gpi6 { + label = "gpi6"; + gpios = GP_GPI_6; + linux,code = ; + }; + + gpi7 { + label = "gpi7"; + gpios = GP_GPI_7; + linux,code = ; + }; + + gpi8 { + label = "gpi8"; + gpios = GP_GPI_8; + linux,code = ; + }; + + gpi9 { + label = "gpi9"; + gpios = GP_GPI_9; + linux,code = ; + }; + + gpi10 { + label = "gpi10"; + gpios = GP_GPI_10; + linux,code = ; + }; + + gpi11 { + label = "gpi11"; + gpios = GP_GPI_11; + linux,code = ; + }; + + gpi12 { + label = "gpi12"; + gpios = GP_GPI_12; + linux,code = ; + }; + + gpi13 { + label = "gpi13"; + gpios = GP_GPI_13; + linux,code = ; + }; + + gpi14 { + label = "gpi14"; + gpios = GP_GPI_14; + linux,code = ; + }; + + gpi15 { + label = "gpi15"; + gpios = GP_GPI_15; + linux,code = ; + }; + + gpi16 { + label = "gpi16"; + gpios = GP_GPI_16; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0x50000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + regulator-always-on; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-hp-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_PODF>, <&clks IMX6QDL_CLK_CKO2_SEL>, <&clks IMX6QDL_CLK_CKO>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2_SEL>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_CKO1>; + assigned-clock-rates = <24000000>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <2>; + cs-gpios = GP_ECSPI2_SS0, GP_ECSPI2_SS1; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + spidev@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI3_UART; + status = "okay"; + + xrm1170@0 { + clocks = <&clks IMX6QDL_CLK_CKO2>; + compatible = "exar,xrm1170"; + spi-max-frequency = <8000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupts-extended = GPIRQ_SPI_UART; + reset-gpios = GP_SPI_UART_RESET; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + apds9300@29 { + compatible = "avago,apds9300"; + reg = <0x29>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + atmel_maxtouch@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + reset-gpios = GP_I2C3_J6_RESET; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J6; + wakeup-gpios = GP_I2C3_J6; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + lvds1080p: lvds1080p { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>; + hfront-porch = <88>; + vback-porch = <36>; + vfront-porch = <4>; + hsync-len = <44>; + vsync-len = <5>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disable"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + control-gpios = GP_UART1_TX_EN; +#define M_TX_EN 1 + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = ; + rs232_txen_levels = ; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + rs485-mode = <1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + control-gpios = GP_UART3_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = ; + rs232_txen_levels = ; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + rs485-mode = <1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + control-gpios = GP_UART4_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = ; + rs232_txen_levels = ; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + rs485-mode = <1>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + control-gpios = GP_UART5_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = ; + rs232_txen_levels = ; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + rs485-mode = <1>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { +#if 1 + /* Always used as peripheral */ + dr_mode = "peripheral"; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + cd-gpios = GP_USDHC1_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, silex/TiWi wl1271 */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wlan>, <&pinctrl_audmux4>; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard-lvds.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard-lvds.dtsi new file mode 100644 index 00000000000000..5af67f5e89342f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard-lvds.dtsi @@ -0,0 +1,75 @@ +/ { + panel { + compatible = "powertip,ph800480t024", "panel-lvds"; + width-mm = <108>; + height-mm = <65>; + data-mapping = "jeida-18"; + backlight = <&lvds_backlight>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <22>; + hsync-len = <60>; + vsync-len = <10>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + lvds_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 10000000>; + power-supply = <&v_3v2>; + brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <12>; + }; +}; + +&i2c1 { + touchscreen@55 { + compatible = "sitronix,st1232"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_touchscreen>; + reg = <0x55>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&iomuxc { + hummingboard { + pinctrl_hummingboard_touchscreen: hummingboard-touchscreen { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard-vendor.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard-vendor.dtsi new file mode 100644 index 00000000000000..848198a232a4c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard-vendor.dtsi @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + mxcfb0 = &mxcfb1; + mxcfb2 = &mxcfb2; + }; + + chosen { + bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 5 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + mipi_camera = <1>; + default_input = <1>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_ecspi2>; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + status = "okay"; +}; + +&i2c1 { + /* Raspberry Pi camera rev 1.3 */ + camera@36 { + compatible = "ovti,ov5647_mipi"; + reg = <0x36>; + /* Pi camera has its own 25MHz clock. */ + clocks = <&clks 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <&v_3v2>; + AVDD-supply = <&v_3v2>; + DVDD-supply = <&v_3v2>; + pwn-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + led-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + ipu_id = <0>; + csi_id = <1>; + mclk = <25000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_mipi>; + extended-buffer; + }; + + /* Pro baseboard model */ + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + nxp,12p5_pf; + }; +}; + +&i2c2 { + ddc@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + hummingboard { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 26 pin header GPIO description. The pins + * numbering as following - + * GPIO number | GPIO (bank,num) | PIN number + * ------------+-----------------+------------ + * gpio1 | (1,1) | IO7 + * gpio73 | (3,9) | IO11 + * gpio72 | (3,8) | IO12 + * gpio71 | (3,7) | IO13 + * gpio70 | (3,6) | IO15 + * gpio194 | (7,2) | IO16 + * gpio195 | (7,3) | IO18 + * gpio67 | (3,3) | IO22 + * + * Notice the gpioX and GPIO (Y,Z) mapping forumla : + * X = (Y-1) * 32 + Z + */ + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1 + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1 + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + >; + }; + + pinctrl_hummingboard_i2c3: hummingboard-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_mipi: hummingboard_mipi { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x17059 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x13059 + >; + }; + + pinctrl_hummingboard_ecspi2: hummingboard_ecspi2 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ + >; + }; + + pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_hummingboard_usdhc2_100mhz: hummingboard-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_hummingboard_usdhc2_200mhz: hummingboard-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; + }; +}; + +&ldb { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu2-di0"; + primary; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + mipi_dphy_clk = /bits/ 8 <0x28>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2 + >; + pinctrl-1 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2_100mhz + >; + pinctrl-2 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2_200mhz + >; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index d6c2358ffad449..dc1ca0a72f8758 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -38,8 +38,10 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" + +#ifndef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-lvds.dtsi" +#endif / { chosen { @@ -53,38 +55,58 @@ pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; }; - regulators { - compatible = "simple-bus"; + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + vin-supply = <&v_5v0>; + }; - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; }; sound-sgtl5000 { @@ -132,20 +154,20 @@ status = "okay"; /* Pro baseboard model */ - rtc: pcf8523@68 { + rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; /* Pro baseboard model */ - sgtl5000: sgtl5000@0a { + sgtl5000: codec@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <&v_3v2>; + VDDIO-supply = <&v_3v2>; }; }; @@ -201,6 +223,12 @@ fsl,pins = ; }; + pinctrl_hummingboard_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { fsl,pins = < MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 @@ -224,7 +252,7 @@ * Similar to pinctrl_usbotg_2, but we want it * pulled down for a fixed host connection. */ - fsl,pins = ; + fsl,pins = ; }; pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { @@ -247,6 +275,11 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 >; }; + pinctrl_hummingboard_vmmc: hummingboard-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; }; }; @@ -268,6 +301,12 @@ status = "okay"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_pwm3>; + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_spdif>; @@ -280,7 +319,7 @@ &usbh1 { disable-over-current; - vbus-supply = <®_usbh1_vbus>; + vbus-supply = <&v_usb2>; status = "okay"; }; @@ -288,7 +327,7 @@ disable-over-current; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; + vbus-supply = <&v_usb1>; status = "okay"; }; @@ -298,7 +337,11 @@ &pinctrl_hummingboard_usdhc2_aux &pinctrl_hummingboard_usdhc2 >; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&v_sd>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi new file mode 100644 index 00000000000000..f400405381a721 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi @@ -0,0 +1,72 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + hummingboard2 { + pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; + vmmc-supply = <&v_3v2>; + vqmmc-supply = <&v_3v2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-vendor.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2-vendor.dtsi new file mode 100644 index 00000000000000..e00520790aee28 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2-vendor.dtsi @@ -0,0 +1,362 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + mxcfb0 = &mxcfb1; + mxcfb2 = &mxcfb2; + }; + + chosen { + bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 9 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + mipi_camera = <1>; + default_input = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0xf>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; + status = "okay"; + + camera@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + ipu_id = <0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_mipi>; + extended-buffer; + }; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + nxp,12p5_pf; + }; +}; + +&i2c2 { + ddc@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + hummingboard2 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 36 pin headers GPIO description. The pins + * numbering as following - + * + * 3.2v 5v 74 75 + * 73 72 71 70 + * 69 68 67 66 + * + * 77 78 79 76 + * 65 64 61 60 + * 53 52 51 50 + * 49 48 166 132 + * 95 94 90 91 + * GND 54 24 204 + * + * The GPIO numbers can be extracted using + * signal name from below. + * Example - + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 + * + * i.e. The mapping of GPIO(X,Y) to Linux gpio + * number is : gpio number = (X-1) * 32 + Y + */ + /* DI1_PIN15 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 + /* DI1_PIN02 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 + /* DISP1_DATA00 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + /* DISP1_DATA01 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + /* DISP1_DATA02 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + /* DISP1_DATA03 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + /* DISP1_DATA04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 + /* DISP1_DATA05 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 + /* DISP1_DATA06 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + /* DISP1_DATA07 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 + /* DI1_D0_CS */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 + /* DI1_D1_CS */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 + /* DI1_PIN01 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 + /* DI1_PIN03 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 + /* DISP1_DATA08 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 + /* DISP1_DATA09 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 + /* DISP1_DATA10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 + /* DISP1_DATA11 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 + /* DISP1_DATA12 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 + /* DISP1_DATA13 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 + /* DISP1_DATA14 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 + /* DISP1_DATA15 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 + /* DISP1_DATA16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 + /* DISP1_DATA17 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 + /* DISP1_DATA18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 + /* DISP1_DATA19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 + /* DISP1_DATA20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 + /* DISP1_DATA21 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 + /* DISP1_DATA22 */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 + /* DISP1_DATA23 */ + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 + /* DI1_DISP_CLK */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 + /* SPDIF_IN */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 + /* SPDIF_OUT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 + + /* MikroBUS GPIO pin number 10 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 + >; + }; + + pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + }; +}; + +&ldb { + status = "disabled"; + + lvds@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu2-di0"; + primary; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + mipi_dphy_clk = <0x14>; + status = "okay"; +}; + +&pwm3 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi new file mode 100644 index 00000000000000..e529268d3b245d --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef MXC_USE_VENDOR_DRIVERS +#include "imx6qdl-hummingboard-lvds.dtsi" +#endif + +/ { + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + }; + + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; + + vcc_1p8: regulator-vcc-1p8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1p8"; + vin-supply = <&v_3v2>; + }; + + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; + }; + + v_usb2: regulator-v-usb2 { + /* USB hub port 1 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb3: regulator-v-usb3 { + /* USB hub port 3 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb3"; + vin-supply = <&v_5v0>; + }; + + v_usb4: regulator-v-usb4 { + /* USB hub port 4 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb4"; + vin-supply = <&v_5v0>; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; + cs-gpios = <&gpio2 26 0>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: codec@0a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <&v_3v2>; + VDDD-supply = <&vcc_1p8>; + VDDIO-supply = <&v_3v2>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hummingboard2 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 36 pin headers GPIO description. The pins + * numbering as following - + * + * 3.2v 5v 74 75 + * 73 72 71 70 + * 69 68 67 66 + * + * 77 78 79 76 + * 65 64 61 60 + * 53 52 51 50 + * 49 48 166 132 + * 95 94 90 91 + * GND 54 24 204 + * + * The GPIO numbers can be extracted using + * signal name from below. + * Example - + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 + * + * i.e. The mapping of GPIO(X,Y) to Linux gpio + * number is : gpio number = (X-1) * 32 + Y + */ + /* DI1_PIN15 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 + /* DI1_PIN02 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 + /* DISP1_DATA00 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + /* DISP1_DATA01 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + /* DISP1_DATA02 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + /* DISP1_DATA03 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + /* DISP1_DATA04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 + /* DISP1_DATA05 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 + /* DISP1_DATA06 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + /* DISP1_DATA07 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 + /* DI1_D0_CS */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 + /* DI1_D1_CS */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 + /* DI1_PIN01 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 + /* DI1_PIN03 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 + /* DISP1_DATA08 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 + /* DISP1_DATA09 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 + /* DISP1_DATA10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 + /* DISP1_DATA11 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 + /* DISP1_DATA12 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 + /* DISP1_DATA13 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 + /* DISP1_DATA14 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 + /* DISP1_DATA15 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 + /* DISP1_DATA16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 + /* DISP1_DATA17 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 + /* DISP1_DATA18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 + /* DISP1_DATA19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 + /* DISP1_DATA20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 + /* DISP1_DATA21 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 + /* DISP1_DATA22 */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 + /* DISP1_DATA23 */ + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 + /* DI1_DISP_CLK */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 + /* SPDIF_IN */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 + /* SPDIF_OUT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 + + /* MikroBUS GPIO pin number 10 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 + >; + }; + + pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ + >; + }; + + pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 + >; + }; + + pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_mipi: hummingboard2_mipi { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { + /* + * Similar to pinctrl_usbotg_2, but we want it + * pulled down for a fixed host connection. + */ + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; + + pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hummingboard2_uart3: hummingboard2-uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; + reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; + vbus-supply = <&v_usb1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2 + >; + pinctrl-1 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_100mhz + >; + pinctrl-2 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_200mhz + >; + vmmc-supply = <&v_sd>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_uart3>; + status = "okay"; +}; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-insp.dtsi b/arch/arm/boot/dts/imx6qdl-insp.dtsi new file mode 100644 index 00000000000000..75d10e1ff7777a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-insp.dtsi @@ -0,0 +1,904 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_insp: iomuxc-imx6q-inspgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_insp { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < +#define GP_MAIN_POWER_BUTTON <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x0b0b0 +#define GP_INSP_GP1 <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0b0b0 +#define GP_INSP_GP2 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0b0b0 +#define GP_INSP_GP3 <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0b0b0 +#define GP_INSP_GP4 <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 +#define GP_INSP_GP5 <&gpio4 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x0b0b0 +#define GP_INSP_GP6 <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 +#define GP_INSP_GP7 <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0b0b0 +#define GP_INSP_GP8 <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 +#define GP_INSP_GP9 <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 +#define GP_INSP_GP10 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x0b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Main power on, Low shuts down system */ +#define GP_MAIN_POWER_EN <&gpio3 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x030b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_MUTE <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x030b0 + /* no headphone detect */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < +#define GP_I2C2_J6_EN <&gpio6 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b0 +#define GP_I2C2_HDMI_EN <&gpio2 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7180: i2c3-adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b1 +#define GP_ADV7180_RESET <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 /* Reset */ +#define GPIRQ_ADV7180 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* Irq */ + >; + }; + + pinctrl_i2c3_adv7180_cea861: i2c3-adv7180_cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + >; + }; + + pinctrl_i2c3_adv7180_no_cea861: i2c3-adv7180_no_cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* Hsync */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* Vsync */ + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio2 27 IRQ_TYPE_LEVEL_LOW> +#define GP_TSC2004 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_TSC2004_RESET <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0b0b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x10 /* Contrast */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + /* Bluetooth */ + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_H1_PWR <&gpio7 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + /* USDHC2: TiWi-R2 */ + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17031 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10031 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17031 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17031 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17031 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17031 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + >; + }; + + /* USDHC3 - micro sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10031 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17031 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17031 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17031 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17031 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17031 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lcd; + pwm_lcd = &pwm3; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm3 0 20000>; + }; + + extledcontrol { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 + 45 46 47 48 49 50 51 52 53 54 55 56 57 58 + 59 60 61 62 63 64 65 66 67 68 69 70 71 72 + 73 74 75 76 77 78 79 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 97 98 99>; + compatible = "pwm-backlight"; + default-brightness-level = <0>; + pwms = <&pwm1 0 20000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="800x600MR@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str ="LSA40AT9001"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + power { + label = "Power Button"; + gpios = GP_MAIN_POWER_BUTTON; + linux,code = ; + gpio-key,wakeup; + }; + + input1 { + label = "Input 1"; + gpios = GP_INSP_GP1; + linux,code = ; + }; + + input2 { + label = "Input 2"; + gpios = GP_INSP_GP2; + linux,code = ; + }; + }; + + i2c2mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C2_J6_EN, GP_I2C2_HDMI_EN; + i2c-parent = <&i2c2>; + idle-state = <0>; + + i2c3@1 { + /* J6 */ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3@2 { + /* HDMI */ + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + poweroff: poweroff { + compatible = "gpio-poweroff"; + gpios = GP_MAIN_POWER_EN; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_H1_PWR; + enable-active-low; + }; + + reg_usbotg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-low; + }; + + reg_wlan_en: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + sound-sgtl5000 { + compatible = "fsl,imx6q-insp-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_SGTL5000_MUTE; + }; + + v4l2_cap_0 { /* Adv7180 */ + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + /* hdmi/lcd show same content */ + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + override_edid = [ + 00 ff ff ff ff ff ff 00 04 69 f3 24 d6 12 00 00 + 16 16 01 03 80 34 1d 78 2a c7 20 a4 55 49 99 27 + 13 50 54 bf ef 00 71 4f 81 40 81 80 95 00 b3 00 + d1 c0 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c + 45 00 09 25 21 00 00 1e 00 00 00 ff 00 43 36 4c + 4d 54 46 30 30 34 38 32 32 0a 00 00 00 fd 00 37 + 4b 1e 55 10 00 0a 20 20 20 20 20 20 00 00 00 fc + 00 41 53 55 53 20 56 48 32 34 32 48 0a 20 01 78 ]; + + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + micbias-voltage-m-volts = <2250>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + reset-gpios = GP_TSC2004_RESET; + }; + + adv7180: adv7180@20 { + compatible = "adv,adv7180"; + reg = <0x20>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_i2c3_adv7180>; + pinctrl-1 = <&pinctrl_i2c3_adv7180_no_cea861>; + pinctrl-2 = <&pinctrl_i2c3_adv7180_cea861>; + cea861 = <0>; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + rst-gpios = GP_ADV7180_RESET; + interrupts-extended = GPIRQ_ADV7180; + ipu_id = <0>; + csi_id = <0>; + mclk = <28636300>; + mclk_source = <0>; + cvbs = <1>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ioc.dtsi b/arch/arm/boot/dts/imx6qdl-ioc.dtsi new file mode 100644 index 00000000000000..56e754258012b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ioc.dtsi @@ -0,0 +1,1054 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_ioc: iomuxc-imx6q-iocgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ioc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +#define GP_ECSPI2_CS <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_ecspi2_mcp2515: ecspi2_mcp2515grp { + fsl,pins = < +#define GP_MCP2515_RESET <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 +#define GPIRQ_MCP2515 <&gpio3 3 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* Spare */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* Spare */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_ar1020: i2c1_ar1020grp { + fsl,pins = < +#define GP_AR1020_IRQ <&gpio1 9 GPIO_ACTIVE_HIGH> +#define GPIRQ_AR1020 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10030 + >; + }; + + pinctrl_i2c1_isl1208: i2c1-isl1208grp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio6 7 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + >; + }; + + pinctrl_i2c2_sc16is7xx: i2c2_sc16is7xxgrp { + fsl,pins = < +#define GPIRQ_SC16IS7XX <&gpio5 20 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 +#define GP_ADV7180_RESET <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 +#define GPIRQ_ADV7180 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_i2c3_adv7180_cea861: adv7180-cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 + >; + }; + + pinctrl_i2c3_adv7180_no_cea861: adv7180-no-cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0xb0b1 /* Hsync */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0xb0b1 /* Vsync */ + >; + }; + + pinctrl_lcd0: lcd0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x000b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_tsc2004: tsc2004grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10061 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17061 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17061 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17061 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17061 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17061 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17061 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17061 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17061 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10061 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17061 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17061 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17061 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17061 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17061 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + mxcfb2 = &fb_lcd; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm1 0 100000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk20m: clk20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-ioc-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0: v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1: v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_3: v4l2_cap_3 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +/* assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; */ +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS; + status = "okay"; + /* can bus */ + mcp2515: mcp2515@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_mcp2515>; + compatible = "microchip,mcp2515"; + clocks = <&clk20m>; + interrupts-extended = GPIRQ_MCP2515; + reg = <0>; + spi-max-frequency = <10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + ar1020_i2c@4d { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_ar1020>; + compatible = "ar1020_i2c"; + reg = <0x4d>; + interrupts-extended = GPIRQ_AR1020; + wakeup-gpios = GP_AR1020_IRQ; + }; + + isl1208@6f { + compatible = "isl,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_isl1208>; + reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; + }; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; + + sc16is7xx_uart@49 { + compatible = "nxp,sc16is7xx-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_sc16is7xx>; + reg = <0x49>; + interrupts-extended = GPIRQ_SC16IS7XX; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + adv7180: adv7180@20 { + compatible = "adv,adv7180"; + reg = <0x20>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_i2c3_adv7180>; + pinctrl-1 = <&pinctrl_i2c3_adv7180_no_cea861>; + pinctrl-2 = <&pinctrl_i2c3_adv7180_cea861>; + cea861 = <0>; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + rst-gpios = GP_ADV7180_RESET; + interrupts-extended = GPIRQ_ADV7180; + ipu_id = <0>; + csi_id = <0>; + mclk = <28636300>; + mclk_source = <0>; + cvbs = <1>; + }; +}; + +&ldb { + status = "okay"; + + lvds_channel0: lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* AA065VE11 values may be changed in bootscript */ + clock-frequency = <43748359>; + hactive = <640>; + vactive = <480>; + hback-porch = <148>; + hfront-porch = <116>; + vback-porch = <83>; + vfront-porch = <60>; + hsync-len = <96>; + vsync-len = <2>; + }; + lg1280x800: lp101wx1 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + vga_lvds: vga { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <33>; + vfront-porch = <10>; + hsync-len = <96>; + vsync-len = <2>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = GP_USDHC4_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-jlm.dtsi b/arch/arm/boot/dts/imx6qdl-jlm.dtsi new file mode 100644 index 00000000000000..e27d9ccf02146f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-jlm.dtsi @@ -0,0 +1,879 @@ +/* + * Copyright 2013-2016 Boundary Devices, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_jlm: iomuxc-imx6q-jlmgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_jlm { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /* Spare */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* Spare */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_isl1208: i2c1-isl1208grp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio6 7 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_ov5640_mipi: i2c3-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_lcd0: lcd0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17071 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17071 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17071 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17071 +#define GP_EMMC_RESET <&gpio2 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc4; + mmc1 = &usdhc3; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + mxcfb2 = &fb_lcd; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + power-supply = <®_3p3v>; + pwms = <&pwm1 0 5000000>; + status = "okay"; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + power-supply = <®_3p3v>; + pwms = <&pwm4 0 5000000>; + status = "okay"; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + chosen { + stdout-path = &uart2; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-jlm-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0: v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + isl1208@6f { + compatible = "isil,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_isl1208>; + reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + }; + + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + AA065VE11: AA065VE11 { + clock-frequency = <43748359>; + hactive = <640>; + vactive = <480>; + hback-porch = <148>; + hfront-porch = <116>; + vback-porch = <83>; + vfront-porch = <60>; + hsync-len = <96>; + vsync-len = <2>; + }; + vga_lvds: vga { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <33>; + vfront-porch = <10>; + hsync-len = <96>; + vsync-len = <2>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = GP_USDHC4_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ls.dtsi b/arch/arm/boot/dts/imx6qdl-ls.dtsi new file mode 100644 index 00000000000000..0e27a5efa57434 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ls.dtsi @@ -0,0 +1,1319 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + iomuxc_imx6q_ls: iomuxc-imx6q-lsgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ls { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_audmux6: audmux6grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + >; + }; + + pinctrl_braille_display: braille_displaygrp { + fsl,pins = < +#define GP_DISP_CLK <&gpio4 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x030b0 +#define GP_DISP_DATA_BUF_EN <&gpio5 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x030b0 +#define GP_DISP_HV_EN <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b0 +#define GP_DISP_MISO <&gpio5 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x130b0 +#define GP_DISP_MOSI <&gpio5 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x030b0 +#define GP_DISP_STROBE <&gpio5 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < +#ifdef CONFIG_NEW_REV + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 +#else + MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio5 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 +#endif + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_GSM <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x100b1 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x100b1 +#define GP_ECSPI5_WM5102 <&gpio1 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < +#define GP_KEY_1 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x130b0 +#define GP_KEY_2 <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130b0 +#define GP_KEY_3 <&gpio3 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x130b0 +#define GP_KEY_4 <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x130b0 +#define GP_KEY_5 <&gpio3 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x130b0 +#define GP_KEY_6 <&gpio3 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x130b0 +#define GP_KEY_SHIFT <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x130b0 +#define GP_KEY_SPACE <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x130b0 +#define GP_KEY_CTRL <&gpio3 14 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x130b0 +#define GP_KEYPAD_LOCK <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_gsm: gsmgrp { + fsl,pins = < +#define GP_GSM_SIM_RESET <&gpio5, 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x0b0b0 +#define GP_GSM_HOST_WAKE_WWAN <&gpio5, 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0b0b0 +#define GP_GSM_PWR_EN <&gpio6, 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x0b0b0 +#define GP_GSM_RESET <&gpio6, 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0b0b0 +#define GP_GSM_ON_OFF <&gpio6, 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x0b0b0 +#define GP_GSM_HOST_WAKE <&gpio6, 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0b0b0 +// MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x000b0 /* slow clock */ + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog_1: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x000b0 /* slow clock */ +#define GP_DISP_LED_RED <&gpio5 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 +#define GP_DISP_LED_GREEN <&gpio5 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio5 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 +#define GP_I2C1_SDA <&gpio5 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 +#ifdef CONFIG_NEW_REV + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +#else + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 +#endif + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio2 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 +#ifdef CONFIG_NEW_REV +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 +#else +#define GP_I2C2_SDA <&gpio3 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 +#endif + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < +#define GP_I2C2_HDMI_EN <&gpio5 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x000b0 +#define GP_I2C2_OV5640_MIPI_EN <&gpio1 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x000b0 +#ifdef CONFIG_NEW_REV +#define GP_I2C2_FLASH_EN <&gpio2 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x030b0 +#else +#define GP_I2C2_FLASH_EN <&gpio3 17 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x030b0 +#endif + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3_ACCEL_EN <&gpio5 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x000b0 +#define GP_I2C3_MAX77818_EN <&gpio4 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x030b0 + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__KEY_COL0 0x110b0 + MX6QDL_PAD_KEY_COL1__KEY_COL1 0x110b0 + MX6QDL_PAD_KEY_COL2__KEY_COL2 0x110b0 + MX6QDL_PAD_KEY_COL3__KEY_COL3 0x110b0 + MX6QDL_PAD_KEY_COL4__KEY_COL4 0x110b0 + MX6QDL_PAD_GPIO_19__KEY_COL5 0x110b0 + MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1b0b0 + MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 + >; + }; + + pinctrl_keypad_sleep: keypad_sleepgrp { + fsl,pins = < + /* Choose 1 col/ 1 row button for wakeup (comment out chosen) */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x030b0 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x030b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x030b0 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x030b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x030b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x030b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x030b0 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x030b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x030b0 + >; + }; + + pinctrl_keypad_gpio: keypad_gpiogrp { + fsl,pins = < +#define GP_KPP_C0 <&gpio2 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x0b0b0 +#define GP_KPP_C1 <&gpio2 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0b0b0 +#define GP_KPP_C2 <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b0 +#define GP_KPP_C3 <&gpio3 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 +#define GP_KPP_C4 <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0b0b0 +#define GP_KPP_C5 <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b0 +#define GP_KPP_R0 <&gpio3 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 +#define GP_KPP_R1 <&gpio3 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_KPP_R2 <&gpio3 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GP_KPP_R3 <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_KPP_R4 <&gpio2 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 +#define GP_KPP_R5 <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + /* ends with B(active low) */ + pinctrl_max77818: max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_INOKB <&gpio4 26 IRQ_TYPE_LEVEL_LOW> /* C5 */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 +#define GPIRQ_MAX77818_WCINOKB <&gpio5 7 IRQ_TYPE_LEVEL_LOW> /* A5 */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 +#define GPIRQ_MAX77818_INTB <&gpio5 6 IRQ_TYPE_LEVEL_LOW> /* C3 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + + pinctrl_mpu9250: mpu9250grp { + fsl,pins = < +#define GPIRQ_ACCEL <&gpio5 30 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + >; + }; + + pinctrl_power: powergrp { + fsl,pins = < +#define GP_MAIN_ON_OFF <&gpio3 20 GPIO_ACTIVE_HIGH> /* input to or gate */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0b0b0 +#define GP_ON_OFF <&gpio5 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + >; + }; + + pinctrl_ov5640_mipi: ov5640_mipigrp { + fsl,pins = < +#ifdef CONFIG_NEW_REV +#define GP_CAM_STROBE <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x030b0 +#define GP_CAM_TORCH <&gpio3 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x030b0 +#else +#define GP_CAM_STROBE <&gpio3 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x030b0 +#define GP_CAM_TORCH <&gpio3 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x030b0 +#endif +#define GP_OV5640_MIPI_RESET <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* XCLK */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_5v: reg_5vgrp { + fsl,pins = < +#define GP_REG_5V_EN <&gpio7 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0b0b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio5 12 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x130b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x030b1 +#define GP_GPS_HEARTBEAT <&gpio4 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x030b0 +#define GPIRQ_GPS <&gpio4 28 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_uart5_gps_rfkill: uart5_gps_rfkillgrp { + fsl,pins = < +#define GP_GPS_RESET <&gpio4 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x030b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio4 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0b0b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10031 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17031 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17031 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17031 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17031 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17031 +// MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +#define GP_SD3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; + + pinctrl_wm5102: wm5102grp { + fsl,pins = < +#define GPIRQ_WM5102 <&gpio2 20 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 /* Irq */ +#define GP_WM5102_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x000b0 /* Reset */ +#define GP_WM5102_LDOENA <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x000b0 /* ldo enable */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* MCLK1 */ +// MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x000b0 /* MCLK2 */ + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + braille_display { + compatible = "ls-braille"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_braille_display>; + buf_en-gpios = GP_DISP_DATA_BUF_EN; + clock-gpios = GP_DISP_CLK; + hv_en-gpios = GP_DISP_HV_EN; + miso-gpios = GP_DISP_MISO; + mosi-gpios = GP_DISP_MOSI; + strobe-gpios = GP_DISP_STROBE; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_power>, <&pinctrl_gpio_keys>; + power { + label = "Power Button"; + gpios = GP_ON_OFF; + linux,code = ; /* 116(0x74) */ + gpio-key,wakeup; + }; + + 1 { + label = "KEY_1"; + gpios = GP_KEY_1; + linux,code = ; /* 2 */ + }; + 2 { + label = "KEY_2"; + gpios = GP_KEY_2; + linux,code = ; /* 3 */ + }; + 3 { + label = "KEY_3"; + gpios = GP_KEY_3; + linux,code = ; /* 4 */ + }; + 4 { + label = "KEY_4"; + gpios = GP_KEY_4; + linux,code = ; /* 5 */ + }; + 5 { + label = "KEY_5"; + gpios = GP_KEY_5; + linux,code = ; /* 6 */ + }; + 6 { + label = "KEY_6"; + gpios = GP_KEY_6; + linux,code = ; /* 7 */ + }; + 7 { + label = "KEY_LEFTSHIFT"; + gpios = GP_KEY_SHIFT; + linux,code = ; /* 42(0x2a) */ + }; + 8 { + label = "KEY_SPACE"; + gpios = GP_KEY_SPACE; + linux,code = ; /* 57(0x39) */ + }; + 9 { + label = "KEY_CTRL"; + gpios = GP_KEY_CTRL; + linux,code = ; /* 97(0x61) */ + }; + 12 { + label = "KEYPAD_LOCK"; + gpios = GP_KEYPAD_LOCK; + linux,code = ; /* 152(0x98) */ + }; + }; + + i2c2mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C2_HDMI_EN, GP_I2C2_OV5640_MIPI_EN, GP_I2C2_FLASH_EN; + i2c-parent = <&i2c2>; + idle-state = <0>; + + i2c2a: i2c2@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2b: i2c2@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2c: i2c2@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c3mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = GP_I2C3_ACCEL_EN, GP_I2C3_MAX77818_EN; + + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3a: i2c3@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3b: i2c3@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + kpp_gpio { + compatible = "gpio-matrix-keypad"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keypad_gpio>; + col-gpios = GP_KPP_C0, GP_KPP_C1, GP_KPP_C2, GP_KPP_C3, GP_KPP_C4, GP_KPP_C5; /* output */ + row-gpios = GP_KPP_R0, GP_KPP_R1, GP_KPP_R2, GP_KPP_R3, GP_KPP_R4, GP_KPP_R5; /* input */ + linux,no-autorepeat; + linux,wakeup; + gpio-activelow; + debounce-delay-ms = <1>; + col-scan-delay-us = <0>; + + linux,keymap = < + 0x00000001 + 0x0100009e /* KEY_BACK(158)(0x9e) */ + 0x020000a9 /* KEY_PHONE(169)(0xa9) */ + 0x03000066 /* KEY_HOME(102)(0x66) */ + 0x04000005 + 0x05000006 + 0x00010069 /* KEY_LEFT(105)(0x69) */ + 0x0101006a /* KEY_RIGHT(106)(0x6a) */ + 0x02010009 + 0x0301000c /* KEY_MINUS(12)(0x0c) */ + 0x0401000b + 0x0501000c + 0x00020067 /* KEY_UP(103)(0x67) */ + 0x01020161 /* KEY_SELECT(353)(0x161) */ + 0x0202006c /* KEY_DOWN(108)(0x6c) */ + 0x03020010 + 0x04020011 + 0x05020012 + 0x000300d9 /* KEY_SEARCH(217)(0xd9) */ + 0x01030014 + 0x0203008b /* KEY_MENU(139)(0x8b) */ + 0x03030016 + 0x04030017 + 0x05030018 + 0x00040019 + 0x01040038 /* KEY_LEFTALT(56)(0x38), Joystick left */ + 0x020400b1 /* KEY_SCROLLUP(177)(0xb1), Joystick up */ + 0x0304001c /* KEY_ENTER(28)(0x1c), Joystick press */ + 0x04040064 /* KEY_RIGHTALT(100)(0x64), Joystick right */ + 0x050400f1 /* KEY_VIDEO_NEXT(241)(0xf1), advance, blue bottom right */ + 0x00050072 /* KEY_VOLUMEDOWN(114)(0x72), blue right side lower */ + 0x010500a7 /* KEY_RECORD(167)(0xa7), blue rightside */ + 0x020500d4 /* KEY_CAMERA(212)(0xd4), blue rightside */ + 0x03050073 /* KEY_VOLUMEUP(115)(0x73), blue rightside upper */ + 0x04050023 + 0x05050024 + >; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG_PWR; + enable-active-high; + }; + + reg_5v: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_5v>; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_5V_EN; + enable-active-high; + }; + + reg_wlan_en: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound-gsm { + compatible = "fsl,imx6q-ls-gsm", + "fsl,imx-audio-gsm"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + sound-wm5102 { + compatible = "fsl,imx6q-ls-wm5102", + "fsl,imx-audio-wm5102"; + model = "imx6q-ls-wm5102"; + ssi-controller = <&ssi2>; + mux-int-port = <2>; + mux-ext-port = <6>; + }; + + uart5_gps_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_gps_rfkill>; + type = <6>; /* gps */ + gpios = GP_GPS_RESET; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3 &pinctrl_audmux6>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + mtd@000C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi5 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI5_WM5102; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + codec: wm5102@0 { + compatible = "wlf,wm5102"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wm5102>; + clocks = <&clks IMX6QDL_CLK_CKO>, <&clks IMX6QDL_CLK_CKIL>; + clock-names = "mclk1", "mclk2"; + interrupts-extended = GPIRQ_WM5102; + wlf,reset = GP_WM5102_RESET; + wlf,ldoena = GP_WM5102_LDOENA; + wlf,micbias1 = <3300 1 1 1 1>; + wlf,micbias2 = <3300 1 1 1 1>; + wlf,micbias3 = <3300 1 1 1 1>; + wlf,micd-ranges = < + 139 226 + 295 115 + 752 114 + 1257 217 + >; + wlf,micd-configs = <0 1 0>; + wlf,dmic-ref = <0 3 0 0 0 0>; + wlf,inmode = <1 2 2 2 1 1>; + spi-max-frequency = <400000>; + DBVDD1-supply = <®_1p8v>; + DBVDD2-supply = <®_1p8v>; + DBVDD3-supply = <®_1p8v>; + AVDD-supply = <®_1p8v>; + CPVDD-supply = <®_1p8v>; + SPKVDDL-supply = <®_5v>; + SPKVDDR-supply = <®_5v>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c2a { + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c2b { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + }; +}; + +&i2c2c { + lm3555@30 { + compatible = "ti,lm3555"; + reg = <0x30>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; +}; + +&i2c3a { + mpu9250@68 { + compatible = "invn,mpu9250"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mpu9250>; + inven,vdd_ana-supply = <®_3p3v>; + inven,vcc_i2c-supply = <®_3p3v>; + axis_map_x = <1>; + negate_x = <0>; + axis_map_y = <0>; + negate_y = <0>; + axis_map_z = <2>; + negate_z = <1>; + inven,aux_type = "none"; + inven,secondary_type = "compass"; + inven,secondary_name = "ak8963"; + inven,secondary_reg = <0x0c>; + inven,secondary_axis_map_x = <1>; + inven,secondary_negate_x = <0>; + inven,secondary_axis_map_y = <0>; + inven,secondary_negate_y = <0>; + inven,secondary_axis_map_z = <2>; + inven,secondary_negate_z = <1>; + interrupts-extended = GPIRQ_ACCEL; + }; +}; + +&i2c3b { + max77818@66 { + compatible = "maxim,max77823"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max77818>; + reg = <0x66>; + interrupts-extended = GPIRQ_MAX77818_INTB; + max77823,irq-gpio = GPIRQ_MAX77818_INTB; + max77823,wakeup = <1>; + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; +}; + +&max77823_battery { + status = "okay"; + battery,vendor = "SDI SDI"; + battery,charger_name = "max77823-charger"; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,bat_irq_attr = <0x3>; + + battery,chip_vendor = "QCOM"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + + battery,polling_time = <10 30 30 30 3600>; + + battery,adc_check_count = <6>; + + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_check; + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + + battery,temp_check_type = <2>; /* _BATTERY_TEMP_CHECK_TEMP */ + battery,temp_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_soc = <97>; + battery,full_condition_vcell = <4350000>; + + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <98>; + battery,recharge_condition_vcell = <4350000>; + + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + battery,chg_gpio_en = <0>; + battery,chg_polarity_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_status = <0>; + battery,chg_float_voltage = <4400>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 760 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 900 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 1000>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + usbotg-supply = <®_usbotg_vbus>; +}; + +&max77823_fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,fuel_alert_soc = <1>; + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + /* fuelgauge,repeated_fuelalert; */ +}; + +&kpp { + compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; + clocks = <&clks IMX6QDL_CLK_IPG>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_keypad>; + pinctrl-1 = <&pinctrl_keypad_sleep>; + linux,keymap = < + 0x0000003b /* leftmost key, KEY_F1(59)(0x3b) */ + 0x0100003c /* KEY_F2(60)(0x3c) */ + 0x0200003d /* KEY_F3(61)(0x3d) */ + 0x0001003e /* KEY_F4(62)(0x3e) */ + 0x0101003f /* KEY_F5(63)(0x3f) */ + 0x02010040 /* KEY_F6(64)(0x40) */ + 0x00020041 /* KEY_F7(65)(0x41) */ + 0x01020042 /* KEY_F8(66)(0x42) */ + 0x02020043 /* KEY_F9(67)(0x43) */ + 0x00030044 /* KEY_F10(68)(0x44) */ + 0x01030057 /* KEY_F11(87)(0x57) */ + 0x02030058 /* KEY_F12(88)(0x58) */ + 0x000400b7 /* KEY_F13(183)(0xb7) */ + 0x010400b8 /* KEY_F14(184)(0xb8) */ + 0x020400b9 /* KEY_F15(185)(0xb9) */ + 0x000500ba /* KEY_F16(186)(0xba) */ + 0x010500bb /* KEY_F17(187)(0xbb) */ + 0x020500bc /* rightmost key, KEY_F18(188)(0xbc) */ + >; + status = "okay"; +}; + +&mipi_csi { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_5v>; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + max-clock = <25000000>; + status = "okay"; +}; + +&usdhc4 { +#if 1 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; +#else + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +#endif + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-lshore.dtsi b/arch/arm/boot/dts/imx6qdl-lshore.dtsi new file mode 100644 index 00000000000000..5ef86221fcf9e9 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-lshore.dtsi @@ -0,0 +1,781 @@ +/* + * Copyright 2017 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lcd; + mxcfb1 = &fb_lvds; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + leds: leds { + compatible = "gpio-leds"; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: usbotg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi: wlan { + compatible = "regulator-fixed"; + regulator-name = "reg_wifi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound_sgtl5000: sound_sgtl5000 { + compatible = "fsl,imx6dl-lshore-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str = "ASIT500MA6F5D"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_di0>; + status = "okay"; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 100000>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <10>; + }; + + backlight_lvds: backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_lshore: iomuxc-imx6q-lshoregrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_lshore { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* ACC_INT1 */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* ACC_INT2 */ +#define GP_TUSB320_INT <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* TUSB320_INT */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x0b0b0 /* GPIO4 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x0b0b0 /* GPIO5 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x0b0b0 /* GPIO6 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 /* GPIO7 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b0 /* GPIO8 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0b0b0 /* GPIO10 */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0b0b0 /* GPIO11 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0b0b0 /* GPIO12 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 /* GPIO13 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0b0b0 /* SLEEP_PER */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* DISP0_CONTRAST */ +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 /* WL12xx_wl_irq */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b0 /* eMMC reset */ + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 +#define GP_ENET_PHY_INT <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: rtcgrp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_GSLX680 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GPIRQ_TOUCH <&gpio1 9 IRQ_TYPE_LEVEL_LOW> +#define GP_TOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_ipu1_di0: ipu1_di0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_LED_GREEN <&gpio3 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x030b0 +#define GP_LED_RED <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x030b0 +#define GP_LED_YELLOW <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_wifi: reg_wifigrp { + fsl,pins = < +#define GP_WL_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_MUTE <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0b0b0 /* CP2103_RESET */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* CP_SUSPEND */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_SD3_WP <&gpio7 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd0@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupts-extended = GP_ENET_PHY_INT; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + accelerometer@1d { + compatible = "fsl,mma8652"; + reg = <0x1d>; + position = <0>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-route = <1>; + }; + + tusb320@60 { + compatible = "ti,tusb320"; + reg = <0x60>; + tusb320,int-gpio = GP_TUSB320_INT; + tusb320,select-mode = <0>; + tusb320,dfp-power = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; + + gslx680_ts@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupts-extended = GPIRQ_GSLX680; + touchscreen-size-x = <480>; /* swapped below */ + touchscreen-size-y = <800>; + touchscreen-swapped-x-y; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di0"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + green { + gpios = GP_LED_GREEN; + retain-state-suspended; + default-state = "off"; + }; + + red { + gpios = GP_LED_RED; + retain-state-suspended; + default-state = "off"; + }; + + yellow { + gpios = GP_LED_YELLOW; + retain-state-suspended; + default-state = "off"; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi>; + gpio = GP_WL_EN; + startup-delay-us = <70000>; + enable-active-high; +}; + +®_usbotg_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = GP_USB_OTG_PWR; + enable-active-high; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc2 { /* WiFi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi>; + vqmmc-1-8-v; + ocr-limit = <0x180>; /* 1.65v - 2.1v */ + power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + ocr-limit = <0x80>; /* 1.65v - 1.95v */ + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mcs.dtsi b/arch/arm/boot/dts/imx6qdl-mcs.dtsi new file mode 100644 index 00000000000000..5dd517f6cb362e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mcs.dtsi @@ -0,0 +1,626 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_mcs: iomuxc-imx6q-mcsgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_mcs { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 +#define GP_4_5_WIRE_SELECT <&gpio5 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x130b0 +#define GP_4_5_WIRE_SELECT_R1 <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /* J54 pin 9 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 /* J54 pin 6 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b0 /* J54 pin 5 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* J54 pin 4 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* J54 pin 3 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* J54 pin 2 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 7 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_ar1021: i2c3-ar1021grp { + fsl,pins = < +#define GPIRQ_AR1021 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GP_AR1021 <&gpio1 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 /* pcie reset */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x130b1 +#define GP_LVDS_DE_15_4 <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b1 + >; + }; + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 +#define GP_UART3_TX_EN <&gpio2 26 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +#define GP_UART4_TX_EN <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x130b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +#define GP_UART5_TX_EN <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x130b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 +#define GP_USDHC2_CD <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10071 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17071 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17071 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17071 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17071 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17071 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17071 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17071 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17071 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17071 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc4; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + 4_5_WIRE_SELECT { + label = "5wire"; + gpios = GP_4_5_WIRE_SELECT; + linux,code = ; + }; + + 4_5_WIRE_SELECT_R1 { + label = "5wireR1"; + gpios = GP_4_5_WIRE_SELECT_R1; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + ar1020_i2c@4d { + compatible = "ar1020_i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ar1021>; + reg = <0x4d>; + interrupts-extended = GPIRQ_AR1021; + wakeup-gpios = GP_AR1021; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* wxga values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <3>; + vfront-porch = <80>; + hsync-len = <10>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +#define M_TX_EN 1 +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + control-gpios = GP_UART3_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; /* 1 to enable */ + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + control-gpios = GP_UART4_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; /* 1 to enable */ + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + control-gpios = GP_UART5_TX_EN; + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = <0>; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0>; + rs485_txen_mask = ; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; /* 1 to enable */ + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = GP_USDHC2_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mtp.dtsi b/arch/arm/boot/dts/imx6qdl-mtp.dtsi new file mode 100644 index 00000000000000..89be2d731f334b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mtp.dtsi @@ -0,0 +1,683 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_mtp: iomuxc-imx6q-mtpgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_mtp { + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* wl1271 btfunc5 */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* Pic GPIO2 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Pic GPIO1 */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* Pic IRQ */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* Pic GPIO148 */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 /* Pic GPIO149 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* BT_DC */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* BT_DD */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 /* BT_RESET */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /* BT_CPU_GPIO */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Gyro Irq - MPU9250, on I2C3 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b899 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b899 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 9 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x030b0 +#define GP_PCIE_RESET2 <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x030b0 +#define GP_PCIE_PON_RESET <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x030b0 +#define GP_PCIE_WAKE <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_reg_usbotg_vbus: usb_otg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b011 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b011 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 +#define GP_GPS_HEARTBEAT <&gpio5 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x030b0 +#define GPIRQ_GPS <&gpio5 22 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 +#define GP_GPS_RESET <&gpio5 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x0b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbh2_idle: usbh2_idlegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013038 + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013038 +#define GP_USBH2_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */ + >; + }; + + pinctrl_usbh2_active: usbh2_activegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017038 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10031 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17031 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17031 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17031 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17031 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17031 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio6 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; +}; + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + }; + + bt_rfkill: bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + reserved-memory { + linux,cma { + size = <0x08000000>; + }; + + camera_reserved: camera-reserved { + compatible = "shared-dma-pool"; +#if 0 + reusable; +#else + no-map; +#endif + size = <0x20000000>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_PON_RESET,GP_PCIE_RESET,GP_PCIE_RESET2; + status = "okay"; + + hub@pcie { + reg = <0x010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + usb@pcie { + reg = <0x010000 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + camera@1 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <1>; + }; + }; + + port@2 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + camera@1 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <1>; + }; + }; + + port@3 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + camera@1 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <1>; + }; + }; + + port@4 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + camera@1 { + compatible = "usb2a0b,00d3"; + memory-region = <&camera_reserved>; + reg = <1>; + }; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* TiWi(wl1271) bluetooth */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + reset-gpios = GP_USBH2_HUB_RESET; + osc-clkgate-delay = <0x3>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usbotg_vbus>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, silex/TiWi wl1271 */ + disable-adma1; + disable-adma2; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +/* Micro SD */ +&usdhc3 { +#if 0 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; +#endif + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* eMMC */ +&usdhc4 { +#if 0 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; +#endif + bus-width = <8>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-neol.dtsi b/arch/arm/boot/dts/imx6qdl-neol.dtsi new file mode 100644 index 00000000000000..f7b093ecf0caff --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-neol.dtsi @@ -0,0 +1,767 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_neol: iomuxc-imx6q-neolgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_neol { + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 +#define GP_ECSPI2_SS0 <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hdmi_cec: hdmi-cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_5V_DLP_EN <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130b0 +#define GP_STDBY_MODE <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 +#define GP_DLPC_BOOTED <&gpio2 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 +#define GP_INIT_DONE <&gpio2 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_RESET <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GP_KILL <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 +#define GP_MICRO_RESET <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + +#define GP_KEY_IO01 <&gpio4 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +#define GP_KEY_IO02 <&gpio4 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +#define GP_KEY_IO03 <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + +#define GP_KEY_IO07 <&gpio1 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GP_KEY_IO08 <&gpio2 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 +#define GP_KEY_IO09 <&gpio6 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 +#define GP_KEY_IO10 <&gpio2 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_KEY_IO11 <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + +#define GP_TP71 <&gpio1 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP72 <&gpio1 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP76 <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 +#define GP_TP113 <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 +#define GP_TP114 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_TP116 <&gpio2 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_TP118 <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +#define GP_TP121 <&gpio3 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 +#define GP_TP122 <&gpio1 18 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 +#define GP_I2C2_J14_PIN3 <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_I2C2_J14_PIN4 <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 +#define GP_I2C2_J14_PIN5 <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc2_wlan:usdhc2-wlangrp { + fsl,pins = < +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 +#define GP_WIFI_WAKE <&gpio2 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_WIFI_QOW <&gpio2 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x100b0 +#define GP_WIFI_CLK_REQ <&gpio6 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x130b0 +#define GP_BT_HOST_WAKE <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x130b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lcd; + mxcfb1 = &fb_hdmi; + pwm_lcd = &pwm1; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_SS0; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + tsc2004: tsc2004@48 { + compatible = "tsc2004"; + reg = <0x48>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, Silex or Tiwi */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 880bd782a5b70a..7b9676052c1ee8 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -41,9 +41,406 @@ #include #include +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nit6xlite: iomuxc-imx6q-nit6xlitegrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nit6xlite { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* J28 pin 7 - barcode scanner gpio */ + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt_rfkillgrp { + fsl,pins = < +#define GP_BRM_BT_WAKE <&gpio2 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 /* BT wake(Broadcom) */ +#define GP_BRM_BT_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 /* BT reset(Broadcom) */ +#define GP_BRM_BT_SHUTDOWN <&gpio6 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* BT reg en(Broadcom) */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 /* BT host wake irq(Broadcom) */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < +#define GP_HOME <&gpio7 13 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* J14 pin 5 - home button */ +#define GP_BACK <&gpio4 5 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* J14 pin 7 - back button */ + >; + }; + + pinctrl_hdmi_cec: hdmi-cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_TOUCH <&gpio1 9 IRQ_TYPE_LEVEL_LOW> +#define GP_TOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* J7 pin 4 - I2C3 */ +#define GPIRQ_TSC2004 <&gpio2 27 IRQ_TYPE_LEVEL_LOW> +#define GP_TSC2004 <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* tsc2004(I2C3) irq */ +#define GP_TSC2004_RESET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x030b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gslx680: i2c3_gslx680grp { + fsl,pins = < +#define GPIRQ_GSLX680 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +/* MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x130b0 */ +#define GP_GSLX680_POWER <&gpio7 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_ipu1_di0: ipu1_di0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lvds: ipu1_lvdsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* J6 pin 19, DISP0_CONTRAST */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_LED_GREEN <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 /* J14 pin 1 - GLED */ +#define GP_LED_RED <&gpio1 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 /* J14 pin 3 - RLED */ +#define GP_J14_POWER_ON <&gpio3 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 /* J14 pin 8/9(dry contact) */ +#define GP_J46_PIN2_I <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 /* J46 pin 2 - gp(inverted) */ +#define GP_J46_PIN3_I <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 /* J46 pin 3 - gp(inverted) */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_brm_wifi: reg_brm_wifigrp { + fsl,pins = < +#define GP_BRM_WL_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 /* Wifi reg en(Broadcom) */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 /* J10 pin 14 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* J10 pin 15 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* J10 pin 17 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* J10 pin 18 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* Clk req irq(Broadcom) */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* wake output(Broadcom) */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* Broadcom slow clock */ + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + /* USDHC3 - micro sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; +}; + / { - chosen { - stdout-path = &uart2; + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + mxcfb2 = &fb_hdmi; + pwm_lcd = &pwm3; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BRM_BT_RESET; + shutdown-gpios = GP_BRM_BT_SHUTDOWN; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + j14-pin1 { + gpios = GP_LED_GREEN; + retain-state-suspended; + default-state = "off"; + }; + + j14-pin3 { + gpios = GP_LED_RED; + retain-state-suspended; + default-state = "off"; + }; + + j14-pins8-9 { + gpios = GP_J14_POWER_ON; + retain-state-suspended; + default-state = "off"; + }; + + j46-pin2 { + gpios = GP_J46_PIN2_I; + retain-state-suspended; + default-state = "off"; + }; + + j46-pin3 { + gpios = GP_J46_PIN3_I; + retain-state-suspended; + default-state = "off"; + }; }; memory { @@ -55,214 +452,255 @@ #address-cells = <1>; #size-cells = <0>; - reg_2p5v: regulator@0 { + reg_1p8v: regulator@0 { compatible = "regulator-fixed"; reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - reg_3p3v: regulator@1 { + reg_3p3v: regulator@2 { compatible = "regulator-fixed"; - reg = <1>; + reg = <2>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_usb_otg_vbus: regulator@2 { + reg_brm_wifi: regulator@3 { compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_brm_wifi>; + regulator-name = "reg_brm_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_BRM_WL_EN; + startup-delay-us = <70000>; enable-active-high; }; - reg_wlan_vmmc: regulator@3 { + reg_usbotg_vbus: regulator@4 { compatible = "regulator-fixed"; - reg = <3>; + reg = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG_PWR; enable-active-high; }; }; - bt_rfkill { - compatible = "rfkill-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - name = "bt_rfkill"; - type = <2>; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - home { label = "Home"; - gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; - linux,code = <102>; + gpios = GP_HOME; + linux,code = ; }; back { label = "Back"; - gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; - linux,code = <158>; + gpios = GP_BACK; + linux,code = ; }; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - j14-pin1 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; + sound_sgtl5000: sound_sgtl5000 { + compatible = "fsl,imx6dl-nit6xlite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; - j14-pin3 { - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; + sound-hdmi { + compatible = "fsl,imx6dl-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; - j14-pins8-9 { - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; - j46-pin2 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str = "okaya_480x272"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; - j46-pin3 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; + fb_hdmi: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; }; - backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_di0>; status = "okay"; }; - backlight_lvds0: backlight_lvds0 { + backlight_j7 { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + default-brightness-level = <10>; + pwms = <&pwm1 0 100000>; }; - panel_lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm3 0 5000000>; + }; - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; }; - sound { - compatible = "fsl,imx6dl-nit6xlite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6dl-nit6xlite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; + pinctrl-0 = <&pinctrl_audmux3>; status = "okay"; }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - &ecspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + cs-gpios = GP_ECSPI1_NOR_CS; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; + compatible = "sst,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; }; }; &fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; status = "okay"; codec: sgtl5000@0a { @@ -278,258 +716,72 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; status = "okay"; - touchscreen@04 { + egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; + ft5x06_ts@38 { + compatible = "ft5x06-ts"; reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; }; - rtc@6f { - compatible = "isil,isl1208"; + gslx680_ts@40 { + compatible = "silead,gsl1680"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x6f>; - interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_i2c3_gslx680>; + reg = <0x40>; + interrupts-extended = GPIRQ_GSLX680; + power-gpios = GP_GSLX680_POWER; + touchscreen-size-x = <480>; /* swapped below */ + touchscreen-size-y = <800>; + touchscreen-swapped-x-y; }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j10>; - pinctrl-1 = <&pinctrl_j28>; - - imx6dl-nit6xlite { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_bt_rfkill: bt_rfkillgrp { - fsl,pins = < - /* BT wake */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* BT reset */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 - /* BT reg en */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* BT host wake irq */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Home Button: J14 pin 5 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Back Button: J14 pin 7 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - /* Touch IRQ: J7 pin 4 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - /* tcs2004 IRQ */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - /* tsc2004 reset */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 - >; - }; - - pinctrl_j10: j10grp { - fsl,pins = < - /* Broadcom WiFi module pins */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_j28: j28grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + reset-gpios = GP_TSC2004_RESET; + }; + isl1208@6f { + compatible = "isl,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; }; }; @@ -537,15 +789,46 @@ status = "okay"; lvds-channel@0 { + crtc = "ipu1-di0"; fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; @@ -555,18 +838,21 @@ status = "okay"; }; +/* I2c3(J7) pwm */ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; +/* LCD(J33) backlight */ &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; +/* LVDS(J6) backlight */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; @@ -574,6 +860,7 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -601,22 +888,20 @@ }; &usbotg { - vbus-supply = <®_usb_otg_vbus>; + vbus-supply = <®_usbotg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; status = "okay"; }; -&usdhc2 { +&usdhc2 { /* uSDHC2, Broadcom */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; bus-width = <4>; non-removable; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_wlan_vmmc>; + vmmc-supply = <®_brm_wifi>; vqmmc-1-8-v; - ocr-limit = <0x180>; /* 1.65v - 2.1v */ cap-power-off-card; keep-power-in-suspend; status = "okay"; @@ -624,8 +909,8 @@ &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + cd-gpios = GP_SD3_CD; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 01166ba36f2753..2fde0dfe9ca21f 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -41,92 +41,565 @@ #include #include +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen6_max: iomuxc-imx6q-nitrogen6-maxgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen6_max { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio7 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi-cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP71 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_HP_MUTE <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x130b0 /* amplifier mute, weak pull-down */ +#define GP_HEADPHONE_DET <&gpio4 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x100b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2a_ov5642: i2c2a-ov5642grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5642_POWER_DOWN <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0b0b0 +#define GP_OV5642_RESET <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x030b0 + >; + }; + + pinctrl_i2c2b_ov5640_mipi: i2c2b-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_i2c2b_tc358743_mipi: i2c2b-tc358743_mipigrp { + fsl,pins = < +#define GP_TC3587_RESET <&gpio6 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b0 +#define GP_TC3587_IRQ <&gpio2 5 GPIO_ACTIVE_HIGH> +#define GPIRQ_TC3587 <&gpio2 5 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < +#define GP_I2C2MUX_A <&gpio3 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x030b0 +#define GP_I2C2MUX_B <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ +#define GP_I2C3_ATMEL_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3MUX_A <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x030b0 /* pcie i2c enable */ + >; + }; + + pinctrl_i2c3_gt911: i2c3_gt911grp { + fsl,pins = < +#define GPIRQ_GT911 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT911_IRQ <&gpio1 9 GPIO_ACTIVE_HIGH> +/* MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 */ +#define GP_GT911_RESET <&gpio2 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x030b0 + >; + }; + + pinctrl_i2c3_ov5640: i2c3-ov5640grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_ov5640_gpios: i2c3-ov5640-gpiosgrp { + fsl,pins = < +#define GP_OV5640_POWER_DOWN <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 +#define GP_OV5640_RESET <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 +#define GP_UART5_RX_EN <&gpio6 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x030b0 /* RS485 RX Enable: pull down */ +#define GP_UART5_TX_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 /* RS485 DEN: pull down */ +#define GP_UART5_RS485_EN <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b0 /* RS485/!RS232 Select: pull down (rs232) */ +#define GP_UART5_AON <&gpio6 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 /* ON: pull down */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 11 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 /* sd3 voltage select */ +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + / { - chosen { - stdout-path = &uart2; + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + backlight_lvds2 = &backlight_lvds2; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + fb_lvds2 = &fb_lvds2; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + mxcfb2 = &fb_lvds2; + mxcfb3 = &fb_hdmi; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + pwm_lvds2 = &pwm2; + t_lvds = &t_lvds; + t_lvds2 = &t_lvds2; }; - memory { - reg = <0x10000000 0xF0000000>; + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + backlight_lvds2: backlight_lvds2 { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds2>; + pwms = <&pwm2 0 5000000>; + }; - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; }; + }; - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; - reg_usb_h1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; - reg_wlan_vmmc: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; + fb_lvds2: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; - reg_can_xcvr: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; + fb_hdmi: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; }; gpio-keys { @@ -134,42 +607,42 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; }; menu { label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + gpios = GP_GPIOKEY_MENU; linux,code = ; }; - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; }; - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; }; volume-up { label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + gpios = GP_GPIOKEY_VOL_UP; linux,code = ; }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; }; i2cmux@2 { @@ -178,18 +651,17 @@ pinctrl-0 = <&pinctrl_i2c2mux>; #address-cells = <1>; #size-cells = <0>; - mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH - &gpio4 15 GPIO_ACTIVE_HIGH>; + mux-gpios = GP_I2C2MUX_A, GP_I2C2MUX_B; i2c-parent = <&i2c2>; idle-state = <0>; - i2c2@1 { + i2c2a: i2c2@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; - i2c2@2 { + i2c2b: i2c2@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -202,131 +674,163 @@ pinctrl-0 = <&pinctrl_i2c3mux>; #address-cells = <1>; #size-cells = <0>; - mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + mux-gpios = GP_I2C3MUX_A; i2c-parent = <&i2c3>; idle-state = <0>; - i2c3@1 { + i2c3a: i2c3@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; }; - leds { - compatible = "gpio-leds"; - - speaker-enable { - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "off"; - }; - - ttymxc4-rs232 { - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "on"; - }; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; status = "okay"; }; - backlight_lvds0: backlight_lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + memory { + reg = <0x10000000 0xeffffc00>; }; - backlight_lvds1: backlight_lvds1 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ }; - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; + regulators { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - port@0 { + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; - port@1 { + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; }; - }; - - panel_lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; - }; - - panel_lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; }; - }; - panel_lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; }; }; sound { compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_max-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; - audio-codec = <&codec>; + audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; + "Headphone Jack", "HP_OUT", + "Ext Spk", "HP_OUT"; mux-int-port = <1>; mux-ext-port = <3>; + mute-gpios = GP_SGTL5000_HP_MUTE; + hp-detect-gpios = GP_HEADPHONE_DET; + /* + * mute the amplifier on the hp outputs + * when hp jack detected + */ + spk-mute-on-hp-detect; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1: v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_3: v4l2_cap_3 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -338,439 +842,391 @@ &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; status = "okay"; }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - &ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; status = "okay"; flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; + compatible = "sst,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; }; }; &fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; status = "okay"; - codec: sgtl5000@0a { + sgtl5000: sgtl5000@0a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; - - rtc: rtc@68 { - compatible = "st,rv4162"; + rv4162@68 { + compatible = "microcrystal,rv4162"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; reg = <0x68>; - interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = GPIRQ_RTC_RV4162; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c2a { + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ov5642: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2a_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c2b { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2b_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2b_tc358743_mipi>; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = GP_TC3587_RESET; + irq-gpios = GP_TC3587_IRQ; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <27000000>; + mclk_source = <0>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; status = "okay"; - touchscreen@04 { + atmel_maxtouch@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + reset-gpios = GP_I2C3_ATMEL_RESET; + }; + + egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; }; - touchscreen@38 { - compatible = "edt,edt-ft5x06"; + ft5x06_ts@38 { + compatible = "ft5x06-ts"; reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; }; -}; - -&iomuxc { - imx6q-nitrogen6_max { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2mux: i2c2muxgrp { - fsl,pins = < - /* ov5642 camera i2c enable */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 - /* ov5640_mipi camera i2c enable */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 - /* RS485 RX Enable: pull up */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 - /* RS485 DEN: pull down */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 - /* RS485/!RS232 Select: pull down (rs232) */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 - /* ON: pull down */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; + gt911@14 { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x14>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; + gt911@5d { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x5d>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ov5640 &pinctrl_i2c3_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_POWER_DOWN; + rst-gpios = GP_OV5640_RESET; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; }; -}; -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; }; &ldb { status = "okay"; lvds-channel@0 { + crtc = "ipu1-di1"; fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + lvds1080p: lvds1080p { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>; + hfront-porch = <88>; + vback-porch = <36>; + vfront-porch = <4>; + hsync-len = <44>; + vsync-len = <5>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; lvds-channel@1 { + crtc = "ipu1-di0"; fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; + display-timings { + t_lvds2: t_lvds2_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600_2: okaya7x0WP_2 { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar_2: hsd100pxn1_2 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; }; +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + reset-gpios = GP_PCIE_RESET; status = "okay"; }; @@ -799,6 +1255,7 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -814,31 +1271,60 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; + control-gpios = GP_UART5_RX_EN, GP_UART5_TX_EN, GP_UART5_RS485_EN, GP_UART5_AON; +#define M_RX_EN 1 +#define M_TX_EN 2 +#define M_RS485 4 +#define M_AON 8 + off_levels = <0>; + rxact_mask = <0>; + rxact_levels = <0>; + rs232_levels = ; + rs232_txen_mask = <0>; + rs232_txen_levels = <0>; + rs485_levels = <0xd>; + rs485_txen_mask = <0x3>; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; /* 1 to enable */ status = "okay"; }; &usbh1 { - vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; status = "okay"; }; &usbotg { - vbus-supply = <®_usb_otg_vbus>; + vbus-supply = <®_usbotg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; - vmmc-supply = <®_wlan_vmmc>; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; cap-power-off-card; keep-power-in-suspend; status = "okay"; @@ -847,9 +1333,8 @@ #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; ref-clock-frequency = <38400000>; }; }; @@ -857,8 +1342,8 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; bus-width = <4>; + cd-gpios = GP_USDHC3_CD; vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -868,6 +1353,7 @@ pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; non-removable; + vqmmc-1-8-v; vmmc-supply = <®_1p8v>; keep-power-in-suspend; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi new file mode 100644 index 00000000000000..8b6a4b09fbd672 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -0,0 +1,1149 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen6_som2: iomuxc-imx6q-nitrogen6-som2grp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen6_som2 { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_lvds2: backlight-lvds2grp { + fsl,pins = < +#define GP_BACKLIGHT_LVDS2 <&gpio2 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_SS0 <&gpio5 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP71 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio6 7 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_HP_MUTE <&gpio3 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 /* amplifier mute, weak pull-down */ +#define GP_SGTL5000_HP_DET <&gpio3 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x100b0 +#define GP_SGTL5000_MIC_DET <&gpio1 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x030b0 + >; + }; + + pinctrl_i2c2_ov5642: i2c2-ov5642grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5642_POWER_DOWN <&gpio1 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x0b0b0 +#define GP_OV5642_RESET <&gpio6 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x030b0 + >; + }; + + pinctrl_i2c2_tc358743_mipi: i2c2-tc358743_mipigrp { + fsl,pins = < +#define GP_TC3587_RESET <&gpio6 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b0 +#define GP_TC3587_IRQ <&gpio2 5 GPIO_ACTIVE_HIGH> +#define GPIRQ_TC3587 <&gpio2 5 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gt911: i2c3_gt911grp { + fsl,pins = < +#define GPIRQ_GT911 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT911_IRQ <&gpio1 9 GPIO_ACTIVE_HIGH> +/* MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 */ +#define GP_GT911_RESET <&gpio2 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x030b0 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < + /* tsc2004 interrupt on rgb connector J28 */ +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio3 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 +#define GP_PCIE_DISABLE <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + /* Backlight on RGB connector J28 */ + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + /* ov5640 mipi mclk */ + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + /* Backlight on LVDS connector: J6 */ + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + backlight_lvds2 = &backlight_lvds2; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + fb_lvds2 = &fb_lvds2; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + mxcfb2 = &fb_lvds2; + mxcfb3 = &fb_hdmi; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + t_lvds2 = &t_lvds2; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + backlight_lvds2: backlight_lvds2 { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds2>; + gpios = GP_BACKLIGHT_LVDS2; + display = <&fb_lvds2>; + default-on; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds2: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_SGTL5000_HP_MUTE; + hp-detect-gpios = GP_SGTL5000_HP_DET; + /* + * mute the amplifier on the hp outputs + * when hp jack detected + */ + spk-mute-on-hp-detect; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_3 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_SS0; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy { + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3d { + compatible = "ovti,ov5640_mipi"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; + + ov5642: ov5642@3e { + compatible = "ovti,ov5642"; + reg = <0x3e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_tc358743_mipi>; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = GP_TC3587_RESET; + irq-gpios = GP_TC3587_IRQ; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <27000000>; + mclk_source = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + gt911@14 { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x14>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; + + gt911@5d { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x5d>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; + + lvds-channel@1 { + crtc = "ipu1-di0"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + t_lvds2: t_lvds2_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_vm.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_vm.dtsi new file mode 100644 index 00000000000000..de218b7351eebd --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_vm.dtsi @@ -0,0 +1,802 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen6_vm: iomuxc-imx6q-nitrogen6_vmgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen6_vm { + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_VM_GPIO_1 <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0b0b0 +#define GP_VM_GPIO_2 <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0b0b0 +#define GP_VM_GPIO_3 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0b0b0 +#define GP_VM_GPIO_4 <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0b0b0 +#define GP_VM_GPIO_5 <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 +#define GP_VM_GPIO_6 <&gpio4 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x0b0b0 +#define GP_VM_GPIO_7 <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0b0b0 +#define GP_VM_GPIO_8 <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_HP_MUTE <&gpio5 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x030b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_PCAP_TOUCH <&gpio1 9 IRQ_TYPE_LEVEL_LOW> +#define GP_PCAP_TOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* J40 pin 4 - I2C3 and J57 pin 4 */ +#define PCAP_RESETN <&gpio1 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* J40 pin 3 */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_ar1021: i2c3-ar1021grp { + fsl,pins = < +#define GPIRQ_AR1021 <&gpio1 2 IRQ_TYPE_LEVEL_HIGH> +#define GP_AR1021 <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 +#define GP_AR1021_5_WIRE_SEL <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_ipu1_di0: ipu1_di0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* Contrast */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lvds: ipu1_lvdsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* J39 - pin 19, DISP0_CONTRAST */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < +#define GP_LED_1 <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Not used, keeps group from being empty */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + /* USDHC3 - FULL sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_lcd; + mxcfb1 = &fb_hdmi; + mxcfb2 = &fb_lvds; + pwm_lcd = &pwm3; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + leds: leds { + compatible = "gpio-leds"; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: usbotg_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG_PWR; + enable-active-high; + }; + }; + + magstripe: mag-stripe { + compatible = "boundary,magdecode"; + data_pin = <&gpio4 6 GPIO_ACTIVE_HIGH>; + clock_pin = <&gpio4 7 GPIO_ACTIVE_LOW>; + rear_pin = <&gpio4 8 GPIO_ACTIVE_LOW>; + front_pin = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sound_sgtl5000 { + compatible = "fsl,imx6dl-nitrogen6_vm-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_SGTL5000_HP_MUTE; + limit-to-16-bit-samples; + }; + + sound-hdmi { + compatible = "fsl,imx6dl-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + mode_str ="hitachi_hvga"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_di0>; + status = "okay"; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm3 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy { + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + at24@52 { + compatible = "ramtron,24c256"; + reg = <0x52>; + }; + + at24@53 { + compatible = "ramtron,24c256"; + reg = <0x53>; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + ar1021@4d { + compatible = "ar1020_i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ar1021>; + reg = <0x4d>; + interrupts-extended = GPIRQ_AR1021; + wakeup-gpios = GP_AR1021; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_PCAP_TOUCH; + wakeup-gpios = GP_PCAP_TOUCH; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_PCAP_TOUCH; + wakeup-gpios = GP_PCAP_TOUCH; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + okaya1024x600: okaya7x0WP { + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <7>; + vfront-porch = <21>; + hsync-len = <60>; + vsync-len = <10>; + }; + hannstar: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + j48-pinx { + gpios = GP_LED_1; /* Just a place holder */ + retain-state-suspended; + default-state = "off"; + }; +}; + +&pcie { + status = "okay"; +}; + +/* LCD(J58) backlight */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +/* LVDS(J39) backlight */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + cd-gpios = GP_USDHC3_CD; + wp-gpios = GP_USDHC3_WP; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index db868bc42c0f0b..f5f27255a5e121 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Boundary Devices, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * This file is dual-licensed: you can use it either under the terms @@ -43,41 +43,635 @@ #include #include +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen6x: iomuxc-imx6q-nitrogen6xgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen6x { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_audmux_tc358743: audmux-tc358743grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /* Spare */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* Spare */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_isl1208: i2c1-isl1208grp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio6 7 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + >; + }; + + pinctrl_i2c2_ov5642: i2c2-ov5642grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5642_POWER_DOWN <&gpio1 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 +#define GP_OV5642_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 + >; + }; + + pinctrl_i2c2_tc358743_mipi: i2c2-tc358743_mipigrp { + fsl,pins = < +#define GP_TC3587_RESET <&gpio6 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b0 +#define GP_TC3587_IRQ <&gpio2 5 GPIO_ACTIVE_HIGH> +#define GPIRQ_TC3587 <&gpio2 5 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7180_gpios: i2c3-adv7180_gpiosgrp { + fsl,pins = < + /* No data enable pin, make sure it is not selected */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b1 +#define GP_ADV7180_PWN <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 +#define GP_ADV7180_RESET <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 +#define GPIRQ_ADV7180 <&gpio5 0 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c3_adv7180: i2c3-adv7180grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_adv7180_cea861: i2c3-adv7180_cea861grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_adv7180_no_cea861: i2c3-adv7180_no_cea861grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b1 /* Hsync */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b1 /* Vsync */ + >; + }; + + pinctrl_i2c3_gt911: i2c3_gt911grp { + fsl,pins = < +#define GPIRQ_GT911 <&gpio1 9 IRQ_TYPE_LEVEL_HIGH> +#define GP_GT911_IRQ <&gpio1 9 GPIO_ACTIVE_HIGH> +/* MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 */ +#define GP_GT911_RESET <&gpio2 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x030b0 + >; + }; + + pinctrl_i2c3_ov5640: i2c3-ov5640grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_ov5640_gpios: i2c3-ov5640-gpiosgrp { + fsl,pins = < +#define GP_OV5640_POWER_DOWN <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 +#define GP_OV5640_RESET <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_lcd0_rgb: lcd0_rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + >; + }; + + pinctrl_lcd0_rgb24: lcd0_rgb24grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170B9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100B9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170B9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170B9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170B9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170F9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100F9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170F9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170F9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170F9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + / { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + mxcfb2 = &fb_hdmi; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + power-supply = <®_3p3v>; + pwms = <&pwm1 0 5000000>; + status = "okay"; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + power-supply = <®_3p3v>; + pwms = <&pwm4 0 5000000>; + status = "okay"; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + chosen { stdout-path = &uart2; }; + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default", "rgb24"; + pinctrl-0 = <&pinctrl_lcd0_rgb>; + pinctrl-1 = <&pinctrl_lcd0_rgb &pinctrl_lcd0_rgb24>; + status = "okay"; + }; + memory { reg = <0x10000000 0x40000000>; }; + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - reg_2p5v: regulator@0 { + reg_1p8v: regulator@0 { compatible = "regulator-fixed"; reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - reg_3p3v: regulator@1 { + reg_3p3v: regulator@2 { compatible = "regulator-fixed"; - reg = <1>; + reg = <2>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_usb_otg_vbus: regulator@2 { + reg_usb_otg_vbus: regulator@3 { compatible = "regulator-fixed"; - reg = <2>; + reg = <3>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -85,22 +679,11 @@ enable-active-high; }; - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - reg_wlan_vmmc: regulator@4 { compatible = "regulator-fixed"; reg = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; + pinctrl-0 = <&pinctrl_reg_wlan_vmmc>; regulator-name = "reg_wlan_vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -110,53 +693,10 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - sound { compatible = "fsl,imx6q-nitrogen6x-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6x-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = @@ -167,70 +707,61 @@ mux-ext-port = <3>; }; - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; }; - backlight_lvds: backlight_lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + sound-hdmi-input { + compatible = "fsl,imx-audio-tc358743"; + ssi-controller = <&ssi2>; + model = "imx-audio-tc358743"; + mux-int-port = <2>; + mux-ext-port = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_tc358743>; + status = "disabled"; }; - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; + v4l2_cap_0: v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; - lcd_panel { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; + v4l2_cap_1: v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; + v4l2_cap_2: v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_3: v4l2_cap_3 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -242,21 +773,14 @@ &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; status = "okay"; }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - &ecspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; + cs-gpios = GP_ECSPI1_NOR_CS; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -265,335 +789,300 @@ compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; }; }; &fec { + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 0>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; rxc-skew-ps = <3000>; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; txd0-skew-ps = <0>; txd1-skew-ps = <0>; txd2-skew-ps = <0>; txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; + txen-skew-ps = <0>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy { + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; status = "okay"; codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; - rtc: rtc@6f { + rtc: isl1208@6f { compatible = "isil,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_isl1208>; reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5642: ov5642@3d { + compatible = "ovti,ov5642"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; + + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_tc358743_mipi>; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = GP_TC3587_RESET; + irq-gpios = GP_TC3587_IRQ; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <27000000>; + mclk_source = <0>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; status = "okay"; - touchscreen@04 { + adv7180: adv7180@20 { + compatible = "adv,adv7180"; + reg = <0x20>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_i2c3_adv7180 &pinctrl_i2c3_adv7180_gpios>; + pinctrl-1 = <&pinctrl_i2c3_adv7180_no_cea861>; + pinctrl-2 = <&pinctrl_i2c3_adv7180_cea861>; + cea861 = <0>; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + rst-gpios = GP_ADV7180_RESET; + pwn-gpios = GP_ADV7180_PWN; + interrupts-extended = GPIRQ_ADV7180; + csi_id = <1>; + mclk = <28636300>; + mclk_source = <0>; + cvbs = <1>; + }; + + egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; }; - touchscreen@38 { - compatible = "edt,edt-ft5x06"; + ft5x06_ts@38 { + compatible = "ft5x06-ts"; reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-nitrogen6x { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - >; - }; + gt911@14 { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x14>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - >; - }; + gt911@5d { + compatible = "goodix,gt911"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gt911>; + reg = <0x5d>; + esd-recovery-timeout-ms = <2000>; + interrupts-extended = GPIRQ_GT911; + irq-gpios = GP_GT911_IRQ; + reset-gpios = GP_GT911_RESET; + }; - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; + ov5640: ov5640@3c { + compatible = "ov5640_int"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ov5640 &pinctrl_i2c3_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_POWER_DOWN; + rst-gpios = GP_OV5640_RESET; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; }; -}; -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; }; &ldb { status = "okay"; lvds-channel@0 { + crtc = "ipu1-di1"; fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; }; }; }; }; +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + &pcie { status = "okay"; }; @@ -617,6 +1106,12 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -632,7 +1127,18 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + &usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; status = "okay"; }; @@ -646,7 +1152,10 @@ &usdhc2 { pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wlan_vmmc>; @@ -658,9 +1167,8 @@ #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; ref-clock-frequency = <38400000>; }; }; @@ -668,7 +1176,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + cd-gpios = GP_USDHC3_CD; vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -676,7 +1184,7 @@ &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + cd-gpios = GP_USDHC4_CD; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nw2.dtsi b/arch/arm/boot/dts/imx6qdl-nw2.dtsi new file mode 100644 index 00000000000000..02ca5d89882a16 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nw2.dtsi @@ -0,0 +1,422 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_nitrogen6_max: iomuxc-imx6q-nitrogen6-maxgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_nitrogen6_max { + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 +#define GP_BT_RFKILL_SHUTDOWN <&gpio6 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GPIRQ_BT <&gpio6 16 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 +#define GP_BT_WAKE <&gpio2 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b0 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < +#define GPIRQ_WL <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 +#define GPIRQ_WL_CLK_REQ <&gpio6 9 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x100b0 + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + mmc0 = &usdhc4; + mxcfb0 = &fb_hdmi; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + shutdown-gpios = GP_BT_RFKILL_SHUTDOWN; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, Wifi GB863021 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-per.dtsi b/arch/arm/boot/dts/imx6qdl-per.dtsi new file mode 100644 index 00000000000000..34fe1602e101ac --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-per.dtsi @@ -0,0 +1,960 @@ +/* + * Copyright 2014 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_per: iomuxc-imx6q-pergrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_per { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* Audio - GS2971 */ + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1b070 + MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x1b070 + MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b070 + + /* Audio - TC3587 mipi hdmi input */ + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1b070 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1b070 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1b070 + + /* Audio - WM5102 */ + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b070 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b070 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b070 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b070 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 +#define GP_ECSPI2_GS2971_CS <&gpio2 26 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x0b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_WM5102_CS <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0b0b0 /* WM5102 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gs2971: gs2971grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_gs2971_cea861: gs2971_cea861grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_gs2971_no_cea861: gs2971_no_cea861grp { /* parallel camera */ + /* sav/eav codes are used, not hsync/vsync */ + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b1 /* HSYNC */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b1 /* VSYNC */ + >; + }; + + pinctrl_gs2971_gpios: gs2971_gpiosgrp { + fsl,pins = < +#define GPIO_INPUT 2 +#define GP_GS2971_STANDBY <&gpio5 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 /* 1 - pin K2 - Standby */ +#define GP_GS2971_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x000b0 /* 0 - pin C7 - reset */ +#define GP_GS2971_RC_BYPASS <&gpio4 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x000b0 /* 0 - pin G3 - RC bypass - output is buffered(low) */ +#define GP_GS2971_IOPROC_EN <&gpio4 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x000b0 /* 0 - pin H8 - io(A/V) processor enable */ +#define GP_GS2971_AUDIO_EN <&gpio4 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x000b0 /* 0 - pin H3 - Audio Enable */ +#define GP_GS2971_TIM_861 <&gpio4 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x000b0 /* 0 - pin H5 - TIM861 timing format, 1-use HSYNC/VSYNC */ +#define GP_GS2971_SW_EN <&gpio4 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x000b0 /* 0 - pin D7 - SW_EN - line lock enable */ +#define GP_GS2971_DVB_ASI <&gpio5 5 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b0 /* pin G8 i/o DVB_ASI */ +#define GP_GS2971_SMPTE_BYPASS <&gpio2 27 GPIO_INPUT> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* pin G7 - i/o SMPTE bypass */ +#define GP_GS2971_DVI_LOCK <&gpio3 14 GPIO_INPUT> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 /* pin B6 - stat3 - DVI_LOCK */ +#define GP_GS2971_DATA_ERR <&gpio3 15 GPIO_INPUT> + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 /* pin C6 - stat5 - DATA error */ +#define GP_GS2971_LB_CONT <&gpio3 20 GPIO_INPUT> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 /* pin A3 - LB control - float, analog input */ +#define GP_GS2971_Y_1ANC <&gpio4 26 GPIO_INPUT> + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* pin C5 - stat4 - 1ANC - Y signal detect */ + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* TP101 alert */ + MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x1b0b0 /* PTT_ON */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* power on J11 pin 3 */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* 1-wire enable */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* KL04 SWD_CLK */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* KL04 SWD_IO */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* KL04 Reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 /* KL04 Program */ + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 /* KL04 Irq */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 /* NC */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 /* NC */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 /* NC */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 /* NC */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 /* NC */ +#define GP_ANX7738_RESET <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x130b0 /* I_HDMI_RESET_N */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1a_tc358743_mipi: i2c1a-tc358743_mipigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* J13 pin1 - Video detect */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 /* J13 pin20 - HPD in */ +#define GP_TC3587_RESET <&gpio6 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x000b0 /* Reset */ +#define GPIRQ_TC3587 <&gpio6 14 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 /* Irq */ + >; + }; + + pinctrl_i2c1mux: i2c1muxgrp { + fsl,pins = < +#define GP_I2C1_MUX_KL04 <&gpio5 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x030b0 +#define GP_I2C1_MUX_ANX7814 <&gpio1 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x030b0 +#define GP_I2C1_MUX_AX7738 <&gpio2 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x030b0 +#define GP_I2C1_MUX_TC3587 <&gpio6 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_i2c1c_anx7814: i2c2a_anx7814grp { + fsl,pins = < +#define GP_ANX7814_P_DWN <&gpio1 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 /* O_HDMI_PD */ +#define GP_ANX7814_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 /* O_HDMI_RESET_N */ +#define GP_ANX7814_CBL_DET <&gpio2 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x130b0 /* O_HDMI_MYDP_DET_INTR */ +#define GP_ANX7814_HDMI_INTR <&gpio1 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 /* O_HDMI_INTR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < +#define GP_I2C2_MUX_ANX7814_DDC <&gpio1 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7180: i2c3-adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b1 +#define GP_ADV7180_RESET <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 /* Reset */ +#define GPIRQ_ADV7180 <&gpio1 9 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Irq */ + >; + }; + + pinctrl_i2c3_adv7180_cea861: i2c3-adv7180_cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + >; + }; + + pinctrl_i2c3_adv7180_no_cea861: i2c3-adv7180_no_cea861grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* Hsync */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* Vsync */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio5 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b0 /* pcie reset */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x000b0 /* Radio on */ + >; + }; + + pinctrl_uart1: uart1grp { /* UART1 - J2 - PTT connector */ + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { /* UART2 - debug console */ + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { /* UART3 - relay J3 */ + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* J3, pin 5 */ + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* J3, pin 6 */ + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* Relay Detect */ + MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x1b0b0 /* Carrier sense */ + >; + }; + + pinctrl_uart4: uart4grp { /* UART4 - GPS */ + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /* GPS reset */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* GPS Irq */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* GPS Heartbeat */ + >; + }; + + pinctrl_uart5: uart5grp { /* UART5 - J6 data connector */ + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x0b0b1 /* J6, pin 5 */ + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 /* J6, pin 6 */ + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x1b0b0 /* J6, pin 8 - Data detect */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* J6, Power enable */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* J6, pin 16 */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USB_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB Hub Reset for USB2512 4 port hub */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0b0b0 /* otg power en */ + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* eMMC reset */ + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4grp-2 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4grp-3 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; + + pinctrl_wm5102: wm5102grp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* MCLK2 */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 /* MCLK1 */ +#define GP_WM5102_RESET <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b0 /* Reset */ +#define GPIRQ_WM5102 <&gpio5 10 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 /* Irq */ +#define GP_WM5102_LDOENA <&gpio5 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x000b0 /* ldo enable */ +#define GP_WM5102_MIC_PTT_L <&gpio2 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 /* J2, pin 6: PTT_L */ +#define GP_WM5102_MIC_PTT_R <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 /* J2, pin 7: PTT_R */ + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + mmc0 = &usdhc4; + mxcfb0 = &fb_hdmi; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + i2c1mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C1_MUX_KL04, GP_I2C1_MUX_ANX7814, GP_I2C1_MUX_AX7738, GP_I2C1_MUX_TC3587; + i2c-parent = <&i2c1>; + idle-state = <0>; + + i2c1a: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1b: i2c1@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1c: i2c1@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1d: i2c1@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c2mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C2_MUX_ANX7814_DDC; + i2c-parent = <&i2c2>; + idle-state = <0>; + + i2c2a: i2c2@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_1p8v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG_PWR; + enable-active-high; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + sound-wm5102 { + compatible = "fsl,imx6q-per-wm5102", + "fsl,imx-audio-wm5102"; + model = "imx6q-per-wm5102"; + ssi-controller = <&ssi1>; + mux-int-port = <1>; + mux-ext-port = <6>; + }; + + v4l2_cap_0 { /* Adv7180 */ + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { /* TC3587 */ + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { /* GS2971 */ + compatible = "fsl,imx6q-v4l2-capture"; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_GS2971_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + gs2971: gs2971@0 { + compatible = "gn,gs2971"; + reg = <0>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_gs2971>, <&pinctrl_gs2971_gpios>; + pinctrl-1 = <&pinctrl_gs2971_no_cea861>; + pinctrl-2 = <&pinctrl_gs2971_cea861>; + mclk = <27000000>; + csi = <1>; + cea861 = <0>; + spi-max-frequency = <1000000>; + standby-gpios = GP_GS2971_STANDBY; /* 1 - powerdown */ + rst-gpios = GP_GS2971_RESET; /* 0 - reset */ + tim_861-gpios = GP_GS2971_TIM_861; /* 0 - TIM861 timing format sav/eav codes */ + /* enable on power up */ + ioproc_en-gpios = GP_GS2971_IOPROC_EN; /* 0 - io(A/V) processor disabled */ + sw_en-gpios = GP_GS2971_SW_EN; /* 0 - line lock disabled */ + rc_bypass-gpios = GP_GS2971_RC_BYPASS; /* 0 - RC bypass - output is buffered(low) */ + audio_en-gpios = GP_GS2971_AUDIO_EN; /* 0 - audio disabled */ + dvb_asi-gpios = GP_GS2971_DVB_ASI; /* 0 - dvs_asi disabled */ + smpte_bypass-gpios = GP_GS2971_SMPTE_BYPASS; /* in */ + dvi_lock-gpios = GP_GS2971_DVI_LOCK; /* in */ + data_err-gpios = GP_GS2971_DATA_ERR; /* in */ + lb_cont-gpios = GP_GS2971_LB_CONT; /* in */ + y_1anc-gpios = GP_GS2971_Y_1ANC; /* in */ + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI3_WM5102_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + codec: wm5102@0 { + compatible = "wlf,wm5102"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wm5102>; + clocks = <&clks IMX6QDL_CLK_CKO2>, <&clks IMX6QDL_CLK_CKIL>; + clock-names = "mclk1", "mclk2"; + interrupts-extended = GPIRQ_WM5102; + wlf,reset = GP_WM5102_RESET; + wlf,ldoena = GP_WM5102_LDOENA; + wlf,micptt-gpio = GP_WM5102_MIC_PTT_L, GP_WM5102_MIC_PTT_R; + wlf,micbias1 = <3300 1 1 1 1>; + wlf,micbias2 = <3300 1 1 1 1>; + wlf,inmode = <1 1 1 1>; + spi-max-frequency = <400000>; + DBVDD1-supply = <®_1p8v>; + DBVDD2-supply = <®_1p8v>; + DBVDD3-supply = <®_1p8v>; + AVDD-supply = <®_1p8v>; + CPVDD-supply = <®_1p8v>; + SPKVDDL-supply = <®_5v>; + SPKVDDR-supply = <®_5v>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <50000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + /* microcontroller KL04Z32TFK4 */ +}; + +&i2c1b { + anx7814: anx7814@38 { +#if 1 + compatible = "analogix,anx7814"; + /* uses many addresses: 0x38,0x39,0x3d,0x3f,0x40*/ + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1c_anx7814>; + pd-gpios = GP_ANX7814_P_DWN; + reset-gpios = GP_ANX7814_RESET; + analogix,cbl-det-gpio = GP_ANX7814_CBL_DET; + analogix,external-ldo-control= <0>; + analogix,v10-ctrl-gpio = <®_1p0v>; + analogix,v33-ctrl-gpio = <®_3p3v>; +#else + compatible = "anx7816"; + /* uses many addresses: 0x38,0x39,0x3d,0x3f,0x40*/ + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1c_anx7814>; + analogix,p-dwn-gpio = GP_ANX7814_P_DWN; + analogix,reset-gpio = GP_ANX7814_RESET; + analogix,cbl-det-gpio = GP_ANX7814_CBL_DET; + analogix,external-ldo-control= <0>; + analogix,v10-ctrl-gpio = <®_1p0v>; + analogix,v33-ctrl-gpio = <®_3p3v>; +#endif + + }; +}; + +&i2c1d { + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1a_tc358743_mipi>; + rst-gpios = GP_TC3587_RESET; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <27000000>; + mclk_source = <0>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c2a { + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + + adv7180: adv7180@20 { + compatible = "adv,adv7180"; + reg = <0x20>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_i2c3_adv7180>; + pinctrl-1 = <&pinctrl_i2c3_adv7180_no_cea861>; + pinctrl-2 = <&pinctrl_i2c3_adv7180_cea861>; + cea861 = <0>; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + rst-gpios = GP_ADV7180_RESET; + interrupts-extended = GPIRQ_ADV7180; + ipu_id = <0>; + csi_id = <0>; + mclk = <28636300>; + mclk_source = <0>; + cvbs = <1>; + }; +}; + +&mipi_csi { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi3 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USB_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc4 { +#if 0 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; +#endif + bus-width = <8>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index 585b4f6986c1cc..044d46ec99e24d 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -12,6 +14,10 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + }; + chosen { linux,stdout-path = &uart4; }; @@ -76,6 +82,17 @@ }; }; + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + }; &audmux { @@ -109,7 +126,15 @@ status = "okay"; }; -&hdmi { +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-rc.dtsi b/arch/arm/boot/dts/imx6qdl-rc.dtsi new file mode 100644 index 00000000000000..1ac65731d9f8e5 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-rc.dtsi @@ -0,0 +1,643 @@ +/* + * Copyright 2015 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_rc: iomuxc-imx6q-rcgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_rc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_HOG_TP68 <&gpio2 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 +#define GP_HOG_TP69 <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_HOG_TP70 <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_HOG_TP71 <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_HOG_TP77 <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_HOG_TP78 <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 +#define GPIRQ_IR <&gpio2 30 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GPIRQ_MIC_DET <&gpio1 2 IRQ_TYPE_EDGE_BOTH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 +#define GPIRQ_HP_DET <&gpio1 3 IRQ_TYPE_EDGE_BOTH> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio2 26 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x030b0 +#define GP_PCIE_DISABLE <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x030b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; +}; + +/ { + aliases { + fb_hdmi = &fb_hdmi; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + }; + + backlight_j7: backlight_j7 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <10>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-rc-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index 17704a5c1bcb5c..08596ca6f7fe83 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -1,6 +1,8 @@ /* * Copyright 2014 FEDEVEL, Inc. * + * Copyright 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * * Author: Robert Nelson * * This program is free software; you can redistribute it and/or modify @@ -13,6 +15,10 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + }; + chosen { stdout-path = &uart1; }; @@ -80,6 +86,17 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &audmux { @@ -112,8 +129,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -138,6 +162,11 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + eeprom@57 { compatible = "at,24c02"; reg = <0x57>; diff --git a/arch/arm/boot/dts/imx6qdl-s.dtsi b/arch/arm/boot/dts/imx6qdl-s.dtsi new file mode 100644 index 00000000000000..7950ed79cd9c87 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-s.dtsi @@ -0,0 +1,897 @@ +/* + * Copyright 2015 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_s: iomuxc-imx6q-sgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_s { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_CS1 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_TEMP_ALARM <&gpio2 21 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 +#define GP_FAN_FAIL <&gpio2 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_AC_FAIL <&gpio2 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 +#define GP_J5_PIN33 <&gpio1 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 +#define GP_J34_PIN6 <&gpio5 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 +#define GP_J34_PIN8 <&gpio6 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 +#define GP_ON_OFF <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_LED_RED <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0b0b0 +#define GP_LED_GREEN <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 +#define GP_LED_AMBER <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x0b0b0 +#define GP_J34_DRY1 <&gpio2 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x030b0 +#define GP_J34_DRY2 <&gpio5 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x030b0 +#define GP_TP_R201 <&gpio4 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_isl1208: i2c1-isl1208grp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio6 7 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_TDA7491P_GAIN0 <&gpio3 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x030b0 +#define GP_TDA7491P_GAIN1 <&gpio3 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x030b0 +#define GP_TDA7491P_STBY <&gpio2 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x030b0 +#define GP_TDA7491P_MUTE <&gpio2 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x030b0 +#define GPIRQ_MIC_DET <&gpio1 24 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_ov5642: i2c2a-ov5642grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5642_POWER_DOWN <&gpio3 29 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0b0b0 +#define GP_OV5642_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x030b0 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3_EDID <&gpio2 17 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x030b0 + >; + }; + + pinctrl_poweroff: poweroffgrp { + fsl,pins = < + /* Main power, high shuts down system */ +#define GP_POWER_OFF <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x0b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_tps: backlight_tps { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <5>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + temp-alarm { + label = "temp-alarm"; + gpios = GP_TEMP_ALARM; + linux,code = ; + }; + + fan-fail { + label = "fan-fail"; + gpios = GP_FAN_FAIL; + linux,code = ; + }; + + ac-fail { + label = "ac-fail"; + gpios = GP_AC_FAIL; + linux,code = ; + }; + + J5-pin33 { + label = "J5-pin33"; + gpios = GP_J5_PIN33; + linux,code = ; + }; + + J34-pin6 { + label = "J34-pin6"; + gpios = GP_J34_PIN6; + linux,code = ; + }; + + J34-pin8 { + label = "J34-pin8"; + gpios = GP_J34_PIN8; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_ON_OFF; + linux,code = ; + gpio-key,wakeup; + }; + }; + + i2cmux@3 { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = GP_I2C3_EDID; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3a: i2c3@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + poweroff: poweroff { + compatible = "gpio-poweroff"; + gpios = GP_POWER_OFF; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_poweroff>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-s-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Ext Spk", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_TDA7491P_MUTE; + amp-standby-gpios = GP_TDA7491P_STBY; + amp-gain-gpios = GP_TDA7491P_GAIN1, GP_TDA7491P_GAIN0; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS1; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + isl1208@6f { + compatible = "isl,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_isl1208>; + reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + ov5642: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c3a { + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <68936991>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <48>; + vback-porch = <8>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + cd-gpios = GP_USDHC4_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e000e6f12bf527..97ae485f2adab7 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -11,9 +11,58 @@ */ #include +#include / { - memory { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + gpio-keys { + compatible = "gpio-keys1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + home { + label = "Home"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + program { + label = "Program"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + }; + + memory: memory { reg = <0x10000000 0x80000000>; }; @@ -50,6 +99,14 @@ regulator-always-on; }; + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; reg = <1>; @@ -69,28 +126,159 @@ gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_si4763_vio1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio2: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vd: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_va: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_sd3_vmmc: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "P3V3_SDa_SWITCHED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay = <20000>; + /* remove below line to enable this regulator */ + status = "disabled"; + }; + + reg_can_en: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; }; sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; + "fsl,imx-audio-cs42888"; model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; + esai-controller = <&esai>; + asrc-controller = <&asrc>; audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; }; sound-spdif { @@ -108,6 +296,29 @@ default-brightness-level = <7>; status = "okay"; }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&asrc { + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; }; &clks { @@ -118,11 +329,23 @@ <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -153,19 +376,52 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,magic-packet; fsl,err006687-workaround-present; status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ + xceiver-supply = <®_can_stby>; + status = "disabled"; /* pin conflict with fec */ +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* pin conflict with uart3 */ + nand-on-flash-bbt; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; status = "okay"; }; -&hdmi { +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -175,6 +431,16 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio2>; + interrupts = <28 2>; + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + pmic: pfuze100@08 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -274,6 +540,11 @@ }; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + codec: cs42888@48 { compatible = "cirrus,cs42888"; reg = <0x48>; @@ -285,6 +556,19 @@ VLC-supply = <®_audio>; }; + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <®_si4763_va>; + vd-supply = <®_si4763_vd>; + vio1-supply = <®_si4763_vio1>; + vio2-supply = <®_si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; }; &i2c3 { @@ -292,6 +576,32 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + pwn-gpios = <&max7310_b 2 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio5>; + interrupts = <17 2>; + }; + max7310_a: gpio@30 { compatible = "maxim,max7310"; reg = <0x30>; @@ -312,6 +622,23 @@ gpio-controller; #gpio-cells = <2>; }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio2>; + interrupts = <29 1>; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio6>; + interrupts = <31 8>; + interrupt-route = <1>; + }; }; &iomuxc { @@ -319,11 +646,27 @@ pinctrl-0 = <&pinctrl_hog>; imx6qdl-sabreauto { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 >; }; @@ -341,6 +684,12 @@ >; }; + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 @@ -358,6 +707,12 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -377,6 +732,30 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 @@ -412,6 +791,30 @@ >; }; + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -419,6 +822,14 @@ >; }; + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 @@ -431,6 +842,24 @@ >; }; + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -444,6 +873,17 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -542,6 +982,12 @@ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 >; }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; }; }; @@ -551,6 +997,7 @@ lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; + primary; status = "okay"; display-timings { @@ -568,6 +1015,33 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; }; &pwm3 { @@ -576,12 +1050,44 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>, + <&clks IMX6QDL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>; + assigned-clock-rates = <0>, <227368421>; status = "okay"; }; +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>; + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -597,6 +1103,19 @@ vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -607,6 +1126,20 @@ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + /* + * Due to board issue, we can not use external regulator for card slot + * by default since the card power is shared with card detect pullup. + * Disabling the vmmc regulator will cause unexpected card detect + * interrupts. + * HW rework is needed to fix this isssue. Remove R695 first, then you + * can open below line to enable the using of external regulator. + * Then you will be able to power off the card during suspend. This is + * especially needed for a SD3.0 card re-enumeration working on UHS mode + * Note: reg_sd3_vmmc is also need to be enabled + */ + /* vmmc-supply = <®_sd3_vmmc>; */ + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 81dd6cd1937d4c..e64cfd708d108d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -1,5 +1,6 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Boundary Devices, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * This file is dual-licensed: you can use it either under the terms @@ -42,107 +43,557 @@ #include #include +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_sabrelite: iomuxc-imx6q-sabrelitegrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_sabrelite { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_audmux_tc358743: audmux-tc358743grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio3 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0b0b0 /* CAN enable */ + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 +#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 +#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 +#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 +#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 +#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + >; + }; + + pinctrl_i2c2_ov5642: i2c2-ov5642grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5642_POWER_DOWN <&gpio1 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 +#define GP_OV5642_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 + >; + }; + + pinctrl_i2c2_tc358743_mipi: i2c2-tc358743_mipigrp { + fsl,pins = < +#define GP_TC3587_RESET <&gpio6 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b0 +#define GP_TC3587_IRQ <&gpio2 5 GPIO_ACTIVE_HIGH> +#define GPIRQ_TC3587 <&gpio2 5 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3_adv7180_gpios: i2c3-adv7180_gpiosgrp { + fsl,pins = < + /* No data enable pin, make sure it is not selected */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b1 +#define GP_ADV7180_PWN <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 +#define GP_ADV7180_RESET <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 +#define GPIRQ_ADV7180 <&gpio5 0 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c3_adv7180: i2c3-adv7180grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_adv7180_cea861: i2c3-adv7180_cea861grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_adv7180_no_cea861: i2c3-adv7180_no_cea861grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b1 /* Hsync */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b1 /* Vsync */ + >; + }; + + pinctrl_i2c3_ov5640: i2c3-ov5640grp { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_i2c3_ov5640_gpios: i2c3-ov5640-gpiosgrp { + fsl,pins = < +#define GP_OV5640_POWER_DOWN <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 +#define GP_OV5640_RESET <&gpio3 14 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 + >; + }; + + pinctrl_i2c3_tsc2004: i2c3-tsc2004grp { + fsl,pins = < +#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING> +#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + >; + }; + + pinctrl_lcd0: lcd0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + / { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + mxcfb2 = &fb_hdmi; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lcd>; + power-supply = <®_3p3v>; + pwms = <&pwm1 0 5000000>; + status = "okay"; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&fb_lvds>; + power-supply = <®_3p3v>; + pwms = <&pwm4 0 5000000>; + status = "okay"; + }; + chosen { stdout-path = &uart2; }; + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_hdmi: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + back { + label = "Back"; + gpios = GP_GPIOKEY_BACK; + linux,code = ; + }; + + home { + label = "Home"; + gpios = GP_GPIOKEY_HOME; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = GP_GPIOKEY_MENU; + linux,code = ; + }; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = GP_GPIOKEY_VOL_DN; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_GPIOKEY_VOL_UP; + linux,code = ; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0>; + status = "okay"; + }; + memory { reg = <0x10000000 0x40000000>; }; + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - reg_2p5v: regulator@0 { + reg_1p8v: regulator@0 { compatible = "regulator-fixed"; reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - reg_3p3v: regulator@1 { + reg_3p3v: regulator@2 { compatible = "regulator-fixed"; - reg = <1>; + reg = <2>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_usb_otg_vbus: regulator@2 { + reg_usb_otg_vbus: regulator@3 { compatible = "regulator-fixed"; - reg = <2>; + reg = <3>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio3 22 0>; enable-active-high; }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; }; sound { compatible = "fsl,imx6q-sabrelite-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; + model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = @@ -153,70 +604,61 @@ mux-ext-port = <4>; }; - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; }; - backlight_lvds: backlight_lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; + sound-hdmi-input { + compatible = "fsl,imx-audio-tc358743"; + ssi-controller = <&ssi2>; + model = "imx-audio-tc358743"; + mux-int-port = <2>; + mux-ext-port = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_tc358743>; + status = "disabled"; }; - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; + v4l2_cap_0: v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; - lcd_panel { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; + v4l2_cap_1: v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; + v4l2_cap_2: v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_3: v4l2_cap_3 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -228,21 +670,14 @@ &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; status = "okay"; }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - &ecspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; + cs-gpios = GP_ECSPI1_NOR_CS; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -251,45 +686,84 @@ compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; }; }; &fec { + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; rxc-skew-ps = <3000>; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; txd0-skew-ps = <0>; txd1-skew-ps = <0>; txd2-skew-ps = <0>; txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; + txen-skew-ps = <0>; status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy { + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; status = "okay"; codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; @@ -299,246 +773,182 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5642: ov5642@3d { + compatible = "ovti,ov5642"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; + + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_tc358743_mipi>; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = GP_TC3587_RESET; + irq-gpios = GP_TC3587_IRQ; + interrupts-extended = GPIRQ_TC3587; + ipu_id = <0>; + csi_id = <0>; + mclk = <27000000>; + mclk_source = <0>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-sabrelite { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + adv7180: adv7180@20 { + compatible = "adv,adv7180"; + reg = <0x20>; + pinctrl-names = "default", "no_cea861", "cea861"; + pinctrl-0 = <&pinctrl_i2c3_adv7180 &pinctrl_i2c3_adv7180_gpios>; + pinctrl-1 = <&pinctrl_i2c3_adv7180_no_cea861>; + pinctrl-2 = <&pinctrl_i2c3_adv7180_cea861>; + cea861 = <0>; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + rst-gpios = GP_ADV7180_RESET; + pwn-gpios = GP_ADV7180_PWN; + interrupts-extended = GPIRQ_ADV7180; + csi_id = <1>; + mclk = <28636300>; + mclk_source = <0>; + cvbs = <1>; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ - >; - }; + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_ov5640 &pinctrl_i2c3_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_POWER_DOWN; + rst-gpios = GP_OV5640_RESET; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; }; -}; -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = GPIRQ_TSC2004; + wakeup-gpios = GP_TSC2004; + }; }; &ldb { status = "okay"; lvds-channel@0 { + crtc = "ipu1-di1"; fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; }; }; }; }; +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + &pcie { status = "okay"; }; @@ -562,6 +972,12 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -578,6 +994,10 @@ }; &usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; status = "okay"; }; @@ -592,8 +1012,8 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + cd-gpios = GP_USDHC3_CD; + wp-gpios = GP_USDHC3_WP; vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -601,7 +1021,7 @@ &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + cd-gpios = GP_USDHC4_CD; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi new file mode 100644 index 00000000000000..7164a9e44bc142 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD2 + * slot using Murata i.MX InterConnect Ver 2.0 Adapter & connecting Bluetooth + * UART & control signals via ribbon cable. + * This configuration supports both WLAN and Bluetooth. + * WL_REG_ON/BT_REG_ON/WL_HOST_WAKE are connected via ribbon cable (J13 connector + * on board). + * ==> Hardware modification is required. Refer to schematic. + */ + +/ { + leds { + compatible = "gpio-leds"; + status = "disabled"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 7 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + gpios = <&gpio4 6 0>; /* WL_HOST_WAKE */ + wlreg_on-supply = <&wlreg_on>; + }; +}; + +&ecspi1 { + status = "disabled"; +}; + +&iomuxc { + imx6qdl-sabresd-murata-v2 { + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* add MUXing entry for SD2 4-bit interface and configure control pins */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x13069 /* WL_REG_ON */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x13069 /* WL_HOST_WAKE */ + >; + }; + }; +}; + +&pinctrl_gpio_leds { + fsl,pins = < + >; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 8e9e0d98db2fd8..8aba9101ee9900 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -14,11 +14,51 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio2 24 1>; + uok_input = <&gpio1 27 1>; + chg_input = <&gpio3 23 1>; + flt_input = <&gpio5 2 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,usb_valid; + status = "okay"; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; + lvds1 { + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + }; + chosen { stdout-path = &uart1; }; - memory { + leds { + compatible = "gpio-leds"; + + charger-led { + gpios = <&gpio1 2 0>; + linux,default-trigger = "max8903-charger-charging"; + retain-state-suspended; + }; + }; + + memory: memory { reg = <0x10000000 0x40000000>; }; @@ -69,6 +109,34 @@ regulator-always-on; enable-active-high; }; + + reg_sensor: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "sensor-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 0>; + startup-delay-us = <500>; + enable-active-high; + }; + + reg_hdmi: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; + enable-active-high; + }; }; gpio-keys { @@ -102,20 +170,89 @@ compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; + asrc-controller = <&asrc>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", - "IN3R", "AMIC"; + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; }; - backlight_lvds: backlight-lvds { + backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -123,29 +260,32 @@ status = "okay"; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - red { - gpios = <&gpio1 2 0>; - default-state = "on"; - }; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; +&asrc { + status = "okay"; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -155,8 +295,11 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&clks { }; &ecspi1 { @@ -180,11 +323,46 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 0>; + fsl,magic-packet; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; status = "okay"; }; @@ -214,15 +392,66 @@ 0x8014 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; + amic-mono; }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <0>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio1>; + interrupts = <18 8>; + interrupt-route = <1>; + }; + + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, + on rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 2>; + wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + }; + + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ + }; + pmic: pfuze100@08 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -322,6 +551,27 @@ }; }; }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 201>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c3 { @@ -333,9 +583,30 @@ egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_egalax_int>; interrupt-parent = <&gpio6>; interrupts = <7 2>; - wakeup-gpios = <&gpio6 7 0>; + wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + vdd-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <9 2>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <16 1>; }; }; @@ -346,15 +617,29 @@ imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 >; }; @@ -376,6 +661,18 @@ >; }; + pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + >; + }; + + pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 @@ -397,6 +694,12 @@ >; }; + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 @@ -405,6 +708,19 @@ >; }; + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 @@ -419,6 +735,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2_gpio_grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -426,6 +749,59 @@ >; }; + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 @@ -451,6 +827,24 @@ >; }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -504,7 +898,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 >; }; }; @@ -521,25 +915,72 @@ &ldb { status = "okay"; - lvds-channel@1 { + lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - port@4 { - reg = <4>; + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; }; +&mipi_csi { + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -549,11 +990,30 @@ status = "okay"; }; +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + &snvs_poweroff { status = "okay"; }; &ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <1179648000>, <0>, <0>; status = "okay"; }; @@ -573,15 +1033,29 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; bus-width = <8>; cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -591,6 +1065,9 @@ bus-width = <8>; cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -600,6 +1077,7 @@ bus-width = <8>; non-removable; no-1-8-v; + keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-snap.dtsi b/arch/arm/boot/dts/imx6qdl-snap.dtsi new file mode 100644 index 00000000000000..4fb1597add6898 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-snap.dtsi @@ -0,0 +1,533 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + }; + + i2c3mux: i2cmux@3 { + compatible = "i2c-mux-gpio"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usbh1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + iomuxc_imx6q_snap: iomuxc-imx6q-snapgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_snap { + pinctrl_hog_1: hoggrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x1b0b0 + + /* spares on DB */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b0 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x1b0b0 + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3_EN_SATA <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x000b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b0 + >; + }; + + pinctrl_ov5640_mipi: ov5640_mipigrp { + fsl,pins = < +#define GP_OV5640_MIPI_RESET <&gpio6 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x0b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* XCLK */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_sata: satagrp { + fsl,pins = < +#define GP_HD_DETECT <&gpio2 30 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USBH1_HUB_RESET <&gpio2 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10031 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17031 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17031 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17031 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17031 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17031 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + +}; + +&i2c3mux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = GP_I2C3_EN_SATA; + + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3a: i2c3@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +®_usb_otg_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = GP_USB_OTG_PWR; + enable-active-high; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sp.dtsi b/arch/arm/boot/dts/imx6qdl-sp.dtsi new file mode 100644 index 00000000000000..4281e7c74ec6b6 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sp.dtsi @@ -0,0 +1,616 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + iomuxc_imx6q_sp: iomuxc-imx6q-spgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_sp { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* J46 pin 4 - back button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* J47 pin 5 - home button */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_ar1020: i2c1_ar1020grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x100b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* J7 pin 4 - I2C3 */ + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_ipu1_lvds: ipu1_lvdsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* J6 pin 19, DISP0_CONTRAST */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 /* J46 pin 2 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 /* J46 pin 3 */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 /* J46 pins 6-7 (Dry Contact) */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* PCIe reset */ + >; + }; + + pinctrl_piezo: piezo { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b0 /* Piezo speaker */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_brm_wifi: reg_brm_wifigrp { + fsl,pins = < +#define GP_BRM_WL_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 /* Wifi reg en(Broadcom) */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 /* J10 pin 14 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* J10 pin 15 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 /* J10 pin 16 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* J10 pin 17 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* J10 pin 18 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* Clk req irq(Broadcom) */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* wake output(Broadcom) */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 /* BT host wake irq(Broadcom) */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* Broadcom slow clock */ + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b1 /* GPS RESET */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b1 /* GPS INT */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b1 /* GPS heart beat */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + /* USDHC3 - micro sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_bt_rfkill: bt_rfkillgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 /* BT reset(Broadcom) */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 /* BT reg en(Broadcom) */ + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + bt_rfkill: bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + shutdown-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + home { + label = "Home"; + gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + linux,code = <102>; /* KEY_HOME */ + }; + + back { + label = "Back"; + gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; + linux,code = <158>; /* KEY_BACK */ + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + j46-pin2 { + gpios = <&gpio1 7 0>; + retain-state-suspended; + default-state = "off"; + }; + + j46-pin3 { + gpios = <&gpio1 8 0>; + retain-state-suspended; + default-state = "off"; + }; + cart-kill { + gpios = <&gpio3 29 0>; + retain-state-suspended; + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + pwmleds { + compatible = "pwm-leds"; + piezo { + label = "buzzer"; + pwms = <&pwm1 0 7812500>; + max-brightness = <256>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: usbotg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_brm_wifi: brm_wlan { + compatible = "regulator-fixed"; + regulator-name = "reg_brm_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + ar1020_i2c@4d { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_ar1020>; + compatible = "ar1020_i2c"; + reg = <0x4d>; +#define GPIRQ_AR1020 <&gpio7 1 IRQ_TYPE_LEVEL_HIGH> +#define GP_AR1020 <&gpio7 1 GPIO_ACTIVE_HIGH> + interrupts-extended = GPIRQ_AR1020; + wakeup-gpios = GP_AR1020; + }; + ads1000@49 { + compatible = "ads1000,ads1000"; + reg = <0x49>; + numerator = <55000>; /* 5V supply 500/50 (1/11) voltage divider */ + denominator = <2048>; /* 12-bit A/D */ + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + isl1208@6f { + compatible = "isl,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x6f>; +#define GPIRQ_RTC_ISL1208 <&gpio2 26 IRQ_TYPE_EDGE_FALLING> + interrupts-extended = GPIRQ_RTC_ISL1208; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu1-di0"; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + /* lg97 values may be changed in bootscript */ + clock-frequency = <100000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <260>; + hfront-porch = <480>; + vback-porch = <6>; + vfront-porch = <16>; + hsync-len = <250>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Piezo pwm */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_piezo>; + status = "okay"; +}; + +/* LVDS(J6) backlight */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +®_brm_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_brm_wifi>; + gpio = GP_BRM_WL_EN; + startup-delay-us = <70000>; + enable-active-high; +}; + +®_usbotg_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = GP_USB_OTG_PWR; + enable-active-high; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, Broadcom */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_brm_wifi>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi similarity index 83% rename from arch/arm/boot/dts/imx6qdl-microsom.dtsi rename to arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi index 3d62401dbd7fe5..b55af61dfecab1 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi @@ -10,17 +10,17 @@ * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * - * This file is distributed in the hope that it will be useful + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Or, alternatively + * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use + * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following @@ -29,18 +29,18 @@ * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include / { - clk_sdio: sdio-clock { + clk_brcm: brcm-clock { compatible = "gpio-gate-clock"; #clock-cells = <0>; pinctrl-names = "default"; @@ -48,27 +48,23 @@ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; }; - regulators { - compatible = "simple-bus"; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; + reg_brcm: brcm-reg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; }; usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_sdio>; + clocks = <&clk_brcm>; clock-names = "ext_clock"; }; }; @@ -104,13 +100,6 @@ >; }; - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - pinctrl_microsom_uart4: microsom-uart4 { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 @@ -133,12 +122,6 @@ }; }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; - /* UART4 - Connected to optional BRCM Wifi/BT/FM */ &uart4 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi new file mode 100644 index 00000000000000..5f3b8baab20ffa --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + microsom { + pinctrl_microsom_usdhc3: microsom-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +/* USDHC3 - eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc3>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi new file mode 100644 index 00000000000000..44a97ba93a9575 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + nvcc_sd1: regulator-nvcc-sd1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "nvcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + clk_ti_wifi: ti-wifi-clock { + /* This is a hack around the kernel - using "fixed clock" + * results in the "pinctrl" properties being ignored, and + * the clock not being output. Instead, use a gated clock + * and the unrouted WL_XTAL_PU gpio. + */ + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_clk>; + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + pwrseq_ti_wifi: ti-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + }; +}; + +&iomuxc { + microsom { + pinctrl_microsom_ti_bt: microsom-ti-bt { + fsl,pins = < + /* BT_EN_SOC */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 + >; + }; + + pinctrl_microsom_ti_clk: microsom-ti-clk { + fsl,pins = < + /* EXT_32K */ + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 + /* WL_XTAL_PU (unrouted) */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { + fsl,pins = < + /* WLAN_EN_SOC */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { + fsl,pins = < + /* WLAN_IRQ */ + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 + >; + }; + + pinctrl_microsom_uart4: microsom-uart4 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_microsom_usdhc1: microsom-usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + }; +}; + +/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart4>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_bt>; + }; +}; + +/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&pwrseq_ti_wifi>; + non-removable; + vmmc-supply = <&vcc_3v3>; + /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi similarity index 83% rename from arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi rename to arch/arm/boot/dts/imx6qdl-sr-som.dtsi index 469ef58ce4bc8c..94e0c6c338c602 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -1,9 +1,6 @@ /* * Copyright (C) 2013,2014 Russell King * - * This describes the hookup for an AR8035 to the iMX6 on the SolidRun - * MicroSOM. - * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a @@ -41,17 +38,29 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ +#include + +/ { + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-mode = "rgmii"; phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 0>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { - enet { + microsom { pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 @@ -59,10 +68,10 @@ /* AR8035 reset */ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 @@ -95,5 +104,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 >; }; + + pinctrl_microsom_uart1: microsom-uart1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; }; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ta.dtsi b/arch/arm/boot/dts/imx6qdl-ta.dtsi new file mode 100644 index 00000000000000..5136313e057322 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ta.dtsi @@ -0,0 +1,658 @@ +/* + * Copyright 2014 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + fb_lvds: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-WXGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usbh1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + sound { + compatible = "fsl,imx6q-ta-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + iomuxc_imx6q_ta: iomuxc-imx6q-tagrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_ta { + pinctrl_hog_1: hoggrp { + fsl,pins = < +#define GP_EXCH_OFF <&gpio3 11 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x130b0 + /* Heater */ +#define GP_HEATER_OFF <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x130b0 + /* LEDS */ +#define GP_LED_RED <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 + /* dry contact relays */ +#define GP_RELAY_EVENT <&gpio3 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x030b0 +#define GP_RELAY_GAS <&gpio3 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x030b0 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < +#define GP_INTERLOCK_IRQ <&gpio2 20 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 +#define GP_ZERO_CROSSING_IRQ <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 +#define GP_SYNC_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b0 +#define GP_HEATER_FAULT_IRQ <&gpio3 3 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 +#define GP_EXCH_FAULT1 <&gpio3 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 +#define GP_EXCH_FAULT2 <&gpio3 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GP_EXCH_FAULT_IRQ <&gpio3 10 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 +#define GP_CAN_CONNECT <&gpio3 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x130b0 +#define GP_UART1_DTR <&gpio3 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_TOUCH <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_TOUCH <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x0b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbusgrp { + fsl,pins = < +#define GP_USBH1_PWR <&gpio2 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + interlock { + label = "interlock"; + gpios = GP_INTERLOCK_IRQ; + linux,code = ; + gpio-key,wakeup; + }; + + zero_crossing { + label = "zero_crossing"; + gpios = GP_ZERO_CROSSING_IRQ; + linux,code = ; + }; + + sync { + label = "sync"; + gpios = GP_SYNC_IRQ; + linux,code = ; + }; + + heater_fault { + label = "heater_fault"; + gpios = GP_HEATER_FAULT_IRQ; + linux,code = ; + }; + + exch_fault1 { + label = "exch_fault1"; + gpios = GP_EXCH_FAULT1; + linux,code = ; + }; + + exch_fault2 { + label = "exch_fault2"; + gpios = GP_EXCH_FAULT2; + linux,code = ; + }; + + exch_fault_irq { + label = "exch_fault_irq"; + gpios = GP_EXCH_FAULT_IRQ; + linux,code = ; + }; + + can_connected { + label = "can_connect"; + gpios = GP_CAN_CONNECT; + linux,code = ; + }; + + uart1_dtr { + label = "uart1_dtr"; + gpios = GP_UART1_DTR; + linux,code = ; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_TOUCH; + wakeup-gpios = GP_I2C3_TOUCH; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_TOUCH; + wakeup-gpios = GP_I2C3_TOUCH; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_TOUCH; + wakeup-gpios = GP_I2C3_TOUCH; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + crtc = "ipu1-di0"; + + display-timings { + t_lvds: t_lvds_default { + /* values may be changed in bootscript */ + clock-frequency = <75000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <3>; + vfront-porch = <80>; + hsync-len = <10>; + vsync-len = <10>; + }; + }; + }; +}; + +®_usbh1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = GP_USBH1_PWR; + enable-active-high; +}; + +®_usb_otg_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = GP_USB_OTG_PWR; + enable-active-high; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index c96c91d8367851..6b4984feea936b 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * Author: Fabio Estevam * @@ -15,6 +15,7 @@ panelchan = &panelchan; panel7 = &panel7; touchscreenp7 = &touchscreenp7; + mxcfb0 = &mxcfb1; }; chosen { @@ -89,6 +90,17 @@ mux-int-port = <1>; mux-ext-port = <6>; }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; }; &fec { @@ -98,8 +110,15 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -108,6 +127,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/imx6qdl-usd.dtsi b/arch/arm/boot/dts/imx6qdl-usd.dtsi new file mode 100644 index 00000000000000..37c5b6c0a69167 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-usd.dtsi @@ -0,0 +1,759 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_usd: iomuxc-imx6q-usdgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_usd { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_lvds: backlight-lvdsgrp { + fsl,pins = < +#define GP_LVDS_J5_PIN36 <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000b1 +#define GP_ECSPI2_CS1 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0b0b1 +#define GP_KS8995_POWER_DOWN <&gpio5 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x030b0 +#define GP_KS8995_RESET <&gpio5 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x030b0 +#define GP_KS8995_SCRS <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x130b0 +#define GP_KS8995_SCOL <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_5V_STATUS <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x130b0 +#define GP_48V_STATUS <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x130b0 +#define GP_48V_FAULT <&gpio1 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x130b0 +#define GP_J33_PIN3_INPUT <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_REG_48V <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x030b0 +#define GP_POWER_J33 <&gpio7 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 +#define GP_LED1 <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x030b0 +#define GP_TP71 <&gpio1 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP83 <&gpio5 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 +#define GP_TP95 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_TP96 <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 +#define GP_TP_R210 <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_TDA7491P_GAIN0 <&gpio3 0 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 +#define GP_TDA7491P_GAIN1 <&gpio3 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x030b0 +#define GP_TDA7491P_STBY <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x030b0 +#define GP_TDA7491P_MUTE <&gpio3 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x030b0 +#define GPIRQ_MIC_DET <&gpio7 8 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio4 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GP_I2C3_J7_RESET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x030b0 +#define GP_PCIE_DISABLE <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x030b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10071 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17071 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17071 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17071 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17071 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17071 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17071 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17071 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17071 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17071 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <9>; + display = <&fb_lvds>; + enable-gpios = GP_LVDS_J5_PIN36; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds>; + pwms = <&pwm4 0 200000>; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + 5v_status { + label = "5v_status"; + gpios = GP_5V_STATUS; + linux,code = ; + }; + + 48v_status { + label = "48v_status"; + gpios = GP_48V_STATUS; + linux,code = ; + }; + + 48v_fault { + label = "48v_fault"; + gpios = GP_48V_FAULT; + linux,code = ; + }; + + j3 { + label = "j3"; + gpios = GP_J33_PIN3_INPUT; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-usd-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Ext Spk", "HP_OUT", + "Line Out Jack", "LINE_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + mute-gpios = GP_TDA7491P_MUTE; + amp-standby-gpios = GP_TDA7491P_STBY; + amp-gain-gpios = GP_TDA7491P_GAIN1, GP_TDA7491P_GAIN0; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS1; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + reset-gpios = GP_KS8995_RESET; + power-down-gpios = GP_KS8995_POWER_DOWN; + spi-max-frequency = <4000000>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ads1000@49 { + compatible = "ti,ads1000"; + reg = <0x49>; + }; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + reset-gpios = GP_I2C3_J7_RESET; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <68936991>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <48>; + vback-porch = <8>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-usd_mr2.dtsi b/arch/arm/boot/dts/imx6qdl-usd_mr2.dtsi new file mode 100644 index 00000000000000..3f628d94e51589 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-usd_mr2.dtsi @@ -0,0 +1,878 @@ +/* + * Copyright 2017 Boundary Devices, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_usd_mr2: iomuxc-imx6q-usd_mr2grp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_usd_mr2 { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + pinctrl_audmux4: audmux4grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_backlight_lvds: backlight-lvdsgrp { + fsl,pins = < +#define GP_LVDS_J5_PIN36 <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 +#define GP_ECSPI2_CS1 <&gpio5 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_5V_STATUS <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x130b0 +#define GP_48V_STATUS <&gpio4 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x130b0 +#define GP_CH1_INPUT <&gpio1 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 +#define GP_CH1_16V_FAULT <&gpio5 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x100b0 +#define GP_CH1_48V_FAULT <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x100b0 + +#define GP_CH2_INPUT <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 +#define GP_CH2_16V_FAULT <&gpio4 28 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x100b0 +#define GP_CH2_48V_FAULT <&gpio1 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x100b0 +>; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < +#define GP_CH1_16V <&gpio5 6 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x030b0 +#define GP_CH1_48V <&gpio4 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x030b0 +#define GP_CH1_RELAY_OUT <&gpio4 23 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x030b0 + +#define GP_CH2_16V <&gpio4 31 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x030b0 +#define GP_CH2_48V <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x030b0 +#define GP_CH2_RELAY_OUT <&gpio4 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x030b0 + +#define GP_LED1 <&gpio7 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x030b0 +#define GP_TP71 <&gpio1 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 +#define GP_TP74 <&gpio2 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_TP86 <&gpio4 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 +#define GP_TP87 <&gpio4 24 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 +#define GP_TP88 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 +#define GP_TP95 <&gpio2 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +#define GP_TP96 <&gpio5 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 +#define GP_TP100 <&gpio4 10 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +#define GP_TP_R65 <&gpio1 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 +#define GP_TP_R66 <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000a: i2c1-sgtl5000agrp { + fsl,pins = < +#define GP_CODEC_A_G1 <&gpio3 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 +#define GP_CODEC_A_G2 <&gpio3 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b0 +#define GP_CODEC_A_MUTE_N <&gpio3 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x030b0 +#define GP_CODEC_A_SHTDN_N <&gpio3 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x030b0 +#define GP_CODEC_A_FS1 <&gpio5 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0b0b0 +#define GP_CODEC_A_FS2 <&gpio5 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0b0b0 +#define GPIRQ_CODEC_A_MIC_DET <&gpio5 12 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000b: i2c1-sgtl5000bgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_CODEC_B_G1 <&gpio4 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0b0b0 +#define GP_CODEC_B_G2 <&gpio4 18 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0b0b0 +#define GP_CODEC_B_MUTE_N <&gpio3 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 +#define GP_CODEC_B_SHTDN_N <&gpio1 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x030b0 +#define GP_CODEC_B_FS1 <&gpio4 30 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0b0b0 +#define GP_CODEC_B_FS2 <&gpio4 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x0b0b0 +#define GPIRQ_CODEC_B_MIC_DET <&gpio7 8 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 +#define GP_CODEC_B_SYNC <&gpio1 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x030b0 +#define GP_CODEC_B_SYNC_CHAIN <&gpio1 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x030b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 +#define GP_OV5640_MIPI_POWER_DOWN <&gpio2 27 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio2 25 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GP_I2C3_J7_RESET <&gpio1 4 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x030b0 +#define GP_PCIE_DISABLE <&gpio4 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x030b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10071 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17071 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17071 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17071 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17071 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17071 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17071 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17071 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17071 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17071 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + backlight_lvds = &backlight_lvds; + fb_hdmi = &fb_hdmi; + fb_lvds = &fb_lvds; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lvds; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <9>; + display = <&fb_lvds>; + enable-gpios = GP_LVDS_J5_PIN36; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds>; + pwms = <&pwm4 0 200000>; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1280x720M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + 5v_status { + label = "5v_status"; + gpios = GP_5V_STATUS; + linux,code = ; + }; + + 48v_status { + label = "48v_status"; + gpios = GP_48V_STATUS; + linux,code = ; + }; + + ch1_input { + label = "ch1_input"; + gpios = GP_CH1_INPUT; + linux,code = ; + }; + + ch1_16v_fault { + label = "ch1_16v_fault"; + gpios = GP_CH1_16V_FAULT; + linux,code = ; + }; + + ch1_48v_fault { + label = "ch1_48v_fault"; + gpios = GP_CH1_48V_FAULT; + linux,code = ; + }; + + ch2_input { + label = "ch2_input"; + gpios = GP_CH2_INPUT; + linux,code = ; + }; + + ch2_16v_fault { + label = "ch2_16v_fault"; + gpios = GP_CH2_16V_FAULT; + linux,code = ; + }; + + ch2_48v_fault { + label = "ch2_48v_fault"; + gpios = GP_CH2_48V_FAULT; + linux,code = ; + }; + }; + + memory { + reg = <0x10000000 0xeffffc00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + }; + + sound_a { + compatible = "fsl,imx6q-usd-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio-a"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000a>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Ext Spk", "HP_OUT", + "Line Out Jack", "LINE_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + mute-gpios = GP_CODEC_A_MUTE_N; + /* delay between mute and standby enter */ + amp-standby-enter-wait-ms = <50>; + /* delay between standby exit and unmute */ + amp-standby-exit-delay-ms = <100>; + amp-standby-gpios = GP_CODEC_A_SHTDN_N; + amp-gain-gpios = GP_CODEC_A_G1, GP_CODEC_A_G2; + amp-gain-seq = /bits/ 8 <1 0 2 3>; + }; + + sound_b { + compatible = "fsl,imx6q-usd-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio-b"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000b>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Ext Spk", "HP_OUT", + "Line Out Jack", "LINE_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + mute-gpios = GP_CODEC_B_MUTE_N; + /* delay between mute and standby enter */ + amp-standby-enter-wait-ms = <50>; + /* delay between standby exit and unmute */ + amp-standby-exit-delay-ms = <100>; + amp-standby-gpios = GP_CODEC_B_SHTDN_N; + amp-gain-gpios = GP_CODEC_B_G1, GP_CODEC_B_G2; + amp-gain-seq = /bits/ 8 <1 0 2 3>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>,<&pinctrl_audmux4>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS1; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000a: sgtl5000@2a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000a>; + reg = <0x2a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + sgtl5000b: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000b>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ads1000@49 { + compatible = "ti,ads1000"; + reg = <0x49>; + }; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + reset-gpios = GP_I2C3_J7_RESET; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + clock-frequency = <68936991>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <48>; + vback-porch = <8>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-utc.dtsi b/arch/arm/boot/dts/imx6qdl-utc.dtsi new file mode 100644 index 00000000000000..e354b757f8b5d2 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-utc.dtsi @@ -0,0 +1,856 @@ +/* + * Copyright 2015 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_utc: iomuxc-imx6q-utcgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_utc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio6 16 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 +#define GPIRQ_ENET <&gpio1 6 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 +#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < +#define GP_SPARE1 <&gpio7 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /* Spare */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* UGPIO5 */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* UGPIO7 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* UGPIO8 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* UGPIO9 */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 /* spare */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 /* UGPIO10 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* CSI RGB GP */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* UGPIO0 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* UGPIO1 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* UGPIO3/CSI RGB GP */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* UGPIO4 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* UGPIO12/Microphone Detect */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* spare */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 /* J6 - LVDS Display */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c1_isl1208: i2c1-isl1208grp { + fsl,pins = < +#define GPIRQ_RTC_ISL1208 <&gpio2 27 IRQ_TYPE_EDGE_FALLING> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */ +#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_OV5640_MIPI_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio4 8 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio3 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x030b0 /* UGPIO13/PCIe reset */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_reg_wlan_en: reg-wlan-engrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b0 +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbusgrp { + fsl,pins = < +#define GP_USBH1_PWR <&gpio2 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ +#define GPIRQ_WL1271 <&gpio6 14 IRQ_TYPE_LEVEL_HIGH> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17071 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10071 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17071 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17071 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17071 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17071 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17071 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17071 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17071 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17071 +#define GP_EMMC_RESET <&gpio2 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 /* EMMC reset */ + >; + }; +}; + +/ { + aliases { + backlight_lcd = &backlight_lcd; + backlight_lvds = &backlight_lvds; + fb_lcd = &fb_lcd; + fb_lvds = &fb_lvds; + lcd = &lcd; + ldb = &ldb; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_lvds; + mxcfb1 = &fb_lcd; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + t_lvds = &t_lvds; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm1 0 5000000>; + }; + + backlight_lvds: backlight_lvds { + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lvds>; + pwms = <&pwm4 0 5000000>; + }; + + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + fb_lcd: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lvds: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + spare { + label = "spare"; + gpios = GP_SPARE1; + linux,code = ; + gpio-key,wakeup; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USBH1_PWR; + enable-active-high; + }; + + reg_usbotg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; + + reg_wlan_en: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan_en>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = GP_REG_WLAN_EN; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-utc-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mipi_camera = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_FLEXCAN1_STANDBY; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + interrupts-extended = GPIRQ_ENET, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy@6 { + reg = <6>; + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + isl1208@6f { + compatible = "isl,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_isl1208>; + reg = <0x6f>; + interrupts-extended = GPIRQ_RTC_ISL1208; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_ov5640_mipi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5640_MIPI_POWER_DOWN; + rst-gpios = GP_OV5640_MIPI_RESET; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_I2C3_J7; + wakeup-gpios = GP_I2C3_J7; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + crtc = "ipu1-di1"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + primary; + + display-timings { + t_lvds: t_lvds_default { + /* lg1280x800 values may be changed in bootscript */ + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <48>; + hfront-porch = <80>; + vback-porch = <15>; + vfront-porch = <2>; + hsync-len = <32>; + vsync-len = <6>; + }; + }; + }; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-vp.dtsi b/arch/arm/boot/dts/imx6qdl-vp.dtsi new file mode 100644 index 00000000000000..61a0dc124cf911 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-vp.dtsi @@ -0,0 +1,1045 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + aliases { + backlight_lcd = &backlight_lcd; + fb_hdmi = &fb_hdmi; + fb_lcd = &fb_lcd; + lcd = &lcd; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + mmc2 = &usdhc2; + mxcfb0 = &fb_hdmi; + mxcfb1 = &fb_lcd; + pwm_lcd = &pwm1; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbotg_vbus: usbotg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh1_vbus: usbh1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + gpio_keys: gpio_keysgrp { + compatible = "gpio-keys"; + }; + + sound_sgtl5000: sound_sgtl5000 { + compatible = "fsl,imx6q-vp-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Line Out Jack", "LINE_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + fb_hdmi: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + fb_lcd: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB24"; + mode_str ="480x272MR@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_di0>; + status = "okay"; + }; + + backlight_lcd: backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <10>; + display = <&fb_lcd>; + pwms = <&pwm1 0 50000>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + i2c3mux: i2c3muxgrp { + compatible = "i2c-mux-gpio"; + }; + + uart4_gps_rfkill: uart4_gps_rfkill { + compatible = "net,rfkill-gpio"; + }; + + wlan_bt_rfkill: wlan_bt_rfkillgrp { + compatible = "net,rfkill-gpio"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_imx6q_vp: iomuxc-imx6q-vpgrp { + status = "okay"; + }; +}; + +&iomuxc_imx6q_vp { + pinctrl_hog: hoggrp { + fsl,pins = < + /* Main power on, high shuts down system */ +#define GP_MAIN_POWER_EN <&gpio1 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x030b0 +#define GP_LED_BLUE <&gpio2 24 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0b0b0 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < +#define GP_MAIN_POWER_BUTTON <&gpio1 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 +#define GP_MENU <&gpio2 1 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b0 +#define GP_BACK <&gpio4 5 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0b0b0 +#define GP_SEARCH <&gpio2 3 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b0 +#define GP_VOLUME_UP <&gpio7 13 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0b0b0 +#define GP_INPUT1 <&gpio4 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0b0b0 +#define GP_INPUT2 <&gpio4 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmi_cecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < +#define GP_I2C3_PCIE_EN <&gpio2 25 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0b0b0 +#define GP_I2C3_MAX77818_EN <&gpio3 2 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x0b0b0 + >; + }; + + pinctrl_i2c3_max77818: i2c3_max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_INOKB <&gpio3 4 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 +#define GPIRQ_MAX77818_WCINOKB <&gpio3 5 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 +#define GPIRQ_MAX77818_INTB <&gpio3 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 + >; + }; + + pinctrl_i2c3_touchscreen: i2c3_touchscreengrp { + fsl,pins = < +#define GP_TOUCH_RESET <&gpio2 22 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0b0b0 +#define GPIRQ_TOUCH <&gpio2 27 IRQ_TYPE_LEVEL_LOW> +#define GP_TOUCH <&gpio2 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + >; + }; + + pinctrl_ipu1_di0: ipu1_di0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 /* DRDY */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* Contrast */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio6 31 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b0 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 6 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ +#define GP_SGTL5000_MUTE <&gpio1 29 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x030b0 +#define GP_HEADPHONE_DET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 +#define GP_LINE_IN_JACK_DETECT <&gpio1 17 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 +#define GP_MIC_DETECT <&gpio7 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + /* Bluetooth */ + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + /* GPS */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 +#define GP_GPS_IRQ <&gpio6 1 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x1b0b0 +#define GP_GPS_HEARTBEAT <&gpio6 2 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0 +#define GP_GPS_ANT_ON <&gpio3 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b0 + >; + }; + + pinctrl_uart4_gps_rfkill: uart4_gps_rfkillgrp { + /* GPS */ + fsl,pins = < +#define GP_GPS_RESET <&gpio6 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0b8b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USB_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 +#define GP_5V_EN <&gpio1 7 GPIO_ACTIVE_HIGH> /* usb and hdmi 5v*/ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x030b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_DN1_PWR_EN <&gpio1 4 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotg_vbus: usbotg_vbusgrp { + fsl,pins = < + /* power enable, high active */ +#define GP_USB_OTG_PWR <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + /* USDHC2: Broadcom Wifi */ + pinctrl_usdhc2_50mhz: usdhc2_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17031 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10031 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17031 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17031 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17031 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17031 +#define GP_BRM_WL_WAKE_IRQ <&gpio6 11 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 +#define GP_BRM_CLOCK_REQUEST <&gpio6 9 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 +#define GP_BRM_WL_EN <&gpio6 7 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* slow clock */ + >; + }; + + /* USDHC3 - micro sd */ + pinctrl_usdhc3_50mhz: usdhc3_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10031 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17031 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17031 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17031 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17031 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17031 +#define GP_SD3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4_50mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10031 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17031 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17031 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17031 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17031 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17031 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17031 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17031 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17031 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17031 +#define GP_EMMC_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4_100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100b9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170b9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170b9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170b9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170b9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170b9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170b9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170b9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170b9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4_200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100f9 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170f9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170f9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170f9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170f9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170f9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170f9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170f9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170f9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170f9 + >; + }; + + pinctrl_wlan_bt_rfkill: wlan_bt_rfkillgrp { + fsl,pins = < +#define GP_BRM_BT_RESET <&gpio6 8 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 /* BT reset(Broadcom) */ +#define GP_BRM_BT_SHUTDOWN <&gpio6 15 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 /* BT reg en(Broadcom) */ +#define GP_BRM_BT_WAKE_IRQ <&gpio2 7 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 +#define GP_BRM_BT_WAKEUP <&gpio6 16 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0f0b0 + >; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + power { + label = "Power Button"; + gpios = GP_MAIN_POWER_BUTTON; + linux,code = ; + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = GP_MENU; + linux,code = ; + }; + + back { + label = "Back"; + gpios = GP_BACK; + linux,code = ; + }; + + search { + label = "Search"; + gpios = GP_SEARCH; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = GP_VOLUME_UP; + linux,code = ; + }; + + input1 { + label = "Input 1"; + gpios = GP_INPUT1; + linux,code = ; + }; + + input2 { + label = "Input 2"; + gpios = GP_INPUT2; + linux,code = ; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <1>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; + + ili210x@41 { + compatible = "ili210x"; + reg = <0x41>; + interrupts-extended = GPIRQ_TOUCH; + wakeup-gpios = GP_TOUCH; + }; +}; + +&i2c3mux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = GP_I2C3_PCIE_EN, GP_I2C3_MAX77818_EN; + + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3a: i2c3@1 { + /* PCIe */ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3b: i2c3@2 { + /* MAX77818 */ + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c3b { + max77818@66 { + compatible = "maxim,max77823"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_max77818>; + reg = <0x66>; + interrupts-extended = GPIRQ_MAX77818_INTB; + max77823,irq-gpio = GPIRQ_MAX77818_INTB; + max77823,wakeup = <1>; + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; +}; + +&max77823_battery { + status = "okay"; + battery,vendor = "SDI SDI"; + battery,charger_name = "max77823-charger"; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,bat_irq_attr = <0x3>; + + battery,chip_vendor = "QCOM"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + + battery,polling_time = <10 30 30 30 3600>; + + battery,adc_check_count = <6>; + + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_check; + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + + battery,temp_check_type = <2>; /* _BATTERY_TEMP_CHECK_TEMP */ + battery,temp_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_soc = <97>; + battery,full_condition_vcell = <4350000>; + + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <98>; + battery,recharge_condition_vcell = <4350000>; + + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + battery,chg_gpio_en = <0>; + battery,chg_polarity_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_status = <0>; + battery,chg_float_voltage = <4400>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 760 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 900 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 1000>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + usbotg-supply = <®_usbotg_vbus>; +}; + +&max77823_fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,fuel_alert_soc = <1>; + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + /* fuelgauge,repeated_fuelalert; */ + temp-calibration = <0 (-6763) 9858>; + /* if temp-calibration defined, temp-calibration-data not used */ + temp-calibration-data = <250 0x7cde + 255 0x7c50 + 260 0x7aa0 + 265 0x792e + 270 0x788e + 275 0x7714 + 280 0x761a + 285 0x7536 + 290 0x73ca + 295 0x7326 + 300 0x726c + 305 0x71cc + 310 0x71b2 + 315 0x70a4 + 320 0x6f6a + 325 0x6eae + 330 0x6a2e + 335 0x6800 + 340 0x673c + 345 0x665a + 350 0x65b4 + 355 0x6478 + 360 0x6318 + 365 0x6270 + 370 0x614e + 375 0x5f56 + 380 0x5ed2 + 385 0x5d9e + 390 0x5b38 + 395 0x5ae0 + 400 0x59ce + 405 0x57b2 + 410 0x55f2 + 415 0x53c2 + 420 0x505a>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +®_usbh1_vbus { + gpio = GP_USB_DN1_PWR_EN; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; +}; + +®_usbotg_vbus { + gpio = GP_USB_OTG_PWR; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; +}; + +&sound_sgtl5000 { + line-out-mute-gpios = GP_SGTL5000_MUTE; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4_gps_rfkill { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_gps_rfkill>; + type = <6>; /* gps */ + gpios = GP_GPS_RESET; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + reset-gpios = GP_USB_HUB_RESET; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, Broadcom */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-1-8-v; + power-gpio = GP_BRM_WL_EN; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + bus-width = <4>; + cd-gpios = GP_SD3_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; + +&wlan_bt_rfkill { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_bt_rfkill>; + type = <2>; /* bluetooth */ + reset-gpios = GP_BRM_BT_RESET; + shutdown-gpios = GP_BRM_BT_SHUTDOWN; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 2b9c2be436f944..0fb20cd3157e31 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * Author: Fabio Estevam * @@ -64,11 +64,6 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c1>; - status = "okay"; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b13b0b2db88163..776d9e3fa81fcb 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -78,6 +78,11 @@ interrupt-parent = <&gpc>; ranges; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + dma_apbh: dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; @@ -91,6 +96,16 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + gpmi: gpmi-nand@00112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -160,6 +175,18 @@ power-domains = <&gpc 1>; }; + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -211,6 +238,7 @@ <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; status = "disabled"; }; @@ -219,6 +247,45 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; + hdmi_core: hdmi_core@00120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x00120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@020e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x020e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@00120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 25 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@00120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + aips-bus@02000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -241,8 +308,8 @@ <&sdma 15 18 0>; dma-names = "rx", "tx"; clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, + <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", @@ -262,7 +329,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI1>, <&clks IMX6QDL_CLK_ECSPI1>; clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -276,7 +343,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI2>, <&clks IMX6QDL_CLK_ECSPI2>; clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -290,7 +357,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI3>, <&clks IMX6QDL_CLK_ECSPI3>; clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -304,7 +371,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI4>, <&clks IMX6QDL_CLK_ECSPI4>; clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -346,8 +413,8 @@ clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, <&clks IMX6QDL_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, + <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -362,8 +429,8 @@ clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, <&clks IMX6QDL_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, + <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -378,8 +445,8 @@ clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, <&clks IMX6QDL_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, + <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -407,7 +474,7 @@ "txa", "txb", "txc"; fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; - status = "okay"; + status = "disabled"; }; spba@0203c000 { @@ -427,6 +494,24 @@ power-domains = <&gpc 1>; resets = <&src 1>; iram = <&ocram>; + status = "disabled"; + }; + + vpu_fsl: vpu_fsl@02040000 { + compatible = "fsl,imx6-vpu"; + reg = <0x02040000 0x3c000>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_EDGE_RISING>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + power-domains = <&gpc 1>; }; aipstz@0207c000 { /* AIPSTZ1 */ @@ -484,6 +569,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x34 28 0x10 17>; status = "disabled"; }; @@ -494,6 +580,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x34 29 0x10 18>; status = "disabled"; }; @@ -634,20 +721,21 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -662,6 +750,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2000000>; anatop-max-voltage = <2750000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { @@ -679,6 +768,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -696,6 +786,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -713,6 +804,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -729,6 +821,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -737,9 +830,27 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + usbphy_nop2: usbphy_nop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -756,7 +867,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; @@ -793,7 +904,8 @@ <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; + <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_IPG>; #power-domain-cells = <1>; }; @@ -862,13 +974,23 @@ }; dcic1: dcic@020e4000 { + compatible = "fsl,imx6q-dcic"; reg = <0x020e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; dcic2: dcic@020e8000 { + compatible = "fsl,imx6q-dcic"; reg = <0x020e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; sdma: sdma@020ec000 { @@ -892,11 +1014,11 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; + ranges = <0 0x2100000 0x40000>; + interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, <&clks IMX6QDL_CLK_CAAM_ACLK>, <&clks IMX6QDL_CLK_CAAM_IPG>, @@ -930,6 +1052,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -957,6 +1080,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -970,6 +1096,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop2>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -984,20 +1113,28 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + <&gpc 0 118 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; + stop-mode = <&gpr 0x34 27>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb@0218c000 { + mlb: mlb@0218c000 { + compatible = "fsl,imx6q-mlb150"; reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MLB>, + <&clks IMX6QDL_CLK_PLL8_MLB>; + clock-names = "mlb", "pll8_mlb"; + iram = <&ocram>; + status = "disabled"; }; usdhc1: usdhc@02190000 { @@ -1082,6 +1219,11 @@ reg = <0x021ac000 0x4000>; }; + mmdc0-1@021b0000 { /* MMDC0-1 */ + compatible = "fsl,imx6q-mmdc-combine"; + reg = <0x021b0000 0x8000>; + }; + mmdc0: mmdc@021b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; @@ -1120,13 +1262,23 @@ status = "disabled"; }; - mipi_csi: mipi@021dc000 { + mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */ + compatible = "fsl,imx6q-mipi-csi2"; reg = <0x021dc000 0x4000>; + interrupts = <0 100 0x04>, <0 101 0x04>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_EIM_SEL>, + <&clks IMX6QDL_CLK_VIDEO_27M>; + /* Note: clks 138 is hsi_tx, however, the dphy_c + * hsi_tx and pll_refclk use the same clk gate. + * In current clk driver, open/close clk gate do + * use hsi_tx for a temporary debug purpose. + */ + clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; + status = "disabled"; }; - mipi_dsi: mipi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; + mipi@021e0000 { /* MIPI-DSI */ reg = <0x021e0000 0x4000>; status = "disabled"; @@ -1153,8 +1305,11 @@ }; vdoa@021e4000 { + compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@021e8000 { @@ -1214,10 +1369,17 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", + "540m", "video_pll"; resets = <&src 2>; + bypass_reset = <0>; ipu1_csi0: port@0 { reg = <0>; diff --git a/arch/arm/boot/dts/imx6qp-mtp.dts b/arch/arm/boot/dts/imx6qp-mtp.dts new file mode 100644 index 00000000000000..9424947a7cfbe2 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-mtp.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qp.dtsi" +#include "imx6qdl-mtp.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus MTP Board"; + compatible = "fsl,imx6qp-mtp", "fsl,imx6q"; + + memory: memory { + reg = <0x10000000 0x40000000>; + }; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts index a39b8603658189..23c8c65034c71e 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts @@ -48,12 +48,79 @@ / { model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; + + memory: memory { + reg = <0x10000000 0xeffffc00>; + }; +}; + +&fb_lvds { + prefetch; +}; + +&fb_lvds2 { + prefetch; +}; + +&fb_lcd { + prefetch; +}; + +&fb_hdmi { + prefetch; +}; + +&ov5640 { + ipu_id = <1>; }; -&pcie { - status = "disabled"; +&pinctrl_i2c3_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; }; &sata { status = "okay"; }; + +&v4l2_cap_2 { + ipu_id = <1>; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts new file mode 100644 index 00000000000000..f411c31097445e --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2016 Boundary Devices + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qp.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus Nitrogen6 som2 Board"; + compatible = "fsl,imx6qp-nitrogen6_som2", "fsl,imx6q"; + + memory: memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&fb_lvds { + prefetch; +}; + +&fb_lvds2 { + prefetch; +}; + +&fb_lcd { + prefetch; +}; + +&fb_hdmi { + prefetch; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + ipu_id = <1>; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts b/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts new file mode 100644 index 00000000000000..8846739a55585f --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts b/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts new file mode 100644 index 00000000000000..b57607b0c22280 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts b/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000000..b91ebad611169e --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + compatible = "fsl,imx6qp-gpmi-nand"; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index 5ce3840d83d3f5..59778f046ccef1 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -50,6 +50,40 @@ compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&fec { + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; +}; + &i2c2 { max7322: gpio@68 { compatible = "maxim,max7322"; @@ -59,33 +93,47 @@ }; }; -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; +&pcie { + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; }; -&pcie { - status = "disabled"; +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +®_sd3_vmmc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_sd3_vmmc>; }; &vgen3_reg { diff --git a/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts b/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts new file mode 100644 index 00000000000000..38d39cab570c1e --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts b/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts new file mode 100644 index 00000000000000..e19ff136c226af --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6qp-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd-ldo-pcie-cert.dts b/arch/arm/boot/dts/imx6qp-sabresd-ldo-pcie-cert.dts new file mode 100644 index 00000000000000..da6b11773680be --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-ldo-pcie-cert.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd-ldo.dts" + +&fec { + status = "disabled"; +}; + +&pcie { + ext_osc = <1>; +}; + +&sata { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts b/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts new file mode 100644 index 00000000000000..946fa2cf96bfa5 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index b23458062f5e66..9b7df2154badd1 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,8 +50,8 @@ compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; }; -&cpu0 { - arm-supply = <&sw2_reg>; +®_arm { + vin-supply = <&sw2_reg>; }; &iomuxc { @@ -88,6 +88,112 @@ }; }; +&iomuxc { + imx6qdl-sabresd { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ov564x { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&ov564x_mipi { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + &pcie { - status = "disabled"; + pcie-bus-supply = <&vgen3_reg>; /* 1.8v pwr up pcie ext osc on revb */ + reset-gpios = <&gpio7 12 0>; + status = "okay"; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&sata { + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 886dbf2eca49b8..225e59b508df73 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -43,6 +43,15 @@ #include "imx6q.dtsi" / { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + soc { ocram2: sram@00940000 { compatible = "mmio-sram"; @@ -56,17 +65,102 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + pcie: pcie@0x01000000 { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_PLL6_BYPASS>, + <&clks IMX6QDL_PLL6_BYPASS_SRC>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>; + clock-names = "pcie_phy", "pcie_ext", "pcie_ext_src", "pcie_bus", "pcie"; + status = "disabled"; + }; + + aips-bus@02100000 { /* AIPS2 */ + pre1: pre@021c8000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021c8000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE0>; + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram2>; + status = "disabled"; + }; + + pre2: pre@021c9000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021c9000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE1>; + interrupts = <0 97 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram2>; + status = "disabled"; + }; + + pre3: pre@021ca000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021ca000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE2>; + interrupts = <0 98 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram3>; + status = "disabled"; + }; + + pre4: pre@021cb000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021cb000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE3>; + interrupts = <0 99 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram3>; + status = "disabled"; + }; + + prg1: prg@021cc000 { + compatible = "fsl,imx6q-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_AXI>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; + }; + + prg2: prg@021cd000 { + compatible = "fsl,imx6q-prg"; + reg = <0x021cd000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG1_AXI>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; + }; + }; + ipu1: ipu@02400000 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; clocks = <&clks IMX6QDL_CLK_IPU1>, <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG0_APB>; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PLL3_PFD1_540M>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; clock-names = "bus", "di0", "di1", "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; + "ldb_di0", "ldb_di1", "prg", + "540m", "video_pll"; }; ipu2: ipu@02800000 { @@ -74,16 +168,18 @@ clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG1_APB>; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>, <&clks IMX6QDL_CLK_PLL3_PFD1_540M>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; clock-names = "bus", "di0", "di1", "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; - }; - - pcie: pcie@0x01000000 { - compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + "ldb_di0", "ldb_di1", "prg", + "540m", "video_pll"; }; }; }; + +&ldb { + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-btwifi.dts b/arch/arm/boot/dts/imx6sl-evk-btwifi.dts new file mode 100644 index 00000000000000..4eac83e12cf239 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-btwifi.dts @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD1 + * slot using Murata i.MX InterConnect Ver 1.0 Adapter AND wiring in control + * signals with SD Card Extender on SD3 slot. + * Bluetooth UART connect via SD1 EMMC/MMC Plus pinout. + * WL_REG_ON/BT_REG_ON/WL_HOST_WAKE are connected from SD Card Extender on SD3 + * slot. + */ +#include "imx6sl-evk.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio5 16 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + gpios = <&gpio5 20 0>; /* WL_HOST_WAKE */ + wlreg_on-supply = <&wlreg_on>; + }; +}; + +&iomuxc { + imx6sl-evk-murata-v1_sdext { + /* Only MUX SD1_DAT0..3 lines so UART4 can be MUXed on higher data lines. */ + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x13069 /* WL_HOST_WAKE */ + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x13069 /* WL_REG_ON */ + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + >; + }; + }; +}; +/* Murata: declare UART4 interface for Bluetooth. */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + bus-width = <1>; + no-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-csi.dts b/arch/arm/boot/dts/imx6sl-evk-csi.dts new file mode 100644 index 00000000000000..56d824b60e419d --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-csi.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&csi { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&epdc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-ldo.dts b/arch/arm/boot/dts/imx6sl-evk-ldo.dts new file mode 100644 index 00000000000000..a230e217222cb3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-ldo.dts @@ -0,0 +1,27 @@ + +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk-uart.dts b/arch/arm/boot/dts/imx6sl-evk-uart.dts new file mode 100644 index 00000000000000..6179842731a7f5 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk-uart.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index be118820e9f7f2..be64521b3fa495 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -16,6 +16,19 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + memory { reg = <0x80000000 0x40000000>; }; @@ -39,6 +52,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -96,7 +114,7 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -107,6 +125,23 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 19 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sl-evk-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 19 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; }; }; @@ -116,6 +151,29 @@ status = "okay"; }; +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_pu { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 11 0>; @@ -132,6 +190,15 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; @@ -140,6 +207,10 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -245,6 +316,89 @@ }; }; }; + + elan@10 { + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + gpio_elan_cs = <&gpio2 9 0>; + gpio_elan_rst = <&gpio4 4 0>; + gpio_intr = <&gpio2 10 0>; + status = "okay"; + }; + + mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + }; &i2c2 { @@ -265,6 +419,45 @@ PLLVDD-supply = <&vgen3_reg>; SPKVDD1-supply = <®_aud4v>; SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + }; + }; }; }; @@ -283,6 +476,17 @@ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000 + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000 + MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 >; }; @@ -304,6 +508,39 @@ >; }; + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000 + MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000 + MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000 + MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000 + MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000 + MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000 + MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000 + MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000 + MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000 + MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000 + MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000 + MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000 + MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000 + MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000 + MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000 + MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000 + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000 + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000 + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000 + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000 + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000 + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000 + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000 + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000 + MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000 + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000 + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000 + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 @@ -346,6 +583,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1 + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -357,7 +601,7 @@ >; }; - pinctrl_lcd: lcdgrp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 @@ -383,6 +627,11 @@ MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 @@ -402,6 +651,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 @@ -409,6 +664,24 @@ >; }; + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4dte_1: uart4dtegrp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -525,9 +798,34 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; }; }; +&pxp { + status = "okay"; +}; + &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; @@ -546,13 +844,14 @@ &lcdif { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; lcd-supply = <®_lcd_3v3>; display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <32>; + display0: display@0 { + bits-per-pixel = <16>; bus-width = <24>; display-timings { @@ -586,7 +885,21 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>, + <&clks IMX6SL_CLK_SPDIF0_PODF>; + assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>; + assigned-clock-rates = <0>, <227368421>; + status = "okay"; +}; + &ssi2 { + fsl,mode = "i2s-slave"; + assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>, + <&clks IMX6SL_CLK_SSI2>; + assigned-clock-rates = <0>, <24000000>; status = "okay"; }; @@ -601,6 +914,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -611,6 +927,14 @@ status = "okay"; }; +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -619,6 +943,8 @@ bus-width = <8>; cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -629,6 +955,8 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -638,5 +966,7 @@ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 02378db3f5fce2..a742d7400b0e9d 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -8,6 +8,7 @@ */ #include +#include #include "skeleton.dtsi" #include "imx6sl-pinfunc.h" #include @@ -20,6 +21,10 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -37,7 +42,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -55,17 +60,37 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -92,6 +117,10 @@ }; }; + reg_vbus_wakeup: usb_vbus_wakeup { + compatible = "fsl,imx6-dummy-ldo2p5"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -99,9 +128,42 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@00900000 { + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; @@ -164,6 +226,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI1>, <&clks IMX6SL_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -176,6 +240,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI2>, <&clks IMX6SL_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -188,6 +254,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI3>, <&clks IMX6SL_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -200,6 +268,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI4>, <&clks IMX6SL_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -251,8 +321,8 @@ clocks = <&clks IMX6SL_CLK_SSI1_IPG>, <&clks IMX6SL_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, + <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -267,8 +337,8 @@ clocks = <&clks IMX6SL_CLK_SSI2_IPG>, <&clks IMX6SL_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, + <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -283,8 +353,8 @@ clocks = <&clks IMX6SL_CLK_SSI3_IPG>, <&clks IMX6SL_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, + <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -520,20 +590,21 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -548,6 +619,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { @@ -565,6 +637,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -572,7 +645,8 @@ regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-always-on; + regulator-enable-ramp-delay = <150>; + regulator-boot-on; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; @@ -582,6 +656,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -599,6 +674,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -615,6 +691,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -623,9 +700,16 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -642,7 +726,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; @@ -673,8 +757,12 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; + clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>; + clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi", + "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi"; #power-domain-cells = <1>; }; @@ -690,8 +778,14 @@ }; csi: csi@020e4000 { + compatible = "fsl,imx6sl-csi"; reg = <0x020e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; }; spdc: spdc@020e8000 { @@ -707,18 +801,26 @@ <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + iram = <&ocram>; /* imx6sl reuses imx6q sdma firmware */ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; pxp: pxp@020f0000 { + compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { + compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@020f8000 { @@ -738,6 +840,10 @@ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, <0 100 IRQ_TYPE_LEVEL_HIGH>, <0 101 IRQ_TYPE_LEVEL_HIGH>; + /* DCP clock always on */ + clocks = <&clks IMX6SL_CLK_DUMMY>; + clock-names = "dcp"; + status = "okay"; }; }; @@ -758,6 +864,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -784,6 +891,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -792,6 +902,7 @@ compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SL_CLK_USBOH3>; + vbus-wakeup-supply = <®_vbus_wakeup>; }; fec: ethernet@02188000 { @@ -887,9 +998,11 @@ reg = <0x021b0000 0x4000>; }; - rngb: rngb@021b4000 { + rng: rng@021b4000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@021b8000 { @@ -908,6 +1021,24 @@ reg = <0x021d8000 0x4000>; status = "disabled"; }; + + gpu: gpu@02200000 { + compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu"; + reg = <0x02200000 0x4000>, <0x02204000 0x4000>, + <0x80000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_2d", "iobase_vg", + "phys_baseaddr", "contiguous_mem"; + interrupts = , ; + interrupt-names = "irq_2d", "irq_vg"; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu2d_clk"; + resets = <&src 3>, <&src 3>; + reset-names = "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6sll-evk-btwifi.dts b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts new file mode 100644 index 00000000000000..db30b1f7deb3d6 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into Slot + * SD1 and using Murata i.MX InterConnect Ver 2.0 Adapter. Bluetooth UART & + * control signals are connected via ribbon cable (J4 connector). + */ + +#include "imx6sll-evk.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio3 24 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + gpios = <&gpio3 26 0>; /* WL_HOST_WAKE */ + }; +}; + +&iomuxc { + imx6sll-evk-murata-v2 { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + + MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x17059 /* WL_REG_ON */ + MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x17059 /* WL_HOST_WAKE */ + >; + }; + }; +}; + +&lcdif { + status = "disabled"; +}; + +®_sd3_vmmc { + regulator-always-on; +}; + +&uart5 { + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; /* add hook for SD card detect mechanism for BCMDHD driver */ +}; diff --git a/arch/arm/boot/dts/imx6sll-evk-reva.dts b/arch/arm/boot/dts/imx6sll-evk-reva.dts new file mode 100644 index 00000000000000..8562facad609d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk-reva.dts @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-evk.dts" + +&usdhc2 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +}; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts new file mode 100644 index 00000000000000..6fb3207bda4ac5 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -0,0 +1,815 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 0>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6sll-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + /* + * Must set the LVE of pad SD2_RESET, otherwise current + * leakage through eMMC chip will pull high the VCCQ to + * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch. + */ + MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */ + MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */ + MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17061 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13061 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170a1 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130a1 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170e9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + lcd-supply = <®_lcd>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + no-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6sll-lpddr2-arm2.dts b/arch/arm/boot/dts/imx6sll-lpddr2-arm2.dts new file mode 100644 index 00000000000000..d5fd505177cbe3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-lpddr2-arm2.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2-csi.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-csi.dts new file mode 100644 index 00000000000000..59a0c0223610d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-csi.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" + +&csi { + status = "okay"; +}; + +&epdc { + status = "disabled"; +}; + +&ov5640 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2-ecspi.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-ecspi.dts new file mode 100644 index 00000000000000..d1facfc26f7c9c --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-ecspi.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" + +&ecspi1 { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2-spdif.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-spdif.dts new file mode 100644 index 00000000000000..4079e84b154961 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2-spdif.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" + +/ { + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sl-evk-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SLL_CLK_SPDIF_SEL>, + <&clks IMX6SLL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <98304000>; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts new file mode 100644 index 00000000000000..894f75e0479499 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts @@ -0,0 +1,834 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL LPDDR3 ARM2 Board"; + compatible = "fsl,imx6sll-lpddr3-arm2", "fsl,imx6sll"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + users { + label = "debug"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 0>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC_VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6SLL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>; + + imx6sll-lpddr3-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + + pinctrl_hog_sd2_reset: hoggrp-1 { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x17059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x100b1 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + lcd-supply = <®_lcd>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + no-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + flash: m25p80@0 { + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h new file mode 100755 index 00000000000000..5a3700b0a0fff3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -0,0 +1,882 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi new file mode 100644 index 00000000000000..b2036fea497098 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "imx6sll-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1225000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1225000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + fsl,low-power-run; + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>, + <&clks IMX6SLL_CLK_PLL1>, + <&clks IMX6SLL_PLL1_BYPASS>, + <&clks IMX6SLL_PLL1_BYPASS_SRC>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>, + <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>, + <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>, + <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>, + <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>, + <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>, + <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { + compatible = "mmio-sram"; + reg = <0x00905000 0x1B000>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + + ecspi1: ecspi@02008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@02018000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts =; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@02024000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi@02028000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi2@0202c000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi@02030000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@02034000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = ; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6sll-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_3M>; + clock-names = "ipg", "osc_per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x4000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + }; + + tempmon: tempmon { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: src@020d8000 { + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@020e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_SDMA>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pxp: pxp@020f0000 { + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x020f0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + epdc: epdc@020f4000 { + compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc"; + reg = <0x020f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + status = "disabled"; + }; + + lcdif: lcdif@020f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: dcp@020fc000 { + compatible = "fsl,imx6sl-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: usdhc@02198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + romcp@021ac000 { + compatible = "fsl,imx6sll-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + rngb: rngb@021b4000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6sll-csu"; + reg = <0x021c0000 0x4000>; + interrupts = ; + status = "disabled"; + }; + + snvs_gpr: snvs-gpr@0x021c4000 { + compatible = "fsl, imx6sll-snvs-gpr"; + reg = <0x021c4000 0x10000>; + }; + + iomuxc_snvs: iomuxc-snvs@021c8000 { + compatible = "fsl,imx6sll-iomuxc-snvs"; + reg = <0x021c80000 0x10000>; + }; + + audmux: audmux@021d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts =; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-14x14-arm2.dts b/arch/arm/boot/dts/imx6sx-14x14-arm2.dts new file mode 100644 index 00000000000000..3a04d28b0e80ed --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-14x14-arm2.dts @@ -0,0 +1,1333 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX 14x14 ARM2 Board"; + compatible = "fsl,imx6sx-14x14-lpddr2-arm2", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + off-on-delay = <20000>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-id = <1>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-id = <0>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4_3: usdhc4grp-3 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts new file mode 100644 index 00000000000000..2de2cc3d8d1dde --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-arm2.dts" + +&esai { + /* pin conflict with sai */ + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&i2c2 { + ov5640: ov5640@3c { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts new file mode 100644 index 00000000000000..a50f335adb806e --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-arm2.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts new file mode 100644 index 00000000000000..b7aeaca70e4a17 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-arm2.dts" + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts new file mode 100644 index 00000000000000..44607424d5b8c4 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts @@ -0,0 +1,1259 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX 19x19 ARM2 Board"; + compatible = "fsl,imx6sx-19x19-arm2", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&cs42888>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_1>; + status = "okay"; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_1>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 26 1>; + rst-gpios = <&gpio3 25 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_2>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + cs42888: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>; + clock-names = "mclk"; + VA-supply = <®_3p3v>; + VD-supply = <®_3p3v>; + VLS-supply = <®_3p3v>; + VLC-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_1>; + status = "disabled"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + bus-width = <4>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x50000000 0x08000000>; + status = "disabled"; /* pin conflict with qspi, nand and lcd1 */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6_scm.dts b/arch/arm/boot/dts/imx6sx-nitrogen6_scm.dts new file mode 100644 index 00000000000000..1c941c149c97e5 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-nitrogen6_scm.dts @@ -0,0 +1,990 @@ +/* + * Copyright (C) 2014 Boundary Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_nitrogen6_scm: iomuxc-nitrogen6_scmgrp { + status = "okay"; + }; +}; + +&iomuxc_nitrogen6_scm { + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio2 18 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x1b0b0 + >; + }; + + pinctrl_csi_ov5642: csi-ov5642grp { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + +#define GP_OV5642_RESET <&gpio7 4 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 +#define GP_OV5642_POWER_DOWN <&gpio7 5 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0xb0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio2 16 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x130b1 + MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x130b1 + MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x130b1 + MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x130b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < +#define GP_GPIOKEY_POWER <&gpio4 27 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 + >; + }; + + pinctrl_gpio_poweroff: gpio-poweroffgrp { + fsl,pins = < + /* gpio - output */ +#define GP_POWER_OFF <&gpio4 26 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x130b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Test points */ +#define GP_TP16 <&gpio7 6 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 +#define GP_TP17 <&gpio7 7 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 +#define GP_TP18 <&gpio6 14 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x1b0b0 +#define GP_TP19 <&gpio6 15 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x000b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x4001b8b1 +#define GP_I2C2_SDA <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x4001b8b1 + >; + }; + + /* J4 */ + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 +#define GP_I2C3_J4_RESET <&gpio1 8 GPIO_ACTIVE_LOW> + MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x1b0b0 +#define GPIRQ_I2C3_J4 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J4 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio2 8 GPIO_ACTIVE_HIGH> + MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x4001b8b1 +#define GP_I2C3_SDA <&gpio2 9 GPIO_ACTIVE_HIGH> + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1: i2c4_1grp { + fsl,pins = < +#define GP_I2C4_SCL <&gpio7 2 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x4001b8b1 +#define GP_I2C4_SDA <&gpio7 3 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x4001b8b1 + >; + }; + + pinctrl_i2c4a_max77818: i2c4a_max77818grp { + fsl,pins = < +#define GPIRQ_MAX77818_INTB <&gpio7 0 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x1b0b0 +#define GPIRQ_MAX77818_WCINOKB <&gpio7 8 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x1b0b0 +#define GPIRQ_MAX77818_INOKB <&gpio7 9 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x1b0b0 + >; + }; + + pinctrl_lcdif1: lcdif1grp { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_reg_5v: reg-5vgrp { + fsl,pins = < +#define GP_5V_BST_EN <&gpio6 12 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x1b0b0 + >; + }; + + pinctrl_reg_wlan: reg-wlangrp { + fsl,pins = < +#define GP_WLAN_EN <&gpio2 13 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x1b0b0 + MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_NAND_DATA07__UART3_TX 0x1b0b1 + MX6SX_PAD_NAND_DATA06__UART3_RX 0x1b0b1 + MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1 + MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x1b0b1 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { + fsl,pins = < +#define GP_USB_OTG1_PWR <&gpio4 24 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x030b0 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x1b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2-vbusgrp { + fsl,pins = < +#define GP_USB_OTG2_PWR <&gpio4 25 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x030b0 + >; + }; + + /* microSD */ + pinctrl_usdhc1_50mhz: usdhc1-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17071 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17071 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17071 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17071 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17071 +#define GP_USDHC1_CD <&gpio4 30 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x1b0b0 + >; + }; + + /* Wifi */ + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10071 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17071 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17071 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17071 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17071 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_wlan:wlangrp { + fsl,pins = < +#define GPIRQ_WL1271 <&gpio2 14 IRQ_TYPE_LEVEL_HIGH> + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x130b0 +#define GP_WLAN_CLK_REQ <&gpio2 12 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x130b0 +#define GP_WLAN_QOW <&gpio2 17 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x130b0 +#define GP_BT_HOST_WAKE <&gpio1 13 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x130b0 + >; + }; +}; + +/ { + model = "Freescale i.MX6 SoloX Nitrogen6_scm Board"; + compatible = "fsl,imx6sx-nitrogen6_scm", "fsl,imx6sx"; + + aliases { + fb_lcd = &lcdif1; + lcd = &display0; + mmc0 = &usdhc1; + t_lcd = &t_lcd; + }; + + backlight_lcd { + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + display = <&lcdif1>; + pwms = <&pwm1 0 5000000>; + }; + + bt_rfkill { + reset-gpios = GP_BT_RFKILL_RESET; + compatible = "net,rfkill-gpio"; + name = "bt_rfkill"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + type = <2>; /* bluetooth */ + status = "okay"; + }; + + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + clock-frequency = <24576000>; + compatible = "fixed-clock"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = GP_GPIOKEY_POWER; + linux,code = ; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + poweroff: poweroff { + compatible = "gpio-poweroff"; + gpios = GP_POWER_OFF; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_poweroff>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "1P8V"; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "2P5V"; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3P3V"; + }; + + reg_5v: regulator@3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_5V_BST_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_5v>; + reg = <3>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "5V"; + vin-supply = <&swbst_reg>; + }; + + reg_usbotg1_vbus: regulator@4 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_USB_OTG1_PWR; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + reg = <4>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb_otg1_vbus"; + vin-supply = <®_5v>; + }; + + reg_usbotg2_vbus: regulator@5 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_USB_OTG2_PWR; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + reg = <5>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb_otg2_vbus"; + vin-supply = <®_5v>; + }; + + reg_wlan_en: regulator@6 { + clocks = <&clks IMX6SX_CLK_CKO>; + clock-names = "slow"; + compatible = "regulator-fixed"; + enable-active-high; + gpio = GP_WLAN_EN; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan>; + reg = <6>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlan-en"; + startup-delay-us = <70000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_CKO>, + <&clks IMX6SX_CLK_CKO1_SEL>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_CLK_CKO1>, + <&clks IMX6SX_CLK_CKIL>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5642_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: is25wp032@0 { + compatible = "issi,is25wp032"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J4; + wakeup-gpios = GP_I2C3_J4; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J4; + wakeup-gpios = GP_I2C3_J4; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_1>; + scl-gpios = GP_I2C4_SCL; + sda-gpios = GP_I2C4_SDA; + status = "okay"; + + max77818@66 { + compatible = "maxim,max77823"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4a_max77818>; + reg = <0x66>; + interrupts-extended = GPIRQ_MAX77818_INTB; + max77823,irq-gpio = GPIRQ_MAX77818_INTB; + max77823,wakeup = <1>; + max77823_battery: battery { + compatible = "samsung,sec-battery"; + }; + + max77823_charger: charger { + compatible = "samsung,max77823-charger"; + }; + + max77823_fuelgauge: fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + }; + }; + + ov5642: ov5642@3c { + compatible = "ovti,ov5642subdev"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_ov5642>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen3_reg>; /* measured 1.7v */ + AVDD-supply = <&vgen5_reg>; /* measured 2.7v */ + DVDD-supply = <&vgen2_reg>; /* measured 1.5v, resistor not stuffed, optional */ + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5642_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif1>; + lcd-supply = <®_3p3v>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + t_lcd: t_lcd_default { + /* 720p values may be changed in bootscript */ + clock-frequency = <74160000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + + +&max77823_battery { + status = "okay"; + battery,vendor = "SDI SDI"; + battery,charger_name = "max77823-charger"; + battery,fuelgauge_name = "max77823-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,bat_irq_attr = <0x3>; + + battery,chip_vendor = "QCOM"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + + battery,polling_time = <10 30 30 30 3600>; + + battery,adc_check_count = <6>; + + /* SEC_BATTERY_CABLE_CHECK_PSY | SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE */ + battery,cable_check_type = <6>; + battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_check; + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + + battery,battery_check_type = <6>; /* SEC_BATTERY_CHECK_INT */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + + battery,thermal_source = <0>; /* SEC_BATTERY_THERMAL_SOURCE_FG */ + + battery,temp_check_type = <2>; /* _BATTERY_TEMP_CHECK_TEMP */ + battery,temp_check_count = <1>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + + /* SEC_BATTERY_FULL_CONDITION_SOC | + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL | + SEC_BATTERY_FULL_CONDITION_VCELL */ + battery,full_condition_type = <13>; + battery,full_condition_soc = <97>; + battery,full_condition_vcell = <4350000>; + + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <98>; + battery,recharge_condition_vcell = <4350000>; + + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; +}; + +&max77823_charger { + battery,charger_name = "max77823-charger"; + battery,chg_gpio_en = <0>; + battery,chg_polarity_en = <0>; + battery,chg_gpio_status = <0>; + battery,chg_polarity_status = <0>; + battery,chg_float_voltage = <4400>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + + battery,input_current_limit = <1800 460 460 4000 460 900 1000 460 460 1000 760 1800 1800 460 1300 300 700 1300 1800 300 80 1800 460 1000 1633 1000 1000 4000>; + battery,fast_charging_current = <2100 0 460 2100 460 1200 1000 460 0 1200 900 2100 2100 0 1300 300 700 1300 1800 300 80 2100 0 1000 2800 1000 1000 1000>; + battery,full_check_current_1st = <200 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 200 200 200 200 200 0 200 200 200 200 200>; + battery,full_check_current_2nd = <2400 0 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 0 2400 2400 2400 2400 2400 2400 2400 2400 0 2400 2400 2400 2400 2400>; + usbotg-supply = <®_usbotg1_vbus>; +}; + +&max77823_fuelgauge { + compatible = "samsung,max77823-fuelgauge"; + fuelgauge,capacity_max = <990>; + fuelgauge,capacity_max_margin = <50>; + fuelgauge,capacity_min = <0>; + fuelgauge,capacity_calculation_type = <0x17>; + fuelgauge,fuel_alert_soc = <1>; + empty_detect_voltage = <2900>; + empty_recovery_voltage = <3100>; + /* fuelgauge,repeated_fuelalert; */ + temp-calibration = <0 (-6763) 9858>; + /* if temp-calibration defined, temp-calibration-data not used */ + temp-calibration-data = <250 0x7cde + 255 0x7c50 + 260 0x7aa0 + 265 0x792e + 270 0x788e + 275 0x7714 + 280 0x761a + 285 0x7536 + 290 0x73ca + 295 0x7326 + 300 0x726c + 305 0x71cc + 310 0x71b2 + 315 0x70a4 + 320 0x6f6a + 325 0x6eae + 330 0x6a2e + 335 0x6800 + 340 0x673c + 345 0x665a + 350 0x65b4 + 355 0x6478 + 360 0x6318 + 365 0x6270 + 370 0x614e + 375 0x5f56 + 380 0x5ed2 + 385 0x5d9e + 390 0x5b38 + 395 0x5ae0 + 400 0x59ce + 405 0x57b2 + 410 0x55f2 + 415 0x53c2 + 420 0x505a>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; + vbus-supply = <®_usbotg1_vbus>; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + status = "okay"; + vbus-supply = <®_usbotg2_vbus>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC1_CD; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* Silex */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_wlan_en>; + cap-power-off-card; + cap-sdio-irq; + vqmmc-1-8-v; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wlan>; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx-m4.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx-m4.dts new file mode 100644 index 00000000000000..9a98c1ff31edeb --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx-m4.dts @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Boundary Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-nitrogen6sx.dts" + +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&rpmsg{ + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 9b817f3501a66a..e4126636d25fc6 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -43,667 +43,1037 @@ #include "imx6sx.dtsi" -/ { - model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; - compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; - aliases { - fb_lcd = &lcdif1; - t_lcd = &t_lcd; + iomuxc_nitrogen6sx: iomuxc-nitrogen6sxgrp { + status = "okay"; }; +}; - memory { - reg = <0x80000000 0x40000000>; +&iomuxc_nitrogen6sx { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 + MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 + MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 + >; }; - backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3p3v>; + pinctrl_bt_rfkill: bt-rfkillgrp { + fsl,pins = < +#define GP_BT_RFKILL_RESET <&gpio2 17 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x1b0b0 + >; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; + pinctrl_csi_ov5642: csi-ov5642grp { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + +#define GP_OV5642_RESET <&gpio4 2 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x30b0 +#define GP_OV5642_POWER_DOWN <&gpio4 0 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0xb0b0 + >; }; - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio2 16 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 + >; }; - reg_can1_3v3: regulator-can1-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 +#define GP_RGMII1_PHY_RESET <&gpio2 7 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 +#define GPIRQ_RGMII1_PHY <&gpio2 4 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 + MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 + >; }; - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 +#define GP_RGMII2_PHY_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 +#define GPIRQ_RGMII2_PHY <&gpio2 8 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 + >; }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 +#define GP_CAN1_STANDBY <&gpio4 27 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 + >; }; - reg_wlan: regulator-wlan { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan>; - compatible = "regulator-fixed"; - clocks = <&clks IMX6SX_CLK_CKO>; - clock-names = "slow"; - regulator-name = "wlan-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6sx-nitrogen6sx-sgtl5000"; - cpu-dai = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 +#define GP_CAN2_STANDBY <&gpio4 24 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 + >; }; -}; -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 + MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 + MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 + MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 +#define GP_WIFI_PASS <&gpio4 6 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x030b1 +#define GP_WIFI_FAIL <&gpio4 4 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x030b1 +#define GP_WIFI_TEST <&gpio4 7 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x0b0b1 + /* Test points */ + MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 + >; + }; -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + >; + }; - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio1 0 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x4001b8b1 +#define GP_I2C1_SDA <&gpio1 1 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x4001b8b1 + >; + }; - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - read-only; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + >; + }; - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - read-only; - }; + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x4001b8b1 +#define GP_I2C2_SDA <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x4001b8b1 + >; + }; - partition@c2000 { - label = "Kernel"; - reg = <0xc2000 0x11e000>; - }; + pinctrl_i2c2_tfp410: i2c2-tfp410grp { + fsl,pins = < +#define GPIRQ_I2C2_TFP410 <&gpio4 3 IRQ_TYPE_EDGE_FALLING> + MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 +#define GP_I2C2_TFP410_I2C_SEL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 + >; + }; - partition@1e0000 { - label = "M4"; - reg = <0x1e0000 0x20000>; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J18 <&gpio4 25 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J18 <&gpio4 25 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 + >; }; -}; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio2 14 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x4001b8b1 +#define GP_I2C3_SDA <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x4001b8b1 + >; + }; - mdio { - #address-cells = <1>; - #size-cells = <0>; + pinctrl_lcdif1: lcdif1grp { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; - ethphy1: ethernet-phy@4 { - reg = <4>; - }; + pinctrl_lvds: lvdsgrp { + fsl,pins = < +#define GP_LVDS_ENABLE <&gpio4 21 GPIO_ACTIVE_HIGH> + MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0xb0b0 + >; + }; - ethphy2: ethernet-phy@5 { - reg = <5>; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 10 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x30b0 +#define GP_PCIE_DISABLE <&gpio4 11 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x30b0 +#define GP_PCIE_WAKE <&gpio4 9 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x30b0 + >; }; -}; -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; -}; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 + >; + }; -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; + pinctrl_reg_wifi_1p8v: reg-wifi-1p8vgrp { + fsl,pins = < +#define GP_REG_WIFI_1P8V_EN <&gpio4 5 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x030b0 + >; + }; -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; + pinctrl_reg_wifi_3p3v: reg-wifi-3p3vgrp { + fsl,pins = < +#define GP_REG_WIFI_3P3V_EN <&gpio6 1 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x030b0 + >; + }; -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6SX_CLK_CKO2>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - VDDD-supply = <®_1p8v>; - assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, - <&clks IMX6SX_CLK_CKO2>; - assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; - assigned-clock-rates = <0>, <24000000>; + pinctrl_reg_wlan: reg-wlangrp { + fsl,pins = < +#define GP_REG_WLAN_EN <&gpio7 6 GPIO_ACTIVE_HIGH> + MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 + MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 + >; }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif1>; - lcd-supply = <®_3p3v>; - display = <&display0>; - status = "okay"; - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - clock-frequency = <74160000>; - hactive = <1280>; - vactive = <720>; - hback-porch = <220>; - hfront-porch = <110>; - vback-porch = <20>; - vfront-porch = <5>; - hsync-len = <40>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 +#define GP_SGTL5000_HP_DETECT <&gpio2 0 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 +#define GP_SGTL5000_MIC_DETECT <&gpio2 1 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 +#define GP_SGTL5000_MUTE <&gpio4 22 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 + >; }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - disable-over-current; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - vmmc-supply = <®_wlan>; - cap-power-off-card; - cap-sdio-irq; - status = "okay"; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; }; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ref-clock-frequency = <38400000>; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + >; }; -}; -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + >; + }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 + >; + }; - pinctrl_audmux: audmuxgrp { + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { fsl,pins = < - MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 - MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 - MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 - MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 +#define GP_USB_OTG1_PWR <&gpio1 9 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 >; }; - pinctrl_ecspi1: ecspi1grp { + pinctrl_usbotg2: usbotg2grp { fsl,pins = < - MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 +#define GP_USB_HUB_RESET <&gpio4 26 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 >; }; - pinctrl_enet1: enet1grp { + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 - MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 - MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10071 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x1f071 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x1f071 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x1f071 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x1f071 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x1f071 +#define GP_USDHC2_CD <&gpio2 12 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 >; }; - pinctrl_enet2: enet2grp { + pinctrl_usdhc3_50mhz: usdhc3-50mhzgrp { fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 - MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 - MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 +#define GPIRQ_WL1271 <&gpio7 7 IRQ_TYPE_LEVEL_HIGH> + MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 >; }; - pinctrl_flexcan1: flexcan1grp { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 >; }; - pinctrl_flexcan2: flexcan2grp { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 >; }; - pinctrl_hog: hoggrp { + pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { fsl,pins = < - MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 - MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 - MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 - MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 - MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 - MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 - MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 - MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 - /* Test points */ - MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 >; }; - - pinctrl_i2c1: i2c1grp { + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { fsl,pins = < - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 >; }; - pinctrl_i2c2: i2c2grp { + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { fsl,pins = < - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 >; }; +}; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - >; +/ { + model = "Freescale i.MX6 SoloX Nitrogen6sx Board"; + compatible = "fsl,imx6sx-nitrogen6sx", "fsl,imx6sx"; + + aliases { + fb_lcd = &lcdif1; + fb_lvds = &lcdif2; + lcd = &display0; + lvds = &display1; + ldb = &ldb; + mmc0 = &usdhc2; + mmc1 = &usdhc4; + mmc2 = &usdhc3; + t_lcd = &t_lcd; + t_lvds = &t_lvds; }; - pinctrl_lcdif1: lcdif1grp { - fsl,pins = < - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - >; + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif2"; + power-supply = <®_3p3v>; }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 - MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 - MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 - >; + bt_rfkill { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + compatible = "net,rfkill-gpio"; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = GP_BT_RFKILL_RESET; + status = "okay"; }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 - >; + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; }; - pinctrl_reg_wlan: reg-wlangrp { - fsl,pins = < - MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 - MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 - >; + memory { + reg = <0x80000000 0x40000000>; }; - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 - MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 - >; + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator@3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG1_PWR; + enable-active-high; + }; + + reg_wifi_3p3v: regulator@4 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi_3p3v>; + reg = <4>; + regulator-name = "wifi_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + gpio = GP_REG_WIFI_3P3V_EN; + enable-active-high; + }; + + reg_wifi_1p8v: regulator@5 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi_1p8v>; + reg = <5>; + regulator-name = "wifi_1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <400000>; + gpio = GP_REG_WIFI_1P8V_EN; + enable-active-high; + vin-supply = <®_wifi_3p3v>; + }; + + reg_wlan_en: regulator@6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan>; + compatible = "regulator-fixed"; + clocks = <&clks IMX6SX_CLK_CKO>; + clock-names = "slow"; + reg = <6>; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + gpio = GP_REG_WLAN_EN; + enable-active-high; + vin-supply = <®_wifi_1p8v>; + }; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 - >; + sound_sgtl5000 { + compatible = "fsl,imx6sx-nitrogen6sx-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT", + "Line Out Jack", "LINE_OUT"; + mux-int-port = <1>; + mux-ext-port = <5>; + line-out-mute-gpios = GP_SGTL5000_MUTE; }; +}; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 - >; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_CKO>, + <&clks IMX6SX_CLK_CKO1_SEL>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_CLK_CKO1>, + <&clks IMX6SX_CLK_CKIL>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5642_ep>; + }; }; +}; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 - >; +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; }; +}; - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 - >; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; }; +}; - pinctrl_usbotg1_vbus: usbotg1-vbusgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 - >; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_RGMII1_PHY_RESET; +#endif + phy-handle = <ðphy1>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = GPIRQ_RGMII1_PHY; + }; + + ethphy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts-extended = GPIRQ_RGMII2_PHY; + }; }; +}; - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 - >; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_RGMII2_PHY_RESET; +#endif + phy-handle = <ðphy2>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + trx-stby-gpio = GP_CAN1_STANDBY; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + trx-stby-gpio = GP_CAN2_STANDBY; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6SX_CLK_CKO2>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, + <&clks IMX6SX_CLK_CKO2>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; + assigned-clock-rates = <0>, <24000000>; }; +}; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 - >; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + tfp410@38 { + compatible = "tfp410"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_tfp410>; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C2_TFP410; + i2c_sel-gpios = GP_I2C2_TFP410_I2C_SEL; + display_id = "mxs-lcdif"; }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 - >; + /* pcie i2c */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupts-extended = GPIRQ_I2C3_J18; + wakeup-gpios = GP_I2C3_J18; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts"; + reg = <0x38>; + interrupts-extended = GPIRQ_I2C3_J18; + wakeup-gpios = GP_I2C3_J18; }; - pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 - >; + ov5642: ov5642@3c { + compatible = "ovti,ov5642subdev"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_ov5642>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = GP_OV5642_POWER_DOWN; + rst-gpios = GP_OV5642_RESET; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5642_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; }; +}; - pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif1>; + lcd-supply = <®_3p3v>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + t_lcd: t_lcd_default { + /* 720p values may be changed in bootscript */ + clock-frequency = <74160000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; +}; - pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; +&lcdif2 { + lcd-supply = <®_3p3v>; + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + assigned-clocks = <&clks IMX6SX_CLK_LCDIF2_SEL>; + assigned-clock-parents = <&clks IMX6SX_CLK_LDB_DI0>; + assigned-clock-rates = <0>; + + display1: display1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + + display-timings { + t_lvds: t_lvds_default { + /* values may be changed in bootscript */ + clock-frequency = <73404600>; + hactive = <1280>; + vactive = <800>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <3>; + vfront-porch = <80>; + hsync-len = <10>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + disable-over-current; + reset-gpios = GP_USB_HUB_RESET; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC2_CD; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* TiWi or broadcom or Silex */ +&usdhc3 { + bus-width = <4>; + cap-power-off-card; + cap-sdio-irq; +#if 0 + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; +#endif + keep-power-in-suspend; +#if 1 + max-clock = <20000000>; +#endif + non-removable; +#if 0 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; +#else + pinctrl-names = "default"; +#endif + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <®_wlan_en>; + vqmmc-1-8-v; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; + reg = <2>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index 42c4c800feea19..5a989206f3336b 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -70,6 +70,7 @@ #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 @@ -79,6 +80,7 @@ #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -88,6 +90,7 @@ #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 #define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -97,6 +100,7 @@ #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -204,6 +208,7 @@ #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -214,6 +219,7 @@ #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -223,6 +229,7 @@ #define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 #define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -255,6 +262,7 @@ #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -357,6 +365,7 @@ #define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 #define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -367,6 +376,7 @@ #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -376,6 +386,7 @@ #define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -394,6 +405,7 @@ #define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -419,6 +431,7 @@ #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -438,6 +451,7 @@ #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -820,6 +834,7 @@ #define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -830,6 +845,7 @@ #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -972,6 +988,7 @@ #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -980,6 +997,7 @@ #define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1251,6 +1269,7 @@ #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1260,6 +1279,7 @@ #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1330,6 +1350,7 @@ #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1369,6 +1390,7 @@ #define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1414,6 +1436,7 @@ #define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 #define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1424,6 +1447,7 @@ #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1515,6 +1539,7 @@ #define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1525,6 +1550,7 @@ #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 diff --git a/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts b/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts new file mode 100644 index 00000000000000..b0822dc3ea90f1 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sabreauto.dts" + +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>, + <0xc0000000 0x40000000>; + }; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0x1E000>; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&qspi1 { + status = "disabled"; +}; + +&qspi_m4 { + reg = <0x021e0000 0x4000>; + status = "okay"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 240a2864d044fe..9b01adf3c687a8 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -14,15 +14,83 @@ model = "Freescale i.MX6 SoloX Sabre Auto Board"; compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + }; + + max7310_reset: max7310-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + memory { reg = <0x80000000 0x80000000>; }; + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + reg_audio: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio1: vio1_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio2: vio2_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vd: f3v3_tnr { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_va: f5v_tnr { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + vcc_sd3: regulator@0 { compatible = "regulator-fixed"; reg = <0>; @@ -34,15 +102,507 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_can_wake: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "can-wake"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_wake>; + }; + + reg_can_stby: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_vref_3v3: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; }; }; +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_2>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; + status = "okay"; + + codec: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&codec_osc 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <22 2>; + wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; + }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <&si4763_va>; + vd-supply = <&si4763_vd>; + vio1-supply = <&si4763_vio1>; + vio2-supply = <&si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_2>; + status = "okay"; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7310_reset>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7310_reset>; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio3>; + interrupts = <24 8>; + interrupt-route = <1>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <6 1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <23 2>; + }; + +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_2>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&max7310_b 3 0>; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -68,8 +628,169 @@ status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &iomuxc { imx6x-sabreauto { + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x80000000 + >; + }; + + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 @@ -77,6 +798,49 @@ >; }; + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 @@ -89,8 +853,8 @@ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x17059 /* CD */ + MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x17059 /* WP */ >; }; @@ -126,14 +890,13 @@ pinctrl_usdhc4: usdhc4grp { fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x17071 /* CD */ >; }; @@ -142,5 +905,48 @@ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; }; }; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts b/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts new file mode 100644 index 00000000000000..698e49ef7734d3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD3 + * slot using Murata i.MX InterConnect Ver 1.0 Adapter AND SD Card Extender on + * SD2 slot. Bluetooth UART connects via SD3 EMMC/MMC Plus pinout. + * WL_REG_ON/BT_REG_ON/WL_HOST_WAKE connect via SD Card Extender. + */ + +#include "imx6sx-sdb.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio6 10 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + /* WL_HOST_WAKE: SD2_DAT1 (gpio6 9) */ + gpios = <&gpio6 9 0>; + wlreg_on-supply = <&wlreg_on>; + }; +}; + +&iomuxc { + imx6sx-sdb-murata-v1_sdext { + pinctrl_bt: btgrp { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_SD3_DATA4__UART3_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA5__UART3_TX 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 + >; + }; + + /* change MUXing on SD2 slot for control signals. */ + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + >; + }; + + /* Murata change SD3 to 4-bit SDIO only; use upper 4-bits for UART. */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + /* Murata Module control signals */ + MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x13069 /* WL_HOST_WAKE */ + MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x13069 /* WL_REG_ON */ + >; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 + &pinctrl_bt>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + bus-width = <1>; +}; + +&vcc_sd3 { + regulator-always-on; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; /* pull in card detect mechanism for BCMDHD driver */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-emmc.dts b/arch/arm/boot/dts/imx6sx-sdb-emmc.dts new file mode 100644 index 00000000000000..6a2a07b0e2ba77 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-emmc.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/* + * The eMMC chip on imx6sx sdb board is DNP by default. + * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4 + * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + /* + * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA + * signals after rework + */ + cd-gpios = <>; + wp-gpios = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts b/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts new file mode 100644 index 00000000000000..280540453aebf7 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/ { + sii902x_reset: sii902x-reset { + status = "okay"; + }; +}; + +&csi1 { + status = "disabled"; +}; + +&lcdif1 { + status = "okay"; +}; + +&i2c1 { + sii902x@39 { + status = "okay"; + }; +}; + +&ov5640 { + status = "disabled"; +}; + +&crypto { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-ldo.dts b/arch/arm/boot/dts/imx6sx-sdb-ldo.dts new file mode 100644 index 00000000000000..3a8c194ba2d6c4 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-ldo.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-m4.dts b/arch/arm/boot/dts/imx6sx-sdb-m4.dts new file mode 100644 index 00000000000000..61a1db351dd69e --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-m4.dts @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&qspi2 { + status = "disabled"; +}; + +&qspi_m4 { + status = "okay"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts new file mode 100644 index 00000000000000..e5ff9fb99013a7 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This feature is supported by the MX6SX-SD-EXP1 board + * + */ + +#include "imx6sx-sdb.dts" +/ { + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + asrc-controller = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&usdhc2 { + /* pin conflict with mqs*/ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <>; + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts b/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts new file mode 100644 index 00000000000000..86719991523650 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb-reva.dts" + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 71005478cdf06f..b5cabf97fcaf79 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -10,6 +10,48 @@ / { model = "Freescale i.MX6 SoloX SDB RevA Board"; + + regulators { + /* Transceiver EN/STBY is active high on RevA board */ + reg_can_en: regulator@9 { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator@10 { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; }; &i2c1 { @@ -124,13 +166,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; + ddrsmp=<0>; flash0: s25fl128s@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; + spi-max-frequency = <29000000>; }; flash1: s25fl128s@1 { @@ -138,6 +181,6 @@ #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; + spi-max-frequency = <29000000>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/imx6sx-sdb-sai.dts index 0155450d680e22..f4f699fbdfe1a2 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-sai.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-sai.dts @@ -43,7 +43,7 @@ / { sound { - audio-cpu = <&sai1>; + cpu-dai = <&sai1>; }; }; @@ -53,6 +53,8 @@ }; &sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index d71da30c9cff23..7797130c98b535 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -10,101 +10,41 @@ / { model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + regulators { + /* Transceiver EN/STBY is active low on RevB board */ + reg_can_stby: regulator@10 { + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + }; +}; - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; }; &qspi2 { @@ -112,6 +52,9 @@ pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; +#ifndef SPANSIONFLASH + ddrsmp=<0>; + flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; @@ -127,4 +70,13 @@ spi-max-frequency = <29000000>; reg = <1>; }; +#endif +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 9d70cfd40aff66..eaea8ff94cb692 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -24,11 +24,19 @@ reg = <0x80000000 0x40000000>; }; - backlight { + backlight1 { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; }; gpio-keys { @@ -49,6 +57,18 @@ }; }; + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -63,6 +83,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; enable-active-high; }; @@ -104,6 +125,7 @@ regulator-name = "lcd-3v3"; gpio = <&gpio3 27 0>; enable-active-high; + status = "disabled"; }; reg_peri_3v3: regulator@5 { @@ -129,12 +151,49 @@ regulator-max-microvolt = <3300000>; gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; }; + + reg_vref_3v3: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_pcie: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 0>; + regulator-always-on; + enable-active-high; + }; + + reg_can_en: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -145,15 +204,48 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + codec-master; + hp-det-gpios = <&gpio1 17 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; }; }; +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; + +&gpc { + fsl,ldo-bypass = <1>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -176,6 +268,37 @@ }; }; +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; @@ -184,11 +307,196 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio6>; + interrupts = <2 8>; + interrupt-route = <2>; + }; }; &i2c4 { @@ -209,6 +517,7 @@ PLLVDD-supply = <&vgen4_reg>; SPKVDD1-supply = <®_psu_5v>; SPKVDD2-supply = <®_psu_5v>; + amic-mono; }; }; @@ -217,9 +526,9 @@ pinctrl-0 = <&pinctrl_lcd>; lcd-supply = <®_lcd_3v3>; display = <&display0>; - status = "okay"; + status = "disabled"; - display0: display0 { + display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; @@ -244,12 +553,62 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 0>; + status = "okay"; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; +&ldb { + status = "okay"; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -260,6 +619,12 @@ status = "disabled"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -275,12 +640,18 @@ pinctrl-0 = <&pinctrl_uart5>; uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -329,7 +700,25 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 @@ -340,11 +729,38 @@ >; }; + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 @@ -383,6 +799,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 @@ -397,6 +827,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 @@ -445,6 +882,25 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + pinctrl_peri_3v3: peri3v3grp { fsl,pins = < MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 @@ -457,6 +913,12 @@ >; }; + pinctrl_pwm4: pwm4grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi2: qspi2grp { fsl,pins = < MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 @@ -474,6 +936,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 @@ -506,6 +974,15 @@ >; }; + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 @@ -537,16 +1014,16 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ >; @@ -595,6 +1072,51 @@ >; }; + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 @@ -602,3 +1124,14 @@ }; }; }; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-ys-m4.dts b/arch/arm/boot/dts/imx6sx-ys-m4.dts new file mode 100644 index 00000000000000..f82a4ffab924ca --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-ys-m4.dts @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 Boundary Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-ys.dts" + +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&rpmsg{ + status = "okay"; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sx-ys.dts b/arch/arm/boot/dts/imx6sx-ys.dts new file mode 100644 index 00000000000000..6a139610609661 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-ys.dts @@ -0,0 +1,634 @@ +/* + * Copyright (C) 2017 Boundary Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + iomuxc_ys: iomuxc-ysgrp { + status = "okay"; + }; +}; + +&iomuxc_ys { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 +#define GP_ECSPI1_NOR_CS <&gpio2 16 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x100b1 + MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x100b1 + MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x100b1 + MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x100b1 +#define GP_ECSPI2_CS <&gpio6 14 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x100b1 + MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x100b1 + MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x100b1 +#define GP_ECSPI3_CS <&gpio6 21 GPIO_ACTIVE_LOW> + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x0b0b1 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x100b1 + MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x100b1 + MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x100b1 +#define GP_ECSPI5_CS <&gpio4 28 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x0b0b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30b1 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30b1 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30b1 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x30b1 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0xb0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0xb0b1 +#define GP_RGMII1_PHY_RESET <&gpio2 7 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 +#define GPIRQ_RGMII1_PHY <&gpio2 4 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 + MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0xb0b1 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x30b1 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x30b1 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x30b1 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0xb0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0xb0b1 +#define GP_RGMII2_PHY_RESET <&gpio2 6 GPIO_ACTIVE_LOW> + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 +#define GPIRQ_RGMII2_PHY <&gpio2 8 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x30b0 + MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x30b0 + MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0xb0b0 + MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x30b0 + MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x30b0 + MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x30b0 + MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x30b0 + MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x30b0 + MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x30b0 + MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x30b0 + /* Test points */ + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x30b0 + MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x30b0 + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x30b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio1 0 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x4001b8b1 +#define GP_I2C1_SDA <&gpio1 1 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x4001b8b1 + >; + }; + + pinctrl_i2c1_rv4162: i2c1-rv4162grp { + fsl,pins = < +#define GPIRQ_RTC_RV4162 <&gpio4 30 IRQ_TYPE_LEVEL_LOW> + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio1 2 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x4001b8b1 +#define GP_I2C2_SDA <&gpio1 3 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio2 14 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x4001b8b1 +#define GP_I2C3_SDA <&gpio2 19 GPIO_ACTIVE_HIGH> + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < +#define GP_PCIE_RESET <&gpio4 7 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x30b0 +#define GP_PCIE_DISABLE <&gpio4 8 GPIO_ACTIVE_HIGH> + MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x30b0 +#define GP_PCIE_WAKE <&gpio4 9 GPIO_ACTIVE_LOW> + MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x30b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_NAND_DATA07__UART3_TX 0x1b0b1 + MX6SX_PAD_NAND_DATA06__UART3_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 +#define GP_UART5_TX_EN <&gpio1 12 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0b0b0 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { + fsl,pins = < +#define GP_USB_OTG1_PWR <&gpio1 9 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < +#define GP_USB_HUB_RESET <&gpio4 26 GPIO_ACTIVE_LOW> + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2-vbusgrp { + fsl,pins = < +#define GP_USB_HOST_PWR_EN <&gpio1 11 GPIO_ACTIVE_HIGH> + MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0xb0b0 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10071 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x1f071 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x1f071 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x1f071 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x1f071 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x1f071 +#define GP_USDHC2_CD <&gpio2 12 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 + >; + }; + + pinctrl_usdhc3_50mhz: usdhc3-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x410071 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x417071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x417071 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x417071 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x417071 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x417071 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x417071 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x417071 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x417071 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x417071 +#define GP_EMMC_RESET <&gpio2 17 GPIO_ACTIVE_LOW> + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x000b0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x4100b9 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x4170b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x4170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x4170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x4170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x4170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x4170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x4170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x4170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x4170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x4100f9 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x4170f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x4170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x4170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x4170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x4170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x4170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x4170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x4170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x4170f9 + >; + }; +}; + +/ { + model = "Freescale i.MX6 SoloX YS Board"; + compatible = "fsl,imx6sx-ys", "fsl,imx6sx"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; + + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator@3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_OTG1_PWR; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_USB_HOST_PWR_EN; + enable-active-high; + }; + }; + + reserved-memory { + linux,cma { + size = <0x2000000>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "U-Boot Env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Logo"; + reg = <0xC2000 0x11e000>; + }; + partition@1e0000 { + label = "M4 FW"; + reg = <0x1e0000 0x8000>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI2_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI3_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi5 { + fsl,spi-num-chipselects = <1>; + cs-gpios = GP_ECSPI5_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_RGMII1_PHY_RESET; +#endif + phy-handle = <ðphy1>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = GPIRQ_RGMII1_PHY; + }; + + ethphy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts-extended = GPIRQ_RGMII2_PHY; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_RGMII2_PHY_RESET; +#endif + phy-handle = <ðphy2>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; + + rv4162@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_rv4162>; + reg = <0x68>; + interrupts-extended = GPIRQ_RTC_RV4162; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = GP_PCIE_RESET; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + control-gpios = GP_UART5_TX_EN; +#define M_TX_EN 1 + rs485_txen_mask = ; + rs485_txen_levels = ; + uart-has-rs485-half-duplex; + rs485-mode = <1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + disable-over-current; + reset-gpios = GP_USB_HUB_RESET; + status = "okay"; + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + bus-width = <4>; + cd-gpios = GP_USDHC2_CD; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_50mhz>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-1-8-v; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 1a473e83efbfd8..0d1c808f74dba3 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -47,6 +47,8 @@ spi4 = &ecspi5; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + lcdif0 = &lcdif1; + lcdif1 = &lcdif2; }; cpus { @@ -77,14 +79,32 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -138,13 +158,53 @@ interrupt-parent = <&gpc>; ranges; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>, + <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>, + <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>, + <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>, + <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>, + <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>, + <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>, + <&clks IMX6SX_CLK_M4>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "pll1_sys", "periph2", + "ahb", "ocram", "pll1_sw", "periph2_pre", + "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", + "m4"; + fsl,max_ddr_freq = <400000000>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = ; }; - ocram: sram@00900000 { + ocrams: sram@008f8000 { + compatible = "fsl,lpm-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram: sram@00901000 { compatible = "mmio-sram"; + reg = <0x00901000 0x1F000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; @@ -159,16 +219,6 @@ arm,data-latency = <4 2 3>; }; - gpu: gpu@01800000 { - compatible = "vivante,gc"; - reg = <0x01800000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>; - clock-names = "bus", "core", "shader"; - }; - dma_apbh: dma-apbh@01804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; @@ -182,6 +232,37 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpu: gpu@01800000 { + compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu"; + reg = <0x01800000 0x4000>, <0x80000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>, + <&clks 0>; + clock-names = "gpu3d_axi_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>; + reset-names = "gpu3d"; + power-domains = <&gpc 1>; + }; + gpmi: gpmi-nand@01806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; @@ -247,6 +328,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI1>, <&clks IMX6SX_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -259,6 +342,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI2>, <&clks IMX6SX_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -271,6 +356,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI3>, <&clks IMX6SX_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -283,11 +370,14 @@ clocks = <&clks IMX6SX_CLK_ECSPI4>, <&clks IMX6SX_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -299,6 +389,7 @@ }; esai: esai@02024000 { + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -308,6 +399,9 @@ <&clks IMX6SX_CLK_SPBA>; clock-names = "core", "mem", "extal", "fsys", "spba"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -319,7 +413,7 @@ clocks = <&clks IMX6SX_CLK_SSI1_IPG>, <&clks IMX6SX_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -333,7 +427,7 @@ clocks = <&clks IMX6SX_CLK_SSI2_IPG>, <&clks IMX6SX_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -347,25 +441,34 @@ clocks = <&clks IMX6SX_CLK_SSI3_IPG>, <&clks IMX6SX_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; status = "okay"; }; }; @@ -417,6 +520,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -427,6 +531,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -523,6 +628,12 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + kpp: kpp@020b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; @@ -576,20 +687,21 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -604,6 +716,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { @@ -623,9 +736,9 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie { + reg_pcie_phy: regulator-vddpcie-phy@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; + regulator-name = "vddpcie-phy"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; anatop-reg-offset = <0x140>; @@ -670,6 +783,7 @@ reg = <0x020c9000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -678,9 +792,21 @@ reg = <0x020ca000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SX_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -696,7 +822,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; @@ -734,6 +860,16 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; + clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>, + <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix", + "lcdif_axi", "lcdif2_pix", "csi_mclk"; + pcie-phy-supply = <®_pcie_phy>; + #power-domain-cells = <1>; }; iomuxc: iomuxc@020e0000 { @@ -747,8 +883,40 @@ reg = <0x020e4000 0x4000>; }; + ldb: ldb@020e0014 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + clocks = <&clks IMX6SX_CLK_LDB_DI0>, + <&clks IMX6SX_CLK_LCDIF1_SEL>, + <&clks IMX6SX_CLK_LCDIF2_SEL>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_7>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>, + <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_PFD0>, + <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL3_PFD3>; + clock-names = "ldb_di0", + "di0_sel", + "di1_sel", + "ldb_di0_div_3_5", + "ldb_di0_div_7", + "ldb_di0_div_sel", + "", + "choice1", + "choice2", + "choice3"; + lvds-channel@0 { + reg = <0>; + status = "disabled"; + }; + }; + sdma: sdma@020ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; + compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SDMA>, @@ -769,12 +937,10 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; + reg = <0x2100000 0x40000>; + ranges = <0 0x2100000 0x40000>; clocks = <&clks IMX6SX_CLK_CAAM_MEM>, <&clks IMX6SX_CLK_CAAM_ACLK>, <&clks IMX6SX_CLK_CAAM_IPG>, @@ -828,6 +994,7 @@ clocks = <&clks IMX6SX_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; fsl,anatop = <&anatop>; dr_mode = "host"; ahb-burst-config = <0x0>; @@ -857,15 +1024,20 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; mlb: mlb@0218c000 { + compatible = "fsl,imx6sx-mlb50"; reg = <0x0218c000 0x4000>; interrupts = , , ; clocks = <&clks IMX6SX_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; status = "disabled"; }; @@ -964,6 +1136,10 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 4>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -975,21 +1151,28 @@ }; ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sx-ocotp", "syscon"; + compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; }; + romcp@021ac000 { + compatible = "fsl,imx6sx-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + sai1: sai@021d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI1>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; + dma-source = <&gpr 0 15 0 16>; status = "disabled"; }; @@ -1004,9 +1187,10 @@ reg = <0x021dc000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI2>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; status = "disabled"; @@ -1038,8 +1222,15 @@ status = "disabled"; }; + qspi_m4: qspi-m4 { + compatible = "fsl,imx6sx-qspi-m4-restore"; + reg = <0x021e4000 0x4000>; + status = "disabled"; + }; + uart2: serial@021e8000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1051,7 +1242,8 @@ }; uart3: serial@021ec000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1063,7 +1255,8 @@ }; uart4: serial@021f0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1075,7 +1268,8 @@ }; uart5: serial@021f4000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1095,6 +1289,11 @@ clocks = <&clks IMX6SX_CLK_I2C4>; status = "disabled"; }; + + qosc: qosc@021fc000 { + compatible = "fsl,imx6sx-qosc"; + reg = <0x021fc000 0x4000>; + }; }; aips3: aips-bus@02200000 { @@ -1112,31 +1311,59 @@ ranges; csi1: csi@02214000 { + compatible = "fsl,imx6s-csi"; reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&gpc 2>; + status = "disabled"; + }; + + dcic1: dcic@0220c000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x0220c000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC1>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; + }; + + dcic2: dcic@02210000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x02210000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC2>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; status = "disabled"; }; pxp: pxp@02218000 { + compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x02218000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pxp-axi", "disp-axi"; + power-domains = <&gpc 2>; status = "disabled"; }; csi2: csi@0221c000 { + compatible = "fsl,imx6s-csi"; reg = <0x0221c000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&gpc 2>; status = "disabled"; }; @@ -1148,6 +1375,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&gpc 2>; status = "disabled"; }; @@ -1159,15 +1387,19 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&gpc 2>; status = "disabled"; }; vadc: vadc@02228000 { + compatible = "fsl,imx6sx-vadc"; reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&gpc 2>; + gpr = <&gpr>; status = "disabled"; }; }; @@ -1177,6 +1409,7 @@ reg = <0x02280000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -1188,6 +1421,7 @@ reg = <0x02284000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -1214,8 +1448,28 @@ status = "disabled"; }; + sema4: sema4@02290000 { /* sema4 */ + compatible = "fsl,imx6sx-sema4"; + reg = <0x02290000 0x4000>; + interrupts = <0 116 0x04>; + status = "okay"; + }; + + mu: mu@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + status = "disabled"; + }; + uart6: serial@022a0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x022a0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1269,24 +1523,30 @@ pcie: pcie@0x08000000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + pcie-phy-supply = <®_pcie_phy>; + power-domains = <&gpc 2>; + fsl,max-link-speed = <2>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-btwifi-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-btwifi-ldo.dts new file mode 100644 index 00000000000000..a31c4d69bd0e4a --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-btwifi-ldo.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +#include "imx6sxscm-evb-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-lcdif1-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-lcdif1-ldo.dts new file mode 100644 index 00000000000000..03ddbe9e652562 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-lcdif1-ldo.dts @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +/ { + regulators { + reg_lcd_3v3: regulator@4 { + status = "okay"; + }; + }; + + sii902x_reset: sii902x-reset { + status = "okay"; + }; +}; + +&csi1 { + status = "disabled"; +}; + +&lcdif1 { + status = "okay"; +}; + +&i2c4 { + sii902x@39 { + status = "okay"; + }; +}; + +&ov5640 { + status = "disabled"; +}; + +&crypto { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-ldo.dts new file mode 100644 index 00000000000000..357b920983187a --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-ldo.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-evb-ldo.dts" diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-m4-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-m4-ldo.dts new file mode 100644 index 00000000000000..af0e8be603ed17 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-m4-ldo.dts @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&qspi2 { + status = "disabled"; +}; + +&qspi_m4 { + status = "okay"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-mqs-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-mqs-ldo.dts new file mode 100644 index 00000000000000..08aac2c6636f0b --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-mqs-ldo.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +/ { + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + asrc-controller = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&usdhc2 { + /* pin conflict with mqs*/ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <>; + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-1gb-evb-sai-ldo.dts b/arch/arm/boot/dts/imx6sxscm-1gb-evb-sai-ldo.dts new file mode 100644 index 00000000000000..d95d2e6f45c35e --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-1gb-evb-sai-ldo.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +/ { + sound { + cpu-dai = <&sai1>; + }; +}; + +&audmux { + /* pin conflict with sai */ + status = "disabled"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-512mb-evb-ldo.dts b/arch/arm/boot/dts/imx6sxscm-512mb-evb-ldo.dts new file mode 100644 index 00000000000000..f34b358021673e --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-512mb-evb-ldo.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-ldo.dts" +#include "imx6sxscm-512mb.dtsi" diff --git a/arch/arm/boot/dts/imx6sxscm-512mb-evb-m4-ldo.dts b/arch/arm/boot/dts/imx6sxscm-512mb-evb-m4-ldo.dts new file mode 100644 index 00000000000000..2408594457471e --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-512mb-evb-m4-ldo.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-1gb-evb-m4-ldo.dts" +/{ + memory { + linux,usable-memory = <0x80000000 0x1ff00000> ; + }; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0x9FFF0000 0x10000>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-512mb.dtsi b/arch/arm/boot/dts/imx6sxscm-512mb.dtsi new file mode 100644 index 00000000000000..023c997640bc43 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-512mb.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + memory { + reg = <0x80000000 0x20000000>; + }; + +}; diff --git a/arch/arm/boot/dts/imx6sxscm-emmc.dtsi b/arch/arm/boot/dts/imx6sxscm-emmc.dtsi new file mode 100644 index 00000000000000..7e616f40ce515a --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-emmc.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&spdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-epop-evb-ldo.dts b/arch/arm/boot/dts/imx6sxscm-epop-evb-ldo.dts new file mode 100644 index 00000000000000..62bc1ff83776ee --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-epop-evb-ldo.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx6sxscm-512mb-evb-ldo.dts" +#include "imx6sxscm-emmc.dtsi" diff --git a/arch/arm/boot/dts/imx6sxscm-epop-evb-m4-ldo.dts b/arch/arm/boot/dts/imx6sxscm-epop-evb-m4-ldo.dts new file mode 100644 index 00000000000000..ab6060283f9298 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-epop-evb-m4-ldo.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx6sxscm-512mb-evb-m4-ldo.dts" +#include "imx6sxscm-emmc.dtsi" diff --git a/arch/arm/boot/dts/imx6sxscm-evb-btwifi.dtsi b/arch/arm/boot/dts/imx6sxscm-evb-btwifi.dtsi new file mode 100644 index 00000000000000..938aac4119e857 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-evb-btwifi.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 8 0>; + startup-delay-us = <100>; + enable-active-high; + }; + vcc_sd3: regulator@0 { + status = "disabled"; + }; + + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + gpios = <&gpio7 9 0>; /* WL_HOST_WAKE */ + }; +}; + +&iomuxc { + imx6sxscm-evb-murata-v2_rc { + pinctrl_bt: btgrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x13069 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__UART6_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW1__UART6_RX 0x1b0b1 + MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + >; + }; + + /* For Murata, SD to 4-bit SDIO; use upper 4-bits for UART */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17069 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10071 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17069 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17069 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17069 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17069 + /* Murata Module control signals */ + MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x13069 + MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x13069 + >; + }; + }; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6 + &pinctrl_bt>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + cd-post; + pm-ignore-notify; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-evb-ldo.dts b/arch/arm/boot/dts/imx6sxscm-evb-ldo.dts new file mode 100644 index 00000000000000..954057769c87ab --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-evb-ldo.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sxscm-evb.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; diff --git a/arch/arm/boot/dts/imx6sxscm-evb.dts b/arch/arm/boot/dts/imx6sxscm-evb.dts new file mode 100644 index 00000000000000..97651e7e6b6cf6 --- /dev/null +++ b/arch/arm/boot/dts/imx6sxscm-evb.dts @@ -0,0 +1,1156 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SXSCM EVB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart3; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_psu_5v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + status = "disabled"; + }; + + reg_peri_3v3: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet_3v3: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>, + <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + + reg_vref_3v3: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_pcie: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 0>; + regulator-always-on; + enable-active-high; + }; + + reg_can_en: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "fsl,imx6sxscm-evb-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <6>; + codec-master; + hp-det-gpios = <&gpio1 17 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_enet_3v3>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio4 26 0>; + fsl,magic-packet; + status = "okay"; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio4>; + interrupts = <17 8>; + interrupt-route = <2>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio4>; + interrupts = <22 1>; + shared-interrupt; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio4>; + interrupts = <22 1>; + shared-interrupt; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SX_CLK_AUDIO>; + DCVDD-supply = <&vgen4_reg>; + DBVDD-supply = <&vgen4_reg>; + AVDD-supply = <&vgen4_reg>; + CPVDD-supply = <&vgen4_reg>; + MICVDD-supply = <&vgen3_reg>; + PLLVDD-supply = <&vgen4_reg>; + SPKVDD1-supply = <®_psu_5v>; + SPKVDD2-supply = <®_psu_5v>; + amic-mono; + }; + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; + DVDD-supply = <&vgen2_reg>; + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + +#ifndef SPANSIONFLASH + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; +#endif +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "disabled"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + wifi-host; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <>; + wp-gpios = <>; + keep-power-in-suspend; + wakeup-source; + pm-ignore-notify; + vmmc-supply = <>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x17059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_canfd1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + + pinctrl_canfd2: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0xa0b1 + MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + + pinctrl_enet_3v3: enet3v3grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x80000000 + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x80000000 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + + pinctrl_peri_3v3: peri3v3grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 + >; + }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2: usbot2ggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 + >; + }; + + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + >; + }; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "disabled"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts new file mode 100644 index 00000000000000..2e35ed6d353ed8 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1_8bit>; + pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>; + bus-width = <8>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + tuning-step = <2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-flexcan2.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-flexcan2.dts new file mode 100644 index 00000000000000..827bc02d9935da --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-flexcan2.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +&uart2{ + status = "disabled"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts new file mode 100644 index 00000000000000..2e6b54495d05ff --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/* + * solve pin conflict with NAND + * + * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also + * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog + * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB, + * WP, DQS pin + * + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; +}; + +&qspi{ + status = "disabled"; +}; + +&gpmi{ + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-mqs.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-mqs.dts new file mode 100644 index 00000000000000..3427bc33063879 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-mqs.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/ { + sound-mqs { + compatible = "fsl,imx6ul-ddr3-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + asrc-controller = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&sai1 { + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-spdif.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-spdif.dts new file mode 100644 index 00000000000000..7191f0572e3b4c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-spdif.dts @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/ { + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog &pinctrl_hog1>; +}; + +&usdhc1 { + no-1-8-v; + vmmc-supply = <>; +}; + +&usdhc2 { + no-1-8-v; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6UL_CLK_SPDIF_SEL>, + <&clks IMX6UL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <98304000>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-wm8958.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-wm8958.dts new file mode 100644 index 00000000000000..bdc5b903602aa5 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-wm8958.dts @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/ { + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_codec_5v: codec_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_aud_3v3: aud_3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + }; + + sound-wm8958 { + compatible = "fsl,imx6ul-ddr3-arm2-wm8958", + "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + hp-det-gpios = <&gpio5 0 1>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_3v3>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_codec_5v>; + SPKVDD2-supply = <®_codec_5v>; + + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts new file mode 100644 index 00000000000000..ee19df65737069 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts @@ -0,0 +1,774 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite DDR3 ARM2 Board"; + compatible = "fsl,imx6ul-14x14-ddr3-arm2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>; + + imx6ul-ddr3-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */ + >; + }; + + pinctrl_hog1: hoggrp1 { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */ + >; + }; + + pinctrl_hog_sd: hoggrp_sd { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..90e0045fa2e4ee --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts new file mode 100644 index 00000000000000..4613799a97c75a --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts new file mode 100644 index 00000000000000..f2bf26fff351a6 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +&sim2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts new file mode 100644 index 00000000000000..b56d34d9f8a4de --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts @@ -0,0 +1,20 @@ + +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000000..7cff0874697b68 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + imx6ul-evk-gpmi-rework { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-pf1550.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-pf1550.dts new file mode 100644 index 00000000000000..d319f2ea551d7d --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-pf1550.dts @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + +&cpu0 { + /* + * on i.MX6UL, no separated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the separated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1_reg>; + regulator-allow-bypass; +}; + +&gpc { + fsl,ldo-bypass = <1>; /* use ldo-bypass */ +}; + +&i2c1 { + pmic: pf1550@08 { + compatible = "fsl,pf1550"; + interrupt-parent = <&gpio5>; + interrupts = <4 8>; + reg = <0x08>; + pinctrl-0 = <&pinctrl_pf1550>; + + onkey { + compatible = "fsl,pf1550-onkey"; + linux,keycode = ; + wakeup; + }; + + charger { + compatible = "fsl,pf1550-charger"; + }; + + regulators { + compatible = "fsl,pf1550-regulator"; + + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&sai2 { + status = "disabled"; +}; + +&sound { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk-usb-certi.dts b/arch/arm/boot/dts/imx6ul-14x14-evk-usb-certi.dts new file mode 100644 index 00000000000000..8aaf248812e60a --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk-usb-certi.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for USB Certification at i.mx6ul 14x14 evk board */ + +#include "imx6ul-14x14-evk.dts" + +/ { + regulators { + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; /* hardware rework is needed */ + tpl-support; +}; + +&tsc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index e281d5087d4ad6..da2ae89b3f00cc 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -22,6 +22,19 @@ reg = <0x80000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -30,6 +43,11 @@ status = "okay"; }; + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -41,41 +59,90 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; enable-active-high; }; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = + sound: sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; }; }; }; @@ -88,6 +155,7 @@ &cpu0 { arm-supply = <®_arm>; soc-supply = <®_soc>; + dc-supply = <®_gpio_dvfs>; }; &i2c2 { @@ -101,6 +169,38 @@ compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; }; }; @@ -124,15 +224,59 @@ #size-cells = <0>; ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <2>; }; ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; &lcdif { pinctrl-names = "default"; @@ -141,7 +285,7 @@ display = <&display0>; status = "okay"; - display0: display { + display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; @@ -173,16 +317,22 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; + ddrsmp=<0>; flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a"; spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; reg = <0>; }; }; @@ -202,6 +352,22 @@ status = "okay"; }; +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control + * NCN8025:Vcc = ACTIVE_HIGH?5V:3V + * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V + */ + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + port = <1>; + sven_low_active; + status = "okay"; +}; + &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; @@ -221,11 +387,19 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "okay"; }; &usbotg1 { - dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -235,6 +409,14 @@ status = "okay"; }; +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -250,9 +432,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; + non-removable; status = "okay"; }; @@ -264,6 +444,13 @@ &iomuxc { pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; pinctrl_csi1: csi1grp { fsl,pins = < @@ -282,6 +469,12 @@ >; }; + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 @@ -307,7 +500,6 @@ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 >; }; @@ -401,6 +593,12 @@ >; }; + pinctrl_pf1550: pf1550 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 @@ -410,14 +608,23 @@ pinctrl_sim2: sim2grp { fsl,pins = < MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 - MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 - MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 - MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 - MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x11 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb810 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb810 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb811 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 >; }; + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 @@ -443,10 +650,25 @@ >; }; + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 @@ -482,7 +704,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 @@ -491,9 +713,65 @@ >; }; + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-lpddr2-arm2.dts b/arch/arm/boot/dts/imx6ul-14x14-lpddr2-arm2.dts new file mode 100644 index 00000000000000..94f5d86cb74826 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-lpddr2-arm2.dts @@ -0,0 +1,788 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14X14 LPDDR2 ARM2 Board"; + compatible = "fsl,imx6ul-14x14-lpddr2-arm2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "disabled"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + keep-power-in-suspend; + vmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; + + imx6ul-14x14-lpddr2-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_hog_nand: hoggrp_nand { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + >; + }; + + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 + MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 + MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 + MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2_8bit_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..8a8ece34d775d2 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts new file mode 100644 index 00000000000000..de89052d97fc5b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts new file mode 100644 index 00000000000000..21778070fb188a --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-csi.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" + + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +&sim2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts new file mode 100644 index 00000000000000..715efcb9512eaf --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk.dts b/arch/arm/boot/dts/imx6ul-9x9-evk.dts new file mode 100644 index 00000000000000..29896ea1830351 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-9x9-evk.dts @@ -0,0 +1,813 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2_1>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + port = <1>; + sven_low_active; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi b/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi new file mode 100644 index 00000000000000..cd7a5e6964e1a3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&bcmdhd_wlan_0 { + /* Need to define WL_HOST_WAKE for OOB IRQ: ENET2_RX_ER (gpio2_15) */ + /* Hardware modification is needed on imx6ul evk for using OOB. */ + gpios = <&gpio2 15 0>; /* WL_HOST_WAKE */ +}; + +&pinctrl_wifi { + fsl,pins = < + /* MUXing for WL_HOST_WAKE */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x13041 + >; +}; + +/* + * For WL_HOST_WAKE (OOB_IRQ) to function correctly, we must disable + * the secondary ethernet port (FEC2). Hardware re-work is to remove + * R1633 and populate R1704 with 0 Ohm resistor. + * Refer to Murata Hardware Reference Manual for more details. + */ +&fec2 { + status="disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi b/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi new file mode 100644 index 00000000000000..d4810bd30d5887 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into Slot + * SD1 and using Murata i.MX InterConnect Ver 2.0 Adapter. Bluetooth UART & + * control signals are connected via ribbon cable (J1701 connector). + */ + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio_spi 4 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio5 1 0>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + }; +}; + +&iomuxc { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x03029 + >; + }; +}; + +®_sd1_vmmc { + regulator-always-on; +}; + +&uart2 { + resets = <&modem_reset>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifi>; + no-1-8-v; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; /* add hook for SD card detect mechanism for BCMDHD driver */ +}; + +&gpio_spi { + /* Murata: modify default setting so that BT_nPWD/BT_REG_ON + * is low (0V) during kernel boot. + */ + registers-default = /bits/ 8 <0x47>; +}; diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h index 0034eeb84542ff..9538b0ed5c11c4 100644 --- a/arch/arm/boot/dts/imx6ul-pinfunc.h +++ b/arch/arm/boot/dts/imx6ul-pinfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -34,14 +34,14 @@ #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 #define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 #define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 @@ -63,12 +63,14 @@ #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__REF_CLK_32K 0x0054 0x02e0 0x0000 6 0 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 @@ -94,22 +96,24 @@ #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x0068 0x02f4 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 @@ -200,7 +204,7 @@ #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 @@ -232,7 +236,7 @@ #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 @@ -242,7 +246,7 @@ #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 @@ -251,7 +255,7 @@ #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 @@ -259,7 +263,7 @@ #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 @@ -267,7 +271,7 @@ #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 @@ -275,23 +279,23 @@ #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 @@ -299,59 +303,61 @@ #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__REF_CLK_32K 0x00cc 0x0358 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 @@ -360,7 +366,7 @@ #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 @@ -377,7 +383,7 @@ #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 @@ -400,6 +406,7 @@ #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 @@ -412,7 +419,7 @@ #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 @@ -431,7 +438,7 @@ #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 @@ -440,7 +447,7 @@ #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 @@ -464,7 +471,7 @@ #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 @@ -477,13 +484,15 @@ #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 @@ -491,6 +500,7 @@ #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 @@ -498,14 +508,16 @@ #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 @@ -514,6 +526,7 @@ #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 @@ -522,6 +535,7 @@ #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 @@ -530,6 +544,7 @@ #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 @@ -537,56 +552,64 @@ #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 @@ -594,7 +617,8 @@ #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 @@ -602,7 +626,8 @@ #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 @@ -610,7 +635,7 @@ #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 @@ -622,7 +647,7 @@ #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 @@ -631,12 +656,12 @@ #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 @@ -644,7 +669,7 @@ #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 @@ -652,7 +677,7 @@ #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 @@ -660,42 +685,42 @@ #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 #define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 #define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 #define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 #define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 @@ -726,7 +751,7 @@ #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 #define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 @@ -748,7 +773,7 @@ #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 @@ -783,7 +808,7 @@ #define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 #define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 @@ -791,11 +816,11 @@ #define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 #define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 @@ -878,10 +903,10 @@ #define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 #define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 @@ -913,7 +938,7 @@ #define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 #define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 @@ -924,7 +949,7 @@ #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 #define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c5c05fdccc783d..7db03c1037fc97 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -1,5 +1,6 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -58,12 +59,14 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 @@ -133,15 +136,43 @@ interrupt-parent = <&gpc>; ranges; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc"; + fsl,max_ddr_freq = <400000000>; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = ; status = "disabled"; }; - ocram: sram@00900000 { + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; }; dma_apbh: dma-apbh@01804000 { @@ -157,6 +188,21 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpmi: gpmi-nand@01806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -191,6 +237,28 @@ reg = <0x02000000 0x40000>; ranges; + spdif: spdif@02004000 { + compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 41 18 0>, + <&sdma 42 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, + <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_SPDIF>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + ecspi1: ecspi@02008000 { #address-cells = <1>; #size-cells = <0>; @@ -200,6 +268,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI1>, <&clks IMX6UL_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -212,6 +282,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI2>, <&clks IMX6UL_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -224,6 +296,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI3>, <&clks IMX6UL_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -236,23 +310,27 @@ clocks = <&clks IMX6UL_CLK_ECSPI4>, <&clks IMX6UL_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart7: serial@02018000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART7_IPG>, <&clks IMX6UL_CLK_UART7_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART1_IPG>, @@ -263,12 +341,14 @@ uart8: serial@02024000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART8_IPG>, <&clks IMX6UL_CLK_UART8_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -278,9 +358,10 @@ reg = <0x02028000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI1>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; dma-names = "rx", "tx"; @@ -293,9 +374,11 @@ reg = <0x0202c000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI2>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; dma-names = "rx", "tx"; @@ -308,14 +391,40 @@ reg = <0x02030000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; + + asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; }; tsc: tsc@02040000 { @@ -329,6 +438,13 @@ status = "disabled"; }; + bee: bee@02044000 { + compatible = "fsl,imx6ul-bee"; + reg = <0x02044000 0x4000>; + interrupts = ; + status = "disabled"; + }; + pwm1: pwm@02080000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -380,6 +496,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -390,6 +507,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -398,8 +516,8 @@ reg = <0x02098000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; + <&clks IMX6UL_CLK_GPT_3M>; + clock-names = "ipg", "osc_per"; }; gpio1: gpio@0209c000 { @@ -463,6 +581,12 @@ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; + snvslp: snvs@020b0000 { + compatible = "fsl,imx6ul-snvs"; + reg = <0x020b0000 0x4000>; + interrupts = ; + }; + fec2: ethernet@020b4000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x020b4000 0x4000>; @@ -475,8 +599,11 @@ <&clks IMX6UL_CLK_ENET2_REF_125M>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 4>; fsl,num-tx-queues=<1>; fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -588,6 +715,19 @@ fsl,anatop = <&anatop>; }; + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -604,7 +744,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; @@ -642,6 +782,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: iomuxc@020e0000 { @@ -664,6 +805,13 @@ clock-names = "ipg", "per"; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + sdma: sdma@020ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; @@ -673,6 +821,7 @@ <&clks IMX6UL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + iram = <&ocram>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; @@ -728,6 +877,35 @@ reg = <0x02100000 0x100000>; ranges; + crypto: caam@2140000 { + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + usbotg1: usb@02184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; @@ -773,8 +951,18 @@ <&clks IMX6UL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 3>; fsl,num-tx-queues=<1>; fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + sim1: sim@0218c000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x0218c000 0x4000>; + interrupts = ; status = "disabled"; }; @@ -844,11 +1032,56 @@ status = "disabled"; }; + romcp@021ac000 { + compatible = "fsl,imx6ul-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + mmdc: mmdc@021b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; + sim2: sim@021b4000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SIM2>; + clock-names = "sim"; + status = "disabled"; + }; + + weim: weim@021b8000 { + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6ul-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6ul-csu"; + reg = <0x021c0000 0x4000>; + interrupts = ; + status = "disabled"; + }; + + csi: csi@021c4000 { + compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; + reg = <0x021c4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + lcdif: lcdif@021c8000 { compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; @@ -873,47 +1106,65 @@ status = "disabled"; }; + pxp: pxp@021cc000 { + compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x021cc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PXP>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART2_IPG>, <&clks IMX6UL_CLK_UART2_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart3: serial@021ec000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART3_IPG>, <&clks IMX6UL_CLK_UART3_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart4: serial@021f0000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART4_IPG>, <&clks IMX6UL_CLK_UART4_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart5: serial@021f4000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART5_IPG>, <&clks IMX6UL_CLK_UART5_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -929,12 +1180,14 @@ uart6: serial@021fc000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021fc000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART6_IPG>, <&clks IMX6UL_CLK_UART6_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-adc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-adc.dts new file mode 100644 index 00000000000000..334597cac3cefa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-adc.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&usbotg1 { + status = "disabled"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_vref_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts new file mode 100644 index 00000000000000..0b498b21fc8ad9 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-cs42888.dts @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2-lcdif.dts" + +/ { + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_codec_5v: codec_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_aud_3v3: aud_3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec_a>; + codec-master; + }; + + sound-wm8958 { + compatible = "fsl,imx6ul-ddr3-arm2-wm8958", + "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec_b>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + hp-det-gpios = <&gpio5 0 1>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6UL_CLK_ESAI_SEL>, + <&clks IMX6UL_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec_a: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&codec_osc 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + codec_b: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_3v3>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_codec_5v>; + SPKVDD2-supply = <®_codec_5v>; + + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&ov5640 { + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for ESAI */ + fsl,sdma-event-remap = <0 14 1>, <0 15 1>; +}; + +&uart2 { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ecspi.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ecspi.dts new file mode 100644 index 00000000000000..60962c47c41be1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ecspi.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&ecspi1 { + status ="okay"; +}; + +&esai { + status ="disabled"; +}; + +&ov5640{ + status ="disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts new file mode 100644 index 00000000000000..934e6f6b8502ed --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-epdc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-epdc.dts new file mode 100644 index 00000000000000..c476f442efdf43 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-epdc.dts @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&epdc { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-flexcan2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-flexcan2.dts new file mode 100644 index 00000000000000..7169630ccc516d --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-flexcan2.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +/* flexcan2 tx/rx pin conflicts with uart2 */ + +&uart2{ + status = "disabled"; +}; + +&flexcan2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts new file mode 100644 index 00000000000000..327677aafa7da1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&gpmi { + status ="okay"; +}; + +&qspi { + status ="disabled"; +}; + +&usdhc2{ + status ="disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts new file mode 100644 index 00000000000000..40e86a4e08c3d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for LCDIF at imx6ull ddr3 arm2 board */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +/ { + backlight { + status = "okay"; + }; +}; + +&fec1 { + status = "disabled"; +}; + +&lcdif { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ldo.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ldo.dts new file mode 100644 index 00000000000000..4266dc243da622 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-ldo.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 996000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi-all.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi-all.dts new file mode 100644 index 00000000000000..a4cdbe588d834b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi-all.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define REWORKED_ENABLE_ALL_QSPI +#include "imx6ull-14x14-ddr3-arm2.dts" + +&gpmi { + status ="disabled"; +}; + +&usdhc2{ + status ="disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi.dts new file mode 100644 index 00000000000000..2155c7af1b7796 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-qspi.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-tsc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-tsc.dts new file mode 100644 index 00000000000000..8893e39b0ac36a --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-tsc.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2-lcdif.dts" + +&csi { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +®_usb_otg1_vbus { + pinctrl-0 = < >; + gpio = < >; +}; + +&ov5640 { + status = "disabled"; +}; + +&usbotg1 { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + status = "okay"; + xnur-gpio = <&gpio1 3 0>; + measure_delay_time = <0xfff>; + pre_charge_time = <0xffff>; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-uart2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-uart2.dts new file mode 100644 index 00000000000000..6f157ea4656d4d --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-uart2.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&flexcan2 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-usb.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-usb.dts new file mode 100644 index 00000000000000..619c28b89d46c0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-usb.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for validate USB at i.mx6ull ddr3 arm2 board */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +/ { + regulators { + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg2_vbus"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + usbotg2 { + pinctrl_usb_otg2_id: usbotg2idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usb_otg2: usbotg2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x10b0 + >; + }; + }; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; /* hardware rework is needed */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + no-1-8-v; + vmmc-supply = <>; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts new file mode 100644 index 00000000000000..498281b2c88b7f --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-wm8958.dts @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +/ { + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_codec_5v: codec_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_aud_3v3: aud_3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + }; + + sound-mqs { + compatible = "fsl,imx6ul-ddr3-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + asrc-controller = <&asrc>; + audio-codec = <&mqs>; + }; + + sound-wm8958 { + compatible = "fsl,imx6ul-ddr3-arm2-wm8958", + "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec_b>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + hp-det-gpios = <&gpio5 0 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec_b: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_3v3>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_codec_5v>; + SPKVDD2-supply = <®_codec_5v>; + + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6UL_CLK_SPDIF_SEL>, + <&clks IMX6UL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <49152000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usdhc1 { + no-1-8-v; + vmmc-supply = <>; + status = "disabled"; +}; + +&usdhc2 { + no-1-8-v; +}; + +&wdog1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts new file mode 100644 index 00000000000000..fdd27eb717a85a --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts @@ -0,0 +1,1029 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL DDR3 ARM2 Board"; + compatible = "fsl,imx6ull-ddr3-arm2", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "disabled"; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + /* For bringup, comments this. + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; + */ +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio5 8 1>; + rst-gpios = <&gpio5 7 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio3 16 0>; + gpio_pmic_vcom_ctrl = <&gpio3 24 0>; + gpio_pmic_wakeup = <&gpio3 14 0>; + gpio_pmic_v3p3 = <&gpio3 17 0>; + gpio_pmic_intr = <&gpio3 13 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&iomuxc { + imx6ul-ddr3-arm2 { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1 + MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1 + MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1 + MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1 + MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1 + MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1 + MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1 + MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1 + MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1 + MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1 + MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1 + MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1 + MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1 + MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1 + MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1 + MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1 + MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1 + MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1 + MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1 + MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1 + MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1 + MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1 + MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1 + MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1 + MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x10b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0 + MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0 + MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0 + MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0 + MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0 + MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0 + MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0 + MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */ + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */ + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 +#ifdef REWORKED_ENABLE_ALL_QSPI + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 +#endif + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + >; + }; + + pinctrl_usdhc1_rst: usdhc1_rst_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_vselect: usdhc1_vselect_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_rst: usdhc2_rst_grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + imx6ul-ddr3-arm2 { + pinctrl_bt: btgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; +#ifdef REWORKED_ENABLE_ALL_QSPI + fsl,qspi-has-second-chip = <1>; +#endif + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + +#ifdef REWORKED_ENABLE_ALL_QSPI + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +#endif +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "disabled"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>; + non-removable; + no-1-8-v; /* VSELECT not connected by default */ + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..85ea147de16f68 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts new file mode 100644 index 00000000000000..8a0a85d2e19753 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts new file mode 100644 index 00000000000000..4ea3d91e2cb68c --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000000..924696ee6d7dab --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + imx6ull-evk-gpmi-rework { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-usb-certi.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-usb-certi.dts new file mode 100644 index 00000000000000..15d9176fdd5925 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-usb-certi.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for USB Certification at i.mx6ull 14x14 evk board */ + +#include "imx6ull-14x14-evk.dts" + +/ { + regulators { + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; /* hardware rework is needed */ + tpl-support; +}; + +&tsc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts new file mode 100644 index 00000000000000..0f2d7e961459d0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,750 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&cpu0 { + dc-supply = <®_gpio_dvfs>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ul-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts new file mode 100644 index 00000000000000..8d00a908ee94aa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk-btwifi.dts" +#include "imx6ul-evk-btwifi-oob.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts new file mode 100644 index 00000000000000..c8a51006213f24 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts b/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts new file mode 100644 index 00000000000000..a878fe5bbb78c8 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +&cpu0 { + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff --git a/arch/arm/boot/dts/imx6ull-9x9-evk.dts b/arch/arm/boot/dts/imx6ull-9x9-evk.dts new file mode 100644 index 00000000000000..8f7c6f8926b6d1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-9x9-evk.dts @@ -0,0 +1,813 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 9x9 EVK Board"; + compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ull-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h new file mode 100644 index 00000000000000..7df88fd7c25ff5 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +#define __DTS_IMX6ULL_PINFUNC_SNVS_H +/* + * The pin function ID is a tuple of + * + */ +#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h new file mode 100644 index 00000000000000..b788dac7e11159 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-pinfunc.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_H +#define __DTS_IMX6ULL_PINFUNC_H + +#include "imx6ul-pinfunc.h" +/* + * The pin function ID is a tuple of + * + */ +#define MX6UL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 + +#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 + +#define MX6UL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 +#define MX6UL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 +#define MX6UL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 +#define MX6UL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 +#define MX6UL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 +#define MX6UL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 +#define MX6UL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 +#define MX6UL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 +#define MX6UL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 +#define MX6UL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 +#define MX6UL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 + +/* Below pinfunc are different with i.MX6UL, so override them in here + * To avoid build warning, firstly undef them. + */ +#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX +#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX +#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS +#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS +#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 + +#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi new file mode 100644 index 00000000000000..2253804b85053a --- /dev/null +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -0,0 +1,1180 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "imx6ull-pinfunc.h" +#include "imx6ull-pinfunc-snvs.h" +#include "skeleton.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-latency = <61036>; /* two CLK32 periods */ + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,low-power-run; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", + "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + status = "disabled"; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { + compatible = "mmio-sram"; + reg = <0x00905000 0x1B000>; + }; + + dma_apbh: dma-apbh@01804000 { + compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6UL_CLK_APBHDMA>; + }; + + gpmi: gpmi-nand@01806000{ + compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX6UL_CLK_GPMI_IO>, + <&clks IMX6UL_CLK_GPMI_APB>, + <&clks IMX6UL_CLK_GPMI_BCH>, + <&clks IMX6UL_CLK_GPMI_BCH_APB>, + <&clks IMX6UL_CLK_PER_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 41 18 0>, + <&sdma 42 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, + <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_SPDIF>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial@02018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + esai: esai@02024000 { + compatible = "fsl,imx6ull-esai"; + reg = <0x02024000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ESAI_IPG>, + <&clks IMX6UL_CLK_ESAI_MEM>, + <&clks IMX6UL_CLK_ESAI_EXTAL>, + <&clks IMX6UL_CLK_ESAI_IPG>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "mem", "extal", + "fsys", "spba"; + dmas = <&sdma 0 21 0>, <&sdma 47 21 0>; + dma-names = "rx", "tx"; + dma-source = <&gpr 0 14 0 15>; + status = "disabled"; + }; + + sai1: sai@02028000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x02028000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI1>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; + status = "disabled"; + }; + + sai2: sai@0202c000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x0202c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; + status = "disabled"; + }; + + sai3: sai@02030000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x02030000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI3>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; + status = "disabled"; + }; + + asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; + }; + + tsc: tsc@02040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + status = "disabled"; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM1>, + <&clks IMX6UL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM3>, + <&clks IMX6UL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + flexcan1: can@02090000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN1_IPG>, + <&clks IMX6UL_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; + status = "disabled"; + }; + + flexcan2: can@02094000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN2_IPG>, + <&clks IMX6UL_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; + status = "disabled"; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT_3M>; + clock-names = "ipg", "osc_per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + snvslp: snvs@020b0000 { + compatible = "fsl,imx6ul-snvs"; + reg = <0x020b0000 0x4000>; + interrupts = ; + }; + + fec2: ethernet@020b4000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x020b4000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET2_REF_125M>, + <&clks IMX6UL_CLK_ENET2_REF_125M>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 4>; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: src@020d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + gpt2: gpt@020e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SDMA>, + <&clks IMX6UL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pwm5: pwm@020f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm6: pwm@020f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm7: pwm@020f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm8: pwm@020fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + fec1: ethernet@02188000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET_REF>, + <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; + bus-width = <4>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; + bus-width = <4>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + adc1: adc@02198000 { + compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ADC1>; + num-channels = <2>; + clock-names = "adc"; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + romcp@021ac000 { + compatible = "fsl,imx6ul-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + weim: weim@021b8000 { + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6ull-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6ul-csu"; + reg = <0x021c0000 0x4000>; + interrupts = ; + status = "disabled"; + }; + + csi: csi@021c4000 { + compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; + reg = <0x021c4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + lcdif: lcdif@021c8000 { + compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; + reg = <0x021c8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, + <&clks IMX6UL_CLK_LCDIF_APB>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + pxp: pxp@021cc000 { + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x021cc000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + qspi: qspi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6UL_CLK_QSPI>, + <&clks IMX6UL_CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@021fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + aips3: aips-bus@02200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + dcp: dcp@02280000 { + compatible = "fsl,imx6sl-dcp"; + reg = <0x02280000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6UL_CLK_DCP_CLK>; + clock-names = "dcp"; + }; + + rngb: rngb@02284000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + uart8: serial@02288000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02288000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + epdc: epdc@0228c000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x0228c000 0x4000>; + clocks = <&clks IMX6UL_CLK_EPDC_ACLK>, + <&clks IMX6UL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + /* Need to fix epdc-ram */ + /* epdc-ram = <&gpr 0x4 30>; */ + status = "disabled"; + }; + + iomuxc_snvs: iomuxc-snvs@02290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x10000>; + }; + + snvs_gpr: snvs-gpr@0x02294000 { + compatible = "fsl, imx6ull-snvs-gpr"; + reg = <0x02294000 0x10000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts new file mode 100644 index 00000000000000..8626f3b50fb3f2 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts @@ -0,0 +1,558 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 DDR3 12x12 ARM2 Board"; + compatible = "fsl,imx7d-12x12-ddr3-arm2", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <4>; + cs-gpios = <&gpio5 3 0>, <&gpio5 4 0>, <&gpio5 5 0>, <&gpio5 6 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epxp { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-12x12-ddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + >; + }; + + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CLK__GPIO5_IO3 0x2 + MX7D_PAD_SD1_CMD__GPIO5_IO4 0x2 + MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x2 + MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x2 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x2 + MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x2 + MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x2 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x59 + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x59 + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x32 + MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x32 + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x4001b0b0 + MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x4001b0b0 + MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x4001b0b0 + MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x4001b0b0 + MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x4001b0b0 + MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x4001b0b0 + MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x4001b0b0 + MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x4001b0b0 + MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x4001b0b0 + MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x4001b0b0 + MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x4001b0b0 + MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x4001b0b0 + MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x4001b0b0 + MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x4001b0b0 + MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x4001b0b0 + MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x4001b0b0 + MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x4001b0b0 + MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x4001b0b0 + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x4001b0b0 + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x4001b0b0 + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x4001b0b0 + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x4001b0b0 + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x4001b0b0 + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x4001b0b0 + MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x4001b0b0 + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x4001b0b0 + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x4001b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x59 + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x59 + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x59 + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5a + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5a + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5a + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5b + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5b + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5b + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-12x12-ddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */ + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */ + MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x80000000 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x4000007f + MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x4000007f + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC2_ROOT_CLK>; + assigned-clocks-rates = <400000000>; + bus-width = <8>; + tuning-step = <2>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + vmmc-supply = <®_sd3_vmmc>; + cd-gpios = <&gpio1 14>; + wp-gpios = <&gpio1 15>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts new file mode 100644 index 00000000000000..16dd447a141f9e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +&epdc { + status = "disabled"; +}; + +&ecspi1{ + status = "okay"; +}; + +/* + * pin conflict with ecspi1 + * default hog setting conflicts with ECSPI1 MOSI and MISO + * EPDC PWRCTRL conflicts with ECSPI1 CS pin + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl-1 = <&pinctrl_hog_1>; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-enet2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-enet2.dts new file mode 100644 index 00000000000000..151853dc1712ad --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-enet2.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +&epdc { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-flexcan.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-flexcan.dts new file mode 100644 index 00000000000000..90ea88599b708b --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-flexcan.dts @@ -0,0 +1,29 @@ +/* +* Copyright (C) 2015 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +&fec1 { + status = "disabled"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&sai1 { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-m4.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-m4.dts new file mode 100644 index 00000000000000..d5579f2b437c1e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-m4.dts @@ -0,0 +1,76 @@ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/ { + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>, + <0xc0000000 0x40000000>; + }; + + gpio-keys { + status = "disabled"; + }; + + m4_tcm: tcml@007f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; +}; + +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + + +&i2c1 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&gpt3 { + status = "disabled"; +}; + +&gpt4 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +&rpmsg{ + status = "okay"; +}; + +&sim1 { + status = "disabled"; +}; + +&tempmon { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mipi_dsi.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mipi_dsi.dts new file mode 100644 index 00000000000000..db38d4120f3408 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mipi_dsi.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/ { + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; +}; + +&lcdif { + disp-dev = "mipi_dsi_samsung"; +}; + +&mipi_dsi { + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mqs.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mqs.dts new file mode 100644 index 00000000000000..7fcdf6a060d8b0 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-mqs.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/ { + sound-mqs { + compatible = "fsl,imx7d-12x12-lpddr3-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <786432000>; +}; + +&mqs { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mqs>; + pinctrl-1 = <&pinctrl_mqs>; + clocks = <&clks IMX7D_SAI1_ROOT_CLK>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&sim1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-pcie.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-pcie.dts new file mode 100644 index 00000000000000..ffe65d934331ae --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-pcie.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* + * On imx7d 12x12 arm2 board, there is pin(gpio6_21) iomux + * between ecspi3 and pcie_rst_b. In order to resove this + * pin conflict, disable ecspi3 in this pcie named dts file. + */ +&ecspi3 { + status = "disabled"; +}; + +&pcie{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts new file mode 100644 index 00000000000000..3a7af2e8bf92e4 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-qspi.dts @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts new file mode 100644 index 00000000000000..f1d36ce65119d5 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/ { + sound { + compatible = "fsl,imx7d-12x12-lpddr3-arm2-wm8958", + "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + hp-det-gpios = <&gpio1 12 1>; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_headphone_det>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect>; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&sim1 { + status = "disabled"; +}; + +&usdhc2 { + no-1-8-v; +}; diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts new file mode 100644 index 00000000000000..feaf056c62d9ab --- /dev/null +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts @@ -0,0 +1,1017 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 LPDDR3 12x12 ARM2 Board"; + compatible = "fsl,imx7d-12x12-lpddr3-arm2", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-arm2 { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-arm2 { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + }; + + imx7d-sdb { + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts new file mode 100644 index 00000000000000..2af374c666154f --- /dev/null +++ b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7D LPDDR2 19x19 ARM2 Board"; + compatible = "fsl,imx7d-19x19-lpddr2-arm2", "fsl,imx7d"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x71 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__EIM_OE 0x71 + MX7D_PAD_EPDC_DATA09__EIM_RW 0x71 + MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x71 + MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x71 + MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x75 + /* data */ + MX7D_PAD_LCD_DATA00__EIM_DATA0 0x7d + MX7D_PAD_LCD_DATA01__EIM_DATA1 0x7d + MX7D_PAD_LCD_DATA02__EIM_DATA2 0x7d + MX7D_PAD_LCD_DATA03__EIM_DATA3 0x7d + MX7D_PAD_LCD_DATA04__EIM_DATA4 0x7d + MX7D_PAD_LCD_DATA05__EIM_DATA5 0x7d + MX7D_PAD_LCD_DATA06__EIM_DATA6 0x7d + MX7D_PAD_LCD_DATA07__EIM_DATA7 0x7d + MX7D_PAD_LCD_DATA08__EIM_DATA8 0x7d + MX7D_PAD_LCD_DATA09__EIM_DATA9 0x7d + MX7D_PAD_LCD_DATA10__EIM_DATA10 0x7d + MX7D_PAD_LCD_DATA11__EIM_DATA11 0x7d + MX7D_PAD_LCD_DATA12__EIM_DATA12 0x7d + MX7D_PAD_LCD_DATA13__EIM_DATA13 0x7d + MX7D_PAD_LCD_DATA14__EIM_DATA14 0x7d + MX7D_PAD_LCD_DATA15__EIM_DATA15 0x7d + /* address */ + MX7D_PAD_EPDC_DATA00__EIM_AD0 0x71 + MX7D_PAD_EPDC_DATA01__EIM_AD1 0x71 + MX7D_PAD_EPDC_DATA02__EIM_AD2 0x71 + MX7D_PAD_EPDC_DATA03__EIM_AD3 0x71 + MX7D_PAD_EPDC_DATA04__EIM_AD4 0x71 + MX7D_PAD_EPDC_DATA05__EIM_AD5 0x71 + MX7D_PAD_EPDC_DATA06__EIM_AD6 0x71 + MX7D_PAD_EPDC_DATA07__EIM_AD7 0x71 + MX7D_PAD_EPDC_BDR1__EIM_AD8 0x71 + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x71 + MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x71 + MX7D_PAD_EPDC_SDLE__EIM_AD11 0x71 + MX7D_PAD_EPDC_SDOE__EIM_AD12 0x71 + MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x71 + MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x71 + MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x71 + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x71 + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x71 + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x71 + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x71 + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x71 + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x71 + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x71 + MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x71 + MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x71 + MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x71 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x28000000 0x08000000>; + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x08000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7-m4.dts b/arch/arm/boot/dts/imx7d-nitrogen7-m4.dts new file mode 100644 index 00000000000000..062acfbf9ff207 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-nitrogen7-m4.dts @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Boundary Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-nitrogen7.dts" + +/ { + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; + m4_tcm: tcml@007f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; +}; + +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&gpt3 { + status = "disabled"; +}; + +&gpt4 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&rpmsg { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index ce08f180f213e1..73d4ceceb3ba0e 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -44,20 +44,466 @@ #include "imx7d.dtsi" +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; + + iomuxc_nitrogen7: iomuxc-nitrogen7grp { + status = "okay"; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + iomuxc_lpsr_nitrogen7: iomuxc-lpsr-nitrogen7grp { + status = "okay"; + }; +}; + +&iomuxc_nitrogen7 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC reset */ + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d /* MIPI backlight */ + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d /* pmic */ + >; + }; + + pinctrl_bt_rfkill: btrfkillgrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x7d + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 + MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 /* Reset */ + >; + }; + + pinctrl_flash: flashgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x71 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x71 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x71 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x71 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x71 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x71 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_1: i2c1_1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio4 8 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f +#define GP_I2C1_SDA <&gpio4 9 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2_1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 10 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f +#define GP_I2C2_SDA <&gpio4 11 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3_1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f +#define GP_I2C3_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + >; + }; + + pinctrl_i2c3_tsc2004: i2c3tsc2004grp { + fsl,pins = < + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4_1grp { + fsl,pins = < +#define GP_I2C4_SCL <&gpio4 14 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x4000007f +#define GP_I2C4_SDA <&gpio4 15 GPIO_ACTIVE_HIGH> + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x4000007f + >; + }; + + pinctrl_j2: j2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d /* pin 1 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d /* pin 2 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d /* pin 3 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d /* pin 4 */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d /* pin 5 */ + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d /* pin 6 */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d /* pin 7 */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d /* pin 10 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d /* pin 15 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d /* pin 17 */ + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d /* pin 19 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d /* pin 21 */ + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d /* pin 23 */ + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d /* pin 25 */ + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d /* pin 26 */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d /* pin 27 */ + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d /* pin 28 */ + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d /* pin 30 */ + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d /* pin 33 */ + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d /* pin 34 */ + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d /* pin 35 */ + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d /* pin 37 */ + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d /* pin 38 */ + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d /* pin 39 */ + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d /* pin 40 */ + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d /* pin 41 */ + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d /* pin 42 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d /* pin 43 */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d /* pin 45 */ + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d /* pin 47 */ + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d /* pin 51 */ + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d /* pin 53 */ + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d /* pin 55 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d /* pin 57 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d /* pin 59 */ + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x79 + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x79 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x0a + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x0b + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a +#define GPIRQ_WL1271 <&gpio4 20 IRQ_TYPE_LEVEL_HIGH> + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x5a /* WL_HOST_WAKE */ + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x5a /* WL_REG_ON */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; +}; + +&iomuxc_lpsr_nitrogen7 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d /* ENET INT */ + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d /* Slow clock */ + >; + }; + + pinctrl_backlight_j9: backlightj9grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d /* J9 pin 3 */ + >; + }; + + pinctrl_mipi_csi: mipicsigrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x15 /* MIPI reset */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75 + >; + }; +}; + / { model = "Boundary Devices i.MX7 Nitrogen7 Board"; compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; aliases { fb_lcd = &lcdif; + lcd = &display0; + mmc0 = &usdhc1; + mmc1 = &usdhc3; + mmc2 = &usdhc2; t_lcd = &t_lcd; }; - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight-j9 { + backlight_j9 { compatible = "gpio-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight_j9>; @@ -65,7 +511,7 @@ default-on; }; - backlight-j20 { + backlight_j20 { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -73,56 +519,114 @@ status = "okay"; }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; + bt_rfkill { + compatible = "net,rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_rfkill>; + name = "bt_rfkill"; + type = <2>; /* bluetooth */ + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; }; - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; + memory { + reg = <0x80000000 0x40000000>; }; - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + mipi_mclk: mipi_mclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm2 0 45>; /* 1 / 45 ns = 22 MHz */ }; - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; }; - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vref_2v5: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vref-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_vref_3v3: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan: regulator@5 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "slow"; + regulator-name = "reg_wlan"; + startup-delay-us = <70000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "slow"; - regulator-name = "reg_wlan"; - startup-delay-us = <70000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; + sound { + compatible = "fsl,imx7d-nitrogen7-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; }; }; @@ -138,18 +642,37 @@ &clks { assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; + <&clks IMX7D_CLKO2_ROOT_DIV>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; + assigned-clock-rates = <0>, <32768>, <884736000>; }; &cpu0 { arm-supply = <&sw1a_reg>; }; +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + +&epxp { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; +#if 0 + phy-reset-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; +#endif assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; @@ -164,7 +687,9 @@ #size-cells = <0>; ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; + interrupts-extended = <&gpio1 2 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -172,13 +697,49 @@ &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; + trx-stby-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; status = "okay"; }; -&i2c1 { +&qspi1 { pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flash>; + status = "okay"; + + flash: m25p80@0 { + compatible = "winbond,w25q128"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "U-Boot Env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x11e000>; + }; + partition@1E0000 { + label = "M4"; + reg = <0x1E0000 0x20000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; status = "okay"; pmic: pfuze3000@08 { @@ -274,12 +835,38 @@ }; &i2c2 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; status = "okay"; - rtc@68 { - compatible = "rv4162"; + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipisubdev"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi>; + clocks = <&mipi_mclk>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_vref_1v8>; + AVDD-supply = <®_vref_2v5>; + DVDD-supply = <®_vref_3v3>; + pwn-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; + + rv4162@68 { + compatible = "microcrystal,rv4162"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2_rv4162>; reg = <0x68>; @@ -288,12 +875,16 @@ }; &i2c3 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; status = "okay"; - touch@48 { - compatible = "ti,tsc2004"; + tsc2004: tsc2004@48 { + compatible = "tsc2004,tsc2004"; reg = <0x48>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_tsc2004>; @@ -303,8 +894,12 @@ }; &i2c4 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_1>; + scl-gpios = GP_I2C4_SCL; + sda-gpios = GP_I2C4_SDA; status = "okay"; codec: wm8960@1a { @@ -350,6 +945,30 @@ }; }; +&mipi_csi { + status = "okay"; + port { + mipi_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-wclk; + }; + + csi_mipi_ep: endpoint2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio6 17 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -359,6 +978,23 @@ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; + assigned-clocks = <&clks IMX7D_PWM2_ROOT_SRC>, <&clks IMX7D_PWM2_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <49152000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sdma { status = "okay"; }; @@ -383,6 +1019,11 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + control-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + rs485_txen_mask = <0x1>; + rs485_txen_levels = <0x1>; + uart-has-rs485-half-duplex; + rs485-mode = <1>; status = "okay"; }; @@ -411,45 +1052,50 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; vmmc-supply = <&vgen3_reg>; - bus-width = <4>; - fsl,tuning-step = <2>; - wakeup-source; + enable-sdio-wakeup; + no-1-8-v; /* tmp, 1.8V should work*/ keep-power-in-suspend; status = "okay"; }; &usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wlan>; + vqmmc-1-8-v; cap-power-off-card; keep-power-in-suspend; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; + interrupts-extended = GPIRQ_WL1271; reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; ref-clock-frequency = <38400000>; }; }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-step = <2>; non-removable; status = "okay"; }; @@ -457,288 +1103,6 @@ &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; status = "okay"; }; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; - - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c2_rv4162: i2c2-rv4162grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_tsc2004: i2c3tsc2004grp { - fsl,pins = < - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_j2: j2grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_2>; - - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d - MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_backlight_j9: backlightj9grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h new file mode 100644 index 00000000000000..378694ee05c206 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX7D_PINFUNC_LPSR_H +#define __DTS_IMX7D_PINFUNC_LPSR_H + +/* + * The pin function ID is a tuple of + * + * + * NOTE: imx7d-lpsr pin groups should be put under &iomuxc_lpsr node when used + */ + +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 + +#endif /* __DTS_IMX7D_PINFUNC_LPSR_H */ diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index 3f9f0d9c8094b3..3c54694782d0dc 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,57 +15,6 @@ * */ -#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 #define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 @@ -588,7 +537,7 @@ #define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 @@ -1108,13 +1057,13 @@ #define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 diff --git a/arch/arm/boot/dts/imx7d-sdb-epdc.dts b/arch/arm/boot/dts/imx7d-sdb-epdc.dts new file mode 100644 index 00000000000000..e263ad446373eb --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-epdc.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-epdc.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi b/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi new file mode 100644 index 00000000000000..a04aca79b19db6 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts new file mode 100644 index 00000000000000..346e38cca609c5 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-gpmi-weim.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi new file mode 100644 index 00000000000000..3a1208f44242a4 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&gpmi{ + status = "okay"; +}; + +&sai1{ + status = "disabled"; +}; + +&usdhc3{ + status = "disabled"; +}; + +&uart5{ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-m4.dts b/arch/arm/boot/dts/imx7d-sdb-m4.dts new file mode 100644 index 00000000000000..7aa803559ef59a --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-m4.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-m4.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-m4.dtsi b/arch/arm/boot/dts/imx7d-sdb-m4.dtsi new file mode 100644 index 00000000000000..deba9ef7564600 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-m4.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + memory { + linux,usable-memory = <0x80000000 0x1ff00000>, + <0xa0000000 0x1ff00000>; + }; + m4_tcm: tcml@007f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; +}; + +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&gpt3 { + status = "disabled"; +}; + +&gpt4 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts new file mode 100644 index 00000000000000..327d976e40660f --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; +}; + +&lcdif { + disp-dev = "mipi_dsi_samsung"; + disp-videomode = "TRUULY-WVGA-SYNC-LOW"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dts b/arch/arm/boot/dts/imx7d-sdb-qspi.dts new file mode 100644 index 00000000000000..a46990554d28ed --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-qspi.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi b/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi new file mode 100644 index 00000000000000..1ba3e66c974ad9 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l51245g"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-epdc.dts b/arch/arm/boot/dts/imx7d-sdb-reva-epdc.dts new file mode 100644 index 00000000000000..341a8ad0b696b0 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-epdc.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb-reva.dts" +#include "imx7d-sdb-epdc.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-gpmi-weim.dts b/arch/arm/boot/dts/imx7d-sdb-reva-gpmi-weim.dts new file mode 100644 index 00000000000000..4d221f8d7dd776 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-gpmi-weim.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb-reva.dts" +#include "imx7d-sdb-gpmi-weim.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-hdmi-audio.dts b/arch/arm/boot/dts/imx7d-sdb-reva-hdmi-audio.dts new file mode 100644 index 00000000000000..b9fea5be4b9346 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-hdmi-audio.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + sound { + status = "disabled"; + }; + + sound-hdmi { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-m4.dts b/arch/arm/boot/dts/imx7d-sdb-reva-m4.dts new file mode 100644 index 00000000000000..78148f0d0a04d2 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-m4.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb-reva.dts" +#include "imx7d-sdb-m4.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-qspi.dts b/arch/arm/boot/dts/imx7d-sdb-reva-qspi.dts new file mode 100644 index 00000000000000..7b523cac9575b4 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-qspi.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb-reva.dts" +#include "imx7d-sdb-qspi.dtsi" diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-touch.dts b/arch/arm/boot/dts/imx7d-sdb-reva-touch.dts new file mode 100644 index 00000000000000..d3855e8d797819 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-touch.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb-reva.dts" + +&sii902x { + status = "disabled"; +}; + +&ecspi3 { + status = "okay"; + + tsc2046 { + interrupts = <13 0>; + pendown-gpio = <&gpio2 13 0>; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-reva-wm8960.dts b/arch/arm/boot/dts/imx7d-sdb-reva-wm8960.dts new file mode 100644 index 00000000000000..4aa7d91485c5f0 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva-wm8960.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + sound { + status = "okay"; + }; + + sound-hdmi { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/imx7d-sdb-reva.dts new file mode 100644 index 00000000000000..36568bd8df5739 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + regulators { + reg_usb_otg2_vbus: regulator@1 { + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + }; + + reg_pcie: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-hdmi { + cpu-dai = <&sai1>; + }; +}; + +&ecspi3 { + status = "disabled"; +}; + +&epdc { + pinctrl-0 = <&pinctrl_epdc0>; + en-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <>; +}; + +&i2c4 { + ov5647_mipi: ov5647_mipi@36 { + pwn-gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79 + >; + }; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_usbotg2_pwr_1>; +}; + +&iomuxc_lpsr { + pinctrl-0 = <&pinctrl_hog_2>; +}; + +&uart5 { + fsl,uart-has-rtscts; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 2f33c463cbce4f..1f09a0e7b99968 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -52,6 +52,13 @@ reg = <0x80000000 0x80000000>; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -73,7 +80,7 @@ regulator-name = "usb_otg2_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -83,7 +90,7 @@ regulator-name = "can2-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; }; reg_vref_1v8: regulator@3 { @@ -93,6 +100,102 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + reg_sd1_vmmc: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + off-on-delay = <20000>; + enable-active-high; + }; + + wlreg_on: fixedregulator@6 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + gpios = <&gpio4 20 0>; /* WL_HOST_WAKE */ + wlreg_on-supply = <&wlreg_on>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + hp-det-gpios = <&gpio2 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; + }; + + sound-hdmi { + compatible = "fsl,imx7d-sdb-sii902x", + "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + cpu-dai = <&sai3>; + hdmi-controler = <&sii902x>; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + gpio-sck = <&gpio1 13 0>; + gpio-mosi = <&gpio1 9 0>; + cs-gpios = <&gpio1 12 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ + spi-max-frequency = <100000>; + }; }; }; @@ -113,7 +216,7 @@ &ecspi3 { fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -136,9 +239,40 @@ }; }; +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&epxp { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; + pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>; assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; @@ -153,10 +287,12 @@ #size-cells = <0>; ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; @@ -164,7 +300,8 @@ &fec2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>; + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; @@ -175,7 +312,33 @@ status = "okay"; }; +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi_mipi_ep: endpoint2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + &i2c1 { + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; @@ -187,7 +350,7 @@ regulators { sw1a_reg: sw1a { regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; @@ -272,18 +435,117 @@ }; &i2c2 { + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; }; &i2c3 { + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sii902x>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + reg = <0x39>; + status = "okay"; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio2 23 0>; + gpio_pmic_v3p3 = <&gpio2 30 0>; + gpio_pmic_intr = <&gpio2 22 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; }; &i2c4 { + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; @@ -295,15 +557,33 @@ clock-names = "mclk"; wlf,shared-lrclk; }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif>; + enable-gpio = <&gpio_spi 7 GPIO_ACTIVE_LOW>; display = <&display0>; status = "okay"; - display0: display { + display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; @@ -329,22 +609,133 @@ }; }; +&pcie_phy{ + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + reset-gpio = <&gpio_spi 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio_spi 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; + + imx7d-sdb { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usbotg2_pwr_2: usbotg2-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + + pinctrl_enet2_epdc0_en: enet2_epdc0_grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; +}; + +&sim1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim1_1>; + port = <0>; + sven_low_active; + status = "okay"; +}; + + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -355,15 +746,33 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + enable-sdio-wakeup; keep-power-in-suspend; status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + enable-sdio-wakeup; + keep-power-in-suspend; + non-removable; + cd-post; + pm-ignore-notify; + wifi-host; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -372,7 +781,6 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-step = <2>; non-removable; status = "okay"; }; @@ -383,17 +791,50 @@ fsl,ext-reset-output; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_hog_1>; imx7d-sdb { + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ + >; + }; + + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + >; + }; + + pinctrl_ecspi3_cs: ecspi3_cs_grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000 + >; + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 >; }; @@ -433,10 +874,63 @@ >; }; - pinctrl_hog: hoggrp { + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + >; + }; + + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 >; }; @@ -502,9 +996,40 @@ >; }; - pinctrl_pwm1: pwm1grp { + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { fsl,pins = < - MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0 + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 >; }; @@ -514,6 +1039,30 @@ >; }; + pinctrl_spi1: spi1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_sii902x: hdmigrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 @@ -525,8 +1074,13 @@ fsl,pins = < MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 >; }; @@ -536,6 +1090,22 @@ MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x19 /* BT_REG_ON */ + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usbotg2_pwr_1: usbotg2-1 { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 >; }; @@ -547,9 +1117,29 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; @@ -561,7 +1151,8 @@ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ >; }; @@ -636,10 +1227,5 @@ >; }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 - >; - }; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f6dee41a05d95b..457927ab3ffdea 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -1,6 +1,7 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2016 Toradex AG + * Copyright 2017 NXP. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -48,6 +49,7 @@ cpu0: cpu@0 { operating-points = < /* KHz uV */ + 1200000 1225000 996000 1075000 792000 975000 >; @@ -62,6 +64,20 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; @@ -83,6 +99,266 @@ }; }; }; + + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", + "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + status = "disabled"; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x00901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@00180000 { + compatible = "fsl,lpm-sram"; + reg = <0x00180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocrams_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_NAND_ROOT_CLK>; + clock-names = "dma_apbh_bch", "dma_apbh_io"; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@0x33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + pcie-phy-supply = <®_1p0d>; + fsl,max-link-speed = <2>; + status = "disabled"; + }; + }; +}; + +&aips1 { + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + status = "okay"; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = ; + fsl,tempmon =<&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + iomuxc_lpsr_gpr: lpsr-gpr@30270000 { + compatible = "fsl,imx7d-lpsr-gpr"; + reg = <0x30270000 0x10000>; + }; +}; + +&aips2 { + flextimer1: flextimer@30640000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30640000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + flextimer2: flextimer@30650000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30650000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + pcie_phy: pcie-phy@306d0000 { + compatible = "fsl,imx-pcie-phy"; + reg = <0x306d0000 0x10000>; + status = "disabled"; + }; + + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + mipi-phy-supply = <®_1p0d>; + status = "disabled"; + }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; }; }; @@ -95,6 +371,9 @@ fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; phy-clkgate-delay-us = <400>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -116,17 +395,111 @@ interrupts = , , ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; status = "disabled"; }; + + crypto: caam@30900000 { + compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + status = "disabled"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + qspi1: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + weim: weim@30bc0000 { + compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x30bc0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_EIM_ROOT_CLK>; + status = "disabled"; + }; + +}; + +&usbphynop3 { + vcc-supply = <®_1p2>; }; &ca_funnel_ports { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 2b6cb05bc01a85..74a3938ffd462c 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -46,6 +46,7 @@ #include #include #include "imx7d-pinfunc.h" +#include "imx7d-pinfunc-lpsr.h" #include "skeleton.dtsi" / { @@ -88,6 +89,7 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; + clock-names = "arm"; }; }; @@ -109,7 +111,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; funnel@30041000 { @@ -295,14 +297,18 @@ <0x31002000 0x2000>, <0x31004000 0x2000>, <0x31006000 0x2000>; + interrupt-parent = <&intc>; }; timer { compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; interrupts = , , , ; + interrupt-parent = <&intc>; + clock-frequency = <8000000>; }; aips1: aips-bus@30000000 { @@ -312,6 +318,23 @@ reg = <0x30000000 0x400000>; ranges; + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; + + pgc { + compatible = "fsl,imx7d-pgc"; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -437,9 +460,10 @@ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302d0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; + clocks = <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; }; gpt2: gpt@302e0000 { @@ -507,8 +531,23 @@ anatop-min-bit-val = <8>; anatop-min-voltage = <800000>; anatop-max-voltage = <1200000>; - anatop-enable-bit = <31>; + anatop-enable-bit = <0>; + }; + + reg_1p2: regulator-vdd1p2@220 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <31>; }; + }; snvs: snvs@30370000 { @@ -527,7 +566,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; }; snvs_pwrkey: snvs-powerkey { @@ -643,8 +682,9 @@ reg = <0x30730000 0x10000>; interrupts = ; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; }; @@ -711,6 +751,8 @@ clocks = <&clks IMX7D_UART2_ROOT_CLK>, <&clks IMX7D_UART2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -722,6 +764,8 @@ clocks = <&clks IMX7D_UART3_ROOT_CLK>, <&clks IMX7D_UART3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -731,10 +775,11 @@ reg = <0x308a0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI1_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; status = "disabled"; @@ -746,10 +791,11 @@ reg = <0x308b0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI2_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; status = "disabled"; @@ -761,10 +807,11 @@ reg = <0x308c0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI3_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; status = "disabled"; @@ -777,6 +824,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -787,6 +835,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -838,6 +887,8 @@ clocks = <&clks IMX7D_UART4_ROOT_CLK>, <&clks IMX7D_UART4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -849,6 +900,8 @@ clocks = <&clks IMX7D_UART5_ROOT_CLK>, <&clks IMX7D_UART5_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -860,6 +913,8 @@ clocks = <&clks IMX7D_UART6_ROOT_CLK>, <&clks IMX7D_UART6_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -871,6 +926,8 @@ clocks = <&clks IMX7D_UART7_ROOT_CLK>, <&clks IMX7D_UART7_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -882,6 +939,9 @@ fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; phy-clkgate-delay-us = <400>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -926,10 +986,12 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -942,6 +1004,8 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -954,6 +1018,8 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -975,11 +1041,11 @@ interrupts = , , ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; diff --git a/arch/arm/boot/dts/imx7ulp-14x14-arm2.dts b/arch/arm/boot/dts/imx7ulp-14x14-arm2.dts new file mode 100644 index 00000000000000..6db59d4e0bee83 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-14x14-arm2.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP 14x14 arm2"; + compatible = "fsl,imx7ulp-14x14-arm2", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; + stdout-path = &lpuart4; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-14x14-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + ULP1_PAD_PTC10__PTC10 0x30100 + ULP1_PAD_PTC1__PTC1 0x20100 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + ULP1_PAD_PTC3__LPUART4_RX 0x400 + ULP1_PAD_PTC2__LPUART4_TX 0x400 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + ULP1_PAD_PTE3__SDHC1_CMD 0x843 + ULP1_PAD_PTE2__SDHC1_CLK 0x843 + ULP1_PAD_PTE4__SDHC1_D3 0x843 + ULP1_PAD_PTE5__SDHC1_D2 0x843 + ULP1_PAD_PTE0__SDHC1_D1 0x843 + ULP1_PAD_PTE1__SDHC1_D0 0x843 + >; + }; + }; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-emmc-qspi.dts b/arch/arm/boot/dts/imx7ulp-evk-emmc-qspi.dts new file mode 100644 index 00000000000000..47289c636e94e8 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-emmc-qspi.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk-qspi.dts" + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-emmc.dts b/arch/arm/boot/dts/imx7ulp-evk-emmc.dts new file mode 100644 index 00000000000000..e58616e71b17aa --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-emmc.dts @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts b/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts new file mode 100644 index 00000000000000..2d86e33e1abb33 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&lpi2c7 { + focaltech@38 { + focaltech,panel-type = ; + focaltech,swap-xy; + /delete-property/focaltech,scaling-down-half; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-hdmi.dts b/arch/arm/boot/dts/imx7ulp-evk-hdmi.dts new file mode 100644 index 00000000000000..d56c8e147a2bcd --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-hdmi.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&adv7535 { + status = "okay"; + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; +}; + +&mipi_dsi { + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts b/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts new file mode 100644 index 00000000000000..6c9dba0f2a3554 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&lpi2c7 { + status = "disabled"; +}; + +&lpuart7 { /* Uart test */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-qspi.dts b/arch/arm/boot/dts/imx7ulp-evk-qspi.dts new file mode 100644 index 00000000000000..55bbad6f7c0bb8 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-qspi.dts @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/ { + regulators { + compatible = "simple-bus"; + + dummy: regulator-dummy { + compatible = "regulator-fixed"; + regulator-name = "dummy"; + regulator-always-on; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + + flash0: mx25r6435f@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25r6435f"; + spi-max-frequency = <29000000>; + }; +}; + +&rpmsg{ + status = "disabled"; +}; + +&cpu0 { + arm-supply= <&dummy>; + operating-points = < + /* KHz uV */ + 503666 1025000 + >; +}; + +&usdhc0 { + vqmmc-supply = <&dummy>; + no-1-8-v; + non-removable; +}; + +&iomuxc { + status = "okay"; +}; + +&iomuxc { + imx7ulp-evk { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x43 /* SS1 */ + ULP1_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + ULP1_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x43 /* DQS */ + ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x43 /* D3 */ + ULP1_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + ULP1_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x43 /* D0 */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-sd1.dts b/arch/arm/boot/dts/imx7ulp-evk-sd1.dts new file mode 100644 index 00000000000000..1dddfb214cf9ca --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-sd1.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/ { + regulators { + reg_vsd_3v3b: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VSD_3V3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&bcmdhd_wlan_0 { + status = "disabled"; +}; + +&lpuart6 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-2 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + cd-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_vsd_3v3b>; + /delete-property/non-removable; + /delete-property/cd-post; + /delete-property/wifi-host; + /delete-property/pm-ignore-notify; + /delete-property/keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-sensors-to-i2c5.dts b/arch/arm/boot/dts/imx7ulp-evk-sensors-to-i2c5.dts new file mode 100644 index 00000000000000..26f8c93782eb9a --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-sensors-to-i2c5.dts @@ -0,0 +1,21 @@ + +#include "imx7ulp-evk.dts" + +&lpi2c5 { + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk-wm8960.dts b/arch/arm/boot/dts/imx7ulp-evk-wm8960.dts new file mode 100644 index 00000000000000..9988bd15e0ae96 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk-wm8960.dts @@ -0,0 +1,217 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/ { + + aips0: aips-bus@41000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41000000 0x80000>; + ranges; + + pcc0: pcc0@41026000 { + compatible = "fsl,imx7ulp-pcc0"; + reg = <0x41026000 0x1000>; + }; + + clks_m4: scg0@41027000 { + compatible = "fsl,imx7ulp-scg0"; + reg = <0x41027000 0x1000>; + clocks = <&cm4_ckil>, <&cm4_osc>, <&cm4_sirc>, <&cm4_firc>; + clock-names = "cm4_ckil", "cm4_osc", "cm4_sirc", "cm4_firc"; + #clock-cells = <1>; + }; + + sai0: sai@41037000 { + compatible = "fsl,imx7ulp-sai"; + reg = <0x41037000 0x1000>; + interrupts = ; + clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI0_IPG>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>, + <&clks_m4 IMX7ULP_CM4_CLK_SAI0_ROOT>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 0 59>, <&edma0 0 60>; + status = "disabled"; + }; + }; + + aips1: aips-bus@41080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41080000 0x80000>; + ranges; + + smc0: smc0@410a4000 { + compatible = "fsl,imx7ulp-smc0"; + reg = <0x410a4000 0x1000>; + }; + + sai1: sai@410AA000 { + compatible = "fsl,imx7ulp-sai"; + reg = <0x410AA000 0x1000>; + interrupts = ; + clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI1_IPG>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>, + <&clks_m4 IMX7ULP_CM4_CLK_SAI1_ROOT>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>, + <&clks_m4 IMX7ULP_CM4_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 0 61>, <&edma0 0 62>; + status = "disabled"; + }; + + pcc1: pcc1@410b2000 { + compatible = "fsl,imx7ulp-pcc1"; + reg = <0x410b2000 0x1000>; + }; + }; + + clocks_m4 { + #address-cells = <1>; + #size-cells = <0>; + + cm4_ckil: clock@6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "cm4_ckil"; + }; + + cm4_osc: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cm4_osc"; + }; + + cm4_sirc: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "cm4_sirc"; + }; + + cm4_firc: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "cm4_firc"; + }; + }; + + sound-rpmsg { + status = "disabled"; + }; + + sound { + compatible = "fsl,imx7ulp-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai0>; + audio-codec = <&codec>; + codec-master; + /* JD3: hp detect high for headphone*/ + hp-det = <3 0>; + hp-det-gpios = <&gpio3 0 0>; + mic-det-gpios = <&gpio3 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB"; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_0_1>; + status = "okay"; + + imx7ulp-evk-0 { + pinctrl_hog_0_1: hoggrp-0-1 { + fsl,pins = < + ULP1_PAD_PTA24__PTA24 0x127 + ULP1_PAD_PTB0__CLKOUT 0x900 + >; + }; + + pinctrl_sai0: sai0_grp { + fsl,pins = < + ULP1_PAD_PTA4__I2S0_MCLK 0x700 + ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0700 + ULP1_PAD_PTA2__I2S0_RXD0 0x0700 + ULP1_PAD_PTA6__I2S0_TX_FS 0x0700 + ULP1_PAD_PTA7__I2S0_TXD0 0x0700 + >; + }; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_audio>; + + imx7ulp-evk { + pinctrl_hog_audio: hoggrp-audio { + fsl,pins = < + ULP1_PAD_PTF0__PTF0 0x30100 + >; + }; + }; +}; + +&lpi2c7 { + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks_m4 IMX7ULP_CLK_SCG0_CLKOUT>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_APLL_SEL>, + <&clks_m4 IMX7ULP_CLK_SCG0_CLKOUT>; + assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2>, + <&clks_m4 IMX7ULP_CM4_CLK_APLL_SEL>; + }; +}; + +&clks_m4 { + assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL>, + <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO>, + <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1>, + <&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2>, + <&clks_m4 IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV>; + assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_OSC>; + assigned-clock-rates = <0>, <540672000>, <49152000>, <12288000>, <270336000>; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks = <&clks_m4 IMX7ULP_CM4_CLK_SAI0_SEL>, + <&clks_m4 IMX7ULP_CM4_CLK_SAI0_DIV>; + assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,dataline = <0x1 0x1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts new file mode 100644 index 00000000000000..3ee6e3c34747d4 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -0,0 +1,551 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" +#include + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + + aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; + stdout-path = &lpuart4; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 1 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usb_otg1>; + pinctrl-1 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_extcon_usb1>; + pinctrl-1 = <&pinctrl_extcon_usb1>; + }; + + pf1550-rpmsg { + compatible = "fsl,pf1550-rpmsg"; + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; + }; + + rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + linux,code = ; + }; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; + }; +}; + +&cpu0 { + arm-supply= <&sw1_reg>; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + ULP1_PAD_PTC1__PTC1 0x20000 + >; + }; + + pinctrl_pwm0: pwm0_grp { + fsl,pins = < + ULP1_PAD_PTF2__TPM4_CH1 0x3 + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + ULP1_PAD_PTC4__LPI2C5_SCL 0x27 + ULP1_PAD_PTC5__LPI2C5_SDA 0x27 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + ULP1_PAD_PTC19__PTC19 0x20003 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + ULP1_PAD_PTC3__LPUART4_RX 0x3 + ULP1_PAD_PTC2__LPUART4_TX 0x3 + >; + }; + + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + ULP1_PAD_PTE10__LPUART6_TX 0x3 + ULP1_PAD_PTE11__LPUART6_RX 0x3 + ULP1_PAD_PTE9__LPUART6_RTS_B 0x3 + ULP1_PAD_PTE8__LPUART6_CTS_B 0x3 + ULP1_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + ULP1_PAD_PTF14__LPUART7_TX 0x3 + ULP1_PAD_PTF15__LPUART7_RX 0x3 + ULP1_PAD_PTF13__LPUART7_RTS_B 0x3 + ULP1_PAD_PTF12__LPUART7_CTS_B 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x43 + ULP1_PAD_PTD2__SDHC0_CLK 0x10043 + ULP1_PAD_PTD7__SDHC0_D3 0x43 + ULP1_PAD_PTD8__SDHC0_D2 0x43 + ULP1_PAD_PTD9__SDHC0_D1 0x43 + ULP1_PAD_PTD10__SDHC0_D0 0x43 + ULP1_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */ + ULP1_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */ + >; + }; + + pinctrl_usdhc0_8bit: usdhc0grp_8bit { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x43 + ULP1_PAD_PTD2__SDHC0_CLK 0x43 + ULP1_PAD_PTD3__SDHC0_D7 0x43 + ULP1_PAD_PTD4__SDHC0_D6 0x43 + ULP1_PAD_PTD5__SDHC0_D5 0x43 + ULP1_PAD_PTD6__SDHC0_D4 0x43 + ULP1_PAD_PTD7__SDHC0_D3 0x43 + ULP1_PAD_PTD8__SDHC0_D2 0x43 + ULP1_PAD_PTD9__SDHC0_D1 0x43 + ULP1_PAD_PTD10__SDHC0_D0 0x43 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + ULP1_PAD_PTF12__LPI2C7_SCL 0x27 + ULP1_PAD_PTF13__LPI2C7_SDA 0x27 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + ULP1_PAD_PTF16__LPSPI3_SIN 0x0 + ULP1_PAD_PTF17__LPSPI3_SOUT 0x0 + ULP1_PAD_PTF18__LPSPI3_SCK 0x0 + ULP1_PAD_PTF19__LPSPI3_PCS0 0x0 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + ULP1_PAD_PTC0__PTC0 0x20000 + >; + }; + + pinctrl_extcon_usb1: extcon1grp { + fsl,pins = < + ULP1_PAD_PTC8__PTC8 0x10003 + >; + }; + + pinctrl_focaltech: focaltechgrp { + fsl,pins = < + ULP1_PAD_PTF0__PTF0 0x10043 + ULP1_PAD_PTF1__PTF1 0x20043 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + ULP1_PAD_PTE3__SDHC1_CMD 0x43 + ULP1_PAD_PTE2__SDHC1_CLK 0x43 + ULP1_PAD_PTE1__SDHC1_D0 0x43 + ULP1_PAD_PTE0__SDHC1_D1 0x43 + ULP1_PAD_PTE5__SDHC1_D2 0x43 + ULP1_PAD_PTE4__SDHC1_D3 0x43 + >; + }; + + pinctrl_usdhc1_rst: usdhc1grp_rst { + fsl,pins = < + ULP1_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + ULP1_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + ULP1_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + ULP1_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + ULP1_PAD_PTE6__PTE6 0x20043 /* WL_REG_ON */ + >; + }; + + pinctrl_dsi_hdmi: dsi_hdmi_grp { + fsl,pins = < + ULP1_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ + >; + }; + }; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c7 &pinctrl_focaltech>; + pinctrl-1 = <&pinctrl_lpi2c7 &pinctrl_focaltech>; + status = "okay"; + + focaltech@38 { + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <0 0x02>; + focaltech,panel-type = ; + focaltech,reset-gpio = <&gpio3 1 0x01>; + focaltech,irq-gpio = <&gpio3 0 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 272 480>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,scaling-down-half; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_hdmi>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + video-mode = <1>; /* + * Only support CEA modes. + * Reference mxc_edid.c + */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "disabled"; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + }; +}; + +&mipi_dsi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-1 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart4>; + pinctrl-1 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&lpuart6 { /* BT */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart6>; + pinctrl-1 = <&pinctrl_lpuart6>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart7 { /* Uart test */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart7>; + pinctrl-1 = <&pinctrl_lpuart7>; + status = "disabled"; +}; + +&pwm0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pwm0>; + pinctrl-1 = <&pinctrl_pwm0>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance, default using 2 rpmsg instances: + * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio + * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty + */ + vdev-nums = <2>; + reg = <0x9FF00000 0x20000>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + extcon = <0>, <&extcon_usb1>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0xc>; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <&vldo2_reg>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_wifi>; + non-removable; + keep-power-in-suspend; + cd-post; + pm-ignore-notify; + wifi-host; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h new file mode 100644 index 00000000000000..388345d62db58e --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h @@ -0,0 +1,875 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_ULP1_PINFUNC_H +#define __DTS_ULP1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 +#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 +#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1 +#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1 +#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1 +#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1 +#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0 +#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1 +#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1 +#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1 +#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1 +#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1 +#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0 +#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1 +#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1 +#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1 +#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1 +#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1 +#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0 +#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1 +#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1 +#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1 +#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1 +#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0 +#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1 +#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1 +#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1 +#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1 +#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1 +#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1 +#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1 +#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1 +#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0 +#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0 +#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1 +#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1 +#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1 +#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1 +#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 +#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0 +#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 +#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1 +#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1 +#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1 +#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 +#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1 +#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1 +#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1 +#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1 +#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1 +#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1 +#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1 +#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2 +#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0 +#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1 +#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1 +#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1 +#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1 +#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1 +#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1 +#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2 +#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1 +#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1 +#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1 +#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2 +#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0 +#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 +#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1 +#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1 +#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1 +#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1 +#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2 +#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0 +#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 +#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2 +#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 +#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2 +#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1 +#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1 +#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2 +#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1 +#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1 +#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0 +#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 +#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 +#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2 +#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2 +#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2 +#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1 +#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1 +#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0 +#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 +#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 +#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2 +#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 +#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2 +#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2 +#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1 +#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0 +#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 +#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 +#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 +#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 +#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2 +#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2 +#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2 +#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2 +#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1 +#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1 +#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0 +#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 +#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 +#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2 +#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2 +#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2 +#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2 +#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1 +#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0 +#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 +#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 +#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2 +#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 +#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2 +#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2 +#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1 +#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 +#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 +#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 +#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2 +#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2 +#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2 +#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2 +#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1 +#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0 +#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2 +#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2 +#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1 +#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 +#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 +#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 +#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2 +#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2 +#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2 +#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2 +#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 +#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 +#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 +#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 +#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1 +#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 +#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1 +#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2 +#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 +#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0 +#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 +#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 +#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 +#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1 +#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1 +#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1 +#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2 +#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1 +#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 +#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 +#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 +#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 +#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3 +#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3 +#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2 +#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2 +#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2 +#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0 +#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 +#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 +#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3 +#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3 +#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2 +#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 +#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0 +#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 +#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3 +#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3 +#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3 +#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2 +#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 +#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 +#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0 +#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 +#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3 +#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3 +#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3 +#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2 +#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2 +#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3 +#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3 +#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3 +#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2 +#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2 +#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0 +#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3 +#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3 +#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3 +#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2 +#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0 +#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0 +#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0 +#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3 +#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3 +#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3 +#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2 +#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0 +#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3 +#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3 +#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3 +#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2 +#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0 +#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3 +#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3 +#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3 +#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2 +#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0 +#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3 +#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3 +#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3 +#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2 +#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3 +#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3 +#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0 +#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 +#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 + +#endif /* __DTS_ULP1_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index 00000000000000..323fa580bd5958 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -0,0 +1,633 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "skeleton.dtsi" +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + usbphy0 = &usbphy1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clock-latency = <61036>; /* two CLK32 periods */ + reg = <0>; + + operating-points = < + /* KHz uV */ + 531648 1125000 + 416072 1025000 + >; + clocks = <&clks IMX7ULP_CLK_ARM>, + <&clks IMX7ULP_CLK_CORE_DIV>, + <&clks IMX7ULP_CLK_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_CORE>, + <&clks IMX7ULP_CLK_SPLL_PFD0>, + <&clks IMX7ULP_CLK_SPLL_SEL>, + <&clks IMX7ULP_CLK_FIRC>; + clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", + "hsrun_core", "spll_pfd0", "spll_sel", "firc"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xC000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + rpmsg_reserved: rpmsg@9FFF0000 { + no-map; + reg = <0x9FF00000 0x100000>; + }; + + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + sirc: clock@2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + }; + + firc: clock@3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "firc"; + }; + + upll: clock@4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "upll"; + }; + + mpll: clock@5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + }; + }; + + sram: sram@20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x1fffc000 0x4000>; + }; + + ahbbridge0: ahb-bridge0@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + edma0: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "nxp,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>; + }; + + mu: mu@40220000 { + compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu"; + reg = <0x40220000 0x1000>; + interrupts = , + ; + status = "okay"; + }; + + nmi: nmi@40220000 { + compatible = "fsl,imx7ulp-nmi"; + reg = <0x40220000 0x1000>; + interrupts = ; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7ulp-rpmsg"; + memory-region = <&rpmsg_reserved>; + status = "disabled"; + }; + + snvs: snvs@40230000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x40230000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = ; + clock-names = "snvs-rtc"; + clocks = <&clks IMX7ULP_CLK_SNVS>; + }; + }; + + pwm0: tpm@40250000 { + compatible = "nxp,tpm-pwm"; + reg = <0x40250000 0x1000>; + nxp,pwm-number = <6>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + clocks = <&clks IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <2>; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPTPM5>; + }; + + lpit: 1@40270000 { + compatible = "fsl,imx-lpit"; + reg = <0x40270000 0x1000>; + interrupts = ; + /* clocks = <&lpclk>;*/ + clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-rates = <48000000>; + assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + }; + + lpi2c4: lpi2c4@402B0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402B0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: lpi2c5@402C0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402C0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + }; + + lpspi2: lpspi@40290000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPSPI2>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi3: lpspi@402A0000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x402A0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPSPI3>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial@402D0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402D0000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402E0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402E0000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 20>, <&edma0 0 19>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + usbotg1: usb@40330000 { + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x40330000 0x200>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_USB0>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@40330200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x40330200 0x200>; + }; + + usbphy1: usbphy@0x40350000 { + compatible = "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x40350000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_USB_PHY>; + nxp,sim = <&sim>; + }; + + usdhc0: usdhc@40370000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + wdog1: wdog@403D0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403D0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + /* + * As the 1KHz LPO clock rate is not trimed,the actually clock + * is about 667Hz, so the init timeout 60s should set 40*1000 + * in the TOVAL register. + */ + timeout-sec = <40>; + }; + + wdog2: wdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + timeout-sec = <40>; + }; + + clks: scg1@403E0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403E0000 0x10000>; + clocks = <&ckil>, <&osc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "ckil", "osc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, + <&clks IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + }; + + pcc2: pcc2@403F0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403F0000 0x10000>; + }; + + pmc1: pmc1@40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + + smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + + }; + + ahbbridge1: ahb-bridge1@40800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: lpi2c6@40A40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: lpi2c7@40A50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@40A60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A60000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 22>, <&edma0 0 21>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart7: serial@40A70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A70000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 24>, <&edma0 0 23>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lcdif: lcdif@40AA0000 { + compatible = "fsl,imx7ulp-lcdif"; + reg = <0x40aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_LCDIF>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "axi", "pix", "disp_axi"; + status = "disabled"; + }; + + mipi_dsi: mipi_dsi@40A90000 { + compatible = "fsl,imx7ulp-mipi-dsi"; + reg = <0x40A90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DSI>; + clock-names = "mipi_dsi_clk"; + data-lanes-num = <2>; + max-data-rate = <800000000>; + sim = <&sim>; + status = "disabled"; + }; + + mmdc: mmdc@40ab0000 { + compatible = "fsl,imx7ulp-mmdc"; + reg = <0x40ab0000 0x4000>; + }; + + pcc3: pcc3@40B30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40B30000 0x10000>; + }; + + iomuxc: iomuxc@4103D000 { + compatible = "fsl,imx7ulp-iomuxc-0"; + reg = <0x4103D000 0x1000>; + fsl,mux_mask = <0xf00>; + status = "disabled"; + }; + + iomuxc1: iomuxc1@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc-1"; + reg = <0x40ac0000 0x1000>; + fsl,mux_mask = <0xf00>; + }; + + gpio0: gpio@40ae0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400F0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio1: gpio@40af0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400F0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio2: gpio@40b00000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400F0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio3: gpio@40b10000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400F00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + + pmc0: pmc0@410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + + sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + + qspi1: qspi@410A5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-qspi"; + reg = <0x410A5000 0x1000>, <0xC0000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + ocotp: ocotp@410a6000 { + compatible = "fsl,imx7ulp-ocotp"; + reg = <0x410a6000 0x4000>; + clocks = <&clks IMX7ULP_CLK_DUMMY>; + }; + + gpu: gpu@41800000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x41800000 0x80000>, <0x41880000 0x80000>, + <0x60000000 0x40000000>, <0x0 0x4000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX7ULP_CLK_GPU3D>, + <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_GPU_DIV>, + <&clks IMX7ULP_CLK_GPU2D>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu2d_axi_clk"; + }; + }; + + heartbeat-rpmsg { + compatible = "fsl,heartbeat-rpmsg"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; +}; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2c13ec696ac541..4cddd8029703a3 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -344,6 +344,7 @@ iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; + fsl,mux_mask = <0x700000>; }; gpio0: gpio@40049000 { diff --git a/arch/arm/configs/boundary_defconfig b/arch/arm/configs/boundary_defconfig new file mode 100644 index 00000000000000..e3901be0acb1d6 --- /dev/null +++ b/arch/arm/configs/boundary_defconfig @@ -0,0 +1,484 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX51=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX7D=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX7D_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=m +CONFIG_NFT_EXTHDR=m +CONFIG_NFT_META=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_M_CAN=y +CONFIG_CAN_MCP251X=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_FTP628=m +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_TUN=m +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_R8169=m +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX88179_178A is not set +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_ATH9K=m +# CONFIG_ATH9K_RFKILL is not set +CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_RTL8192CE=m +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_IMX=m +CONFIG_KEYBOARD_CWC_HOOKSWITCH=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_CR_MULTI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_FT5X06=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_PIC16F616=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_AR1010_UART=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_GPS_MAX7W=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_XR20M117X=m +CONFIG_FSL_OTP=y +CONFIG_HW_RANDOM_IMX_RNG=y +CONFIG_MAGSTRIPE=m +CONFIG_SAS=m +CONFIG_DUMMY_I2C_DEVICE=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=m +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_HS=m +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_ADS1000=m +CONFIG_SENSORS_MAG3110=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MAX77823=y +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_ARIZONA=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_TW686X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_VIDEO_GS2971=m +CONFIG_MXC_HDMI_CSI2_TC358743=m +CONFIG_TC358743_AUDIO=y +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_SUBDEV_OV5640=m +CONFIG_MXC_CAMERA_SUBDEV_OV5642=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_SUBDEV_OV5640_MIPI=m +CONFIG_SOC_CAMERA=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_MIPI_RM68200=y +CONFIG_FB_MXC_TVOUT_ADV739X=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP8860=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_DVI_TFP410=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_WM8960=m +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_WM5102=m +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_HID_MULTITOUCH=m +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_KEYSPAN=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_CC_TUSB320=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_MULTI=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_SIM=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_LM3643=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +# CONFIG_MX3_IPU is not set +CONFIG_STAGING=y +CONFIG_DRM_ANX78XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_COMMON_CLK_PWM=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_ISL28022_ADC=m +CONFIG_TI_ADC081C=m +CONFIG_TI_ADS7924=m +CONFIG_TI_LMP900XX=m +CONFIG_ISL76534=m +CONFIG_APDS9300=m +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_BATTERY_SAMSUNG=y +CONFIG_FUELGAUGE_MAX77823=m +CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING=y +CONFIG_CHARGER_MAX77823=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/bt_defconfig b/arch/arm/configs/bt_defconfig new file mode 100644 index 00000000000000..d3d68d49e090d8 --- /dev/null +++ b/arch/arm/configs/bt_defconfig @@ -0,0 +1,395 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_VLAN_8021Q=y +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_M_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_SST25L=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_R8169=m +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX88179_178A is not set +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_USB_HSO=m +CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m +CONFIG_RTL8192CE=m +CONFIG_WL_TI=y +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CWC_HOOKSWITCH=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_CR_MULTI=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_ILI210X=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_GPS_MAX7W=y +CONFIG_SERIAL_SC16IS7XX=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_MAGSTRIPE=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_TW686X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_VIDEO_GS2971=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_SOC_CAMERA=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_TVOUT_ADV739X=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_KEYSPAN=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_MULTI=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_RV4162=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/imx_v7_cbi_hb_base_defconfig b/arch/arm/configs/imx_v7_cbi_hb_base_defconfig new file mode 100644 index 00000000000000..49b16a088ed62c --- /dev/null +++ b/arch/arm/configs/imx_v7_cbi_hb_base_defconfig @@ -0,0 +1,411 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +CONFIG_CLEANCACHE=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_MXC_USE_VENDOR_DRIVERS=y +CONFIG_MXC_DEBUG_BOARD=y +CONFIG_SOC_IMX6Q=y +# CONFIG_SOC_IMX6SL is not set +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCIE_DW=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_3G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_SUSPEND=y +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_BT=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY +# CONFIG_NET_VENDOR_INTEL +# CONFIG_NET_VENDOR_I825XX +# CONFIG_NET_VENDOR_MARVELL +# CONFIG_NET_VENDOR_MICROCHIP +# CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +# CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +# CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_VELOCITY is not set +# CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_FEC=y +CONFIG_PHYLIB=y +CONFIG_AT803X_PHY=y +CONFIG_WLAN=y +CONFIG_BRCMUTIL=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_SDIO=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL18XX=m +CONFIG_WLCORE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_DMA_CMA=y +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CONNECTOR=y +# CONFIG_MTD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_NETDEVICES=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_MISC=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_FSL_OTP=y +CONFIG_GPIO_MXC=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +CONFIG_VIDEO_V4L2_INT_DEVICE=y +# CONFIG_MEDIA_USB_SUPPORT isnot set +# CONFIG_USB_VIDEO_CLASS is not set +# CONFIG_RADIO_ADAPTERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_OV2640=y +CONFIG_VIVANTE_GALCORE=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +# CONFIG_FB_MX3 is not set +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=m +CONFIG_MXC_ASRC=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_PCF8523=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_SRAM=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_PWM_IMX=y +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_CRYPTODEV=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 +# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +# CONFIG_MXC_MMA8451 is not set +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_LIRC=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_RC5_SZ_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_LIRC_CODEC=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_FINTEK=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_ENE=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_GPIO_CIR=m diff --git a/arch/arm/configs/imx_v7_cbi_hb_defconfig b/arch/arm/configs/imx_v7_cbi_hb_defconfig new file mode 100644 index 00000000000000..8d9fc56a66bc34 --- /dev/null +++ b/arch/arm/configs/imx_v7_cbi_hb_defconfig @@ -0,0 +1,5154 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MMU=y +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +CONFIG_LOCALVERSION="" +CONFIG_CROSS_COMPILE="" +CONFIG_DEFAULT_HOSTNAME="(none)" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_HOTPLUG=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_PREVENT_FIRMWARE_BUILD=y + +CONFIG_BUILD_DOCSRC=y + +# +# General setup +# +CONFIG_KERNEL_LZO=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SWAP=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_COMPILE_TEST is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_SYSCTL=y +# CONFIG_IKCONFIG is not set +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y + +CONFIG_POSIX_MQUEUE=y +CONFIG_PREEMPT_VOLUNTARY=y + +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_DEBUG_ON is not set + +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_IWMC3200TOP is not set +# CONFIG_BLK_DEV_BSG is not set + +# MX6 specific kernel configuration +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_MXC_USE_VENDOR_DRIVERS=y +CONFIG_MXC_DEBUG_BOARD=y +CONFIG_SOC_IMX6Q=y +# CONFIG_SOC_IMX6SL is not set +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCIE_DW=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_3G=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=m +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY +# CONFIG_NET_VENDOR_INTEL +# CONFIG_NET_VENDOR_I825XX +# CONFIG_NET_VENDOR_MARVELL +# CONFIG_NET_VENDOR_MICROCHIP +# CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +# CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +# CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_VELOCITY is not set +# CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_FEC=y +CONFIG_PHYLIB=y +CONFIG_AT803X_PHY=y +CONFIG_WLAN=y +CONFIG_BRCMUTIL=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_SDIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_DMA_CMA=y +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CONNECTOR=y +# CONFIG_MTD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_NETDEVICES=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_MISC=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_FSL_OTP=y +CONFIG_GPIO_MXC=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +CONFIG_VIDEO_V4L2_INT_DEVICE=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +# CONFIG_RADIO_ADAPTERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +# CONFIG_MXC_CAMERA_OV5640 is not set +# CONFIG_MXC_CAMERA_OV5642 is not set +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV5647_MIPI=m +CONFIG_MXC_HDMI_CSI2_TC358743=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_OV2640=y +CONFIG_VIVANTE_GALCORE=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +# CONFIG_FB_MX3 is not set +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=m +CONFIG_MXC_ASRC=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_PCF8523=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_SRAM=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_PWM_IMX=y +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 +# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +# CONFIG_MXC_MMA8451 is not set + +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y + +# +# Loadable module support +# +# CONFIG_MODULE_FORCE_LOAD is not set +# -- MODULE_FORCE_UNLOAD is controlled by config-debug/nodebug + +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HT_IRQ=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_PCIE_ECRC=y +CONFIG_PCIEAER_INJECT=m +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_FAKE=m + +# CONFIG_SGI_IOC4 is not set + +# CONFIG_ISA is not set +# CONFIG_SCx200 is not set + +# +# PCMCIA/CardBus support +# FIXME: Deprecate Cardbus ? +# +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_YENTA=m +CONFIG_CARDBUS=y +CONFIG_I82092=m +CONFIG_PD6729=m + +CONFIG_PCCARD=y +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_DEBUG is not set +# https://lists.fedoraproject.org/pipermail/kernel/2014-February/004889.html +# CONFIG_MMC_CLKGATE is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_ACPI=m +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_WBSD=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_CB710=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_USHC=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_VUB300=m +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set + + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_DEBUG=y +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +# CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING is not set #staging +CONFIG_INFINIBAND_IPATH=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_AMSO1100=m +# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set +CONFIG_INFINIBAND_CXGB3=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +# CONFIG_INFINIBAND_CXGB3_DEBUG is not set +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_NES=m +# CONFIG_INFINIBAND_NES_DEBUG is not set +CONFIG_INFINIBAND_QIB=m +CONFIG_INFINIBAND_QIB_DCA=y +# CONFIG_INFINIBAND_OCRDMA is not set +# CONFIG_INFINIBAND_USNIC is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_SCRIPT=y + +# +# Device Drivers +# + +# CONFIG_COMMON_CLK_SI5351 is not set + +# +# Generic Driver Options +# +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" + +# Give this a try in rawhide for now +# CONFIG_FW_LOADER_USER_HELPER is not set + + + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_TS5500 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# Self-contained MTD device drivers +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# Parallel port support +# +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_PC_PCMCIA=m +CONFIG_PARPORT_1284=y +# CONFIG_PARPORT_AX88796 is not set + +CONFIG_ACPI_PCI_SLOT=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m + +# +# Block devices +# +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_FD=m +# CONFIG_PARIDE is not set +CONFIG_ZRAM=m +# CONFIG_ZRAM_DEBUG is not set +CONFIG_ENHANCEIO=m + +CONFIG_BLK_CPQ_DA=m +CONFIG_BLK_CPQ_CISS_DA=m +CONFIG_CISS_SCSI_TAPE=y +CONFIG_BLK_DEV_DAC960=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_UMEM=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +# Fedora 18 util-linux is the last release that supports cryptoloop devices +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NVME=m +CONFIG_BLK_DEV_SKD=m # 64-bit only but easier to put here +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_IO_TRACE=y + +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_CMDLINE_PARSER is not set + + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RSXX is not set + +CONFIG_SCSI_VIRTIO=m +CONFIG_VIRTIO_BLK=m +CONFIG_VIRTIO_PCI=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_NET=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_VIRTIO_CONSOLE=m +CONFIG_VHOST_NET=m +CONFIG_TCM_VHOST=m +CONFIG_VHOST_SCSI=m + +# +# SCSI device support +# +CONFIG_SCSI=y + +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_SRP=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_TGT=m +CONFIG_SCSI_ISCI=m +CONFIG_SCSI_CHELSIO_FCOE=m + +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_RAID_ATTRS=m + +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m + +# +# SCSI low-level drivers +# +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004102.html +# CONFIG_SCSI_AIC7XXX_OLD is not set +CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=4 +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +# CONFIG_AIC79XX_BUILD_FIRMWARE is not set +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +# CONFIG_SCSI_ADVANSYS is not set +CONFIG_SCSI_BFA_FC=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_ESAS2R=m +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS_LOGGING=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_LOGGING=y + +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFSHCD_PLATFORM is not set + +CONFIG_SCSI_MVUMI=m + +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set + +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_SCSI_PMCRAID=m + +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_PM8001=m +CONFIG_VMWARE_PVSCSI=m +CONFIG_VMWARE_BALLOON=m + +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_FLASHPOINT=y +CONFIG_SCSI_DMX3191D=m +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +CONFIG_SCSI_GDTH=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INIA100=m +# CONFIG_SCSI_PPA is not set +# CONFIG_SCSI_IMM is not set +# CONFIG_SCSI_IZIP_EPP16 is not set +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_DC395x=m +# CONFIG_SCSI_NSP32 is not set +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DC390T=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +# CONFIG_SCSI_DPT_I2O is not set +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set + +# PCMCIA SCSI adapter support +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set + +CONFIG_ATA_BMDMA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_SFF=y +CONFIG_ATA_PIIX=y +# CONFIG_SATA_HIGHBANK is not set +CONFIG_ATA_ACPI=y +CONFIG_BLK_DEV_SX8=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_AHCI=y +CONFIG_SATA_INIC162X=m +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PMP=y +CONFIG_SATA_PROMISE=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_RCAR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_SX4=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_ACARD_AHCI=m + +# CONFIG_PATA_LEGACY is not set +CONFIG_PATA_ACPI=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARASAN_CF=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CS5520=m +CONFIG_PATA_CS5530=m +CONFIG_PATA_CS5535=m +CONFIG_PATA_CS5536=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_ATA_GENERIC=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT821X=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PDC_OLD=m +# CONFIG_PATA_RADISYS is not set +CONFIG_PATA_RDC=m +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +CONFIG_PATA_ATP867X=m + + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_FAULTY=m +CONFIG_MD_LINEAR=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m + +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_EDEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set + +# CONFIG_MULTICORE_RAID456 is not set +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m +CONFIG_DM_DEBUG=y +CONFIG_DM_DELAY=m +CONFIG_DM_MIRROR=y +CONFIG_DM_MULTIPATH=m +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_MQ=m +CONFIG_DM_CACHE_CLEANER=m +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set +# CONFIG_DM_DEBUG_SPACE_MAPS is not set +CONFIG_DM_UEVENT=y +CONFIG_DM_ZERO=y +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_RAID=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_SWITCH=m + +# +# Fusion MPT device support +# +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_MAX_SGE=40 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_LOGGING=y + +# +# IEEE 1394 (FireWire) support (JUJU alternative stack) +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_OHCI_DEBUG=y +CONFIG_FIREWIRE_NOSY=m +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_LCT_NOTIFY_ON_CHANGES is not set + +# +# Virtualization support drivers +# +# CONFIG_VIRT_DRIVERS is not set + +# Networking support +# + +CONFIG_NET_DMA=y + +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=m + +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m + +CONFIG_TCP_MD5SIG=y + +# +# Networking options +# +CONFIG_PACKET_DIAG=m +CONFIG_UNIX_DIAG=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_NF_SECURITY=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y + +# +# IP: Virtual Server Configuration +# +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m + +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_GRE is not set +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y + +CONFIG_RDS=m +# CONFIG_RDS_DEBUG is not set +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m + +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_RDMA=m + +# CONFIG_DECNET is not set +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y + +# PHY timestamping adds overhead +CONFIG_NETWORK_PHY_TIMESTAMPING=y + +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NF_CONNTRACK=m +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_QUEUE_CT=y +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m + +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m + +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_BRIDGE_NETFILTER=y + +# +# IP: Netfilter Configuration +# + +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y # check if contrack(8) in f17 supports netlink +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_IPV6=y +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_NETLINK=m +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_PROTO_UDPLITE=m + +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_RAW=m + +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +# CONFIG_IP6_NF_TARGET_NPT is not set + +# nf_tables support +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=m +CONFIG_NFT_EXTHDR=m +CONFIG_NFT_META=m +CONFIG_NFT_CT=m +CONFIG_NFT_RBTREE=m +CONFIG_NFT_HASH=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_NAT=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m + +CONFIG_NF_TABLES_IPV4=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NF_TABLES_ARP=m + +CONFIG_NF_TABLES_IPV6=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m + +CONFIG_NF_TABLES_BRIDGE=m +# +# Bridge: Netfilter Configuration +# +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_XFRM=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_USER=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_INET6_XFRM_MODE_BEET=m + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IP_SCTP=m +CONFIG_NET_SCTPPROBE=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=m +CONFIG_IP_DCCP=m +CONFIG_IP_DCCP_CCID2=m +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +# CONFIG_IP_DCCP_DEBUG is not set +# CONFIG_NET_DCCPPROBE is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +CONFIG_TIPC=m +CONFIG_TIPC_PORTS=8192 +# CONFIG_TIPC_MEDIA_IB is not set +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set + +CONFIG_NETLABEL=y + +# +# QoS and/or fair queueing +# +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_IND=y +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_U32=m + +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m + +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y + +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=y +CONFIG_OPENVSWITCH_VXLAN=y +CONFIG_VSOCKETS=m + + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_TCPPROBE is not set +CONFIG_NET_DROP_MONITOR=y + +# disable later --kyle + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_DUMMY=m +CONFIG_BONDING=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_VXLAN=m +CONFIG_EQUALIZER=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NLMON=m + +# +# ATM +# +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_BR2684=m +CONFIG_NET_SCH_ATM=m +CONFIG_ATM_TCP=m +# CONFIG_ATM_LANAI is not set +CONFIG_ATM_ENI=m +CONFIG_ATM_FIRESTREAM=m +# CONFIG_ATM_ZATM is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_HORIZON is not set +# CONFIG_ATM_FORE200E is not set +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 + +CONFIG_ATM_HE=m +CONFIG_PPTP=m +CONFIG_PPPOATM=m +CONFIG_PPPOL2TP=m +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_IA is not set +# CONFIG_ATM_CLIP_NO_ICMP is not set +# CONFIG_ATM_MPOA is not set +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +# CONFIG_ATM_ZATM_DEBUG is not set +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +# CONFIG_ATM_HORIZON_DEBUG is not set +# CONFIG_ATM_HE_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_SOLOS=m + +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m + +# CONFIG_CAIF is not set + +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y + + +# +# Ethernet (10 or 100Mbit) +# + +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m + +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set + +CONFIG_NET_VENDOR_AMD=y +CONFIG_PCNET32=m +CONFIG_AMD8111_ETH=m +CONFIG_PCMCIA_NMCLAN=m + +CONFIG_NET_VENDOR_ARC=y +CONFIG_ARC_EMAC=m + +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ALX=m +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +CONFIG_NET_CADENCE=y +CONFIG_ARM_AT91_ETHER=m +CONFIG_MACB=m + +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_CALXEDA_XGMAC=m + +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m + +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m + +CONFIG_NET_VENDOR_DEC=y +# +# Tulip family network device support +# +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_NAPI is not set +# CONFIG_TULIP_MWI is not set +CONFIG_TULIP_MMIO=y +# CONFIG_NI5010 is not set +CONFIG_DE4X5=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_ULI526X=m + +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DE600=m +CONFIG_DE620=m +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set + +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m + +CONFIG_NET_VENDOR_EXAR=y +CONFIG_S2IO=m +CONFIG_VXGE=m +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set + +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGB_DCA=y +CONFIG_IGB_PTP=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBEVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_DCA=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_PTP=y +CONFIG_I40E=m +# CONFIG_I40E_VXLAN is not set +# CONFIG_I40E_DCB is not set +# CONFIG_I40EVF is not set + + +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set + +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KSZ884X_PCI=m +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set + +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_MYRI10GE_DCA=y + +CONFIG_NATSEMI=m +CONFIG_NS83820=m + +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_NE3210=m +CONFIG_PCMCIA_PCNET=m + +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m + +CONFIG_NET_VENDOR_OKI=y +# CONFIG_PCH_GBE is not set +# CONFIG_PCH_PTP is not set + +CONFIG_NET_PACKET_ENGINE=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m + +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLGE=m +CONFIG_NETXEN_NIC=m + +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_ATP=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m + + +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m + + +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m + +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m + +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC9420=m + +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +# CONFIG_STMMAC_DA is not set +# CONFIG_STMMAC_DUAL_MAC is not set +# CONFIG_STMMAC_TIMER is not set +# CONFIG_STMMAC_DEBUG_FS is not set + +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m + +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m + +CONFIG_NET_VENDOR_TI=y +CONFIG_TLAN=m + +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y + +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m + +CONFIG_AMD_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_DP83640_PHY=m +CONFIG_FIXED_PHY=y +CONFIG_MDIO_BITBANG=m +CONFIG_NATIONAL_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_BCM63XX_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LXT_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_VITESSE_PHY=m +CONFIG_MICREL_PHY=m + +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_NET_VENDOR_3COM=y +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_DNET=m + + +CONFIG_LNE390=m +CONFIG_ES3210=m +CONFIG_NET_PCI=y +CONFIG_B44=m +CONFIG_B44_PCI=y +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_CNIC=m +CONFIG_FEALNX=m +CONFIG_NET_POCKET=y + +# +# Ethernet (1000 Mbit) +# +CONFIG_TIGON3=m +CONFIG_JME=m + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IP1000 is not set +# CONFIG_MLX4_EN is not set +# CONFIG_SFC is not set + +# CONFIG_FDDI is not set +# CONFIG_DEFXX is not set +# CONFIG_SKFP is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_IPPP_FILTER=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPPOE=m +CONFIG_PPP_MPPE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +# CONFIG_SLIP_MODE_SLIP6 is not set + +# +# Wireless LAN +# +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_RAYCS is not set + +CONFIG_CFG80211_WEXT=y +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_NL80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_WIRELESS_EXT_SYSFS is not set +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set + +# CONFIG_WIMAX is not set + +# CONFIG_ADM8211 is not set +CONFIG_ATH_COMMON=m +CONFIG_ATH_CARDS=m +CONFIG_ATH5K=m +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH6KL=m +CONFIG_ATH6KL_DEBUG=y +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_AHB=y +# CONFIG_ATH9K_DEBUG is not set +# CONFIG_ATH9K_MAC_DEBUG is not set +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set +# CONFIG_ATH9K_WOW is not set +# +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_ATH10K_DEBUGFS=y +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +# CONFIG_WIL6210_TRACING is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_HWRNG is not set +CONFIG_AT76C50X_USB=m +# CONFIG_AIRO is not set +# CONFIG_AIRO_CS is not set +# CONFIG_ATMEL is not set +CONFIG_B43=m +CONFIG_B43_PCMCIA=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA=y +# CONFIG_B43_BCMA_EXTRA is not set +CONFIG_B43_BCMA_PIO=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_HT=y +# CONFIG_B43_FORCE_PIO is not set +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMSMAC=m +# CONFIG_BRCMFMAC_SDIO_OOB is not set +CONFIG_BRCMFMAC_USB=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMISCAN is not set +# CONFIG_BRCMDBG is not set +CONFIG_HERMES=m +CONFIG_HERMES_CACHE_FW_ON_INIT=y +# CONFIG_HERMES_PRISM is not set +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PLX_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_ORINOCO_USB=m +# CONFIG_TMD_HERMES is not set +# CONFIG_PCMCIA_SPECTRUM is not set +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IPW2100_DEBUG is not set +# CONFIG_IPW2200_DEBUG is not set +# CONFIG_LIBIPW_DEBUG is not set +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEVICE_SVTOOL=y +# CONFIG_IWLWIFI_EXPERIMENTAL_MFP is not set +CONFIG_IWLWIFI_UCODE16=y +# CONFIG_IWLWIFI_P2P is not set +CONFIG_IWLEGACY=m +CONFIG_IWLEGACY_DEBUG=y +# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set +CONFIG_IWL4965=y +CONFIG_IWL3945=m +# CONFIG_IWM is not set +# CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE is not set +CONFIG_MAC80211_HWSIM=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_MWL8K=m +# CONFIG_PRISM54 is not set +# CONFIG_PCMCIA_WL3501 is not set +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2500USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT73USB=m +CONFIG_RTL8180=m +CONFIG_RTL8187=m +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL18XX=m +CONFIG_WLCORE=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set + +CONFIG_WL12XX=m +CONFIG_WL12XX_SPI=m +CONFIG_WL12XX_SDIO=m + +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m + +CONFIG_RTL_CARDS=m +CONFIG_RTLWIFI=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8188EE=m + +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m + +# +# Token Ring devices +# +# CONFIG_TR is not set + +CONFIG_NET_FC=y + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_FMVJ18X=m + +# +# Amateur Radio support +# +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y + +# CONFIG_CAN is not set + +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_EPP=m +CONFIG_YAM=m + +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_LLCP=y +CONFIG_NFC_SIM=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m + +# +# Near Field Communication (NFC) devices +# +CONFIG_NFC_PORT100=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m + +# +# IrDA (infrared) support +# +CONFIG_IRDA=m +# CONFIG_IRDA_DEBUG is not set +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +CONFIG_IRTTY_SIR=m +CONFIG_DONGLE=y +CONFIG_ACTISYS_DONGLE=m +CONFIG_ACT200L_DONGLE=m +CONFIG_ESI_DONGLE=m +CONFIG_GIRBIL_DONGLE=m +CONFIG_KINGSUN_DONGLE=m +CONFIG_KSDAZZLE_DONGLE=m +CONFIG_KS959_DONGLE=m +CONFIG_LITELINK_DONGLE=m +CONFIG_MA600_DONGLE=m +CONFIG_MCP2120_DONGLE=m +CONFIG_OLD_BELKIN_DONGLE=m +CONFIG_TEKRAM_DONGLE=m +CONFIG_TOIM3232_DONGLE=m + +CONFIG_ALI_FIR=m +CONFIG_MCS_FIR=m +CONFIG_NSC_FIR=m +CONFIG_SIGMATEL_FIR=m +CONFIG_SMC_IRCC_FIR=m +# CONFIG_TOSHIBA_FIR is not set +CONFIG_USB_IRDA=m +CONFIG_VLSI_FIR=m +CONFIG_VIA_FIR=m +CONFIG_WINBOND_FIR=m + +# +# Bluetooth support +# +CONFIG_BT=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_CMTP=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +# Disable the BT_HCIUSB driver. +# It sucks more power than BT_HCIBTUSB which has the same functionality. +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBTUART=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_WILINK=m + +# +# ISDN subsystem +# +CONFIG_ISDN=y +CONFIG_MISDN=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_L1OIP=m +CONFIG_MISDN_AVMFRITZ=m +CONFIG_MISDN_SPEEDFAX=m +CONFIG_MISDN_INFINEON=m +CONFIG_MISDN_W6692=m +CONFIG_MISDN_NETJET=m + +# +# mISDN hardware drivers +# +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_ISDN_I4L=m +CONFIG_ISDN_DRV_AVMB1_B1PCI=m +CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m +CONFIG_ISDN_DRV_AVMB1_T1PCI=m +CONFIG_ISDN_DRV_AVMB1_C4=m + +CONFIG_MISDN_HFCUSB=m + +CONFIG_ISDN_PPP=y +CONFIG_ISDN_PPP_VJ=y +CONFIG_ISDN_MPP=y +# CONFIG_ISDN_PPP_BSDCOMP is not set +CONFIG_ISDN_TTY_FAX=y +CONFIG_DE_AOC=y + +CONFIG_ISDN_AUDIO=y + +CONFIG_ISDN_DRV_HISAX=m +CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y +CONFIG_ISDN_DRV_AVMB1_AVM_CS=m + +CONFIG_ISDN_CAPI_CAPIDRV=m +CONFIG_ISDN_DIVERSION=m + +CONFIG_HISAX_EURO=y +CONFIG_HISAX_1TR6=y +CONFIG_HISAX_NI1=y +CONFIG_HISAX_MAX_CARDS=8 +CONFIG_HISAX_16_3=y +CONFIG_HISAX_TELESPCI=y +CONFIG_HISAX_S0BOX=y +CONFIG_HISAX_FRITZPCI=y +CONFIG_HISAX_AVM_A1_PCMCIA=y +CONFIG_HISAX_ELSA=y +CONFIG_HISAX_DIEHLDIVA=y +CONFIG_HISAX_SEDLBAUER=y +CONFIG_HISAX_NETJET=y +CONFIG_HISAX_NETJET_U=y +CONFIG_HISAX_NICCY=y +CONFIG_HISAX_BKM_A4T=y +CONFIG_HISAX_SCT_QUADRO=y +CONFIG_HISAX_GAZEL=y +CONFIG_HISAX_HFC_PCI=y +CONFIG_HISAX_W6692=y +CONFIG_HISAX_HFC_SX=y +CONFIG_HISAX_ENTERNOW_PCI=y +# CONFIG_HISAX_DEBUG is not set +CONFIG_HISAX_AVM_A1_CS=m +CONFIG_HISAX_ST5481=m +# CONFIG_HISAX_HFCUSB is not set +CONFIG_HISAX_FRITZ_PCIPNP=m +CONFIG_HISAX_NO_SENDCOMPLETE=y +CONFIG_HISAX_NO_LLC=y +CONFIG_HISAX_NO_KEYPAD=y +CONFIG_HISAX_SEDLBAUER_CS=m +CONFIG_HISAX_ELSA_CS=m +CONFIG_HISAX_TELES_CS=m +CONFIG_HISAX_HFC4S8S=m + +CONFIG_ISDN_DRV_LOOP=m +CONFIG_HYSDN=m +CONFIG_HYSDN_CAPI=y + + +# +# CAPI subsystem +# +CONFIG_ISDN_CAPI=m +# CONFIG_CAPI_TRACE is not set +CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y +CONFIG_ISDN_CAPI_MIDDLEWARE=y +CONFIG_ISDN_CAPI_CAPI20=m + +# +# CAPI hardware drivers +# + +# +# Active AVM cards +# +CONFIG_CAPI_AVM=y + +# +# Active Eicon DIVA Server cards +# +# CONFIG_CAPI_EICON is not set +CONFIG_ISDN_DIVAS=m +CONFIG_ISDN_DIVAS_BRIPCI=y +CONFIG_ISDN_DIVAS_PRIPCI=y +CONFIG_ISDN_DIVAS_DIVACAPI=m +CONFIG_ISDN_DIVAS_USERIDI=m +CONFIG_ISDN_DIVAS_MAINT=m + +CONFIG_ISDN_DRV_GIGASET=m +CONFIG_GIGASET_CAPI=y +CONFIG_GIGASET_BASE=m +CONFIG_GIGASET_M101=m +CONFIG_GIGASET_M105=m +# CONFIG_GIGASET_DEBUG is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=m + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +# CONFIG_INPUT_MATRIXKMAP is not set + +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_WACOM=m + +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_POLLDEV=m +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_IMS_PCU is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m + +# +# Input I/O drivers +# +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_APBPS2 is not set + +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_CYAPA=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_ZHENHUA=m +# CONFIG_JOYSTICK_AS5011 is not set + +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_UCB1400=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +# CONFIG_TOUCHSCREEN_WM97XX is not set +CONFIG_TOUCHSCREEN_W90X900=m +# CONFIG_TOUCHSCREEN_BU21013 is not set +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_MAX11801 is not set +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m +CONFIG_TOUCHSCREEN_ZFORCE=m + +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_RETU_PWRBUTTON=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_WISTRON_BTNS=m +CONFIG_INPUT_ATLAS_BTNS=m + +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m + +CONFIG_MAC_EMUMOUSEBTN=y + +CONFIG_INPUT_WM831X_ON=m + + +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_PCF8574 is not set +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MPU3050=m +CONFIG_INPUT_KXTJ9=m +# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_ROCKETPORT=m +CONFIG_SYNCLINK=m +CONFIG_SYNCLINKMP=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_N_GSM=m +# CONFIG_TRACE_SINK is not set +# CONFIG_STALDRV is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS=m +# CONFIG_TCG_TIS_I2C_INFINEON is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +CONFIG_TCG_NSC=m +CONFIG_TCG_ATMEL=m +# CONFIG_TCG_INFINEON is not set +# CONFIG_TCG_ST33_I2C is not set +# CONFIG_TCG_XEN is not set +CONFIG_TELCLOCK=m + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set +CONFIG_CYCLADES=m +# CONFIG_CYZ_INTR is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_RIO is not set +CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_MFD_HSU is not set + +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_PCH_UART is not set + +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_PRINTER=m +CONFIG_LP_CONSOLE=y +CONFIG_PPDEV=m + +# +# I2C support +# +CONFIG_I2C=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# + +# +# I2C Algorithms +# +# CONFIG_I2C_DEBUG_ALGO is not set +CONFIG_I2C_ALGOBIT=m + +# +# I2C Hardware Bus support +# + +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD756_S4882 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_NFORCE2_S4985 is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_VIPERBOARD=m + +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_93CX6=m +CONFIG_EEPROM_MAX6875=m + +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +CONFIG_I2C_PASEMI=m +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PIIX4 is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_STUB=m +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_XILINX is not set + +CONFIG_I2C_DIOLAN_U2C=m + +# +# I2C Hardware Sensors Chip support +# +CONFIG_SENSORS_ATK0110=m +CONFIG_SENSORS_ABITUGURU=m +CONFIG_SENSORS_ABITUGURU3=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_APPLESMC=m +CONFIG_SENSORS_ASB100=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_DS1621=m +# CONFIG_DS1682 is not set +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FSCHMD=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_HDAPS=m +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# FIXME: IBMAEM x86 only? +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_SPI=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SIS5595=m +CONFIG_CHARGER_SMB347=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP401=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29020=m +CONFIG_ISL29003=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VIA_CPUTEMP=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_WM8350=m +CONFIG_SENSORS_WM831X=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_ADS1015=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_EMC6W201=m + +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m + +# Industrial I/O subsystem configuration +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +# CONFIG_IIO_KFIFO_BUF is not set +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +CONFIG_HID_SENSOR_ENUM_BASE_QUIRKS=y +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5064 is not set +# CONFIG_BMA180 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX517 is not set +# CONFIG_MCP4725 is not set +# CONFIG_ITG3200 is not set +# CONFIG_APDS9300 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set +# CONFIG_TCS3472 is not set +# CONFIG_TSL4531 is not set +# CONFIG_NAU7802 is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_EXYNOS_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +# CONFIG_INV_MPU6050_IIO is not set +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +# CONFIG_ADJD_S311 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_VCNL4000 is not set +# CONFIG_AK8975 is not set +# CONFIG_MAG3110 is not set +# CONFIG_TMP006 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_KXSD9 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_AD8366 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD9523 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_DHT11 is not set +# CONFIG_MPL3115 is not set + +# staging IIO drivers +# CONFIG_AD7291 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_ADT7316 is not set +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set +# CONFIG_AD5933 is not set +# CONFIG_ADE7854 is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_HMC5843 is not set +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_SCA3000 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set +# CONFIG_ADIS16060 is not set +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + + + +# CONFIG_HMC6352 is not set +# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set + +CONFIG_W1=m +CONFIG_W1_CON=y +# CONFIG_W1_MASTER_MATROX is not set +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_HDQ_MASTER_OMAP is not set +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_BQ27000=m + +# +# Mice +# + +# +# IPMI +# +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_POWEROFF=m + +# +# Watchdog Cards +# +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_SOFT_WATCHDOG=m +CONFIG_WDTPCI=m +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +CONFIG_IB700_WDT=m +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +CONFIG_W83877F_WDT=m +CONFIG_W83627HF_WDT=m +CONFIG_MACHZ_WDT=m +# CONFIG_SC520_WDT is not set +CONFIG_ALIM7101_WDT=m +CONFIG_ALIM1535_WDT=m +CONFIG_IT87_WDT=m +CONFIG_ITCO_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +# CONFIG_SC1200_WDT is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set +CONFIG_I6300ESB_WDT=m +CONFIG_IT8712F_WDT=m +# CONFIG_SBC8360_WDT is not set +# CONFIG_SBC7240_WDT is not set +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_W83977F_WDT=m +CONFIG_PCIPCWATCHDOG=m +CONFIG_USBPCWATCHDOG=m +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +CONFIG_WM8350_WATCHDOG=m +CONFIG_WM831X_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_W83697UG_WDT=m +# CONFIG_MEN_A21_WDT is not set +# CONFIG_GPIO_WATCHDOG is not set + +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=m +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_RTC_DEBUG is not set +# CONFIG_GEN_RTC is not set +CONFIG_RTC_HCTOSYS=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS1374=m +# CONFIG_RTC_DRV_EP93XX is not set +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MAX6900=m +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_SA1100 is not set +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_V3020=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_S35390A is not set +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_BQ4802=m +CONFIG_RTC_DRV_WM8350=m +# CONFIG_RTC_DRV_AB3100 is not set +CONFIG_RTC_DRV_WM831X=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_PCF50633=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_MOXART is not set +# CONFIG_RTC_DRV_ISL12057 is not set + +CONFIG_R3964=m +# CONFIG_APPLICOM is not set +# CONFIG_SONYPI is not set + +# +# Ftape, the floppy tape device driver +# +CONFIG_AGP=y +CONFIG_AGP_ALI=y +CONFIG_AGP_ATI=y +CONFIG_AGP_AMD=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +CONFIG_AGP_NVIDIA=y +CONFIG_AGP_SIS=y +CONFIG_AGP_SWORKS=y +CONFIG_AGP_VIA=y +CONFIG_AGP_EFFICEON=y + +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 + +# CONFIG_STUB_POULSBO is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set + +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m + +CONFIG_MWAVE=m +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +CONFIG_HANGCHECK_TIMER=m + +CONFIG_MEDIA_PCI_SUPPORT=y +# +# Multimedia devices +# +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=m +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_USB_SI4713 is not set +# CONFIG_PLATFORM_SI4713 is not set +# CONFIG_I2C_SI4713 is not set +# CONFIG_USB_RAREMONO is not set + +# +# Video For Linux +# + +# +# Video Adapters +# +CONFIG_V4L_USB_DRIVERS=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +CONFIG_V4L_PCI_DRIVERS=y +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_BT848=m +CONFIG_VIDEO_BT848_DVB=y +CONFIG_VIDEO_BWQCAM=m +CONFIG_VIDEO_SR030PC30=m +CONFIG_VIDEO_NOON010PC30=m +CONFIG_VIDEO_CAFE_CCIC=m +# CONFIG_VIDEO_CPIA is not set +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_CQCAM=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_IVTV=m +# CONFIG_VIDEO_IVTV_ALSA is not set +CONFIG_VIDEO_MEYE=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PMS is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_SAA6588=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_STK1160_AC97=y +CONFIG_VIDEO_W9966=m +CONFIG_VIDEO_ZORAN=m +CONFIG_VIDEO_ZORAN_AVS6EYES=m +CONFIG_VIDEO_ZORAN_BUZ=m +CONFIG_VIDEO_ZORAN_DC10=m +CONFIG_VIDEO_ZORAN_DC30=m +CONFIG_VIDEO_ZORAN_LML33=m +CONFIG_VIDEO_ZORAN_LML33R10=m +CONFIG_VIDEO_ZORAN_ZR36060=m +# CONFIG_V4L_ISA_PARPORT_DRIVERS is not set +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_SAA7164=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_USBTV=m + +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y + +# +# Radio Adapters +# +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_WL1273=m + +CONFIG_MEDIA_ATTACH=y + +# +# V4L/DVB tuners +# Selected automatically by not setting CONFIG_MEDIA_TUNER_CUSTOMISE +# +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set + +# +# Digital Video Broadcasting Devices +# +CONFIG_DVB_CAPTURE_DRIVERS=y +CONFIG_DVB_CORE=m +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y + +# +# DVB frontends +# Selected automatically by not setting CONFIG_DVB_FE_CUSTOMISE +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# Supported DVB bridge Modules +# +CONFIG_DVB_BT8XX=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_PLUTO2=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_SMS_USB_DRV=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_FRIIO=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_IT913X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m + +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_PATCH=m + +CONFIG_DVB_TTUSB_BUDGET=m + +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_B2C2_FLEXCOP=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set + +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_AF9035=m + +CONFIG_DVB_PT1=m + +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m + +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_BTCX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set + +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_LIRC=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_RC5_SZ_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_LIRC_CODEC=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_FINTEK=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_ENE=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_GPIO_CIR=m + +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_SH_VEU is not set +# CONFIG_VIDEO_RENESAS_VSP1 is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set + +# +# Broadcom Crystal HD video decoder driver +# +CONFIG_CRYSTALHD=m + +# +# Graphics support +# + +CONFIG_DISPLAY_SUPPORT=m +CONFIG_VIDEO_OUTPUT_CONTROL=m + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y + +# +# Logo configuration +# +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# + +# +# Advanced Linux Sound Architecture +# +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_RTCTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set + +# +# Generic devices +# +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 + +CONFIG_SND_DRIVERS=y + +# +# ISA devices +# +CONFIG_SND_AD1889=m + +# +# PCI devices +# +CONFIG_SND_PCI=y +CONFIG_SND_ALI5451=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +# CONFIG_SND_AW2 is not set +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CS4281=m +CONFIG_SND_CS5530=m +CONFIG_SND_CS5535AUDIO=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_CTXFI=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_HDA_INTEL=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_INPUT_JACK=y +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_CODEC_REALTEK=y +CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y +CONFIG_SND_HDA_CODEC_CA0110=y +CONFIG_SND_HDA_CODEC_ANALOG=y +CONFIG_SND_HDA_CODEC_SIGMATEL=y +CONFIG_SND_HDA_CODEC_VIA=y +CONFIG_SND_HDA_CODEC_CIRRUS=y +CONFIG_SND_HDA_CODEC_CONEXANT=y +CONFIG_SND_HDA_CODEC_CMEDIA=y +CONFIG_SND_HDA_CODEC_SI3054=y +CONFIG_SND_HDA_CODEC_HDMI=y +CONFIG_SND_HDA_I915=y +CONFIG_SND_HDA_CODEC_CA0132=y +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_GENERIC=y +CONFIG_SND_HDA_POWER_SAVE=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_PREALLOC_SIZE=4096 +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=y +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_RME32=m +CONFIG_SND_PCSP=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SIS7019=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_HDSP=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_ASIHPI=m +CONFIG_SND_LOLA=m + +# +# ALSA USB devices +# +CONFIG_SND_USB=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_US122L=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m + +# +# PCMCIA devices +# +# CONFIG_SND_PCMCIA is not set + +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_SPEAKERS=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_SCS1X=m +CONFIG_SND_DICE=m + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# USB support +# +CONFIG_USB_SUPPORT=y +# CONFIG_USB_DEBUG is not set + +# DEPRECATED: See bug 362221. Fix udev. +# CONFIG_USB_DEVICE_CLASS is not set + + +# +# Miscellaneous USB options +# + +# Deprecated. +# CONFIG_USB_DEVICEFS is not set + +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_MV is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_ISP1362_HCD=m +CONFIG_USB_FUSBH200_HCD=m +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_GR_UDC is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +# CONFIG_USB_SL811_CS is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_HCD_DEBUGGING is not set + +# +# USB Device Class drivers +# + +# +# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m +# CONFIG_BLK_DEV_UB is not set +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_ENE_UB6250=m +# CONFIG_USB_LIBUSUAL is not set +# CONFIG_USB_UAS is not set + + +# +# USB Human Interface Devices (HID) +# +CONFIG_USB_HID=y + +CONFIG_HID_SUPPORT=y + +CONFIG_HID=y +CONFIG_I2C_HID=m +CONFIG_HID_BATTERY_STRENGTH=y +# debugging default is y upstream now +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_PID=y +CONFIG_LOGITECH_FF=y +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGIWII_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_PANTHERLORD_FF=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +CONFIG_HID_WACOM_POWER_SUPPLY=y +CONFIG_ZEROPLUS_FF=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_IDMOUSE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_GREENASIA_FF=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=y +CONFIG_HID_QUANTA=y +CONFIG_HID_PRIMAX=m +CONFIG_HID_PS3REMOTE=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_ROCCAT_KONE=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SUNPLUS=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_ROCCAT_PYRA=m +CONFIG_HID_ROCCAT_KONEPLUS=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO_TPKBD=m +CONFIG_HID_ROCCAT_ARVO=m +CONFIG_HID_ROCCAT_ISKU=m +CONFIG_HID_ROCCAT_KOVAPLUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_HUION=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WIIMOTE_EXT=y +CONFIG_HID_KYE=m +CONFIG_HID_SAITEK=m +CONFIG_HID_TIVO=m +CONFIG_HID_GENERIC=y +CONFIG_HID_AUREAL=m +CONFIG_HID_APPLEIR=m + + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m + +# +# USB Multimedia devices +# + +CONFIG_USB_DSBR=m +# CONFIG_USB_ET61X251 is not set +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_SE401=m + +CONFIG_USB_S2255=m +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set +# CONFIG_USB_SN9C102 is not set +CONFIG_USB_ZR364XX=m + +# +# USB Network adaptors +# +CONFIG_USB_CATC=m +CONFIG_USB_HSO=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_USBNET=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m + +# +# USB Host-to-Host Cables +# +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y + +# +# Intelligent USB Devices/Gadgets +# +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y + +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m + +# +# USB Serial Converter support +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +# CONFIG_USB_SERIAL_F81232 is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_ZTE is not set +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MOTOROLA=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_QUATECH2 is not set +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIEMENS_MPI=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_FLASHLOADER=m +CONFIG_USB_SERIAL_SUUNTO=m +CONFIG_USB_SERIAL_CONSOLE=y + +CONFIG_USB_EZUSB=y +CONFIG_USB_EMI62=m +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set + +# +# USB Miscellaneous drivers +# + +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_APPLEDISPLAY=m + +# Physical Layer USB driver +# CONFIG_USB_OTG_FSM is not set + +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set +# CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_OMAP_USB2 is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USBPHY is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_USB_RCAR_PHY=m +CONFIG_USB_ATM=m +CONFIG_USB_CXACRU=m +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_EMI26=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_MON=y +CONFIG_USB_PWC=m +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_USB_PWC_DEBUG is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_RADIO_SI470X=y +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_RADIO_SI4713=m +# CONFIG_RADIO_TEF6862 is not set +CONFIG_USB_MR800=m +CONFIG_USB_STKWEBCAM=m +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# CONFIG_USB_DWC2 is not set + +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# CONFIG_USB_ISP1301 is not set + +# CONFIG_USB_OTG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_PCMCIAHOST=y +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y + +# Multifunction USB devices +# CONFIG_MFD_PCF50633 is not set +CONFIG_PCF50633_ADC=m +CONFIG_PCF50633_GPIO=m +# CONFIG_AB3100_CORE is not set +CONFIG_INPUT_PCF50633_PMU=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m + +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_VX855=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_RTSX_PCI=m +# CONFIG_MFD_TI_AM335X_TSCADC is not set +CONFIG_MFD_VIPERBOARD=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8350 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_AB3100_OTP is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_LPC_SCH is not set +# CONFIG_LPC_ICH is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_TPS6507X is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_ARIZONA is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_LP3943 is not set + +# +# File systems +# +CONFIG_MISC_FILESYSTEMS=y + +# ext4 is used for ext2 and ext3 filesystems +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_XFS_FS=m +# CONFIG_XFS_DEBUG is not set +# CONFIG_XFS_RT is not set +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_MINIX_FS=m +CONFIG_ROMFS_FS=m +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_DNOTIFY=y +# Autofsv3 is obsolete. +# systemd is dependant upon AUTOFS, so build it in. +# CONFIG_EXOFS_FS is not set +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NILFS2_FS=m +# CONFIG_LOGFS is not set +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_BLK_DEV_RBD=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set + +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_FSCACHE_OBJECT_LIST=y + +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +# CONFIG_DEBUG_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set + +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +# CONFIG_OMFS_FS is not set +CONFIG_CUSE=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set + + +# +# Network File Systems +# +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_2=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_PNFS_OBJLAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUNRPC_DEBUG=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_SMB2=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS_ACL=y +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_NFSD_EXPORT=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_SMALLDOS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +# CONFIG_AF_RXRPC is not set + +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +# CONFIG_OCFS2_FS_STATS is not set + +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# Maybe see if we want this on for debug kernels? +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set + +CONFIG_CONFIGFS_FS=y + +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y + + +CONFIG_UBIFS_FS_XATTR=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +# CONFIG_UBIFS_FS_DEBUG is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_AIX_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_BSD_DISKLABEL=y +CONFIG_EFI_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SUN_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set + +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m + +# +# Profiling support +# +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_OPROFILE_EVENT_MULTIPLEX=y + +# +# Kernel hacking +# +CONFIG_DEBUG_KERNEL=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +# CONFIG_DEBUG_INFO is not set +CONFIG_FRAME_POINTER=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_DEBUG_DRIVER is not set +CONFIG_HEADERS_CHECK=y +# CONFIG_LKDTM is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_READABLE_ASM is not set + +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set + +# DEBUG options that don't get enabled/disabled with 'make debug/release' + +# This generates a huge amount of dmesg spew +# CONFIG_DEBUG_KOBJECT is not set +# +# This breaks booting until the module patches are in-tree +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +# +# +# These debug options are deliberatly left on (even in 'make release' kernels). +# They aren't that much of a performance impact, and the value +# from getting useful bug-reports makes it worth leaving them on. +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DEBUG_DEVRES=y +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_DEBUG_NX_TEST=m +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_DEBUG_BOOT_PARAMS=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +CONFIG_EARLY_PRINTK_DBGP=y +# CONFIG_PAGE_POISONING is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_CRASH is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_RAMOOPS is not set + + +# +# Security options +# +CONFIG_SECURITY=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +# CONFIG_SECURITY_PATH is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_SECURITY_SELINUX_AVC_STATS=y +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_YAMA is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004125.html +CONFIG_AUDIT_LOGINUID_IMMUTABLE=y + +CONFIG_SECCOMP=y + +# CONFIG_SSBI is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_CRYPTODEV=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_BLKCIPHER=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SALSA20_586=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_CRC32C_INTEL=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_DEV_HIFN_795X=m +CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y +CONFIG_CRYPTO_PCRYPT=m + + + +# Random number generation + +# +# Library routines +# +CONFIG_CRC16=y +CONFIG_CRC32=m +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC8=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_CORDIC=m +# CONFIG_DDR is not set + +CONFIG_CRYPTO_ZLIB=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m + +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_XZ=y +CONFIG_KEYS=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_BIG_KEYS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set + +CONFIG_ATA_OVER_ETH=m +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=m +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PROGEAR=m + +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_PLATFORM=m + +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y + +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set + +CONFIG_PRINTK_TIME=y + +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set + +CONFIG_KEXEC=y + +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_EMULATION is not set + +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y + +# +# Bus devices +# +# CONFIG_OMAP_OCP2SCP is not set +CONFIG_PROC_EVENTS=y + +CONFIG_IBMASR=m + +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_DPM_WATCHDOG is not set # revisit this in debug +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +# CONFIG_PM_OPP is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +# CONFIG_HIBERNATION is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_SUSPEND=y + +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y + + +CONFIG_NET_VENDOR_SMC=y +# CONFIG_IBMTR is not set +# CONFIG_SKISA is not set +# CONFIG_PROTEON is not set +# CONFIG_SMCTR is not set + +# CONFIG_MOUSE_ATIXL is not set + +# CONFIG_MEDIA_PARPORT_SUPPORT is not set + +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_CADET=m +CONFIG_RADIO_RTRACK=m +CONFIG_RADIO_RTRACK2=m +CONFIG_RADIO_AZTECH=m +CONFIG_RADIO_GEMTEK=m +CONFIG_RADIO_SF16FMI=m +CONFIG_RADIO_SF16FMR2=m +CONFIG_RADIO_TERRATEC=m +CONFIG_RADIO_TRUST=m +CONFIG_RADIO_TYPHOON=m +CONFIG_RADIO_ZOLTRIX=m + +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m + +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_BOUNCE=y +# CONFIG_LEDS_AMS_DELTA is not set +# CONFIG_LEDS_LOCOMO is not set +# CONFIG_LEDS_NET48XX is not set +# CONFIG_LEDS_NET5501 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_S3C24XX is not set +# CONFIG_LEDS_PCA9633 is not set +CONFIG_LEDS_DELL_NETBOOKS=m +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA9685 is not set +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_ALIX2=m +CONFIG_LEDS_CLEVO_MAIL=m +CONFIG_LEDS_INTEL_SS4200=m +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3642 is not set +CONFIG_LEDS_LM3556=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_REGULATOR=m +CONFIG_LEDS_WM8350=m +CONFIG_LEDS_WM831X_STATUS=m + +CONFIG_DMA_ENGINE=y +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_DMAC_BIG_ENDIAN_IO is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_DMATEST is not set +CONFIG_ASYNC_TX_DMA=y + +CONFIG_UNUSED_SYMBOLS=y + +CONFIG_UPROBE_EVENT=y + +CONFIG_DYNAMIC_FTRACE=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_FTRACE_SYSCALLS=y +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_FUNCTION_PROFILER=y +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_STACK_TRACER=y +# CONFIG_FUNCTION_GRAPH_TRACER is not set + +CONFIG_KPROBES=y +CONFIG_KPROBE_EVENT=y +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_OPTPROBES=y + +CONFIG_HZ_1000=y + +CONFIG_TIMER_STATS=y +CONFIG_PERF_COUNTERS=y + +# Auxillary displays +CONFIG_KS0108=m +CONFIG_KS0108_PORT=0x378 +CONFIG_KS0108_DELAY=2 +CONFIG_CFAG12864B=y +CONFIG_CFAG12864B_RATE=20 + +# CONFIG_PHANTOM is not set + +# CONFIG_POWER_SUPPLY_DEBUG is not set + +# CONFIG_TEST_POWER is not set +CONFIG_APM_POWER=m +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_WM831X_POWER is not set + +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ20Z75 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_GOLDFISH is not set + +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_PCF50633 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24735 is not set +CONFIG_POWER_RESET=y + +# CONFIG_PDA_POWER is not set + +CONFIG_AUXDISPLAY=y + +CONFIG_UIO=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_DMEM_GENIRQ is not set +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set + +CONFIG_VFIO=m +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_PCI=m + + +# LIRC +CONFIG_LIRC_STAGING=y +CONFIG_LIRC_BT829=m +CONFIG_LIRC_IGORPLUGUSB=m +CONFIG_LIRC_IMON=m +CONFIG_LIRC_ZILOG=m +CONFIG_LIRC_PARALLEL=m +CONFIG_LIRC_SERIAL=m +CONFIG_LIRC_SERIAL_TRANSMITTER=y +CONFIG_LIRC_SASEM=m +CONFIG_LIRC_SIR=m +CONFIG_LIRC_TTUSBIR=m + +# CONFIG_SAMPLES is not set + + +CONFIG_NOZOMI=m +# CONFIG_TPS65010 is not set + +CONFIG_INPUT_APANEL=m +CONFIG_INPUT_GP2A=m +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_GPIO_BEEPER is not set + +# CONFIG_INTEL_MENLOW is not set +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_IPWIRELESS=m + +# CONFIG_BLK_DEV_XIP is not set +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m + +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# CONFIG_HTC_PASIC3 is not set + +# MT9V022_PCA9536_SWITCH is not set + +CONFIG_OPTIMIZE_INLINING=y + +# FIXME: This should be x86/ia64 only +# CONFIG_HP_ILO is not set + +CONFIG_GPIOLIB=y +# CONFIG_PINCTRL is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINMUX is not set +# CONFIG_PINCONF is not set + +CONFIG_NET_DSA=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MV88E6131=m +CONFIG_NET_DSA_MV88E6123_61_65=m + +# Used by Maemo, we don't care. +# CONFIG_PHONET is not set + +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set + +# CONFIG_C2PORT is not set + +# CONFIG_REGULATOR_DEBUG is not set + +CONFIG_WM8350_POWER=m + +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set + +CONFIG_USB_WUSB=m +CONFIG_USB_WUSB_CBAF=m +# CONFIG_USB_WUSB_CBAF_DEBUG is not set +CONFIG_USB_WHCI_HCD=m +CONFIG_USB_HWA_HCD=m +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set + +CONFIG_UWB=m +CONFIG_UWB_HWA=m +CONFIG_UWB_WHCI=m +CONFIG_UWB_I1480U=m + +# CONFIG_ANDROID is not set +CONFIG_STAGING_MEDIA=y +# CONFIG_DVB_AS102 is not set +# CONFIG_ET131X is not set +# CONFIG_SLICOSS is not set +# CONFIG_WLAGS49_H2 is not set +# CONFIG_WLAGS49_H25 is not set +# CONFIG_VIDEO_DT3155 is not set +# CONFIG_TI_ST is not set +# CONFIG_FB_XGI is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_I2C_BCM2048 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_OMAP4 is not set +# CONFIG_USB_MSI3101 is not set +# CONFIG_DT3155 is not set +# CONFIG_W35UND is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +CONFIG_USB_ATMEL=m +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_PANEL is not set +# CONFIG_TRANZPORT is not set +# CONFIG_POHMELFS is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_LINE6_USB is not set +# CONFIG_VME_BUS is not set +# CONFIG_RAR_REGISTER is not set +# CONFIG_VT6656 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# Larry Finger maintains these (rhbz 913753) +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +# CONFIG_INPUT_GPIO is not set +# CONFIG_VIDEO_CX25821 is not set +# CONFIG_R8187SE is not set +# CONFIG_R8188EU is not set +# CONFIG_R8821AE is not set +# CONFIG_RTL8192U is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_SPECTRA is not set +# CONFIG_EASYCAP is not set +# CONFIG_SOLO6X10 is not set +# CONFIG_ACPI_QUICKSTART is not set +# CONFIG_LTE_GDM724X is not set +CONFIG_R8712U=m # Larry Finger maintains this (rhbz 699618) +# CONFIG_R8712_AP is not set +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_USB_BTMTK is not set +# CONFIG_FT1000 is not set +# CONFIG_SPEAKUP is not set +# CONFIG_DX_SEP is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_RTS_PSTOR is not set +CONFIG_ALTERA_STAPL=m +# CONFIG_DVB_CXD2099 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_ZCACHE is not set +# CONFIG_RTS5139 is not set +# CONFIG_NVEC_LEDS is not set +# CONFIG_VT6655 is not set +# CONFIG_RAMSTER is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_IPACK_BUS is not set +# CONFIG_CSR_WIFI is not set +# CONFIG_ZCACHE2 is not set +# CONFIG_NET_VENDOR_SILICOM is not set +# CONFIG_SBYPASS is not set +# CONFIG_BPCTL is not set +# CONFIG_CED1401 is not set +# CONFIG_DGRP is not set +# CONFIG_SB105X is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_XILLYBUS is not set +# CONFIG_DGAP is not set +# CONFIG_DGNC is not set +# CONFIG_RTS5208 is not set +# END OF STAGING + +# +# Remoteproc drivers (EXPERIMENTAL) +# +# CONFIG_STE_MODEM_RPROC is not set + +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_FCOE_FNIC=m + + +# CONFIG_IMA is not set +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_AUDIT=y +CONFIG_IMA_LSM_RULES=y + +# CONFIG_EVM is not set +# CONFIG_PWM_PCA9685 is not set + +CONFIG_LSM_MMAP_MIN_ADDR=65536 + +CONFIG_STRIP_ASM_SYMS=y + +# CONFIG_RCU_FANOUT_EXACT is not set +# FIXME: Revisit FAST_NO_HZ after it's fixed +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_USER_QS is not set + +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +CONFIG_FSNOTIFY=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y + +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKEHARD=m +CONFIG_IEEE802154_FAKELB=m + +CONFIG_MAC802154=m +CONFIG_NET_MPLS_GSO=m + +# CONFIG_HSR is not set + +# CONFIG_EXTCON is not set +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_MEMORY is not set + +CONFIG_PPS=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_GENERATOR_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_NTP_PPS=y + +CONFIG_PTP_1588_CLOCK=m +CONFIG_PTP_1588_CLOCK_PCH=m + +CONFIG_CLEANCACHE=y +# CONFIG_PGTABLE_MAPPING is not set + +# CONFIG_MDIO_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG SB105x is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VIPERBOARD is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS6105X is not set +# CONFIG_RADIO_MIROPCM20 is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_BCM_KONA is not set +# CONFIG_GPIO_SCH311X is not set +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_SX150X=y +CONFIG_GPIO_ADP5588=m +CONFIG_GPIO_ADNP=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MCP23S08=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_74X164=m + +CONFIG_TEST_KSTRTOX=y + +# CONFIG_POWER_AVS is not set + +CONFIG_TARGET_CORE=m +CONFIG_ISCSI_TARGET=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_SBP_TARGET=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_FC=m + +CONFIG_HWSPINLOCK=m + +CONFIG_PSTORE=y +CONFIG_PSTORE_RAM=m +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_FTRACE is not set + +# CONFIG_TEST_MODULE is not set +# CONFIG_TEST_USER_COPY is not set + +# CONFIG_AVERAGE is not set +# CONFIG_VMXNET3 is not set + +# CONFIG_SIGMA is not set + +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 + +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# CONFIG_GOOGLE_FIRMWARE is not set +# CONFIG_INTEL_MID_PTI is not set + +# CONFIG_MAILBOX is not set + +CONFIG_FMC=m +CONFIG_FMC_FAKEDEV=m +CONFIG_FMC_TRIVIAL=m +CONFIG_FMC_WRITE_EEPROM=m +CONFIG_FMC_CHARDEV=m + +# CONFIG_GENWQE is not set + +# CONFIG_POWERCAP is not set + +# CONFIG_HSI is not set + + +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# CONFIG_MODULE_VERIFY_ELF is not set +# CONFIG_CRYPTO_KEY_TYPE is not set +# CONFIG_PGP_LIBRARY is not set +# CONFIG_PGP_PRELOAD is not set +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_PROC_DEVICETREE=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig new file mode 100644 index 00000000000000..5d6d3d0189b53c --- /dev/null +++ b/arch/arm/configs/imx_v7_defconfig @@ -0,0 +1,455 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6ULL=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX6SLL=y +CONFIG_SOC_IMX7ULP=y +CONFIG_SOC_VF610=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_CMA=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX7D_CPUFREQ=y +CONFIG_ARM_IMX7ULP_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_VLAN_8021Q=y +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_M_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_ATH3K=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_MICREL_PHY=y +CONFIG_USB_KAWETH=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8150=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_CDC_EEM=m +CONFIG_BCMDHD=y +CONFIG_BCMDHD_SDIO=y +CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm/ZP_BCM4339/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcm/ZP_BCM4339/bcmdhd.ZP.OOB.cal" +# CONFIG_RTL_CARDS is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_PF1550_ONKEY=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_ELAN_TS=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_FTS=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_INPUT_MPL3115=y +CONFIG_SENSOR_FXLS8471=y +CONFIG_INPUT_ISL29023=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_HW_RANDOM_IMX_RNG=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_74X164=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_CHARGER_PF1550=y +CONFIG_SABRESD_MAX8903=y +CONFIG_SENSORS_MAX17135=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_PF1550=y +CONFIG_MFD_MAX17135=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PF1550=y +CONFIG_REGULATOR_PF1550_RPMSG=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5647_MIPI=m +CONFIG_SOC_CAMERA=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=y +CONFIG_RADIO_SI476X=y +CONFIG_SOC_CAMERA_OV2640=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_OVERLAY=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5079E=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=m +CONFIG_FB_MXC_ADV7535=y +CONFIG_HANNSTAR_CABC=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_SII902X=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_MC13783=y +CONFIG_SND_SOC_IMX_SI476X=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_SIM=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +CONFIG_DMATEST=m +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_ION=y +CONFIG_ION_MXC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_IMX7D_ADC=y +CONFIG_VF610_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_PWM_TPM=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/imx_v7_mfg_defconfig b/arch/arm/configs/imx_v7_mfg_defconfig new file mode 100644 index 00000000000000..b137a506ac35ae --- /dev/null +++ b/arch/arm/configs/imx_v7_mfg_defconfig @@ -0,0 +1,301 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MULTI_V6=y +CONFIG_ARCH_MXC=y +# CONFIG_MACH_MX31ADS is not set +# CONFIG_MACH_BUG is not set +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6ULL=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX6SLL=y +CONFIG_SOC_IMX7ULP=y +CONFIG_SOC_VF610=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_CMA=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_NETFILTER=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_BRCMFMAC=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_PF1550=y +CONFIG_MFD_MAX17135=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PF1550=y +CONFIG_REGULATOR_PF1550_RPMSG=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=y +CONFIG_SOC_CAMERA_OV2640=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_MC13783=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_MASS_STORAGE=y +CONFIG_FSL_UTP=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_SECURITYFS=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/mtp_defconfig b/arch/arm/configs/mtp_defconfig new file mode 100644 index 00000000000000..60905269178980 --- /dev/null +++ b/arch/arm/configs/mtp_defconfig @@ -0,0 +1,290 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=520 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_FEC is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_PHYLIB=y +CONFIG_MICREL_PHY=y +CONFIG_ATH_CARDS=m +CONFIG_HOSTAP=y +CONFIG_IWLWIFI=m +CONFIG_WL_TI=y +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_SSB=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +# CONFIG_USB_GSPCA is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_EZUSB_FX2=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_RV4162=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/nitrogen51_vm_defconfig b/arch/arm/configs/nitrogen51_vm_defconfig new file mode 100644 index 00000000000000..0f69688832656f --- /dev/null +++ b/arch/arm/configs/nitrogen51_vm_defconfig @@ -0,0 +1,299 @@ +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX51=y +CONFIG_SWP_EMULATE=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_814220=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_VLAN_8021Q=y +CONFIG_LLC2=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=2 +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CWC_HOOKSWITCH=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PIC16F616=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_SAS=y +CONFIG_SAS_PARTIAL_RX=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_HS=y +CONFIG_I2C_RESERVE=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_SENSORS_ADS1000=m +CONFIG_SENSORS_MAG3110=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MXC_HDMI=y +CONFIG_MFD_SYSCON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_MC13892=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_TVOUT_ADV739X=y +# CONFIG_FB_MXC_EDID is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_PL2303=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_SIM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +# CONFIG_MX3_IPU is not set +CONFIG_IMX_SDMA=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/nitrogen6_vm_defconfig b/arch/arm/configs/nitrogen6_vm_defconfig new file mode 100644 index 00000000000000..3e992ca478d327 --- /dev/null +++ b/arch/arm/configs/nitrogen6_vm_defconfig @@ -0,0 +1,296 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_ILI210X=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_MAGSTRIPE=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_KEYSPAN=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_MULTI=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_RV4162=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/nitrogen6_vm_pt_defconfig b/arch/arm/configs/nitrogen6_vm_pt_defconfig new file mode 100644 index 00000000000000..aa0b15c5d61f5a --- /dev/null +++ b/arch/arm/configs/nitrogen6_vm_pt_defconfig @@ -0,0 +1,259 @@ +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_PIC16F616=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_SAS=y +CONFIG_SAS_PARTIAL_RX=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_MXS_PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_RV4162=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_IMX_SDMA=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index bce58e975ad1fc..24e60ce1834763 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -81,6 +81,14 @@ #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) +#define IMX6SLL_UART1_BASE_ADDR 0x02020000 +#define IMX6SLL_UART2_BASE_ADDR 0x02024000 +#define IMX6SLL_UART3_BASE_ADDR 0x02034000 +#define IMX6SLL_UART4_BASE_ADDR 0x02018000 +#define IMX6SLL_UART5_BASE_ADDR 0x021f4000 +#define IMX6SLL_UART_BASE_ADDR(n) IMX6SLL_UART##n##_BASE_ADDR +#define IMX6SLL_UART_BASE(n) IMX6SLL_UART_BASE_ADDR(n) + #define IMX6SX_UART1_BASE_ADDR 0x02020000 #define IMX6SX_UART2_BASE_ADDR 0x021e8000 #define IMX6SX_UART3_BASE_ADDR 0x021ec000 @@ -133,6 +141,8 @@ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) #elif defined(CONFIG_DEBUG_IMX6SL_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) +#elif defined(CONFIG_DEBUG_IMX6SLL_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SLL) #elif defined(CONFIG_DEBUG_IMX6SX_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) #elif defined(CONFIG_DEBUG_IMX6UL_UART) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index f4e54503afa958..a4e4206f35978c 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -762,8 +762,9 @@ int __init arm_add_memory(u64 start, u64 size) } if (aligned_start + size > ULONG_MAX) { - pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n", - (long long)start); + if (aligned_start + size != (1ULL << 32)) + pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n", + (long long)start); /* * To ensure bank->start + bank->size is representable in * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9155b639c9aa9b..c02a1ad8468214 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -14,6 +14,14 @@ menuconfig ARCH_MXC if ARCH_MXC +config MXC_USE_VENDOR_DRIVERS + bool "Use Vendor drivers instead of Mainline" + help + This tree includes many vendor specific drivers that conflict or + duplicate existing mainline kernel drivers. This option will be + used to try and distinguish which driver will be available in the + kernel build + config MXC_TZIC bool @@ -44,6 +52,9 @@ config MXC_USE_EPIT uses the same clocks as the GPT. Anyway, on some systems the GPT may be in use for other purposes. +config HAVE_IMX_RNG + bool + config HAVE_IMX_ANATOP bool @@ -51,9 +62,26 @@ config HAVE_IMX_GPC bool select PM_GENERIC_DOMAINS if PM +config HAVE_IMX_GPCV2 + bool + select PM_GENERIC_DOMAINS if PM + config HAVE_IMX_MMDC bool +config HAVE_IMX_AMP + bool + +config HAVE_IMX_DDRC + bool + +config HAVE_IMX_MU + bool + +config HAVE_IMX_RPMSG + select RPMSG_VIRTIO + bool + config HAVE_IMX_SRC def_bool y if SMP select ARCH_HAS_RESET_CONTROLLER @@ -491,6 +519,8 @@ config SOC_IMX6 select HAVE_IMX_MMDC select HAVE_IMX_SRC select MFD_SYSCON + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP select PL310_ERRATA_769419 if CACHE_L2X0 config SOC_IMX6Q @@ -498,6 +528,7 @@ config SOC_IMX6Q select ARM_ERRATA_764369 if SMP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD + select PCI_DOMAINS if PCI select PINCTRL_IMX6Q select SOC_IMX6 @@ -506,6 +537,7 @@ config SOC_IMX6Q config SOC_IMX6SL bool "i.MX6 SoloLite support" + select HAVE_IMX_RNG select PINCTRL_IMX6SL select SOC_IMX6 @@ -515,7 +547,14 @@ config SOC_IMX6SL config SOC_IMX6SX bool "i.MX6 SoloX support" select PINCTRL_IMX6SX + select HAVE_IMX_AMP select SOC_IMX6 + select HAVE_IMX_MU + select HAVE_IMX_RPMSG + select RPMSG + select IMX_SEMA4 + select MXC_MLB150 + select KEYBOARD_SNVS_PWRKEY help This enables support for Freescale i.MX6 SoloX processor. @@ -524,18 +563,41 @@ config SOC_IMX6UL bool "i.MX6 UltraLite support" select PINCTRL_IMX6UL select SOC_IMX6 + select KEYBOARD_SNVS_PWRKEY + select ARM_ERRATA_814220 help This enables support for Freescale i.MX6 UltraLite processor. +config SOC_IMX6ULL + bool "i.MX6 ULL support" + select SOC_IMX6UL + + help + This enables support for Freescale i.MX6 ULL processor. + +config SOC_IMX7 + bool + select CPU_V7 + select ARM_GIC + select HAVE_IMX_MU + select HAVE_IMX_RPMSG + select RPMSG + config SOC_IMX7D bool "i.MX7 Dual support" + select SOC_IMX7 + select PCI_DOMAINS if PCI select PINCTRL_IMX7D - select ARM_GIC select HAVE_ARM_ARCH_TIMER select HAVE_IMX_ANATOP select HAVE_IMX_MMDC + select HAVE_IMX_DDRC select HAVE_IMX_SRC + select KEYBOARD_SNVS_PWRKEY + select HAVE_IMX_GPCV2 + select ARM_ERRATA_814220 + help This enables support for Freescale i.MX7 Dual processor. @@ -553,6 +615,23 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M +config SOC_IMX6SLL + bool "i.MX6 SLL support" + select PINCTRL_IMX6SLL + select SOC_IMX6 + select KEYBOARD_SNVS_PWRKEY + + help + This enables support for Freescale i.MX6 SLL processor. + +config SOC_IMX7ULP + bool "i.MX7ULP support" + select SOC_IMX7 + select CLKSRC_IMX_TPM + select PINCTRL_IMX7ULP + help + This enables support for Freescale i.MX7 Ultra Low Power processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index cab128913e72a7..b568f83f9145b3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,4 +1,4 @@ -obj-y := cpu.o system.o irq-common.o +obj-y := cpu.o system.o irq-common.o common.o obj-$(CONFIG_SOC_IMX21) += mm-imx21.o @@ -25,9 +25,19 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o -obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o +AFLAGS_imx6sl_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o imx6sl_low_power_idle.o +AFLAGS_imx6sx_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o imx6sx_low_power_idle.o +AFLAGS_imx6ul_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6ul.o imx6ul_low_power_idle.o +AFLAGS_imx6ull_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6ULL) += imx6ull_low_power_idle.o +AFLAGS_imx6sll_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sll.o imx6sll_low_power_idle.o +AFLAGS_imx7d_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX7D) += cpuidle-imx7d.o imx7d_low_power_idle.o endif ifdef CONFIG_SND_IMX_SOC @@ -68,25 +78,50 @@ obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o +obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o +obj-$(CONFIG_HAVE_IMX_DDRC) += ddrc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) +obj-$(CONFIG_HAVE_IMX_MU) += mu.o +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7)$(CONFIG_SOC_LS1021A),) AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o endif -obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o +obj-$(CONFIG_CPU_FREQ) += busfreq_lpddr2.o busfreq-imx.o busfreq_ddr3.o +AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a +AFLAGS_smp_wfe_imx6.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6q.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o smp_wfe_imx6.o \ + lpddr2_freq_imx6q.o +AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o lpddr2_freq_imx6.o +AFLAGS_lpddr2_freq_imx6sll.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o lpddr2_freq_imx6sll.o +AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o ddr3_freq_imx6sx.o \ + lpddr2_freq_imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o ddr3_freq_imx6sx.o \ + lpddr2_freq_imx6sx.o obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o pm-rpmsg.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7ulp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o +obj-$(CONFIG_SOC_IMX7D) += suspend-imx7.o obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o +obj-$(CONFIG_SOC_IMX7ULP) += suspend-imx7ulp.o endif obj-$(CONFIG_SOC_IMX6) += pm-imx6.o +AFLAGS_smp_wfe.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx7d.o :=-Wa,-march=armv7-a +AFLAGS_lpddr3_freq_imx.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX7D) += pm-imx7.o ddr3_freq_imx7d.o smp_wfe.o \ + lpddr3_freq_imx.o obj-$(CONFIG_SOC_IMX1) += mach-imx1.o obj-$(CONFIG_SOC_IMX50) += mach-imx50.o diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 649a84c251ad6e..d46f68417bbb66 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -9,6 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include #include @@ -21,9 +23,17 @@ #define REG_SET 0x4 #define REG_CLR 0x8 +#define ANADIG_ARM_PLL 0x60 +#define ANADIG_DDR_PLL 0x70 +#define ANADIG_SYS_PLL 0xb0 +#define ANADIG_ENET_PLL 0xe0 +#define ANADIG_AUDIO_PLL 0xf0 +#define ANADIG_VIDEO_PLL 0x130 + #define ANADIG_REG_2P5 0x130 #define ANADIG_REG_CORE 0x140 #define ANADIG_ANA_MISC0 0x150 +#define ANADIG_ANA_MISC2 0x170 #define ANADIG_USB1_CHRG_DETECT 0x1b0 #define ANADIG_USB2_CHRG_DETECT 0x210 #define ANADIG_DIGPROG 0x260 @@ -33,24 +43,43 @@ #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 +#define BM_ANADIG_REG_CORE_REG1 (0x1f << 9) +#define BM_ANADIG_REG_CORE_REG2 (0x1f << 18) +#define BP_ANADIG_REG_CORE_REG2 (18) #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 +#define BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG 0x800 +#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG 0xc00 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << 26) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME (26) /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 +/* Since i.MX6SX, DISCON_HIGH_SNVS is changed to bit 12 */ +#define BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS 0x1000 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 +#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */ +#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */ + static struct regmap *anatop; static void imx_anatop_enable_weak2p5(bool enable) { - u32 reg, val; + u32 reg, val, mask; regmap_read(anatop, ANADIG_ANA_MISC0, &val); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) + mask = BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG; + else if (cpu_is_imx6sl()) + mask = BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG; + else + mask = BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG; + /* can only be enabled when stop_mode_config is clear. */ reg = ANADIG_REG_2P5; - reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? - REG_SET : REG_CLR; + reg += (enable && (val & mask) == 0) ? REG_SET : REG_CLR; regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); } @@ -68,35 +97,100 @@ static inline void imx_anatop_enable_2p5_pulldown(bool enable) static inline void imx_anatop_disconnect_high_snvs(bool enable) { - regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), - BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6sll()) + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS); + else + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); +} + +static void imx_anatop_disable_pu(bool off) +{ + u32 val, soc, delay; + if (off) { + regmap_read(anatop, ANADIG_REG_CORE, &val); + val &= ~BM_ANADIG_REG_CORE_REG1; + regmap_write(anatop, ANADIG_REG_CORE, val); + } else { + /* track vddpu with vddsoc */ + regmap_read(anatop, ANADIG_REG_CORE, &val); + soc = val & BM_ANADIG_REG_CORE_REG2; + val &= ~BM_ANADIG_REG_CORE_REG1; + val |= soc >> 9; + regmap_write(anatop, ANADIG_REG_CORE, val); + /* wait PU LDO ramp */ + regmap_read(anatop, ANADIG_ANA_MISC2, &val); + val &= BM_ANADIG_ANA_MISC2_REG1_STEP_TIME; + val >>= BP_ANADIG_ANA_MISC2_REG1_STEP_TIME; + delay = (soc >> BP_ANADIG_REG_CORE_REG2) * + (LDO_RAMP_UP_UNIT_IN_CYCLES << val) / + LDO_RAMP_UP_FREQ_IN_MHZ + 1; + udelay(delay); + } } void imx_anatop_pre_suspend(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite set */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_SET, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_SET, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_SET, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_SET, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_SET, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_SET, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(true); + + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || + imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) && + !imx_gpc_usb_wakeup_enabled() && !imx_gpc_enet_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(true); else imx_anatop_enable_weak2p5(true); imx_anatop_enable_fet_odrive(true); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(true); } void imx_anatop_post_resume(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite clear */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_CLR, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_CLR, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_CLR, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_CLR, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_CLR, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_CLR, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(false); + + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || + imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) && + !imx_gpc_usb_wakeup_enabled() && !imx_gpc_enet_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(false); else imx_anatop_enable_weak2p5(false); imx_anatop_enable_fet_odrive(false); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(false); - } static void imx_anatop_usb_chrg_detect_disable(void) @@ -116,6 +210,7 @@ void __init imx_init_revision_from_anatop(void) unsigned int revision; u32 digprog; u16 offset = ANADIG_DIGPROG; + u16 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); @@ -127,45 +222,25 @@ void __init imx_init_revision_from_anatop(void) digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); - switch (digprog & 0xff) { - case 0: - /* - * For i.MX6QP, most of the code for i.MX6Q can be resued, - * so internally, we identify it as i.MX6Q Rev 2.0 - */ - if (digprog >> 8 & 0x01) - revision = IMX_CHIP_REVISION_2_0; - else - revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - revision = IMX_CHIP_REVISION_1_2; - break; - case 3: - revision = IMX_CHIP_REVISION_1_3; - break; - case 4: - revision = IMX_CHIP_REVISION_1_4; - break; - case 5: - /* - * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked - * as 'D' in Part Number last character. - */ - revision = IMX_CHIP_REVISION_1_5; - break; - default: + /* + * On i.MX7D digprog value match linux version format, so + * it needn't map again and we can use register value directly. + */ + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { + revision = digprog & 0xff; + } else { /* - * Fail back to return raw register value instead of 0xff. - * It will be easy to know version information in SOC if it - * can't be recognized by known version. And some chip's (i.MX7D) - * digprog value match linux version format, so it needn't map - * again and we can use register value directly. + * MAJOR: [15:8], the major silicon revison; + * MINOR: [7: 0], the minor silicon revison; + * + * please refer to the i.MX RM for the detailed + * silicon revison bit define. + * format the major part and minor part to match the + * linux kernel soc version format. */ - revision = digprog & 0xff; + major_part = (digprog >> 8) & 0xf; + minor_part = digprog & 0xf; + revision = ((major_part + 1) << 4) | minor_part; } mxc_set_cpu_type(digprog >> 16 & 0xff); diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c new file mode 100644 index 00000000000000..05db663de76fa9 --- /dev/null +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -0,0 +1,1379 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hardware.h" +#include "common.h" + +#define LPAPM_CLK 24000000 +#define LOW_AUDIO_CLK 50000000 +#define HIGH_AUDIO_CLK 100000000 + +#define LOW_POWER_RUN_VOLTAGE 950000 + +#define MMDC_MDMISC_DDR_TYPE_DDR3 0 +#define MMDC_MDMISC_DDR_TYPE_LPDDR2 1 + +unsigned int ddr_med_rate; +unsigned int ddr_normal_rate; +unsigned long ddr_freq_change_total_size; +unsigned long ddr_freq_change_iram_base; +unsigned long ddr_freq_change_iram_phys; + +static int ddr_type; +static int low_bus_freq_mode; +static int audio_bus_freq_mode; +static int ultra_low_bus_freq_mode; +static int high_bus_freq_mode; +static int med_bus_freq_mode; +static int bus_freq_scaling_initialized; +static bool cancel_reduce_bus_freq; +static struct device *busfreq_dev; +static int busfreq_suspended; +static int bus_freq_scaling_is_active; +static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; +static unsigned int ddr_low_rate; +static int cur_bus_freq_mode; +static u32 org_arm_rate; +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ +static int origin_arm_volt, origin_soc_volt; +#endif + +extern unsigned long iram_tlb_phys_addr; +extern int unsigned long iram_tlb_base_addr; + +extern int init_mmdc_lpddr2_settings(struct platform_device *dev); +extern int init_mmdc_lpddr2_settings_mx6q(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_up(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *dev); +extern int init_ddrc_ddr_settings(struct platform_device *dev); +extern int update_ddr_freq_imx_smp(int ddr_rate); +extern int update_ddr_freq_imx6_up(int ddr_rate); +extern int update_lpddr2_freq(int ddr_rate); +extern int update_lpddr2_freq_smp(int ddr_rate); + +DEFINE_MUTEX(bus_freq_mutex); + +static struct clk *osc_clk; +static struct clk *ahb_clk; +static struct clk *axi_sel_clk; +static struct clk *dram_root; +static struct clk *dram_alt_sel; +static struct clk *dram_alt_root; +static struct clk *pfd0_392m; +static struct clk *pfd2_270m; +static struct clk *pfd1_332m; +static struct clk *pll_dram; +static struct clk *ahb_sel_clk; +static struct clk *axi_clk; + +static struct clk *m4_clk; +static struct clk *arm_clk; +static struct clk *pll3_clk; +static struct clk *step_clk; +static struct clk *mmdc_clk; +static struct clk *ocram_clk; +static struct clk *pll1_clk; +static struct clk *pll1_bypass_clk; +static struct clk *pll1_bypass_src_clk; +static struct clk *pll1_sys_clk; +static struct clk *pll1_sw_clk; +static struct clk *pll2_bypass_src_clk; +static struct clk *pll2_bypass_clk; +static struct clk *pll2_clk; +static struct clk *pll2_400_clk; +static struct clk *pll2_200_clk; +static struct clk *pll2_bus_clk; +static struct clk *periph_clk; +static struct clk *periph_pre_clk; +static struct clk *periph_clk2_clk; +static struct clk *periph_clk2_sel_clk; +static struct clk *periph2_clk; +static struct clk *periph2_pre_clk; +static struct clk *periph2_clk2_clk; +static struct clk *periph2_clk2_sel_clk; +static struct clk *axi_alt_sel_clk; +static struct clk *pll3_pfd1_540m_clk; + +static struct delayed_work low_bus_freq_handler; +static struct delayed_work bus_freq_daemon; + +static RAW_NOTIFIER_HEAD(busfreq_notifier_chain); + +static bool check_m4_sleep(void) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + while (imx_gpc_is_m4_sleeping() == 0) + if (time_after(jiffies, timeout)) + return false; + return true; +} + +static int busfreq_notify(enum busfreq_event event) +{ + int ret; + + ret = raw_notifier_call_chain(&busfreq_notifier_chain, event, NULL); + + return notifier_to_errno(ret); +} + +int register_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_register(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(register_busfreq_notifier); + +int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_unregister(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(unregister_busfreq_notifier); + +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ +static struct clk *origin_step_parent; + +/* + * on i.MX6ULL, when entering low bus mode, the ARM core + * can run at 24MHz to support the low power run mode per + * to design team. + */ +static void imx6ull_lower_cpu_rate(bool enter) +{ + int ret; + + if (enter) { + org_arm_rate = clk_get_rate(arm_clk); + origin_arm_volt = regulator_get_voltage(arm_reg); + origin_soc_volt = regulator_get_voltage(soc_reg); + } + + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + if (enter) { + origin_step_parent = clk_get_parent(step_clk); + clk_set_parent(step_clk, osc_clk); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, LPAPM_CLK); + if (cpu_is_imx6sll() && uart_from_osc) { + ret = regulator_set_voltage_tol(arm_reg, LOW_POWER_RUN_VOLTAGE, 0); + if (ret) + pr_err("set arm reg voltage failed\n"); + ret = regulator_set_voltage_tol(soc_reg, LOW_POWER_RUN_VOLTAGE, 0); + if (ret) + pr_err("set soc reg voltage failed\n"); + } + } else { + if (uart_from_osc) { + ret = regulator_set_voltage_tol(soc_reg, origin_soc_volt, 0); + if (ret) + pr_err("set soc reg voltage failed\n"); + ret = regulator_set_voltage_tol(arm_reg, origin_arm_volt, 0); + if (ret) + pr_err("set arm reg voltage failed\n"); + } + clk_set_parent(step_clk, origin_step_parent); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, org_arm_rate); + clk_set_parent(pll1_bypass_clk, pll1_clk); + } +} +#endif + +/* + * enter_lpm_imx6_up and exit_lpm_imx6_up is used by + * i.MX6SX/i.MX6UL for entering and exiting lpm mode. + */ +static void enter_lpm_imx6_up(void) +{ + if (cpu_is_imx6sx() && imx_src_is_m4_enabled()) + if (!check_m4_sleep()) + pr_err("M4 is NOT in sleep!!!\n"); + + /* set periph_clk2 to source from OSC for periph */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* set ahb/ocram to 24MHz */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == IMX_DDR_TYPE_DDR3) + update_ddr_freq_imx6_up(LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + update_lpddr2_freq(HIGH_AUDIO_CLK); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + /* + * As periph2_clk's parent is not changed from + * high mode to audio mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (high_bus_freq_mode) { + if (ddr_type == IMX_DDR_TYPE_DDR3) + clk_set_rate(mmdc_clk, LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + clk_set_rate(mmdc_clk, HIGH_AUDIO_CLK); + } + +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ + if ((cpu_is_imx6ull() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); +#endif + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + if (ddr_type == IMX_DDR_TYPE_DDR3) + update_ddr_freq_imx6_up(LPAPM_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + update_lpddr2_freq(LPAPM_CLK); + clk_set_parent(periph2_clk2_sel_clk, osc_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ + if (cpu_is_imx6ull() || cpu_is_imx6sll()) + imx6ull_lower_cpu_rate(true); +#endif + + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void enter_lpm_imx6_smp(void) +{ + if (cpu_is_imx6dl()) + /* Set axi to periph_clk */ + clk_set_parent(axi_sel_clk, periph_clk); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + update_ddr_freq_imx_smp(LOW_AUDIO_CLK); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + update_lpddr2_freq_smp(HIGH_AUDIO_CLK); + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + clk_set_parent(periph_pre_clk, pll2_200_clk); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (high_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + update_ddr_freq_imx_smp(LPAPM_CLK); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + update_lpddr2_freq_smp(LPAPM_CLK); + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + /* Set periph_clk parent to OSC via periph_clk2_sel */ + clk_set_parent(periph_clk, periph_clk2_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void exit_lpm_imx6_up(void) +{ +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ + if ((cpu_is_imx6ull() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); +#endif + + clk_prepare_enable(pll2_400_clk); + + /* + * lower ahb/ocram's freq first to avoid too high + * freq during parent switch from OSC to pll3. + */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) + clk_set_rate(ahb_clk, LPAPM_CLK / 4); + else + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + /* set periph clk to from pll2_bus on i.MX6UL */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) + clk_set_parent(periph_pre_clk, pll2_bus_clk); + /* set periph clk to from pll2_400 */ + else + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + /* set periph_clk2 to pll3 */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + + if (ddr_type == IMX_DDR_TYPE_DDR3) + update_ddr_freq_imx6_up(ddr_normal_rate); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + update_lpddr2_freq(ddr_normal_rate); + /* correct parent info after ddr freq change in asm code */ + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + + /* + * As periph2_clk's parent is not changed from + * audio mode to high mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (audio_bus_freq_mode) + clk_set_rate(mmdc_clk, ddr_normal_rate); + + clk_disable_unprepare(pll2_400_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void exit_lpm_imx6_smp(void) +{ + struct clk *periph_clk_parent; + + if (cpu_is_imx6q() && ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + periph_clk_parent = pll2_bus_clk; + else + periph_clk_parent = pll2_400_clk; + + clk_prepare_enable(pll2_400_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + update_ddr_freq_imx_smp(ddr_normal_rate); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + update_lpddr2_freq_smp(ddr_normal_rate); + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + clk_set_parent(periph_pre_clk, periph_clk_parent); + clk_set_parent(periph_clk, periph_pre_clk); + if (cpu_is_imx6dl()) { + /* Set axi to pll3_pfd1_540m */ + clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m_clk); + clk_set_parent(axi_sel_clk, axi_alt_sel_clk); + } + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (audio_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + clk_disable_unprepare(pll2_400_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void enter_lpm_imx6sl(void) +{ + if (high_bus_freq_mode) { + /* Set periph_clk to be sourced from OSC_CLK */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* Ensure AHB/AXI clks are at 24MHz. */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + } + if (audio_bus_count) { + /* Set AHB to 8MHz to lower pwer.*/ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + /* Set up DDR to 100MHz. */ + update_lpddr2_freq(HIGH_AUDIO_CLK); + + /* Fix the clock tree in kernel */ + clk_set_parent(periph2_pre_clk, pll2_200_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* + * Fix the clock tree in kernel, make sure + * pll2_bypass is updated as it is + * sourced from PLL2. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + /* + * Swtich ARM to run off PLL2_PFD2_400MHz + * since DDR is anyway at 100MHz. + */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + + /* + * Ensure that the clock will be + * at original speed. + */ + clk_set_rate(arm_clk, org_arm_rate); + } + low_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + audio_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + u32 arm_div, pll1_rate; + org_arm_rate = clk_get_rate(arm_clk); + if (low_bus_freq_mode && low_bus_count == 0) { + /* + * We are already in DDR @ 24MHz state, but + * no one but ARM needs the DDR. In this case, + * we can lower the DDR freq to 1MHz when ARM + * enters WFI in this state. Keep track of this state. + */ + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) { + /* + * Anyway, make sure the AHB is running at 24MHz + * in low_bus_freq_mode. + */ + if (audio_bus_freq_mode) + clk_set_rate(ahb_clk, LPAPM_CLK); + /* + * Set DDR to 24MHz. + * Since we are going to bypass PLL2, + * we need to move ARM clk off PLL2_PFD2 + * to PLL1. Make sure the PLL1 is running + * at the lowest possible freq. + * To work well with CPUFREQ we want to ensure that + * the CPU freq does not change, so attempt to + * get a freq as close to 396MHz as possible. + */ + clk_set_rate(pll1_clk, + clk_round_rate(pll1_clk, (org_arm_rate * 2))); + pll1_rate = clk_get_rate(pll1_clk); + arm_div = pll1_rate / org_arm_rate; + if (pll1_rate / arm_div > org_arm_rate) + arm_div++; + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_clk); + /* + * Ensure ARM CLK is lower before + * changing the parent. + */ + clk_set_rate(arm_clk, org_arm_rate / arm_div); + /* Now set the ARM clk parent to PLL1_SYS. */ + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + /* + * Set STEP_CLK back to OSC to save power and + * also to maintain the parent.The WFI iram code + * will switch step_clk to osc, but the clock API + * is not aware of the change and when a new request + * to change the step_clk parent to pll2_pfd2_400M + * is requested sometime later, the change is ignored. + */ + clk_set_parent(step_clk, osc_clk); + /* Now set DDR to 24MHz. */ + update_lpddr2_freq(LPAPM_CLK); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_bypass_src_clk); + clk_set_parent(periph2_clk2_sel_clk, pll2_bus_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + } + if (low_bus_count == 0) { + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + ultra_low_bus_freq_mode = 0; + low_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_LOW; + } + audio_bus_freq_mode = 0; + } + } +} + +static void exit_lpm_imx6sl(void) +{ + /* Change DDR freq in IRAM. */ + update_lpddr2_freq(ddr_normal_rate); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * un-bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + /* Ensure that periph_clk is sourced from PLL2_400. */ + clk_set_parent(periph_pre_clk, pll2_400_clk); + /* + * Before switching the perhiph_clk, ensure that the + * AHB/AXI will not be too fast. + */ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + clk_set_parent(periph_clk, periph_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* Move ARM from PLL1_SW_CLK to PLL2_400. */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_rate(arm_clk, org_arm_rate); + ultra_low_bus_freq_mode = 0; + } +} + +static void enter_lpm_imx7d(void) +{ + if (audio_bus_count) { + clk_prepare_enable(pfd0_392m); + update_ddr_freq_imx_smp(HIGH_AUDIO_CLK); + + clk_set_parent(dram_alt_sel, pfd0_392m); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + clk_disable_unprepare(pfd0_392m); + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + update_ddr_freq_imx_smp(LPAPM_CLK); + + clk_set_parent(dram_alt_sel, osc_clk); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void exit_lpm_imx7d(void) +{ + clk_set_parent(axi_sel_clk, pfd1_332m); + clk_set_rate(ahb_clk, LPAPM_CLK / 2); + clk_set_parent(ahb_sel_clk, pfd2_270m); + + update_ddr_freq_imx_smp(ddr_normal_rate); + + clk_set_parent(dram_root, pll_dram); +} + +static void reduce_bus_freq(void) +{ + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + busfreq_notify(LOW_BUSFREQ_EXIT); + else if (!audio_bus_count) + busfreq_notify(LOW_BUSFREQ_ENTER); + + if (cpu_is_imx7d()) + enter_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) + enter_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + enter_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + enter_lpm_imx6sl(); + + med_bus_freq_mode = 0; + high_bus_freq_mode = 0; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (audio_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to audio mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (low_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to low mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); +} + +static void reduce_bus_freq_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + + if (!cancel_reduce_bus_freq) + reduce_bus_freq(); + + mutex_unlock(&bus_freq_mutex); +} + +/* + * Set the DDR, AHB to 24MHz. + * This mode will be activated only when none of the modules that + * need a higher DDR or AHB frequency are active. + */ +static int set_low_bus_freq(void) +{ + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + cancel_reduce_bus_freq = false; + + /* + * Check to see if we need to got from + * low bus freq mode to audio bus freq mode. + * If so, the change needs to be done immediately. + */ + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + reduce_bus_freq(); + else + /* + * Don't lower the frequency immediately. Instead + * scheduled a delayed work and drop the freq if + * the conditions still remain the same. + */ + schedule_delayed_work(&low_bus_freq_handler, + usecs_to_jiffies(3000000)); + return 0; +} + +static inline void cancel_low_bus_freq_handler(void) +{ + cancel_delayed_work(&low_bus_freq_handler); + cancel_reduce_bus_freq = true; +} + +/* + * Set the DDR to either 528MHz or 400MHz for iMX6qd + * or 400MHz for iMX6dl. + */ +static int set_high_bus_freq(int high_bus_freq) +{ + if (bus_freq_scaling_initialized && bus_freq_scaling_is_active) + cancel_low_bus_freq_handler(); + + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + if (high_bus_freq_mode) + return 0; + + /* medium bus freq is only supported for MX6DQ */ + if (med_bus_freq_mode && !high_bus_freq) + return 0; + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) + busfreq_notify(LOW_BUSFREQ_EXIT); + + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (cpu_is_imx7d()) + exit_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) + exit_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + exit_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + exit_lpm_imx6sl(); + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (high_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to high mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (med_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to med mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + + return 0; +} + +void request_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, "This mode cannot be requested!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) + high_bus_count++; + else if (mode == BUS_FREQ_MED) + med_bus_count++; + else if (mode == BUS_FREQ_AUDIO) + audio_bus_count++; + else if (mode == BUS_FREQ_LOW) + low_bus_count++; + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + cancel_low_bus_freq_handler(); + + if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) { + set_high_bus_freq(1); + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) && + (!med_bus_freq_mode)) { + set_high_bus_freq(0); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) && + (!med_bus_freq_mode) && (!audio_bus_freq_mode)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(request_bus_freq); + +void release_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, + "This mode cannot be released!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) { + if (high_bus_count == 0) { + dev_err(busfreq_dev, "high bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + high_bus_count--; + } else if (mode == BUS_FREQ_MED) { + if (med_bus_count == 0) { + dev_err(busfreq_dev, "med bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + med_bus_count--; + } else if (mode == BUS_FREQ_AUDIO) { + if (audio_bus_count == 0) { + dev_err(busfreq_dev, "audio bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + audio_bus_count--; + } else if (mode == BUS_FREQ_LOW) { + if (low_bus_count == 0) { + dev_err(busfreq_dev, "low bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + low_bus_count--; + } + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((!audio_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count == 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(release_bus_freq); + +int get_bus_freq_mode(void) +{ + return cur_bus_freq_mode; +} +EXPORT_SYMBOL(get_bus_freq_mode); + +static struct map_desc ddr_iram_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +const static char *ddr_freq_iram_match[] __initconst = { + "fsl,ddr-lpm-sram", + NULL +}; + +static int __init imx_dt_find_ddr_sram(unsigned long node, + const char *uname, int depth, void *data) +{ + unsigned long ddr_iram_addr; + const __be32 *prop; + + if (of_flat_dt_match(node, ddr_freq_iram_match)) { + unsigned int len; + + prop = of_get_flat_dt_prop(node, "reg", &len); + if (prop == NULL || len != (sizeof(unsigned long) * 2)) + return -EINVAL; + ddr_iram_addr = be32_to_cpu(prop[0]); + ddr_freq_change_total_size = be32_to_cpu(prop[1]); + ddr_freq_change_iram_phys = ddr_iram_addr; + + /* Make sure ddr_freq_change_iram_phys is 8 byte aligned. */ + if ((uintptr_t)(ddr_freq_change_iram_phys) & (FNCPY_ALIGN - 1)) + ddr_freq_change_iram_phys += FNCPY_ALIGN - + ((uintptr_t)ddr_freq_change_iram_phys % + (FNCPY_ALIGN)); + } + return 0; +} + +void __init imx_busfreq_map_io(void) +{ + /* + * Get the address of IRAM to be used by the ddr frequency + * change code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx_dt_find_ddr_sram, NULL)); + if (ddr_freq_change_iram_phys) { + ddr_freq_change_iram_base = IMX_IO_P2V( + ddr_freq_change_iram_phys); + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + /* We need to create a 1M page table entry. */ + ddr_iram_io_desc.virtual = IMX_IO_P2V( + ddr_freq_change_iram_phys & 0xFFF00000); + ddr_iram_io_desc.pfn = __phys_to_pfn( + ddr_freq_change_iram_phys & 0xFFF00000); + iotable_init(&ddr_iram_io_desc, 1); + } + memset((void *)ddr_freq_change_iram_base, 0, + ddr_freq_change_total_size); + } +} + +static void bus_freq_daemon_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) + && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0)) + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); +} + +static ssize_t bus_freq_scaling_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (bus_freq_scaling_is_active) + return sprintf(buf, "Bus frequency scaling is enabled\n"); + else + return sprintf(buf, "Bus frequency scaling is disabled\n"); +} + +static ssize_t bus_freq_scaling_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strncmp(buf, "1", 1) == 0) { + bus_freq_scaling_is_active = 1; + set_high_bus_freq(1); + /* + * We set bus freq to highest at the beginning, + * so we use this daemon thread to make sure system + * can enter low bus mode if + * there is no high bus request pending + */ + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } else if (strncmp(buf, "0", 1) == 0) { + if (bus_freq_scaling_is_active) + set_high_bus_freq(1); + bus_freq_scaling_is_active = 0; + } + return size; +} + +static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event, + void *dummy) +{ + mutex_lock(&bus_freq_mutex); + + if (event == PM_SUSPEND_PREPARE) { + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(false); + high_bus_count++; + set_high_bus_freq(1); + busfreq_suspended = 1; + } else if (event == PM_POST_SUSPEND) { + busfreq_suspended = 0; + high_bus_count--; + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(true); + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } + + mutex_unlock(&bus_freq_mutex); + + return NOTIFY_OK; +} + +static int busfreq_reboot_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + /* System is rebooting. Set the system into high_bus_freq_mode. */ + request_bus_freq(BUS_FREQ_HIGH); + + return 0; +} + +static struct notifier_block imx_bus_freq_pm_notifier = { + .notifier_call = bus_freq_pm_notify, +}; + +static struct notifier_block imx_busfreq_reboot_notifier = { + .notifier_call = busfreq_reboot_notifier_event, +}; + + +static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, + bus_freq_scaling_enable_store); + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ + +static int busfreq_probe(struct platform_device *pdev) +{ + u32 err; + + busfreq_dev = &pdev->dev; + + /* Return if no IRAM space is allocated for ddr freq change code. */ + if (!ddr_freq_change_iram_base) + return -ENOMEM; + + if (cpu_is_imx6()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + pll2_400_clk = devm_clk_get(&pdev->dev, "pll2_pfd2_396m"); + pll2_200_clk = devm_clk_get(&pdev->dev, "pll2_198m"); + pll2_bus_clk = devm_clk_get(&pdev->dev, "pll2_bus"); + pll3_clk = devm_clk_get(&pdev->dev, "pll3_usb_otg"); + periph_clk = devm_clk_get(&pdev->dev, "periph"); + periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre"); + periph_clk2_clk = devm_clk_get(&pdev->dev, "periph_clk2"); + periph_clk2_sel_clk = devm_clk_get(&pdev->dev, + "periph_clk2_sel"); + if (IS_ERR(osc_clk) || IS_ERR(pll2_400_clk) + || IS_ERR(pll2_200_clk) || IS_ERR(pll2_bus_clk) + || IS_ERR(pll3_clk) || IS_ERR(periph_clk) + || IS_ERR(periph_pre_clk) || IS_ERR(periph_clk2_clk) + || IS_ERR(periph_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6dl()) { + axi_alt_sel_clk = devm_clk_get(&pdev->dev, "axi_alt_sel"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + pll3_pfd1_540m_clk = devm_clk_get(&pdev->dev, "pll3_pfd1_540m"); + if (IS_ERR(axi_alt_sel_clk) || IS_ERR(axi_sel_clk) + || IS_ERR(pll3_pfd1_540m_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6sl() || cpu_is_imx6ull() || + cpu_is_imx6sll()) { + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + ocram_clk = devm_clk_get(&pdev->dev, "ocram"); + periph2_clk = devm_clk_get(&pdev->dev, "periph2"); + periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre"); + periph2_clk2_clk = devm_clk_get(&pdev->dev, "periph2_clk2"); + periph2_clk2_sel_clk = + devm_clk_get(&pdev->dev, "periph2_clk2_sel"); + if (IS_ERR(ahb_clk) || IS_ERR(ocram_clk) + || IS_ERR(periph2_clk) || IS_ERR(periph2_pre_clk) + || IS_ERR(periph2_clk2_clk) + || IS_ERR(periph2_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk for imx6ul/sx/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + dev_err(busfreq_dev, + "%s: failed to get mmdc clk for imx6sx/ul.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6q()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + mmdc_clk = NULL; + } + } + + if (cpu_is_imx6sx()) { + m4_clk = devm_clk_get(&pdev->dev, "m4"); + if (IS_ERR(m4_clk)) { + dev_err(busfreq_dev, "%s: failed to get m4 clk.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sl()) { + pll2_bypass_src_clk = devm_clk_get(&pdev->dev, "pll2_bypass_src"); + pll2_bypass_clk = devm_clk_get(&pdev->dev, "pll2_bypass"); + pll2_clk = devm_clk_get(&pdev->dev, "pll2"); + if (IS_ERR(pll2_bypass_src_clk) || IS_ERR(pll2_bypass_clk) + || IS_ERR(pll2_clk)) { + dev_err(busfreq_dev, + "%s failed to get busfreq clk for imx6sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6ull() || cpu_is_imx6sl() || cpu_is_imx6sll()) { + arm_clk = devm_clk_get(&pdev->dev, "arm"); + step_clk = devm_clk_get(&pdev->dev, "step"); + pll1_clk = devm_clk_get(&pdev->dev, "pll1"); + pll1_bypass_src_clk = devm_clk_get(&pdev->dev, "pll1_bypass_src"); + pll1_bypass_clk = devm_clk_get(&pdev->dev, "pll1_bypass"); + pll1_sys_clk = devm_clk_get(&pdev->dev, "pll1_sys"); + pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw"); + if (IS_ERR(arm_clk) || IS_ERR(step_clk) || IS_ERR(pll1_clk) + || IS_ERR(pll1_bypass_src_clk) || IS_ERR(pll1_bypass_clk) + || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk)) { + dev_err(busfreq_dev, "%s failed to get busfreq clk for imx6ull/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx7d()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + ahb_sel_clk = devm_clk_get(&pdev->dev, "ahb_sel"); + pfd0_392m = devm_clk_get(&pdev->dev, "pfd0_392m"); + dram_root = devm_clk_get(&pdev->dev, "dram_root"); + dram_alt_sel = devm_clk_get(&pdev->dev, "dram_alt_sel"); + pll_dram = devm_clk_get(&pdev->dev, "pll_dram"); + dram_alt_root = devm_clk_get(&pdev->dev, "dram_alt_root"); + pfd1_332m = devm_clk_get(&pdev->dev, "pfd1_332m"); + pfd2_270m = devm_clk_get(&pdev->dev, "pfd2_270m"); + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + axi_clk = devm_clk_get(&pdev->dev, "axi"); + if (IS_ERR(osc_clk) || IS_ERR(axi_sel_clk) || IS_ERR(ahb_clk) + || IS_ERR(pfd0_392m) || IS_ERR(dram_root) + || IS_ERR(dram_alt_sel) || IS_ERR(pll_dram) + || IS_ERR(dram_alt_root) || IS_ERR(pfd1_332m) + || IS_ERR(ahb_clk) || IS_ERR(axi_clk) + || IS_ERR(pfd2_270m)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + if (err) { + dev_err(busfreq_dev, + "Unable to register sysdev entry for BUSFREQ"); + return err; + } + + if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq", + &ddr_normal_rate)) { + dev_err(busfreq_dev, "max_ddr_freq entry missing\n"); + return -EINVAL; + } + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + bus_freq_scaling_is_active = 1; + bus_freq_scaling_initialized = 1; + + ddr_low_rate = LPAPM_CLK; + + INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler); + INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler); + register_pm_notifier(&imx_bus_freq_pm_notifier); + register_reboot_notifier(&imx_busfreq_reboot_notifier); + + /* enter low bus mode if no high speed device enabled */ + schedule_delayed_work(&bus_freq_daemon, + msecs_to_jiffies(10000)); + + /* + * Need to make sure to an entry for the ddr freq change code + * address in the IRAM page table. + * This is only required if the DDR freq code and suspend/idle + * code are in different OCRAM spaces. + */ + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + unsigned long i; + + /* + * Make sure the ddr_iram virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(ddr_freq_change_iram_phys) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (ddr_freq_change_iram_phys & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + if (cpu_is_imx7d()) { + ddr_type = imx_ddrc_get_ddr_type(); + /* reduce ddr3 normal rate to 400M due to CKE issue on TO1.1 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_1 && + ddr_type == IMX_DDR_TYPE_DDR3) { + ddr_normal_rate = 400000000; + pr_info("ddr3 normal rate changed to 400MHz for TO1.1.\n"); + } + err = init_ddrc_ddr_settings(pdev); + } else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6sll()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == IMX_DDR_TYPE_DDR3) + err = init_mmdc_ddr3_settings_imx6_up(pdev); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + err = init_mmdc_lpddr2_settings(pdev); + } else if (cpu_is_imx6q() || cpu_is_imx6dl()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + err = init_mmdc_ddr3_settings_imx6_smp(pdev); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + err = init_mmdc_lpddr2_settings_mx6q(pdev); + } else if (cpu_is_imx6sl()) { + err = init_mmdc_lpddr2_settings(pdev); + } + + if (cpu_is_imx6sx()) { + /* if M4 is enabled and rate > 24MHz, add high bus count */ + if (imx_src_is_m4_enabled() && + (clk_get_rate(m4_clk) > LPAPM_CLK)) + high_bus_count++; + } + + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) { + high_bus_count++; + imx_mu_lpm_ready(true); + } + + if (err) { + dev_err(busfreq_dev, "Busfreq init of ddr controller failed\n"); + return err; + } + return 0; +} + +static const struct of_device_id imx_busfreq_ids[] = { + { .compatible = "fsl,imx_busfreq", }, + { /* sentinel */ } +}; + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "imx_busfreq", + .owner = THIS_MODULE, + .of_match_table = imx_busfreq_ids, + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ +#ifndef CONFIG_MX6_VPU_352M + if (platform_driver_register(&busfreq_driver) != 0) + return -ENODEV; + + printk(KERN_INFO "Bus freq driver module loaded\n"); +#endif + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); + bus_freq_scaling_initialized = 0; +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-imx/busfreq_ddr3.c b/arch/arm/mach-imx/busfreq_ddr3.c new file mode 100644 index 00000000000000..3a016f15d5bb26 --- /dev/null +++ b/arch/arm/mach-imx/busfreq_ddr3.c @@ -0,0 +1,773 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_ddr3.c + * + * @brief iMX6 DDR3 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hardware.h" +#include "common.h" + +#define SMP_WFE_CODE_SIZE 0x400 + +#define MIN_DLL_ON_FREQ 333000000 +#define MAX_DLL_OFF_FREQ 125000000 +#define MMDC0_MPMUR0 0x8b8 +#define MMDC0_MPMUR0_OFFSET 16 +#define MMDC0_MPMUR0_MASK 0x3ff + +/* + * This structure is for passing necessary data for low level ocram + * busfreq code(arch/arm/mach-imx/ddr3_freq_imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/ddr3_freq_imx6.S must be also changed accordingly, + * otherwise, the busfreq change function will be broken! + * + * This structure will be placed in front of the asm code on ocram. + */ +struct imx6_busfreq_info { + u32 freq; + void *ddr_settings; + u32 dll_off; + void *iomux_offsets; + u32 mu_delay_val; +} __aligned(8); + +static struct imx6_busfreq_info *imx6_busfreq_info; + +/* DDR settings */ +static unsigned long (*iram_ddr_settings)[2]; +static unsigned long (*normal_mmdc_settings)[2]; +static unsigned long (*iram_iomux_settings)[2]; + +static void __iomem *mmdc_base; +static void __iomem *iomux_base; +static void __iomem *gic_dist_base; + +static int ddr_settings_size; +static int iomux_settings_size; +static int curr_ddr_rate; + +void (*imx6_up_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info); +extern void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info); +void (*imx7d_change_ddr_freq)(u32 freq) = NULL; +extern void imx7d_ddr3_freq_change(u32 freq); +extern void imx_lpddr3_freq_change(u32 freq); + +void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) = NULL; + +extern unsigned int ddr_normal_rate; +extern int low_bus_freq_mode; +extern int audio_bus_freq_mode; +extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets); + +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern unsigned long ddr_freq_change_iram_base; + +extern unsigned long ddr_freq_change_total_size; +extern unsigned long iram_tlb_phys_addr; + +extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start"); +extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end"); +extern unsigned long imx6_up_ddr3_freq_change_start asm("imx6_up_ddr3_freq_change_start"); +extern unsigned long imx6_up_ddr3_freq_change_end asm("imx6_up_ddr3_freq_change_end"); + +#ifdef CONFIG_SMP +static unsigned long wfe_freq_change_iram_base; +volatile u32 *wait_for_ddr_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; + +void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done); +void (*imx7_wfe_change_ddr_freq)(u32 cpuid, u32 ocram_base); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern void imx7_smp_wfe(u32 cpuid, u32 ocram_base); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *imx_scu_base; +#endif + +unsigned long ddr3_dll_mx6sx[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x00048031}, + {0x1C, 0x05208030}, + {0x1C, 0x04008040}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration_mx6sx[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x848, 0x0}, + {0x850, 0x0}, +}; + +unsigned long iomux_offsets_mx6sx[][2] = { + {0x330, 0x0}, + {0x334, 0x0}, + {0x338, 0x0}, + {0x33c, 0x0}, +}; + +unsigned long iomux_offsets_mx6ul[][2] = { + {0x280, 0x0}, + {0x284, 0x0}, +}; + +unsigned long ddr3_dll_mx6q[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04088032}, + {0x1C, 0x0408803a}, + {0x1C, 0x08408030}, + {0x1C, 0x08408038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x483c, 0x0}, + {0x4840, 0x0}, + {0x848, 0x0}, + {0x4848, 0x0}, + {0x850, 0x0}, + {0x4850, 0x0}, +}; + +unsigned long iomux_offsets_mx6q[][2] = { + {0x5A8, 0x0}, + {0x5B0, 0x0}, + {0x524, 0x0}, + {0x51C, 0x0}, + {0x518, 0x0}, + {0x50C, 0x0}, + {0x5B8, 0x0}, + {0x5C0, 0x0}, +}; + +unsigned long ddr3_dll_mx6dl[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x0400803a}, + {0x1C, 0x07208030}, + {0x1C, 0x07208038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long iomux_offsets_mx6dl[][2] = { + {0x4BC, 0x0}, + {0x4C0, 0x0}, + {0x4C4, 0x0}, + {0x4C8, 0x0}, + {0x4CC, 0x0}, + {0x4D0, 0x0}, + {0x4D4, 0x0}, + {0x4D8, 0x0}, +}; + +int can_change_ddr_freq(void) +{ + return 1; +} + +#ifdef CONFIG_SMP +/* + * each active core apart from the one changing + * the DDR frequency will execute this function. + * the rest of the cores have to remain in WFE + * state until the frequency is changed. + */ +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, + &me); +#endif + if (cpu_is_imx7d()) + imx7_wfe_change_ddr_freq(0x8 * me, + (u32)ddr_freq_change_iram_base); + else + wfe_change_ddr_freq(0xff << (me * 8), + (u32 *)&iram_iomux_settings[0][1]); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, + &me); +#endif + + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_ddr_freq_imx_smp(int ddr_rate) +{ + int me = 0; + unsigned long ttbr1; + bool dll_off = false; + int i; +#ifdef CONFIG_SMP + unsigned int reg = 0; + int cpu = 0; +#endif + int mode = get_bus_freq_mode(); + + if (!can_change_ddr_freq()) + return -1; + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if (cpu_is_imx6()) { + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + if (ddr_rate == ddr_normal_rate) { + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + } + } + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + u32 reg = 0; + + for_each_online_cpu(cpu) { + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = __raw_readl(imx_scu_base + 0x08); + + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_ddr_freq_update = 1; + dsb(); + if (cpu_is_imx7d()) + online_cpus = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + online_cpus = readl_relaxed(imx_scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + /* set the interrupt to be pending in the GIC. */ + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + /* Wait for the other active CPUs to idle */ + while (1) { + u32 reg = 0; + + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = readl_relaxed(imx_scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + if (cpu_is_imx6()) + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + + ttbr1 = save_ttbr1(); + /* Now we can change the DDR frequency. */ + if (cpu_is_imx7d()) + imx7d_change_ddr_freq(ddr_rate); + else if (cpu_is_imx6()) + mx6_change_ddr_freq(ddr_rate, iram_ddr_settings, + dll_off, iram_iomux_settings); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_ddr_freq_update = 0; + dsb(); + + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for updating the ddr frequency */ +int update_ddr_freq_imx6_up(int ddr_rate) +{ + int i; + bool dll_off = false; + unsigned long ttbr1; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + imx6_busfreq_info->dll_off = dll_off; + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + + local_irq_disable(); + + ttbr1 = save_ttbr1(); + imx6_busfreq_info->freq = ddr_rate; + imx6_busfreq_info->ddr_settings = iram_ddr_settings; + imx6_busfreq_info->iomux_offsets = iram_iomux_settings; + imx6_busfreq_info->mu_delay_val = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0) + >> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK); + + imx6_up_change_ddr_freq(imx6_busfreq_info); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done!\n", ddr_rate); + + return 0; +} + +int init_ddrc_ddr_settings(struct platform_device *busfreq_pdev) +{ + int ddr_type = imx_ddrc_get_ddr_type(); +#ifdef CONFIG_SMP + struct device_node *node; + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx7d-a7-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + for_each_online_cpu(cpu) { + int irq; + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "ddrc", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Store the variable used to communicate between cores */ + wait_for_ddr_freq_update = (u32 *)ddr_freq_change_iram_base; + imx7_wfe_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + 0x8, + &imx7_smp_wfe, SMP_WFE_CODE_SIZE - 0x8); +#endif + if (ddr_type == IMX_DDR_TYPE_DDR3) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + SMP_WFE_CODE_SIZE, + &imx7d_ddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + else if (ddr_type == IMX_DDR_TYPE_LPDDR3 + || ddr_type == IMX_DDR_TYPE_LPDDR2) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + + SMP_WFE_CODE_SIZE, + &imx_lpddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for mmdc setting init. */ +int init_mmdc_ddr3_settings_imx6_up(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + if (cpu_is_imx6sx()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc"); + else + node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find iomuxc device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6sx) + + ARRAY_SIZE(ddr3_calibration_mx6sx); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + memcpy(normal_mmdc_settings, ddr3_dll_mx6sx, + sizeof(ddr3_dll_mx6sx)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6sx)), + ddr3_calibration_mx6sx, sizeof(ddr3_calibration_mx6sx)); + + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + + if (cpu_is_imx6ul() || cpu_is_imx6ull()) + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6ul); + else + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx); + + ddr_code_size = (&imx6_up_ddr3_freq_change_end -&imx6_up_ddr3_freq_change_start) *4 + + sizeof(*imx6_busfreq_info); + + imx6_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base; + + imx6_up_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6_busfreq_info), + &imx6_up_ddr3_freq_change, ddr_code_size - sizeof(*imx6_busfreq_info)); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; + + if ((ddr_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n"); + return EINVAL; + } + + for (i = 0; i < iomux_settings_size; i++) { + if (cpu_is_imx6ul() || cpu_is_imx6ull()) { + iomux_offsets_mx6ul[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6ul[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6ul[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6ul[i][1]; + } else { + iomux_offsets_mx6sx[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6sx[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6sx[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6sx[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + unsigned long wfe_code_size = 0; +#ifdef CONFIG_SMP + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + node = NULL; + if (cpu_is_imx6q()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc"); + if (cpu_is_imx6dl()) + node = of_find_compatible_node(NULL, NULL, + "fsl,imx6dl-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + node = NULL; + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + if (cpu_is_imx6q()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) + + ARRAY_SIZE(ddr3_calibration); + if (cpu_is_imx6dl()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) + + ARRAY_SIZE(ddr3_calibration); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + if (cpu_is_imx6q()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6q, + sizeof(ddr3_dll_mx6q)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + if (cpu_is_imx6dl()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6dl, + sizeof(ddr3_dll_mx6dl)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + +#ifdef CONFIG_SMP + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq; + + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } +#endif + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q); + + ddr_code_size = (&mx6_ddr3_freq_change_end - + &mx6_ddr3_freq_change_start) * 4; + + mx6_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base, + &mx6_ddr3_freq_change, ddr_code_size); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; +#ifdef CONFIG_SMP + wfe_freq_change_iram_base = (unsigned long)((u32 *)iram_ddr_settings + + (ddr_settings_size * 8) + 8); + + if (wfe_freq_change_iram_base & (FNCPY_ALIGN - 1)) + wfe_freq_change_iram_base += FNCPY_ALIGN - + ((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN)); + + wfe_code_size = (&wfe_smp_freq_change_end - + &wfe_smp_freq_change_start) *4; + + wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base, + &wfe_smp_freq_change, wfe_code_size); + + /* + * Store the variable used to communicate + * between cores in a non-cacheable IRAM area + */ + wait_for_ddr_freq_update = (u32 *)&iram_iomux_settings[0][1]; +#endif + + if ((ddr_code_size + wfe_code_size + (iomux_settings_size + + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory for DDR Freq scale.\n"); + return EINVAL; + } + + if (cpu_is_imx6q()) { + /* store the IOMUX settings at boot. */ + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6q[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6q[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6q[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6q[i][1]; + } + } + + if (cpu_is_imx6dl()) { + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6dl[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6dl[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6dl[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6dl[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c new file mode 100644 index 00000000000000..2ef1806bbc3505 --- /dev/null +++ b/arch/arm/mach-imx/busfreq_lpddr2.c @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_lpddr2.c + * + * @brief iMX6 LPDDR2 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +static struct device *busfreq_dev; +static int curr_ddr_rate; +static DEFINE_SPINLOCK(freq_lock); + +void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode) = NULL; + +extern unsigned int ddr_normal_rate; +extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings); +extern unsigned long ddr_freq_change_iram_base; +extern unsigned long imx6_lpddr2_freq_change_start asm("imx6_lpddr2_freq_change_start"); +extern unsigned long imx6_lpddr2_freq_change_end asm("imx6_lpddr2_freq_change_end"); +extern unsigned long mx6q_lpddr2_freq_change_start asm("mx6q_lpddr2_freq_change_start"); +extern unsigned long mx6q_lpddr2_freq_change_end asm("mx6q_lpddr2_freq_change_end"); +extern unsigned long iram_tlb_phys_addr; + +struct mmdc_settings_info { + u32 size; + void *settings; + int freq; +} __aligned(8); +static struct mmdc_settings_info *mmdc_settings_info; +void (*mx6_change_lpddr2_freq_smp)(u32 ddr_freq, struct mmdc_settings_info + *mmdc_settings_info) = NULL; + +static int mmdc_settings_size; +static unsigned long (*mmdc_settings)[2]; +static unsigned long (*iram_mmdc_settings)[2]; +static unsigned long *iram_settings_size; +static unsigned long *iram_ddr_freq_chage; +unsigned long mmdc_timing_settings[][2] = { + {0x0C, 0x0}, /* mmdc_mdcfg0 */ + {0x10, 0x0}, /* mmdc_mdcfg1 */ + {0x14, 0x0}, /* mmdc_mdcfg2 */ + {0x18, 0x0}, /* mmdc_mdmisc */ + {0x38, 0x0}, /* mmdc_mdcfg3lp */ +}; + +#ifdef CONFIG_SMP +volatile u32 *wait_for_lpddr2_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; +void (*wfe_change_lpddr2_freq)(u32 cpuid, u32 *ddr_freq_change_done); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *imx_scu_base; +static void __iomem *gic_dist_base; +#endif + +#ifdef CONFIG_SMP +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &me); +#endif + wfe_change_lpddr2_freq(0xff << (me * 8), + (u32 *)ddr_freq_change_iram_base); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &me); +#endif + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_lpddr2_freq(int ddr_rate) +{ + unsigned long ttbr1, flags; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + spin_lock_irqsave(&freq_lock, flags); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + /* Now change DDR frequency. */ + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_ULTRA_LOW) ? 1 : 0); + else + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_AUDIO) ? 1 : 0); + + restore_ttbr1(ttbr1); + + curr_ddr_rate = ddr_rate; + spin_unlock_irqrestore(&freq_lock, flags); + + printk(KERN_DEBUG "\nBus freq set to %d done...\n", ddr_rate); + + return 0; +} + +int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev) +{ + unsigned long ddr_code_size; + busfreq_dev = &busfreq_pdev->dev; + + ddr_code_size = SZ_4K; + + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &mx6_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6_up_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sll()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6sll_lpddr2_freq_change, ddr_code_size); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int update_lpddr2_freq_smp(int ddr_rate) +{ + unsigned long ttbr1; + int i, me = 0; +#ifdef CONFIG_SMP + int cpu = 0; + u32 reg = 0; +#endif + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "Bus freq set to %d start...\n", ddr_rate); + + for (i=0; i < mmdc_settings_size; i++) { + iram_mmdc_settings[i][0] = mmdc_settings[i][0]; + iram_mmdc_settings[i][1] = mmdc_settings[i][1]; + } + + mmdc_settings_info->size = mmdc_settings_size; + mmdc_settings_info->settings = iram_mmdc_settings; + mmdc_settings_info->freq = curr_ddr_rate; + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + for_each_online_cpu(cpu) { + reg = __raw_readl(imx_scu_base + 0x08); + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_lpddr2_freq_update = 1; + dsb(); + online_cpus = readl_relaxed(imx_scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + + /* Wait for the other active CPUs to idle */ + while (1) { + reg = 0; + reg = readl_relaxed(imx_scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + curr_ddr_rate = ddr_rate; + + /* Now change DDR frequency. */ + mx6_change_lpddr2_freq_smp(ddr_rate, mmdc_settings_info); + + restore_ttbr1(ttbr1); + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_lpddr2_freq_update = 0; + dsb(); + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +int init_mmdc_lpddr2_settings_mx6q(struct platform_device *busfreq_pdev) +{ + struct device *dev = &busfreq_pdev->dev; + unsigned long ddr_code_size = 0; + unsigned long wfe_code_size = 0; + struct device_node *node; + void __iomem *mmdc_base; + int i; +#ifdef CONFIG_SMP + struct irq_data *d; + u32 cpu; + int err; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + + mmdc_base = of_iomap(node, 0); + if (!mmdc_base) { + dev_err(dev, "unable to map mmdc registers\n"); + return -EINVAL; + } + + mmdc_settings_size = ARRAY_SIZE(mmdc_timing_settings); + mmdc_settings = kmalloc((mmdc_settings_size * 8), GFP_KERNEL); + memcpy(mmdc_settings, mmdc_timing_settings, + sizeof(mmdc_timing_settings)); + +#ifdef CONFIG_SMP + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, IRQF_PERCPU, + "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Stoange_iram_basee the variable used to communicate between cores in + * a non-cacheable IRAM area */ + wait_for_lpddr2_freq_update = (u32 *)ddr_freq_change_iram_base; + wfe_code_size = (&wfe_smp_freq_change_end - &wfe_smp_freq_change_start) *4; + + wfe_change_lpddr2_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + 0x8, + &wfe_smp_freq_change, wfe_code_size); +#endif + iram_settings_size = (void *)ddr_freq_change_iram_base + wfe_code_size + 0x8; + iram_mmdc_settings = (void *)iram_settings_size + sizeof(*mmdc_settings_info); + iram_ddr_freq_chage = (void *)iram_mmdc_settings + (mmdc_settings_size * 8) + 0x8; + mmdc_settings_info = (struct mmdc_settings_info *)iram_settings_size; + + ddr_code_size = (&mx6q_lpddr2_freq_change_end -&mx6q_lpddr2_freq_change_start) *4; + + mx6_change_lpddr2_freq_smp = (void *)fncpy(iram_ddr_freq_chage, + &mx6q_lpddr2_freq_change, ddr_code_size); + + /* save initial mmdc boot timing settings */ + for (i=0; i < mmdc_settings_size; i++) + mmdc_settings[i][1] = readl_relaxed(mmdc_base + + mmdc_settings[i][0]); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff --git a/arch/arm/mach-imx/common.c b/arch/arm/mach-imx/common.c new file mode 100644 index 00000000000000..3579f740f80c2f --- /dev/null +++ b/arch/arm/mach-imx/common.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include + +#include "hardware.h" + +unsigned long iram_tlb_base_addr; +unsigned long iram_tlb_phys_addr; + +unsigned long save_ttbr1(void) +{ + unsigned long lttbr1; + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c2, c0, 1\n" + : "=r" (lttbr1) + ); + return lttbr1; +} + +void restore_ttbr1(unsigned long ttbr1) +{ + asm volatile( + ".align 4\n" + "mcr p15, 0, %0, c2, c0, 1\n" + : : "r" (ttbr1) + ); +} + +#define OCOTP_MAC_OFF (cpu_is_imx7d() ? 0x640 : 0x620) +#define OCOTP_MACn(n) (OCOTP_MAC_OFF + (n) * 0x10) +void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat) +{ + struct device_node *ocotp_np, *enet_np, *from = NULL; + void __iomem *base; + struct property *newmac; + u32 macaddr_low; + u32 macaddr_high = 0; + u32 macaddr1_high = 0; + u8 *macaddr; + int i, id; + + for (i = 0; i < 2; i++) { + enet_np = of_find_compatible_node(from, NULL, enet_compat); + if (!enet_np) + return; + + from = enet_np; + + if (of_get_mac_address(enet_np)) + goto put_enet_node; + + id = of_alias_get_id(enet_np, "ethernet"); + if (id < 0) + id = i; + + ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat); + if (!ocotp_np) { + pr_warn("failed to find ocotp node\n"); + goto put_enet_node; + } + + base = of_iomap(ocotp_np, 0); + if (!base) { + pr_warn("failed to map ocotp\n"); + goto put_ocotp_node; + } + + macaddr_low = readl_relaxed(base + OCOTP_MACn(1)); + if (id) + macaddr1_high = readl_relaxed(base + OCOTP_MACn(2)); + else + macaddr_high = readl_relaxed(base + OCOTP_MACn(0)); + + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); + if (!newmac) + goto put_ocotp_node; + + newmac->value = newmac + 1; + newmac->length = 6; + newmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!newmac->name) { + kfree(newmac); + goto put_ocotp_node; + } + + macaddr = newmac->value; + if (id) { + macaddr[5] = (macaddr_low >> 16) & 0xff; + macaddr[4] = (macaddr_low >> 24) & 0xff; + macaddr[3] = macaddr1_high & 0xff; + macaddr[2] = (macaddr1_high >> 8) & 0xff; + macaddr[1] = (macaddr1_high >> 16) & 0xff; + macaddr[0] = (macaddr1_high >> 24) & 0xff; + } else { + macaddr[5] = macaddr_high & 0xff; + macaddr[4] = (macaddr_high >> 8) & 0xff; + macaddr[3] = (macaddr_high >> 16) & 0xff; + macaddr[2] = (macaddr_high >> 24) & 0xff; + macaddr[1] = macaddr_low & 0xff; + macaddr[0] = (macaddr_low >> 8) & 0xff; + } + + of_update_property(enet_np, newmac); + +put_ocotp_node: + of_node_put(ocotp_np); +put_enet_node: + of_node_put(enet_np); + } +} + +#ifndef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; } +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); +#endif + +#if !defined(CONFIG_SOC_IMX6SL) +u32 imx6_lpddr2_freq_change_start, imx6_lpddr2_freq_change_end; +void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SLL) +void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SX) && !defined(CONFIG_SOC_IMX6UL) +u32 imx6_up_ddr3_freq_change_start, imx6_up_ddr3_freq_change_end; +struct imx6_busfreq_info { +} __aligned(8); +void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info) {} +void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6Q) +u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end; +u32 mx6q_lpddr2_freq_change_start, mx6q_lpddr2_freq_change_end; +u32 wfe_smp_freq_change_start, wfe_smp_freq_change_end; +void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) {} +void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings) {} +void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {} +#endif + +#if !defined(CONFIG_SOC_IMX7D) +void imx7_smp_wfe(u32 cpuid, u32 ocram_base) {} +void imx7d_ddr3_freq_change(u32 freq) {} +#endif diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index c4436d9c52ff92..b38a54e2b280c9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -1,5 +1,6 @@ /* - * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP */ /* @@ -12,11 +13,13 @@ #define __ASM_ARCH_MXC_COMMON_H__ #include +#include struct irq_data; struct platform_device; struct pt_regs; struct clk; +struct clk_hw; struct device_node; enum mxc_cpu_pwr_mode; struct of_device_id; @@ -63,6 +66,28 @@ void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); void imx25_pm_init(void); void imx27_pm_init(void); +unsigned int imx_gpc_is_mf_mix_off(void); +void imx6sx_set_m4_highfreq(bool high_freq); +void imx_mu_enable_m4_irqs_in_gic(bool enable); +#ifdef CONFIG_HAVE_IMX_GPC +void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable); +unsigned int imx_gpc_is_m4_sleeping(void); +#else +static inline void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable) {} +static inline unsigned int imx_gpc_is_m4_sleeping(void) { return 0; } +#endif +void imx_gpc_hold_m4_in_sleep(void); +void imx_gpc_release_m4_in_sleep(void); +void mcc_receive_from_mu_buffer(unsigned int index, unsigned int *data); +void mcc_send_via_mu_buffer(unsigned int index, unsigned int data); +bool imx_mu_is_m4_in_low_freq(void); +bool imx_mu_is_m4_in_stop(void); +void imx_mu_set_m4_run_mode(void); +#ifdef CONFIG_HAVE_IMX_MU +int imx_mu_lpm_ready(bool ready); +#else +static inline int imx_mu_lpm_ready(bool ready) { return 0; } +#endif enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -79,6 +104,17 @@ enum mx3_cpu_pwr_mode { MX3_SLEEP, }; +enum imx7ulp_cpu_pwr_mode { + HSRUN, + RUN, + VLPR, + WAIT, + VLPW, + STOP, + VLPS, + VLLS, +}; + void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); void imx_enable_cpu(int cpu, bool enable); @@ -93,9 +129,35 @@ void imx_smp_prepare(void); static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} #endif +void imx6_pm_map_io(void); +void imx7_pm_map_io(void); +void imx7ulp_pm_map_io(void); void imx_src_init(void); void imx_gpc_pre_suspend(bool arm_power_off); void imx_gpc_post_resume(void); +void imx_gpc_switch_pupscr_clk(bool flag); +unsigned int imx_gpc_is_mf_mix_off(void); +void imx_gpcv2_pre_suspend(bool arm_power_off); +void imx_gpcv2_post_resume(void); +unsigned int imx_gpcv2_is_mf_mix_off(void); +void imx_gpcv2_enable_wakeup_for_m4(void); +void imx_gpcv2_disable_wakeup_for_m4(void); +int imx_gpc_mf_power_on(unsigned int irq, unsigned int on); +#ifdef CONFIG_HAVE_IMX_GPCV2 +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on); +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable); +#else +static inline int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) { return 0; } +static inline void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) {} +static inline void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) {} +#endif +void __init imx_gpcv2_check_dt(void); +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode); +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn); +void imx_gpcv2_enable_rbc(bool enable); +unsigned long save_ttbr1(void); +void restore_ttbr1(unsigned long ttbr1); void imx_gpc_mask_all(void); void imx_gpc_restore_all(void); void imx_gpc_hwirq_mask(unsigned int hwirq); @@ -106,22 +168,52 @@ void imx_anatop_post_resume(void); int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); void imx6_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); +void imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat); +int imx7ulp_set_lpm(enum imx7ulp_cpu_pwr_mode mode); +#ifdef CONFIG_HAVE_IMX_MMDC int imx_mmdc_get_ddr_type(void); - +int imx_mmdc_get_lpddr2_2ch_mode(void); +#else +static inline int imx_mmdc_get_ddr_type(void) { return 0; } +static inline int imx_mmdc_get_lpddr2_2ch_mode(void) { return 0; } +#endif +#ifdef CONFIG_HAVE_IMX_DDRC +int imx_ddrc_get_ddr_type(void); +#else +static inline int imx_ddrc_get_ddr_type(void) { return 0; } +#endif void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); +void imx_busfreq_map_io(void); +void imx7d_low_power_idle(void); +void imx6sx_low_power_idle(void); +void imx6ul_low_power_idle(void); +void imx6ull_low_power_idle(void); +void imx6sl_low_power_idle(void); +void imx6sll_low_power_idle(void); +bool imx_gpc_usb_wakeup_enabled(void); +bool imx_gpc_enet_wakeup_enabled(void); #ifdef CONFIG_SUSPEND void v7_cpu_resume(void); +void ca7_cpu_resume(void); void imx53_suspend(void __iomem *ocram_vbase); extern const u32 imx53_suspend_sz; +void imx7ulp_cpu_resume(void); void imx6_suspend(void __iomem *ocram_vbase); +void imx7_suspend(void __iomem *ocram_vbase); +void imx7ulp_suspend(void __iomem *ocram_vbase); #else static inline void v7_cpu_resume(void) {} +static inline void ca7_cpu_resume(void) {} static inline void imx53_suspend(void __iomem *ocram_vbase) {} static const u32 imx53_suspend_sz; +static inline void imx7ulp_cpu_resume(void) {} static inline void imx6_suspend(void __iomem *ocram_vbase) {} +static inline void imx7_suspend(void __iomem *ocram_vbase) {} +static inline void imx7ulp_suspend(void __iomem *ocram_vbase) {} #endif +void pm_shutdown_notify_m4(void); void imx6_pm_ccm_init(const char *ccm_compat); void imx6q_pm_init(void); @@ -129,6 +221,11 @@ void imx6dl_pm_init(void); void imx6sl_pm_init(void); void imx6sx_pm_init(void); void imx6ul_pm_init(void); +void imx6ull_pm_init(void); +void imx7d_pm_init(void); +void imx7ulp_pm_init(void); +void imx7ulp_enable_nmi(void); +void imx6q_pm_set_ccm_base(void __iomem *base); #ifdef CONFIG_PM void imx51_pm_init(void); @@ -153,4 +250,6 @@ static inline void imx_init_l2cache(void) {} extern const struct smp_operations imx_smp_ops; extern const struct smp_operations ls1021a_smp_ops; +extern bool uart_from_osc; + #endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index b3347d32349f6a..a02b47a0be36bd 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -126,14 +126,26 @@ struct device * __init imx_soc_device_init(void) soc_id = "i.MX6SX"; break; case MXC_CPU_IMX6Q: - soc_id = "i.MX6Q"; + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + soc_id = "i.MX6QP"; + else + soc_id = "i.MX6Q"; break; case MXC_CPU_IMX6UL: soc_id = "i.MX6UL"; break; + case MXC_CPU_IMX6ULL: + soc_id = "i.MX6ULL"; + break; case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; + case MXC_CPU_IMX6SLL: + soc_id = "i.MX6SLL"; + break; + case MXC_CPU_IMX7ULP: + soc_id = "i.MX7ULP"; + break; default: soc_id = "Unknown"; } diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index bfeb25aaf9a2a7..02d55ae7e0eb59 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012, 2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,6 +30,8 @@ static int imx6q_enter_wait(struct cpuidle_device *dev, if (!spin_trylock(&master_lock)) goto idle; imx6_set_lpm(WAIT_UNCLOCKED); + if (atomic_read(&master) != num_online_cpus()) + imx6_set_lpm(WAIT_CLOCKED); cpu_do_idle(); imx6_set_lpm(WAIT_CLOCKED); spin_unlock(&master_lock); @@ -41,6 +43,7 @@ static int imx6q_enter_wait(struct cpuidle_device *dev, done: atomic_dec(&master); + imx6_set_lpm(WAIT_CLOCKED); return index; } diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index 8d866fb674a85a..21ecebf699aa96 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -1,29 +1,86 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include +#include +#include +#include +#include #include +#include +#include #include "common.h" #include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 19 + +static void __iomem *wfi_iram_base; +extern unsigned long iram_tlb_base_addr; + +#ifdef CONFIG_CPU_FREQ +extern unsigned long mx6sl_lpm_wfi_start asm("mx6sl_lpm_wfi_start"); +extern unsigned long mx6sl_lpm_wfi_end asm("mx6sl_lpm_wfi_end"); +#endif + +struct imx6_cpuidle_pm_info { + u32 pm_info_size; /* Size of pm_info */ + u32 ttbr; + void __iomem *mmdc_base; + void __iomem *iomuxc_base; + void __iomem *ccm_base; + void __iomem *l2_base; + void __iomem *anatop_base; + u32 mmdc_io_num; /*Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /*CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /*SODT0, SODT1, ,MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /*SDCKE0, SDCK1, RESET */ +}; + +static struct regulator *vbus_ldo; +static struct regulator_dev *ldo2p5_dummy_regulator_rdev; +static struct regulator_init_data ldo2p5_dummy_initdata = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; +static int ldo2p5_dummy_enable; + +static void (*imx6sl_wfi_in_iram_fn)(void __iomem *iram_vbase, + int audio_mode, bool vbus_ldo); static int imx6sl_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + int mode = get_bus_freq_mode(); + imx6_set_lpm(WAIT_UNCLOCKED); - /* - * Software workaround for ERR005311, see function - * description for details. - */ - imx6sl_set_wait_clk(true); - cpu_do_idle(); - imx6sl_set_wait_clk(false); + if ((mode == BUS_FREQ_AUDIO) || (mode == BUS_FREQ_ULTRA_LOW)) { + imx6sl_wfi_in_iram_fn(wfi_iram_base, (mode == BUS_FREQ_AUDIO) ? 1 : 0 , + ldo2p5_dummy_enable); + } else { + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + } imx6_set_lpm(WAIT_CLOCKED); return index; @@ -51,5 +108,108 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = { int __init imx6sl_cpuidle_init(void) { + +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + vbus_ldo = regulator_get(NULL, "ldo2p5-dummy"); + if (IS_ERR(vbus_ldo)) + vbus_ldo = NULL; + + wfi_iram_base = (void *)(iram_tlb_base_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wif_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base) & (FNCPY_ALIGN - 1)) + wfi_iram_base += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base % (FNCPY_ALIGN)); + + pm_info = wfi_iram_base; + pm_info->pm_info_size = sizeof(*pm_info); + pm_info->mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset); + mmdc_offset_array = imx6sl_mmdc_io_offset; + pm_info->mmdc_base = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + pm_info->ccm_base = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + pm_info->anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + pm_info->iomuxc_base = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + pm_info->l2_base = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < pm_info->mmdc_io_num; i++) + pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + wfi_code_size = (&mx6sl_lpm_wfi_end -&mx6sl_lpm_wfi_start) *4; + + imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*pm_info), + &imx6sl_low_power_idle, wfi_code_size); +#endif + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); } + +static int imx_ldo2p5_dummy_enable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 1; + return 0; +} + +static int imx_ldo2p5_dummy_disable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 0; + return 0; +} + +static int imx_ldo2p5_dummy_is_enable(struct regulator_dev *rdev) +{ + return ldo2p5_dummy_enable; +} + +static struct regulator_ops ldo2p5_dummy_ops = { + .enable = imx_ldo2p5_dummy_enable, + .disable = imx_ldo2p5_dummy_disable, + .is_enabled = imx_ldo2p5_dummy_is_enable, +}; + +static struct regulator_desc ldo2p5_dummy_desc = { + .name = "ldo2p5-dummy", + .id = -1, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + .ops = &ldo2p5_dummy_ops, +}; + +static int ldo2p5_dummy_probe(struct platform_device *pdev) +{ + struct regulator_config config = { }; + int ret; + + config.dev = &pdev->dev; + config.init_data = &ldo2p5_dummy_initdata; + config.of_node = pdev->dev.of_node; + + ldo2p5_dummy_regulator_rdev = regulator_register(&ldo2p5_dummy_desc, &config); + if (IS_ERR(ldo2p5_dummy_regulator_rdev)) { + ret = PTR_ERR(ldo2p5_dummy_regulator_rdev); + dev_err(&pdev->dev, "Failed to register dummy ldo2p5 regulator: %d\n", ret); + return ret; + } + return 0; +} + +static const struct of_device_id imx_ldo2p5_dummy_ids[] = { + { .compatible = "fsl,imx6-dummy-ldo2p5"}, + }; +MODULE_DEVICE_TABLE(ofm, imx_ldo2p5_dummy_ids); + +static struct platform_driver ldo2p5_dummy_driver = { + .probe = ldo2p5_dummy_probe, + .driver = { + .name = "ldo2p5-dummy", + .owner = THIS_MODULE, + .of_match_table = imx_ldo2p5_dummy_ids, + }, +}; + +module_platform_driver(ldo2p5_dummy_driver); diff --git a/arch/arm/mach-imx/cpuidle-imx6sll.c b/arch/arm/mach-imx/cpuidle-imx6sll.c new file mode 100644 index 00000000000000..65d82e5855e27d --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6sll.c @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sll_lpm_wfi_start asm("mx6sll_lpm_wfi_start"); +extern unsigned long mx6sll_lpm_wfi_end asm("mx6sll_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base l2_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0, DQM1, RAS, CAS */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK0, GPR_ADDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1 */ +}; + +static void (*imx6sll_wfi_in_iram_fn)(void __iomem *iram_vbase); + +static int imx6sll_idle_finish(unsigned long val) +{ + imx6sll_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6sll_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + cpu_do_idle(); + } else { + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6sll_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sll_cpuidle_driver = { + .name = "imx6sll_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6sll_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6sll_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6sll_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset); + mmdc_offset_array = imx6sll_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + wfi_code_size = (&mx6sll_lpm_wfi_end -&mx6sll_lpm_wfi_start) *4; + + imx6sll_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sll_low_power_idle, wfi_code_size); +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + return cpuidle_register(&imx6sll_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index c5a5c3a70ab15c..be73709ebce596 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -1,22 +1,92 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include +#include +#include +#include #include #include #include +#include +#include +#include #include +#include #include "common.h" #include "cpuidle.h" +#include "hardware.h" -static int imx6sx_idle_finish(unsigned long val) +#define MX6_MAX_MMDC_IO_NUM 19 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; + +static void __iomem *wfi_iram_base; +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sx_lpm_wfi_start asm("mx6sx_lpm_wfi_start"); +extern unsigned long mx6sx_lpm_wfi_end asm("mx6sx_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +static const u32 imx6sx_mmdc_io_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x60c, 0x610, 0x61c, 0x620, /* B0DS ~ B3DS */ + 0x5f8, 0x608, 0x310, 0x314, /* CTL, MODE, SODT0, SODT1 */ + 0x300, 0x2fc, 0x32c, /* CAS, RAS, SDCLK_0 */ +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base sema4_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static void (*imx6sx_wfi_in_iram_fn)(void __iomem *iram_vbase); + +static int imx6_idle_finish(unsigned long val) { /* * for Cortex-A7 which has an internal L2 @@ -27,7 +97,7 @@ static int imx6sx_idle_finish(unsigned long val) * just call flush_cache_all() is fine. */ flush_cache_all(); - cpu_do_idle(); + imx6sx_wfi_in_iram_fn(wfi_iram_base); return 0; } @@ -35,29 +105,22 @@ static int imx6sx_idle_finish(unsigned long val) static int imx6sx_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - imx6_set_lpm(WAIT_UNCLOCKED); + int mode = get_bus_freq_mode(); - switch (index) { - case 1: + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; cpu_do_idle(); - break; - case 2: - imx6_enable_rbc(true); - imx_gpc_set_arm_power_in_lpm(true); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Need to notify there is a cpu pm operation. */ - cpu_pm_enter(); - cpu_cluster_pm_enter(); - - cpu_suspend(0, imx6sx_idle_finish); - - cpu_cluster_pm_exit(); - cpu_pm_exit(); - imx_gpc_set_arm_power_in_lpm(false); - imx6_enable_rbc(false); - break; - default: - break; + } else { + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); } imx6_set_lpm(WAIT_CLOCKED); @@ -71,24 +134,23 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { .states = { /* WFI */ ARM_CPUIDLE_WFI_STATE, - /* WAIT */ + /* WAIT MODE */ { .exit_latency = 50, .target_residency = 75, - .flags = CPUIDLE_FLAG_TIMER_STOP, .enter = imx6sx_enter_wait, .name = "WAIT", .desc = "Clock off", }, - /* WAIT + ARM power off */ + /* LOW POWER IDLE */ { /* - * ARM gating 31us * 5 + RBC clear 65us - * and some margin for SW execution, here set it - * to 300us. + * RBC 130us + ARM gating 93us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 800us. */ - .exit_latency = 300, - .target_residency = 500, + .exit_latency = 800, + .target_residency = 1000, .enter = imx6sx_enter_wait, .name = "LOW-POWER-IDLE", .desc = "ARM power off", @@ -100,16 +162,119 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { int __init imx6sx_cpuidle_init(void) { + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset); + mmdc_offset_array = imx6sx_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->sema4_base.pbase = MX6Q_SEMA4_BASE_ADDR; + cpuidle_pm_info->sema4_base.vbase = + (void __iomem *)IMX_IO_P2V(MX6Q_SEMA4_BASE_ADDR); + + /* only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* code size should include cpuidle_pm_info size */ + wfi_code_size = (&mx6sx_lpm_wfi_end -&mx6sx_lpm_wfi_start) *4 + sizeof(*cpuidle_pm_info); + imx6sx_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sx_low_power_idle, wfi_code_size); +#endif + imx6_set_int_mem_clk_lpm(true); - imx6_enable_rbc(false); - /* - * set ARM power up/down timing to the fastest, - * sw2iso and sw can be set to one 32K cycle = 31us - * except for power up sw2iso which need to be - * larger than LDO ramp up time. - */ - imx_gpc_set_arm_power_up_timing(2, 1); - imx_gpc_set_arm_power_down_timing(1, 1); + + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) { + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + } return cpuidle_register(&imx6sx_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/cpuidle-imx6ul.c b/arch/arm/mach-imx/cpuidle-imx6ul.c new file mode 100644 index 00000000000000..7708d878615c3e --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6ul.c @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6ul_lpm_wfi_start asm("mx6ul_lpm_wfi_start"); +extern unsigned long mx6ul_lpm_wfi_end asm("mx6ul_lpm_wfi_end"); +extern unsigned long mx6ull_lpm_wfi_start asm("mx6ull_lpm_wfi_start"); +extern unsigned long mx6ull_lpm_wfi_end asm("mx6ull_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6ul_mmdc_io_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, /* MODE_CTL, MODE, */ +}; + +static void (*imx6ul_wfi_in_iram_fn)(void __iomem *iram_vbase); + +static int imx6ul_idle_finish(unsigned long val) +{ + imx6ul_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6ul_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + cpu_do_idle(); + index = 1; + } else { + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case. + */ + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6ul_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6ul_cpuidle_driver_v2 = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +static struct cpuidle_driver imx6ul_cpuidle_driver = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 1370us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 2100us. + */ + .exit_latency = 2100, + .target_residency = 2500, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6ul_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset); + mmdc_offset_array = imx6ul_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + if (cpu_is_imx6ul()) { + wfi_code_size = (&mx6ul_lpm_wfi_end -&mx6ul_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ul_low_power_idle, wfi_code_size); + } else { + wfi_code_size = (&mx6ull_lpm_wfi_end -&mx6ull_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ull_low_power_idle, wfi_code_size); + } +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + /* ARM power up time is reduced since TO1.1 */ + if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_0) + return cpuidle_register(&imx6ul_cpuidle_driver_v2, NULL); + else + return cpuidle_register(&imx6ul_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx7d.c b/arch/arm/mach-imx/cpuidle-imx7d.c new file mode 100644 index 00000000000000..36ad21a33dfa4f --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx7d.c @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define XTALOSC24M_OSC_CONFIG0 0x10 +#define XTALOSC24M_OSC_CONFIG1 0x20 +#define XTALOSC24M_OSC_CONFIG2 0x30 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +#define XTALOSC_CTRL_24M 0x0 +#define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13 +#define REG_SET 0x4 + +static void __iomem *wfi_iram_base; +static void __iomem *wfi_iram_base_phys; +extern unsigned long iram_tlb_phys_addr; + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_cpuidle_pm_info { + phys_addr_t vbase; /* The virtual address of pm_info. */ + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; + u32 ttbr; + u32 num_online_cpus; + u32 num_lpi_cpus; + atomic_t val; + atomic_t flag0; + atomic_t flag1; + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base gic_dist_base; +} __aligned(8); + +static atomic_t master_wait = ATOMIC_INIT(0); + +static void (*imx7d_wfi_in_iram_fn)(void __iomem *iram_vbase); +static struct imx7_cpuidle_pm_info *cpuidle_pm_info; + +/* Mapped for the kernel, unlike cpuidle_pm_info->gic_dist_base.vbase */ +static void __iomem *imx7d_cpuidle_gic_base; + +static void imx_pen_lock(int cpu) +{ + if (cpu == 0) { + atomic_set(&cpuidle_pm_info->flag0, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag1) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } else { + atomic_set(&cpuidle_pm_info->flag1, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag0) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } +} + +static void imx_pen_unlock(int cpu) +{ + dsb(); + if (cpu == 0) + atomic_set(&cpuidle_pm_info->flag0, 0); + else + atomic_set(&cpuidle_pm_info->flag1, 0); +} + +static int imx7d_idle_finish(unsigned long val) +{ + imx7d_wfi_in_iram_fn(wfi_iram_base); + return 0; +} + +static bool imx7d_gic_sgis_pending(void) +{ + void __iomem *sgip_base = imx7d_cpuidle_gic_base + 0x1f20; + + return (readl_relaxed(sgip_base + 0x0) | + readl_relaxed(sgip_base + 0x4) | + readl_relaxed(sgip_base + 0x8) | + readl_relaxed(sgip_base + 0xc)); +} + +static int imx7d_enter_low_power_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + if (atomic_inc_return(&master_wait) == num_online_cpus()) + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + + cpu_do_idle(); + + atomic_dec(&master_wait); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } else { + imx_pen_lock(dev->cpu); + ++cpuidle_pm_info->num_lpi_cpus; + cpu_pm_enter(); + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + /* + * GPC will not wake on SGIs so check for them + * manually here. At this point we know the other cpu + * is in wfi or waiting for the lock and can't send + * any additional IPIs. + */ + if (imx7d_gic_sgis_pending()) { + index = -1; + goto skip_lpi_flow; + } + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + imx_gpcv2_set_cpu_power_gate_in_idle(true); + cpu_cluster_pm_enter(); + } else { + imx_set_cpu_jump(dev->cpu, ca7_cpu_resume); + } + + cpu_suspend(0, imx7d_idle_finish); + + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + cpu_cluster_pm_exit(); + imx_gpcv2_set_cpu_power_gate_in_idle(false); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } + +skip_lpi_flow: + cpu_pm_exit(); + --cpuidle_pm_info->num_lpi_cpus; + imx_pen_unlock(dev->cpu); + } + + return index; +} + +static struct cpuidle_driver imx7d_cpuidle_driver = { + .name = "imx7d_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT MODE */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx7d_enter_low_power_idle, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + .exit_latency = 10000, + .target_residency = 20000, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx7d_enter_low_power_idle, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +#ifdef CONFIG_HOTPLUG_CPU +static int cpu_hotplug_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + switch (action) { + case CPU_DEAD: + case CPU_ONLINE: + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + break; + } + return NOTIFY_OK; +} + +static struct notifier_block __refdata cpu_hotplug_notifier = { + .notifier_call = cpu_hotplug_notify, +}; +#endif + +int imx7d_enable_rcosc(void) +{ + void __iomem *anatop_base = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + u32 val; + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + /* set RC-OSC freq and turn it on */ + writel_relaxed(0x1 << XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT, + anatop_base + XTALOSC_CTRL_24M + REG_SET); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait at least 4ms according to hardware design */ + mdelay(6); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + + return 0; +} + +int __init imx7d_cpuidle_init(void) +{ + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + + MX7_CPUIDLE_OCRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - + ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->vbase = (phys_addr_t) wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + + cpuidle_pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + cpuidle_pm_info->ddrc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + cpuidle_pm_info->iomuxc_gpr_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + cpuidle_pm_info->gic_dist_base.pbase = MX7D_GIC_BASE_ADDR; + cpuidle_pm_info->gic_dist_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + imx7d_cpuidle_gic_base = ioremap(MX7D_GIC_BASE_ADDR, MX7D_GIC_SIZE); + + imx7d_enable_rcosc(); + +#ifdef CONFIG_HOTPLUG_CPU + register_hotcpu_notifier(&cpu_hotplug_notifier); +#endif + /* code size should include cpuidle_pm_info size */ + imx7d_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + + sizeof(*cpuidle_pm_info), + &imx7d_low_power_idle, + MX7_CPUIDLE_OCRAM_SIZE - sizeof(*cpuidle_pm_info)); + + return cpuidle_register(&imx7d_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c new file mode 100644 index 00000000000000..924a19c1632108 --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +static int imx7ulp_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + if (index == 1) + imx7ulp_set_lpm(WAIT); + else + imx7ulp_set_lpm(STOP); + + cpu_do_idle(); + + imx7ulp_set_lpm(RUN); + + return index; +} + +static struct cpuidle_driver imx7ulp_cpuidle_driver = { + .name = "imx7ulp_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx7ulp_enter_wait, + .name = "WAIT", + .desc = "PSTOP2", + }, + /* STOP */ + { + .exit_latency = 100, + .target_residency = 150, + .enter = imx7ulp_enter_wait, + .name = "STOP", + .desc = "PSTOP1", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx7ulp_cpuidle_init(void) +{ + return cpuidle_register(&imx7ulp_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h index f9140128ba0518..14eeb339e76b9d 100644 --- a/arch/arm/mach-imx/cpuidle.h +++ b/arch/arm/mach-imx/cpuidle.h @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2016 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -14,7 +14,12 @@ extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); extern int imx6sl_cpuidle_init(void); +extern int imx6sll_cpuidle_init(void); extern int imx6sx_cpuidle_init(void); +extern int imx6ul_cpuidle_init(void); +extern int imx7d_cpuidle_init(void); +extern int imx7d_enable_rcosc(void); +extern int imx7ulp_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) { @@ -28,8 +33,28 @@ static inline int imx6sl_cpuidle_init(void) { return 0; } +static inline int imx6sll_cpuidle_init(void) +{ + return 0; +} static inline int imx6sx_cpuidle_init(void) { return 0; } +static inline int imx6ul_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_enable_rcosc(void) +{ + return 0; +} +static inline int imx7ulp_cpuidle_init(void) +{ + return 0; +} #endif diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S new file mode 100644 index 00000000000000..2a12669a3bef1e --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx6.S @@ -0,0 +1,1079 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0x0c +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAARCR 0x400 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC1_MPZQHWCTRL 0x4800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC1_MPODTCTRL 0x4818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC1_MPDGCTRL0 0x483c +#define MMDC0_MPMUR0 0x8b8 +#define MMDC1_MPMUR0 0x48b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 + +#define IMX6QP_REVISION_ID 0x630100 +#define ANADIG_DIGPROG 0x260 + +.extern iram_tlb_phys_addr + +.globl mx6_ddr3_freq_change_start +.globl mx6_ddr3_freq_change_end + + .align 3 + + .macro is_mx6qp + + /* check if the SOC is i.MX6QP */ + ldr r0, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r1, [r0, #ANADIG_DIGPROG] + ldr r2, =IMX6QP_REVISION_ID + cmp r1, r2 + + .endm + + .macro switch_to_528MHz + + /* check if periph_clk_sel is already set */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 20) + str r0, [r6, #CCM_CBCDR] + + /* + * set the AHB dividers before the switch, + * don't change AXI clock divider, + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528 + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch3: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch3 + + b switch_pre_periph_clk_528 + +set_ahb_podf_before_switch: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528_1 + +switch_pre_periph_clk_528: + + /* now switch pre_periph_clk to PLL2_528MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch4: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch4 + + .endm + + .macro switch_to_400MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch1 + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch5: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch5 + + b switch_pre_periph_clk_400 + +set_ahb_podf_before_switch1: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_1 + +switch_pre_periph_clk_400: + + /* now switch pre_periph_clk to PFD_400MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + orr r0, r0, #(0x4 << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch6: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch6 + + /* + * change AHB divider so that we are at 400/3=133MHz. + * don't change AXI clock divider. + * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_2 + + .endm + + .macro switch_to_50MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq switch_pre_periph_clk_50 + + /* + * set the periph_clk to be sourced from PLL2_PFD_200M + * change periph_clk to be sourced from pll3_clk. + * ensure PLL3 is the source and set the divider to 1. + */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch_50 + +switch_pre_periph_clk_50: + + /* now switch pre_periph_clk to PFD_200MHz. */ + ldr r0, [r6, #CCM_CBCMR] + orr r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* + * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x18 << 16) + orr r0, r0, #(0x3 << 16) + + /* + * if changing AHB divider remember to change + * the IPGPER divider too below. + */ + orr r0, r0, #0x1d00 + str r0, [r6, #CCM_CBCDR] + +wait_div_update_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update_50 + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch2 + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + orr r0, r0, #(1 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch1 + + /* change all the dividers to 1. */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(1 << 8) + str r0, [r6, #CCM_CBCDR] + + /* Wait for the divider to change. */ +wait_div_update: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_ddr3_freq_change + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx6_ddr3_freq_change) + +mx6_ddr3_freq_change_start: + stmfd sp!, {r4-r12} + + /* + * r5 -> mmdc_base + * r6 -> ccm_base + * r7 -> iomux_base + * r12 -> l2_base + */ + mov r4, r0 + mov r8, r1 + mov r9, r2 + mov r11, r3 + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* + * Make sure the L2 buffers are drained. + * Sync operation on L2 drains the buffers. + */ + ldr r12, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r1, [r12, #L2_CACHE_SYNC] + cmp r1, #0x0 + bne wait_for_l2_to_idle + + mov r1, #0x0 + str r1, [r12, #L2_CACHE_SYNC] + + /* Disable L2. */ + str r1, [r12, #0x100] + + dsb + isb +#endif + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + + /* Now switch the TTBR. */ + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r7, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + /* Read the Original MU delay value */ + ldr r1, [r5, #MMDC0_MPMUR0] + mov r10, r1, lsr #16 + ldr r1, =0x3ff + and r10, r10, r1 + + /* disable automatic power saving. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + bic r0, r0, #(0xff << 8) + str r0, [r5, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r1, =4 +delay1: + ldr r2, =0 +cont1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay1 + + /* set CON_REG */ + ldr r0, =0x8000 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is great than + * 300MHz, skip setting bypass adopt mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge 1f + + is_mx6qp + bne 1f + /* Switch to adopt mode, set MMDC0_MAARCR bit25~26 to 2b'01 */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, #(0x01 << 25) + str r0 , [r5, #MMDC0_MAARCR] +1: + ldr r0, =0x00008050 + str r0, [r5, #MMDC0_MDSCR] + ldr r0, =0x00008058 + str r0, [r5, #MMDC0_MDSCR] + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge dll_on_mode + +dll_off_mode: + + /* if DLL is currently on, turn it off. */ + cmp r9, #1 + beq continue_dll_off_1 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r1, =10 +delay1a: + ldr r2, =0 +cont1a: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1a + sub r1, r1, #1 + cmp r1, #0 + bgt delay1a + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r1, =24000000 + cmp r4, r1 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + + /* set SBS - block ddr accesses */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r9, #1 + beq continue_dll_off_3 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208038 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00088032 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x0008803A + str r0, [r5, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r1, =4 +delay_1: + ldr r2, =0 +cont_1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont_1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay_1 + + ldr r0, [r5, #MMDC0_MDCF0] + bic r0, r0, #0xf + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MDCF0] + + ldr r0, [r5, #MMDC0_MDCF1] + bic r0, r0, #0x7 + orr r0, r0, #0x4 + str r0, [r5, #MMDC0_MDCF1] + + ldr r0, [r5, #MMDC0_MDMISC] + bic r0, r0, #(0x3 << 16) /* walat = 0x1 */ + orr r0, r0, #(0x1 << 16) + bic r0, r0, #(0x7 << 6) /* ralat = 0x2 */ + orr r0, r0, #(0x2 << 6) + str r0, [r5, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 + ldr r2, =0x3028 +update_iomux: + ldr r0, [r11, #0x0] + ldr r3, [r7, r0] + bic r3, r3, r2 + orr r3, r3, #(0x3 << 12) + orr r3, r3, #0x28 + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r0, =0x0 + ldr r2, =MMDC0_MPODTCTRL + str r0, [r5, r2] + ldr r2, =MMDC1_MPODTCTRL + str r0, [r5, r2] + + /* DQS gating disabled. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(0x1 << 29) + str r0, [r5, r2] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + lsl r10, r10, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r2, [r5, #MMDC0_MPMUR0] + orr r2, r2, #0x400 + orr r2, r2, r10 + str r2, [r5, #MMDC0_MPMUR0] + ldr r0, =MMDC1_MPMUR0 + str r2, [r5, r0] + + /* Now perform a force measure */ + ldr r0, [r5, #MMDC0_MPMUR0] + orr r0, r0, #0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(0x1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_2 + + ldr r1, =528000000 + cmp r4, r1 + beq switch_freq_528 + + switch_to_400MHz + + b continue_dll_on + +switch_freq_528: + switch_to_528MHz + +continue_dll_on: + + /* set SBS step-by-step mode. */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #( 1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r9, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r0, [r5, #MMDC0_MPZQHWCTRL] + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MPZQHWCTRL] + ldr r2, =MMDC1_MPZQHWCTRL + str r0, [r5, r2] + + /* enable DQS gating. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + /* force measure. */ + ldr r0, =0x00000800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 +update_iomux1: + ldr r0, [r11, #0x0] + ldr r3, [r11, #0x4] + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux1 + + /* config MMDC timings to 528MHz. */ + ldr r9, [r8] + add r8, r8, #8 + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r0, =0x00048031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00048039 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =4 +delay7: + ldr r2, =0 +cont7: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont7 + sub r1, r1, #1 + cmp r1, #0 + bgt delay7 + + /* reset dll. */ + ldr r0, =0x09408030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x09408038 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =100 +delay8: + ldr r2, =0 +cont8: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont8 + sub r1, r1, #1 + cmp r1, #0 + bgt delay8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, =0x00428031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00428039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* issue a zq command. */ + ldr r0, =0x04008040 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x04008048 + str r0, [r5, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r2, =0x4818 + str r3, [r5, r2] + + /* delay for while. */ + ldr r1, =40 +delay15: + ldr r2, =0 +cont15: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont15 + sub r1, r1, #1 + cmp r1, #0 + bgt delay15 + + /* enable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + orr r0, r0, #(0x55 << 8) + str r0, [r5, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r1, [r8] + sub r1, r1, #7 + add r8, r8, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r1, r9 + sub r1, r1, #7 + +update_calib: + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r0, =0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + is_mx6qp + bne 3f + /* + * Switch back to adopt_bp mode, set MMDC0_MAARCR + * bit25~26 to 2b'10. + */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, r0, #(0x2 << 25) + str r0, [r5, #MMDC0_MAARCR] +3: + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + /* MMDC0_MAPSR adopt power down enable. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] + isb + dsb +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + isb + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + isb + dsb + + /* restore registers */ + ldmfd sp!, {r4-r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6_ddr3_freq_change_end: diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S new file mode 100644 index 00000000000000..9846c05f454142 --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S @@ -0,0 +1,737 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +.globl imx6_up_ddr3_freq_change_start +.globl imx6_up_ddr3_freq_change_end + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0xc +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC0_MPMUR0 0x8b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 + +#define BUSFREQ_INFO_FREQ_OFFSET 0x0 +#define BUSFREQ_INFO_DDR_SETTINGS_OFFSET 0x4 +#define BUSFREQ_INFO_DLL_OFF_OFFSET 0x8 +#define BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET 0xc +#define BUSFREQ_INFO_MU_DELAY_OFFSET 0x10 + +.extern iram_tlb_phys_addr + + .align 3 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r7, c0, c0, 0 + ldr r8, =0xfff0 + and r7, r7, r8 + ldr r8, =0xc070 + cmp r7, r8 + + .endm + + .macro do_delay + +1: + ldr r9, =0 +2: + ldr r10, [r4, r9] + add r9, r9, #4 + cmp r9, #16 + bne 2b + sub r8, r8, #1 + cmp r8, #0 + bgt 1b + + .endm + + .macro wait_for_ccm_handshake + +3: + ldr r8, [r5, #CCM_CDHIPR] + cmp r8, #0 + bne 3b + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_50MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_50m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_50m: + + /* fabric_mmdc_podf to 7 so that mmdc is 400 / 8 = 50MHz */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r5, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r5, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r5, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + +/* + * imx6_up_ddr3_freq_change + * Below code can be used by i.MX6SX and i.MX6UL. + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(imx6_up_ddr3_freq_change) + +imx6_up_ddr3_freq_change_start: + stmfd sp!, {r4 - r11} + + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r2, [r0, #BUSFREQ_INFO_DLL_OFF_OFFSET] + ldr r3, [r0, #BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * make sure the L2 buffers are drained, + * sync operation on L2 drains the buffers. + */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r8, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r8, #L2_CACHE_SYNC] + + /* Disable L2. */ + mov r7, #0x0 + str r7, [r8, #0x100] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb +#endif + +skip_disable_l2: + /* disable automatic power saving. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #0x1 + str r8, [r4, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + bic r8, r8, #(0xff << 8) + str r8, [r4, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r8, =4 + do_delay + + /* set CON_REG */ + ldr r8, =0x8000 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =300000000 + cmp r8, r9 + bge dll_on_mode + +dll_off_mode: + /* if DLL is currently on, turn it off. */ + cmp r2, #1 + beq continue_dll_off_1 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =10 + do_delay + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =24000000 + cmp r8, r9 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + /* set SBS - block ddr accesses */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r2, #1 + beq continue_dll_off_3 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208038 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00088032 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x0008803A + str r8, [r4, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r8, =4 + do_delay + + ldr r8, [r4, #MMDC0_MDCF0] + bic r8, r8, #0xf + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MDCF0] + + ldr r8, [r4, #MMDC0_MDCF1] + bic r8, r8, #0x7 + orr r8, r8, #0x4 + str r8, [r4, #MMDC0_MDCF1] + + ldr r8, [r4, #MMDC0_MDMISC] + bic r8, r8, #(0x3 << 16) /* walat = 0x1 */ + orr r8, r8, #(0x1 << 16) + bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */ + orr r8, r8, #(0x2 << 6) + str r8, [r4, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 + ldr r9, =0x3028 +update_iomux: + ldr r10, [r3] + ldr r11, [r6, r10] + bic r11, r11, r9 + orr r11, r11, #(0x3 << 12) + orr r11, r11, #0x28 + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r8, =0x0 + str r8, [r4, #MMDC0_MPODTCTRL] + + /* DQS gating disabled. */ + ldr r8, [r4, #MMDC0_MPDGCTRL0] + orr r8, r8, #(1 << 29) + str r8, [r4, #MMDC0_MPDGCTRL0] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + ldr r8, [r0, #BUSFREQ_INFO_MU_DELAY_OFFSET] + lsl r8, r8, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r10, [r4, #MMDC0_MPMUR0] + orr r10, r10, #0x400 + /* Set the MU_BYP_VAL */ + orr r10, r10, r8 + str r10, [r4, #MMDC0_MPMUR0] + + /* Now perform a force measure */ + ldr r8, [r4, #MMDC0_MPMUR0] + orr r8, r8, #0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(0x1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_2 + + switch_to_400MHz + + /* set SBS step-by-step mode. */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r8, [r4, #MMDC0_MAPSR] + ands r8, r8, #(1 << 25) + bne poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r2, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r8, [r4, #MMDC0_MPZQHWCTRL] + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MPZQHWCTRL] + + /* enable DQS gating. */ + ldr r10, =MMDC0_MPDGCTRL0 + ldr r8, [r4, r10] + bic r8, r8, #(1 << 29) + str r8, [r4, r10] + + /* Now perform a force measure */ + ldr r8, =0x00000800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 +update_iomux1: + ldr r10, [r3, #0x0] + ldr r11, [r3, #0x4] + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux1 + + /* config MMDC timings to 400MHz. */ + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r7, [r1] + add r1, r1, #8 + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r8, =0x00028031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00028039 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =4 + do_delay + + /* reset dll. */ + ldr r8, =0x09208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x09208038 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =100 + do_delay + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r8, =0x00428031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00428039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* issue a zq command. */ + ldr r8, =0x04008040 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04008048 + str r8, [r4, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* delay for while. */ + ldr r8, =40 + do_delay + + /* enable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + orr r8, r8, #(0x55 << 8) + str r8, [r4, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r8, [r1] + sub r8, r8, #7 + add r1, r1, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r8, r7 + sub r8, r8, #7 + +update_calib: + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r8, =0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + + /* MMDC0_MAPSR adopt power down enable. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #0x01 + str r8, [r4, #MMDC0_MAPSR] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r7, =0x1 + str r7, [r8, #0x100] +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x4 + mcr p15, 0, r7, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x800 + mcr p15, 0, r7, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r7, =0x0 + mcr p15, 0, r7, c7, c1, 6 + + /* restore registers */ + ldmfd sp!, {r4 - r11} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_up_ddr3_freq_change_end: +ENDPROC(imx6_up_ddr3_freq_change) diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S new file mode 100644 index 00000000000000..9342e0d83f5e88 --- /dev/null +++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S @@ -0,0 +1,586 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_MRCTRL0 0x10 +#define DDRC_MRCTRL1 0x14 +#define DDRC_MRSTAT 0x18 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHCTL3 0x60 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_ZQCTL0 0x180 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro switch_to_below_100m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x36000000 +1: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 1b + + ldr r6, =0x1 +2: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 2b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +3: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 3b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x8 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 4b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, =0x03048001 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +6: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 6b + + ldr r7, =0x10010100 + str r7, [r5, #0x4] + + ldr r6, =24000000 + cmp r0, r6 + beq 25f + + ldr r7, =0x000B000D + str r7,[r4, #DDRC_RFSHTMG] + b 7f + +25: + ldr r7, =0x00030004 + str r7,[r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 8f +7: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +8: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 20f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 21f +20: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +21: + ldr r7, =0x1100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +9: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 9b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x820 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +10: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 10b + + ldr r7, =0x800020 + str r7, [r4, #DDRC_ZQCTL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_533m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x78 + str r7, [r3, #IOMUXC_GPR8] + orr r7, r7, #0x100 + str r7, [r3, #IOMUXC_GPR8] + + ldr r6, =0x30000000 +11: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + ldr r6, =0x1 +12: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 12b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +13: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 13b + + ldr r7, =0x03040001 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x40800020 + str r7, [r4, #DDRC_ZQCTL0] + + + ldr r7, =0x10210100 + str r7, [r5, #0x4] + + ldr r7, =0x00040046 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 22f + + ldr r7, =0x40404040 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x18181818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x40401818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 23f +22: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +23: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +14: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + ldr r7, =0x1 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x3 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +15: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 15b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +16: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 16b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x2 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r6, =0x1 +17: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 17b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +18: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 18b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x408 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +19: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 19b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x4 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7d_ddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr + .ltorg +ENDPROC(imx7d_ddr3_freq_change) diff --git a/arch/arm/mach-imx/ddrc.c b/arch/arm/mach-imx/ddrc.c new file mode 100644 index 00000000000000..9c7f627d465e70 --- /dev/null +++ b/arch/arm/mach-imx/ddrc.c @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define BM_DDRC_MSTR_DDR3 0x1 +#define BM_DDRC_MSTR_LPDDR2 0x4 +#define BM_DDRC_MSTR_LPDDR3 0x8 + +static int ddr_type; + +static int imx_ddrc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + void __iomem *ddrc_base, *reg; + u32 val; + + ddrc_base = of_iomap(np, 0); + WARN_ON(!ddrc_base); + + reg = ddrc_base + DDRC_MSTR; + /* Get ddr type */ + val = readl_relaxed(reg); + val &= (BM_DDRC_MSTR_DDR3 | BM_DDRC_MSTR_LPDDR2 + | BM_DDRC_MSTR_LPDDR3); + + switch (val) { + case BM_DDRC_MSTR_DDR3: + pr_info("DDR type is DDR3!\n"); + ddr_type = IMX_DDR_TYPE_DDR3; + break; + case BM_DDRC_MSTR_LPDDR2: + pr_info("DDR type is LPDDR2!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR2; + break; + case BM_DDRC_MSTR_LPDDR3: + pr_info("DDR type is LPDDR3!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR3; + break; + default: + break; + } + + return 0; +} + +int imx_ddrc_get_ddr_type(void) +{ + return ddr_type; +} + +static struct of_device_id imx_ddrc_dt_ids[] = { + { .compatible = "fsl,imx7-ddrc", }, + { /* sentinel */ } +}; + +static struct platform_driver imx_ddrc_driver = { + .driver = { + .name = "imx-ddrc", + .owner = THIS_MODULE, + .of_match_table = imx_ddrc_dt_ids, + }, + .probe = imx_ddrc_probe, +}; + +static int __init imx_ddrc_init(void) +{ + return platform_driver_register(&imx_ddrc_driver); +} +postcore_initcall(imx_ddrc_init); diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index b54db47f6f322d..9cdde6afd6e9b4 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -1,6 +1,7 @@ /* - * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -26,7 +27,13 @@ #include "hardware.h" #define GPC_CNTR 0x000 +#define GPC_CNTR_PCIE_PHY_PDU_SHIFT 0x7 +#define GPC_CNTR_PCIE_PHY_PDN_SHIFT 0x6 +#define GPC_CNTR_L2_PGE 22 +#define PGC_PCIE_PHY_CTRL 0x200 +#define PGC_PCIE_PHY_PDN_EN 0x1 #define GPC_IMR1 0x008 +#define GPC_PGC_MF_PDN 0x220 #define GPC_PGC_GPU_PDN 0x260 #define GPC_PGC_GPU_PUPSCR 0x264 #define GPC_PGC_GPU_PDNSCR 0x268 @@ -35,6 +42,22 @@ #define GPC_PGC_CPU_PDNSCR 0x2a8 #define GPC_PGC_SW2ISO_SHIFT 0x8 #define GPC_PGC_SW_SHIFT 0x0 +#define GPC_PGC_DISP_PGCR_OFFSET 0x240 +#define GPC_PGC_DISP_PUPSCR_OFFSET 0x244 +#define GPC_PGC_DISP_PDNSCR_OFFSET 0x248 +#define GPC_PGC_DISP_SR_OFFSET 0x24c +#define GPC_M4_LPSR 0x2c +#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 +#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT 0 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT 1 + +#define GPC_PGC_CPU_SW_SHIFT 0 +#define GPC_PGC_CPU_SW_MASK 0x3f +#define GPC_PGC_CPU_SW2ISO_SHIFT 8 +#define GPC_PGC_CPU_SW2ISO_MASK 0x3f #define IMR_NUM 4 #define GPC_MAX_IRQS (IMR_NUM * 32) @@ -42,7 +65,15 @@ #define GPU_VPU_PUP_REQ BIT(1) #define GPU_VPU_PDN_REQ BIT(0) -#define GPC_CLK_MAX 6 +#define GPC_CLK_MAX 10 +#define DEFAULT_IPG_RATE 66000000 +#define GPC_PU_UP_DELAY_MARGIN 2 + +/* for irq #74 and #75 */ +#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00 + +/* for irq #150 and #151 */ +#define GPC_ENET_WAKEUP_IRQ_MASK 0xC00000 struct pu_domain { struct generic_pm_domain base; @@ -51,9 +82,133 @@ struct pu_domain { int num_clks; }; +struct disp_domain { + struct generic_pm_domain base; + struct clk *clk[GPC_CLK_MAX]; + int num_clks; +}; + static void __iomem *gpc_base; static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM]; +static u32 gpc_mf_irqs[IMR_NUM]; +static u32 gpc_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpc_lock); +static struct notifier_block nb_pcie; +static struct pu_domain imx6q_pu_domain; +static bool pu_on; /* keep always on i.mx6qp */ +static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd); +static void _imx6q_pm_pu_power_on(struct generic_pm_domain *genpd); +static struct clk *ipg; + +void imx_gpc_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); + gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask : + gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); +} + +void imx_gpc_hold_m4_in_sleep(void) +{ + int val; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait M4 in wfi before asserting hold request */ + while (!imx_gpc_is_m4_sleeping()) + if (time_after(jiffies, timeout)) + pr_err("M4 is NOT in expected sleep!\n"); + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT); + writel_relaxed(val, gpc_base + GPC_M4_LPSR); + + timeout = jiffies + msecs_to_jiffies(500); + while (readl_relaxed(gpc_base + GPC_M4_LPSR) + & (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT)) + if (time_after(jiffies, timeout)) + pr_err("Wait M4 hold ack timeout!\n"); +} + +void imx_gpc_release_m4_in_sleep(void) +{ + int val; + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT; + writel_relaxed(val, gpc_base + GPC_M4_LPSR); +} + +unsigned int imx_gpc_is_m4_sleeping(void) +{ + if (readl_relaxed(gpc_base + GPC_M4_LPSR) & + (GPC_M4_LPSR_M4_SLEEPING_MASK << + GPC_M4_LPSR_M4_SLEEPING_SHIFT)) + return 1; + + return 0; +} + +bool imx_gpc_usb_wakeup_enabled(void) +{ + if (!(cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll())) + return false; + + /* + * for SoC later than i.MX6SX, USB vbus wakeup + * only needs weak 2P5 on, stop_mode_config is + * NOT needed, so we check if is USB vbus wakeup + * is enabled(assume irq #74 and #75) to decide + * if to keep weak 2P5 on. + */ + if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +bool imx_gpc_enet_wakeup_enabled(void) +{ + if (!cpu_is_imx6q()) + return false; + + if (gpc_wake_irqs[3] & GPC_ENET_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +unsigned int imx_gpc_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_MF_PDN); +} + +static void imx_gpc_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) & + gpc_mf_irqs[i]) != 0) + return; + + pr_info("Turn off M/F mix!\n"); + /* turn off mega/fast mix */ + writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN); +} void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) { @@ -77,6 +232,14 @@ void imx_gpc_pre_suspend(bool arm_power_off) void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + _imx6q_pm_pu_power_off(&imx6q_pu_domain.base); + + /* power down the mega-fast power domain */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) && arm_power_off) + imx_gpc_mf_mix_off(); + /* Tell GPC to power off ARM core when suspend */ if (arm_power_off) imx_gpc_set_arm_power_in_lpm(arm_power_off); @@ -92,8 +255,15 @@ void imx_gpc_post_resume(void) void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + _imx6q_pm_pu_power_on(&imx6q_pu_domain.base); + /* Keep ARM core powered on for other low-power modes */ imx_gpc_set_arm_power_in_lpm(false); + /* Keep M/F mix powered on for other low-power modes */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) + writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN); for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); @@ -102,11 +272,14 @@ void imx_gpc_post_resume(void) static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int idx = d->hwirq / 32; + unsigned long flags; u32 mask; mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); /* * Do *not* call into the parent, as the GIC doesn't have any @@ -238,11 +411,102 @@ static const struct irq_domain_ops imx_gpc_domain_ops = { .free = irq_domain_free_irqs_common, }; +int imx_gpc_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *d = irq_to_desc(irq); + unsigned int idx = d->irq_data.hwirq / 32; + unsigned long flags; + u32 mask; + + mask = 1 << (d->irq_data.hwirq % 32); + spin_lock_irqsave(&gpc_lock, flags); + gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask : + gpc_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); + + return 0; +} + +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) +{ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) + return imx_gpc_mf_power_on(irq, on); + else if (cpu_is_imx7d()) + return imx_gpcv2_mf_power_on(irq, on); + else + return 0; +} +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); + +void imx_gpc_switch_pupscr_clk(bool flag) +{ + static u32 pupscr_sw2iso, pupscr_sw; + u32 ratio, pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + + if (flag) { + /* save the init clock setting IPG/2048 for IPG@66Mhz */ + pupscr_sw2iso = (pupscr >> GPC_PGC_CPU_SW2ISO_SHIFT) & + GPC_PGC_CPU_SW2ISO_MASK; + pupscr_sw = (pupscr >> GPC_PGC_CPU_SW_SHIFT) & + GPC_PGC_CPU_SW_MASK; + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case(IPG@1.5Mhz). So the sw and + * sw2iso need to be adjusted as below: + * sw_new(sw2iso_new) = (2048 * 1.5 / 66 * 32) * sw(sw2iso) + */ + ratio = 3072 / (66 * 32); + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= (ratio * pupscr_sw + 1) << GPC_PGC_CPU_SW_SHIFT | + 1 << 5 | (ratio * pupscr_sw2iso + 1) << + GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } else { + /* restore back after exit from low power idle */ + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= pupscr_sw << GPC_PGC_CPU_SW_SHIFT | + pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } +} + +static int imx_pcie_regulator_notify(struct notifier_block *nb, + unsigned long event, + void *ignored) +{ + u32 value = readl_relaxed(gpc_base + GPC_CNTR); + + switch (event) { + case REGULATOR_EVENT_PRE_DO_ENABLE: + value |= 1 << GPC_CNTR_PCIE_PHY_PDU_SHIFT; + writel_relaxed(value, gpc_base + GPC_CNTR); + break; + case REGULATOR_EVENT_PRE_DO_DISABLE: + value |= 1 << GPC_CNTR_PCIE_PHY_PDN_SHIFT; + writel_relaxed(value, gpc_base + GPC_CNTR); + writel_relaxed(PGC_PCIE_PHY_PDN_EN, + gpc_base + PGC_PCIE_PHY_CTRL); + break; + default: + break; + } + + return NOTIFY_OK; +} + static int __init imx_gpc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *parent_domain, *domain; int i; + u32 val; + u32 cpu_pupscr_sw2iso, cpu_pupscr_sw; + u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso; if (!parent) { pr_err("%s: no parent, giving up\n", node->full_name); @@ -271,12 +535,70 @@ static int __init imx_gpc_init(struct device_node *node, for (i = 0; i < IMR_NUM; i++) writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpc_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpc_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpc_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpc_mf_irqs[3]); + if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] | + gpc_mf_irqs[2] | gpc_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* clear the L2_PGE bit on i.MX6SLL */ + if (cpu_is_imx6sll()) { + val = readl_relaxed(gpc_base + GPC_CNTR); + val &= ~(1 << GPC_CNTR_L2_PGE); + writel_relaxed(val, gpc_base + GPC_CNTR); + } + /* * Clear the OF_POPULATED flag set in of_irq_init so that * later the GPC power domain driver will not be skipped. */ of_node_clear_flag(node, OF_POPULATED); + /* + * If there are CPU isolation timing settings in dts, + * update them according to dts, otherwise, keep them + * with default value in registers. + */ + cpu_pupscr_sw2iso = cpu_pupscr_sw = + cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0; + + /* Read CPU isolation setting for GPC */ + of_property_read_u32(node, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso); + of_property_read_u32(node, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso); + + /* Return if no property found in dtb */ + if ((cpu_pupscr_sw2iso | cpu_pupscr_sw + | cpu_pdnscr_iso2sw | cpu_pdnscr_iso) == 0) + return 0; + + /* Update CPU PUPSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR); + + /* Update CPU PDNSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR); + return 0; } IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); @@ -317,12 +639,19 @@ static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) /* Wait ISO + ISO2SW IPG clock cycles */ ndelay((iso + iso2sw) * 1000 / 66); + + while (readl_relaxed(gpc_base + GPC_CNTR) & GPU_VPU_PDN_REQ) + ; } static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) { struct pu_domain *pu = container_of(genpd, struct pu_domain, base); + if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + return 0; + _imx6q_pm_pu_power_off(genpd); if (pu->reg) @@ -331,18 +660,11 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) return 0; } -static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) +static void _imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) { struct pu_domain *pu = container_of(genpd, struct pu_domain, base); - int i, ret, sw, sw2iso; - u32 val; - - if (pu->reg) - ret = regulator_enable(pu->reg); - if (pu->reg && ret) { - pr_err("%s: failed to enable regulator: %d\n", __func__, ret); - return ret; - } + int i; + u32 val, ipg_rate = clk_get_rate(ipg); /* Enable reset clocks for all devices in the PU domain */ for (i = 0; i < pu->num_clks; i++) @@ -351,26 +673,108 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) /* Gate off PU domain when GPU/VPU when powered down */ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); - /* Read ISO and ISO2SW power down delays */ - val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); - sw = val & 0x3f; - sw2iso = (val >> 8) & 0x3f; - /* Request GPC to power up GPU/VPU */ val = readl_relaxed(gpc_base + GPC_CNTR); val |= GPU_VPU_PUP_REQ; writel_relaxed(val, gpc_base + GPC_CNTR); - /* Wait ISO + ISO2SW IPG clock cycles */ - ndelay((sw + sw2iso) * 1000 / 66); + while (readl_relaxed(gpc_base + GPC_CNTR) & GPU_VPU_PUP_REQ) + ; + /* Wait power switch done */ + udelay(2 * DEFAULT_IPG_RATE / ipg_rate + + GPC_PU_UP_DELAY_MARGIN); /* Disable reset clocks for all devices in the PU domain */ for (i = 0; i < pu->num_clks; i++) clk_disable_unprepare(pu->clk[i]); +} + +static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) +{ + struct pu_domain *pu = container_of(genpd, struct pu_domain, base); + int ret; + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0 + && &imx6q_pu_domain == pu) { + if (!pu_on) + pu_on = true; + else + return 0; + } + + if (pu->reg) + ret = regulator_enable(pu->reg); + if (pu->reg && ret) { + pr_err("%s: failed to enable regulator: %d\n", __func__, ret); + return ret; + } + + _imx6q_pm_pu_power_on(genpd); return 0; } +static int imx_pm_dispmix_on(struct generic_pm_domain *genpd) +{ + struct disp_domain *disp = container_of(genpd, struct disp_domain, base); + u32 val = readl_relaxed(gpc_base + GPC_CNTR); + int i; + u32 ipg_rate = clk_get_rate(ipg); + + if ((cpu_is_imx6sl() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) { + + /* Enable reset clocks for all devices in the disp domain */ + for (i = 0; i < disp->num_clks; i++) + clk_prepare_enable(disp->clk[i]); + + writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); + writel_relaxed(0x20 | val, gpc_base + GPC_CNTR); + while (readl_relaxed(gpc_base + GPC_CNTR) & 0x20) + ; + + writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET); + + /* Wait power switch done */ + udelay(2 * DEFAULT_IPG_RATE / ipg_rate + + GPC_PU_UP_DELAY_MARGIN); + + /* Disable reset clocks for all devices in the disp domain */ + for (i = 0; i < disp->num_clks; i++) + clk_disable_unprepare(disp->clk[i]); + } + return 0; +} + +static int imx_pm_dispmix_off(struct generic_pm_domain *genpd) +{ + struct disp_domain *disp = container_of(genpd, struct disp_domain, base); + u32 val = readl_relaxed(gpc_base + GPC_CNTR); + int i; + + if ((cpu_is_imx6sl() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) { + + /* Enable reset clocks for all devices in the disp domain */ + for (i = 0; i < disp->num_clks; i++) + clk_prepare_enable(disp->clk[i]); + + writel_relaxed(0xFFFFFFFF, + gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET); + writel_relaxed(0xFFFFFFFF, + gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET); + writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); + writel_relaxed(0x10 | val, gpc_base + GPC_CNTR); + while (readl_relaxed(gpc_base + GPC_CNTR) & 0x10) + ; + + /* Disable reset clocks for all devices in the disp domain */ + for (i = 0; i < disp->num_clks; i++) + clk_disable_unprepare(disp->clk[i]); + } + return 0; +} + static struct generic_pm_domain imx6q_arm_domain = { .name = "ARM", }; @@ -390,14 +794,18 @@ static struct pu_domain imx6q_pu_domain = { }, }; -static struct generic_pm_domain imx6sl_display_domain = { - .name = "DISPLAY", +static struct disp_domain imx6s_display_domain = { + .base = { + .name = "DISPLAY", + .power_off = imx_pm_dispmix_off, + .power_on = imx_pm_dispmix_on, + }, }; static struct generic_pm_domain *imx_gpc_domains[] = { &imx6q_arm_domain, &imx6q_pu_domain.base, - &imx6sl_display_domain, + &imx6s_display_domain.base, }; static struct genpd_onecell_data imx_gpc_onecell_data = { @@ -408,30 +816,61 @@ static struct genpd_onecell_data imx_gpc_onecell_data = { static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) { struct clk *clk; - int i, ret; + bool is_off; + int pu_clks, disp_clks, ipg_clks = 1; + int i = 0, k = 0, ret; imx6q_pu_domain.reg = pu_reg; - for (i = 0; ; i++) { + if ((cpu_is_imx6sl() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2)) { + pu_clks = 2 ; + disp_clks = 5; + } else if (cpu_is_imx6sx()) { + pu_clks = 1; + disp_clks = 7; + } else { + pu_clks = 6; + disp_clks = 0; + } + + /* Get pu domain clks */ + for (i = 0; i < pu_clks ; i++) { clk = of_clk_get(dev->of_node, i); if (IS_ERR(clk)) break; - if (i >= GPC_CLK_MAX) { - dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX); - goto clk_err; - } imx6q_pu_domain.clk[i] = clk; } imx6q_pu_domain.num_clks = i; - /* Enable power always in case bootloader disabled it. */ - imx6q_pm_pu_power_on(&imx6q_pu_domain.base); + ipg = of_clk_get(dev->of_node, pu_clks); + if (IS_ERR(ipg)) + goto err; - if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) - return 0; + /* Get disp domain clks */ + for (i = pu_clks + ipg_clks; i < pu_clks + ipg_clks + disp_clks; + i++) { + clk = of_clk_get(dev->of_node, i); + if (IS_ERR(clk)) + break; + imx6s_display_domain.clk[k++] = clk; + } + imx6s_display_domain.num_clks = k; + + is_off = IS_ENABLED(CONFIG_PM); + if (is_off && !(cpu_is_imx6q() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)) { + _imx6q_pm_pu_power_off(&imx6q_pu_domain.base); + } else { + /* + * Enable power if compiled without CONFIG_PM in case the + * bootloader disabled it. + */ + imx6q_pm_pu_power_on(&imx6q_pu_domain.base); + } for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++) - pm_genpd_init(imx_gpc_domains[i], NULL, false); + pm_genpd_init(imx_gpc_domains[i], NULL, is_off); ret = of_genpd_add_provider_onecell(dev->of_node, &imx_gpc_onecell_data); @@ -442,10 +881,7 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) power_off: imx6q_pm_pu_power_off(&imx6q_pu_domain.base); -clk_err: - while (i--) - clk_put(imx6q_pu_domain.clk[i]); - imx6q_pu_domain.reg = NULL; +err: return -EINVAL; } @@ -453,6 +889,7 @@ static int imx_gpc_probe(struct platform_device *pdev) { struct regulator *pu_reg; int ret; + u32 bypass = 0; /* bail out if DT too old and doesn't provide the necessary info */ if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells")) @@ -463,11 +900,46 @@ static int imx_gpc_probe(struct platform_device *pdev) pu_reg = NULL; if (IS_ERR(pu_reg)) { ret = PTR_ERR(pu_reg); - dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret); + if (ret == -EPROBE_DEFER) + dev_warn(&pdev->dev, "pu regulator not ready, retry\n"); + else + dev_err(&pdev->dev, "failed to get pu regulator: %d\n", + ret); return ret; } - return imx_gpc_genpd_init(&pdev->dev, pu_reg); + if (of_property_read_u32(pdev->dev.of_node, "fsl,ldo-bypass", &bypass)) + dev_warn(&pdev->dev, + "no fsl,ldo-bypass found!\n"); + /* We only bypass pu since arm and soc has been set in u-boot */ + if (pu_reg && bypass) + regulator_allow_bypass(pu_reg, true); + + if (cpu_is_imx6sx()) { + struct regulator *pcie_reg; + + pcie_reg = devm_regulator_get(&pdev->dev, "pcie-phy"); + if (IS_ERR(pcie_reg)) { + ret = PTR_ERR(pcie_reg); + dev_info(&pdev->dev, "pcie regulator not ready.\n"); + return ret; + } + nb_pcie.notifier_call = &imx_pcie_regulator_notify; + + ret = regulator_register_notifier(pcie_reg, &nb_pcie); + if (ret) { + dev_err(&pdev->dev, + "pcie regulator notifier request failed\n"); + return ret; + } + } + + ret = imx_gpc_genpd_init(&pdev->dev, pu_reg); + if (ret) + return ret; + dev_info(&pdev->dev, "Registered imx-gpc\n"); + + return 0; } static const struct of_device_id imx_gpc_dt_ids[] = { diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c new file mode 100644 index 00000000000000..60070e57633abe --- /dev/null +++ b/arch/arm/mach-imx/gpcv2.c @@ -0,0 +1,1052 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +#define IMR_NUM 4 +#define GPC_MAX_IRQS (IMR_NUM * 32) +#define GPC_LPCR_A7_BSC 0x0 +#define GPC_LPCR_A7_AD 0x4 +#define GPC_LPCR_M4 0x8 +#define GPC_SLPCR 0x14 +#define GPC_MLPCR 0x20 +#define GPC_PGC_ACK_SEL_A7 0x24 +#define GPC_MISC 0x2c +#define GPC_IMR1_CORE0 0x30 +#define GPC_IMR1_CORE1 0x40 +#define GPC_IMR1_M4 0x50 +#define GPC_SLOT0_CFG 0xb0 +#define GPC_PGC_CPU_MAPPING 0xec +#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_PU_PGC_SW_PUP_REQ 0xf8 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PU_PGC_SW_PDN_REQ 0x104 +#define GPC_GTOR 0x124 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_C0_PUPSCR 0x804 +#define GPC_PGC_SCU_TIMING 0x890 +#define GPC_PGC_C1 0x840 +#define GPC_PGC_C1_PUPSCR 0x844 +#define GPC_PGC_SCU 0x880 +#define GPC_PGC_FM 0xa00 +#define GPC_PGC_MIPI_PHY 0xc00 +#define GPC_PGC_PCIE_PHY 0xc40 +#define GPC_PGC_USB_OTG1_PHY 0xc80 +#define GPC_PGC_USB_OTG2_PHY 0xcc0 +#define GPC_PGC_USB_HSIC_PHY 0xd00 + +#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000 +#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000 +#define BM_LPCR_A7_BSC_LPM1 0xc +#define BM_LPCR_A7_BSC_LPM0 0x3 +#define BP_LPCR_A7_BSC_LPM1 2 +#define BP_LPCR_A7_BSC_LPM0 0 +#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000 +#define BM_SLPCR_EN_DSM 0x80000000 +#define BM_SLPCR_RBC_EN 0x40000000 +#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000 +#define BM_SLPCR_VSTBY 0x4 +#define BM_SLPCR_SBYOS 0x2 +#define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000 +#define BM_LPCR_A7_AD_L2PGE 0x10000 +#define BM_LPCR_A7_AD_EN_C1_PUP 0x800 +#define BM_LPCR_A7_AD_EN_C1_IRQ_PUP 0x400 +#define BM_LPCR_A7_AD_EN_C0_PUP 0x200 +#define BM_LPCR_A7_AD_EN_C0_IRQ_PUP 0x100 +#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10 +#define BM_LPCR_A7_AD_EN_C1_PDN 0x8 +#define BM_LPCR_A7_AD_EN_C1_WFI_PDN 0x4 +#define BM_LPCR_A7_AD_EN_C0_PDN 0x2 +#define BM_LPCR_A7_AD_EN_C0_WFI_PDN 0x1 + +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 +#define BM_GPC_PGC_PCG 0x1 +#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80 + +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000 +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000 +#define BM_GPC_MLPCR_MEMLP_CTL_DIS 0x1 + +#define BP_LPCR_A7_BSC_IRQ_SRC 28 + +#define MAX_SLOT_NUMBER 10 +#define A7_LPM_WAIT 0x5 +#define A7_LPM_STOP 0xa + +enum imx_gpc_slot { + CORE0_A7, + CORE1_A7, + SCU_A7, + FAST_MEGA_MIX, + MIPI_PHY, + PCIE_PHY, + USB_OTG1_PHY, + USB_OTG2_PHY, + USB_HSIC_PHY, + CORE0_M4, +}; + +static void __iomem *gpc_base; +static u32 gpcv2_wake_irqs[IMR_NUM]; +static u32 gpcv2_saved_imrs[IMR_NUM]; +static u32 gpcv2_saved_imrs_m4[IMR_NUM]; +static u32 gpcv2_mf_irqs[IMR_NUM]; +static u32 gpcv2_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpcv2_lock); +static struct notifier_block nb_mipi, nb_pcie, nb_usb_hsic; + +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +{ + unsigned int idx = d->hwirq / 32; + unsigned long flags; + u32 mask; + + BUG_ON(idx >= IMR_NUM); + + mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = on ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_mask_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~0, reg_imr1 + i * 4); + } +} + +void imx_gpcv2_restore_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); +} + +void imx_gpcv2_hwirq_unmask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val &= ~(1 << hwirq % 32); + writel_relaxed(val, reg); +} + +void imx_gpcv2_hwirq_mask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val |= 1 << (hwirq % 32); + writel_relaxed(val, reg); +} + +static void imx_gpcv2_irq_unmask(struct irq_data *d) +{ + imx_gpcv2_hwirq_unmask(d->hwirq); + irq_chip_unmask_parent(d); +} + +static void imx_gpcv2_irq_mask(struct irq_data *d) +{ + imx_gpcv2_hwirq_mask(d->hwirq); + irq_chip_mask_parent(d); +} + +void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core, + bool mode, bool ack) +{ + u32 val; + + if (index >= MAX_SLOT_NUMBER) + pr_err("Invalid slot index!\n"); + /* set slot */ + writel_relaxed(readl_relaxed(gpc_base + GPC_SLOT0_CFG + index * 4) | + ((mode + 1) << (m_core * 2)), + gpc_base + GPC_SLOT0_CFG + index * 4); + + if (ack) { + /* set ack */ + val = readl_relaxed(gpc_base + GPC_PGC_ACK_SEL_A7); + /* clear dummy ack */ + val &= ~(1 << (15 + (mode ? 16 : 0))); + val |= 1 << (m_core + (mode ? 16 : 0)); + writel_relaxed(val, gpc_base + GPC_PGC_ACK_SEL_A7); + } +} + +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode) +{ + unsigned long flags; + u32 val1, val2; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val1 = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val2 = readl_relaxed(gpc_base + GPC_SLPCR); + + /* all cores' LPM settings must be same */ + val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1); + + val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + + val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + /* + * GPC: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_IRQ. + * 2) Software should then unmask IRQ #32 in GPC before setting GPC + * Low-Power mode. + * 3) Software should mask IRQ #32 right after GPC Low-Power mode + * is set. + */ + switch (mode) { + case WAIT_CLOCKED: + imx_gpcv2_hwirq_unmask(0); + break; + case WAIT_UNCLOCKED: + val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_ON: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_OFF: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_SBYOS; + val2 |= BM_SLPCR_VSTBY; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + default: + return; + } + writel_relaxed(val1, gpc_base + GPC_LPCR_A7_BSC); + writel_relaxed(val2, gpc_base + GPC_SLPCR); + + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE); + if (pdn) + val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE; + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); +} + +void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) +{ + u32 val = readl_relaxed(gpc_base + offset) & (~BM_GPC_PGC_PCG); + + if (enable) + val |= BM_GPC_PGC_PCG; + + writel_relaxed(val, gpc_base + offset); +} + +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + while ((readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)) & + BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); +} + +void imx_gpcv2_set_cpu_power_gate_by_wfi(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + if (cpu == 0) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + val |= BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + val &= ~(BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP); + } + } + if (cpu == 1) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); + val &= ~(BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP); + } + } + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + if (cpu == 0) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP); + } + if (cpu == 1) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP); + } + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn) +{ + unsigned long flags; + u32 cpu; + + for_each_possible_cpu(cpu) + imx_gpcv2_set_cpu_power_gate_by_lpm(cpu, pdn); + + spin_lock_irqsave(&gpcv2_lock, flags); + + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C0); + if (num_online_cpus() > 1) + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C1); + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_SCU); + imx_gpcv2_set_plat_power_gate_by_lpm(pdn); + + if (pdn) { + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(2, CORE1_A7, false, false); + imx_gpcv2_set_slot_ack(3, SCU_A7, false, true); + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(6, CORE1_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + } else { + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 0 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 2 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 3 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 6 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 7 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 8 * 0x4); + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + imx_gpcv2_enable_rbc(false); + } + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_mix_phy_gate_by_lpm(u32 pdn_index, u32 pup_index) +{ + /* set power down slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2), + gpc_base + GPC_SLOT0_CFG + pdn_index * 4); + + /* set power up slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2 + 1), + gpc_base + GPC_SLOT0_CFG + pup_index * 4); +} + +unsigned int imx_gpcv2_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_FM); +} + +static void imx_gpcv2_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpcv2_wake_irqs[i] | gpcv2_mf_request_on[i]) & + gpcv2_mf_irqs[i]) != 0) + return; + + pr_info("Turn off Mega/Fast mix in DSM\n"); + imx_gpcv2_set_slot_ack(1, FAST_MEGA_MIX, false, false); + imx_gpcv2_set_slot_ack(5, FAST_MEGA_MIX, true, false); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_FM); +} + +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *desc = irq_to_desc(irq); + unsigned long hwirq = desc->irq_data.hwirq; + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask = 1 << (hwirq % 32); + + BUG_ON(idx >= IMR_NUM); + + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_mf_request_on[idx] = on ? gpcv2_mf_request_on[idx] | mask : + gpcv2_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpcv2_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_RBC_EN; + val |= enable ? BM_SLPCR_RBC_EN : 0; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + /* configure RBC count */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_REG_BYPASS_COUNT; + val |= enable ? BM_SLPCR_REG_BYPASS_COUNT : 0; + writel(val, gpc_base + GPC_SLPCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpcv2_restore_all(); +} + + +void imx_gpcv2_pre_suspend(bool arm_power_off) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + if (arm_power_off) { + imx_gpcv2_set_lpm_mode(STOP_POWER_OFF); + /* enable core0 power down/up with low power mode */ + imx_gpcv2_set_cpu_power_gate_by_lpm(0, true); + /* enable plat power down with low power mode */ + imx_gpcv2_set_plat_power_gate_by_lpm(true); + + /* + * To avoid confuse, we use slot 0~4 for power down, + * slot 5~9 for power up. + * + * Power down slot sequence: + * Slot0 -> CORE0 + * Slot1 -> Mega/Fast MIX + * Slot2 -> SCU + * + * Power up slot sequence: + * Slot5 -> Mega/Fast MIX + * Slot6 -> SCU + * Slot7 -> CORE0 + */ + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + imx_gpcv2_set_slot_ack(2, SCU_A7, false, true); + + if ((!imx_src_is_m4_enabled()) || + (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop())) + imx_gpcv2_mf_mix_off();; + + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + + /* enable core0, scu */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU); + } else { + imx_gpcv2_set_lpm_mode(STOP_POWER_ON); + } + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr1 + i * 4); + } +} + +void imx_gpcv2_enable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs_m4[i] = readl_relaxed(reg_imr2 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr2 + i * 4); + } +} + +void imx_gpcv2_disable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs_m4[i], reg_imr2 + i * 4); +} + +void imx_gpcv2_post_resume(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i, val; + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + imx_gpcv2_set_cpu_power_gate_by_lpm(0, false); + imx_gpcv2_set_plat_power_gate_by_lpm(false); + + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_FM); + for (i = 0; i < MAX_SLOT_NUMBER; i++){ + if (i == 1 || i == 5) /* skip slts m4 uses */ + continue; + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + i * 0x4); + } + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); +} + +static struct irq_chip imx_gpcv2_chip = { + .name = "GPCV2", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = imx_gpcv2_irq_mask, + .irq_unmask = imx_gpcv2_irq_unmask, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_wake = imx_gpcv2_irq_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = irq_chip_set_affinity_parent, +#endif +}; + +static int imx_gpcv2_domain_xlate(struct irq_domain *domain, + struct device_node *controller, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (irq_domain_get_of_node(domain) != controller) + return -EINVAL; /* Shouldn't happen, really... */ + if (intsize != 3) + return -EINVAL; /* Not GIC compliant */ + if (intspec[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + *out_hwirq = intspec[1]; + *out_type = intspec[2]; + return 0; +} + +static int imx_gpcv2_domain_alloc(struct irq_domain *domain, + unsigned int irq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; + int i; + + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1]; + if (hwirq >= GPC_MAX_IRQS) + return -EINVAL; /* Can't deal with this */ + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, + &imx_gpcv2_chip, NULL); + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = hwirq; + parent_fwspec.param[2] = fwspec->param[2]; + + return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, + &parent_fwspec); +} + +static struct irq_domain_ops imx_gpcv2_domain_ops = { + .xlate = imx_gpcv2_domain_xlate, + .alloc = imx_gpcv2_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int imx_usb_hsic_regulator_notify(struct notifier_block *nb, + unsigned long event, + void *ignored) +{ + u32 val = 0; + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val | BIT(6), gpc_base + GPC_PGC_CPU_MAPPING); + + switch (event) { + case REGULATOR_EVENT_PRE_DO_ENABLE: + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ); + writel_relaxed(val | BIT(4), gpc_base + GPC_PU_PGC_SW_PUP_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ) & BIT(4)) + ; + break; + case REGULATOR_EVENT_PRE_DO_DISABLE: + /* only disable phy need to set PGC bit, enable does NOT need */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_USB_HSIC_PHY); + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ); + writel_relaxed(val | BIT(4), gpc_base + GPC_PU_PGC_SW_PDN_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ) & BIT(4)) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_USB_HSIC_PHY); + break; + default: + break; + } + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val & ~BIT(6), gpc_base + GPC_PGC_CPU_MAPPING); + + return NOTIFY_OK; +} + +static int imx_mipi_regulator_notify(struct notifier_block *nb, + unsigned long event, + void *ignored) +{ + u32 val = 0; + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val | BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); + + switch (event) { + case REGULATOR_EVENT_AFT_DO_ENABLE: + /* + * For imx7d pcie phy, VDD18 turn on time has to wait + * at least 0.1 .s after VDD10 turns on. + */ + udelay(1); + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ); + writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PUP_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ) & BIT(0)) + ; + break; + case REGULATOR_EVENT_PRE_DO_DISABLE: + /* only disable phy need to set PGC bit, enable does NOT need */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_MIPI_PHY); + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ); + writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PDN_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ) & BIT(0)) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_MIPI_PHY); + /* + * For imx7d pcie phy, VDD18 turn off time has to advance + * at least 0.1 .s before VDD10 turns off. + */ + udelay(1); + break; + default: + break; + } + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val & ~BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); + + return NOTIFY_OK; +} + +static int imx_pcie_regulator_notify(struct notifier_block *nb, + unsigned long event, + void *ignored) +{ + u32 val = 0; + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val | BIT(3), gpc_base + GPC_PGC_CPU_MAPPING); + + switch (event) { + case REGULATOR_EVENT_AFT_DO_ENABLE: + /* + * For imx7d pcie phy, VDD18 turn on time has to wait + * at least 0.1 .s after VDD10 turns on. + */ + udelay(1); + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ); + writel_relaxed(val | BIT(1), gpc_base + GPC_PU_PGC_SW_PUP_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ) & BIT(1)) + ; + break; + case REGULATOR_EVENT_PRE_DO_DISABLE: + /* only disable phy need to set PGC bit, enable does NOT need */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_PCIE_PHY); + val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ); + writel_relaxed(val | BIT(1), gpc_base + GPC_PU_PGC_SW_PDN_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ) & BIT(1)) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_PCIE_PHY); + /* + * For imx7d pcie phy, VDD18 turn off time has to advance + * at least 0.1 .s before VDD10 turns off. + */ + udelay(1); + break; + default: + break; + } + + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val & ~BIT(3), gpc_base + GPC_PGC_CPU_MAPPING); + + return NOTIFY_OK; +} + +static int __init imx_gpcv2_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + int i, val; + + if (!parent) { + pr_err("%s: no parent, giving up\n", node->full_name); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%s: unable to obtain parent domain\n", node->full_name); + return -ENXIO; + } + + gpc_base = of_iomap(node, 0); + if (WARN_ON(!gpc_base)) + return -ENOMEM; + + domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, + node, &imx_gpcv2_domain_ops, + NULL); + if (!domain) { + iounmap(gpc_base); + return -ENOMEM; + } + + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) { + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE0 + i * 4); + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE1 + i * 4); + } + /* + * Due to hardware design requirement, need to make sure GPR + * interrupt(#32) is unmasked during RUN mode to avoid entering + * DSM by mistake. + */ + writel_relaxed(~0x1, gpc_base + GPC_IMR1_CORE0); + + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx7d()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpcv2_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpcv2_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpcv2_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpcv2_mf_irqs[3]); + if (!(gpcv2_mf_irqs[0] | gpcv2_mf_irqs[1] | + gpcv2_mf_irqs[2] | gpcv2_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); + + return 0; +} + +/* + * We cannot use the IRQCHIP_DECLARE macro that lives in + * drivers/irqchip, so we're forced to roll our own. Not very nice. + */ +OF_DECLARE_2(irqchip, imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_init); + +void __init imx_gpcv2_check_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); + if (WARN_ON(!np)) + return; + + if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { + pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); + + /* map GPC, so that at least CPUidle and WARs keep working */ + gpc_base = of_iomap(np, 0); + } +} + +static int imx_gpcv2_probe(struct platform_device *pdev) +{ + int ret; + struct regulator *mipi_reg, *pcie_reg, *usb_hsic_reg; + + if (cpu_is_imx7d()) { + mipi_reg = devm_regulator_get(&pdev->dev, "mipi-phy"); + if (IS_ERR(mipi_reg)) { + ret = PTR_ERR(mipi_reg); + dev_info(&pdev->dev, "mipi regulator not ready.\n"); + return ret; + } + nb_mipi.notifier_call = &imx_mipi_regulator_notify; + + ret = regulator_register_notifier(mipi_reg, &nb_mipi); + if (ret) { + dev_err(&pdev->dev, + "mipi regulator notifier request failed.\n"); + return ret; + } + } + + if (cpu_is_imx7d()) { + pcie_reg = devm_regulator_get(&pdev->dev, "pcie-phy"); + if (IS_ERR(pcie_reg)) { + ret = PTR_ERR(pcie_reg); + dev_info(&pdev->dev, "pcie regulator not ready.\n"); + return ret; + } + nb_pcie.notifier_call = &imx_pcie_regulator_notify; + + ret = regulator_register_notifier(pcie_reg, &nb_pcie); + if (ret) { + dev_err(&pdev->dev, + "pcie regulator notifier request failed\n"); + return ret; + } + + usb_hsic_reg = devm_regulator_get(&pdev->dev, "vcc"); + if (IS_ERR(usb_hsic_reg)) { + ret = PTR_ERR(usb_hsic_reg); + dev_err(&pdev->dev, "usb hsic regulator not ready.\n"); + return ret; + } + nb_usb_hsic.notifier_call = &imx_usb_hsic_regulator_notify; + + ret = regulator_register_notifier(usb_hsic_reg, &nb_usb_hsic); + if (ret) { + dev_err(&pdev->dev, + "usb hsic regulator notifier request failed\n"); + return ret; + } + } + return 0; +} + +static struct of_device_id imx_gpcv2_dt_ids[] = { + { .compatible = "fsl,imx7d-pgc" }, + { } +}; + +static struct platform_driver imx_gpcv2_driver = { + .driver = { + .name = "imx-gpcv2", + .owner = THIS_MODULE, + .of_match_table = imx_gpcv2_dt_ids, + }, + .probe = imx_gpcv2_probe, +}; + +static int __init imx_pgcv2_init(void) +{ + return platform_driver_register(&imx_gpcv2_driver); +} +subsys_initcall(imx_pgcv2_init); diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 90e10cbd8fd11d..665c596a0b76e1 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -94,13 +94,16 @@ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 - */ + * mx7d: + * CCM 0x30380000+0x010000 -> 0xf5380000+0x010000 + * ANATOP 0x30360000+0x010000 -> 0xf5360000+0x010000 + * UART1 0x30860000+0x010000 -> 0xf5860000+0x010000 +*/ #define IMX_IO_P2V(x) ( \ - (((x) & 0x80000000) >> 7) | \ (0xf4000000 + \ - (((x) & 0x50000000) >> 6) + \ - (((x) & 0x0b000000) >> 4) + \ - (((x) & 0x000fffff)))) + (((x) & 0x50000000) >> 4) + \ + (((x) & 0x0a000000) >> 4) + \ + (((x) & 0x00ffffff)))) #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) @@ -112,6 +115,9 @@ #include "mx2x.h" #include "mx21.h" #include "mx27.h" +#include "mx6.h" +#include "mx7.h" +#include "mx7ulp.h" #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 6c28d28b3c6479..5d6a5e2fe9eee7 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -27,6 +27,17 @@ diag_reg_offset: ENTRY(v7_secondary_startup) ARM_BE8(setend be) @ go BE8 if entered LE + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =0xf00 + orr r1, r1, #0xff + mov r0, r0, lsr #4 + and r0, r0, r1 + /* 0xc07 is cortex A7's ID */ + ldr r1, =0xc00 + orr r1, r1, #0x7 + cmp r0, r1 + beq secondary_startup + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index b35e99cc5e5b4f..06dab2fc1c252a 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -16,6 +16,7 @@ #include #include "common.h" +#include "hardware.h" static inline void cpu_enter_lowpower(void) { @@ -66,5 +67,7 @@ int imx_cpu_kill(unsigned int cpu) return 0; imx_enable_cpu(cpu, false); imx_set_cpu_arg(cpu, 0); + if (cpu_is_imx7d()) + imx_gpcv2_set_core1_pdn_pup_by_software(true); return 1; } diff --git a/arch/arm/mach-imx/imx6sl_low_power_idle.S b/arch/arm/mach-imx/imx6sl_low_power_idle.S new file mode 100644 index 00000000000000..978f8d1cc234fa --- /dev/null +++ b/arch/arm/mach-imx/imx6sl_low_power_idle.S @@ -0,0 +1,776 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the license, or + * (at your option) any later version. + * + * This program is distributed in teh hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x0 +#define PM_INFO_TTBR_OFFSET 0x4 +#define PM_INFO_MMDC_V_OFFSET 0x8 +#define PM_INFO_IOMUXC_V_OFFSET 0xc +#define PM_INFO_CCM_V_OFFSET 0x10 +#define PM_INFO_L2_V_OFFSET 0x14 +#define PM_INFO_ANATOP_V_OFFSET 0x18 +#define PM_INFO_IO_NUM_OFFSET 0x1c +#define PM_INFO_IO_VAL_OFFSET 0x20 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c + +.global mx6sl_lpm_wfi_start +.global mx6sl_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* + * if in audio_bus_freq_mode, skip to + * audio_mode low power setting. + */ + cmp r1, #0x1 + beq audio_mode + /* + * Now set DDR rate to 1MHz. + * DDR is from bypassed PLL2 on periph2_clk2 path. + * Set the periph2_clk2_podf to divide by 8. + */ + ldr r6, [r10, #0x14] + orr r6, r6, #0x07 + str r6, [r10, #0x14] + + /* Now set MMDC PODF to divide by 3. */ + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x10 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Set the AHB to 3MHz. AXI to 3MHz. */ + ldr r6, [r10, #0x14] + /*r12 stores the origin AHB podf value */ + mov r12, r6 + orr r6, r6, #0x1c00 + orr r6, r6, #0x70000 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Now set ARM to 24MHz. + * Move ARM to be sourced from step_clk + * after setting step_clk to 24MHz. + */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x100 + str r6, [r10, #0xc] + /*Now pll1_sw_clk to step_clk */ + ldr r6, [r10, #0x0c] + orr r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Bypass PLL1 and power it down */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, =(1 << 16) + orr r6, r6, #0x1000 + str r6, [r10, #0x04] + + /* + * Set the ARM PODF to divide by 8. + * IPG is at 1.5MHz here, we need ARM to + * run at the 12:5 ratio (WAIT mode issue). + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r11, [r10, #0x10] + ldr r6, =0x07 + str r6, [r10, #0x10] + + ccm_do_wait + + b ccm_idle_done + +audio_mode: + /* + * MMDC is sourced from pll2_200M. + * Set the mmdc_podf to div by 8 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + orr r6, r6, #0x38 + str r6, [r10, #0x14] + + ccm_do_wait + + /* + * ARM is sourced from pll2_pfd2_400M here. + * switch ARM to bypassed PLL1 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0xc] + + /* + * set the arm_podf to divide by 3 + * as IPG is at 4MHz, we cannot run + * arm clk above 9.6MHz when system + * enter WAIT mode + */ + ldr r11, [r10, #0x10] + ldr r6, =0x2 + str r6, [r10, #0x10] + + ccm_do_wait + +ccm_idle_done: + + .endm + + .macro ccm_exit_idle + + /* + * If in audio_bus_freq_mode, skip to + * audio_mode ccm restore. + */ + cmp r1, #0x1 + beq audio_ccm_restore + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* Power up PLL1 and un-bypass it. */ + ldr r6, =(1 << 12) + str r6, [r10, #0x08] + + /* Wait for PLL1 to relock */ + ldr r8, =0x0 + pll_do_wait_lock + + ldr r6, =(1 << 16) + str r6, [r10, #0x08] + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Set PLL1_sw_clk back to PLL1 */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Restore AHB/AXI back */ + str r12, [r10, #0x14] + + ccm_do_wait + + /* restore mmdc back to 24MHz*/ + ldr r6, [r10, #0x14] + bic r6, r6, #0x3f + str r6, [r10, #0x14] + + ccm_do_wait + b ccm_exit_done + +audio_ccm_restore: + /* move arm clk back to pll2_pfd2_400M */ + ldr r6, [r10, #0xc] + orr r6, r6, #0x4 + str r6, [r10, #0xc] + + /* restore mmdc podf */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, #0x8 + str r6, [r10, #0x14] + + ccm_do_wait + +ccm_exit_done: + + .endm + + .macro check_pll_state + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* + * Check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2p5 can be off and + * only enable the weak one. PLL1 will be powered + * down late, so no need to check PLL1 state. + */ + + /* sys PLL2 */ + ldr r6, [r10, #0x30] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb PLL3 */ + ldr r6, [r10, #0x10] + ands r6, r6, #(1 << 31) + bne 1f + + /* audio PLL4 */ + ldr r6, [r10, #0x70] + ands r6, r6, #(1 << 31) + bne 1f + + /* video PLL5 */ + ldr r6, [r10, #0xa0] + ands r6, r6, #(1 << 31) + bne 1f + + /* enet PLL6 */ + ldr r6, [r10, #0xe0] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb host PLL7 */ + ldr r6, [r10, #0x20] + ands r6, r6, #(1 << 31) + bne 1f + + ldr r4, =0x1 + b check_done +1: + ldr r4, =0x0 + +check_done: + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq anatop_enter_done + + /* Disable 1p1 brown out. */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, [r10, #0x110] + bic r6, r6, #0x2 + str r6, [r10, #0x110] + /* + * Set the OSC bias current to -37.5% + * to drop the power on VDDHIGH. + */ + ldr r6, [r10, #0x150] + orr r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* + * if the usb VBUS wakeup is enabled, skip + * disable main 2p5. + */ + cmp r2, #0x1 + beq anatop_enter_done + + /* Enable the week 2p5 */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x40000 + str r6, [r10, #0x130] + + /* Disable main 2p5. */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x1 + str r6, [r10, #0x130] + + /* + * Cannot diable regular bandgap + * in LDO-enable mode. The bandgap + * is required for ARM-LDO to regulate + * the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne anatop_enter_done + + /* Enable low power bandgap */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x20 + str r6, [r10, #0x260] + + /* + * Turn off the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x80 + str r6, [r10, #0x260] + + /* + * Clear the REFTTOP+SELFBIASOFF, + * self_bais circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Power down the regular bandgap */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x1 + str r6, [r10, #0x150] +anatop_enter_done: + + .endm + + .macro anatop_exit_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq skip_anatop_restore + + cmp r2, #0x1 + beq ldo2p5_not_disabled + /* + * Regular bandgap will not be disabled + * in LDO-enabled mode as it is required + * for ARM-LDO to reguulate the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne skip_bandgap_restore + + /* Power up the regular bandgap */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x1 + str r6, [r10, #0x150] + + /* wait for bandgap stable */ +3: + ldr r6, [r10, #0x150] + and r6, r6, #0x80 + cmp r6, #0x80 + bne 3b + + /* now disable bandgap self-bias circuit */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Turn on the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x80 + str r6, [r10, #0x260] + + /* Disable the low power bandgap */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x20 + str r6, [r10, #0x260] + +skip_bandgap_restore: + /* Enable main 2p5. */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x1 + str r6, [r10, #0x130] + + /* Ensure the 2p5 is up */ +5: + ldr r6, [r10, #0x130] + and r6, r6, #0x20000 + cmp r6, #0x20000 + bne 5b + + /* Disable the weak 2p5 */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x40000 + str r6, [r10, #0x130] + +ldo2p5_not_disabled: + /* + * Set the OSC bias current to max + * value for normal operation. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* Enable 1p1 brown out, */ + ldr r6, [r10, #0x110] + orr r6, r6, #0x2 + str r6, [r10, #0x110] + +skip_anatop_restore: + + .endm + + .macro disable_l1_dcache + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + dsb + isb + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power saving. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x04] + bic r7, r7, #0xff00 + str r7, [r10, #0x04] + + /* Make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + /* set SBS step-by step mode */ + ldr r7, [r10, #0x410] + orr r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro resume_mmdc + /* restore MMDC IO */ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + + ldr r6, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r7, =PM_INFO_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + /* + * Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 <<31) + bne 8b + + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* Let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x04] + orr r7, r7, #0x5500 + str r7, [r10, #0x04] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* Clear SBS - unblock DDR accesses */ + ldr r7, [r10, #0x410] + bic r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * we need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to the IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is transslated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + /* Read TTBCR and set PD0=1, N=1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N=0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0 ,r6, c1, c0, 0 + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + /* Restore ttbr */ + ldr r7, [r0, #PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* + * imx6sl_low_power_wfi code + * r0: wfi code base address + * r1: audio_bus_freq mode stat + * r2: vbus_ldo status + * r4: used for store the PLLs state + * r11: used for saving the ARM_PODF origin value + * r12: used for saving AHB_PODF origin value + */ + .align 3 +ENTRY(imx6sl_low_power_idle) + +mx6sl_lpm_wfi_start: + push {r4-r12} + + tlb_set_to_ocram + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + /* Wait for background operations to complete. */ +wait_for_l2_idle: + ldr r6, [r10, #0x730] + cmp r6, #0x0 + bne wait_for_l2_idle + + mov r6, #0x0 + str r6, [r10, #0x730] + /* disable L2 */ + str r6, [r10, #0x100] + + dsb + isb +#endif + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + /* save DDR IO settings and set to LPM mode*/ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r8, =PM_INFO_IO_VAL_OFFSET + add r8, r8, r0 + + /* imx6sl's last 3 IOs need special setting */ + sub r7, r7, #0x3 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + ldr r6, =0x1000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r5, [r8], #0x4 + str r6, [r10, r9] + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + ldr r6, =0x80000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + + + /* check the PLLs lock state */ + check_pll_state + + ccm_enter_idle + /* if in audio low power mode, no + * need to do anatop setting. + */ + cmp r1, #0x1 + beq do_wfi + anatop_enter_idle +do_wfi: + wfi + /* + * Add these nops so that the + * prefetcher will not try to get + * any instrutions from DDR. + * The prefetch depth is about 23 + * on A9, so adding 25 nops. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* + * restore the ARM PODF first to speed + * up the restore procedure + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Restore arm_clk_podf */ + str r11, [r10, #0x10] + ccm_do_wait + + /* + * if in audio low power mode, skip + * restore the anatop setting. + */ + cmp r1, #0x1 + beq skip_analog_restore + anatop_exit_idle + +skip_analog_restore: + ccm_exit_idle + resume_mmdc + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + tlb_back_to_ddr + + /* Restore register */ + pop {r4 - r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6sl_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6sll_low_power_idle.S b/arch/arm/mach-imx/imx6sll_low_power_idle.S new file mode 100644 index 00000000000000..a7e206ecbb42d7 --- /dev/null +++ b/arch/arm/mach-imx/imx6sll_low_power_idle.S @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x48 + +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x4c +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x50 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sll_lpm_wfi_start +.globl mx6sll_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sll_low_power_idle) +mx6sll_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sll_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sll_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6sx_low_power_idle.S b/arch/arm/mach-imx/imx6sx_low_power_idle.S new file mode 100644 index 00000000000000..7ddda1cd1a8fff --- /dev/null +++ b/arch/arm/mach-imx/imx6sx_low_power_idle.S @@ -0,0 +1,887 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x30 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x34 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x40 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SEMA4_P_OFFSET 0x48 +#define PM_INFO_MX6Q_SEMA4_V_OFFSET 0x4c +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sx_lpm_wfi_start +.globl mx6sx_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* only switch to RC-OSC clk after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 10f + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* only switch to RC-OSC after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 15f + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro sema4_lock + + /* lock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x1 +16: + ldrb r7, [r10, #0x6] + cmp r7, #0x0 + bne 16b + strb r6, [r10, #0x6] + + .endm + + .macro sema4_unlock + + /* unlock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x0 + strb r6, [r10, #0x6] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sx_low_power_idle) +mx6sx_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sx_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + sema4_lock + ccm_enter_idle + anatop_enter_idle + sema4_unlock + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sx_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6ul_low_power_idle.S b/arch/arm/mach-imx/imx6ul_low_power_idle.S new file mode 100644 index 00000000000000..26bb83da1a7dd9 --- /dev/null +++ b/arch/arm/mach-imx/imx6ul_low_power_idle.S @@ -0,0 +1,821 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ul_lpm_wfi_start +.globl mx6ul_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* bypass PLL1 output to OSC */ + ldr r7, [r10] + orr r7, r7, #(0x1 << 16) + str r7, [r10] + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* Unbypass PLL1 */ + ldr r7, [r10] + bic r7, r7, #(0x1 << 16) + str r7, [r10] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ul_low_power_idle */ + + .align 3 +ENTRY(imx6ul_low_power_idle) +mx6ul_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ul_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ul_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx6ull_low_power_idle.S b/arch/arm/mach-imx/imx6ull_low_power_idle.S new file mode 100644 index 00000000000000..76ceac7fae2649 --- /dev/null +++ b/arch/arm/mach-imx/imx6ull_low_power_idle.S @@ -0,0 +1,764 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ull_lpm_wfi_start +.globl mx6ull_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ull_low_power_idle */ + + .align 3 +ENTRY(imx6ull_low_power_idle) +mx6ull_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ull_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ull_lpm_wfi_end: diff --git a/arch/arm/mach-imx/imx7d_low_power_idle.S b/arch/arm/mach-imx/imx7d_low_power_idle.S new file mode 100644 index 00000000000000..1551d2ce1acf0d --- /dev/null +++ b/arch/arm/mach-imx/imx7d_low_power_idle.S @@ -0,0 +1,787 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_VBASE_OFFSET 0x0 +#define PM_INFO_PBASE_OFFSET 0x4 +#define PM_INFO_RESUME_ADDR_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xc +#define PM_INFO_PM_INFO_TTBR_OFFSET 0x10 +#define PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET 0x14 +#define PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET 0x18 +#define PM_INFO_VAL_OFFSET 0x1c +#define PM_INFO_FLAG0_OFFSET 0x20 +#define PM_INFO_FLAG1_OFFSET 0x24 +#define PM_INFO_MX7D_DDRC_P_OFFSET 0x28 +#define PM_INFO_MX7D_DDRC_V_OFFSET 0x2c +#define PM_INFO_MX7D_CCM_P_OFFSET 0x30 +#define PM_INFO_MX7D_CCM_V_OFFSET 0x34 +#define PM_INFO_MX7D_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX7D_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX7D_SRC_P_OFFSET 0x40 +#define PM_INFO_MX7D_SRC_V_OFFSET 0x44 +#define PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET 0x48 +#define PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET 0x4c +#define PM_INFO_MX7D_GPC_P_OFFSET 0x50 +#define PM_INFO_MX7D_GPC_V_OFFSET 0x54 +#define PM_INFO_MX7D_GIC_DIST_P_OFFSET 0x58 +#define PM_INFO_MX7D_GIC_DIST_V_OFFSET 0x5c + +#define MX7D_SRC_GPR1 0x74 +#define MX7D_SRC_GPR2 0x78 +#define MX7D_SRC_GPR3 0x7c +#define MX7D_SRC_GPR4 0x80 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_DBG1 0x304 +#define DDRC_DBGCAM 0x308 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 + +/* + * imx_pen_lock + * + * The reference link of Peterson's algorithm: + * http://en.wikipedia.org/wiki/Peterson's_algorithm + * + * val1 = r1 = !turn (inverted from Peterson's algorithm) + * on cpu 0: + * r2 = flag[0] (in flag0) + * r3 = flag[1] (in flag1) + * on cpu1: + * r2 = flag[1] (in flag1) + * r3 = flag[0] (in flag0) + * + */ + .macro imx_pen_lock + + mov r8, r0 + mrc p15, 0, r5, c0, c0, 5 + and r5, r5, #3 + add r6, r8, #PM_INFO_VAL_OFFSET + cmp r5, #0 + addeq r7, r8, #PM_INFO_FLAG0_OFFSET + addeq r8, r8, #PM_INFO_FLAG1_OFFSET + addne r7, r8, #PM_INFO_FLAG1_OFFSET + addne r8, r8, #PM_INFO_FLAG0_OFFSET + + mov r9, #1 + str r9, [r7] + dsb + str r5, [r6] +1: + dsb + ldr r9, [r8] + cmp r9, #1 + ldreq r9, [r6] + cmpeq r9, r5 + beq 1b + + .endm + + .macro imx_pen_unlock + + dsb + mrc p15, 0, r6, c0, c0, 5 + and r6, r6, #3 + cmp r6, #0 + addeq r7, r0, #PM_INFO_FLAG0_OFFSET + addne r7, r0, #PM_INFO_FLAG1_OFFSET + mov r9, #0 + str r9, [r7] + + .endm + + .macro disable_l1_dcache + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + +#ifdef CONFIG_SMP + clrex + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + dsb +#endif + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_enter_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + /* disable port */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PCTRL_0] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +2: + ldr r7, [r10, #DDRC_PSTAT] + ands r7, r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x36000000 +11: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +3: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 3b +4: + ldr r7, [r10, #DDRC_STAT] + ands r7, r7, #0x20 + beq 4b + + /* disable dram clk */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r10, #DDRC_PWRCTL] + + /* + * TO1.1 adds feature of DDR pads power down, + * although TO1.0 has no such function, but it is + * NOT harmful to program GPR registers for TO1.0, + * it can avoid the logic of version check in idle + * thread. + */ + ldr r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + ldr r7, =0xf0000 + str r7, [r10] + + /* delay 20us, measured by gpio */ + ldr r7, =20 +12: + subs r7, r7, #0x1 + bne 12b + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_exit_self_refresh + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10] + + ldr r7, =20 +13: + subs r7, r7, #0x1 + bne 13b + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_DDRC_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x30000000 +14: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode exited */ +5: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 5b + + /* enable auto self-refresh */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r10, #DDRC_PWRCTL] + + ldr r7, =0x1 + str r7, [r10, #DDRC_PCTRL_0] + + .endm + + .macro pll_do_wait_lock +6: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 6b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + ldr r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to OSC */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + bic r7, r7, #0x7000000 + str r7, [r10, r8] + + /* lower AXI clk from 24MHz to 3MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* lower AHB clk from 24MHz to 3MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* gate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + bic r7, r7, #0x10000000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + /* gate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb4] + /* power down ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x64] + str r7, [r10, #0xb4] + ldr r7, =0x100000 + str r7, [r10, #0x74] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power up ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x68] + ldr r8, =0x60 + pll_do_wait_lock + + ldr r7, =0x1000 + str r7, [r10, #0xb8] + ldr r8, =0xb0 + pll_do_wait_lock + + ldr r7, =0x100000 + str r7, [r10, #0x78] + ldr r8, =0x70 + pll_do_wait_lock + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + /* ungate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_CCM_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to PLL */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + orr r7, r7, #0x1000000 + str r7, [r10, r8] + + /* restore AXI clk from 3MHz to 24MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* restore AHB clk from 3MHz to 24MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* ungate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + orr r7, r7, #0x10000000 + str r7, [r10, r8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* XTAL to RC-OSC switch */ + ldr r7, [r10] + orr r7, r7, #0x1000 + str r7, [r10] + /* power down XTAL */ + ldr r7, [r10] + orr r7, r7, #0x1 + str r7, [r10] + + /* enable weak 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* disable LDO 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x1 + str r7, [r10, #0x200] + + /* disable LDO 1P0D */ + ldr r7, [r10, #0x210] + bic r7, r7, #0x1 + str r7, [r10, #0x210] + + /* disable LDO 1P2 */ + ldr r7, [r10, #0x220] + bic r7, r7, #0x1 + str r7, [r10, #0x220] + + /* switch to low power bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x400 + str r7, [r10, #0x270] + /* power down normal bandgap */ + orr r7, r7, #0x1 + str r7, [r10, #0x270] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power on normal bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x1 + str r7, [r10, #0x270] + /* switch to normal bandgap */ + bic r7, r7, #0x400 + str r7, [r10, #0x270] + + /* enable LDO 1P2 */ + ldr r7, [r10, #0x220] + orr r7, r7, #0x1 + str r7, [r10, #0x220] +7: + ldr r7, [r10, #0x220] + ands r7, #0x20000 + beq 7b + + /* enable LDO 1P0D */ + ldr r7, [r10, #0x210] + orr r7, r7, #0x1 + str r7, [r10, #0x210] +8: + ldr r7, [r10, #0x210] + ands r7, #0x20000 + beq 8b + + /* enable LDO 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x1 + str r7, [r10, #0x200] +9: + ldr r7, [r10, #0x200] + ands r7, #0x20000 + beq 9b + /* disable weak 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* power up XTAL and wait */ + ldr r7, [r10] + bic r7, r7, #0x1 + str r7, [r10] +10: + ldr r7, [r10] + ands r7, r7, #0x4 + beq 10b + /* RC-OSC to XTAL switch */ + ldr r7, [r10] + bic r7, r7, #0x1000 + str r7, [r10] + + .endm + +.extern iram_tlb_phys_addr + + .align 3 +ENTRY(imx7d_low_power_idle) + push {r0 - r12} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx7d_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* r11 is cpu id */ + mrc p15, 0, r11, c0, c0, 5 + and r11, r11, #3 + cmp r11, #0x0 + ldreq r6, =MX7D_SRC_GPR1 + ldreq r7, =MX7D_SRC_GPR2 + ldrne r6, =MX7D_SRC_GPR3 + ldrne r7, =MX7D_SRC_GPR4 + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX7D_SRC_V_OFFSET] + str r3, [r10, r6] + str r1, [r10, r7] + + disable_l1_dcache + + tlb_set_to_ocram + + /* check last to sleep */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne lpi_enter_done + + ddrc_enter_self_refresh + ccm_enter_idle + anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_GPC_V_OFFSET] + ldr r4, [r10, #MX7D_GPC_IMR1] + ldr r5, [r10, #MX7D_GPC_IMR2] + ldr r6, [r10, #MX7D_GPC_IMR3] + ldr r7, [r10, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r10, #MX7D_GPC_IMR1] + str r8, [r10, #MX7D_GPC_IMR2] + str r8, [r10, #MX7D_GPC_IMR3] + str r8, [r10, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (240us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~250uS. + */ + ldr r8, [r10, #0x14] + bic r8, r8, #(0x3f << 24) + orr r8, r8, #(0x8 << 24) + str r8, [r10, #0x14] + + /* enable the counter. */ + ldr r8, [r10, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r10, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r10, #MX7D_GPC_IMR1] + str r5, [r10, #MX7D_GPC_IMR2] + str r6, [r10, #MX7D_GPC_IMR3] + str r7, [r10, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (30usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =5 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + +lpi_enter_done: + + imx_pen_unlock + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne skip_lpi_flow + + ldr r5, =0x0 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r10, r8] + +skip_lpi_flow: + tlb_back_to_ddr + +#ifdef CONFIG_SMP + /* Turn on SMP bit. */ + mrc p15, 0, r7, c1, c0, 1 + orr r7, r7, #0x40 + mcr p15, 0, r7, c1, c0, 1 + + isb +#endif + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + /* Restore registers */ + pop {r0 - r12} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne wakeup_skip_lpi_flow + + ldr r5, =0x1 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + +wakeup_skip_lpi_flow: + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + /* Restore registers */ + mov pc, lr + .ltorg +ENDPROC(imx7d_low_power_idle) diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6.S b/arch/arm/mach-imx/lpddr2_freq_imx6.S new file mode 100644 index 00000000000000..a7f387701bfa64 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6.S @@ -0,0 +1,593 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +.globl imx6_lpddr2_freq_change_start +.globl imx6_lpddr2_freq_change_end + + .macro mx6sl_switch_to_24MHz + + /* + * Set MMDC clock to be sourced from PLL3. + * Ensure first periph2_clk2 is sourced from PLL3. + * Set the PERIPH2_CLK2_PODF to divide by 2. + */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + orr r6, r6, #0x1 + str r6, [r2, #0x14] + + /* Select PLL3 to source MMDC. */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Swtich periph2_clk_sel to run from PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch1 + + /* + * Need to clock gate the 528 PFDs before + * powering down PLL2. + * Only the PLL2_PFD2_400M should be ON + * at this time, so only clock gate that one. + */ + ldr r6, [r3, #0x100] + orr r6, r6, #0x800000 + str r6, [r3, #0x100] + + /* + * Set PLL2 to bypass state. We should be here + * only if MMDC is not sourced from PLL2. + */ + ldr r6, [r3, #0x30] + orr r6, r6, #0x10000 + str r6, [r3, #0x30] + + ldr r6, [r3, #0x30] + orr r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Ensure pre_periph2_clk_mux is set to pll2 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + str r6, [r2, #0x18] + + /* Set MMDC clock to be sourced from the bypassed PLL2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch2: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch2 + + /* + * Now move MMDC back to periph2_clk2 source. + * after selecting PLL2 as the option. + * Select PLL2 as the source. + */ + ldr r6, [r2, #0x18] + orr r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* set periph2_clk2_podf to divide by 1. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + str r6, [r2, #0x14] + + /* Now move periph2_clk to periph2_clk2 source */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch3: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch3 + + /* Now set the MMDC PODF back to 1.*/ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + str r6, [r2, #0x14] + +mmdc_podf0: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf0 + + .endm + + .macro ddr_switch_400MHz + + /* Set MMDC divider first, in case PLL3 is at 480MHz. */ + ldr r6, [r3, #0x10] + and r6, r6, #0x10000 + cmp r6, #0x10000 + beq pll3_in_bypass + + /* Set MMDC divder to divide by 2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x8 + str r6, [r2, #0x14] + +mmdc_podf: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf + +pll3_in_bypass: + /* + * Check if we are switching between + * 400Mhz <-> 100MHz.If so, we should + * try to source MMDC from PLL2_200M. + */ + cmp r1, #0 + beq not_low_bus_freq + + /* Ensure that MMDC is sourced from PLL2 mux first. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch4: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch4 + +not_low_bus_freq: + /* Now ensure periph2_clk2_sel mux is set to PLL3 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Now switch MMDC to PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch5: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch5 + + /* + * Check if PLL2 is already unlocked. + * If so do nothing with PLL2. + */ + cmp r1, #0 + beq pll2_already_on + + /* Now power up PLL2 and unbypass it. */ + ldr r6, [r3, #0x30] + bic r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Make sure PLL2 has locked.*/ +wait_for_pll_lock: + ldr r6, [r3, #0x30] + and r6, r6, #0x80000000 + cmp r6, #0x80000000 + bne wait_for_pll_lock + + ldr r6, [r3, #0x30] + bic r6, r6, #0x10000 + str r6, [r3, #0x30] + + /* + * Need to enable the 528 PFDs after + * powering up PLL2. + * Only the PLL2_PFD2_400M should be ON + * as it feeds the MMDC. Rest should have + * been managed by clock code. + */ + ldr r6, [r3, #0x100] + bic r6, r6, #0x800000 + str r6, [r3, #0x100] + +pll2_already_on: + /* + * Now switch MMDC clk back to pll2_mux option. + * Ensure pre_periph2_clk2 is set to pll2_pfd_400M. + * If switching to audio DDR freq, set the + * pre_periph2_clk2 to PLL2_PFD_200M + */ + ldr r6, =400000000 + cmp r6, r0 + bne use_pll2_pfd_200M + + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + orr r6, r6, #0x200000 + str r6, [r2, #0x18] + ldr r6, =400000000 + b cont2 + +use_pll2_pfd_200M: + ldr r6, [r2, #0x18] + orr r6, r6, #0x600000 + str r6, [r2, #0x18] + ldr r6, =200000000 + +cont2: + ldr r4, [r2, #0x14] + bic r4, r4, #0x4000000 + str r4, [r2, #0x14] + +periph2_clk_switch6: + ldr r4, [r2, #0x48] + cmp r4, #0 + bne periph2_clk_switch6 + +change_divider_only: + /* + * Calculate the MMDC divider + * based on the requested freq. + */ + ldr r4, =0 +Loop2: + sub r6, r6, r0 + cmp r6, r0 + blt Div_Found + add r4, r4, #1 + bgt Loop2 + + /* Shift divider into correct offset. */ + lsl r4, r4, #3 +Div_Found: + /* Set the MMDC PODF. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, r4 + str r6, [r2, #0x14] + +mmdc_podf1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf1 + + .endm + + .macro mmdc_clk_lower_100MHz + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r8, r5] + + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1: low_bus_freq_mode flag + */ + .align 3 +ENTRY(mx6_lpddr2_freq_change) +imx6_lpddr2_freq_change_start: + push {r4-r10} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ddr_switch_400MHz + + ldr r10,=100000000 + cmp r0, r10 + blt done + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + mx6sl_switch_to_24MHz + +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r4-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_lpddr2_freq_change_end: diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6q.S b/arch/arm/mach-imx/lpddr2_freq_imx6q.S new file mode 100644 index 00000000000000..6c9aac07df1619 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6q.S @@ -0,0 +1,765 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +.globl mx6q_lpddr2_freq_change_start +.globl mx6q_lpddr2_freq_change_end + + .macro wait_for_ccm_handshake + /* wait for div update */ +1: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne 1b + + .endm + + .macro set_mmdc_misc_ralat_2_cycles + + /* Set MMDCx_MISC[RALAT] = 2 cycles */ + ldr r6, [r8, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r8, #0x18] + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 1f + + ldr r6, [r4, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r4, #0x18] +1: + .endm + + .macro switch_to_400MHz + /* set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x9 << 8) + orr r9, r9, #(1 << 16) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check periph_clk_sel */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_400m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_400m: + + .endm + + .macro switch_to_100MHz + /* set the MMDC_DIV=4, AXI_DIV=8, AHB_DIV=8 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x1F << 16) + orr r9, r9, #(0x1D << 8) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check if periph_clk_sel is already set. */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_100m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_100m: + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 12) + orr r9, r9, #(1 << 12) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(0x7 << 27) + str r9, [r2, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r9, [r2, #CCM_CBCDR] + orr r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* change all the dividers to 1. */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + str r9, [r2, #CCM_CBCDR] + + /* Wait for the divider to change. */ + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHZ_from_pll2 + /* Change DDR freq settings from pll2_pfd2 (div 2) */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 18) + orr r9, r9, #(0x3 << 18) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + orr r9, r9, #(0x7 << 19) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro set_timings_below_100MHz_operation + set_mmdc_misc_ralat_2_cycles + + /* Adjust LPDDR2 timings for 24Mhz operation */ + ldr r5, =0x03162073 + str r5, [r8, #0xC] /* MMDC0_MDCFG0 */ + ldr r7, =0x00020482 + str r7, [r8, #0x10] /* MMDC0_MDCFG1 */ + ldr r9, =0x00000049 + str r9, [r8, #0x14] /* MMDC0_MDCFG2 */ + ldr r10, =0x00020333 + str r10, [r8, #0x38] /* MMDC0_MDCFG3LP */ + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_below_100Mhz_ch1_timings + + str r5, [r4, #0xC] /* MMDC1_MDCFG0 */ + str r7, [r4, #0x10] /* MMDC1_MDCFG1 */ + str r9, [r4, #0x14] /* MMDC1_MDCFG2 */ + str r10, [r4, #0x38] /* MMDC1_MDCFG3LP */ + +skip_below_100Mhz_ch1_timings: + + .endm + + .macro restore_mmdc_settings_info + /* restore timing from mmdc_settings_info */ + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +1: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r8, r9] + subs r6, r6, #0x1 + bne 1b + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 3f + + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +2: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r4, r9] + subs r6, r6, #0x1 + bne 2b +3: + + .endm + + .macro mmdc_clk_lower_equal_100MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_timmings_100MHz + set_timings_below_100MHz_operation + b common_to_lower_equal_100MHz + +set_timmings_100MHz: + restore_mmdc_settings_info + set_mmdc_misc_ralat_2_cycles + +common_to_lower_equal_100MHz: + + /* if MMDC is not in 400MHz mode, skip double mu count */ + ldr r5, [r1, #0x8] + ldr r6, =400000000 + cmp r5, r6 + bne skip_lower_force_measure_ch1 + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_lower_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r4, r5] + orr r6, r6, #0x400 + str r6, [r4, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r4, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure_ch1 + +skip_lower_force_measure_ch1: + + .endm + + .macro mmdc_clk_above_100MHz + + restore_mmdc_settings_info + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_above_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + bic r6, r6, #0x400 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1_ch1 + +skip_above_force_measure_ch1: + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1 : mmdc_settings_info + */ + .align 3 +ENTRY(mx6q_lpddr2_freq_change) +mx6q_lpddr2_freq_change_start: + push {r2-r10} + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_psd_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x01 + str r6, [r4, #0x404] + + ldr r6, [r4, #0x4] + bic r6, r6, #0xff00 + str r6, [r4, #0x4] + +skip_psd_ch1: + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_sbs_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_set_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_2 + + ldr r6, [r4, #0x410] + orr r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_sbs_ch1: + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_equal_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_to_100MHz + + ldr r10, =400000000 + cmp r0, r10 + switch_to_400MHz + b done + +set_to_24MHz: +/* + switch_to_24MHZ_from_pll2 +*/ + switch_to_24MHz + b done + +set_to_100MHz: + switch_to_100MHz + +done: + + ldr r10,=100000000 + cmp r0, r10 + ble skip_mmdc_clk_check + mmdc_clk_above_100MHz + +skip_mmdc_clk_check: + + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_enable_psd_ch1 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_clear_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_2 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x01 + str r6, [r4, #0x404] + +skip_enable_psd_ch1: + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_power_down + + ldr r6, [r4, #0x4] + orr r6, r6, #0x5500 + str r6, [r4, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_disable_sbs_ch1 + + ldr r6, [r4, #0x410] + bic r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_disable_sbs_ch1: +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r2-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6q_lpddr2_freq_change_end: diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sll.S b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S new file mode 100644 index 00000000000000..edc115c6d72e8e --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SLL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6sll_lpddr2_freq_change) + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =0xa0000000 + str r6, [r5, #0x83c] + + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S new file mode 100644 index 00000000000000..31555347b82fc4 --- /dev/null +++ b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S @@ -0,0 +1,468 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r6, c0, c0, 0 + ldr r7, =0xfff0 + and r6, r6, r7 + ldr r7, =0xc070 + cmp r6, r7 + + .endm + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SX and i.MX6UL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6_up_lpddr2_freq_change) + + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + +skip_disable_l2: + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r5, #MMDC0_MDPDC] + bic r6, r6, #0xff00 + str r6, [r5, #MMDC0_MDPDC] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + ldr r6, =24000000 + cmp r0, r6 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r5, #MMDC0_MDPDC] + orr r6, r6, #0x5500 + str r6, [r5, #MMDC0_MDPDC] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S new file mode 100644 index 00000000000000..80fb1184fa547a --- /dev/null +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_PHY_CON1 0x4 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_RFSHTMG 0x64 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro ddrc_prepare + + /* disable port */ + ldr r7, =0x0 + str r7, [r4, #DDRC_PCTRL_0] + + /* wait port busy done */ + ldr r6, =0x10001 +1: + ldr r7, [r4, #DDRC_PSTAT] + and r7, r7, r6 + cmp r7, #0 + bne 1b + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +2: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x30000000 +3: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 3b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DFIMISC] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 4b + + .endm + + .macro ddrc_done + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x3 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + beq 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x1 + str r7, [r4, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_below_100m + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + bne 9f + + /* LPDDR3 */ + ldr r7, =0x00000100 + str r7, [r5, #DDRPHY_PHY_CON1] + b 10f +9: + /* LPDDR2 */ + ldr r7, =0x10010100 + str r7, [r5, #DDRPHY_PHY_CON1] +10: + ldr r6, =24000000 + cmp r0, r6 + beq 16f + + ldr r7, =0x0005000B + str r7, [r4, #DDRC_RFSHTMG] + b 6f +16: + ldr r7, =0x00010003 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 7f + +6: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +7: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 11f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 12f +11: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +12: + ldr r7, =0x100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + .endm + + .macro switch_to_533m + + ldr r7, =0x10210100 + str r7, [r5, #DDRPHY_PHY_CON1] + + ldr r7, =0x00200038 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + beq 15f + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 14f + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0a0a0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x0a0a0a0a + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +15: + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 13f + + ldr r7, =0x1c1c1c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x30301c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x30303030 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +13: + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +14: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +8: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 8b + + .endm + +ENTRY(imx_lpddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ddrc_prepare + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + ddrc_done + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr +ENDPROC(imx_lpddr3_freq_change) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 45801b27ee5ced..a80587e2b0e7b5 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -1,6 +1,7 @@ /* - * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -31,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +41,16 @@ #include "cpuidle.h" #include "hardware.h" +static int ar803x_smarteee = 0; + +static int __init ar803x_smarteee_setup(char *__unused) +{ + ar803x_smarteee = 1; + return 1; +} + +__setup("ar803x_smarteee", ar803x_smarteee_setup); + /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { @@ -112,6 +124,18 @@ static int ar8031_phy_fixup(struct phy_device *dev) { u16 val; + /* Set RGMII IO voltage to 1.8V */ + phy_write(dev, 0x1d, 0x1f); + phy_write(dev, 0x1e, 0x8); + + /* disable phy AR8031 SmartEEE function. */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val &= ~(0x1 << 8); + phy_write(dev, 0xe, val); + /* To enable AR8031 output a 125MHz clk from CLK_25M */ phy_write(dev, 0xd, 0x7); phy_write(dev, 0xe, 0x8016); @@ -137,20 +161,11 @@ static int ar8035_phy_fixup(struct phy_device *dev) { u16 val; - /* Ar803x phy SmartEEE feature cause link status generates glitch, - * which cause ethernet link down/up issue, so disable SmartEEE - */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); - - val = phy_read(dev, 0xe); - phy_write(dev, 0xe, val & ~(1 << 8)); - /* - * Enable 125MHz clock from CLK_25M on the AR8031. This - * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. - * Also, introduce a tx clock delay. + * Disable SmartEEE and Enable 125MHz clock from + * CLK_25M on the AR8031. This is fed in to the + * IMX6 on the ENET_REF_CLK (V22) pad. Also, + * introduce a tx clock delay. * * This is the same as is the AR8031 fixup. */ @@ -161,6 +176,31 @@ static int ar8035_phy_fixup(struct phy_device *dev) if (val & BMCR_PDOWN) phy_write(dev, 0x0, val & ~BMCR_PDOWN); + if (!ar803x_smarteee) + return 0; + + /* Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val |= (0x1 << 8); + phy_write(dev, 0xe, val); + + /* Increase 1000BT tw time for SmartEEE. It seems that we need + * a bit more time than standard to git up and running. Bumping + * up the Tw time allows us to enable SmartEEE without generating + * ethernet disconnects occasionally + */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805b); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val = 0x1717; + phy_write(dev, 0xe, val); + return 0; } @@ -184,9 +224,7 @@ static void __init imx6q_1588_init(void) { struct device_node *np; struct clk *ptp_clk; - struct clk *enet_ref; struct regmap *gpr; - u32 clksel; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (!np) { @@ -200,35 +238,55 @@ static void __init imx6q_1588_init(void) goto put_node; } - enet_ref = clk_get_sys(NULL, "enet_ref"); - if (IS_ERR(enet_ref)) { - pr_warn("%s: failed to get enet clock\n", __func__); - goto put_ptp_clk; - } - /* * If enet_ref from ANATOP/CCM is the PTP clock source, we need to * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad * (external OSC), and we need to clear the bit. */ - clksel = clk_is_match(ptp_clk, enet_ref) ? - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : - IMX6Q_GPR1_ENET_CLK_SEL_PAD; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, - clksel); + IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); else pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); - clk_put(enet_ref); -put_ptp_clk: clk_put(ptp_clk); put_node: of_node_put(np); } +static void __init imx6q_csi_mux_init(void) +{ + /* + * MX6Q SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR1 bit 19 to 0x1. + * + * MX6DL SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR13 bit 0-2 to 0x4. + * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1. + * Set GPR13 bit 3-5 to 0x1. + */ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q-sabresd") || + of_machine_is_compatible("fsl,imx6q-sabreauto") || + of_machine_is_compatible("fsl,imx6qp-sabresd") || + of_machine_is_compatible("fsl,imx6qp-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19); + else if (of_machine_is_compatible("fsl,imx6dl-sabresd") || + of_machine_is_compatible("fsl,imx6dl-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C); + } else { + pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } +} + static void __init imx6q_axi_init(void) { struct regmap *gpr; @@ -262,11 +320,32 @@ static void __init imx6q_axi_init(void) } } +static void __init imx6q_enet_clk_sel(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TX_CLK_SEL, IMX6Q_GPR5_ENET_TX_CLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); +} + +static inline void imx6q_enet_init(void) +{ + imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp"); + imx6q_enet_phy_init(); + imx6q_1588_init(); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx6q_enet_clk_sel(); +} + static void __init imx6q_init_machine(void) { struct device *parent; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", @@ -276,13 +355,12 @@ static void __init imx6q_init_machine(void) if (parent == NULL) pr_warn("failed to initialize soc device\n"); - imx6q_enet_phy_init(); - of_platform_default_populate(NULL, NULL, parent); + imx6q_enet_init(); imx_anatop_init(); + imx6q_csi_mux_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); - imx6q_1588_init(); imx6q_axi_init(); } @@ -295,6 +373,7 @@ static void __init imx6q_init_machine(void) static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) { struct device_node *np; + struct dev_pm_opp *opp; void __iomem *base; u32 val; @@ -322,18 +401,47 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q()) - if (dev_pm_opp_disable(cpu_dev, 1200000000)) - pr_warn("failed to disable 1.2 GHz OPP\n"); - if (val < OCOTP_CFG3_SPEED_996MHZ) - if (dev_pm_opp_disable(cpu_dev, 996000000)) - pr_warn("failed to disable 996 MHz OPP\n"); if (cpu_is_imx6q()) { - if (val != OCOTP_CFG3_SPEED_852MHZ) - if (dev_pm_opp_disable(cpu_dev, 852000000)) - pr_warn("failed to disable 852 MHz OPP\n"); + if (!val) { + /* fuses not set for IMX_CHIP_REVISION_1_0 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + val = OCOTP_CFG3_SPEED_996MHZ; + } + } + if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q()) { + opp = dev_pm_opp_find_freq_exact(cpu_dev, 1200000000, true); + if (!IS_ERR(opp)) { + if (dev_pm_opp_disable(cpu_dev, 1200000000)) + pr_warn("failed to disable 1.2 GHz OPP\n"); + } + } + if (val < OCOTP_CFG3_SPEED_996MHZ) { + opp = dev_pm_opp_find_freq_exact(cpu_dev, 996000000, true); + if (!IS_ERR(opp)) { + if (dev_pm_opp_disable(cpu_dev, 996000000)) + pr_warn("failed to disable 996 MHz OPP\n"); + } + } + if (cpu_is_imx6q()) { + if (val != OCOTP_CFG3_SPEED_852MHZ) { + opp = dev_pm_opp_find_freq_exact(cpu_dev, 852000000, true); + if (!IS_ERR(opp)) { + if (dev_pm_opp_disable(cpu_dev, 852000000)) + pr_warn("failed to disable 852 MHz OPP\n"); + } + } } iounmap(base); + + if (IS_ENABLED(CONFIG_MX6_VPU_352M)) { + opp = dev_pm_opp_find_freq_exact(cpu_dev, 396000000, true); + if (!IS_ERR(opp)) { + if (dev_pm_opp_disable(cpu_dev, 396000000)) + pr_warn("failed to disable 396MHz OPP\n"); + pr_info("remove 396MHz OPP for VPU running at 352MHz!\n"); + } + } + put_node: of_node_put(np); } @@ -368,13 +476,26 @@ static struct platform_device imx6q_cpufreq_pdev = { .name = "imx6q-cpufreq", }; +extern unsigned int system_rev; + static void __init imx6q_init_late(void) { + if (!system_rev) { + if (cpu_is_imx6q()) + system_rev = 0x63000; + else if (cpu_is_imx6dl()) + system_rev = 0x61000; + else if (cpu_is_imx6sl()) + system_rev = 0x60000; + system_rev |= imx_get_soc_revision(); + } /* * WAIT mode is broken on TO 1.0 and 1.1, so there is no point * to run cpuidle on them. */ - if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + || (cpu_is_imx6dl() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0)) imx6q_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { @@ -387,6 +508,10 @@ static void __init imx6q_map_io(void) { debug_ll_io_init(); imx_scu_map_io(); + imx6_pm_map_io(); +#ifdef CONFIG_CPU_FREQ + imx_busfreq_map_io(); +#endif } static void __init imx6q_init_irq(void) diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 04084900d810b2..459d451958977e 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -18,8 +18,9 @@ #include "common.h" #include "cpuidle.h" +#include "hardware.h" -static void __init imx6sl_fec_init(void) +static void __init imx6sl_fec_clk_init(void) { struct regmap *gpr; @@ -30,9 +31,14 @@ static void __init imx6sl_fec_init(void) IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); regmap_update_bits(gpr, IOMUXC_GPR1, IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); - } else { + } else pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); - } +} + +static inline void imx6sl_fec_init(void) +{ + imx6sl_fec_clk_init(); + imx6_enet_mac_init("fsl,imx6sl-fec", "fsl,imx6sl-ocotp"); } static void __init imx6sl_init_late(void) @@ -41,7 +47,13 @@ static void __init imx6sl_init_late(void) if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); - imx6sl_cpuidle_init(); + /* cpuidle will be enabled later for i.MX6SLL */ +#if defined(CONFIG_SOC_IMX6SLL) + if (cpu_is_imx6sll()) + imx6sll_cpuidle_init(); + else +#endif + imx6sl_cpuidle_init(); } static void __init imx6sl_init_machine(void) @@ -54,7 +66,8 @@ static void __init imx6sl_init_machine(void) of_platform_default_populate(NULL, NULL, parent); - imx6sl_fec_init(); + if (!cpu_is_imx6sll()) + imx6sl_fec_init(); imx_anatop_init(); imx6sl_pm_init(); } @@ -66,17 +79,31 @@ static void __init imx6sl_init_irq(void) imx_init_l2cache(); imx_src_init(); irqchip_init(); - imx6_pm_ccm_init("fsl,imx6sl-ccm"); + if (cpu_is_imx6sll()) + imx6_pm_ccm_init("fsl,imx6sll-ccm"); + else + imx6_pm_ccm_init("fsl,imx6sl-ccm"); +} + +static void __init imx6sl_map_io(void) +{ + debug_ll_io_init(); + imx6_pm_map_io(); +#ifdef CONFIG_CPU_FREQ + imx_busfreq_map_io(); +#endif } static const char * const imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", + "fsl,imx6sll", NULL, }; DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sl_map_io, .init_irq = imx6sl_init_irq, .init_machine = imx6sl_init_machine, .init_late = imx6sl_init_late, diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index 7f52d9b1e8a451..6fb6fa862679d0 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,9 +14,31 @@ #include #include #include +#include +#include #include "common.h" #include "cpuidle.h" +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) +{ + phy_write(dev, 0x0d, device); + phy_write(dev, 0x0e, reg); + phy_write(dev, 0x0d, (1 << 14) | device); + phy_write(dev, 0x0e, val); +} + +static int ksz9031rn_phy_fixup(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + mmd_write_reg(dev, 2, 4, 0); + mmd_write_reg(dev, 2, 5, 0); + mmd_write_reg(dev, 2, 8, 0x003ff); + + return 0; +} static int ar8031_phy_fixup(struct phy_device *dev) { @@ -26,6 +48,14 @@ static int ar8031_phy_fixup(struct phy_device *dev) phy_write(dev, 0x1d, 0x1f); phy_write(dev, 0x1e, 0x8); + /* disable phy AR8031 SmartEEE function. */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + val = phy_read(dev, 0xe); + val &= ~(0x1 << 8); + phy_write(dev, 0xe, val); + /* introduce tx clock delay */ phy_write(dev, 0x1d, 0x5); val = phy_read(dev, 0x1e); @@ -38,9 +68,12 @@ static int ar8031_phy_fixup(struct phy_device *dev) #define PHY_ID_AR8031 0x004dd074 static void __init imx6sx_enet_phy_init(void) { - if (IS_BUILTIN(CONFIG_PHYLIB)) + if (IS_BUILTIN(CONFIG_PHYLIB)) { + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, + ksz9031rn_phy_fixup); phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, ar8031_phy_fixup); + } } static void __init imx6sx_enet_clk_sel(void) @@ -60,6 +93,7 @@ static void __init imx6sx_enet_clk_sel(void) static inline void imx6sx_enet_init(void) { + imx6_enet_mac_init("fsl,imx6sx-fec", "fsl,imx6sx-ocotp"); imx6sx_enet_phy_init(); imx6sx_enet_clk_sel(); } @@ -89,12 +123,24 @@ static void __init imx6sx_init_irq(void) imx6_pm_ccm_init("fsl,imx6sx-ccm"); } +extern unsigned int system_rev; + static void __init imx6sx_init_late(void) { - imx6sx_cpuidle_init(); - + if (!system_rev) { + system_rev = 0x60000 | imx_get_soc_revision(); + } if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + + imx6sx_cpuidle_init(); +} + +static void __init imx6sx_map_io(void) +{ + debug_ll_io_init(); + imx6_pm_map_io(); + imx_busfreq_map_io(); } static const char * const imx6sx_dt_compat[] __initconst = { @@ -105,6 +151,7 @@ static const char * const imx6sx_dt_compat[] __initconst = { DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sx_map_io, .init_irq = imx6sx_init_irq, .init_machine = imx6sx_init_machine, .dt_compat = imx6sx_dt_compat, diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 58a2b88233e665..851034d5f73f29 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,14 +9,17 @@ #include #include #include +#include #include #include +#include #include #include #include #include "common.h" #include "cpuidle.h" +#include "hardware.h" static void __init imx6ul_enet_clk_init(void) { @@ -46,15 +49,122 @@ static int ksz8081_phy_fixup(struct phy_device *dev) static void __init imx6ul_enet_phy_init(void) { - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, - ksz8081_phy_fixup); + if (IS_BUILTIN(CONFIG_PHYLIB)) { + /* + * i.MX6UL EVK board RevA, RevB, RevC all use KSZ8081 + * Silicon revision 00, the PHY ID is 0x00221560, pass our + * test with the phy fixup. + */ + phy_register_fixup(PHY_ANY_ID, PHY_ID_KSZ8081, 0xffffffff, + ksz8081_phy_fixup); + + /* + * i.MX6UL EVK board RevC1 board use KSZ8081 + * Silicon revision 01, the PHY ID is 0x00221561. + * This silicon revision still need the phy fixup setting. + */ + #define PHY_ID_KSZ8081_MNRN61 0x00221561 + phy_register_fixup(PHY_ANY_ID, PHY_ID_KSZ8081_MNRN61, + 0xffffffff, ksz8081_phy_fixup); + } +} + +#define OCOTP_CFG3 0x440 +#define OCOTP_CFG3_SPEED_SHIFT 16 +#define OCOTP_CFG3_SPEED_696MHZ 0x2 +#define OCOTP_CFG3_SPEED_900MHZ 0x3 + +static void __init imx6ul_opp_check_speed_grading(struct device *cpu_dev) +{ + struct device_node *np; + void __iomem *base; + u32 val; + + if (cpu_is_imx6ul()) + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); + else + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ull-ocotp"); + + if (!np) { + pr_warn("failed to find ocotp node\n"); + return; + } + + base = of_iomap(np, 0); + if (!base) { + pr_warn("failed to map ocotp\n"); + goto put_node; + } + + /* + * Speed GRADING[1:0] defines the max speed of ARM: + * 2b'00: Reserved; + * 2b'01: 528000000Hz; + * 2b'10: 700000000Hz(i.MX6UL), 800000000Hz(i.MX6ULL); + * 2b'11: 900000000Hz(i.MX6ULL); + * We need to set the max speed of ARM according to fuse map. + */ + val = readl_relaxed(base + OCOTP_CFG3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + if (cpu_is_imx6ul()) { + if (val < OCOTP_CFG3_SPEED_696MHZ) { + if (dev_pm_opp_disable(cpu_dev, 696000000)) + pr_warn("Failed to disable 696MHz OPP\n"); + } + } + + if (cpu_is_imx6ull()) { + if (val != OCOTP_CFG3_SPEED_696MHZ) { + if (dev_pm_opp_disable(cpu_dev, 792000000)) + pr_warn("Failed to disable 792MHz OPP\n"); + } + + if (val != OCOTP_CFG3_SPEED_900MHZ) { + if(dev_pm_opp_disable(cpu_dev, 900000000)) + pr_warn("Failed to disable 900MHz OPP\n"); + } + } + iounmap(base); + +put_node: + of_node_put(np); +} + +static void __init imx6ul_opp_init(void) +{ + struct device_node *np; + struct device *cpu_dev = get_cpu_device(0); + + if (!cpu_dev) { + pr_warn("failed to get cpu0 device\n"); + return; + } + np = of_node_get(cpu_dev->of_node); + if (!np) { + pr_warn("failed to find cpu0 node\n"); + return; + } + + if (dev_pm_opp_of_add_table(cpu_dev)) { + pr_warn("failed to init OPP table\n"); + goto put_node; + } + + imx6ul_opp_check_speed_grading(cpu_dev); + +put_node: + of_node_put(np); } static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); imx6ul_enet_phy_init(); + if (cpu_is_imx6ul()) + imx6_enet_mac_init("fsl,imx6ul-fec", "fsl,imx6ul-ocotp"); + else + imx6_enet_mac_init("fsl,imx6ul-fec", "fsl,imx6ull-ocotp"); } static void __init imx6ul_init_machine(void) @@ -73,6 +183,7 @@ static void __init imx6ul_init_machine(void) static void __init imx6ul_init_irq(void) { + imx_gpc_check_dt(); imx_init_revision_from_anatop(); imx_src_init(); irqchip_init(); @@ -81,18 +192,29 @@ static void __init imx6ul_init_irq(void) static void __init imx6ul_init_late(void) { - imx6sx_cpuidle_init(); - - if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { + imx6ul_opp_init(); platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + } + + imx6ul_cpuidle_init(); +} + +static void __init imx6ul_map_io(void) +{ + debug_ll_io_init(); + imx6_pm_map_io(); + imx_busfreq_map_io(); } static const char * const imx6ul_dt_compat[] __initconst = { "fsl,imx6ul", + "fsl,imx6ull", NULL, }; -DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") +DT_MACHINE_START(IMX6UL, "Freescale i.MX6 UltraLite (Device Tree)") + .map_io = imx6ul_map_io, .init_irq = imx6ul_init_irq, .init_machine = imx6ul_init_machine, .init_late = imx6ul_init_late, diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 26ca744d3e2b12..3f335974723f1e 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -10,12 +10,20 @@ #include #include #include +#include #include #include #include #include "common.h" +#include "cpuidle.h" + +static struct property device_disabled = { + .name = "status", + .length = sizeof("disabled"), + .value = "disabled", +}; static int ar8031_phy_fixup(struct phy_device *dev) { @@ -66,6 +74,23 @@ static void __init imx7d_enet_phy_init(void) } } +static void __init imx7d_enet_mdio_fixup(void) +{ + struct regmap *gpr; + + /* The management data input/output (MDIO) bus where often high-speed, + * open-drain operation is required. i.MX7D TO1.0 ENET MDIO pin has no + * open drain as IC ticket number: TKT252980, i.MX7D TO1.1 fix the issue. + * GPR1[8:7] are reserved bits at TO1.0, there no need to add version check. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR0, IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK, + IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + else + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); +} + static void __init imx7d_enet_clk_sel(void) { struct regmap *gpr; @@ -81,10 +106,23 @@ static void __init imx7d_enet_clk_sel(void) static inline void imx7d_enet_init(void) { + imx6_enet_mac_init("fsl,imx7d-fec", "fsl,imx7d-ocotp"); + imx7d_enet_mdio_fixup(); imx7d_enet_phy_init(); imx7d_enet_clk_sel(); } +static inline void imx7d_disable_arm_arch_timer(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); + if (node) { + pr_info("disable arm arch timer for nosmp!\n"); + of_add_property(node, &device_disabled); + } +} + static void __init imx7d_init_machine(void) { struct device *parent; @@ -93,15 +131,36 @@ static void __init imx7d_init_machine(void) if (parent == NULL) pr_warn("failed to initialize soc device\n"); + of_platform_default_populate(NULL, NULL, parent); + imx7d_pm_init(); imx_anatop_init(); imx7d_enet_init(); } static void __init imx7d_init_irq(void) { + imx_gpcv2_check_dt(); imx_init_revision_from_anatop(); imx_src_init(); irqchip_init(); +#ifndef CONFIG_SMP + imx7d_disable_arm_arch_timer(); +#endif +} + +static void __init imx7d_init_late(void) +{ + if (IS_ENABLED(CONFIG_ARM_IMX7D_CPUFREQ)) { + platform_device_register_simple("imx7d-cpufreq", -1, NULL, 0); + } + imx7d_cpuidle_init(); +} + +static void __init imx7d_map_io(void) +{ + debug_ll_io_init(); + imx7_pm_map_io(); + imx_busfreq_map_io(); } static const char *const imx7d_dt_compat[] __initconst = { @@ -111,7 +170,10 @@ static const char *const imx7d_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") + .map_io = imx7d_map_io, + .smp = smp_ops(imx_smp_ops), .init_irq = imx7d_init_irq, .init_machine = imx7d_init_machine, + .init_late = imx7d_init_late, .dt_compat = imx7d_dt_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c new file mode 100644 index 00000000000000..2d916e1dd2c968 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +/* static IO mapping, and ioremap() could always share the same mapping. */ +static struct map_desc mx7ulp_io_desc[] __initdata = { + mx7ulp_aips_map_entry(1, MT_DEVICE), + mx7ulp_aips_map_entry(2, MT_DEVICE), + mx7ulp_aips_map_entry(3, MT_DEVICE), + mx7ulp_aips_map_entry(4, MT_DEVICE), + mx7ulp_aips_map_entry(5, MT_DEVICE), +}; + +static void __init imx7ulp_init_machine(void) +{ + struct device *parent; + + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init imx7ulp_init_irq(void) +{ + /* TBD */ + mxc_set_cpu_type(MXC_CPU_IMX7ULP); + + irqchip_init(); + imx7ulp_pm_init(); +} + +static void __init imx7ulp_map_io(void) +{ + iotable_init(mx7ulp_io_desc, ARRAY_SIZE(mx7ulp_io_desc)); + imx7ulp_pm_map_io(); +} + +static void __init imx7ulp_init_late(void) +{ + if (IS_ENABLED(CONFIG_ARM_IMX7ULP_CPUFREQ)) + platform_device_register_simple("imx7ulp-cpufreq", -1, NULL, 0); + + imx7ulp_cpuidle_init(); + imx7ulp_enable_nmi(); +} + +static const char *const imx7ulp_dt_compat[] __initconst = { + "fsl,imx7ulp", + NULL, +}; + +DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .map_io = imx7ulp_map_io, + .init_irq = imx7ulp_init_irq, + .init_machine = imx7ulp_init_machine, + .init_late = imx7ulp_init_late, + .dt_compat = imx7ulp_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index db9621c718ecae..9c185760dbd438 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -1,5 +1,6 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright 2011,2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -10,12 +11,16 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include +#include #include #include #include #include #include +#include +#include #include "common.h" @@ -26,8 +31,520 @@ #define MMDC_MDMISC 0x18 #define BM_MMDC_MDMISC_DDR_TYPE 0x18 #define BP_MMDC_MDMISC_DDR_TYPE 0x3 +#define BM_MMDC_MDMISC_LPDDR2_2CH 0x4 +#define BP_MMDC_MDMISC_LPDDR2_2CH 0x2 + +#define TOTAL_CYCLES 0x0 +#define BUSY_CYCLES 0x1 +#define READ_ACCESSES 0x2 +#define WRITE_ACCESSES 0x3 +#define READ_BYTES 0x4 +#define WRITE_BYTES 0x5 + +/* Enables, resets, freezes, overflow profiling*/ +#define DBG_DIS 0x0 +#define DBG_EN 0x1 +#define DBG_RST 0x2 +#define PRF_FRZ 0x4 +#define CYC_OVF 0x8 +#define PROFILE_SEL 0x10 + +#define MMDC_MADPCR0 0x410 +#define MMDC_MADPCR1 0x414 +#define MMDC_MADPSR0 0x418 +#define MMDC_MADPSR1 0x41C +#define MMDC_MADPSR2 0x420 +#define MMDC_MADPSR3 0x424 +#define MMDC_MADPSR4 0x428 +#define MMDC_MADPSR5 0x42C + +#define MMDC_NUM_COUNTERS 6 + +#define MMDC_FLAG_PROFILE_SEL 0x1 +#define MMDC_PRF_AXI_ID_CLEAR 0x0 + +#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) static int ddr_type; +static int lpddr2_2ch_mode; + +struct fsl_mmdc_devtype_data { + unsigned int flags; +}; + +static const struct fsl_mmdc_devtype_data imx6q_data = { +}; + +static const struct fsl_mmdc_devtype_data imx6qp_data = { + .flags = MMDC_FLAG_PROFILE_SEL, +}; + +static const struct of_device_id imx_mmdc_dt_ids[] = { + { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data}, + { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data}, + { /* sentinel */ } +}; + + +#ifdef CONFIG_PERF_EVENTS + +static enum cpuhp_state cpuhp_mmdc_state; +static DEFINE_IDA(mmdc_ida); + +PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") +PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") +PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") +PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03") +PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") +PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); +PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05") +PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001"); + +struct mmdc_pmu { + struct pmu pmu; + void __iomem *mmdc_base; + cpumask_t cpu; + struct hrtimer hrtimer; + unsigned int active_events; + struct device *dev; + struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; + struct hlist_node node; + struct fsl_mmdc_devtype_data *devtype_data; +}; + +/* + * Polling period is set to one second, overflow of total-cycles (the fastest + * increasing counter) takes ten seconds so one second is safe + */ +static unsigned int mmdc_pmu_poll_period_us = 1000000; + +module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint, + S_IRUGO | S_IWUSR); + +static ktime_t mmdc_pmu_timer_period(void) +{ + return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000); +} + +static ssize_t mmdc_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev); + + return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu); +} + +static struct device_attribute mmdc_pmu_cpumask_attr = + __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL); + +static struct attribute *mmdc_pmu_cpumask_attrs[] = { + &mmdc_pmu_cpumask_attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_cpumask_attr_group = { + .attrs = mmdc_pmu_cpumask_attrs, +}; + +static struct attribute *mmdc_pmu_events_attrs[] = { + &mmdc_pmu_total_cycles.attr.attr, + &mmdc_pmu_busy_cycles.attr.attr, + &mmdc_pmu_read_accesses.attr.attr, + &mmdc_pmu_write_accesses.attr.attr, + &mmdc_pmu_read_bytes.attr.attr, + &mmdc_pmu_read_bytes_unit.attr.attr, + &mmdc_pmu_read_bytes_scale.attr.attr, + &mmdc_pmu_write_bytes.attr.attr, + &mmdc_pmu_write_bytes_unit.attr.attr, + &mmdc_pmu_write_bytes_scale.attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_events_attr_group = { + .name = "events", + .attrs = mmdc_pmu_events_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-63"); +PMU_FORMAT_ATTR(axi_id, "config1:0-63"); + +static struct attribute *mmdc_pmu_format_attrs[] = { + &format_attr_event.attr, + &format_attr_axi_id.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_format_attr_group = { + .name = "format", + .attrs = mmdc_pmu_format_attrs, +}; + +static const struct attribute_group *attr_groups[] = { + &mmdc_pmu_events_attr_group, + &mmdc_pmu_format_attr_group, + &mmdc_pmu_cpumask_attr_group, + NULL, +}; + +static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg) +{ + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + + switch (cfg) { + case TOTAL_CYCLES: + reg = mmdc_base + MMDC_MADPSR0; + break; + case BUSY_CYCLES: + reg = mmdc_base + MMDC_MADPSR1; + break; + case READ_ACCESSES: + reg = mmdc_base + MMDC_MADPSR2; + break; + case WRITE_ACCESSES: + reg = mmdc_base + MMDC_MADPSR3; + break; + case READ_BYTES: + reg = mmdc_base + MMDC_MADPSR4; + break; + case WRITE_BYTES: + reg = mmdc_base + MMDC_MADPSR5; + break; + default: + return WARN_ONCE(1, + "invalid configuration %d for mmdc counter", cfg); + } + return readl(reg); +} + +static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node); + int target; + + if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu)) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target); + cpumask_set_cpu(target, &pmu_mmdc->cpu); + + return 0; +} + +static bool mmdc_pmu_group_event_is_valid(struct perf_event *event, + struct pmu *pmu, + unsigned long *used_counters) +{ + int cfg = event->attr.config; + + if (is_software_event(event)) + return true; + + if (event->pmu != pmu) + return false; + + return !test_and_set_bit(cfg, used_counters); +} + +/* + * Each event has a single fixed-purpose counter, so we can only have a + * single active event for each at any point in time. Here we just check + * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW + * event numbers are valid. + */ +static bool mmdc_pmu_group_is_valid(struct perf_event *event) +{ + struct pmu *pmu = event->pmu; + struct perf_event *leader = event->group_leader; + struct perf_event *sibling; + unsigned long counter_mask = 0; + + set_bit(leader->attr.config, &counter_mask); + + if (event != leader) { + if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) + return false; + } + + list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) + return false; + } + + return true; +} + +static int mmdc_pmu_event_init(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EOPNOTSUPP; + + if (event->cpu < 0) { + dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); + return -EOPNOTSUPP; + } + + if (event->attr.exclude_user || + event->attr.exclude_kernel || + event->attr.exclude_hv || + event->attr.exclude_idle || + event->attr.exclude_host || + event->attr.exclude_guest || + event->attr.sample_period) + return -EINVAL; + + if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS) + return -EINVAL; + + if (!mmdc_pmu_group_is_valid(event)) + return -EINVAL; + + event->cpu = cpumask_first(&pmu_mmdc->cpu); + return 0; +} + +static void mmdc_pmu_event_update(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 delta, prev_raw_count, new_raw_count; + + do { + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = mmdc_pmu_read_counter(pmu_mmdc, + event->attr.config); + } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count); + + delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; + + local64_add(delta, &event->count); +} + +static void mmdc_pmu_event_start(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + void __iomem *mmdc_base, *reg; + u32 val; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + /* + * hrtimer is required because mmdc does not provide an interrupt so + * polling is necessary + */ + hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(), + HRTIMER_MODE_REL_PINNED); + + local64_set(&hwc->prev_count, 0); + + writel(DBG_RST, reg); + + /* + * Write the AXI id parameter to MADPCR1. + */ + val = event->attr.config1; + reg = mmdc_base + MMDC_MADPCR1; + writel(val, reg); + + reg = mmdc_base + MMDC_MADPCR0; + val = DBG_EN; + if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) + val |= PROFILE_SEL; + + writel(val, reg); +} + +static int mmdc_pmu_event_add(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + int cfg = event->attr.config; + + if (flags & PERF_EF_START) + mmdc_pmu_event_start(event, flags); + + if (pmu_mmdc->mmdc_events[cfg] != NULL) + return -EAGAIN; + + pmu_mmdc->mmdc_events[cfg] = event; + pmu_mmdc->active_events++; + + local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg)); + + return 0; +} + +static void mmdc_pmu_event_stop(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + writel(PRF_FRZ, reg); + + reg = mmdc_base + MMDC_MADPCR1; + writel(MMDC_PRF_AXI_ID_CLEAR, reg); + + mmdc_pmu_event_update(event); +} + +static void mmdc_pmu_event_del(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + pmu_mmdc->mmdc_events[cfg] = NULL; + pmu_mmdc->active_events--; + + if (pmu_mmdc->active_events == 0) + hrtimer_cancel(&pmu_mmdc->hrtimer); + + mmdc_pmu_event_stop(event, PERF_EF_UPDATE); +} + +static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc) +{ + int i; + + for (i = 0; i < MMDC_NUM_COUNTERS; i++) { + struct perf_event *event = pmu_mmdc->mmdc_events[i]; + + if (event) + mmdc_pmu_event_update(event); + } +} + +static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) +{ + struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu, + hrtimer); + + mmdc_pmu_overflow_handler(pmu_mmdc); + hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period()); + + return HRTIMER_RESTART; +} + +static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, + void __iomem *mmdc_base, struct device *dev) +{ + int mmdc_num; + + *pmu_mmdc = (struct mmdc_pmu) { + .pmu = (struct pmu) { + .task_ctx_nr = perf_invalid_context, + .attr_groups = attr_groups, + .event_init = mmdc_pmu_event_init, + .add = mmdc_pmu_event_add, + .del = mmdc_pmu_event_del, + .start = mmdc_pmu_event_start, + .stop = mmdc_pmu_event_stop, + .read = mmdc_pmu_event_update, + }, + .mmdc_base = mmdc_base, + .dev = dev, + .active_events = 0, + }; + + mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); + + return mmdc_num; +} + +static int imx_mmdc_remove(struct platform_device *pdev) +{ + struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); + + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + perf_pmu_unregister(&pmu_mmdc->pmu); + kfree(pmu_mmdc); + return 0; +} + +static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base) +{ + struct mmdc_pmu *pmu_mmdc; + char *name; + int mmdc_num; + int ret; + const struct of_device_id *of_id = + of_match_device(imx_mmdc_dt_ids, &pdev->dev); + + pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL); + if (!pmu_mmdc) { + pr_err("failed to allocate PMU device!\n"); + return -ENOMEM; + } + + /* The first instance registers the hotplug state */ + if (!cpuhp_mmdc_state) { + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/arm/mmdc:online", NULL, + mmdc_pmu_offline_cpu); + if (ret < 0) { + pr_err("cpuhp_setup_state_multi failed\n"); + goto pmu_free; + } + cpuhp_mmdc_state = ret; + } + + mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (mmdc_num == 0) + name = "mmdc"; + else + name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", mmdc_num); + + pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; + + hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler; + + cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu); + + /* Register the pmu instance for cpu hotplug */ + cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + + ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1); + if (ret) + goto pmu_register_err; + + platform_set_drvdata(pdev, pmu_mmdc); + return 0; + +pmu_register_err: + pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + hrtimer_cancel(&pmu_mmdc->hrtimer); +pmu_free: + kfree(pmu_mmdc); + return ret; +} + +#else +#define imx_mmdc_remove NULL +#define imx_mmdc_perf_init(pdev, mmdc_base) 0 +#endif static int imx_mmdc_probe(struct platform_device *pdev) { @@ -44,6 +561,9 @@ static int imx_mmdc_probe(struct platform_device *pdev) val = readl_relaxed(reg); ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >> BP_MMDC_MDMISC_DDR_TYPE; + /* Get lpddr2 2ch-mode */ + lpddr2_2ch_mode = (val & BM_MMDC_MDMISC_LPDDR2_2CH) >> + BP_MMDC_MDMISC_LPDDR2_2CH; reg = mmdc_base + MMDC_MAPSR; @@ -62,7 +582,7 @@ static int imx_mmdc_probe(struct platform_device *pdev) return -EBUSY; } - return 0; + return imx_mmdc_perf_init(pdev, mmdc_base); } int imx_mmdc_get_ddr_type(void) @@ -70,10 +590,10 @@ int imx_mmdc_get_ddr_type(void) return ddr_type; } -static const struct of_device_id imx_mmdc_dt_ids[] = { - { .compatible = "fsl,imx6q-mmdc", }, - { /* sentinel */ } -}; +int imx_mmdc_get_lpddr2_2ch_mode(void) +{ + return lpddr2_2ch_mode; +} static struct platform_driver imx_mmdc_driver = { .driver = { @@ -81,6 +601,7 @@ static struct platform_driver imx_mmdc_driver = { .of_match_table = imx_mmdc_dt_ids, }, .probe = imx_mmdc_probe, + .remove = imx_mmdc_remove, }; static int __init imx_mmdc_init(void) diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c new file mode 100644 index 00000000000000..4ab7ef2f9d62cf --- /dev/null +++ b/arch/arm/mach-imx/mu.c @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "hardware.h" + +#define MU_ATR0_OFFSET 0x0 +#define MU_ARR0_OFFSET 0x10 +#define MU_ARR1_OFFSET 0x14 +#define MU_ASR 0x20 +#define MU_ACR 0x24 +#define MX7ULP_MU_TR0 0x20 +#define MX7ULP_MU_RR0 0x40 +#define MX7ULP_MU_RR1 0x44 +#define MX7ULP_MU_SR 0x60 +#define MX7ULP_MU_CR 0x64 + +#define MU_LPM_HANDSHAKE_INDEX 0 +#define MU_RPMSG_HANDSHAKE_INDEX 1 +#define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666 +#define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777 +#define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC +#define MU_LPM_M4_RELEASE_HIGH_BUS 0x2222BBBB +#define MU_LPM_M4_WAKEUP_SRC_VAL 0x55555000 +#define MU_LPM_M4_WAKEUP_SRC_MASK 0xFFFFF000 +#define MU_LPM_M4_WAKEUP_IRQ_MASK 0xFF0 +#define MU_LPM_M4_WAKEUP_IRQ_SHIFT 0x4 +#define MU_LPM_M4_WAKEUP_ENABLE_MASK 0xF +#define MU_LPM_M4_WAKEUP_ENABLE_SHIFT 0x0 + +#define MU_LPM_M4_RUN_MODE 0x5A5A0001 +#define MU_LPM_M4_WAIT_MODE 0x5A5A0002 +#define MU_LPM_M4_STOP_MODE 0x5A5A0003 + +#define MAX_NUM 10 /* enlarge it if overflow happen */ + +static void __iomem *mu_base; +static u32 m4_message[MAX_NUM]; +static u32 in_idx, out_idx; +static struct delayed_work mu_work; +static u32 m4_wake_irqs[4]; +static bool m4_freq_low; +struct irq_domain *domain; +static bool m4_in_stop; +static struct clk *clk; +static DEFINE_SPINLOCK(mu_lock); + +void imx_mu_set_m4_run_mode(void) +{ + m4_in_stop = false; +} + +bool imx_mu_is_m4_in_stop(void) +{ + return m4_in_stop; +} + +bool imx_mu_is_m4_in_low_freq(void) +{ + return m4_freq_low; +} + +void imx_mu_enable_m4_irqs_in_gic(bool enable) +{ + int i, j; + + for (i = 0; i < 4; i++) { + if (m4_wake_irqs[i] == 0) + continue; + for (j = 0; j < 32; j++) { + if (m4_wake_irqs[i] & (1 << j)) { + if (enable) + enable_irq(irq_find_mapping( + domain, i * 32 + j)); + else + disable_irq(irq_find_mapping( + domain, i * 32 + j)); + } + } + } +} + +static irqreturn_t mcc_m4_dummy_isr(int irq, void *param) +{ + return IRQ_HANDLED; +} + +static int imx_mu_send_message(unsigned int index, unsigned int data) +{ + u32 val, ep; + int i, te_flag = 0; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait for transfer buffer empty, and no event pending */ + do { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (time_after(jiffies, timeout)) { + pr_err("Waiting MU transmit buffer empty timeout!\n"); + return -EIO; + } + } while (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))); + + if (cpu_is_imx7ulp()) + writel_relaxed(data, mu_base + index * 0x4 + MX7ULP_MU_TR0); + else + writel_relaxed(data, mu_base + index * 0x4 + MU_ATR0_OFFSET); + + /* + * make a double check that TEn is not empty after write + */ + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + (3 - index)))) == 0) || (ep == BIT(4))) + return 0; + else + te_flag = 1; + + /* + * Make sure that TEn flag is changed, after the ATRn is filled up. + */ + for (i = 0; i < 100; i++) { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))) { + /* + * BUG here. TEn flag is changes, after the + * ATRn is filled with MSG for a while. + */ + te_flag = 0; + break; + } else if (time_after(jiffies, timeout)) { + /* Can't see TEn 1->0, maybe already handled! */ + te_flag = 1; + break; + } + } + if (te_flag == 0) + pr_info("BUG: TEn is not changed immediately" + "when ATRn is filled up.\n"); + + return 0; +} + +static void mu_work_handler(struct work_struct *work) +{ + int ret; + u32 irq, enable, idx, mask, virq; + struct of_phandle_args args; + u32 message; + unsigned long flags; + + spin_lock_irqsave(&mu_lock, flags); + message = m4_message[out_idx % MAX_NUM]; + spin_unlock_irqrestore(&mu_lock, flags); + + pr_debug("receive M4 message 0x%x\n", message); + + switch (message) { + case MU_LPM_M4_RUN_MODE: + case MU_LPM_M4_WAIT_MODE: + m4_in_stop = false; + break; + case MU_LPM_M4_STOP_MODE: + m4_in_stop = true; + break; + case MU_LPM_M4_REQUEST_HIGH_BUS: + request_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) + imx6sx_set_m4_highfreq(true); +#endif + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_BUS_HIGH_READY_FOR_M4); + m4_freq_low = false; + break; + case MU_LPM_M4_RELEASE_HIGH_BUS: + release_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) { + imx6sx_set_m4_highfreq(false); + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_M4_FREQ_CHANGE_READY); + } +#endif + m4_freq_low = true; + break; + default: + if ((message & MU_LPM_M4_WAKEUP_SRC_MASK) == + MU_LPM_M4_WAKEUP_SRC_VAL) { + irq = (message & MU_LPM_M4_WAKEUP_IRQ_MASK) >> + MU_LPM_M4_WAKEUP_IRQ_SHIFT; + + enable = (message & MU_LPM_M4_WAKEUP_ENABLE_MASK) >> + MU_LPM_M4_WAKEUP_ENABLE_SHIFT; + + /* to hwirq start from 0 */ + irq -= 32; + + idx = irq / 32; + mask = 1 << irq % 32; + + args.np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpc"); + args.args_count = 3; + args.args[0] = 0; + args.args[1] = irq; + args.args[2] = IRQ_TYPE_LEVEL_HIGH; + + virq = irq_create_of_mapping(&args); + + if (enable && can_request_irq(virq, 0)) { + ret = request_irq(virq, mcc_m4_dummy_isr, + IRQF_NO_SUSPEND, "imx-m4-dummy", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, virq, ret); + break; + } + disable_irq(virq); + m4_wake_irqs[idx] = m4_wake_irqs[idx] | mask; + } + imx_gpc_add_m4_wake_up_irq(irq, enable); + } + break; + } + + spin_lock_irqsave(&mu_lock, flags); + m4_message[out_idx % MAX_NUM] = 0; + out_idx++; + spin_unlock_irqrestore(&mu_lock, flags); + + /* enable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | BIT(27), + mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(27), + mu_base + MU_ACR); +} + +int imx_mu_lpm_ready(bool ready) +{ + u32 val; + + if (cpu_is_imx7ulp()) { + val = readl_relaxed(mu_base + MX7ULP_MU_CR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(val & ~BIT(0), mu_base + MX7ULP_MU_CR); + } else { + val = readl_relaxed(mu_base + MU_ACR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MU_ACR); + else + writel_relaxed(val & ~BIT(0), mu_base + MU_ACR); + } + return 0; +} + +static irqreturn_t imx_mu_isr(int irq, void *param) +{ + u32 irqs; + unsigned long flags; + + if (cpu_is_imx7ulp()) + irqs = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + irqs = readl_relaxed(mu_base + MU_ASR); + + if (irqs & (1 << 27)) { + spin_lock_irqsave(&mu_lock, flags); + /* get message from receive buffer */ + if (cpu_is_imx7ulp()) + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MX7ULP_MU_RR0); + else + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MU_ARR0_OFFSET); + /* disable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) + & (~BIT(27)), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) + & (~BIT(27)), mu_base + MU_ACR); + in_idx++; + if (in_idx == out_idx) { + spin_unlock_irqrestore(&mu_lock, flags); + pr_err("MU overflow!\n"); + return IRQ_HANDLED; + } + spin_unlock_irqrestore(&mu_lock, flags); + + schedule_delayed_work(&mu_work, 0); + } + + return IRQ_HANDLED; +} + +static int imx_mu_probe(struct platform_device *pdev) +{ + int ret; + u32 irq; + struct device_node *np; + struct device *dev = &pdev->dev; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-mu"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + + ret = of_device_is_compatible(np, "fsl,imx7ulp-mu"); + if (ret) + irq = platform_get_irq(pdev, 1); + else + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, imx_mu_isr, + IRQF_EARLY_RESUME | IRQF_SHARED, "imx-mu", dev); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return ret; + } + + ret = of_device_is_compatible(np, "fsl,imx7d-mu"); + if (ret) { + clk = devm_clk_get(&pdev->dev, "mu"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, + "mu clock source missing or invalid\n"); + return PTR_ERR(clk); + } else { + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, + "unable to enable mu clock\n"); + return ret; + } + } + + /* MU always as a wakeup source for low power mode */ + imx_gpcv2_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, + true); + } else { + /* MU always as a wakeup source for low power mode */ + imx_gpc_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, true); + } + + INIT_DELAYED_WORK(&mu_work, mu_work_handler); + /* bit0 of MX7ULP_MU_CR used to let m4 to know MU is ready now */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | + BIT(26) | BIT(27), mu_base + MU_ACR); + + pr_info("MU is ready for cross core communication!\n"); + + return 0; +} + +static const struct of_device_id imx_mu_ids[] = { + { .compatible = "fsl,imx6sx-mu" }, + { .compatible = "fsl,imx7d-mu" }, + { .compatible = "fsl,imx7ulp-mu" }, + { } +}; + +#ifdef CONFIG_PM_SLEEP +static int mu_suspend(struct device *dev) +{ + return 0; +} + +static int mu_resume(struct device *dev) +{ + if (!cpu_is_imx7ulp()) + return 0; + + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + + return 0; +} +#endif +static const struct dev_pm_ops mu_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(mu_suspend, mu_resume) +}; + +static struct platform_driver imx_mu_driver = { + .driver = { + .name = "imx-mu", + .owner = THIS_MODULE, + .pm = &mu_pm_ops, + .of_match_table = imx_mu_ids, + }, + .probe = imx_mu_probe, +}; + +static int __init imx_mu_init(void) +{ + return platform_driver_register(&imx_mu_driver); +} +subsys_initcall(imx_mu_init); diff --git a/arch/arm/mach-imx/mx6.h b/arch/arm/mach-imx/mx6.h new file mode 100644 index 00000000000000..06b8135a995469 --- /dev/null +++ b/arch/arm/mach-imx/mx6.h @@ -0,0 +1,51 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MXC_IOMAP_H__ +#define __ASM_ARCH_MXC_IOMAP_H__ + +#define MX6Q_IO_P2V(x) IMX_IO_P2V(x) +#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x)) + +#define MX6Q_L2_BASE_ADDR 0x00a02000 +#define MX6Q_L2_SIZE 0x1000 +#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000 +#define MX6Q_IOMUXC_SIZE 0x4000 +#define MX6Q_SRC_BASE_ADDR 0x020d8000 +#define MX6Q_SRC_SIZE 0x4000 +#define MX6Q_CCM_BASE_ADDR 0x020c4000 +#define MX6Q_CCM_SIZE 0x4000 +#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 +#define MX6Q_ANATOP_SIZE 0x1000 +#define MX6Q_GPC_BASE_ADDR 0x020dc000 +#define MX6Q_GPC_SIZE 0x4000 +#define MX6Q_SEMA4_BASE_ADDR 0x02290000 +#define MX6Q_SEMA4_SIZE 0x4000 +#define MX6Q_MMDC_P0_BASE_ADDR 0x021b0000 +#define MX6Q_MMDC_P0_SIZE 0x4000 +#define MX6Q_MMDC_P1_BASE_ADDR 0x021b4000 +#define MX6Q_MMDC_P1_SIZE 0x4000 +#define MX6Q_AIPS1_BASE_ADDR 0x02000000 +#define MX6Q_AIPS1_SIZE 0x100000 +#define MX6Q_AIPS2_BASE_ADDR 0x02100000 +#define MX6Q_AIPS2_SIZE 0x100000 +#define MX6Q_AIPS3_BASE_ADDR 0x02200000 +#define MX6Q_AIPS3_SIZE 0x100000 + +#define MX6SX_IRAM_TLB_BASE_ADDR 0x008f8000 +#define MX6Q_IRAM_TLB_BASE_ADDR 0x00900000 +#define MX6Q_IRAM_TLB_SIZE 0x4000 +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX6_SUSPEND_IRAM_DATA_SIZE 256 +#define MX6SL_WFI_IRAM_DATA_SIZE 100 + +#define MX6_SUSPEND_IRAM_ADDR_OFFSET 0 +#define MX6_CPUIDLE_IRAM_ADDR_OFFSET 0x1000 +#endif diff --git a/arch/arm/mach-imx/mx7.h b/arch/arm/mach-imx/mx7.h new file mode 100644 index 00000000000000..afbeaef12d072e --- /dev/null +++ b/arch/arm/mach-imx/mx7.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V(x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_LPSR_BASE_ADDR 0x30270000 +#define MX7D_LPSR_SIZE 0x10000 +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX7D_IOMUXC_GPR_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_SNVS_BASE_ADDR 0x30370000 +#define MX7D_SNVS_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_DDRC_PHY_BASE_ADDR 0x30790000 +#define MX7D_DDRC_PHY_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 +#define MX7D_GIC_BASE_ADDR 0x31000000 +#define MX7D_GIC_SIZE 0x100000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_CPUIDLE_OCRAM_ADDR_OFFSET 0x1000 +#define MX7_CPUIDLE_OCRAM_SIZE 0x1000 +#define MX7_BUSFREQ_OCRAM_ADDR_OFFSET 0x2000 +#define MX7_BUSFREQ_OCRAM_SIZE 0x1000 + +#endif diff --git a/arch/arm/mach-imx/mx7ulp.h b/arch/arm/mach-imx/mx7ulp.h new file mode 100644 index 00000000000000..a00e86f27e65d1 --- /dev/null +++ b/arch/arm/mach-imx/mx7ulp.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright NXP 2017. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7ULP_IOMAP_H__ +#define __ASM_ARCH_MX7ULP_IOMAP_H__ + +#define MX7ULP_IO_P2V(x) IMX_IO_P2V(x) +#define MX7ULP_IO_ADDRESS(x) IOMEM(MX7ULP_IO_P2V(x)) + +#define MX7ULP_AIPS1_BASE_ADDR 0x40000000 +#define MX7ULP_AIPS1_SIZE 0x100000 +#define MX7ULP_AIPS2_BASE_ADDR 0x40300000 +#define MX7ULP_AIPS2_SIZE 0x100000 +#define MX7ULP_AIPS3_BASE_ADDR 0x40400000 +#define MX7ULP_AIPS3_SIZE 0x100000 +#define MX7ULP_AIPS4_BASE_ADDR 0x40a00000 +#define MX7ULP_AIPS4_SIZE 0x100000 +#define MX7ULP_AIPS5_BASE_ADDR 0x41000000 +#define MX7ULP_AIPS5_SIZE 0x100000 +#define MX7ULP_GPIOC_BASE_ADDR 0x400f0000 +#define MX7ULP_GPIOC_SIZE 0x1000 +#define MX7ULP_PCC3_BASE_ADDR 0x40b30000 +#define MX7ULP_PCC3_SIZE 0x1000 +#define MX7ULP_SCG1_BASE_ADDR 0x403e0000 +#define MX7ULP_SCG1_SIZE 0x1000 +#define MX7ULP_PCC2_BASE_ADDR 0x403f0000 +#define MX7ULP_PCC2_SIZE 0x1000 +#define MX7ULP_SIM_BASE_ADDR 0x410a3000 +#define MX7ULP_SIM_SIZE 0x1000 +#define MX7ULP_PMC1_BASE_ADDR 0x40400000 +#define MX7ULP_PMC1_SIZE 0x1000 +#define MX7ULP_SMC1_BASE_ADDR 0x40410000 +#define MX7ULP_SMC1_SIZE 0x1000 +#define MX7ULP_MMDC_BASE_ADDR 0x40ab0000 +#define MX7ULP_MMDC_SIZE 0x1000 +#define MX7ULP_IOMUXC1_BASE_ADDR 0x40ac0000 +#define MX7ULP_IOMUXC1_BASE__SIZE 0x1000 +#define MX7ULP_MMDC_IO_BASE_ADDR 0x40ad0000 +#define MX7ULP_MMDC_IO_SIZE 0x1000 + +/* below is just used for static mapping of the AIPSx's memory region */ +#define MX7ULP_AIPS_VIRT_BASE(x) (0xf4000000 + ((x) * SZ_1M)) + +#define mx7ulp_aips_map_entry(index, _type) { \ + .virtual = MX7ULP_AIPS_VIRT_BASE(index), \ + .pfn = __phys_to_pfn(MX7ULP_AIPS ## index ## _BASE_ADDR), \ + .length = SZ_1M, \ + .type = _type, \ +} + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7ULP_IRAM_TLB_SIZE 0x4000 +#define MX7ULP_SUSPEND_OCRAM_SIZE 0x1000 + +#endif diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 34f2ff62583c6e..f162e82d3ca154 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -39,9 +39,18 @@ #define MXC_CPU_IMX6SX 0x62 #define MXC_CPU_IMX6Q 0x63 #define MXC_CPU_IMX6UL 0x64 +#define MXC_CPU_IMX6ULL 0x65 +#define MXC_CPU_IMX6SLL 0x67 #define MXC_CPU_IMX7D 0x72 +#define MXC_CPU_IMX7ULP 0xff /* TBD */ +#define IMX_DDR_TYPE_DDR3 0 #define IMX_DDR_TYPE_LPDDR2 1 +#define IMX_DDR_TYPE_LPDDR3 2 +#define IMX_MMDC_DDR_TYPE_LPDDR3 3 + +#define IMX_LPDDR2_1CH_MODE 0 +#define IMX_LPDDR2_2CH_MODE 1 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -73,16 +82,42 @@ static inline bool cpu_is_imx6ul(void) return __mxc_cpu_type == MXC_CPU_IMX6UL; } +static inline bool cpu_is_imx6ull(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6ULL; +} + +static inline bool cpu_is_imx6sll(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SLL; +} + static inline bool cpu_is_imx6q(void) { return __mxc_cpu_type == MXC_CPU_IMX6Q; } +static inline bool cpu_is_imx6(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6Q || + __mxc_cpu_type == MXC_CPU_IMX6DL || + __mxc_cpu_type == MXC_CPU_IMX6SL || + __mxc_cpu_type == MXC_CPU_IMX6SX || + __mxc_cpu_type == MXC_CPU_IMX6UL || + __mxc_cpu_type == MXC_CPU_IMX6ULL || + __mxc_cpu_type == MXC_CPU_IMX6SLL; +} + static inline bool cpu_is_imx7d(void) { return __mxc_cpu_type == MXC_CPU_IMX7D; } +static inline bool cpu_is_imx7ulp(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX7ULP; +} + struct cpu_op { u32 cpu_rate; }; diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 711dbbd5baddaa..1bddda6e69fb34 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -24,7 +24,7 @@ #include "hardware.h" u32 g_diag_reg; -static void __iomem *scu_base; +void __iomem *imx_scu_base; static struct map_desc scu_io_desc __initdata = { /* .virtual and .pfn are run-time assigned */ @@ -43,7 +43,7 @@ void __init imx_scu_map_io(void) scu_io_desc.pfn = __phys_to_pfn(base); iotable_init(&scu_io_desc, 1); - scu_base = IMX_IO_ADDRESS(base); + imx_scu_base = IMX_IO_ADDRESS(base); } static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -53,15 +53,39 @@ static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) return 0; } +#define MXC_ARCH_CA7 0xc07 +static unsigned long __mxc_arch_type; + +static inline bool arm_is_ca7(void) +{ + return __mxc_arch_type == MXC_ARCH_CA7; +} /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ static void __init imx_smp_init_cpus(void) { + unsigned long arch_type; int i, ncores; - ncores = scu_get_core_count(scu_base); + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c0, c0, 0\n" + : "=r" (arch_type) + ); + /* MIDR[15:4] defines ARCH type */ + __mxc_arch_type = (arch_type >> 4) & 0xfff; + + if (arm_is_ca7()) { + unsigned long val; + + /* CA7 core number, [25:24] of CP15 L2CTLR */ + asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + ncores = ((val >> 24) & 0x3) + 1; + } else { + ncores = scu_get_core_count(imx_scu_base); + } for (i = ncores; i < NR_CPUS; i++) set_cpu_possible(i, false); @@ -69,11 +93,15 @@ static void __init imx_smp_init_cpus(void) void imx_smp_prepare(void) { - scu_enable(scu_base); + if (arm_is_ca7()) + return; + scu_enable(imx_scu_base); } static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { + if (arm_is_ca7()) + return; imx_smp_prepare(); /* diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 1515e498d348c6..41e148ee0b3cbe 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -1,5 +1,5 @@ /* - * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -19,11 +19,14 @@ #include #include #include +#include #include #include +#include #include #include #include +#include #include #include #include @@ -60,13 +63,215 @@ #define CGPR 0x64 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) +#define CCGR4 0x78 +#define CCGR6 0x80 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 -#define MX6_MAX_MMDC_IO_NUM 33 +#define MX6_MAX_MMDC_IO_NUM 36 +#define MX6_MAX_MMDC_NUM 36 + +#define ROMC_ROMPATCH0D 0xf0 +#define ROMC_ROMPATCHCNTL 0xf4 +#define ROMC_ROMPATCHENL 0xfc +#define ROMC_ROMPATCH0A 0x100 +#define BM_ROMPATCHCNTL_0D (0x1 << 0) +#define BM_ROMPATCHCNTL_DIS (0x1 << 29) +#define BM_ROMPATCHENL_0D (0x1 << 0) +#define ROM_ADDR_FOR_INTERNAL_RAM_BASE 0x10d7c + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK 0xf800 + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* QSPI register layout */ +#define QSPI_MCR 0x00 +#define QSPI_IPCR 0x08 +#define QSPI_BUF0CR 0x10 +#define QSPI_BUF1CR 0x14 +#define QSPI_BUF2CR 0x18 +#define QSPI_BUF3CR 0x1c +#define QSPI_BFGENCR 0x20 +#define QSPI_BUF0IND 0x30 +#define QSPI_BUF1IND 0x34 +#define QSPI_BUF2IND 0x38 +#define QSPI_SFAR 0x100 +#define QSPI_SMPR 0x108 +#define QSPI_RBSR 0x10c +#define QSPI_RBCT 0x110 +#define QSPI_TBSR 0x150 +#define QSPI_TBDR 0x154 +#define QSPI_SFA1AD 0x180 +#define QSPI_SFA2AD 0x184 +#define QSPI_SFB1AD 0x188 +#define QSPI_SFB2AD 0x18c +#define QSPI_RBDR_BASE 0x200 +#define QSPI_LUTKEY 0x300 +#define QSPI_LCKCR 0x304 +#define QSPI_LUT_BASE 0x310 + +#define QSPI_RBDR_(x) (QSPI_RBDR_BASE + (x) * 4) +#define QSPI_LUT(x) (QSPI_LUT_BASE + (x) * 4) + +#define QSPI_LUTKEY_VALUE 0x5AF05AF0 +#define QSPI_LCKER_LOCK 0x1 +#define QSPI_LCKER_UNLOCK 0x2 + +enum qspi_regs_valuetype { + QSPI_PREDEFINED, + QSPI_RETRIEVED, +}; + +struct qspi_regs { + int offset; + unsigned int value; + enum qspi_regs_valuetype valuetype; +}; +struct qspi_regs qspi_regs_imx6sx[] = { + {QSPI_IPCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF1CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF2CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF3CR, 0, QSPI_RETRIEVED}, + {QSPI_BFGENCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF1IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF2IND, 0, QSPI_RETRIEVED}, + {QSPI_SFAR, 0, QSPI_RETRIEVED}, + {QSPI_SMPR, 0, QSPI_RETRIEVED}, + {QSPI_RBSR, 0, QSPI_RETRIEVED}, + {QSPI_RBCT, 0, QSPI_RETRIEVED}, + {QSPI_TBSR, 0, QSPI_RETRIEVED}, + {QSPI_TBDR, 0, QSPI_RETRIEVED}, + {QSPI_SFA1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFA2AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB2AD, 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(0), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(1), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(2), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(3), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(4), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(5), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(6), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(7), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(8), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(9), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(10), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(11), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(12), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(13), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(14), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(15), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(16), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(17), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(18), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(19), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(20), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(21), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(22), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(23), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(24), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(25), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(26), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(27), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(28), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(29), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(30), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(31), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_UNLOCK, QSPI_PREDEFINED}, + {QSPI_LUT(0), 0, QSPI_RETRIEVED}, + {QSPI_LUT(1), 0, QSPI_RETRIEVED}, + {QSPI_LUT(2), 0, QSPI_RETRIEVED}, + {QSPI_LUT(3), 0, QSPI_RETRIEVED}, + {QSPI_LUT(4), 0, QSPI_RETRIEVED}, + {QSPI_LUT(5), 0, QSPI_RETRIEVED}, + {QSPI_LUT(6), 0, QSPI_RETRIEVED}, + {QSPI_LUT(7), 0, QSPI_RETRIEVED}, + {QSPI_LUT(8), 0, QSPI_RETRIEVED}, + {QSPI_LUT(9), 0, QSPI_RETRIEVED}, + {QSPI_LUT(10), 0, QSPI_RETRIEVED}, + {QSPI_LUT(11), 0, QSPI_RETRIEVED}, + {QSPI_LUT(12), 0, QSPI_RETRIEVED}, + {QSPI_LUT(13), 0, QSPI_RETRIEVED}, + {QSPI_LUT(14), 0, QSPI_RETRIEVED}, + {QSPI_LUT(15), 0, QSPI_RETRIEVED}, + {QSPI_LUT(16), 0, QSPI_RETRIEVED}, + {QSPI_LUT(17), 0, QSPI_RETRIEVED}, + {QSPI_LUT(18), 0, QSPI_RETRIEVED}, + {QSPI_LUT(19), 0, QSPI_RETRIEVED}, + {QSPI_LUT(20), 0, QSPI_RETRIEVED}, + {QSPI_LUT(21), 0, QSPI_RETRIEVED}, + {QSPI_LUT(22), 0, QSPI_RETRIEVED}, + {QSPI_LUT(23), 0, QSPI_RETRIEVED}, + {QSPI_LUT(24), 0, QSPI_RETRIEVED}, + {QSPI_LUT(25), 0, QSPI_RETRIEVED}, + {QSPI_LUT(26), 0, QSPI_RETRIEVED}, + {QSPI_LUT(27), 0, QSPI_RETRIEVED}, + {QSPI_LUT(28), 0, QSPI_RETRIEVED}, + {QSPI_LUT(29), 0, QSPI_RETRIEVED}, + {QSPI_LUT(30), 0, QSPI_RETRIEVED}, + {QSPI_LUT(31), 0, QSPI_RETRIEVED}, + {QSPI_LUT(32), 0, QSPI_RETRIEVED}, + {QSPI_LUT(33), 0, QSPI_RETRIEVED}, + {QSPI_LUT(34), 0, QSPI_RETRIEVED}, + {QSPI_LUT(35), 0, QSPI_RETRIEVED}, + {QSPI_LUT(36), 0, QSPI_RETRIEVED}, + {QSPI_LUT(37), 0, QSPI_RETRIEVED}, + {QSPI_LUT(38), 0, QSPI_RETRIEVED}, + {QSPI_LUT(39), 0, QSPI_RETRIEVED}, + {QSPI_LUT(40), 0, QSPI_RETRIEVED}, + {QSPI_LUT(41), 0, QSPI_RETRIEVED}, + {QSPI_LUT(42), 0, QSPI_RETRIEVED}, + {QSPI_LUT(43), 0, QSPI_RETRIEVED}, + {QSPI_LUT(44), 0, QSPI_RETRIEVED}, + {QSPI_LUT(45), 0, QSPI_RETRIEVED}, + {QSPI_LUT(46), 0, QSPI_RETRIEVED}, + {QSPI_LUT(47), 0, QSPI_RETRIEVED}, + {QSPI_LUT(48), 0, QSPI_RETRIEVED}, + {QSPI_LUT(49), 0, QSPI_RETRIEVED}, + {QSPI_LUT(50), 0, QSPI_RETRIEVED}, + {QSPI_LUT(51), 0, QSPI_RETRIEVED}, + {QSPI_LUT(52), 0, QSPI_RETRIEVED}, + {QSPI_LUT(53), 0, QSPI_RETRIEVED}, + {QSPI_LUT(54), 0, QSPI_RETRIEVED}, + {QSPI_LUT(55), 0, QSPI_RETRIEVED}, + {QSPI_LUT(56), 0, QSPI_RETRIEVED}, + {QSPI_LUT(57), 0, QSPI_RETRIEVED}, + {QSPI_LUT(58), 0, QSPI_RETRIEVED}, + {QSPI_LUT(59), 0, QSPI_RETRIEVED}, + {QSPI_LUT(60), 0, QSPI_RETRIEVED}, + {QSPI_LUT(61), 0, QSPI_RETRIEVED}, + {QSPI_LUT(62), 0, QSPI_RETRIEVED}, + {QSPI_LUT(63), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_LOCK, QSPI_PREDEFINED}, + {QSPI_MCR, 0, QSPI_RETRIEVED}, +}; + +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static void __iomem *console_base; +static void __iomem *qspi_base; +static unsigned int ocram_size; static void __iomem *ccm_base; static void __iomem *suspend_ocram_base; static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct regmap *romcp; /* * suspend ocram space layout: @@ -96,6 +301,8 @@ struct imx6_pm_socdata { const char *pl310_compat; const u32 mmdc_io_num; const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; }; static const u32 imx6q_mmdc_io_offset[] __initconst = { @@ -110,6 +317,18 @@ static const u32 imx6q_mmdc_io_offset[] __initconst = { 0x74c, /* GPR_ADDS */ }; +static const u32 imx6q_mmdc_io_lpddr2_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, 0x590, 0x598, 0x57c, /* GRP_ADDS, SDCKE0, SDCKE1, RESET */ +}; + static const u32 imx6dl_mmdc_io_offset[] __initconst = { 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ @@ -130,6 +349,27 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = { 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ }; +static const u32 imx6sx_mmdc_io_lpddr2_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ + 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x324, 0x328, 0x340, /* DRAM_SDCKE0 ~ 1, DRAM_RESET */ +}; + +static const u32 imx6sx_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x824, + 0x828, 0x82c, 0x830, 0x834, + 0x838, 0x848, 0x850, 0x8c0, + 0x83c, 0x840, 0x8b8, 0x00c, + 0x004, 0x010, 0x014, 0x018, + 0x02c, 0x030, 0x038, 0x008, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + static const u32 imx6sx_mmdc_io_offset[] __initconst = { 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ @@ -138,6 +378,16 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = { 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ }; +static const u32 imx6sx_mmdc_offset[] __initconst = { + 0x800, 0x80c, 0x810, 0x83c, + 0x840, 0x848, 0x850, 0x81c, + 0x820, 0x824, 0x828, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + static const u32 imx6ul_mmdc_io_offset[] __initconst = { 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ @@ -145,6 +395,53 @@ static const u32 imx6ul_mmdc_io_offset[] __initconst = { 0x494, 0x4b0, /* MODE_CTL, MODE, */ }; +static const u32 imx6ul_mmdc_offset[] __initconst = { + 0x01c, 0x800, 0x80c, 0x83c, + 0x848, 0x850, 0x81c, 0x820, + 0x82c, 0x830, 0x8c0, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + +static const u32 imx6ul_mmdc_io_lpddr2_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, 0x274, 0x278, /* MODE_CTL, MODE, SDCKE0, SDCKE1 */ + 0x288, /* DRAM_RESET */ +}; + +static const u32 imx6ul_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +}; + +static const u32 imx6sll_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .mmdc_compat = "fsl,imx6q-mmdc", .src_compat = "fsl,imx6q-src", @@ -153,6 +450,19 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), .mmdc_io_offset = imx6q_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, +}; + +static const struct imx6_pm_socdata imx6q_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6q_mmdc_io_lpddr2_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { @@ -163,6 +473,8 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), .mmdc_io_offset = imx6dl_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { @@ -173,6 +485,8 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), .mmdc_io_offset = imx6sl_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { @@ -183,6 +497,19 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), .mmdc_io_offset = imx6sx_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_offset), + .mmdc_offset = imx6sx_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6sx_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sx-mmdc", + .src_compat = "fsl,imx6sx-src", + .iomuxc_compat = "fsl,imx6sx-iomuxc", + .gpc_compat = "fsl,imx6sx-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6sx_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_lpddr2_offset), + .mmdc_offset = imx6sx_mmdc_lpddr2_offset, }; static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { @@ -193,6 +520,61 @@ static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { .pl310_compat = NULL, .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), .mmdc_io_offset = imx6ul_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_offset), + .mmdc_offset = imx6ul_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6ul_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6ul-mmdc", + .src_compat = "fsl,imx6ul-src", + .iomuxc_compat = "fsl,imx6ul-iomuxc", + .gpc_compat = "fsl,imx6ul-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6ul_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_lpddr2_offset), + .mmdc_offset = imx6ul_mmdc_lpddr2_offset, +}; + +static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sll-mmdc", + .src_compat = "fsl,imx6sll-src", + .iomuxc_compat = "fsl,imx6sll-iomuxc", + .gpc_compat = "fsl,imx6sll-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), + .mmdc_io_offset = imx6sll_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sll_mmdc_lpddr3_offset), + .mmdc_offset = imx6sll_mmdc_lpddr3_offset, +}; + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +/* + * AIPS1 and AIPS2 is not used, because it will trigger a BUG_ON if + * lowlevel debug and earlyprintk are configured. + * + * it is because there is a vm conflict because UART1 is mapped early if + * AIPS1 is mapped using 1M size. + * + * Thus no use AIPS1 and AIPS2 to avoid kernel BUG_ON. + */ +static struct map_desc imx6_pm_io_desc[] __initdata = { + imx_map_entry(MX6Q, MMDC_P0, MT_DEVICE), + imx_map_entry(MX6Q, MMDC_P1, MT_DEVICE), + imx_map_entry(MX6Q, SRC, MT_DEVICE), + imx_map_entry(MX6Q, IOMUXC, MT_DEVICE), + imx_map_entry(MX6Q, CCM, MT_DEVICE), + imx_map_entry(MX6Q, ANATOP, MT_DEVICE), + imx_map_entry(MX6Q, GPC, MT_DEVICE), + imx_map_entry(MX6Q, L2, MT_DEVICE), +}; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL }; /* @@ -207,14 +589,19 @@ struct imx6_cpu_pm_info { phys_addr_t resume_addr; /* The physical resume address for asm code */ u32 ddr_type; u32 pm_info_size; /* Size of pm_info. */ - struct imx6_pm_base mmdc_base; + struct imx6_pm_base mmdc0_base; + struct imx6_pm_base mmdc1_base; struct imx6_pm_base src_base; struct imx6_pm_base iomuxc_base; struct imx6_pm_base ccm_base; struct imx6_pm_base gpc_base; struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + u32 ttbr1; /* Store TTBR1 */ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ - u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][3]; /* To save offset, value, low power settings */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX6_MAX_MMDC_NUM][2]; } __aligned(8); void imx6_set_int_mem_clk_lpm(bool enable) @@ -293,10 +680,18 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x2 << BP_CLPCR_LPM; val &= ~BM_CLPCR_VSTBY; val &= ~BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -310,10 +705,18 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl() || cpu_is_imx6sx()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -335,9 +738,11 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) * * Note that IRQ #32 is GIC SPI #0. */ - imx_gpc_hwirq_unmask(0); + if (mode != WAIT_CLOCKED) + imx_gpc_hwirq_unmask(0); writel_relaxed(val, ccm_base + CLPCR); - imx_gpc_hwirq_mask(0); + if (mode != WAIT_CLOCKED) + imx_gpc_hwirq_mask(0); return 0; } @@ -362,19 +767,104 @@ static int imx6q_suspend_finish(unsigned long val) return 0; } +static void imx6_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx6_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx6_qspi_save(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) { + if (QSPI_RETRIEVED == pregs[i].valuetype) + pregs[i].value = readl_relaxed(qspi_base + + pregs[i].offset); + } +} + +static void imx6_qspi_restore(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) + writel_relaxed(pregs[i].value, qspi_base + pregs[i].offset); +} + static int imx6q_pm_enter(suspend_state_t state) { + unsigned int console_saved_reg[10] = {0}; + static unsigned int ccm_ccgr4, ccm_ccgr6; + +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + if (imx_gpc_is_m4_sleeping() && imx_mu_is_m4_in_low_freq()) { + imx_gpc_hold_m4_in_sleep(); + imx_mu_enable_m4_irqs_in_gic(true); + } else { + pr_info("M4 is busy, enter WAIT mode instead of STOP!\n"); + imx6_set_lpm(WAIT_UNCLOCKED); + imx6_set_int_mem_clk_lpm(true); + imx_gpc_pre_suspend(false); + /* Zzz ... */ + cpu_do_idle(); + imx_gpc_post_resume(); + imx6_set_lpm(WAIT_CLOCKED); + + return 0; + } + } +#endif switch (state) { case PM_SUSPEND_STANDBY: imx6_set_lpm(STOP_POWER_ON); imx6_set_int_mem_clk_lpm(true); imx_gpc_pre_suspend(false); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(true); +#endif /* Zzz ... */ cpu_do_idle(); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(false); +#endif imx_gpc_post_resume(); imx6_set_lpm(WAIT_CLOCKED); break; @@ -390,8 +880,50 @@ static int imx6q_pm_enter(suspend_state_t state) imx6_enable_rbc(true); imx_gpc_pre_suspend(true); imx_anatop_pre_suspend(); + if ((cpu_is_imx6ull() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_save(console_saved_reg); + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + ccm_ccgr4 = readl_relaxed(ccm_base + CCGR4); + ccm_ccgr6 = readl_relaxed(ccm_base + CCGR6); + /* + * i.MX6SX RDC needs PCIe and eim clk to be enabled + * if Mega/Fast off, it is better to check cpu type + * and whether Mega/Fast is off in this suspend flow, + * but we need to add cpu type check for 3 places which + * will increase code size, so here we just do it + * for all cases, as when STOP mode is entered, CCM + * hardware will gate all clocks, so it will NOT impact + * any function or power. + */ + writel_relaxed(ccm_ccgr4 | (0x3 << 0), ccm_base + + CCGR4); + writel_relaxed(ccm_ccgr6 | (0x3 << 10), ccm_base + + CCGR6); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + imx6_console_save(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_save(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); + + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + writel_relaxed(ccm_ccgr4, ccm_base + CCGR4); + writel_relaxed(ccm_ccgr6, ccm_base + CCGR6); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx6_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_restore(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + if ((cpu_is_imx6ull() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_restore(console_saved_reg); if (cpu_is_imx6q() || cpu_is_imx6dl()) imx_smp_prepare(); imx_anatop_post_resume(); @@ -405,6 +937,13 @@ static int imx6q_pm_enter(suspend_state_t state) return -EINVAL; } +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + imx_mu_enable_m4_irqs_in_gic(false); + imx_gpc_release_m4_in_sleep(); + } +#endif + return 0; } @@ -418,44 +957,109 @@ static const struct platform_suspend_ops imx6q_pm_ops = { .valid = imx6q_pm_valid, }; -static int __init imx6_pm_get_base(struct imx6_pm_base *base, - const char *compat) +static int __init imx6_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) { - struct device_node *node; - struct resource res; - int ret = 0; + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; - node = of_find_compatible_node(NULL, NULL, compat); - if (!node) { - ret = -ENODEV; - goto out; + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + + iotable_init(&iram_tlb_io_desc, 1); } - ret = of_address_to_resource(node, 0, &res); - if (ret) - goto put_node; + return 0; +} - base->pbase = res.start; - base->vbase = ioremap(res.start, resource_size(&res)); - if (!base->vbase) - ret = -ENOMEM; +void __init imx6_pm_map_io(void) +{ + unsigned long i; -put_node: - of_node_put(node); -out: - return ret; + iotable_init(imx6_pm_io_desc, ARRAY_SIZE(imx6_pm_io_desc)); + + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx6_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return; + } + + /* Set all entries to 0. */ + memset((void *)iram_tlb_base_addr, 0, MX6Q_IRAM_TLB_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 11 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + i = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS1_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS1_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS2_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS3_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS3_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the L2 controller virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_L2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_L2_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; } static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) { - phys_addr_t ocram_pbase; struct device_node *node; - struct platform_device *pdev; struct imx6_cpu_pm_info *pm_info; - struct gen_pool *ocram_pool; - unsigned long ocram_base; + unsigned long iram_paddr; int i, ret = 0; const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; suspend_set_ops(&imx6q_pm_ops); @@ -464,41 +1068,24 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) return -EINVAL; } - node = of_find_compatible_node(NULL, NULL, "mmio-sram"); - if (!node) { - pr_warn("%s: failed to find ocram node!\n", __func__); - return -ENODEV; - } - - pdev = of_find_device_by_node(node); - if (!pdev) { - pr_warn("%s: failed to find ocram device!\n", __func__); - ret = -ENODEV; - goto put_node; - } - - ocram_pool = gen_pool_get(&pdev->dev, NULL); - if (!ocram_pool) { - pr_warn("%s: ocram pool unavailable!\n", __func__); - ret = -ENODEV; - goto put_node; - } - - ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); - if (!ocram_base) { - pr_warn("%s: unable to alloc ocram!\n", __func__); - ret = -ENOMEM; - goto put_node; - } + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX6_SUSPEND_IRAM_ADDR_OFFSET; - ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); - suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, - MX6Q_SUSPEND_OCRAM_SIZE, false); + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); memset(suspend_ocram_base, 0, sizeof(*pm_info)); pm_info = suspend_ocram_base; - pm_info->pbase = ocram_pbase; + pm_info->pbase = iram_paddr; pm_info->resume_addr = virt_to_phys(v7_cpu_resume); pm_info->pm_info_size = sizeof(*pm_info); @@ -506,53 +1093,120 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) * ccm physical address is not used by asm code currently, * so get ccm virtual address directly. */ - pm_info->ccm_base.vbase = ccm_base; + pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); - if (ret) { - pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); - goto put_node; - } + pm_info->mmdc0_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + pm_info->mmdc0_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); - if (ret) { - pr_warn("%s: failed to get src base %d!\n", __func__, ret); - goto src_map_failed; - } + pm_info->mmdc1_base.pbase = MX6Q_MMDC_P1_BASE_ADDR; + pm_info->mmdc1_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); - if (ret) { - pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); - goto iomuxc_map_failed; - } + pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); - if (ret) { - pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); - goto gpc_map_failed; - } + pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + pm_info->iomuxc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); - if (socdata->pl310_compat) { - ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); - if (ret) { - pr_warn("%s: failed to get pl310-cache base %d!\n", - __func__, ret); - goto pl310_cache_map_failed; - } - } + pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + pm_info->l2_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); pm_info->ddr_type = imx_mmdc_get_ddr_type(); pm_info->mmdc_io_num = socdata->mmdc_io_num; - mmdc_offset_array = socdata->mmdc_io_offset; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; for (i = 0; i < pm_info->mmdc_io_num; i++) { pm_info->mmdc_io_val[i][0] = - mmdc_offset_array[i]; + mmdc_io_offset_array[i]; pm_info->mmdc_io_val[i][1] = readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_io_offset_array[i]); + pm_info->mmdc_io_val[i][2] = 0; + } + + /* i.MX6SLL has no DRAM RESET pin */ + if (cpu_is_imx6sll()) { + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x1000; + } else { + if (pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + /* for LPDDR2, CKE0/1 and RESET pin need special setting */ + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 3][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x80000; + } + } + + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) { + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_val[i][1] = + readl_relaxed(pm_info->mmdc0_base.vbase + mmdc_offset_array[i]); } + if (cpu_is_imx6sll() && pm_info->ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x400000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20052; + pm_info->mmdc_val[20][1] = 0x201718; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; + } + + /* need to overwrite the value for some mmdc registers */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull()) && + pm_info->ddr_type != IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[20][1] = (pm_info->mmdc_val[20][1] + & 0xffff0000) | 0x0202; + pm_info->mmdc_val[23][1] = 0x8033; + } + + if (cpu_is_imx6sx() && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x380000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[18][1] = 0x800; + pm_info->mmdc_val[20][1] = 0x20024; + pm_info->mmdc_val[23][1] = 0x1748; + pm_info->mmdc_val[32][1] = 0xa1310003; + } + + if ((cpu_is_imx6ul() || cpu_is_imx6ull()) && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x470000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20012; + pm_info->mmdc_val[20][1] = 0x1748; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; + } + imx6_suspend_in_ocram_fn = fncpy( suspend_ocram_base + sizeof(*pm_info), &imx6_suspend, @@ -560,14 +1214,6 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) goto put_node; -pl310_cache_map_failed: - iounmap(pm_info->gpc_base.vbase); -gpc_map_failed: - iounmap(pm_info->iomuxc_base.vbase); -iomuxc_map_failed: - iounmap(pm_info->src_base.vbase); -src_map_failed: - iounmap(pm_info->mmdc_base.vbase); put_node: of_node_put(node); @@ -622,7 +1268,10 @@ void __init imx6_pm_ccm_init(const char *ccm_compat) void __init imx6q_pm_init(void) { - imx6_pm_common_init(&imx6q_pm_data); + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6q_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6q_pm_data); } void __init imx6dl_pm_init(void) @@ -632,15 +1281,96 @@ void __init imx6dl_pm_init(void) void __init imx6sl_pm_init(void) { + struct device_node *np; + struct regmap *gpr; + + if (cpu_is_imx6sll()) { + imx6_pm_common_init(&imx6sll_pm_data); + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + /* i.MX6SLL has bus auto clock gating function */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK, 0); + return; + } + imx6_pm_common_init(&imx6sl_pm_data); } void __init imx6sx_pm_init(void) { - imx6_pm_common_init(&imx6sx_pm_data); + struct device_node *np; + struct resource res; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6sx_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6sx_pm_data); + if (imx_get_soc_revision() < IMX_CHIP_REVISION_1_2) { + /* + * As there is a 16K OCRAM(start from 0x8f8000) + * dedicated for low power function on i.MX6SX, + * but ROM did NOT do the ocram address change + * accordingly, so we need to add a data patch + * to workaround this issue, otherwise, system + * will fail to resume from DSM mode. TO1.2 fixes + * this issue. + */ + romcp = syscon_regmap_lookup_by_compatible( + "fsl,imx6sx-romcp"); + if (IS_ERR(romcp)) { + pr_err("failed to find fsl,imx6sx-romcp regmap\n"); + return; + } + regmap_write(romcp, ROMC_ROMPATCH0D, iram_tlb_phys_addr); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_0D, BM_ROMPATCHCNTL_0D); + regmap_update_bits(romcp, ROMC_ROMPATCHENL, + BM_ROMPATCHENL_0D, BM_ROMPATCHENL_0D); + regmap_write(romcp, ROMC_ROMPATCH0A, + ROM_ADDR_FOR_INTERNAL_RAM_BASE); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_DIS, ~BM_ROMPATCHCNTL_DIS); + } + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + if (imx_src_is_m4_enabled()) { + np = of_find_compatible_node(NULL, NULL, + "fsl,imx6sx-qspi-m4-restore"); + if (np) + qspi_base = of_iomap(np, 0); + WARN_ON(!qspi_base); + } } void __init imx6ul_pm_init(void) { - imx6_pm_common_init(&imx6ul_pm_data); + struct device_node *np; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6ul_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6ul_pm_data); + + if (cpu_is_imx6ull()) { + np = of_find_node_by_path( + "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000"); + if (np) + console_base = of_iomap(np, 0); + } } diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c new file mode 100644 index 00000000000000..540bc8effecf00 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7.c @@ -0,0 +1,1187 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" +#include "cpuidle.h" + +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_MAX_DDRC_NUM 32 +#define MX7_MAX_DDRC_PHY_NUM 16 + +#define MX7_SUSPEND_IRAM_ADDR_OFFSET 0 +#define READ_DATA_FROM_HARDWARE 0 + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define MAX_IOMUXC_GPR 23 +#define MAX_UART_IO 4 +#define MAX_CCM_LPCG 167 +#define MAX_GPT 3 +#define MAX_GPIO_ROW 7 +#define MAX_GPIO_COL 8 + +#define UART_RX_IO 0x128 +#define UART_RX_PAD 0x398 +#define UART_TX_IO 0x12c +#define UART_TX_PAD 0x39c + +#define GPT_CR 0x0 +#define GPT_PR 0x4 +#define GPT_IR 0xc + +#define CCM_LPCG_START 0x4040 +#define CCM_LPCG_STEP 0x10 +#define CCM_EIM_LPCG 0x4160 +#define CCM_PXP_LPCG 0x44c0 +#define CCM_PCIE_LPCG 0x4600 + +#define BM_CCM_ROOT_POST_PODF 0x3f +#define BM_CCM_ROOT_PRE_PODF 0x70000 +#define BM_CCM_ROOT_MUX 0x7000000 +#define BM_CCM_ROOT_ENABLE 0x10000000 + +#define BM_SYS_COUNTER_CNTCR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTCR_FCR0 0x100 + +#define PFD_A_OFFSET 0xc0 +#define PFD_B_OFFSET 0xd0 + +#define PLL_ARM_OFFSET 0x60 +#define PLL_DDR_OFFSET 0x70 +#define PLL_DDR_SS_OFFSET 0x80 +#define PLL_DDR_NUM_OFFSET 0x90 +#define PLL_DDR_DENOM_OFFSET 0xa0 +#define PLL_480_OFFSET 0xb0 +#define PLL_ENET_OFFSET 0xe0 +#define PLL_AUDIO_OFFSET 0xf0 +#define PLL_AUDIO_SS_OFFSET 0x100 +#define PLL_AUDIO_NUM_OFFSET 0x110 +#define PLL_AUDIO_DENOM_OFFSET 0x120 +#define PLL_VIDEO_OFFSET 0x130 +#define PLL_VIDEO_SS_OFFSET 0x140 +#define PLL_VIDEO_NUM_OFFSET 0x150 +#define PLL_VIDEO_DENOM_OFFSET 0x160 + +#define REG_SET 0x4 +#define REG_CLR 0x8 + +#define GPIO_DR 0x0 +#define GPIO_GDIR 0x4 +#define GPIO_ICR1 0xc +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_EDGE 0x1c + +#define M4RCR 0x0C +#define M4_SP_OFF 0x00 +#define M4_PC_OFF 0x04 +#define M4_RCR_HALT 0xAB +#define M4_RCR_GO 0xAA +#define M4_OCRAMS_RESERVED_SIZE 0xc + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static unsigned int ocram_size; +static unsigned int *lpm_ocram_saved_in_ddr; +static void __iomem *lpm_ocram_base; + +static unsigned int *lpm_m4tcm_saved_in_ddr; +static void __iomem *lpm_m4tcm_base; +static void __iomem *m4_bootrom_base; + +static unsigned int lpm_ocram_size; +static void __iomem *ccm_base; +static void __iomem *lpsr_base; +static void __iomem *console_base; +static void __iomem *suspend_ocram_base; +static void __iomem *iomuxc_base; +static void __iomem *gpt1_base; +static void __iomem *system_counter_ctrl_base; +static void __iomem *system_counter_cmp_base; +static void __iomem *gpio1_base; +static void (*imx7_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct imx7_cpu_pm_info *pm_info; +static bool lpsr_enabled; +static u32 iomuxc_gpr[MAX_IOMUXC_GPR]; +static u32 uart1_io[MAX_UART_IO]; +static u32 ccm_lpcg[MAX_CCM_LPCG]; +static u32 ccm_root[][2] = { + {0x8000, 0}, {0x8080, 0}, {0x8100, 0}, {0x8800, 0}, + {0x8880, 0}, {0x8900, 0}, {0x8980, 0}, {0x9000, 0}, + {0x9800, 0}, {0x9880, 0}, {0xa000, 0}, {0xa080, 0}, + {0xa100, 0}, {0xa180, 0}, {0xa200, 0}, {0xa280, 0}, + {0xa300, 0}, {0xa380, 0}, {0xa400, 0}, {0xa480, 0}, + {0xa500, 0}, {0xa580, 0}, {0xa600, 0}, {0xa680, 0}, + {0xa700, 0}, {0xa780, 0}, {0xa800, 0}, {0xa880, 0}, + {0xa900, 0}, {0xa980, 0}, {0xaa00, 0}, {0xaa80, 0}, + {0xab00, 0}, {0xab80, 0}, {0xac00, 0}, {0xac80, 0}, + {0xad00, 0}, {0xad80, 0}, {0xae00, 0}, {0xae80, 0}, + {0xaf00, 0}, {0xaf80, 0}, {0xb000, 0}, {0xb080, 0}, + {0xb100, 0}, {0xb180, 0}, {0xb200, 0}, {0xb280, 0}, + {0xb300, 0}, {0xb380, 0}, {0xb400, 0}, {0xb480, 0}, + {0xb500, 0}, {0xb580, 0}, {0xb600, 0}, {0xb680, 0}, + {0xb700, 0}, {0xb780, 0}, {0xb800, 0}, {0xb880, 0}, + {0xb900, 0}, {0xb980, 0}, {0xba00, 0}, {0xba80, 0}, + {0xbb00, 0}, {0xbb80, 0}, {0xbc00, 0}, {0xbc80, 0}, + {0xbd00, 0}, {0xbd80, 0}, {0xbe00, 0}, +}; +static u32 pfd_a, pfd_b; +static u32 pll[15]; +static u32 gpt1_regs[MAX_GPT]; +static u32 sys_ctrl_reg, sys_cmp_reg; +static u32 gpio_reg[MAX_GPIO_ROW][MAX_GPIO_COL]; +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_pm_socdata { + u32 ddr_type; + const char *ddrc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const u32 ddrc_num; + const u32 (*ddrc_offset)[2]; + const u32 ddrc_phy_num; + const u32 (*ddrc_phy_offset)[2]; +}; + +static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x118, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x11c, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x184, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x8, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x1c, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000008 }, + { 0x50, 0x00000008 }, + { 0xc0, 0x0e487304 }, + { 0xc0, 0x0e4c7304 }, + { 0xc0, 0x0e4c7306 }, + { 0xc0, 0x0e487304 }, +}; + +static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0x490, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xd4, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000010 }, + { 0x50, 0x00000010 }, + { 0xc0, 0x0e407304 }, + { 0xc0, 0x0e447304 }, + { 0xc0, 0x0e447306 }, + { 0xc0, 0x0e407304 }, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_lpddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_lpddr3_setting), + .ddrc_offset = imx7d_ddrc_lpddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_lpddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_lpddr3_setting, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_ddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_ddr3_setting), + .ddrc_offset = imx7d_ddrc_ddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_ddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_ddr3_setting, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx7_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 ddr_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ddrc_phy_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base snvs_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base lpsr_base; + struct imx7_pm_base gic_base; + u32 ttbr1; /* Store TTBR1 */ + u32 ddrc_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ + u32 ddrc_phy_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_phy_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static struct map_desc imx7_pm_io_desc[] __initdata = { + imx_map_entry(MX7D, AIPS1, MT_DEVICE), + imx_map_entry(MX7D, AIPS2, MT_DEVICE), + imx_map_entry(MX7D, AIPS3, MT_DEVICE), +}; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL +}; + +static void imx7_gpio_save(void) +{ + u32 i; + + for (i = 0; i < 7; i++) { + gpio_reg[i][0] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_DR); + gpio_reg[i][1] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_GDIR); + gpio_reg[i][3] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR1); + gpio_reg[i][4] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR2); + gpio_reg[i][5] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_IMR); + gpio_reg[i][7] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_EDGE); + } +} + +static void imx7_gpio_restore(void) +{ + u32 i, val; + + for (i = 0; i < 7; i++) { + writel_relaxed(gpio_reg[i][1], gpio1_base + + (i << 16) + GPIO_GDIR); + writel_relaxed(gpio_reg[i][3], gpio1_base + + (i << 16) + GPIO_ICR1); + writel_relaxed(gpio_reg[i][4], gpio1_base + + (i << 16) + GPIO_ICR2); + writel_relaxed(gpio_reg[i][5], gpio1_base + + (i << 16) + GPIO_IMR); + writel_relaxed(gpio_reg[i][7], gpio1_base + + (i << 16) + GPIO_EDGE); + /* only restore output gpio value */ + val = readl_relaxed(gpio1_base + (i << 16) + GPIO_DR) | + (gpio_reg[i][0] & gpio_reg[i][1]); + writel_relaxed(val, gpio1_base + (i << 16) + GPIO_DR); + } +} + +static void imx7_ccm_save(void) +{ + u32 i; + + for (i = 0; i < MAX_CCM_LPCG; i++) + ccm_lpcg[i] = readl_relaxed(pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + pfd_a = readl_relaxed(pm_info->anatop_base.vbase + PFD_A_OFFSET); + pfd_b = readl_relaxed(pm_info->anatop_base.vbase + PFD_B_OFFSET); + + pll[0] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + pll[1] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + pll[2] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + pll[3] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + pll[4] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + pll[5] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_480_OFFSET); + pll[6] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + pll[7] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + pll[8] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + pll[9] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + pll[10] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + pll[11] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + pll[12] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + pll[13] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + pll[14] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + /* enable all PLLs/PFDs for saving CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + 0x8); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + 0x4); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) + ccm_root[i][1] = readl_relaxed( + pm_info->ccm_base.vbase + ccm_root[i][0]); +} + +static void imx7_ccm_restore(void) +{ + u32 i, val; + + /* enable all PLLs/PFDs for restoring CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + REG_CLR); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + REG_SET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) { + val = readl_relaxed(pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore post podf */ + val &= ~BM_CCM_ROOT_POST_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_POST_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* resotre pre podf */ + val &= ~BM_CCM_ROOT_PRE_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_PRE_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore mux */ + val &= ~BM_CCM_ROOT_MUX; + val |= ccm_root[i][1] & BM_CCM_ROOT_MUX; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore enable */ + val &= ~BM_CCM_ROOT_ENABLE; + val |= ccm_root[i][1] & BM_CCM_ROOT_ENABLE; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + } + + /* restore PLLs */ + writel_relaxed(pll[0], pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + writel_relaxed(pll[1], pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + writel_relaxed(pll[2], pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + writel_relaxed(pll[3], pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + writel_relaxed(pll[4], pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + writel_relaxed(pll[5], pm_info->anatop_base.vbase + + PLL_480_OFFSET); + writel_relaxed(pll[6], pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + writel_relaxed(pll[7], pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(pll[8], pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + writel_relaxed(pll[9], pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + writel_relaxed(pll[10], pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + writel_relaxed(pll[11], pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + writel_relaxed(pll[12], pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + writel_relaxed(pll[13], pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + writel_relaxed(pll[14], pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + for (i = 0; i < MAX_CCM_LPCG; i++) + writel_relaxed(ccm_lpcg[i], pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + /* restore PFDs */ + writel_relaxed(pfd_a & 0x80808080, + pm_info->anatop_base.vbase + PFD_A_OFFSET + REG_SET); + writel_relaxed(pfd_a, pm_info->anatop_base.vbase + PFD_A_OFFSET); + + writel_relaxed(pfd_b & 0x80808080, + pm_info->anatop_base.vbase + PFD_B_OFFSET + REG_SET); + writel_relaxed(pfd_b, pm_info->anatop_base.vbase + PFD_B_OFFSET); +} + +static void imx7_sys_counter_save(void) +{ + sys_ctrl_reg = readl_relaxed(system_counter_ctrl_base); + sys_cmp_reg = readl_relaxed(system_counter_cmp_base); +} + +static void imx7_sys_counter_restore(void) +{ + writel_relaxed(sys_ctrl_reg, system_counter_ctrl_base); + writel_relaxed(sys_cmp_reg, system_counter_cmp_base); +} + +static void imx7_gpt_save(void) +{ + gpt1_regs[0] = readl_relaxed(gpt1_base + GPT_CR); + gpt1_regs[1] = readl_relaxed(gpt1_base + GPT_PR); + gpt1_regs[2] = readl_relaxed(gpt1_base + GPT_IR); +} + +static void imx7_gpt_restore(void) +{ + writel_relaxed(gpt1_regs[0], gpt1_base + GPT_CR); + writel_relaxed(gpt1_regs[1], gpt1_base + GPT_PR); + writel_relaxed(gpt1_regs[2], gpt1_base + GPT_IR); +} + +static void imx7_iomuxc_gpr_save(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + iomuxc_gpr[i] = readl_relaxed( + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_iomuxc_gpr_restore(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + writel_relaxed(iomuxc_gpr[i], + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx7_console_io_save(void) +{ + /* save uart1 io, driver resume is too late */ + uart1_io[0] = readl_relaxed(iomuxc_base + UART_RX_IO); + uart1_io[1] = readl_relaxed(iomuxc_base + UART_RX_PAD); + uart1_io[2] = readl_relaxed(iomuxc_base + UART_TX_IO); + uart1_io[3] = readl_relaxed(iomuxc_base + UART_TX_PAD); +} + +static void imx7_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx7_console_io_restore(void) +{ + /* restore uart1 io */ + writel_relaxed(uart1_io[0], iomuxc_base + UART_RX_IO); + writel_relaxed(uart1_io[1], iomuxc_base + UART_RX_PAD); + writel_relaxed(uart1_io[2], iomuxc_base + UART_TX_IO); + writel_relaxed(uart1_io[3], iomuxc_base + UART_TX_PAD); +} + +static int imx7_suspend_finish(unsigned long val) +{ + if (!imx7_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + imx7_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static void imx7_pm_set_lpsr_resume_addr(unsigned long addr) +{ + writel_relaxed(addr, pm_info->lpsr_base.vbase); +} + +static int imx7_pm_is_resume_from_lpsr(void) +{ + return readl_relaxed(lpsr_base); +} + +static int imx7_pm_enter(suspend_state_t state) +{ + unsigned int console_saved_reg[10] = {0}; + u32 val; + + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return -EINVAL; + } + + /* + * arm_arch_timer driver requires system counter to be + * a clock source with CLOCK_SOURCE_SUSPEND_NONSTOP flag + * set, which means hardware system counter needs to keep + * running during suspend, as the base clock for system + * counter is 24MHz which will be disabled in STOP mode, + * so we need to switch system counter's clock to alternate + * (lower) clock, it is based on 32K, from block guide, there + * is no special flow needs to be followed, system counter + * hardware will handle the clock transition. + */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR0; + val |= BM_SYS_COUNTER_CNTCR_FCR1; + writel_relaxed(val, system_counter_ctrl_base); + + switch (state) { + case PM_SUSPEND_STANDBY: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(false); + + /* Zzz ... */ + imx7_suspend_in_ocram_fn(suspend_ocram_base); + + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + case PM_SUSPEND_MEM: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(true); + if (imx_gpcv2_is_mf_mix_off()) { + /* + * per design requirement, EXSC for PCIe/EIM/PXP + * will need clock to recover RDC setting on + * resume, so enable PCIe/EIM LPCG for RDC + * recovery when M/F mix off + */ + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + /* stop m4 if mix will also be shutdown */ + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + writel(M4_RCR_HALT, + pm_info->src_base.vbase + M4RCR); + imx_gpcv2_enable_wakeup_for_m4(); + } + imx7_console_save(console_saved_reg); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + if (lpsr_enabled) { + imx7_pm_set_lpsr_resume_addr(pm_info->resume_addr); + imx7_console_io_save(); + memcpy(lpm_ocram_saved_in_ddr, lpm_ocram_base, + lpm_ocram_size); + imx7_iomuxc_gpr_save(); + imx7_ccm_save(); + imx7_gpt_save(); + imx7_sys_counter_save(); + imx7_gpio_save(); + } + } + + /* Zzz ... */ + cpu_suspend(0, imx7_suspend_finish); + + if (imx7_pm_is_resume_from_lpsr()) { + imx7_console_io_restore(); + memcpy(lpm_ocram_base, lpm_ocram_saved_in_ddr, + lpm_ocram_size); + imx7_iomuxc_gpr_restore(); + imx7_ccm_restore(); + imx7_gpt_restore(); + imx7_sys_counter_restore(); + imx7_gpio_restore(); + imx7d_enable_rcosc(); + } + if (imx_gpcv2_is_mf_mix_off() || + imx7_pm_is_resume_from_lpsr()) { + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx7_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + imx_gpcv2_disable_wakeup_for_m4(); + /* restore M4 image */ + memcpy(lpm_m4tcm_base, + lpm_m4tcm_saved_in_ddr, SZ_32K); + /* kick m4 to enable */ + writel(M4_RCR_GO, + pm_info->src_base.vbase + M4RCR); + /* offset high bus count for m4 image */ + request_bus_freq(BUS_FREQ_HIGH); + /* restore M4 to run mode */ + imx_mu_set_m4_run_mode(); + /* gpc wakeup */ + } + } + /* clear LPSR resume address */ + imx7_pm_set_lpsr_resume_addr(0); + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + default: + return -EINVAL; + } + + /* restore system counter's clock to base clock */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR1; + val |= BM_SYS_COUNTER_CNTCR_FCR0; + writel_relaxed(val, system_counter_ctrl_base); + + return 0; +} + +static int imx7_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM; +} + +static const struct platform_suspend_ops imx7_pm_ops = { + .enter = imx7_pm_enter, + .valid = imx7_pm_valid, +}; + +void __init imx7_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7_pm_map_io(void) +{ + unsigned long i, j; + + iotable_init(imx7_pm_io_desc, ARRAY_SIZE(imx7_pm_io_desc)); + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } + + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)(iram_tlb_base_addr + M4_OCRAMS_RESERVED_SIZE), + 0, MX7_IRAM_TLB_SIZE - M4_OCRAMS_RESERVED_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS1_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS1_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS2_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS2_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS3_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS3_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the GIC virtual address has a mapping in the + * IRAM page table. + */ + j = ((IMX_IO_P2V(MX7D_GIC_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (MX7D_GIC_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; +} + +static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata) +{ + struct device_node *node; + int i, ret = 0; + const u32 (*ddrc_offset_array)[2]; + const u32 (*ddrc_phy_offset_array)[2]; + unsigned long iram_paddr; + + suspend_set_ops(&imx7_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX7_SUSPEND_IRAM_ADDR_OFFSET; + + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); + + pm_info = suspend_ocram_base; + /* pbase points to iram_paddr. */ + pm_info->pbase = iram_paddr; + pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly, as we already have + * it from ccm driver. + */ + pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + pm_info->ddrc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + pm_info->ddrc_phy_base.pbase = MX7D_DDRC_PHY_BASE_ADDR; + pm_info->ddrc_phy_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR); + + pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + pm_info->iomuxc_gpr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + pm_info->snvs_base.pbase = MX7D_SNVS_BASE_ADDR; + pm_info->snvs_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SNVS_BASE_ADDR); + + pm_info->lpsr_base.pbase = MX7D_LPSR_BASE_ADDR; + lpsr_base = pm_info->lpsr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_LPSR_BASE_ADDR); + + pm_info->gic_base.pbase = MX7D_GIC_BASE_ADDR; + pm_info->gic_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + pm_info->ddrc_num = socdata->ddrc_num; + ddrc_offset_array = socdata->ddrc_offset; + pm_info->ddrc_phy_num = socdata->ddrc_phy_num; + ddrc_phy_offset_array = socdata->ddrc_phy_offset; + + /* initialize DDRC settings */ + for (i = 0; i < pm_info->ddrc_num; i++) { + pm_info->ddrc_val[i][0] = ddrc_offset_array[i][0]; + if (ddrc_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_val[i][1] = + readl_relaxed(pm_info->ddrc_base.vbase + + ddrc_offset_array[i][0]); + else + pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1]; + + if (pm_info->ddrc_val[i][0] == 0xd0) + pm_info->ddrc_val[i][1] |= 0xc0000000; + } + + /* initialize DDRC PHY settings */ + for (i = 0; i < pm_info->ddrc_phy_num; i++) { + pm_info->ddrc_phy_val[i][0] = + ddrc_phy_offset_array[i][0]; + if (ddrc_phy_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_phy_val[i][1] = + readl_relaxed(pm_info->ddrc_phy_base.vbase + + ddrc_phy_offset_array[i][0]); + else + pm_info->ddrc_phy_val[i][1] = + ddrc_phy_offset_array[i][1]; + } + + imx7_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7_suspend, + MX7_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + goto put_node; + +put_node: + of_node_put(node); + + return ret; +} + +static void __init imx7_pm_common_init(const struct imx7_pm_socdata + *socdata) +{ + int ret; + struct regmap *gpr; + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_IRQ_MASK, + IMX7D_GPR1_IRQ_MASK); +} + +void __init imx7d_pm_init(void) +{ + struct device_node *np; + struct resource res; + if (imx_src_is_m4_enabled()) { + /* map the 32K of M4 TCM */ + np = of_find_node_by_path( + "/tcml@007f8000"); + if (np) + lpm_m4tcm_base = of_iomap(np, 0); + WARN_ON(!lpm_m4tcm_base); + + /* map the m4 bootrom from dtb */ + np = of_find_node_by_path( + "/soc/sram@00180000"); + if (np) + m4_bootrom_base = of_iomap(np, 0); + WARN_ON(!m4_bootrom_base); + + lpm_m4tcm_saved_in_ddr = kzalloc(SZ_32K, GFP_KERNEL); + WARN_ON(!lpm_m4tcm_saved_in_ddr); + + /* save M4 Image to DDR */ + memcpy(lpm_m4tcm_saved_in_ddr, lpm_m4tcm_base, SZ_32K); + } + np = of_find_compatible_node(NULL, NULL, "fsl,lpm-sram"); + if (of_get_property(np, "fsl,enable-lpsr", NULL)) + lpsr_enabled = true; + + if (lpsr_enabled) { + pr_info("LPSR mode enabled, DSM will go into LPSR mode!\n"); + lpm_ocram_base = of_iomap(np, 0); + WARN_ON(!lpm_ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + lpm_ocram_size = resource_size(&res); + lpm_ocram_saved_in_ddr = kzalloc(lpm_ocram_size, GFP_KERNEL); + WARN_ON(!lpm_ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/iomuxc@30330000"); + if (np) + iomuxc_base = of_iomap(np, 0); + WARN_ON(!iomuxc_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/gpt@302d0000"); + if (np) + gpt1_base = of_iomap(np, 0); + WARN_ON(!gpt1_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30400000/system-counter-cmp@306b0000"); + if (np) + system_counter_cmp_base = of_iomap(np, 0); + WARN_ON(!system_counter_cmp_base); + + np = of_find_node_by_path( + "/soc/aips-bus@30000000/gpio@30200000"); + if (np) + gpio1_base = of_iomap(np, 0); + WARN_ON(!gpio1_base); + } + + np = of_find_node_by_path( + "/soc/aips-bus@30400000/system-counter-ctrl@306c0000"); + if (np) + system_counter_ctrl_base = of_iomap(np, 0); + WARN_ON(!system_counter_ctrl_base); + + if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR3 + || imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx7_pm_common_init(&imx7d_pm_data_lpddr3); + else if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_DDR3) + imx7_pm_common_init(&imx7d_pm_data_ddr3); + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/aips-bus@30800000/serial@30860000"); + if (np) + console_base = of_iomap(np, 0); + + /* clear LPSR resume address first */ + imx7_pm_set_lpsr_resume_addr(0); +} diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c new file mode 100644 index 00000000000000..15aa46837fb0d2 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -0,0 +1,756 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +#define MU_SR 0x60 + +#define PMPROT 0x8 +#define PMCTRL 0x10 +#define PMSTAT 0x18 +#define SRS 0x20 +#define RPC 0x24 +#define SSRS 0x28 +#define SRIE 0x2c +#define SRIF 0x30 +#define CSRE 0x34 +#define MR 0x40 + +#define PMC_HSRUN 0x4 +#define PMC_RUN 0x8 +#define PMC_VLPR 0xc +#define PMC_STOP 0x10 +#define PMC_VLPS 0x14 +#define PMC_LLS 0x18 +#define PMC_VLLS 0x1c +#define PMC_STATUS 0x20 +#define PMC_CTRL 0x24 +#define PMC_SRAMCTRL_0 0x28 +#define PMC_SRAMCTRL_1 0x2c +#define PMC_SRAMCTRL_2 0x30 + +#define BM_PMPROT_AHSRUN (1 << 7) +#define BM_PMPROT_AVLP (1 << 5) +#define BM_PMPROT_ALLS (1 << 3) +#define BM_PMPROT_AVLLS (1 << 1) + +#define BM_PMCTRL_STOPA (1 << 24) +#define BM_PMCTRL_PSTOPO (3 << 16) +#define BM_PMCTRL_RUNM (3 << 8) +#define BM_PMCTRL_STOPM (7 << 0) + +#define BM_VLPS_RBBEN (1 << 28) + +#define BM_CTRL_LDOEN (1 << 31) +#define BM_CTRL_LDOOKDIS (1 << 30) + +#define BM_VLLS_MON1P2HVDHP (1 << 5) +#define BM_VLLS_MON1P2LVDHP (1 << 4) + +#define BP_PMCTRL_STOPM 0 +#define BP_PMCTRL_PSTOPO 16 + +#define MX7ULP_MAX_MMDC_IO_NUM 36 +#define MX7ULP_MAX_MMDC_NUM 50 +#define MX7ULP_MAX_IOMUX_NUM 116 +#define MX7ULP_MAX_SELECT_INPUT_NUM 78 + +#define IOMUX_START 0x0 +#define SELECT_INPUT_START 0x200 + +#define TPM_SC 0x10 +#define TPM_MOD 0x18 +#define TPM_C0SC 0x20 +#define TPM_C0V 0x24 + +#define PCC2_ENABLE_PCS_FIRC ((1 << 30) | (3 << 24)) +#define PCC2_ENABLE (1 << 30) + +#define LPUART_BAUD 0x10 +#define LPUART_CTRL 0x18 +#define LPUART_FIFO 0x28 +#define LPUART_WATER 0x2c + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 + +#define PTC2_LPUART4_TX_OFFSET 0x8 +#define PTC3_LPUART4_RX_OFFSET 0xc +#define PTC2_LPUART4_TX_INPUT_OFFSET 0x248 +#define PTC3_LPUART4_RX_INPUT_OFFSET 0x24c +#define LPUART4_MUX_VALUE (4 << 8) +#define LPUART4_INPUT_VALUE (1) + +#define MU_B_SR_NMIC (1 << 3) + +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define ADDR_1M_MASK 0xFFF00000 + +static void __iomem *smc1_base; +static void __iomem *pmc0_base; +static void __iomem *pmc1_base; +static void __iomem *tpm5_base; +static void __iomem *lpuart4_base; +static void __iomem *iomuxc1_base; +static void __iomem *pcc2_base; +static void __iomem *pcc3_base; +static void __iomem *mu_base; +static void __iomem *scg1_base; +static void __iomem *gpio_base[4]; +static void __iomem *suspend_ocram_base; +static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base); + +static u32 tpm5_regs[4]; +static u32 lpuart4_regs[4]; +static u32 pcc2_regs[25][2] = { + {0x20, 0}, {0x3c, 0}, {0x40, 0}, {0x6c, 0}, + {0x84, 0}, {0x8c, 0}, {0x90, 0}, {0x94, 0}, + {0x98, 0}, {0x9c, 0}, {0xa4, 0}, {0xa8, 0}, + {0xac, 0}, {0xb0, 0}, {0xb4, 0}, {0xb8, 0}, + {0xc4, 0}, {0xcc, 0}, {0xd0, 0}, {0xd4, 0}, + {0xd8, 0}, {0xdc, 0}, {0xe0, 0}, {0xf4, 0}, + {0x10c, 0}, +}; + +static u32 pcc3_regs[16][2] = { + {0x84, 0}, {0x88, 0}, {0x90, 0}, {0x94, 0}, + {0x98, 0}, {0x9c, 0}, {0xa0, 0}, {0xa4, 0}, + {0xa8, 0}, {0xac, 0}, {0xb8, 0}, {0xbc, 0}, + {0xc0, 0}, {0xc4, 0}, {0x140, 0}, {0x144, 0}, +}; + +static u32 scg1_offset[16] = { + 0x14, 0x30, 0x40, 0x304, + 0x500, 0x504, 0x508, 0x50c, + 0x510, 0x514, 0x600, 0x604, + 0x608, 0x60c, 0x610, 0x614, +}; + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ +struct imx7ulp_pm_socdata { + u32 ddr_type; + const char *mmdc_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; +}; + +static const u32 imx7ulp_mmdc_io_lpddr3_offset[] __initconst = { + 0x128, 0xf8, 0xd8, 0x108, + 0x104, 0x124, 0x80, 0x84, + 0x88, 0x8c, 0x120, 0x10c, + 0x110, 0x114, 0x118, 0x90, + 0x94, 0x98, 0x9c, 0xe0, + 0xe4, +}; + +static const u32 imx7ulp_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x800, 0x85c, 0x890, + 0x848, 0x850, 0x81c, 0x820, + 0x824, 0x828, 0x82c, 0x830, + 0x834, 0x838, 0x8c0, 0x8b8, + 0x004, 0x00c, 0x010, 0x038, + 0x014, 0x018, 0x02c, 0x030, + 0x040, 0x000, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x83c, 0x020, + 0x800, 0x004, 0x404, 0x01c, +}; + +static const u32 imx7ulp_lpddr3_script[] __initconst = { + 0x00008000, 0xA1390003, 0x0D3900A0, 0x00400000, + 0x40404040, 0x40404040, 0x33333333, 0x33333333, + 0x33333333, 0x33333333, 0xf3333333, 0xf3333333, + 0xf3333333, 0xf3333333, 0x24922492, 0x00000800, + 0x00020052, 0x292C42F3, 0x00100A22, 0x00120556, + 0x00C700DB, 0x00211718, 0x0F9F26D2, 0x009F0E10, + 0x0000003F, 0xC3190000, 0x00008050, 0x00008058, + 0x003F8030, 0x003F8038, 0xFF0A8030, 0xFF0A8038, + 0x04028030, 0x04028038, 0x83018030, 0x83018038, + 0x01038030, 0x01038038, 0x20000000, 0x00001800, + 0xA1310000, 0x00020052, 0x00011006, 0x00000000, +}; + +static const struct imx7ulp_pm_socdata imx7ulp_lpddr3_pm_data __initconst = { + .mmdc_compat = "fsl,imx7ulp-mmdc", + .mmdc_io_num = ARRAY_SIZE(imx7ulp_mmdc_io_lpddr3_offset), + .mmdc_io_offset = imx7ulp_mmdc_io_lpddr3_offset, + .mmdc_num = ARRAY_SIZE(imx7ulp_mmdc_lpddr3_offset), + .mmdc_offset = imx7ulp_mmdc_lpddr3_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7ulp.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7ulp.S must be also changed accordingly, + * otherwise, the suspend to sram function will be broken! + */ +struct imx7ulp_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + void __iomem *sim_base; + void __iomem *scg1_base; + void __iomem *mmdc_base; + void __iomem *mmdc_io_base; + void __iomem *smc1_base; + u32 scg1[16]; + u32 ttbr1; /* Store TTBR1 */ + u32 gpio[4][2]; + u32 iomux_num; /* Number of IOs which need saved/restored. */ + u32 iomux_val[MX7ULP_MAX_IOMUX_NUM]; /* To save value */ + u32 select_input_num; /* Number of select input which need saved/restored. */ + u32 select_input_val[MX7ULP_MAX_SELECT_INPUT_NUM]; /* To save value */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX7ULP_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX7ULP_MAX_MMDC_NUM][2]; +} __aligned(8); + +static struct imx7ulp_cpu_pm_info *pm_info; +static void __iomem *aips1_base; +static void __iomem *aips2_base; +static void __iomem *aips3_base; +static void __iomem *aips4_base; +static void __iomem *aips5_base; + +static const char * const low_power_ocram_match[] __initconst = { + "fsl,lpm-sram", + NULL +}; + +static void imx7ulp_gpio_save(void) +{ + int i; + + for (i = 0; i < 4; i++) { + pm_info->gpio[i][0] = readl_relaxed(gpio_base[i] + GPIO_PDOR); + pm_info->gpio[i][1] = readl_relaxed(gpio_base[i] + GPIO_PDDR); + } +} + +static void imx7ulp_scg1_save(void) +{ + int i; + + for (i = 0; i < 16; i++) + pm_info->scg1[i] = readl_relaxed(scg1_base + scg1_offset[i]); +} + +static void imx7ulp_pcc3_save(void) +{ + int i; + + for (i = 0; i < 16; i++) + pcc3_regs[i][1] = readl_relaxed(pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc3_restore(void) +{ + int i; + + for (i = 0; i < 16; i++) + writel_relaxed(pcc3_regs[i][1], pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc2_save(void) +{ + int i; + + for (i = 0; i < 25; i++) + pcc2_regs[i][1] = readl_relaxed(pcc2_base + pcc2_regs[i][0]); +} + +static void imx7ulp_pcc2_restore(void) +{ + int i; + + for (i = 0; i < 25; i++) + writel_relaxed(pcc2_regs[i][1], pcc2_base + pcc2_regs[i][0]); +} + +static inline void imx7ulp_iomuxc_save(void) +{ + int i; + + pm_info->iomux_num = MX7ULP_MAX_IOMUX_NUM; + pm_info->select_input_num = MX7ULP_MAX_SELECT_INPUT_NUM; + + for (i = 0; i < pm_info->iomux_num; i++) + pm_info->iomux_val[i] = + readl_relaxed(iomuxc1_base + + IOMUX_START + i * 0x4); + for (i = 0; i < pm_info->select_input_num; i++) + pm_info->select_input_val[i] = + readl_relaxed(iomuxc1_base + + SELECT_INPUT_START + i * 0x4); +} + +static void imx7ulp_lpuart_save(void) +{ + lpuart4_regs[0] = readl_relaxed(lpuart4_base + LPUART_BAUD); + lpuart4_regs[1] = readl_relaxed(lpuart4_base + LPUART_FIFO); + lpuart4_regs[2] = readl_relaxed(lpuart4_base + LPUART_WATER); + lpuart4_regs[3] = readl_relaxed(lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_lpuart_restore(void) +{ + writel_relaxed(0x10101, scg1_base + 0x104); + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_OFFSET); + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_INPUT_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_INPUT_OFFSET); + + writel_relaxed(lpuart4_regs[0], lpuart4_base + LPUART_BAUD); + writel_relaxed(lpuart4_regs[1], lpuart4_base + LPUART_FIFO); + writel_relaxed(lpuart4_regs[2], lpuart4_base + LPUART_WATER); + writel_relaxed(lpuart4_regs[3], lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_tpm_save(void) +{ + tpm5_regs[0] = readl_relaxed(tpm5_base + TPM_SC); + tpm5_regs[1] = readl_relaxed(tpm5_base + TPM_MOD); + tpm5_regs[2] = readl_relaxed(tpm5_base + TPM_C0SC); + tpm5_regs[3] = readl_relaxed(tpm5_base + TPM_C0V); +} + +static void imx7ulp_tpm_restore(void) +{ + writel_relaxed(tpm5_regs[0], tpm5_base + TPM_SC); + writel_relaxed(tpm5_regs[1], tpm5_base + TPM_MOD); + writel_relaxed(tpm5_regs[2], tpm5_base + TPM_C0SC); + writel_relaxed(tpm5_regs[3], tpm5_base + TPM_C0V); +} + +static void imx7ulp_set_dgo(u32 val) +{ + writel_relaxed(val, pm_info->sim_base + DGO_GPR3); + writel_relaxed(val, pm_info->sim_base + DGO_GPR4); +} + +int imx7ulp_set_lpm(enum imx7ulp_cpu_pwr_mode mode) +{ + u32 val1 = BM_PMPROT_AHSRUN | BM_PMPROT_AVLP | BM_PMPROT_AVLLS; + u32 val2 = readl_relaxed(smc1_base + PMCTRL); + u32 val3 = readl_relaxed(pmc0_base + PMC_CTRL); + + val2 &= ~(BM_PMCTRL_RUNM | + BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + val3 |= BM_CTRL_LDOOKDIS; + + switch (mode) { + case RUN: + /* system/bus clock enabled */ + val2 |= 0x3 << BP_PMCTRL_PSTOPO; + break; + case WAIT: + /* system clock disabled, bus clock enabled */ + val2 |= 0x2 << BP_PMCTRL_PSTOPO; + break; + case STOP: + /* system/bus clock disabled */ + val2 |= 0x1 << BP_PMCTRL_PSTOPO; + break; + case VLPS: + val2 |= 0x2 << BP_PMCTRL_STOPM; + break; + case VLLS: + val2 |= 0x4 << BP_PMCTRL_STOPM; + break; + default: + return -EINVAL; + } + + writel_relaxed(val1, smc1_base + PMPROT); + writel_relaxed(val2, smc1_base + PMCTRL); + writel_relaxed(val3, pmc0_base + PMC_CTRL); + + return 0; +} + +static int imx7ulp_suspend_finish(unsigned long val) +{ + imx7ulp_suspend_in_ocram_fn(suspend_ocram_base); + + return 0; +} + +static int imx7ulp_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + imx7ulp_set_lpm(VLPS); + writel_relaxed( + readl_relaxed(pmc1_base + PMC_VLPS) | BM_VLPS_RBBEN, + pmc1_base + PMC_VLPS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + writel_relaxed( + readl_relaxed(pmc1_base + PMC_VLPS) & ~BM_VLPS_RBBEN, + pmc1_base + PMC_VLPS); + imx7ulp_set_lpm(RUN); + break; + case PM_SUSPEND_MEM: + imx7ulp_gpio_save(); + imx7ulp_scg1_save(); + imx7ulp_pcc2_save(); + imx7ulp_pcc3_save(); + imx7ulp_tpm_save(); + imx7ulp_lpuart_save(); + imx7ulp_iomuxc_save(); + imx7ulp_set_lpm(VLLS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + imx7ulp_pcc2_restore(); + imx7ulp_pcc3_restore(); + imx7ulp_lpuart_restore(); + imx7ulp_set_dgo(0); + imx7ulp_tpm_restore(); + imx7ulp_set_lpm(RUN); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int imx7ulp_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); +} + +static const struct platform_suspend_ops imx7ulp_pm_ops = { + .enter = imx7ulp_pm_enter, + .valid = imx7ulp_pm_valid, +}; + +static int __init imx7ulp_suspend_init(void) +{ + int ret = 0; + + suspend_set_ops(&imx7ulp_pm_ops); + + return ret; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7ulp_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_match(node, low_power_ocram_match)) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = + IMX_IO_P2V(lpram_addr & ADDR_1M_MASK); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & ADDR_1M_MASK); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7ulp_pm_map_io(void) +{ + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7ulp_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } + + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)iram_tlb_base_addr, 0, MX7ULP_IRAM_TLB_SIZE); +} + +void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata + *socdata) +{ + struct device_node *np; + unsigned long sram_paddr; + const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; + unsigned long i, j; + int ret; + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M); + j = (((u32)aips1_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS1_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M); + j = (((u32)aips2_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS2_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS3 virtual address has a mapping in the + * IRAM page table. + */ + aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M); + j = (((u32)aips3_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS3_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS4 virtual address has a mapping in the + * IRAM page table. + */ + aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M); + j = (((u32)aips4_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS4_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS5 virtual address has a mapping in the + * IRAM page table. + */ + aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M); + j = (((u32)aips5_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS5_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); + smc1_base = of_iomap(np, 0); + WARN_ON(!smc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0"); + pmc0_base = of_iomap(np, 0); + WARN_ON(!pmc0_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc1"); + pmc1_base = of_iomap(np, 0); + WARN_ON(!pmc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-tpm"); + tpm5_base = of_iomap(np, 0); + WARN_ON(!tpm5_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-lpuart"); + lpuart4_base = of_iomap(np, 0); + WARN_ON(!lpuart4_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2"); + pcc2_base = of_iomap(np, 0); + WARN_ON(!pcc2_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3"); + pcc3_base = of_iomap(np, 0); + WARN_ON(!pcc3_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-iomuxc-1"); + iomuxc1_base = of_iomap(np, 0); + WARN_ON(!iomuxc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-scg1"); + scg1_base = of_iomap(np, 0); + WARN_ON(!scg1_base); + + np = NULL; + for (i = 0; i < 4; i++) { + np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio"); + gpio_base[i] = of_iomap(np, 1); + WARN_ON(!gpio_base[i]); + } + + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + sram_paddr = iram_tlb_phys_addr; + + /* Make sure sram_paddr is 8 byte aligned. */ + if ((uintptr_t)(sram_paddr) & (FNCPY_ALIGN - 1)) + sram_paddr += FNCPY_ALIGN - sram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(sram_paddr); + + pm_info = suspend_ocram_base; + pm_info->pbase = sram_paddr; + pm_info->resume_addr = virt_to_phys(imx7ulp_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + pm_info->scg1_base = aips2_base + + (MX7ULP_SCG1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->smc1_base = aips3_base + + (MX7ULP_SMC1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_base = aips4_base + + (MX7ULP_MMDC_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_io_base = aips4_base + + (MX7ULP_MMDC_IO_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->sim_base = aips5_base + + (MX7ULP_SIM_BASE_ADDR & ~ADDR_1M_MASK); + + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_io_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->mmdc_io_base + + mmdc_io_offset_array[i]); + } + + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][1] = imx7ulp_lpddr3_script[i]; + + imx7ulp_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7ulp_suspend, + MX7ULP_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7ulp_suspend_init(); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } +} + +void __init imx7ulp_pm_init(void) +{ + imx7ulp_pm_common_init(&imx7ulp_lpddr3_pm_data); + imx7ulp_set_lpm(RUN); +} + +static irqreturn_t imx7ulp_nmi_isr(int irq, void *param) +{ + writel_relaxed(readl_relaxed(mu_base + MU_SR) | MU_B_SR_NMIC, + mu_base + MU_SR); + + return IRQ_HANDLED; +} + +void imx7ulp_enable_nmi(void) +{ + struct device_node *np; + int irq, ret; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-nmi"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + irq = of_irq_get(np, 0); + ret = request_irq(irq, imx7ulp_nmi_isr, + IRQF_NO_SUSPEND, "imx7ulp-nmi", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return; + } +} diff --git a/arch/arm/mach-imx/pm-rpmsg.c b/arch/arm/mach-imx/pm-rpmsg.c new file mode 100644 index 00000000000000..b4bfa2ad12311d --- /dev/null +++ b/arch/arm/mach-imx/pm-rpmsg.c @@ -0,0 +1,343 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPMSG_TIMEOUT 1000 + +#define PM_RPMSG_TYPE 0 +#define HEATBEAT_RPMSG_TYPE 2 + +enum pm_rpmsg_cmd { + PM_RPMSG_MODE, + PM_RPMSG_HEART_BEAT, + PM_RPMSG_HEART_BEAT_OFF, +}; + +enum pm_rpmsg_power_mode { + PM_RPMSG_HSRUN, + PM_RPMSG_RUN, + PM_RPMSG_VLPR, + PM_RPMSG_WAIT, + PM_RPMSG_VLPS, + PM_RPMSG_VLLS, + PM_RPMSG_REBOOT, + PM_RPMSG_SHUTDOWN, +}; + +struct pm_rpmsg_info { + struct rpmsg_device *rpdev; + struct device *dev; + struct pm_rpmsg_data *msg; + struct pm_qos_request pm_qos_req; + struct notifier_block restart_handler; + struct completion cmd_complete; + bool first_flag; + struct mutex lock; +}; + +static struct pm_rpmsg_info pm_rpmsg; + +static struct delayed_work heart_beat_work; + +static bool heartbeat_off; + +struct pm_rpmsg_data { + struct imx_rpmsg_head header; + u8 data; +} __attribute__ ((packed)); + +static int pm_send_message(struct pm_rpmsg_data *msg, + struct pm_rpmsg_info *info, bool ack) +{ + int err; + + if (!info->rpdev) { + dev_dbg(info->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + pm_qos_add_request(&info->pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct pm_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + if (ack) { + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->msg->data != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->msg->data); + err = -EINVAL; + goto err_out; + } + + err = 0; + } + +err_out: + pm_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int pm_vlls_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = enter ? PM_RPMSG_VLLS : PM_RPMSG_RUN; + + return pm_send_message(&msg, &pm_rpmsg, true); +} + +void pm_shutdown_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_SHUTDOWN; + + pm_send_message(&msg, &pm_rpmsg, true); + +} + +void pm_reboot_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_REBOOT; + + pm_send_message(&msg, &pm_rpmsg, true); + +} + +void pm_heartbeat_off_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT_OFF; + msg.data = enter ? 0 : 1; + + pm_send_message(&msg, &pm_rpmsg, true); +} + +static void pm_heart_beat_work_handler(struct work_struct *work) +{ + struct pm_rpmsg_data msg; + + /* Notify M4 side A7 in RUN mode at boot time */ + if (pm_rpmsg.first_flag) { + pm_vlls_notify_m4(false); + + pm_heartbeat_off_notify_m4(heartbeat_off); + + pm_rpmsg.first_flag = false; + } + + if (!heartbeat_off) { + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = HEATBEAT_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT; + msg.data = 0; + pm_send_message(&msg, &pm_rpmsg, false); + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(30000)); + } +} + +static int pm_restart_handler(struct notifier_block *this, unsigned long mode, + void *cmd) +{ + pm_reboot_notify_m4(); + + return NOTIFY_DONE; +} + +static int pm_rpmsg_probe(struct rpmsg_device *rpdev) +{ + int ret; + + pm_rpmsg.rpdev = rpdev; + + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&pm_rpmsg.cmd_complete); + mutex_init(&pm_rpmsg.lock); + + INIT_DELAYED_WORK(&heart_beat_work, + pm_heart_beat_work_handler); + + pm_rpmsg.first_flag = true; + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(100)); + + pm_rpmsg.restart_handler.notifier_call = pm_restart_handler; + pm_rpmsg.restart_handler.priority = 128; + ret = register_restart_handler(&pm_rpmsg.restart_handler); + if (ret) + dev_err(&rpdev->dev, "cannot register restart handler\n"); + + return 0; +} + +static int pm_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len, + void *priv, u32 src) +{ + struct pm_rpmsg_data *msg = (struct pm_rpmsg_data *)data; + + pm_rpmsg.msg = msg; + + complete(&pm_rpmsg.cmd_complete); + + return 0; +} + +static void pm_rpmsg_remove(struct rpmsg_device *rpdev) +{ + dev_info(&rpdev->dev, "pm rpmsg driver is removed\n"); +} + +static struct rpmsg_device_id pm_rpmsg_id_table[] = { + { .name = "rpmsg-life-cycle-channel" }, + { }, +}; + +static struct rpmsg_driver pm_rpmsg_driver = { + .drv.name = "pm_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = pm_rpmsg_id_table, + .probe = pm_rpmsg_probe, + .callback = pm_rpmsg_cb, + .remove = pm_rpmsg_remove, +}; + +#ifdef CONFIG_PM_SLEEP +static int pm_heartbeat_suspend(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(true); + if (err) + return err; + + cancel_delayed_work_sync(&heart_beat_work); + + return 0; +} + +static int pm_heartbeat_resume(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(false); + if (err) + return err; + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(10000)); + + return 0; +} +#endif + +static int pm_heartbeat_probe(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, &pm_rpmsg); + + return register_rpmsg_driver(&pm_rpmsg_driver); +} + +static const struct of_device_id pm_heartbeat_id[] = { + {"fsl,heartbeat-rpmsg",}, + {}, +}; +MODULE_DEVICE_TABLE(of, pm_heartbeat_id); + +static SIMPLE_DEV_PM_OPS(pm_heartbeat_ops, pm_heartbeat_suspend, + pm_heartbeat_resume); + +static struct platform_driver pm_heartbeat_driver = { + .driver = { + .name = "heartbeat-rpmsg", + .owner = THIS_MODULE, + .of_match_table = pm_heartbeat_id, + .pm = &pm_heartbeat_ops, + }, + .probe = pm_heartbeat_probe, +}; + +static int __init setup_heartbeat(char *str) +{ + heartbeat_off = true; + + return 1; +}; +__setup("heartbeat_off", setup_heartbeat); + +module_platform_driver(pm_heartbeat_driver); + +MODULE_DESCRIPTION("Freescale PM rpmsg driver"); +MODULE_AUTHOR("Anson Huang "); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-imx/smp_wfe.S b/arch/arm/mach-imx/smp_wfe.S new file mode 100644 index 00000000000000..08894bb39c4df9 --- /dev/null +++ b/arch/arm/mach-imx/smp_wfe.S @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + +#ifdef CONFIG_SMP + .align 3 + +ENTRY(imx7_smp_wfe) + push {r4 - r11, lr} + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Set flag of entering WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_DORMANT + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + +go_back_wfe: + wfe + + /* Offset 0x0 stores busfeq done flag */ + ldr r6, [r1] + cmp r6, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Set flag of exiting WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_NORMAL + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +ENDPROC(imx7_smp_wfe) +#endif diff --git a/arch/arm/mach-imx/smp_wfe_imx6.S b/arch/arm/mach-imx/smp_wfe_imx6.S new file mode 100644 index 00000000000000..cdee6169958ef0 --- /dev/null +++ b/arch/arm/mach-imx/smp_wfe_imx6.S @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include "hardware.h" + +#ifdef CONFIG_SMP +.extern imx_scu_base +#endif + +.globl wfe_smp_freq_change_start +.globl wfe_smp_freq_change_end + +#ifdef CONFIG_SMP + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +ENTRY(wfe_smp_freq_change) +wfe_smp_freq_change_start: + push {r4 - r11, lr} + + mov r6, r0 + mov r7, r1 + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + + /* Inform the SCU we are going to enter WFE. */ + push {r0 - r11, lr} + + ldr r0,=imx_scu_base + ldr r0, [r0] + mov r1, #SCU_PM_DORMANT + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + +go_back_wfe: + wfe + + ldr r3, [r7] + cmp r3, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Inform the SCU we have exited WFE. */ + push {r0 - r11, lr} + + ldr r0,=imx_scu_base + ldr r0, [r0] + mov r1, #SCU_PM_NORMAL + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +wfe_smp_freq_change_end: +#endif diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 70b083fe934a8f..c53b6da411b90c 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -18,6 +18,7 @@ #include #include #include "common.h" +#include "hardware.h" #define SRC_SCR 0x000 #define SRC_GPR1 0x020 @@ -29,9 +30,18 @@ #define BP_SRC_SCR_SW_IPU2_RST 12 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 +/* below is for i.MX7D */ +#define SRC_GPR1_V2 0x074 +#define SRC_A7RCR0 0x004 +#define SRC_A7RCR1 0x008 +#define SRC_M4RCR 0x00C + +#define BP_SRC_A7RCR0_A7_CORE_RESET0 0 +#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 static void __iomem *src_base; -static DEFINE_SPINLOCK(scr_lock); +static DEFINE_SPINLOCK(src_lock); +static bool m4_is_enabled; static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_GPU_RST, @@ -41,6 +51,11 @@ static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_IPU2_RST }; +bool imx_src_is_m4_enabled(void) +{ + return m4_is_enabled; +} + static int imx_src_reset_module(struct reset_controller_dev *rcdev, unsigned long sw_reset_idx) { @@ -57,11 +72,11 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev, bit = 1 << sw_reset_bits[sw_reset_idx]; - spin_lock_irqsave(&scr_lock, flags); + spin_lock_irqsave(&src_lock, flags); val = readl_relaxed(src_base + SRC_SCR); val |= bit; writel_relaxed(val, src_base + SRC_SCR); - spin_unlock_irqrestore(&scr_lock, flags); + spin_unlock_irqrestore(&src_lock, flags); timeout = jiffies + msecs_to_jiffies(1000); while (readl(src_base + SRC_SCR) & bit) { @@ -87,32 +102,59 @@ void imx_enable_cpu(int cpu, bool enable) u32 mask, val; cpu = cpu_logical_map(cpu); - mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); - spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val = enable ? val | mask : val & ~mask; - val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); + spin_lock(&src_lock); + if (cpu_is_imx7d()) { + /* enable core */ + if (enable) + imx_gpcv2_set_core1_pdn_pup_by_software(false); + + mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_A7RCR1); + val = enable ? val | mask : val & ~mask; + writel_relaxed(val, src_base + SRC_A7RCR1); + } else { + mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_SCR); + val = enable ? val | mask : val & ~mask; + val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); + writel_relaxed(val, src_base + SRC_SCR); + } + spin_unlock(&src_lock); } void imx_set_cpu_jump(int cpu, void *jump_addr) { + spin_lock(&src_lock); cpu = cpu_logical_map(cpu); - writel_relaxed(virt_to_phys(jump_addr), - src_base + SRC_GPR1 + cpu * 8); + if (cpu_is_imx7d()) + writel_relaxed(virt_to_phys(jump_addr), + src_base + SRC_GPR1_V2 + cpu * 8); + else + writel_relaxed(virt_to_phys(jump_addr), + src_base + SRC_GPR1 + cpu * 8); + spin_unlock(&src_lock); } u32 imx_get_cpu_arg(int cpu) { cpu = cpu_logical_map(cpu); - return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); + if (cpu_is_imx7d()) + return readl_relaxed(src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + return readl_relaxed(src_base + SRC_GPR1 + + cpu * 8 + 4); } void imx_set_cpu_arg(int cpu, u32 arg) { cpu = cpu_logical_map(cpu); - writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); + if (cpu_is_imx7d()) + writel_relaxed(arg, src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + writel_relaxed(arg, src_base + SRC_GPR1 + + cpu * 8 + 4); } void __init imx_src_init(void) @@ -126,6 +168,15 @@ void __init imx_src_init(void) src_base = of_iomap(np, 0); WARN_ON(!src_base); + if (cpu_is_imx7d()) { + val = readl_relaxed(src_base + SRC_M4RCR); + if (((val & BIT(3)) == BIT(3)) && !(val & BIT(0))) + m4_is_enabled = true; + else + m4_is_enabled = false; + return; + } + imx_reset_controller.of_node = np; if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) reset_controller_register(&imx_reset_controller); @@ -134,9 +185,17 @@ void __init imx_src_init(void) * force warm reset sources to generate cold reset * for a more reliable restart */ - spin_lock(&scr_lock); + spin_lock(&src_lock); val = readl_relaxed(src_base + SRC_SCR); + + /* bit 4 is m4c_non_sclr_rst on i.MX6SX */ + if (cpu_is_imx6sx() && ((val & + (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0)) + m4_is_enabled = true; + else + m4_is_enabled = false; + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); + spin_unlock(&src_lock); } diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index 76ee2ceec8d546..b8ad48fc85a95b 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -47,23 +47,32 @@ #define PM_INFO_RESUME_ADDR_OFFSET 0x4 #define PM_INFO_DDR_TYPE_OFFSET 0x8 #define PM_INFO_PM_INFO_SIZE_OFFSET 0xC -#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 -#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 -#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 -#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C -#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 -#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 -#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 -#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C -#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 -#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 -#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 -#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C -#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 -#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 +#define PM_INFO_MX6Q_MMDC0_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC0_V_OFFSET 0x14 +#define PM_INFO_MX6Q_MMDC1_P_OFFSET 0x18 +#define PM_INFO_MX6Q_MMDC1_V_OFFSET 0x1C +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x2C +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x30 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x34 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x3C +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x48 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x4C +#define PM_INFO_MX6Q_TTBR1_V_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 +/* below offsets depends on MX6_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x208 +#define PM_INFO_MMDC_VAL_OFFSET 0x20C #define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MISC 0x18 #define MX6Q_MMDC_MAPSR 0x404 #define MX6Q_MMDC_MPDGCTRL0 0x83c #define MX6Q_GPC_IMR1 0x08 @@ -71,9 +80,49 @@ #define MX6Q_GPC_IMR3 0x10 #define MX6Q_GPC_IMR4 0x14 #define MX6Q_CCM_CCR 0x0 +#define MX6Q_ANATOP_CORE 0x140 .align 3 + /* Check if the cpu is cortex-a7 */ + .macro is_cortex_a7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r5, c0, c0, 0 + ldr r6, =0xfff0 + and r5, r5, r6 + ldr r6, =0xc070 + cmp r5, r6 + + .endm + + .macro disable_l1_cache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 -r10, lr} + ldr r7, = v7_flush_dcache_all + mov lr, pc + mov pc , r7 + pop {r0 -r10, lr} + + .endm + .macro sync_l2_cache /* sync L2 cache to drain L2's buffers to DRAM. */ @@ -92,29 +141,8 @@ .endm - .macro resume_mmdc - - /* restore MMDC IO */ - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] - - ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] - ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET - add r7, r7, r0 -1: - ldr r8, [r7], #0x4 - ldr r9, [r7], #0x4 - str r9, [r11, r8] - subs r6, r6, #0x1 - bne 1b - - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] - - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne 4f + /* r11 must be MMDC base address */ + .macro reset_read_fifo /* reset read FIFO, RST_RD_FIFO */ ldr r7, =MX6Q_MMDC_MPDGCTRL0 @@ -134,23 +162,294 @@ ldr r6, [r11, r7] ands r6, r6, #(1 << 31) bne 3b + + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 6f + + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] 4: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 4b + + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] +5: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 5b + +6: + .endm + + /* r11 must be MMDC base address */ + .macro mmdc_out_and_auto_self_refresh + /* let DDR out of self-refresh */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #(1 << 21) str r7, [r11, #MX6Q_MMDC_MAPSR] -5: +7: ldr r7, [r11, #MX6Q_MMDC_MAPSR] ands r7, r7, #(1 << 25) - bne 5b + bne 7b /* enable DDR auto power saving */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #0x1 str r7, [r11, #MX6Q_MMDC_MAPSR] + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 9f + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] +8: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 8b + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] +9: + .endm + + /* r10 must be iomuxc base address */ + .macro resume_iomuxc_gpr + + add r10, r10, #0x4000 + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 27) + str r4, [r10, #0x8] + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 31) + str r4, [r10, #0x8] + + .endm + + .macro resume_io + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +10: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 10b + + cmp r5, #0x0 + /* Here only MMDC0 is set */ + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + ldreq r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] + ldrne r12, [r0, #PM_INFO_MX6Q_MMDC1_P_OFFSET] + + reset_read_fifo + mmdc_out_and_auto_self_refresh + + .endm + + .macro resume_mmdc_io + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* check whether we need to restore MMDC */ + cmp r5, #0x0 + beq 12f + + /* check whether last suspend is with M/F mix off */ + ldr r9, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r6, [r9, #0x220] + cmp r6, #0x0 + bne 13f +12: + resume_iomuxc_gpr + reset_read_fifo + + b 17f +13: + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 14b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +15: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 15b + + resume_iomuxc_gpr + reset_read_fifo + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +16: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 16b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + +17: + mmdc_out_and_auto_self_refresh + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_cortex_a7 + beq 17f + +#ifdef CONFIG_CACHE_L2X0 + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r6, #0x0 + str r6, [r8, #0x100] + + dsb + isb +#endif +17: .endm + .macro restore_ttbr1 + + is_cortex_a7 + beq 18f + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + ldr r7, =0x1 + str r7, [r8, #0x100] +#endif + +18: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + ENTRY(imx6_suspend) ldr r1, [r0, #PM_INFO_PBASE_OFFSET] ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] @@ -185,10 +484,25 @@ ENTRY(imx6_suspend) str r9, [r11, #MX6Q_SRC_GPR1] str r1, [r11, #MX6Q_SRC_GPR2] + /* + * Check if the cpu is Cortex-A7, for Cortex-A7 + * the cache implementation is not the same as + * Cortex-A9, so the cache maintenance operation + * is different. + */ + is_cortex_a7 + beq a7_dache_flush + /* need to sync L2 cache before DSM. */ sync_l2_cache - - ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + b ttbr_store +a7_dache_flush: + disable_l1_cache +ttbr_store: + store_ttbr1 + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldr r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] /* * put DDR explicitly into self-refresh and * disable automatic power savings. @@ -207,31 +521,59 @@ poll_dvfs_set: ands r7, r7, #(1 << 25) beq poll_dvfs_set + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq skip_self_refresh_ch1 + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set_ch1: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set_ch1 + +skip_self_refresh_ch1: + /* use r11 to store the IO address */ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldr r6, =0x0 - ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET add r8, r8, r0 - /* LPDDR2's last 3 IOs need special setting */ - cmp r3, #IMX_DDR_TYPE_LPDDR2 - subeq r7, r7, #0x3 set_mmdc_io_lpm: - ldr r9, [r8], #0x8 - str r6, [r11, r9] - subs r7, r7, #0x1 + ldr r7, [r8], #0x8 + ldr r9, [r8], #0x4 + str r9, [r11, r7] + subs r6, r6, #0x1 bne set_mmdc_io_lpm - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne set_mmdc_io_lpm_done - ldr r6, =0x1000 - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r6, =0x80000 - ldr r9, [r8] - str r6, [r11, r9] -set_mmdc_io_lpm_done: + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq set_mmdc_lpm_done + + /* IOMUXC GPR DRAM_RESET */ + add r11, r11, #0x4000 + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 28) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 27) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 31) + str r6, [r11, #0x8] +set_mmdc_lpm_done: /* * mask all GPC interrupts before @@ -291,6 +633,27 @@ rbc_loop: subs r6, r6, #0x1 bne rbc_loop + /* + * ERR005852 Analog: Transition from Deep Sleep Mode to + * LDO Bypass Mode may cause the slow response of the + * VDDARM_CAP output. + * + * Software workaround: + * if internal ldo(VDDARM) bypassed, switch to analog bypass + * mode (0x1E), prio to entering DSM, and then, revert to the + * normal bypass mode, when exiting from DSM. + */ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1f + bne ldo_check_done1 +ldo_analog_bypass: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + bic r10, r10, #0x1f + orr r10, r10, #0x1e + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done1: /* Zzz, enter stop mode */ wfi nop @@ -303,8 +666,28 @@ rbc_loop: * wakeup source, system should auto * resume, we need to restore MMDC IO first */ + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1e + bne ldo_check_done2 +ldo_bypass_restore: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + orr r10, r10, #0x1f + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done2: mov r5, #0x0 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq only_resume_io + resume_mmdc_io + b resume_mmdc_done +only_resume_io: + resume_io +resume_mmdc_done: + + restore_ttbr1 /* return to suspend finish */ ret lr @@ -319,6 +702,16 @@ resume: mcr p15, 0, r6, c1, c0, 0 isb + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + ldr r7, [r11, #MX6Q_ANATOP_CORE] + and r7, r7, #0x1f + cmp r7, #0x1e + bne ldo_check_done3 + ldr r7, [r11, #MX6Q_ANATOP_CORE] + orr r7, r7, #0x1f + str r7, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done3: /* get physical resume address from pm_info. */ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] /* clear core0's entry and parameter */ @@ -329,7 +722,16 @@ resume: ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] mov r5, #0x1 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq dsm_only_resume_io + resume_mmdc_io + b dsm_resume_mmdc_done +dsm_only_resume_io: + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + resume_io +dsm_resume_mmdc_done: ret lr ENDPROC(imx6_suspend) @@ -342,8 +744,11 @@ ENDPROC(imx6_suspend) ENTRY(v7_cpu_resume) bl v7_invalidate_l1 + is_cortex_a7 + beq done #ifdef CONFIG_CACHE_L2X0 bl l2c310_early_resume #endif +done: b cpu_resume ENDPROC(v7_cpu_resume) diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S new file mode 100644 index 00000000000000..5f4e31152a69a9 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -0,0 +1,714 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_DDR_TYPE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x18 +#define PM_INFO_MX7_DDRC_P_OFFSET 0x1c +#define PM_INFO_MX7_DDRC_V_OFFSET 0x20 +#define PM_INFO_MX7_DDRC_PHY_P_OFFSET 0x24 +#define PM_INFO_MX7_DDRC_PHY_V_OFFSET 0x28 +#define PM_INFO_MX7_SRC_P_OFFSET 0x2c +#define PM_INFO_MX7_SRC_V_OFFSET 0x30 +#define PM_INFO_MX7_IOMUXC_GPR_P_OFFSET 0x34 +#define PM_INFO_MX7_IOMUXC_GPR_V_OFFSET 0x38 +#define PM_INFO_MX7_CCM_P_OFFSET 0x3c +#define PM_INFO_MX7_CCM_V_OFFSET 0x40 +#define PM_INFO_MX7_GPC_P_OFFSET 0x44 +#define PM_INFO_MX7_GPC_V_OFFSET 0x48 +#define PM_INFO_MX7_SNVS_P_OFFSET 0x4c +#define PM_INFO_MX7_SNVS_V_OFFSET 0x50 +#define PM_INFO_MX7_ANATOP_P_OFFSET 0x54 +#define PM_INFO_MX7_ANATOP_V_OFFSET 0x58 +#define PM_INFO_MX7_LPSR_P_OFFSET 0x5c +#define PM_INFO_MX7_LPSR_V_OFFSET 0x60 +#define PM_INFO_MX7_GIC_DIST_P_OFFSET 0x64 +#define PM_INFO_MX7_GIC_DIST_V_OFFSET 0x68 +#define PM_INFO_MX7_TTBR1_V_OFFSET 0x6c +#define PM_INFO_DDRC_REG_NUM_OFFSET 0x70 +#define PM_INFO_DDRC_REG_OFFSET 0x74 +#define PM_INFO_DDRC_VALUE_OFFSET 0x78 +#define PM_INFO_DDRC_PHY_REG_NUM_OFFSET 0x174 +#define PM_INFO_DDRC_PHY_REG_OFFSET 0x178 +#define PM_INFO_DDRC_PHY_VALUE_OFFSET 0x17c + +#define MX7_SRC_GPR1 0x74 +#define MX7_SRC_GPR2 0x78 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_FM 0xa00 +#define ANADIG_SNVS_MISC_CTRL 0x380 +#define ANADIG_SNVS_MISC_CTRL_SET 0x384 +#define ANADIG_SNVS_MISC_CTRL_CLR 0x388 +#define ANADIG_DIGPROG 0x800 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 + +#define CCM_SNVS_LPCG 0x250 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro ddrc_enter_self_refresh + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +1: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 1b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +2: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 2b +3: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 3b + + /* disable dram clk */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro ddrc_exit_self_refresh + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +4: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 4b + + /* enable auto self-refresh */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro wait_delay +5: + subs r6, r6, #0x1 + bne 5b + + .endm + + .macro ddr_enter_retention + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PCTRL_0] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +6: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 6b + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +7: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 7b +8: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 8b + + /* disable dram clk */ + ldr r7, =(0x1 << 5) + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, [r11, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 10f + + /* TO 1.1 */ + ldr r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldr r7, =0x38000000 + str r7, [r11] + + /* LPSR mode need to use TO1.0 flow as IOMUX lost power */ + ldr r10, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r10] + cmp r7, #0x0 + beq 11f +10: + /* reset ddr_phy */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =0x0 + str r7, [r11, #ANADIG_SNVS_MISC_CTRL] + + /* delay 7 us */ + ldr r6, =6000 + wait_delay + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] +11: + /* turn off ddr power */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =(0x1 << 29) + str r7, [r11, #ANADIG_SNVS_MISC_CTRL_SET] + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] + + .endm + + .macro ddr_exit_retention + + cmp r5, #0x0 + ldreq r1, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldrne r1, [r0, #PM_INFO_MX7_ANATOP_P_OFFSET] + ldreq r2, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldrne r2, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + ldreq r3, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r3, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + ldreq r4, [r0, #PM_INFO_MX7_DDRC_PHY_V_OFFSET] + ldrne r4, [r0, #PM_INFO_MX7_DDRC_PHY_P_OFFSET] + ldreq r10, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7_CCM_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_P_OFFSET] + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_CLR] + + ldr r6, =50 + wait_delay + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] +13: + ldr r6, [r0, #PM_INFO_DDRC_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_REG_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r3, r8] + subs r6, r6, #0x1 + bne 14b + ldr r7, =0x20 + str r7, [r3, #DDRC_PWRCTL] + ldr r7, =0x0 + str r7, [r3, #DDRC_DFIMISC] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 12f + + /* + * TKT262940: + * System hang when press RST for DDR PAD is + * in retention mode, fixed on TO1.1 + */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +12: + ldr r7, =(0x1 << 30) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_SET] + + /* need to delay ~5mS */ + ldr r6, =0x100000 + wait_delay + + ldr r6, [r0, #PM_INFO_DDRC_PHY_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_PHY_REG_OFFSET + add r7, r7, r0 + +15: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r4, r8] + subs r6, r6, #0x1 + bne 15b + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #DDRPHY_LP_CON0] + + /* wait until self-refresh mode entered */ +16: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 16b + ldr r7, =0x0 + str r7, [r3, #DDRC_SWCTL] + ldr r7, =0x1 + str r7, [r3, #DDRC_DFIMISC] + ldr r7, =0x1 + str r7, [r3, #DDRC_SWCTL] +17: + ldr r7, [r3, #DDRC_SWSTAT] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 17b +18: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 18b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #DDRC_PWRCTL] +19: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 19b + +20: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 20b + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r3, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r3, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7_suspend) + push {r4-r12} + + /* make sure SNVS clk is enabled */ + ldr r11, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + add r11, r11, #0x4000 + ldr r7, =0x3 + str r7, [r11, #CCM_SNVS_LPCG] + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq ddr_only_self_refresh + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX7_SRC_GPR1] + str r1, [r11, #MX7_SRC_GPR2] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq ddr_only_self_refresh + + ddr_enter_retention + /* enter LPSR mode if resume addr is valid */ + ldr r11, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r11] + cmp r7, #0x0 + beq ddr_retention_enter_out + + /* disable STOP mode before entering LPSR */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11] + bic r7, #0xf + str r7, [r11] + + /* shut down vddsoc to enter lpsr mode */ + ldr r11, [r0, #PM_INFO_MX7_SNVS_V_OFFSET] + ldr r7, [r11, #0x38] + orr r7, r7, #0x60 + str r7, [r11, #0x38] +wait_shutdown: + wfi + nop + nop + nop + nop + b wait_shutdown + +ddr_only_self_refresh: + ddrc_enter_self_refresh + b wfi +ddr_retention_enter_out: + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r11, r8] + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r4, [r11, #MX7D_GPC_IMR1] + ldr r5, [r11, #MX7D_GPC_IMR2] + ldr r6, [r11, #MX7D_GPC_IMR3] + ldr r7, [r11, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r11, #MX7D_GPC_IMR1] + str r8, [r11, #MX7D_GPC_IMR2] + str r8, [r11, #MX7D_GPC_IMR3] + str r8, [r11, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (240us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~250uS. + */ + ldr r8, [r11, #0x14] + bic r8, r8, #(0x3f << 24) + orr r8, r8, #(0x8 << 24) + str r8, [r11, #0x14] + + /* enable the counter. */ + ldr r8, [r11, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r11, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r11, #MX7D_GPC_IMR1] + str r5, [r11, #MX7D_GPC_IMR2] + str r6, [r11, #MX7D_GPC_IMR3] + str r7, [r11, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r7, =2000 +rbc_loop: + subs r7, r7, #0x1 + bne rbc_loop +wfi: + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + mov r5, #0x0 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq wfi_ddr_self_refresh_out + + ddr_exit_retention + b wfi_ddr_retention_out +wfi_ddr_self_refresh_out: + ddrc_exit_self_refresh +wfi_ddr_retention_out: + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq standby_out + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r11, r8] + + restore_ttbr1 +standby_out: + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX7_SRC_GPR1] + str r7, [r11, #MX7_SRC_GPR2] + + mov r5, #0x1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_P_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq dsm_ddr_self_refresh_out + + ddr_exit_retention + b dsm_ddr_retention_out +dsm_ddr_self_refresh_out: + ddrc_exit_self_refresh +dsm_ddr_retention_out: + + mov pc, lr +ENDPROC(imx7_suspend) + +ENTRY(ca7_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(ca7_cpu_resume) diff --git a/arch/arm/mach-imx/suspend-imx7ulp.S b/arch/arm/mach-imx/suspend-imx7ulp.S new file mode 100644 index 00000000000000..70a0dd8d315fa5 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx7ulp.S @@ -0,0 +1,594 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7ulp_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7ulp.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIM_VBASE_OFFSET 0x18 +#define PM_INFO_PM_INFO_SCG1_VBASE_OFFSET 0x1c +#define PM_INFO_PM_INFO_MMDC_VBASE_OFFSET 0x20 +#define PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET 0x24 +#define PM_INFO_PM_INFO_SMC1_VBASE_OFFSET 0x28 +#define PM_INFO_PM_INFO_SCG1_VAL_OFFSET 0x2c +#define PM_INFO_MX7ULP_TTBR1_V_OFFSET 0x6c +#define PM_INFO_MX7ULP_GPIO_REG_OFFSET 0x70 +#define PM_INFO_IOMUX_NUM_OFFSET 0x90 +#define PM_INFO_IOMUX_VAL_OFFSET 0x94 +#define PM_INFO_SELECT_INPUT_NUM_OFFSET 0x264 +#define PM_INFO_SELECT_INPUT_VAL_OFFSET 0x268 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a0 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a4 +/* below offsets depends on MX7ULP_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x4c4 +#define PM_INFO_MMDC_VAL_OFFSET 0x4c8 + +#define DGO_CTRL0 0x50 +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define MX7ULP_MMDC_MISC 0x18 +#define MX7ULP_MMDC_MAPSR 0x404 +#define MX7ULP_MMDC_MPDGCTRL0 0x83c + +#define SCG_RCCR 0x14 +#define SCG_DDRCCR 0x30 +#define SCG_NICCCR 0x40 +#define SCG_FIRCDIV 0x304 +#define SCG_APLLCSR 0x500 +#define SCG_APLLDIV 0x504 +#define SCG_APLLCFG 0x508 +#define SCG_APLLPFD 0x50c +#define SCG_APLLNUM 0x510 +#define SCG_APLLDENOM 0x514 +#define SCG_SPLLCSR 0x600 +#define SCG_SPLLDIV 0x604 +#define SCG_SPLLCFG 0x608 +#define SCG_SPLLPFD 0x60c +#define SCG_SPLLNUM 0x610 +#define SCG_SPLLDENOM 0x614 +#define SCG_SOSCDIV 0x104 + +#define PMC1_CTRL 0x24 + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 +#define GPIO_PORT_NUM 0x4 +#define GPIO_PORT_OFFSET 0x40 + +#define PMCTRL 0x10 + +#define IOMUX_OFFSET 0x0 +#define SELECT_INPUT_OFFSET 0x200 + + .align 3 + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro restore_mmdc_settings + + ldr r10, =MX7ULP_MMDC_IO_BASE_ADDR + ldr r11, =MX7ULP_MMDC_BASE_ADDR + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +2: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 2b + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +3: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 3b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +4: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 4b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + .endm + +ENTRY(imx7ulp_suspend) + push {r4-r12} + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7ulp_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r3 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #DGO_GPR3] + str r1, [r11, #DGO_GPR4] + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] +wait_dgo: + ldr r7, [r11, #DGO_CTRL0] + and r7, r7, #0x18000 + cmp r7, #0x18000 + bne wait_dgo + + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0x18000 + bic r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_VBASE_OFFSET] + + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq poll_dvfs_set + + /* switch NIC clock to FIRC */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_NICCCR] + bic r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* switch RUN clock to FIRC */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x3 << 24) + str r7, [r10, #SCG_RCCR] + + /* turn off SPLL and SPFD */ + ldr r7, [r10, #SCG_SPLLPFD] + mov r8, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_SPLLPFD] + + ldr r7, [r10, #SCG_SPLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_SPLLCSR] + + /* turn off APLL and APFD */ + ldr r7, [r10, #SCG_APLLPFD] + mov r9, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_APLLPFD] + + ldr r7, [r10, #SCG_APLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_APLLCSR] + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + mov r7, #0x0 + str r7, [r10, #DGO_GPR3] + str r7, [r10, #DGO_GPR4] + + /* enable SPLL and SPFD */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_SPLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_SPLLCSR] +wait_spll: + ldr r7, [r10, #SCG_SPLLCSR] + ands r7, r7, #(1 << 24) + beq wait_spll + + str r8, [r10, #SCG_SPLLPFD] + /* switch RUN clock to SPLL */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x6 << 24) + str r7, [r10, #SCG_RCCR] + + /* enable APLL and APFD */ + ldr r7, [r10, #SCG_APLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_APLLCSR] +wait_apll: + ldr r7, [r10, #SCG_APLLCSR] + ands r7, r7, #(1 << 24) + beq wait_apll + + str r9, [r10, #SCG_APLLPFD] + + /* switch NIC clock to DDR */ + ldr r7, [r10, #SCG_NICCCR] + orr r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +poll_dvfs_clear: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne poll_dvfs_clear + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + restore_ttbr1 + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + ldr r6, =MX7ULP_SIM_BASE_ADDR + ldr r0, [r6, #DGO_GPR4] + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + ldr r11, =MX7ULP_SCG1_BASE_ADDR + /* enable spll and pfd0 */ + ldr r5, =PM_INFO_PM_INFO_SCG1_VAL_OFFSET + add r6, r5, #48 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCFG] + + add r6, r5, #56 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLNUM] + + add r6, r5, #60 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDENOM] + + add r6, r5, #40 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCSR] +5: + ldr r7, [r11, #SCG_SPLLCSR] + ands r7, r7, #0x1000000 + beq 5b + + add r6, r5, #44 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDIV] + + add r6, r5, #52 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLPFD] + + add r6, r5, #0 + ldr r7, [r0, r6] + str r7, [r11, #SCG_RCCR] + + /* enable apll and pfd0 */ + add r6, r5, #24 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCFG] + + add r6, r5, #32 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLNUM] + + add r6, r5, #36 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDENOM] + + add r6, r5, #16 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCSR] +6: + ldr r7, [r11, #SCG_APLLCSR] + ands r7, r7, #0x1000000 + beq 6b + + add r6, r5, #20 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDIV] + + add r6, r5, #28 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLPFD] + + /* set ddr ccr */ + add r6, r5, #4 + ldr r7, [r0, r6] + str r7, [r11, #SCG_DDRCCR] + + /* set nic sel */ + add r6, r5, #8 + ldr r7, [r0, r6] + str r7, [r11, #SCG_NICCCR] + + /* set firc div2 to get 48MHz */ + add r6, r5, #12 + ldr r7, [r0, r6] + str r7, [r11, #SCG_FIRCDIV] + + /* enable mmdc clock in pcc3 */ + ldr r11, =MX7ULP_PCC3_BASE_ADDR + ldr r7, [r11, #0xac] + orr r7, r7, #(1 << 30) + str r7, [r11, #0xac] + + /* enable GPIO clock in pcc2 */ + ldr r11, =MX7ULP_PCC2_BASE_ADDR + ldr r7, [r11, #0x3c] + orr r7, r7, #(1 << 30) + str r7, [r11, #0x3c] + + /* restore gpio settings */ + ldr r10, =MX7ULP_GPIOC_BASE_ADDR + ldr r7, =PM_INFO_MX7ULP_GPIO_REG_OFFSET + add r7, r7, r0 + ldr r6, =GPIO_PORT_NUM +12: + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDOR] + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDDR] + add r10, r10, #GPIO_PORT_OFFSET + subs r6, r6, #0x1 + bne 12b + + /* restore iomuxc settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #IOMUX_OFFSET + ldr r6, [r0, #PM_INFO_IOMUX_NUM_OFFSET] + ldr r7, =PM_INFO_IOMUX_VAL_OFFSET + add r7, r7, r0 +13: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 13b + + /* restore select input settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #SELECT_INPUT_OFFSET + ldr r6, [r0, #PM_INFO_SELECT_INPUT_NUM_OFFSET] + ldr r7, =PM_INFO_SELECT_INPUT_VAL_OFFSET + add r7, r7, r0 +14: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 14b + + /* isoack */ + ldr r6, =MX7ULP_PMC1_BASE_ADDR + ldr r7, [r6, #PMC1_CTRL] + orr r7, r7, #(1 << 14) + str r7, [r6, #PMC1_CTRL] + + restore_mmdc_settings + + mov pc, lr +ENDPROC(imx7ulp_suspend) + +ENTRY(imx7ulp_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(imx7ulp_cpu_resume) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c1799dd1d0d99a..aa7d512aaffc62 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -692,7 +692,7 @@ config ARM_VIRT_EXT details. config SWP_EMULATE - bool "Emulate SWP/SWPB instructions" if !SMP + bool "Emulate SWP/SWPB instructions" depends on CPU_V7 default y if SMP select HAVE_PROC_CPU if PROC_FS diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a134d8a13d001e..d2dd211f66ee36 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -162,6 +162,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ swith back to cache level 0 diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 00e9e79b6cb898..1b8f163e04eee4 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2410,6 +2410,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, set_dma_ops(dev, dma_ops); } +EXPORT_SYMBOL_GPL(arch_setup_dma_ops); void arch_teardown_dma_ops(struct device *dev) { diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c index 054b491ff7649c..872b1ff7ff1175 100644 --- a/arch/arm/mm/proc-syms.c +++ b/arch/arm/mm/proc-syms.c @@ -14,6 +14,7 @@ #include #include #include +#include "dma.h" #ifndef MULTI_CPU EXPORT_SYMBOL(cpu_dcache_clean_area); @@ -30,6 +31,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all); EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); EXPORT_SYMBOL(__cpuc_flush_dcache_area); +EXPORT_SYMBOL(__glue(_CACHE,_dma_map_area)); +EXPORT_SYMBOL(__glue(_CACHE,_dma_unmap_area)); +EXPORT_SYMBOL(__glue(_CACHE,_dma_flush_range)); #else EXPORT_SYMBOL(cpu_cache); #endif diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dab2cb0c1f1c93..92fd2f74b66637 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -194,8 +194,7 @@ CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m +# CONFIG_WLAN_VENDOR_TI is not set CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_MISC=y @@ -344,15 +343,10 @@ CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_SDHCI_IPROC is not set CONFIG_MMC_SPI=y CONFIG_MMC_SDHI=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_SUNXI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y diff --git a/arch/x86/include/asm/idle.h b/arch/x86/include/asm/idle.h index c5d1785373ed38..02bab09707f28c 100644 --- a/arch/x86/include/asm/idle.h +++ b/arch/x86/include/asm/idle.h @@ -1,13 +1,6 @@ #ifndef _ASM_X86_IDLE_H #define _ASM_X86_IDLE_H -#define IDLE_START 1 -#define IDLE_END 2 - -struct notifier_block; -void idle_notifier_register(struct notifier_block *n); -void idle_notifier_unregister(struct notifier_block *n); - #ifdef CONFIG_X86_64 void enter_idle(void); void exit_idle(void); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index a55b32007785dc..54b2711f2dbc28 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -67,19 +67,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_tss); #ifdef CONFIG_X86_64 static DEFINE_PER_CPU(unsigned char, is_idle); -static ATOMIC_NOTIFIER_HEAD(idle_notifier); - -void idle_notifier_register(struct notifier_block *n) -{ - atomic_notifier_chain_register(&idle_notifier, n); -} -EXPORT_SYMBOL_GPL(idle_notifier_register); - -void idle_notifier_unregister(struct notifier_block *n) -{ - atomic_notifier_chain_unregister(&idle_notifier, n); -} -EXPORT_SYMBOL_GPL(idle_notifier_unregister); #endif /* @@ -255,14 +242,14 @@ static inline void play_dead(void) void enter_idle(void) { this_cpu_write(is_idle, 1); - atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); + idle_notifier_call_chain(IDLE_START); } static void __exit_idle(void) { if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) return; - atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); + idle_notifier_call_chain(IDLE_END); } /* Called from interrupts to signify idle end */ diff --git a/block/blk-map.c b/block/blk-map.c index 27fd8d92892d47..b18a58fc316aec 100644 --- a/block/blk-map.c +++ b/block/blk-map.c @@ -196,6 +196,12 @@ int blk_rq_unmap_user(struct bio *bio) } EXPORT_SYMBOL(blk_rq_unmap_user); +#ifdef CONFIG_AHCI_IMX +extern void *sg_io_buffer_hack; +#else +#define sg_io_buffer_hack NULL +#endif + /** * blk_rq_map_kern - map kernel data to a request, for REQ_TYPE_BLOCK_PC usage * @q: request queue where request should be inserted @@ -223,7 +229,14 @@ int blk_rq_map_kern(struct request_queue *q, struct request *rq, void *kbuf, if (!len || !kbuf) return -EINVAL; - do_copy = !blk_rq_aligned(q, addr, len) || object_is_on_stack(kbuf); +#ifdef CONFIG_AHCI_IMX + if (kbuf == sg_io_buffer_hack) + do_copy = 0; + else +#endif + do_copy = !blk_rq_aligned(q, addr, len) + || object_is_on_stack(kbuf); + if (do_copy) bio = bio_copy_kern(q, kbuf, len, gfp_mask, reading); else diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c index c6fee7437be445..b00647ee3d1c26 100644 --- a/block/scsi_ioctl.c +++ b/block/scsi_ioctl.c @@ -251,6 +251,12 @@ static int blk_fill_sghdr_rq(struct request_queue *q, struct request *rq, return 0; } +#ifdef CONFIG_AHCI_IMX +extern void *sg_io_buffer_hack; +#else +#define sg_io_buffer_hack NULL +#endif + static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, struct bio *bio) { @@ -279,7 +285,12 @@ static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, ret = -EFAULT; } - r = blk_rq_unmap_user(bio); + if (sg_io_buffer_hack && !hdr->iovec_count) + r = copy_to_user(hdr->dxferp, sg_io_buffer_hack, + hdr->dxfer_len); + else + r = blk_rq_unmap_user(bio); + if (!ret) ret = r; @@ -303,6 +314,9 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, if (hdr->dxfer_len > (queue_max_hw_sectors(q) << 9)) return -EIO; + if (sg_io_buffer_hack && hdr->dxfer_len > 0x10000) + return -EIO; + if (hdr->dxfer_len) switch (hdr->dxfer_direction) { default: @@ -349,9 +363,14 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, ret = blk_rq_map_user_iov(q, rq, NULL, &i, GFP_KERNEL); kfree(iov); - } else if (hdr->dxfer_len) - ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, hdr->dxfer_len, - GFP_KERNEL); + } else if (hdr->dxfer_len) { + if (sg_io_buffer_hack) + ret = blk_rq_map_kern(q, rq, sg_io_buffer_hack, + hdr->dxfer_len, GFP_KERNEL); + else + ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, + hdr->dxfer_len, GFP_KERNEL); + } if (ret) goto out_free_cdb; diff --git a/crypto/gcm.c b/crypto/gcm.c index dd33fbd2d868b5..8d335ec6dfc573 100644 --- a/crypto/gcm.c +++ b/crypto/gcm.c @@ -119,7 +119,7 @@ static int crypto_gcm_setkey(struct crypto_aead *aead, const u8 *key, be128 hash; u8 iv[16]; - struct crypto_gcm_setkey_result result; + struct crypto_gcm_setkey_result result ____cacheline_aligned; struct scatterlist sg[1]; struct skcipher_request req; diff --git a/crypto/testmgr.c b/crypto/testmgr.c index 62dffa0028acdb..bd03502094b5c3 100644 --- a/crypto/testmgr.c +++ b/crypto/testmgr.c @@ -3733,7 +3733,7 @@ static const struct alg_test_desc alg_test_descs[] = { } } }, { - .alg = "rfc4543(gcm(aes))", + .alg = "rfc4543(gcm(aes))-disabled", .test = alg_test_aead, .suite = { .aead = { diff --git a/drivers/Kconfig b/drivers/Kconfig index e1e2066cecdb60..f1ef8ac03657cf 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -102,6 +102,8 @@ source "drivers/mmc/Kconfig" source "drivers/memstick/Kconfig" +source "drivers/mxc/Kconfig" + source "drivers/leds/Kconfig" source "drivers/accessibility/Kconfig" @@ -202,4 +204,6 @@ source "drivers/hwtracing/intel_th/Kconfig" source "drivers/fpga/Kconfig" +source "drivers/battery/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 733bf0b2613ffd..821a9ff502f389 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -124,6 +124,7 @@ obj-y += lguest/ obj-$(CONFIG_CPU_FREQ) += cpufreq/ obj-$(CONFIG_CPU_IDLE) += cpuidle/ obj-y += mmc/ +obj-y += mxc/ obj-$(CONFIG_MEMSTICK) += memstick/ obj-$(CONFIG_NEW_LEDS) += leds/ obj-$(CONFIG_INFINIBAND) += infiniband/ @@ -174,3 +175,4 @@ obj-$(CONFIG_STM) += hwtracing/stm/ obj-$(CONFIG_ANDROID) += android/ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ +obj-$(CONFIG_BATTERY_SAMSUNG) += battery/ diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 3f3a7db208ae51..3fccbed95ab2ae 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -55,6 +55,7 @@ enum { enum ahci_imx_type { AHCI_IMX53, AHCI_IMX6Q, + AHCI_IMX6QP, }; struct imx_ahci_priv { @@ -69,6 +70,8 @@ struct imx_ahci_priv { u32 phy_params; }; +void *sg_io_buffer_hack; + static int ahci_imx_hotplug; module_param_named(hotplug, ahci_imx_hotplug, int, 0644); MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); @@ -231,7 +234,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) if (ret < 0) goto disable_regulator; - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { /* * set PHY Paremeters, two steps to configure the GPR13, * one write for rest of parameters, mask of first write @@ -255,12 +258,26 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) IMX6Q_GPR13_SATA_MPLL_CLK_EN); usleep_range(100, 200); + } + + if (imxpriv->type == AHCI_IMX6Q) { ret = imx_sata_phy_reset(hpriv); - if (ret) { - dev_err(dev, "failed to reset phy: %d\n", ret); - goto disable_clk; - } + } else if (imxpriv->type == AHCI_IMX6QP) { + /* 6qp adds the sata reset mechanism, use it for 6qp sata */ + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + BIT(10), 0); + + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + BIT(11), 0); + udelay(50); + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + BIT(11), BIT(11)); + } + + if (ret) { + dev_err(dev, "failed to reset phy: %d\n", ret); + goto disable_clk; } usleep_range(1000, 2000); @@ -282,7 +299,11 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) if (imxpriv->no_device) return; - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6QP) + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + BIT(10), BIT(10)); + + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, IMX6Q_GPR13_SATA_MPLL_CLK_EN, !IMX6Q_GPR13_SATA_MPLL_CLK_EN); @@ -336,7 +357,7 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, if (imxpriv->type == AHCI_IMX53) ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); - else if (imxpriv->type == AHCI_IMX6Q) + else if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) ret = ahci_ops.softreset(link, class, deadline); return ret; @@ -359,6 +380,7 @@ static const struct ata_port_info ahci_imx_port_info = { static const struct of_device_id imx_ahci_of_match[] = { { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, + { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP }, {}, }; MODULE_DEVICE_TABLE(of, imx_ahci_of_match); @@ -566,7 +588,7 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->ahb_clk); } - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { u32 reg_value; imxpriv->gpr = syscon_regmap_lookup_by_compatible( @@ -622,6 +644,24 @@ static int imx_ahci_probe(struct platform_device *pdev) reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + /* + * Due to IP bug on the Synopsis 3.00 SATA version, + * which is present on mx6q, and not on mx53, + * we should use sg_tablesize = 1 for reliable operation + */ + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { + dma_addr_t dma; + + ahci_platform_sht.sg_tablesize = 1; + + sg_io_buffer_hack = dma_alloc_coherent(NULL, 0x10000, + &dma, GFP_KERNEL); + if (!sg_io_buffer_hack) { + ret = -ENOMEM; + goto disable_sata; + } + } + ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, &ahci_platform_sht); if (ret) diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index 0651010bba217c..4a7032cbb3c1f7 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -154,6 +154,7 @@ config FW_LOADER_USER_HELPER config FW_LOADER_USER_HELPER_FALLBACK bool "Fallback user-helper invocation for firmware loading" depends on FW_LOADER + default y select FW_LOADER_USER_HELPER help This option enables / disables the invocation of user-helper diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c index e167a1e1bccb06..f18a996ffe8126 100644 --- a/drivers/base/dma-contiguous.c +++ b/drivers/base/dma-contiguous.c @@ -248,6 +248,11 @@ static int __init rmem_cma_setup(struct reserved_mem *rmem) struct cma *cma; int err; + if (size_cmdline != -1) { + pr_info("Reserved memory: using cma cmdline parameter\n"); + return -EINVAL; + } + if (!of_get_flat_dt_prop(node, "reusable", NULL) || of_get_flat_dt_prop(node, "no-map", NULL)) return -EINVAL; diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 8c7d0f33bd5376..2d59c2ec06e97b 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -772,6 +772,8 @@ static int pm_genpd_suspend_noirq(struct device *dev) if (dev->power.wakeup_path && genpd_dev_active_wakeup(genpd, dev)) return 0; + pm_generic_suspend_noirq(dev); + if (genpd->dev_ops.stop && genpd->dev_ops.start) { ret = pm_runtime_force_suspend(dev); if (ret) @@ -820,6 +822,8 @@ static int pm_genpd_resume_noirq(struct device *dev) if (genpd->dev_ops.stop && genpd->dev_ops.start) ret = pm_runtime_force_resume(dev); + pm_generic_resume_noirq(dev); + return ret; } @@ -1645,7 +1649,7 @@ EXPORT_SYMBOL_GPL(of_genpd_del_provider); * Returns a valid pointer to struct generic_pm_domain on success or ERR_PTR() * on failure. */ -static struct generic_pm_domain *genpd_get_from_provider( +struct generic_pm_domain *genpd_get_from_provider( struct of_phandle_args *genpdspec) { struct generic_pm_domain *genpd = ERR_PTR(-ENOENT); @@ -1668,6 +1672,7 @@ static struct generic_pm_domain *genpd_get_from_provider( return genpd; } +EXPORT_SYMBOL_GPL(genpd_get_from_provider); /** * of_genpd_add_device() - Add a device to an I/O PM domain diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c index 36ce3511c733f6..6d3dc1429ae575 100644 --- a/drivers/base/regmap/regmap-debugfs.c +++ b/drivers/base/regmap/regmap-debugfs.c @@ -269,7 +269,7 @@ static ssize_t regmap_map_read_file(struct file *file, char __user *user_buf, count, ppos); } -#undef REGMAP_ALLOW_WRITE_DEBUGFS +#define REGMAP_ALLOW_WRITE_DEBUGFS #ifdef REGMAP_ALLOW_WRITE_DEBUGFS /* * This can be dangerous especially when we have clients such as diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index ec262476d04387..6f9af6d3e0a781 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -33,6 +33,7 @@ struct regmap_irq_chip_data { int irq; int wake_count; + int last_irq; void *status_reg_buf; unsigned int *status_buf; @@ -281,6 +282,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } } + data->last_irq = 0; /* * Read in the statuses, using a single bulk read if possible * in order to reduce the I/O overheads. @@ -345,11 +347,11 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * doing a write per register. */ for (i = 0; i < data->chip->num_regs; i++) { - data->status_buf[i] &= ~data->mask_buf[i]; - if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { reg = chip->ack_base + (i * map->reg_stride * data->irq_reg_stride); + handled = true; + data->last_irq = -1; ret = regmap_write(map, reg, data->status_buf[i]); if (ret != 0) dev_err(map->dev, "Failed to ack 0x%x: %d\n", @@ -358,8 +360,11 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } for (i = 0; i < chip->num_irqs; i++) { - if (data->status_buf[chip->irqs[i].reg_offset / - map->reg_stride] & chip->irqs[i].mask) { + unsigned j = chip->irqs[i].reg_offset / map->reg_stride; + + if (data->status_buf[j] & chip->irqs[i].mask & + ~data->mask_buf[j]) { + data->last_irq = data->irq_base + i; handle_nested_irq(irq_find_mapping(data->domain, i)); handled = true; } @@ -374,8 +379,26 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) if (handled) return IRQ_HANDLED; - else - return IRQ_NONE; +#if 0 + dev_err(map->dev, "Spurious int\n"); + for (i = 0; i < data->chip->num_regs; i++) { + unsigned offset = i * map->reg_stride * data->irq_reg_stride; + unsigned reg = chip->status_base + offset; + unsigned buf; + + if (!data->status_buf[i]) + continue; + dev_err(map->dev, "Spurious: reg(%x) = %x, mask=%x\n", reg, data->status_buf[i], data->mask_buf[i]); + buf = 0; + ret = regmap_read(map, chip->mask_base + offset, &buf); + + if (ret) + dev_err(map->dev, "Failed to read IRQ mask: %d\n", ret); + else if (buf != (unsigned)(unsigned short)data->mask_buf[i]) + dev_err(map->dev, "mask(%x): %x expected %x\n", chip->mask_base + offset, buf, data->mask_buf[i]); + } +#endif + return IRQ_NONE; } static int regmap_irq_map(struct irq_domain *h, unsigned int virq, @@ -646,6 +669,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, err_domain: /* Should really dispose of the domain but... */ err_alloc: + *data = NULL; kfree(d->type_buf); kfree(d->type_buf_def); kfree(d->wake_buf); @@ -835,3 +859,9 @@ struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data) return NULL; } EXPORT_SYMBOL_GPL(regmap_irq_get_domain); + +int regmap_irq_chip_get_last_irq(struct regmap_irq_chip_data *data) +{ + return data->last_irq; +} +EXPORT_SYMBOL_GPL(regmap_irq_chip_get_last_irq); diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c index 5189fd6182f6c6..400a297d2490ad 100644 --- a/drivers/base/regmap/regmap-mmio.c +++ b/drivers/base/regmap/regmap-mmio.c @@ -305,19 +305,15 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev, goto err_free; } - if (clk_id == NULL) - return ctx; - ctx->clk = clk_get(dev, clk_id); - if (IS_ERR(ctx->clk)) { - ret = PTR_ERR(ctx->clk); - goto err_free; - } - - ret = clk_prepare(ctx->clk); - if (ret < 0) { - clk_put(ctx->clk); - goto err_free; + if (!IS_ERR(ctx->clk)) { + ret = clk_prepare(ctx->clk); + if (ret < 0) { + clk_put(ctx->clk); + goto err_free; + } + } else { + ctx->clk = NULL; } return ctx; diff --git a/drivers/battery/Kconfig b/drivers/battery/Kconfig new file mode 100644 index 00000000000000..552826a26bf336 --- /dev/null +++ b/drivers/battery/Kconfig @@ -0,0 +1,99 @@ +menuconfig BATTERY_SAMSUNG + bool "samsung battery driver" + help + Say Y to include support for samsung battery driver + This battery driver integrated all battery-related functions + To see battery-related functions, + refer to sec_charging_common.h + +if BATTERY_SAMSUNG + +config BATTERY_SAMSUNG_DATA_FILE + depends on BATTERY_SAMSUNG + string "samsung battery data file" + default "" + help + Path to the battery data file. + +config BATTERY_SAMSUNG_DATA + bool + default BATTERY_SAMSUNG_DATA_FILE != "" + +config CHARGING_VZWCONCEPT + bool "VZW concept about the charging" + depends on BATTERY_SAMSUNG + default n + help + Say Y to include support for the VZW concepts. + +config BATTERY_SWELLING + bool "prevent battery swelling" + depends on BATTERY_SAMSUNG + help + Say Y to include support for prevent battery swelling + +# Fuel Gauge + +config FUELGAUGE_MAX77823 + tristate "MAX77823 fuel gauge driver" + default n + depends on BATTERY_SAMSUNG + help + Say Y to include support + for MAXIM MAX77823 or MAX77818 fuel gauge driver. + This fuel-gauge can be used in voltage-tracking mode + or coulomb-counting mode. + +config FUELGAUGE_MAX77823_VOLTAGE_TRACKING + bool "use MAX77823 fuel gauge only as voltage tracking" + default n + depends on FUELGAUGE_MAX77823 + help + Say Y to use MAX17050 fuel gauge + only as voltage tracking. + This mode is for target that consumes low current + like smart-phone. + +config FUELGAUGE_MAX77823_COULOMB_COUNTING + bool "use MAX77823 fuel gauge as coulomb counting (including voltage tracking)" + default n + depends on FUELGAUGE_MAX77823 + help + Say Y to use MAX77823 fuel gauge + as coulomb counting (including voltage tracking). + This mode is for target that consumes high current + like tablet. + +# Charger + +config CHARGER_MAX77823 + tristate "MAX77823 battery charger support" + depends on BATTERY_SAMSUNG + help + Say Y here to enable support for the MAX77823 charger + +config SAMSUNG_BATTERY_ENG_TEST + bool "enable ENG mode for battery test" + depends on BATTERY_SAMSUNG + default n + help + Say Y to include support for battery test + enable this feature only ENG mode + this featuren must disabled user binary + stability test etc.. + +config SAMSUNG_BATTERY_FACTORY + bool "enable for factory test" + depends on BATTERY_SAMSUNG + default n + help + Say Y to include support for factory test + enable this feature only factory mode + this featuren must disabled user binary + stability test etc.. + +config SEC_BOARD_MXC + tristate "enable for imx6" + default y if ARCH_MXC + +endif #BATTERY_SAMSUNG diff --git a/drivers/battery/Makefile b/drivers/battery/Makefile new file mode 100644 index 00000000000000..dc51ca0fddad7f --- /dev/null +++ b/drivers/battery/Makefile @@ -0,0 +1,6 @@ + +obj-$(CONFIG_BATTERY_SAMSUNG) += sec_battery.o +obj-$(CONFIG_SEC_BOARD_MXC) += sec_board-mxc.o +obj-$(CONFIG_FUELGAUGE_MAX77823) += max77823_fuelgauge.o + +obj-$(CONFIG_CHARGER_MAX77823) += max77823_charger.o diff --git a/drivers/battery/max77823_charger.c b/drivers/battery/max77823_charger.c new file mode 100644 index 00000000000000..709a4b0f4c5e98 --- /dev/null +++ b/drivers/battery/max77823_charger.c @@ -0,0 +1,1851 @@ +/* + * max77823_charger.c + * Samsung MAX77823 Charger Driver + * + * Copyright (C) 2012 Samsung Electronics + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#ifdef CONFIG_EXTCON_MAX77828 +#include +#endif + +#define ENABLE 1 +#define DISABLE 0 + +#define SIOP_INPUT_LIMIT_CURRENT 1200 +#define SIOP_CHARGING_LIMIT_CURRENT 1000 +#define SIOP_WIRELESS_INPUT_LIMIT_CURRENT 660 +#define SIOP_WIRELESS_CHARGING_LIMIT_CURRENT 780 +#define SLOW_CHARGING_CURRENT_STANDARD 400 +#define INPUT_CURRENT_1000mA 0x1E + +static enum power_supply_property max77823_charger_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_CHARGE_TYPE, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_CURRENT_MAX, + POWER_SUPPLY_PROP_CURRENT_AVG, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, +}; + +static const char* const psy_names[] = { +[PS_BATT] = "battery", +[PS_PS] = "ps", +[PS_WIRELESS] = "wireless", +}; + +static int psy_get_prop(struct max77823_charger_data *charger, enum ps_id id, enum power_supply_property property, union power_supply_propval *value) +{ + struct power_supply *psy = charger->psy_ref[id]; + int ret = -EINVAL; + + value->intval = 0; + if (!psy) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + do { + psy = power_supply_get_by_name(psy_names[id]); + if (psy) { + charger->psy_ref[id] = psy; + break; + } + if (time_after(jiffies, timeout)) { + pr_err("%s: charger Failed %s\n", __func__, psy_names[id]); + return -ENODEV; + } + msleep(1); + } while (1); + } + if (psy->desc->get_property) { + ret = psy->desc->get_property(psy, property, value); + if (ret < 0) + pr_err("%s: charger Fail to get %s(%d=>%d)\n", __func__, psy_names[id], property, ret); + } + return ret; +} + +static int psy_set_prop(struct max77823_charger_data *charger, enum ps_id id, enum power_supply_property property, union power_supply_propval *value) +{ + struct power_supply *psy = charger->psy_ref[id]; + int ret = -EINVAL; + + if (!psy) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + do { + psy = power_supply_get_by_name(psy_names[id]); + if (psy) { + charger->psy_ref[id] = psy; + break; + } + if (time_after(jiffies, timeout)) { + pr_err("%s: charger Failed %s\n", __func__, psy_names[id]); + return -ENODEV; + } + msleep(1); + } while (1); + } + if (psy->desc->set_property) { + ret = psy->desc->set_property(psy, property, value); + if (ret < 0) + pr_err("%s: charger Fail to set %s(%d=>%d)\n", __func__, psy_names[id], property, ret); + } + return ret; +} + +static struct sec_charging_current *get_charging_info(struct max77823_charger_data *charger, int index) +{ + struct sec_battery_platform_data *pdata = charger->pdata; + if (index >= pdata->charging_current_entries) { + pr_err("%s: invalid index %d\n", __func__, index); + index = POWER_SUPPLY_TYPE_UNKNOWN; /* 0 */ + } + return &pdata->charging_current[index]; +} + +static void max77823_charger_initialize(struct max77823_charger_data *charger); +static int max77823_get_vbus_state(struct max77823_charger_data *charger); +static int max77823_get_charger_state(struct max77823_charger_data *charger); +static bool max77823_charger_unlock(struct max77823_charger_data *charger) +{ + struct i2c_client *i2c = charger->i2c; + int ret; + u8 chgprot; + int retry_cnt = 0; + bool need_init = false; + + do { + ret = max77823_read_reg(i2c, MAX77823_CHG_CNFG_06); + if (ret < 0) + break; + chgprot = ((ret & 0x0C) >> 2); + if (chgprot != 0x03) { + pr_err("%s: unlock err, chgprot(0x%x), retry(%d)\n", + __func__, chgprot, retry_cnt); + max77823_write_reg(i2c, MAX77823_CHG_CNFG_06, + (0x03 << 2)); + need_init = true; + msleep(20); + } else { + pr_debug("%s: unlock success, chgprot(0x%x)\n", + __func__, chgprot); + break; + } + } while ((chgprot != 0x03) && (++retry_cnt < 10)); + + return need_init; +} + +static void check_charger_unlock_state(struct max77823_charger_data *charger) +{ + bool need_reg_init; + pr_debug("%s\n", __func__); + + need_reg_init = max77823_charger_unlock(charger); + if (need_reg_init) { + pr_err("%s: charger locked state, reg init\n", __func__); + max77823_charger_initialize(charger); + } +} + +static void max77823_test_read(struct max77823_charger_data *charger) +{ + u32 addr = 0; + + for (addr = 0xB0; addr <= 0xC3; addr++) { + pr_debug("MAX77823 addr : 0x%02x data : 0x%02x\n", addr, + max77823_read_reg(charger->i2c, addr)); + } +} + +static int max77823_get_vbus_state(struct max77823_charger_data *charger) +{ + int ret; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_00); + if (ret < 0) + return ret; + + if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) + ret = ((ret & MAX77823_WCIN_DTLS) >> + MAX77823_WCIN_DTLS_SHIFT); + else + ret = ((ret & MAX77823_CHGIN_DTLS) >> + MAX77823_CHGIN_DTLS_SHIFT); + + switch (ret) { + case 0x00: + pr_debug("%s: VBUS is invalid. CHGIN < CHGIN_UVLO\n", + __func__); + break; + case 0x01: + pr_info("%s: VBUS is invalid. CHGIN < MBAT+CHGIN2SYS" \ + "and CHGIN > CHGIN_UVLO\n", __func__); + break; + case 0x02: + pr_info("%s: VBUS is invalid. CHGIN > CHGIN_OVLO", + __func__); + break; + case 0x03: + pr_debug("%s: VBUS is valid. CHGIN < CHGIN_OVLO", __func__); + break; + default: + break; + } + + return ret; +} + +static int max77823_get_charger_state(struct max77823_charger_data *charger) +{ + int status = POWER_SUPPLY_STATUS_UNKNOWN; + int ret; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_01); + + pr_info("%s : charger status (0x%02x)\n", __func__, ret); + if (ret < 0) + return status; + + ret &= 0x0f; + + switch (ret) + { + case 0x00: + case 0x01: + case 0x02: + status = POWER_SUPPLY_STATUS_CHARGING; + break; + case 0x03: + case 0x04: + status = POWER_SUPPLY_STATUS_FULL; + break; + case 0x05: + case 0x06: + case 0x07: + status = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + case 0x08: + case 0xA: + case 0xB: + status = POWER_SUPPLY_STATUS_DISCHARGING; + break; + default: + status = POWER_SUPPLY_STATUS_UNKNOWN; + break; + } + + return (int)status; +} + +static int max77823_get_charger_present(struct max77823_charger_data *charger) +{ + int ret; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_INT_OK); + if (ret < 0) + return 1; + pr_debug("%s:(0x%02x)\n", __func__, ret); + return (ret >> MAX77823_DETBAT_SHIFT) & 1; +} + +static int max77823_get_bat_health(struct max77823_charger_data *charger) +{ + int state; + int ret; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_01); + if (ret < 0) + return POWER_SUPPLY_HEALTH_UNKNOWN; + ret = ((ret & MAX77823_BAT_DTLS) >> MAX77823_BAT_DTLS_SHIFT); + + pr_debug("%s: 0x%x\n", __func__, ret); + switch (ret) { + case 0x00: + pr_info("%s: No battery and the charger is suspended\n", + __func__); + state = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + case 0x01: + pr_info("%s: battery is okay " + "but its voltage is low(~VPQLB)\n", __func__); + state = POWER_SUPPLY_HEALTH_GOOD; + break; + case 0x02: + pr_info("%s: battery dead\n", __func__); + state = POWER_SUPPLY_HEALTH_DEAD; + break; + case 0x03: + state = POWER_SUPPLY_HEALTH_GOOD; + break; + case 0x04: + pr_info("%s: battery is okay " \ + "but its voltage is low\n", __func__); + state = POWER_SUPPLY_HEALTH_GOOD; + break; + case 0x05: + pr_info("%s: battery ovp\n", __func__); + state = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + break; + default: + pr_info("%s: battery unknown : 0x%d\n", __func__, ret); + state = POWER_SUPPLY_HEALTH_UNKNOWN; + break; + } + return state; +} + +static int max77823_get_charging_health(struct max77823_charger_data *charger) +{ + int state = POWER_SUPPLY_HEALTH_GOOD; + int vbus_state; + int retry_cnt; + int ret; + u8 chg_dtls; + + /* VBUS OVP state return battery OVP state */ + vbus_state = max77823_get_vbus_state(charger); + /* read CHG_DTLS and detecting battery terminal error */ + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_01); + if (ret < 0) + return POWER_SUPPLY_HEALTH_UNKNOWN; + chg_dtls = ((ret & MAX77823_CHG_DTLS) >> + MAX77823_CHG_DTLS_SHIFT); + + /* print the log at the abnormal case */ + if (charger->is_charging && (chg_dtls & 0x08)) { + pr_info("%s: CHG_DTLS_00(0x%x), CHG_DTLS_01(0x%x), CHG_CNFG_00(0x%x)\n", + __func__, + max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_00), + chg_dtls, + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_00)); + pr_info("%s: CHG_CNFG_01(0x%x), CHG_CNFG_02(0x%x), CHG_CNFG_04(0x%x)\n", + __func__, + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_01), + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_02), + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_04)); + pr_info("%s: CHG_CNFG_09(0x%x), CHG_CNFG_12(0x%x)\n", + __func__, + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_09), + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_12)); + } + + pr_debug("%s: vbus_state : 0x%x, chg_dtls : 0x%x chg_cnfg_00=0x%x\n", + __func__, vbus_state, chg_dtls, + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_00)); + /* OVP is higher priority */ + if (vbus_state == 0x02) { /* CHGIN_OVLO */ + pr_info("%s: vbus ovp\n", __func__); + state = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + retry_cnt = 0; + do { + msleep(50); + vbus_state = max77823_get_vbus_state(charger); + } while((retry_cnt++ < 2) && (vbus_state == 0x02)); + if (vbus_state == 0x02) { + state = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + pr_info("%s: wpc and over-voltage\n", __func__); + } else + state = POWER_SUPPLY_HEALTH_GOOD; + } + } else if (((vbus_state == 0x0) || (vbus_state == 0x01)) &&(chg_dtls & 0x08) && + (charger->cable_type != POWER_SUPPLY_TYPE_WIRELESS)) { + pr_debug("%s: vbus is under, vbus_state=%d, chg_dtls=%d\n", + __func__, vbus_state, chg_dtls); + state = POWER_SUPPLY_HEALTH_UNDERVOLTAGE; + } + + max77823_test_read(charger); + + /* If we are supplying power, mark as undervoltage */ + if ((state == POWER_SUPPLY_HEALTH_GOOD) && charger->otg_vbus_enabled) + state = POWER_SUPPLY_HEALTH_UNDERVOLTAGE; + return (int)state; +} + +static u8 max77823_get_float_voltage_data(int float_voltage) +{ + u8 data; + + if (float_voltage >= 4350) + data = (float_voltage - 3650) / 25 + 1; + else if (float_voltage == 4340) + data = 0x1c; + else + data = (float_voltage - 3650) / 25; + + return data; +} + +static int max77823_get_input_current(struct max77823_charger_data *charger) +{ + int ret; + int get_current = 0; + + if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_10); + /* AND operation for removing the formal 2bit */ + if (ret >= 0) + ret = ret & 0x3F; + + if (ret <= 0x3) + get_current = 60; + else + get_current = ret * 20; + } else { + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_09); + /* AND operation for removing the formal 1bit */ + if (ret >= 0) + ret = ret & 0x7F; + + if (ret <= 0x3) + get_current = 100; + else if (ret >= 0x78) + get_current = 4000; + else { + int quotient, remainder; + quotient = ret / 3; + remainder = ret % 3; + if (remainder == 0) + get_current = quotient * 100; + else if (remainder == 1) + get_current = quotient * 100 + 33; + else + get_current = quotient * 100 + 67; + } + } + + return get_current; +} + +static void max77823_set_buck(struct max77823_charger_data *charger, + int enable) +{ + int ret; + + ret = max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + enable ? MAX77823_MODE_BUCK : 0, + MAX77823_MODE_BUCK); + + pr_info("%s: CHG_CNFG_00(0x%02x)\n", __func__, ret); +} + +static void max77823_chg_cable_work(struct work_struct *work) +{ + struct max77823_charger_data *charger = + container_of(work, struct max77823_charger_data,chg_cable_work.work); + int quotient, remainder; + int ret; + + pr_debug("[%s]VALUE(%d)DATA(0x%x)\n", + __func__, charger->charging_current_max, + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_09)); + + quotient = charger->charging_current_max / 100; + remainder = charger->charging_current_max % 100; + + ret = quotient * 3; + if (remainder >= 67) + ret += 2; + else if (remainder >= 33) + ret += 1; + + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_09, ret); + + pr_info("[%s]VALUE(%d)DATA(0x%x)\n", + __func__, charger->charging_current_max, + ret); +} + +static void max77823_set_input_current(struct max77823_charger_data *charger, + int input_current) +{ + u8 reg_data = 0; + int quotient, remainder; + + /* disable only buck because power onoff test issue */ + if (input_current <= 0) { + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_09, 0x0F); + max77823_set_buck(charger, DISABLE); + return; + } + else + max77823_set_buck(charger, ENABLE); + + if (charger->cable_type == POWER_SUPPLY_TYPE_MAINS) { + reg_data |= INPUT_CURRENT_1000mA; + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_09, reg_data); + + pr_info("[1][TA][0x%x]\n", reg_data); + schedule_delayed_work(&charger->chg_cable_work, msecs_to_jiffies(2000)); + } else if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + quotient = input_current / 20; + reg_data |= quotient; + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_10, reg_data); + } else { + /* HV TA, etc */ + cancel_delayed_work_sync(&charger->chg_cable_work); + + quotient = input_current / 100; + remainder = input_current % 100; + + if (remainder >= 67) + reg_data |= (quotient * 3) + 2; + else if (remainder >= 33) + reg_data |= (quotient * 3) + 1; + else if (remainder < 33) + reg_data |= quotient * 3; + + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_09, reg_data); + + pr_info("[3][HV TA, etc][0x%x]\n", reg_data); + } +} + +static void max77823_set_charge_current(struct max77823_charger_data *charger, + int fast_charging_current) +{ + int curr_step = 50; + int ret; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_02); + if (ret < 0) + return; + ret &= ~MAX77823_CHG_CC; + + if (!fast_charging_current) { + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_02, ret); + } else { + ret |= (fast_charging_current / curr_step); + max77823_write_reg(charger->i2c,MAX77823_CHG_CNFG_02, ret); + } + pr_info("%s: 0x%02x, charging current(%d)\n", + __func__, ret, fast_charging_current); + +} + +static void max77823_set_topoff_current(struct max77823_charger_data *charger, + int termination_current, + int termination_time) +{ + u8 reg_data; + + if (termination_current >= 350) + reg_data = 0x07; + else if (termination_current >= 300) + reg_data = 0x06; + else if (termination_current >= 250) + reg_data = 0x05; + else if (termination_current >= 200) + reg_data = 0x04; + else if (termination_current >= 175) + reg_data = 0x03; + else if (termination_current >= 150) + reg_data = 0x02; + else if (termination_current >= 125) + reg_data = 0x01; + else + reg_data = 0x00; + + /* the unit of timeout is second*/ + termination_time = termination_time / 60; + reg_data |= ((termination_time / 10) << 3); + pr_info("%s: reg_data(0x%02x), topoff(%d)\n", + __func__, reg_data, termination_current); + + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_03, reg_data); + +} + +static void max77823_set_charger_state(struct max77823_charger_data *charger, + int enable) +{ + int ret; + + ret = max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + enable ? MAX77823_MODE_CHGR : 0, + MAX77823_MODE_CHGR); + + pr_debug("%s : CHG_CNFG_00(0x%02x)\n", __func__, ret); +} + +static void max77823_charger_function_control( + struct max77823_charger_data *charger) +{ + const int usb_charging_current = get_charging_info(charger, POWER_SUPPLY_TYPE_USB)->fast_charging_current; + int set_charging_current, set_charging_current_max; + + pr_info("####%s#### %d\n", __func__, charger->cable_type); + + if (charger->cable_type == POWER_SUPPLY_TYPE_BATTERY) { + int ret; + + charger->is_charging = false; + charger->aicl_on = false; + set_charging_current = 0; + set_charging_current_max = + get_charging_info(charger, POWER_SUPPLY_TYPE_BATTERY)->input_current_limit; + + set_charging_current_max = + get_charging_info(charger, POWER_SUPPLY_TYPE_USB)->input_current_limit; + charger->charging_current = set_charging_current; + charger->charging_current_max = set_charging_current_max; + + ret = max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + charger->pdata->boost ? CHG_CNFG_00_BOOST_MASK : 0, + CHG_CNFG_00_CHG_MASK | CHG_CNFG_00_BUCK_MASK | + CHG_CNFG_00_BOOST_MASK); + pr_debug("%s: CHG_CNFG_00(0x%02x)%d\n", __func__, ret, charger->pdata->boost); + } else { + int ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_12); + + if ((ret >= 0) && (ret & 0x20)) + charger->is_charging = true; + charger->charging_current_max = + get_charging_info(charger, charger->cable_type)->input_current_limit; + charger->charging_current = + get_charging_info(charger, charger->cable_type)->fast_charging_current; + /* decrease the charging current according to siop level */ + set_charging_current = + charger->charging_current * charger->siop_level / 100; + if (set_charging_current > 0 && + set_charging_current < usb_charging_current) + set_charging_current = usb_charging_current; + + set_charging_current_max = + charger->charging_current_max; + + if (charger->siop_level < 100) { + if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + if (set_charging_current_max > SIOP_WIRELESS_INPUT_LIMIT_CURRENT) { + set_charging_current_max = SIOP_WIRELESS_INPUT_LIMIT_CURRENT; + if (set_charging_current > SIOP_WIRELESS_CHARGING_LIMIT_CURRENT) + set_charging_current = SIOP_WIRELESS_CHARGING_LIMIT_CURRENT; + } + } else { + if (set_charging_current_max > SIOP_INPUT_LIMIT_CURRENT) { + set_charging_current_max = SIOP_INPUT_LIMIT_CURRENT; + if (set_charging_current > SIOP_CHARGING_LIMIT_CURRENT) + set_charging_current = SIOP_CHARGING_LIMIT_CURRENT; + } + } + } + } + + max77823_set_charger_state(charger, charger->is_charging); + + /* if battery full, only disable charging */ + if ((charger->status == POWER_SUPPLY_STATUS_CHARGING) || + (charger->status == POWER_SUPPLY_STATUS_FULL) || + (charger->status == POWER_SUPPLY_STATUS_DISCHARGING)) { + /* current setting */ + max77823_set_charge_current(charger, + set_charging_current); + /* if battery is removed, disable input current and reenable input current + * to enable buck always */ + max77823_set_input_current(charger, + set_charging_current_max); + max77823_set_topoff_current(charger, + get_charging_info(charger, charger->cable_type)->full_check_current_1st, + get_charging_info(charger, charger->cable_type)->full_check_current_2nd); + } + + pr_info("charging = %d, fc = %d, il = %d, t1 = %d, t2 = %d, cable = %d\n", + charger->is_charging, + charger->charging_current, + charger->charging_current_max, + get_charging_info(charger, charger->cable_type)->full_check_current_1st, + get_charging_info(charger, charger->cable_type)->full_check_current_2nd, + charger->cable_type); + + max77823_test_read(charger); + +} + +static void max77823_charger_initialize(struct max77823_charger_data *charger) +{ + int ret; + pr_info("%s\n", __func__); + + /* unmasked: CHGIN_I, WCIN_I, BATP_I, BYP_I */ + max77823_write_reg(charger->i2c, MAX77823_CHG_INT_MASK, 0x9a); + + /* unlock charger setting protect */ + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_06, 0x03 << 2); + + /* + * fast charge timer disable + * restart threshold disable + * pre-qual charge enable(default) + */ + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_01, + (0x08 << 0) | (0x03 << 4)); + + /* + * charge current 466mA(default) + * otg current limit 900mA + */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_02, 1 << 6, 3 << 6); + + /* + * top off current 100mA + * top off timer 70min + */ + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_03, 0x38); + + /* + * cv voltage 4.2V or 4.35V + * MINVSYS 3.6V(default) + */ + ret = max77823_get_float_voltage_data(charger->pdata->chg_float_voltage); + ret = max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_04, + (ret << CHG_CNFG_04_CHG_CV_PRM_SHIFT), + CHG_CNFG_04_CHG_CV_PRM_MASK); + pr_info("%s: battery cv voltage 0x%x\n", __func__, ret); + max77823_test_read(charger); +} + +static int max77823_chg_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max77823_charger_data *charger = psy->drv_data; + int ret; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = POWER_SUPPLY_TYPE_BATTERY; + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_INT_OK); + if (ret >= 0) { + if (ret & MAX77823_WCIN_OK) { + val->intval = POWER_SUPPLY_TYPE_WIRELESS; + charger->wc_w_state = 1; + } else if (ret & MAX77823_CHGIN_OK) { + val->intval = POWER_SUPPLY_TYPE_MAINS; + } + } + break; + case POWER_SUPPLY_PROP_STATUS: + val->intval = max77823_get_charger_state(charger); + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = max77823_get_charger_present(charger); + break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + if (!charger->is_charging) + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + else if (charger->aicl_on) + { + val->intval = POWER_SUPPLY_CHARGE_TYPE_SLOW; + pr_info("%s: slow-charging mode\n", __func__); + } + else + val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; + break; + case POWER_SUPPLY_PROP_HEALTH: + val->intval = max77823_get_charging_health(charger); + break; + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + val->intval = 0; + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_12); + if (ret >= 0) + val->intval = (ret >> 5) & 1; + break; + case POWER_SUPPLY_PROP_CURRENT_MAX: + case POWER_SUPPLY_PROP_CURRENT_AVG: + val->intval = max77823_get_input_current(charger); + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = max77823_get_input_current(charger); + pr_debug("%s : set-current(%dmA), current now(%dmA)\n", + __func__, charger->charging_current, val->intval); + break; + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: + break; + default: + return -EINVAL; + } + return 0; +} + +static int max77823_chg_property_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + case POWER_SUPPLY_PROP_CURRENT_MAX: + case POWER_SUPPLY_PROP_CURRENT_NOW: + return 1; + default: + break; + } + return 0; +} + +static int max77823_otg_regulator_nb(struct notifier_block *nb, unsigned long event, void *data) +{ + struct max77823_charger_data *charger = container_of(nb, struct max77823_charger_data, otg_regulator_nb); + + if (event & (REGULATOR_EVENT_DISABLE | REGULATOR_EVENT_AFT_DO_ENABLE | REGULATOR_EVENT_PRE_DO_ENABLE)) { + charger->otg_vbus_enabled = (event & REGULATOR_EVENT_DISABLE) ? false : true; + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_12, + (event & REGULATOR_EVENT_DISABLE) ? 0x20 : 0, 0x20); + if (event & REGULATOR_EVENT_DISABLE) + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + CHG_CNFG_00_CHG_MASK, CHG_CNFG_00_CHG_MASK); + } + return 0; +} + +static void max77823_set_online(struct max77823_charger_data *charger, int type) +{ + union power_supply_propval value; + int ret; + + if (type == POWER_SUPPLY_TYPE_POWER_SHARING) { + int enable_mask = 0; + + psy_get_prop(charger, PS_PS, POWER_SUPPLY_PROP_STATUS, &value); + + if (value.intval | charger->pdata->boost) { + enable_mask |= CHG_CNFG_00_BOOST_MASK; + } else { + ret = max77823_read_reg(charger->i2c, + MAX77823_CHG_CNFG_00); + if (ret < 0) + return; + if (ret & CHG_CNFG_00_OTG_MASK) + enable_mask |= CHG_CNFG_00_BOOST_MASK; + } + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + enable_mask, CHG_CNFG_00_BOOST_MASK); + return; + } + charger->cable_type = type; + max77823_charger_function_control(charger); +} + +static int max77823_chg_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct max77823_charger_data *charger = psy->drv_data; + int set_charging_current_max; + const int usb_charging_current = get_charging_info(charger, POWER_SUPPLY_TYPE_USB)->fast_charging_current; + + switch (psp) { + /* val->intval : type */ + case POWER_SUPPLY_PROP_STATUS: + charger->status = val->intval; + break; + case POWER_SUPPLY_PROP_ONLINE: + max77823_set_online(charger, val->intval); + break; + + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_12, + val->intval ? 0x20 : 0, 0x20); + break; + + /* val->intval : input charging current */ + case POWER_SUPPLY_PROP_CURRENT_MAX: + charger->charging_current_max = val->intval; + break; + /* val->intval : charging current */ + case POWER_SUPPLY_PROP_CURRENT_AVG: + charger->charging_current = val->intval; + break; + /* val->intval : charging current */ + case POWER_SUPPLY_PROP_CURRENT_NOW: + charger->charging_current = val->intval; + max77823_set_charge_current(charger, val->intval); + break; + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: + charger->siop_level = val->intval; + if (charger->is_charging) { + /* decrease the charging current according to siop level */ + int current_now = + charger->charging_current * val->intval / 100; + + /* do forced set charging current */ + if (current_now > 0 && + current_now < usb_charging_current) + current_now = usb_charging_current; + + if (charger->cable_type == POWER_SUPPLY_TYPE_MAINS || \ + charger->cable_type == POWER_SUPPLY_TYPE_HV_MAINS) { + if (charger->siop_level < 100 ) { + set_charging_current_max = SIOP_INPUT_LIMIT_CURRENT; + } else { + set_charging_current_max = + charger->charging_current_max; + } + + if (charger->siop_level < 100 && + current_now > SIOP_CHARGING_LIMIT_CURRENT) + current_now = SIOP_CHARGING_LIMIT_CURRENT; + max77823_set_input_current(charger, + set_charging_current_max); + } else if (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + if (charger->siop_level < 100 ) { + set_charging_current_max = SIOP_WIRELESS_INPUT_LIMIT_CURRENT; + } else { + set_charging_current_max = + charger->charging_current_max; + } + + if (charger->siop_level < 100 && + current_now > SIOP_WIRELESS_CHARGING_LIMIT_CURRENT) + current_now = SIOP_WIRELESS_CHARGING_LIMIT_CURRENT; + max77823_set_input_current(charger, + set_charging_current_max); + } + + max77823_set_charge_current(charger, current_now); + + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int max77823_debugfs_show(struct seq_file *s, void *data) +{ + struct max77823_charger_data *charger = s->private; + int ret; + u8 reg; + + seq_printf(s, "MAX77823 CHARGER IC :\n"); + seq_printf(s, "===================\n"); + for (reg = 0xB0; reg <= 0xC3; reg++) { + ret = max77823_read_reg(charger->i2c, reg); + if (ret >= 0) + seq_printf(s, "0x%02x:\t0x%02x\n", reg, ret); + else + seq_printf(s, "0x%02x:\t----\n", reg); + } + + seq_printf(s, "\n"); + return 0; +} + +static int max77823_debugfs_open(struct inode *inode, struct file *file) +{ + return single_open(file, max77823_debugfs_show, inode->i_private); +} + +static const struct file_operations max77823_debugfs_fops = { + .open = max77823_debugfs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void max77823_chg_isr_work(struct work_struct *work) +{ + struct max77823_charger_data *charger = + container_of(work, struct max77823_charger_data, isr_work.work); + + union power_supply_propval val; + + if (charger->pdata->full_check_type == + SEC_BATTERY_FULLCHARGED_CHGINT) { + + val.intval = max77823_get_charger_state(charger); + + switch (val.intval) { + case POWER_SUPPLY_STATUS_DISCHARGING: + pr_err("%s: Interrupted but Discharging\n", __func__); + break; + + case POWER_SUPPLY_STATUS_NOT_CHARGING: + pr_err("%s: Interrupted but NOT Charging\n", __func__); + break; + + case POWER_SUPPLY_STATUS_FULL: + pr_info("%s: Interrupted by Full\n", __func__); + psy_set_prop(charger, PS_BATT, POWER_SUPPLY_PROP_STATUS, &val); + break; + + case POWER_SUPPLY_STATUS_CHARGING: + pr_err("%s: Interrupted but Charging\n", __func__); + break; + + case POWER_SUPPLY_STATUS_UNKNOWN: + default: + pr_err("%s: Invalid Charger Status\n", __func__); + break; + } + } + + if (charger->pdata->ovp_uvlo_check_type == + SEC_BATTERY_OVP_UVLO_CHGINT) { + val.intval = max77823_get_bat_health(charger); + switch (val.intval) { + case POWER_SUPPLY_HEALTH_OVERHEAT: + case POWER_SUPPLY_HEALTH_COLD: + pr_err("%s: Interrupted but Hot/Cold\n", __func__); + break; + + case POWER_SUPPLY_HEALTH_DEAD: + pr_err("%s: Interrupted but Dead\n", __func__); + break; + + case POWER_SUPPLY_HEALTH_OVERVOLTAGE: + case POWER_SUPPLY_HEALTH_UNDERVOLTAGE: + pr_info("%s: Interrupted by OVP/UVLO, %d\n", __func__, val.intval); + psy_set_prop(charger, PS_BATT, POWER_SUPPLY_PROP_HEALTH, &val); + break; + + case POWER_SUPPLY_HEALTH_UNSPEC_FAILURE: + pr_err("%s: Interrupted but Unspec\n", __func__); + break; + + case POWER_SUPPLY_HEALTH_GOOD: + pr_err("%s: Interrupted but Good\n", __func__); + break; + + case POWER_SUPPLY_HEALTH_UNKNOWN: + default: + pr_err("%s: Invalid Charger Health\n", __func__); + break; + } + } +} + +static irqreturn_t max77823_chg_irq_thread(int irq, void *irq_data) +{ + struct max77823_charger_data *charger = irq_data; + + pr_info("%s: Charger interrupt occured\n", __func__); + + if ((charger->pdata->full_check_type == + SEC_BATTERY_FULLCHARGED_CHGINT) || + (charger->pdata->ovp_uvlo_check_type == + SEC_BATTERY_OVP_UVLO_CHGINT)) + schedule_delayed_work(&charger->isr_work, 0); + + return IRQ_HANDLED; +} + +static void wpc_detect_work(struct work_struct *work) +{ + struct max77823_charger_data *charger = container_of(work, + struct max77823_charger_data, + wpc_work.work); + int wc_w_state = 0; + int retry_cnt; + union power_supply_propval value; + int ret; + + pr_info("%s\n", __func__); + + /* unmask WCIN Interrupt*/ + max77823_update_reg(charger->i2c, + MAX77823_CHG_INT_MASK, 0, 1 << 5); + + /* check and unlock */ + check_charger_unlock_state(charger); + + retry_cnt = 0; + do { + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_INT_OK); + if (ret >= 0) { + wc_w_state = (ret & MAX77823_WCIN_OK) + >> MAX77823_WCIN_OK_SHIFT; + } + msleep(50); + } while((retry_cnt++ < 2) && (wc_w_state == 0)); + + if ((charger->wc_w_state == 0) && (wc_w_state == 1)) { + value.intval = 1; + psy_set_prop(charger, PS_WIRELESS, POWER_SUPPLY_PROP_ONLINE, + &value); + value.intval = POWER_SUPPLY_TYPE_WIRELESS; + pr_info("%s: wpc activated, set V_INT as PN\n", + __func__); + } else if ((charger->wc_w_state == 1) && (wc_w_state == 0)) { + if (!charger->is_charging) + max77823_set_charger_state(charger, true); + + retry_cnt = 0; + do { + ret = max77823_read_reg(charger->i2c, + MAX77823_CHG_DETAILS_01); + if (ret >= 0) + ret = ((ret & MAX77823_CHG_DTLS) + >> MAX77823_CHG_DTLS_SHIFT); + else + ret = 8; + msleep(50); + } while((retry_cnt++ < 2) && (ret == 0x8)); + pr_info("%s: 0x%x, charging: %d\n", __func__, + ret, charger->is_charging); + if (!charger->is_charging) + max77823_set_charger_state(charger, false); + if ((ret != 0x08) + && (charger->cable_type == POWER_SUPPLY_TYPE_WIRELESS)) { + pr_info("%s: wpc uvlo, but charging\n", __func__); + queue_delayed_work(charger->wqueue, &charger->wpc_work, + msecs_to_jiffies(500)); + return; + } else { + value.intval = 0; + psy_set_prop(charger, PS_WIRELESS, + POWER_SUPPLY_PROP_ONLINE, &value); + pr_info("%s: wpc deactivated, set V_INT as PD\n", + __func__); + } + } + pr_info("%s: w(%d to %d)\n", __func__, + charger->wc_w_state, wc_w_state); + + charger->wc_w_state = wc_w_state; + + wake_unlock(&charger->wpc_wake_lock); +} + +static irqreturn_t wpc_charger_irq(int irq, void *data) +{ + struct max77823_charger_data *charger = data; + unsigned long delay; + + max77823_update_reg(charger->i2c, + MAX77823_CHG_INT_MASK, 1 << 5, 1 << 5); + + wake_lock(&charger->wpc_wake_lock); +#ifdef CONFIG_SAMSUNG_BATTERY_FACTORY + delay = msecs_to_jiffies(0); +#else + if (charger->wc_w_state) + delay = msecs_to_jiffies(500); + else + delay = msecs_to_jiffies(0); +#endif + queue_delayed_work(charger->wqueue, &charger->wpc_work, + delay); + return IRQ_HANDLED; +} + +static irqreturn_t max77823_bypass_irq(int irq, void *data) +{ + struct max77823_charger_data *charger = data; +// struct otg_notify *n = get_otg_notify(); + int ret; + u8 byp_dtls; + u8 vbus_state; + + pr_info("%s: irq(%d)\n", __func__, irq); + + /* check and unlock */ + check_charger_unlock_state(charger); + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_02); + if (ret < 0) + ret = 0; + byp_dtls = ((ret & MAX77823_BYP_DTLS) >> + MAX77823_BYP_DTLS_SHIFT); + pr_info("%s: BYP_DTLS(0x%02x)\n", __func__, byp_dtls); + vbus_state = max77823_get_vbus_state(charger); + + if (byp_dtls & 0x1) { + pr_info("%s: bypass overcurrent limit\n", __func__); +// send_otg_notify(n, NOTIFY_EVENT_OVERCURRENT, 0); + + /* disable the register values just related to OTG and + keep the values about the charging */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + charger->pdata->boost ? CHG_CNFG_00_BOOST_MASK : 0, + CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK); + } + return IRQ_HANDLED; +} + +static void max77823_chgin_isr_work(struct work_struct *work) +{ + struct max77823_charger_data *charger = container_of(work, + struct max77823_charger_data, chgin_work); + u8 chgin_dtls = 0; + u8 chg_dtls = 0; + u8 chg_cnfg_00 = 0; + int ret; + u8 prev_chgin_dtls = 0xff; + int bat_health; + union power_supply_propval value; + int stable_count = 0; + + wake_lock(&charger->chgin_wake_lock); + /* mask chrgin interrupt */ + max77823_update_reg(charger->i2c, MAX77823_CHG_INT_MASK, + 1 << 6, 1 << 6); + + while (1) { + psy_get_prop(charger, PS_BATT, POWER_SUPPLY_PROP_HEALTH, &value); + bat_health = value.intval; + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_00); + if (ret >= 0) { + chgin_dtls = ((ret & MAX77823_CHGIN_DTLS) >> + MAX77823_CHGIN_DTLS_SHIFT); + } + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_DETAILS_01); + if (ret >= 0) { + chg_dtls = ((ret & MAX77823_CHG_DTLS) >> + MAX77823_CHG_DTLS_SHIFT); + } + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_00); + if (ret >= 0) + chg_cnfg_00 = ret; + + if (prev_chgin_dtls == chgin_dtls) { + stable_count++; + } else { + stable_count = 0; + prev_chgin_dtls = chgin_dtls; + } + if (stable_count > 10) + break; + msleep(100); + } + pr_info("%s: irq(%d), chgin(0x%x), chg_dtls(0x%x) is_charging %d" + ", bat_health=0x%x\n", + __func__, charger->irq_chgin, chgin_dtls, chg_dtls, + charger->is_charging, bat_health); + if (charger->is_charging) { + if ((chgin_dtls == 0x02) && \ + (bat_health != POWER_SUPPLY_HEALTH_OVERVOLTAGE)) { + pr_info("%s: charger is over voltage\n", __func__); + } else if (((chgin_dtls == 0x0) || (chgin_dtls == 0x01)) && + (chg_dtls & 0x08) && \ + (chg_cnfg_00 & MAX77823_MODE_BUCK) && \ + (chg_cnfg_00 & MAX77823_MODE_CHGR) && \ + (bat_health != POWER_SUPPLY_HEALTH_UNDERVOLTAGE) && \ + (charger->cable_type != POWER_SUPPLY_TYPE_WIRELESS)) { + pr_info("%s, vbus_state : 0x%d, chg_state : 0x%d\n", + __func__, chgin_dtls, chg_dtls); + pr_info("%s: vBus is undervoltage\n", __func__); + } else if ((bat_health == POWER_SUPPLY_HEALTH_OVERVOLTAGE) && + (chgin_dtls != 0x02)) { + pr_info("%s: vbus_state : 0x%d, chg_state : 0x%d\n", + __func__, chgin_dtls, chg_dtls); + pr_info("%s: overvoltage->normal\n", __func__); + } else if ((bat_health == POWER_SUPPLY_HEALTH_UNDERVOLTAGE) && + !((chgin_dtls == 0) || (chgin_dtls == 1))) { + pr_info("%s: vbus_state : 0x%d, chg_state : 0x%d\n", + __func__, chgin_dtls, chg_dtls); + pr_info("%s: undervoltage->normal\n", __func__); + max77823_set_input_current(charger, + charger->charging_current_max); + } + } + /* Have the battery reevaluate charging */ + psy_get_prop(charger, PS_BATT, POWER_SUPPLY_PROP_HEALTH, &value); + /* unmask chrgin interrupt */ + max77823_update_reg(charger->i2c, + MAX77823_CHG_INT_MASK, 0, 1 << 6); + wake_unlock(&charger->chgin_wake_lock); +} + +static irqreturn_t max77823_chgin_irq(int irq, void *data) +{ + struct max77823_charger_data *charger = data; + queue_work(charger->wqueue, &charger->chgin_work); + + return IRQ_HANDLED; +} + +/* register chgin isr after sec_battery_probe */ +static void max77823_chgin_init_work(struct work_struct *work) +{ + struct max77823_charger_data *charger = container_of(work, + struct max77823_charger_data, + chgin_init_work.work); + int ret; + union power_supply_propval value; + + pr_info("%s \n", __func__); + queue_work(charger->wqueue, &charger->chgin_work); + charger->irq_chgin = charger->irq_base + MAX77823_CHG_IRQ_CHGIN_I; + ret = request_threaded_irq(charger->irq_chgin, NULL, + max77823_chgin_irq, 0, "chgin-irq", charger); + if (ret < 0) { + pr_err("%s: fail to request chgin IRQ: %d: %d\n", + __func__, charger->irq_chgin, ret); + charger->irq_chgin = 0; + } + value.intval = POWER_SUPPLY_TYPE_HV_MAINS; + psy_set_prop(charger, PS_BATT, POWER_SUPPLY_PROP_ONLINE, &value); + /* Have the battery reevaluate charging */ + psy_get_prop(charger, PS_BATT, POWER_SUPPLY_PROP_HEALTH, &value); +} + +#ifdef CONFIG_OF +static int max77823_otg_enable(struct max77823_charger_data *charger) +{ + pr_info("%s:\n", __func__); + + charger->otg_vbus_enabled = true; + charger->is_charging = false; + /* Disable charging from CHRG_IN when we are supplying power */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_12, + 0, 0x20); + + /* disable charger interrupt: CHG_I, CHGIN_I */ + /* enable charger interrupt: BYP_I */ + max77823_update_reg(charger->i2c, MAX77823_CHG_INT_MASK, + MAX77823_CHG_IM | MAX77823_CHGIN_IM, + MAX77823_CHG_IM | MAX77823_CHGIN_IM | MAX77823_BYP_IM); + /* disable charger detection */ +#ifdef CONFIG_EXTCON_MAX77828 + max77828_muic_set_chgdeten(DISABLE); +#endif + /* Update CHG_CNFG_11 to 0x54(5.1V) */ + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_11, 0x54); + + /* OTG on, boost on */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK, + CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK); + + pr_debug("%s: INT_MASK(0x%x), CHG_CNFG_00(0x%x)\n", __func__, + max77823_read_reg(charger->i2c, MAX77823_CHG_INT_MASK), + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_00)); + return 0; +} + +static int max77823_otg_disable(struct max77823_charger_data *charger) +{ + int enable_mask = CHG_CNFG_00_CHG_MASK | CHG_CNFG_00_BUCK_MASK; + + pr_info("%s:\n", __func__); + charger->otg_vbus_enabled = false; + if (charger->pdata->boost) + enable_mask |= CHG_CNFG_00_BOOST_MASK; + /* chrg on, OTG off, boost on/off, (buck on) */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + enable_mask, CHG_CNFG_00_CHG_MASK | CHG_CNFG_00_BUCK_MASK | + CHG_CNFG_00_OTG_MASK | CHG_CNFG_00_BOOST_MASK); + + mdelay(50); +#ifdef CONFIG_EXTCON_MAX77828 + max77828_muic_set_chgdeten(ENABLE); +#endif + /* enable charger interrupt */ + max77823_update_reg(charger->i2c, MAX77823_CHG_INT_MASK, + 0, MAX77823_CHG_IM | MAX77823_CHGIN_IM | MAX77823_BYP_IM); + + /* Allow charging from CHRG_IN when we are not supplying power */ + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_12, + 0x20, 0x20); + + if (charger->cable_type != POWER_SUPPLY_TYPE_BATTERY) + charger->is_charging = true; + pr_debug("%s: INT_MASK(0x%x), CHG_CNFG_00(0x%x)\n", __func__, + max77823_read_reg(charger->i2c, MAX77823_CHG_INT_MASK), + max77823_read_reg(charger->i2c, MAX77823_CHG_CNFG_00)); + return 0; +} + +int max77823_regulator_enable(struct regulator_dev *rdev) +{ + int ret = 0; + + if (rdev_get_id(rdev) == REG_OTG) { + ret = max77823_otg_enable(rdev_get_drvdata(rdev)); + } + return (ret < 0) ? ret : 0; +} + +int max77823_regulator_disable(struct regulator_dev *rdev) +{ + int ret = 0; + + if (rdev_get_id(rdev) == REG_OTG) { + ret = max77823_otg_disable(rdev_get_drvdata(rdev)); + } + return (ret < 0) ? ret : 0; +} + +int max77823_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct max77823_charger_data *charger = rdev_get_drvdata(rdev); + int ret; + + ret = max77823_read_reg(charger->i2c, rdev->desc->enable_reg); + if (ret < 0) + return ret; + + ret &= rdev->desc->enable_mask; + return ret != 0; +} + +int max77823_regulator_list_voltage_linear(struct regulator_dev *rdev, + unsigned int selector) +{ + if (selector >= rdev->desc->n_voltages) + return -EINVAL; + if (selector < rdev->desc->linear_min_sel) + return 0; + + selector -= rdev->desc->linear_min_sel; + + return rdev->desc->min_uV + (rdev->desc->uV_step * selector); +} + +static struct regulator_ops max77823_regulator_ops = { + .enable = max77823_regulator_enable, + .disable = max77823_regulator_disable, + .is_enabled = max77823_regulator_is_enabled, + .list_voltage = max77823_regulator_list_voltage_linear, +}; + +static struct regulator_desc regulators_ds[] = { + { + .name = "otg", + .n_voltages = 1, + .ops = &max77823_regulator_ops, + .type = REGULATOR_VOLTAGE, + .id = REG_OTG, + .owner = THIS_MODULE, + .min_uV = 5000000, + .enable_reg = MAX77823_CHG_CNFG_00, + .enable_mask = CHG_CNFG_00_OTG_MASK, + }, +}; + +static struct of_regulator_match reg_matches[] = { + { .name = "otg", }, +}; + +static int parse_regulators_dt(struct device *dev, const struct device_node *np, + struct max77823_charger_data *charger) +{ + struct regulator_config config = { }; + struct device_node *parent; + int ret; + int i; + + parent = of_get_child_by_name(np, "regulators"); + if (!parent) { + dev_err(dev, "regulators node not found\n"); + return -EINVAL; + } + + ret = of_regulator_match(dev, parent, reg_matches, + ARRAY_SIZE(reg_matches)); + + of_node_put(parent); + if (ret < 0) { + dev_err(dev, "Error parsing regulator init data: %d\n", + ret); + return ret; + } + + memcpy(charger->reg_descs, regulators_ds, + sizeof(charger->reg_descs)); + + for (i = 0; i < ARRAY_SIZE(reg_matches); i++) { + struct regulator_desc *desc = &charger->reg_descs[i]; + + config.dev = dev; + config.init_data = reg_matches[i].init_data; + config.driver_data = charger; + config.of_node = reg_matches[i].of_node; + config.ena_gpio = -EINVAL; + + charger->regulators[i] = + devm_regulator_register(dev, desc, &config); + if (IS_ERR(charger->regulators[i])) { + dev_err(dev, "register regulator%s failed\n", + desc->name); + return PTR_ERR(charger->regulators[i]); + } + } + return 0; +} + +static int sec_charger_read_u32_index_dt(const struct device_node *np, + const char *propname, + u32 index, u32 *out_value) +{ + struct property *prop = of_find_property(np, propname, NULL); + u32 len = (index + 1) * sizeof(*out_value); + + if (!prop) + return (-EINVAL); + if (!prop->value) + return (-ENODATA); + if (len > prop->length) + return (-EOVERFLOW); + + *out_value = be32_to_cpup(((__be32 *)prop->value) + index); + + return 0; +} + +static int max77823_charger_parse_dt(struct max77823_charger_data *charger, struct device_node *np) +{ + sec_battery_platform_data_t *pdata = charger->pdata; + int ret = 0; + + if (np == NULL) { + pr_err("%s np NULL\n", __func__); + return -1; + } else { + int i, len; + const u32 *p; + + ret = of_property_read_u32(np, "battery,chg_float_voltage", + &pdata->chg_float_voltage); + ret = of_property_read_u32(np, "battery,ovp_uvlo_check_type", + &pdata->ovp_uvlo_check_type); + ret = of_property_read_u32(np, "battery,full_check_type", + &pdata->full_check_type); + ret = of_property_read_u32(np, "boost", + &pdata->boost); + + if (!pdata->charging_current) { + p = of_get_property(np, "battery,input_current_limit", &len); + len = len / sizeof(u32); + pdata->charging_current = kzalloc(sizeof(sec_charging_current_t) * len, + GFP_KERNEL); + + pdata->charging_current_entries = len; + for(i = 0; i < len; i++) { + struct sec_charging_current *scc = &pdata->charging_current[i]; + + ret = sec_charger_read_u32_index_dt(np, + "battery,input_current_limit", i, + &scc->input_current_limit); + ret = sec_charger_read_u32_index_dt(np, + "battery,fast_charging_current", i, + &scc->fast_charging_current); + ret = sec_charger_read_u32_index_dt(np, + "battery,full_check_current_1st", i, + &scc->full_check_current_1st); + ret = sec_charger_read_u32_index_dt(np, + "battery,full_check_current_2nd", i, + &scc->full_check_current_2nd); + } + } + pr_info("%s:chg_float_voltage=%d, " + "ovp_uvlo_check_type=%d, " + "full_check_type=%d, " + "boost=%d\n", __func__, + pdata->chg_float_voltage, + pdata->ovp_uvlo_check_type, + pdata->full_check_type, + pdata->boost); + } + + return ret; +} +#endif + +const struct power_supply_desc psy_chg_desc = { + .name = "max77823-charger", + .type = POWER_SUPPLY_TYPE_UNKNOWN, + .properties = max77823_charger_props, + .num_properties = ARRAY_SIZE(max77823_charger_props), + .get_property = max77823_chg_get_property, + .set_property = max77823_chg_set_property, + .property_is_writeable = max77823_chg_property_is_writeable, +}; + +struct power_supply_config psy_chg_config = { +}; + +static int max77823_charger_probe(struct platform_device *pdev) +{ + struct max77823_dev *max77823 = dev_get_drvdata(pdev->dev.parent); + struct max77823_platform_data *pdata = dev_get_platdata(max77823->dev); + struct max77823_charger_data *charger; + int ret = 0; + struct regulator *reg_otg; + + pr_info("%s: Max77823 Charger Driver Loading\n", __func__); + + charger = kzalloc(sizeof(*charger), GFP_KERNEL); + if (!charger) + return -ENOMEM; + + pdata->charger_data = kzalloc(sizeof(sec_battery_platform_data_t), GFP_KERNEL); + if (!pdata->charger_data) { + ret = -ENOMEM; + goto err_free; + } + + mutex_init(&charger->charger_mutex); + charger->dev = &pdev->dev; + charger->i2c = max77823->charger; + charger->pdata = pdata->charger_data; + charger->irq_base = pdata->irq_base; + charger->aicl_on = false; + charger->siop_level = 100; + +#if defined(CONFIG_OF) + ret = max77823_charger_parse_dt(charger, pdev->dev.of_node); + if (ret < 0) { + pr_err("%s:dt error! ret[%d]\n", __func__, ret); + goto err_free; + } + ret = parse_regulators_dt(&pdev->dev, pdev->dev.of_node, charger); + if (ret < 0) { + pr_err("%s:reg dt error! ret[%d]\n", __func__, ret); + goto err_free; + } +#endif + + platform_set_drvdata(pdev, charger); + + reg_otg = devm_regulator_get_optional(&pdev->dev, "usbotg"); + if (PTR_ERR(reg_otg) == -EPROBE_DEFER) { + dev_err(&pdev->dev, "usbotg not ready, retry\n"); + ret = PTR_ERR(reg_otg); + goto err_free; + } + if (!IS_ERR(reg_otg)) { + charger->otg_regulator_nb.notifier_call = + max77823_otg_regulator_nb; + ret = regulator_register_notifier(reg_otg, + &charger->otg_regulator_nb); + if (ret != 0) { + dev_err(&pdev->dev, + "Failed to register regulator notifier: %d\n", + ret); + } else { + dev_err(&pdev->dev, "usbotg notifier success\n"); + } + } + + max77823_charger_initialize(charger); + + (void) debugfs_create_file("max77823-regs", + S_IRUGO, NULL, (void *)charger, &max77823_debugfs_fops); + + charger->wqueue = + create_singlethread_workqueue(dev_name(&pdev->dev)); + if (!charger->wqueue) { + pr_err("%s: Fail to Create Workqueue\n", __func__); + kfree(pdata->charger_data); + ret = -ENOMEM; + goto err_free; + } + wake_lock_init(&charger->chgin_wake_lock, WAKE_LOCK_SUSPEND, + "charger-chgin"); + INIT_WORK(&charger->chgin_work, max77823_chgin_isr_work); + INIT_DELAYED_WORK(&charger->chgin_init_work, max77823_chgin_init_work); + INIT_DELAYED_WORK(&charger->chg_cable_work, max77823_chg_cable_work); + wake_lock_init(&charger->wpc_wake_lock, WAKE_LOCK_SUSPEND, + "charger-wpc"); + INIT_DELAYED_WORK(&charger->wpc_work, wpc_detect_work); + psy_chg_config.drv_data = charger; + charger->psy_chg = power_supply_register(&pdev->dev, &psy_chg_desc, &psy_chg_config); + if (IS_ERR(charger->psy_chg)) { + pr_err("%s: Failed to Register psy_chg\n", __func__); + ret = PTR_ERR(charger->psy_chg); + goto err_workqueue; + } + + if (charger->pdata->chg_irq) { + INIT_DELAYED_WORK(&charger->isr_work, max77823_chg_isr_work); + + charger->chg_irq = charger->pdata->chg_irq; + ret = request_threaded_irq(charger->chg_irq, + NULL, max77823_chg_irq_thread, + charger->pdata->chg_irq_attr, + "charger-irq", charger); + if (ret) { + pr_err("%s: Failed to Request IRQ\n", __func__); + goto err_irq; + } + + ret = enable_irq_wake(charger->chg_irq); + if (ret < 0) + pr_err("%s: Failed to Enable Wakeup Source(%d)\n", + __func__, ret); + } + + charger->wc_w_irq = pdata->irq_base + MAX77823_CHG_IRQ_WCIN_I; + ret = request_threaded_irq(charger->wc_w_irq, + NULL, wpc_charger_irq, + IRQF_TRIGGER_FALLING, + "wpc-int", charger); + if (ret) { + pr_err("%s: Failed to Request IRQ\n", __func__); + goto err_wc_irq; + } + + /* Update CHG_CNFG_11 to 0x54(5.1V), boost to 5.1V */ + max77823_write_reg(charger->i2c, + MAX77823_CHG_CNFG_11, 0x54); + + ret = max77823_read_reg(charger->i2c, MAX77823_CHG_INT_OK); + if (ret >= 0) { + charger->wc_w_state = (ret & MAX77823_WCIN_OK) + >> MAX77823_WCIN_OK_SHIFT; + } + + max77823_update_reg(charger->i2c, MAX77823_CHG_CNFG_00, + charger->pdata->boost ? CHG_CNFG_00_BOOST_MASK : 0, + CHG_CNFG_00_BOOST_MASK); + + /* enable chgin irq after sec_battery_probe */ + queue_delayed_work(charger->wqueue, &charger->chgin_init_work, + msecs_to_jiffies(3000)); + + charger->irq_bypass = pdata->irq_base + MAX77823_CHG_IRQ_BYP_I; + ret = request_threaded_irq(charger->irq_bypass, NULL, + max77823_bypass_irq, 0, "bypass-irq", charger); + if (ret < 0) { + pr_err("%s: fail to request bypass IRQ: %d: %d\n", + __func__, charger->irq_bypass, ret); + charger->irq_bypass = 0; + } + + pr_info("%s: MAX77823 Charger Driver Loaded\n", __func__); + + return 0; + +err_wc_irq: + if (charger->chg_irq) + free_irq(charger->chg_irq, charger); +err_irq: + power_supply_unregister(charger->psy_chg); +err_workqueue: + destroy_workqueue(charger->wqueue); +err_free: + kfree(charger); + + return ret; +} + +static int max77823_charger_remove(struct platform_device *pdev) +{ + struct max77823_charger_data *charger = + platform_get_drvdata(pdev); +// int i; + + destroy_workqueue(charger->wqueue); + if (charger->wc_w_irq) + free_irq(charger->wc_w_irq, charger); + if (charger->chg_irq) + free_irq(charger->chg_irq, charger); + if (charger->irq_chgin) + free_irq(charger->irq_chgin, charger); + if (charger->irq_bypass) + free_irq(charger->irq_bypass, charger); + power_supply_unregister(charger->psy_chg); +// for (i = 0; i < ARRAY_SIZE(charger->psy_ref); i++) +// power_supply_put(charger->psy_ref[i]); + kfree(charger); + + return 0; +} + +#if defined CONFIG_PM +static int max77823_charger_suspend(struct device *dev) +{ + return 0; +} + +static int max77823_charger_resume(struct device *dev) +{ + return 0; +} +#else +#define max77823_charger_suspend NULL +#define max77823_charger_resume NULL +#endif + +static void max77823_charger_shutdown(struct device *dev) +{ +/* No need to turn off charging when device is going to poweroff */ +#if 0 + struct max77823_charger_data *charger = + dev_get_drvdata(dev); + + pr_info("%s: MAX77823 Charger driver shutdown\n", __func__); + if (!charger->i2c) { + pr_err("%s: no max77823 i2c client\n", __func__); + return; + } + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_00, 0x04); + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_09, 0x0f); + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_10, 0x19); + max77823_write_reg(charger->i2c, MAX77823_CHG_CNFG_12, 0x67); +#endif + pr_info("func:%s \n", __func__); +} + +#ifdef CONFIG_OF +static struct of_device_id max77823_charger_dt_ids[] = { + { .compatible = "samsung,max77823-charger" }, + { } +}; +MODULE_DEVICE_TABLE(of, max77823_charger_dt_ids); +#endif + +static SIMPLE_DEV_PM_OPS(max77823_charger_pm_ops, max77823_charger_suspend, + max77823_charger_resume); + +static struct platform_driver max77823_charger_driver = { + .driver = { + .name = "max77823-charger", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &max77823_charger_pm_ops, +#endif + .shutdown = max77823_charger_shutdown, +#ifdef CONFIG_OF + .of_match_table = max77823_charger_dt_ids, +#endif + }, + .probe = max77823_charger_probe, + .remove = max77823_charger_remove, +}; + +static int __init max77823_charger_init(void) +{ + pr_info("%s : \n", __func__); + return platform_driver_register(&max77823_charger_driver); +} + +static void __exit max77823_charger_exit(void) +{ + platform_driver_unregister(&max77823_charger_driver); +} + +module_init(max77823_charger_init); +module_exit(max77823_charger_exit); + +MODULE_DESCRIPTION("Samsung MAX77823 Charger Driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:max77823-charger"); diff --git a/drivers/battery/max77823_fuelgauge.c b/drivers/battery/max77823_fuelgauge.c new file mode 100644 index 00000000000000..0dea8e50a79188 --- /dev/null +++ b/drivers/battery/max77823_fuelgauge.c @@ -0,0 +1,2559 @@ +/* + * max77823_fuelgauge.c + * Samsung MAX77823 Fuel Gauge Driver + * + * Copyright (C) 2012 Samsung Electronics + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MV_TO_UV(mv) (mv * 1000) + +extern void board_fuelgauge_init(void *data); + +static enum power_supply_property max77823_fuelgauge_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_VOLTAGE_AVG, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CURRENT_AVG, + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, + POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, + POWER_SUPPLY_PROP_ENERGY_FULL, + POWER_SUPPLY_PROP_ENERGY_EMPTY, + POWER_SUPPLY_PROP_ENERGY_NOW, + POWER_SUPPLY_PROP_ENERGY_AVG, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TEMP_AMBIENT, +}; + +static const char* const psy_names[] = { +[PS_BATT] = "battery", +}; + +static int psy_get_prop(struct max77823_fuelgauge_data *fuelgauge, enum ps_id id, enum power_supply_property property, union power_supply_propval *value) +{ + struct power_supply *psy = fuelgauge->psy_ref[id]; + int ret = -EINVAL; + + value->intval = 0; + if (!psy) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + do { + psy = power_supply_get_by_name(psy_names[id]); + if (psy) { + fuelgauge->psy_ref[id] = psy; + break; + } + if (time_after(jiffies, timeout)) { + pr_err("%s: fuel Failed %s(%d)\n", __func__, psy_names[id], property); + return -ENODEV; + } + msleep(1); + } while (1); + } + if (psy->desc->get_property) { + ret = psy->desc->get_property(psy, property, value); + if (ret < 0) + pr_err("%s: fuel Fail to get %s(%d=>%d)\n", __func__, psy_names[id], property, ret); + } + return ret; +} + +static int psy_set_prop(struct max77823_fuelgauge_data *fuelgauge, enum ps_id id, enum power_supply_property property, union power_supply_propval *value) +{ + struct power_supply *psy = fuelgauge->psy_ref[id]; + int ret = -EINVAL; + + if (!psy) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + do { + psy = power_supply_get_by_name(psy_names[id]); + if (psy) { + fuelgauge->psy_ref[id] = psy; + break; + } + if (time_after(jiffies, timeout)) { + pr_err("%s: fuel Failed %s\n", __func__, psy_names[id]); + return -ENODEV; + } + msleep(1); + } while (1); + } + if (psy->desc->set_property) { + ret = psy->desc->set_property(psy, property, value); + if (ret < 0) + pr_err("%s: fuel Fail to set %s(%d=>%d)\n", __func__, psy_names[id], property, ret); + } + return ret; +} + +static int max77823_get_v(struct max77823_fuelgauge_data *fuelgauge, int reg) +{ + u32 v = 0; + int ret; + + ret = max77823_read_word(fuelgauge->i2c, reg); + if (ret < 0) + return ret; + + pr_debug("%s: reg 0x%x=(%d)\n", __func__, reg, ret); + v = (ret >> 3) * 625; + return v; +} + +static int max77823_get_vfocv(struct max77823_fuelgauge_data *fuelgauge) +{ + return max77823_get_v(fuelgauge, MAX77823_REG_VFOCV); +} + +static int max77823_get_vcell(struct max77823_fuelgauge_data *fuelgauge) +{ + return max77823_get_v(fuelgauge, MAX77823_REG_VCELL); +} + +static int max77823_get_avgvcell(struct max77823_fuelgauge_data *fuelgauge) +{ + return max77823_get_v(fuelgauge, MAX77823_REG_AVGVCELL); +} + +static int max77823_get_status(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS); + if (ret < 0) + return ret; + + pr_debug("%s: reg 0x%x=(0x%x)\n", __func__, MAX77823_REG_STATUS, ret); + if (ret & (1 << 3)) { + /* battery is absent */ + return POWER_SUPPLY_STATUS_NOT_CHARGING; + } + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS2); + if (ret < 0) + return ret; + pr_debug("%s: reg 0x%x=(0x%x)\n", __func__, MAX77823_REG_STATUS2, ret); + if (ret & (1 << 5)) { + return POWER_SUPPLY_STATUS_FULL; + } + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_MAXMIN); + if (ret < 0) + return ret; + pr_debug("%s: reg 0x%x=(0x%x)\n", __func__, MAX77823_REG_MAXMIN, ret); + max77823_write_word(fuelgauge->i2c, MAX77823_REG_MAXMIN, 0x807f); + if (ret == 0x807f) + ret = fuelgauge->prev_status; + else + fuelgauge->prev_status = ret; + ret <<= 16; /* sign extend */ + ret >>= 16; + if (ret > 0) + return POWER_SUPPLY_STATUS_CHARGING; + ret <<= 24; /* sign extend */ + ret >>= 24; + if (ret < 0) + return POWER_SUPPLY_STATUS_DISCHARGING; + return POWER_SUPPLY_STATUS_NOT_CHARGING; +} + +#ifdef CONFIG_FUELGAUGE_MAX77823_VOLTAGE_TRACKING +static void max77823_init_regs(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_FILTERCFG); + if (ret < 0) + return; + + /* Clear average vcell (12 sec) */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_FILTERCFG, ret & 0xff8f); +} + +static void max77823_get_version(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_VERSION); + if (ret < 0) + return; + pr_debug("MAX77823 Fuel-Gauge Ver 0x%x\n", ret); +} + +static void max77823_alert_init(struct max77823_fuelgauge_data *fuelgauge) +{ + /* SALRT Threshold setting */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_SALRT_TH, + 0xff00 | fuelgauge->pdata->fuel_alert_soc); + + /* VALRT Threshold setting */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_VALRT_TH, 0xff00); + + /* TALRT Threshold setting */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TALRT_TH, 0x7f80); +} + +static bool max77823_check_status(struct max77823_fuelgauge_data *fuelgauge) +{ + bool ret = false; + + /* check if Smn was generated */ + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS); + if (ret < 0) + return ret; + + pr_info("%s: status_reg(%x)\n", __func__, ret); + + /* minimum SOC threshold exceeded. */ + if (ret & (0x1 << 10)) + ret = true; + + /* clear status reg */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_STATUS, ret & 0xff); + msleep(200); + return ret; +} + +static int max77823_set_temperature(struct max77823_fuelgauge_data *fuelgauge, + int temperature) +{ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TEMPERATURE, temperature << 8); + pr_debug("%s: temperature to (%d)\n", __func__, temperature); + return temperature; +} +/* return units of 1/10 C */ +static int max77823_get_temperature(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + if (fuelgauge->pdata->temp_disabled) + return 200; + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_TEMPERATURE); + if (ret < 0) + return -ERANGE; + + /* data[] store 2's compliment format number */ + ret <<= 16; + ret >>= 16; /* extent sign bit */ + ret = (ret * 10) >> 8; + pr_debug("%s: temperature (%d)\n", __func__, ret); + return ret; +} + +/* soc should be 0.01% unit */ +static int max77823_get_soc(struct max77823_fuelgauge_data *fuelgauge) +{ + int soc; + int ret; + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_SOC_VF); + if (ret < 0) + return ret; + + soc = (ret * 100) >> 8; + pr_debug("%s: raw capacity (%d)\n", __func__, soc); + return min(soc, 10000); +} + +bool max77823_fg_init(struct max77823_fuelgauge_data *fuelgauge) +{ + /* initialize fuel gauge registers */ + max77823_init_regs(fuelgauge); + + max77823_get_version(fuelgauge); + + return true; +} + +bool max77823_fg_fuelalert_init(struct max77823_fuelgauge_data *fuelgauge, + int soc) +{ + int ret; + + /* 1. Set max77823 alert configuration. */ + max77823_alert_init(fuelgauge); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_CONFIG); + if (ret < 0) + return ret; + + /*Enable Alert (Aen = 1) */ + ret |= (1 << 2); + max77823_write_word(fuelgauge->i2c, MAX77823_REG_CONFIG, ret); + + pr_debug("%s: config_reg(%x) irq(%d)\n", __func__, ret, + fuelgauge->pdata->fg_irq); + return true; +} + +bool max77823_fg_is_fuelalerted(struct max77823_fuelgauge_data *fuelgauge) +{ + return max77823_check_status(fuelgauge); +} + +bool max77823_fg_fuelalert_process(void *irq_data, bool is_fuel_alerted) +{ + struct max77823_fuelgauge_data *fuelgauge = irq_data; + int ret; + + /* update SOC */ + /* max77823_get_soc(fuelgauge); */ + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_CONFIG); + if (ret < 0) + return false; + if (is_fuel_alerted) { + ret |= (1 << 11); + pr_info("%s: Fuel-alert Alerted!! (%x)\n", __func__, ret); + } else { + ret &= ~(1 << 11); + pr_info("%s: Fuel-alert Released!! (%x)\n", __func__, ret); + } + max77823_write_word(fuelgauge->i2c, MAX77823_REG_CONFIG, ret); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_VCELL); + pr_debug("%s: MAX77823_REG_VCELL(%x)\n", __func__, ret); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_TEMPERATURE); + pr_debug("%s: MAX77823_REG_TEMPERATURE(%x)\n", __func__, ret); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_CONFIG); + pr_debug("%s: MAX77823_REG_CONFIG(%x)\n", __func__, ret); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_VFOCV); + pr_debug("%s: MAX77823_REG_VFOCV(%x)\n", __func__, ret); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_SOC_VF); + pr_debug("%s: MAX77823_REG_SOC_VF(%x)\n", __func__, ret); + + pr_debug("%s: FUEL GAUGE IRQ (%d)\n", + __func__, gpio_get_value(fuelgauge->pdata->fg_irq)); + + return true; +} + +bool max77823_fg_full_charged(struct max77823_fuelgauge_data *fuelgauge) +{ + return true; +} +#endif + +static void fg_test_print(struct max77823_fuelgauge_data *fuelgauge) +{ +#ifdef DEBUG + u32 average_vcell; + u32 temp; + u32 temp2; + u16 reg_data; + int ret; + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_AVGVCELL); + if (ret < 0) { + pr_err("%s: Failed to read VCELL\n", __func__); + return; + } + + temp = (ret & 0xFFF) * 78125; + average_vcell = temp / 1000000; + + temp = ((ret & 0xF000) >> 4) * 78125; + temp2 = temp / 1000000; + average_vcell += (temp2 << 4); + + pr_info("%s: AVG_VCELL(%d), data(0x%04x)\n", __func__, + average_vcell, ret); + + reg_data = max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + pr_info("%s: FULLCAP(%d), data(0x%04x)\n", __func__, + reg_data/2, reg_data); + + reg_data = max77823_read_word(fuelgauge->i2c, REMCAP_REP_REG); + pr_info("%s: REMCAP_REP(%d), data(0x%04x)\n", __func__, + reg_data/2, reg_data); + + reg_data = max77823_read_word(fuelgauge->i2c, REMCAP_MIX_REG); + pr_info("%s: REMCAP_MIX(%d), data(0x%04x)\n", __func__, + reg_data/2, reg_data); + + reg_data = max77823_read_word(fuelgauge->i2c, REMCAP_AV_REG); + pr_info("%s: REMCAP_AV(%d), data(0x%04x)\n", __func__, + reg_data/2, reg_data); + + reg_data = max77823_read_word(fuelgauge->i2c, MAX77823_REG_CONFIG); + pr_info("%s: CONFIG(0x%02x), data(0x%04x)\n", __func__, + MAX77823_REG_CONFIG, reg_data); +#endif +} + +static void fg_periodic_read(struct max77823_fuelgauge_data *fuelgauge) +{ +#ifdef DEBUG + u8 reg; + int i; + int data[0x10]; + char *str = NULL; + + str = kzalloc(sizeof(char)*1024, GFP_KERNEL); + if (!str) + return; + + for (i = 0; i < 16; i++) { + for (reg = 0; reg < 0x10; reg++) + data[reg] = max77823_read_word(fuelgauge->i2c, reg + i * 0x10); + + sprintf(str+strlen(str), + "%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,", + data[0x00], data[0x01], data[0x02], data[0x03], + data[0x04], data[0x05], data[0x06], data[0x07]); + sprintf(str+strlen(str), + "%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,%04xh,", + data[0x08], data[0x09], data[0x0a], data[0x0b], + data[0x0c], data[0x0d], data[0x0e], data[0x0f]); + if (i == 4) + i = 13; + } + + pr_info("%s", str); + + kfree(str); +#endif +} + +#ifdef CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING +static int fg_check_battery_present(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + /* 1. Check Bst bit */ + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS); + if (ret < 0) { + pr_err("%s: Failed to read STATUS\n", __func__); + return 0; + } + + if (ret & (0x1 << 3)) { + pr_info("%s: status(0x%x)\n", __func__, ret); + pr_info("%s: battery is absent!!\n", __func__); + return 0; + } + return 1; +} + +static int fg_write_temp(struct max77823_fuelgauge_data *fuelgauge, + int temperature) +{ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TEMPERATURE, (temperature * 256) / 10); + pr_debug("%s: temperature to %d\n", __func__, temperature); + return temperature; +} + +static int fg_read_temp(struct max77823_fuelgauge_data *fuelgauge) +{ + int temper = 200; /* 20.0 C */ + int ret; + + if (fuelgauge->pdata->temp_disabled) + return 200; + if (fg_check_battery_present(fuelgauge)) { + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_TEMPERATURE); + if (ret < 0) { + pr_err("%s: Failed to read TEMPERATURE\n", __func__); + return temper; + } + + ret <<= 16; /* sign extend value */ + ret >>= 16; + temper = (ret * 10) >> 8; + } + +#ifdef DEBUG + if (!(fuelgauge->info.pr_cnt % PRINT_COUNT)) + pr_info("%s: TEMPERATURE(%d)\n", + __func__, temper); +#endif + return temper; +} +#endif + +/* soc should be 0.1% unit */ +static int fg_read_percent(struct max77823_fuelgauge_data *fuelgauge, int reg) +{ + int soc; + int ret; + + ret = max77823_read_word(fuelgauge->i2c, reg); + if (ret < 0) { + pr_err("%s: Failed to read 0x%x\n", __func__, reg); + return ret; + } + soc = (ret * 10) >> 8; + return min(soc, 1000); +} + +static int fg_read_vfsoc(struct max77823_fuelgauge_data *fuelgauge) +{ + return fg_read_percent(fuelgauge, MAX77823_REG_SOC_VF); +} + +#ifdef CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING +static int fg_read_power(struct max77823_fuelgauge_data *fuelgauge, int reg) +{ + + int ret; + + ret = max77823_read_word(fuelgauge->i2c, reg); + if (ret < 0) + pr_err("%s: Failed to read 0x%x(%d)\n", __func__, reg, ret); + /* + * convert from uVh to uWh, with a 10 mOhm sense resistor + * uVh/(.010 Ohms) = uVh * 100/Ohms = 100uAh + * uAh * V = uWh + */ + return ret * 370 ; /* 3.7 Volts nominal */ +} +#endif + +#ifdef DEBUG +static void dbg_current_avg(struct max77823_fuelgauge_data *fuelgauge, s32 i_current) +{ + s32 avg_current; + int ret = max77823_read_word(fuelgauge->i2c, AVG_CURRENT_REG); + + if (ret < 0) { + pr_err("%s: Failed to read AVERAGE CURRENT\n", __func__); + return; + } + + ret <<= 16; /* extend sign bit */ + ret >>= 16; + + /* 1.5625uV/0.01Ohm(Rsense) = 156.25uA */ + avg_current = (ret * 15625) / 100; + + if (!(fuelgauge->info.pr_cnt++ % PRINT_COUNT)) { + fg_test_print(fuelgauge); + pr_debug("%s: CURRENT(%duA), AVG_CURRENT(%duA)\n", __func__, + i_current, avg_current); + /* Read max77823's all registers every 5 minute. */ + fg_periodic_read(fuelgauge); + fuelgauge->info.pr_cnt = 1; + } +} +#endif + +static int fg_read_current(struct max77823_fuelgauge_data *fuelgauge) +{ + s32 i_current; + int ret = max77823_read_word(fuelgauge->i2c, CURRENT_REG); + + if (ret < 0) { + pr_err("%s: Failed to read CURRENT\n", __func__); + return ret; + } + + ret <<= 16; /* extend sign bit */ + ret >>= 16; + + /* 1.5625uV / 0.01Ohm(Rsense) = 156.25uA */ + i_current = (ret * 15625) / 100; + +#ifdef DEBUG + dbg_current_avg(fuelgauge, i_current); +#endif + + return i_current; +} + +static int fg_read_avg_current(struct max77823_fuelgauge_data *fuelgauge) +{ + s32 avg_current; + int ret; + + ret = max77823_read_word(fuelgauge->i2c, AVG_CURRENT_REG); + if (ret < 0) { + pr_err("%s: Failed to read AVERAGE CURRENT\n", + __func__); + return 0; + } + + ret <<= 16; /* extend sign bit */ + ret >>= 16; + + /* 1.5625uV/0.01Ohm(Rsense) = 156.25uA */ + avg_current = (ret * 15625) / 100; + return avg_current; +} + +int fg_reset_soc(struct max77823_fuelgauge_data *fuelgauge) +{ + int vfocv, fullcap; + int ret; + + /* delay for current stablization */ + msleep(500); + + pr_info("%s: Before quick-start - VCELL(%d), VFOCV(%d), VfSOC(%d), RepSOC(%d)\n", + __func__, max77823_get_vcell(fuelgauge), max77823_get_vfocv(fuelgauge), + fg_read_vfsoc(fuelgauge), fg_read_percent(fuelgauge, SOCREP_REG)); + pr_info("%s: Before quick-start - current(%d), avg current(%d)\n", + __func__, fg_read_current(fuelgauge), + fg_read_avg_current(fuelgauge)); + + if (fuelgauge->pdata->check_jig_status && + !fuelgauge->pdata->check_jig_status()) { + pr_info("%s : Return by No JIG_ON signal\n", __func__); + return 0; + } + + max77823_write_word(fuelgauge->i2c, CYCLES_REG, 0); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_MISCCFG); + if (ret < 0) { + pr_err("%s: Failed to read MiscCFG\n", __func__); + return ret; + } + + ret |= (0x1 << 10); + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_MISCCFG, ret); + if (ret < 0) { + pr_err("%s: Failed to write MiscCFG\n", __func__); + return ret; + } + + msleep(250); + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + fuelgauge->battery_data->Capacity); + msleep(500); + + pr_info("%s: After quick-start - VCELL(%d), VFOCV(%d), VfSOC(%d), RepSOC(%d)\n", + __func__, max77823_get_vcell(fuelgauge), max77823_get_vfocv(fuelgauge), + fg_read_vfsoc(fuelgauge), fg_read_percent(fuelgauge, SOCREP_REG)); + pr_info("%s: After quick-start - current(%d), avg current(%d)\n", + __func__, fg_read_current(fuelgauge), + fg_read_avg_current(fuelgauge)); + + max77823_write_word(fuelgauge->i2c, CYCLES_REG, 0x00a0); + +/* P8 is not turned off by Quickstart @3.4V + * (It's not a problem, depend on mode data) + * Power off for factory test(File system, etc..) */ + vfocv = max77823_get_vfocv(fuelgauge); + if (vfocv < POWER_OFF_VOLTAGE_LOW_MARGIN) { + pr_info("%s: Power off condition(%d)\n", __func__, vfocv); + + fullcap = max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + + /* FullCAP * 0.009 */ + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(fullcap * 9 / 1000)); + msleep(200); + pr_info("%s: new soc=%d, vfocv=%d\n", __func__, + fg_read_percent(fuelgauge, SOCREP_REG), vfocv); + } + + pr_info("%s: Additional step - VfOCV(%d), VfSOC(%d), RepSOC(%d)\n", + __func__, max77823_get_vfocv(fuelgauge), + fg_read_vfsoc(fuelgauge), fg_read_percent(fuelgauge, SOCREP_REG)); + + return 0; +} +#ifdef CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING + +int fg_reset_capacity_by_jig_connection(struct max77823_fuelgauge_data *fuelgauge) +{ + + pr_info("%s: DesignCap = Capacity - 1 (Jig Connection)\n", __func__); + + return max77823_write_word(fuelgauge->i2c, DESIGNCAP_REG, + fuelgauge->battery_data->Capacity-1); +} + +int fg_adjust_capacity(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + + /* 1. Write RemCapREP(05h)=0; */ + ret = max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, 0); + if (ret < 0) { + pr_err("%s: Failed to write RemCap_REP\n", __func__); + return ret; + } + msleep(200); + + pr_info("%s: After adjust - RepSOC(%d)\n", __func__, + fg_read_percent(fuelgauge, SOCREP_REG)); + + return 0; +} + +void fg_low_batt_compensation(struct max77823_fuelgauge_data *fuelgauge, + u32 level) +{ + int read_val; + u32 temp; + + pr_info("%s: Adjust SOCrep to %d!!\n", __func__, level); + + read_val = max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + /* RemCapREP (05h) = FullCap(10h) x 0.0090 */ + temp = read_val * (level*90) / 10000; + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)temp); +} + +static int fg_check_status_reg(struct max77823_fuelgauge_data *fuelgauge) +{ + int ret; + int status; + + /* 1. Check Smn was generated read */ + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS); + if (ret < 0) { + pr_err("%s: Failed to read STATUS\n", __func__); + return ret; + } + status = ret; + pr_info("%s: addr(0x00), data(0x%x)\n", __func__, status); + + /* 2. clear Status reg */ + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_STATUS, status & 0xff); + if (ret < 0) { + pr_info("%s: Failed to write STATUS\n", __func__); + return ret; + } + return (status >> 10) & 1; +} + +int fg_alert_init(struct max77823_fuelgauge_data *fuelgauge, int soc) +{ + int ret; + + /* Using RepSOC */ + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_MISCCFG); + if (ret < 0) { + pr_err("%s: Failed to read MISCCFG\n", __func__); + return ret; + } + + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_MISCCFG, ret & ~3); + if (ret < 0) { + pr_info("%s: Failed to write MISCCFG\n", __func__); + return ret; + } + + /* SALRT Threshold setting */ + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_SALRT_TH, 0xff00 | soc); + if (ret < 0) { + pr_info("%s: Failed to write SALRT\n", __func__); + return -1; + } + + /* Reset VALRT Threshold setting (disable) */ + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_VALRT_TH, 0xff00); + if (ret < 0) { + pr_info("%s: Failed to write VALRT\n", __func__); + return ret; + } + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_VALRT_TH); + if (ret != 0xff00) + pr_err("%s: VALRT is not valid (0x%x)\n", __func__, ret); + + /* Reset TALRT Threshold setting (disable) */ + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_TALRT_TH, 0x7f80); + if (ret < 0) { + pr_info("%s: Failed to write TALRT\n", __func__); + return ret; + } + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_TALRT_TH); + if (ret != 0x7f80) + pr_err("%s: TALRT is not valid (0x%x)\n", __func__, ret); + + /*mdelay(100);*/ + + /* Enable SOC alerts */ + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_CONFIG); + if (ret < 0) { + pr_err("%s: Failed to read CONFIG\n", __func__); + return ret; + } + + ret = max77823_write_word(fuelgauge->i2c, MAX77823_REG_CONFIG, ret | (1 << 2)); + if (ret < 0) { + pr_info("%s: Failed to write CONFIG\n", __func__); + return ret; + } + return 1; +} + +void fg_fullcharged_compensation(struct max77823_fuelgauge_data *fuelgauge, + u32 is_recharging, bool pre_update) +{ + static int new_fullcap_data; + + pr_info("%s: is_recharging(%d), pre_update(%d)\n", + __func__, is_recharging, pre_update); + + new_fullcap_data = + max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + if (new_fullcap_data < 0) + new_fullcap_data = fuelgauge->battery_data->Capacity; + + /* compare with initial capacity */ + if (new_fullcap_data > + (fuelgauge->battery_data->Capacity * 110 / 100)) { + pr_info("%s: [Case 1] capacity = 0x%04x, NewFullCap = 0x%04x\n", + __func__, fuelgauge->battery_data->Capacity, + new_fullcap_data); + + new_fullcap_data = + (fuelgauge->battery_data->Capacity * 110) / 100; + + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(new_fullcap_data)); + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + (u16)(new_fullcap_data)); + } else if (new_fullcap_data < + (fuelgauge->battery_data->Capacity * 50 / 100)) { + pr_info("%s: [Case 5] capacity = 0x%04x, NewFullCap = 0x%04x\n", + __func__, fuelgauge->battery_data->Capacity, + new_fullcap_data); + + new_fullcap_data = + (fuelgauge->battery_data->Capacity * 50) / 100; + + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(new_fullcap_data)); + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + (u16)(new_fullcap_data)); + } else { + /* compare with previous capacity */ + if (new_fullcap_data > + (fuelgauge->info.previous_fullcap * 110 / 100)) { + pr_info("%s: [Case 2] previous_fullcap = 0x%04x, NewFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_fullcap, + new_fullcap_data); + + new_fullcap_data = + (fuelgauge->info.previous_fullcap * 110) / 100; + + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(new_fullcap_data)); + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + (u16)(new_fullcap_data)); + } else if (new_fullcap_data < + (fuelgauge->info.previous_fullcap * 90 / 100)) { + pr_info("%s: [Case 3] previous_fullcap = 0x%04x, NewFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_fullcap, + new_fullcap_data); + + new_fullcap_data = + (fuelgauge->info.previous_fullcap * 90) / 100; + + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(new_fullcap_data)); + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + (u16)(new_fullcap_data)); + } else { + pr_info("%s: [Case 4] previous_fullcap = 0x%04x, NewFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_fullcap, + new_fullcap_data); + } + } + + /* 4. Write RepSOC(06h)=100%; */ + max77823_write_word(fuelgauge->i2c, SOCREP_REG, (u16)(0x64 << 8)); + + /* 5. Write MixSOC(0Dh)=100%; */ + max77823_write_word(fuelgauge->i2c, SOCMIX_REG, (u16)(0x64 << 8)); + + /* 6. Write AVSOC(0Eh)=100%; */ + max77823_write_word(fuelgauge->i2c, SOCAV_REG, (u16)(0x64 << 8)); + + /* if pre_update case, skip updating PrevFullCAP value. */ + if (!pre_update) + fuelgauge->info.previous_fullcap = + max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + + pr_debug("%s: (A) FullCap = 0x%04x, RemCap = 0x%04x\n", __func__, + max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG), + max77823_read_word(fuelgauge->i2c, REMCAP_REP_REG)); + + fg_periodic_read(fuelgauge); +} + +void fg_check_vf_fullcap_range(struct max77823_fuelgauge_data *fuelgauge) +{ + static int new_vffullcap; + bool is_vffullcap_changed = true; + + if (fuelgauge->pdata->check_jig_status && + fuelgauge->pdata->check_jig_status()) + fg_reset_capacity_by_jig_connection(fuelgauge); + + new_vffullcap = max77823_read_word(fuelgauge->i2c, FULLCAP_NOM_REG); + if (new_vffullcap < 0) + new_vffullcap = fuelgauge->battery_data->Capacity; + + /* compare with initial capacity */ + if (new_vffullcap > + (fuelgauge->battery_data->Capacity * 110 / 100)) { + pr_debug("%s: [Case 1] capacity = 0x%04x, NewVfFullCap = 0x%04x\n", + __func__, fuelgauge->battery_data->Capacity, + new_vffullcap); + + new_vffullcap = + (fuelgauge->battery_data->Capacity * 110) / 100; + + max77823_write_word(fuelgauge->i2c, DQACC_REG, + (u16)(new_vffullcap / 4)); + max77823_write_word(fuelgauge->i2c, DPACC_REG, (u16)0x3200); + } else if (new_vffullcap < + (fuelgauge->battery_data->Capacity * 50 / 100)) { + pr_debug("%s: [Case 5] capacity = 0x%04x, NewVfFullCap = 0x%04x\n", + __func__, fuelgauge->battery_data->Capacity, + new_vffullcap); + + new_vffullcap = + (fuelgauge->battery_data->Capacity * 50) / 100; + + max77823_write_word(fuelgauge->i2c, DQACC_REG, + (u16)(new_vffullcap / 4)); + max77823_write_word(fuelgauge->i2c, DPACC_REG, + (u16)0x3200); + } else { + /* compare with previous capacity */ + if (new_vffullcap > + (fuelgauge->info.previous_vffullcap * 110 / 100)) { + pr_debug("%s: [Case 2] previous_vffullcap = 0x%04x, NewVfFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_vffullcap, + new_vffullcap); + + new_vffullcap = + (fuelgauge->info.previous_vffullcap * 110) / + 100; + + max77823_write_word(fuelgauge->i2c, DQACC_REG, + (u16)(new_vffullcap / 4)); + max77823_write_word(fuelgauge->i2c, DPACC_REG, + (u16)0x3200); + } else if (new_vffullcap < + (fuelgauge->info.previous_vffullcap * 90 / 100)) { + pr_debug("%s: [Case 3] previous_vffullcap = 0x%04x, NewVfFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_vffullcap, + new_vffullcap); + + new_vffullcap = + (fuelgauge->info.previous_vffullcap * 90) / 100; + + max77823_write_word(fuelgauge->i2c, DQACC_REG, + (u16)(new_vffullcap / 4)); + max77823_write_word(fuelgauge->i2c, DPACC_REG, + (u16)0x3200); + } else { + pr_debug("%s: [Case 4] previous_vffullcap = 0x%04x, NewVfFullCap = 0x%04x\n", + __func__, fuelgauge->info.previous_vffullcap, + new_vffullcap); + is_vffullcap_changed = false; + } + } + + /* delay for register setting (dQacc, dPacc) */ + if (is_vffullcap_changed) + msleep(300); + + fuelgauge->info.previous_vffullcap = + max77823_read_word(fuelgauge->i2c, FULLCAP_NOM_REG); + + if (is_vffullcap_changed) + pr_debug("%s : VfFullCap(0x%04x), dQacc(0x%04x), dPacc(0x%04x)\n", + __func__, + max77823_read_word(fuelgauge->i2c, FULLCAP_NOM_REG), + max77823_read_word(fuelgauge->i2c, DQACC_REG), + max77823_read_word(fuelgauge->i2c, DPACC_REG)); + +} + +void fg_set_full_charged(struct max77823_fuelgauge_data *fuelgauge) +{ + pr_info("[FG_Set_Full] (B) FullCAP(%d), RemCAP(%d)\n", + (max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG)/2), + (max77823_read_word(fuelgauge->i2c, REMCAP_REP_REG)/2)); + + max77823_write_word(fuelgauge->i2c, FULLCAPREP_REG, + (u16)max77823_read_word(fuelgauge->i2c, REMCAP_REP_REG)); + + pr_info("[FG_Set_Full] (A) FullCAP(%d), RemCAP(%d)\n", + (max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG)/2), + (max77823_read_word(fuelgauge->i2c, REMCAP_REP_REG)/2)); +} + +static void display_low_batt_comp_cnt(struct max77823_fuelgauge_data *fuelgauge) +{ + pr_info("Check Array(%s): [%d, %d], [%d, %d], ", + fuelgauge->battery_data->type_str, + fuelgauge->info.low_batt_comp_cnt[0][0], + fuelgauge->info.low_batt_comp_cnt[0][1], + fuelgauge->info.low_batt_comp_cnt[1][0], + fuelgauge->info.low_batt_comp_cnt[1][1]); + pr_info("[%d, %d], [%d, %d], [%d, %d]\n", + fuelgauge->info.low_batt_comp_cnt[2][0], + fuelgauge->info.low_batt_comp_cnt[2][1], + fuelgauge->info.low_batt_comp_cnt[3][0], + fuelgauge->info.low_batt_comp_cnt[3][1], + fuelgauge->info.low_batt_comp_cnt[4][0], + fuelgauge->info.low_batt_comp_cnt[4][1]); +} + +static void add_low_batt_comp_cnt(struct max77823_fuelgauge_data *fuelgauge, + int range, int level) +{ + int i; + int j; + + /* Increase the requested count value, and reset others. */ + fuelgauge->info.low_batt_comp_cnt[range-1][level/2]++; + + for (i = 0; i < LOW_BATT_COMP_RANGE_NUM; i++) { + for (j = 0; j < LOW_BATT_COMP_LEVEL_NUM; j++) { + if (i == range-1 && j == level/2) + continue; + else + fuelgauge->info.low_batt_comp_cnt[i][j] = 0; + } + } +} + +void prevent_early_poweroff(struct max77823_fuelgauge_data *fuelgauge, + int vcell, int *fg_soc) +{ + int soc = 0; + int read_val; + + soc = fg_read_percent(fuelgauge, SOCREP_REG); + + /* No need to write REMCAP_REP in below normal cases */ + if (soc > POWER_OFF_SOC_HIGH_MARGIN || vcell > fuelgauge->battery_data->low_battery_comp_voltage) + return; + + pr_info("%s: soc=%d, vcell=%d\n", __func__, soc, vcell); + + if (vcell > POWER_OFF_VOLTAGE_HIGH_MARGIN) { + read_val = max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + /* FullCAP * 0.013 */ + max77823_write_word(fuelgauge->i2c, REMCAP_REP_REG, + (u16)(read_val * 13 / 1000)); + msleep(200); + *fg_soc = fg_read_percent(fuelgauge, SOCREP_REG); + pr_info("%s: new soc=%d, vcell=%d\n", __func__, *fg_soc, vcell); + } +} + +void reset_low_batt_comp_cnt(struct max77823_fuelgauge_data *fuelgauge) +{ + memset(fuelgauge->info.low_batt_comp_cnt, 0, + sizeof(fuelgauge->info.low_batt_comp_cnt)); +} + +static int check_low_batt_comp_condition( + struct max77823_fuelgauge_data *fuelgauge, + int *nLevel) +{ + int i; + int j; + int ret = 0; + + for (i = 0; i < LOW_BATT_COMP_RANGE_NUM; i++) { + for (j = 0; j < LOW_BATT_COMP_LEVEL_NUM; j++) { + if (fuelgauge->info.low_batt_comp_cnt[i][j] >= + MAX_LOW_BATT_CHECK_CNT) { + display_low_batt_comp_cnt(fuelgauge); + ret = 1; + *nLevel = j*2 + 1; + break; + } + } + } + + return ret; +} + +static int get_low_batt_threshold(struct max77823_fuelgauge_data *fuelgauge, + int range, int nCurrent, int level) +{ + int ret = 0; + + ret = fuelgauge->battery_data->low_battery_table[range][OFFSET] + + (nCurrent * + fuelgauge->battery_data->low_battery_table[range][SLOPE]); + + return ret; +} + +int low_batt_compensation(struct max77823_fuelgauge_data *fuelgauge, + int fg_soc, int fg_vcell, int fg_current) +{ + int fg_avg_current = 0; + int fg_min_current = 0; + int new_level = 0; + int i, table_size; + + /* Not charging, Under low battery comp voltage */ + if (fg_vcell <= fuelgauge->battery_data->low_battery_comp_voltage) { + fg_avg_current = fg_read_avg_current(fuelgauge) / 1000; + fg_min_current = min(fg_avg_current, fg_current); + + table_size = + sizeof(fuelgauge->battery_data->low_battery_table) / + (sizeof(s16)*TABLE_MAX); + + for (i = 1; i < CURRENT_RANGE_MAX_NUM; i++) { + if ((fg_min_current >= fuelgauge->battery_data-> + low_battery_table[i-1][RANGE]) && + (fg_min_current < fuelgauge->battery_data-> + low_battery_table[i][RANGE])) { + if (fg_soc >= 10 && fg_vcell < + get_low_batt_threshold(fuelgauge, + i, fg_min_current, 1)) { + add_low_batt_comp_cnt( + fuelgauge, i, 1); + } else { + reset_low_batt_comp_cnt(fuelgauge); + } + } + } + + if (check_low_batt_comp_condition(fuelgauge, &new_level)) { + fg_low_batt_compensation(fuelgauge, new_level); + reset_low_batt_comp_cnt(fuelgauge); + + /* Do not update soc right after + * low battery compensation + * to prevent from powering-off suddenly + */ + pr_info("%s: SOC is set to %d by low compensation!!\n", + __func__, fg_read_percent(fuelgauge, SOCREP_REG)); + } + } + + /* Prevent power off over 3500mV */ + prevent_early_poweroff(fuelgauge, fg_vcell, &fg_soc); + + return fg_soc; +} + +static bool is_booted_in_low_battery(struct max77823_fuelgauge_data *fuelgauge) +{ + int fg_vcell = max77823_get_vcell(fuelgauge); + int fg_current = fg_read_current(fuelgauge)/1000; + int threshold = 0; + + threshold = 3300000 + (fg_current * 170); + + if (fg_vcell <= threshold) + return true; + else + return false; +} + +static bool fuelgauge_recovery_handler(struct max77823_fuelgauge_data *fuelgauge) +{ + int current_soc; + int avsoc; + int temperature; + + if (fuelgauge->info.soc >= LOW_BATTERY_SOC_REDUCE_UNIT) { + pr_err("%s: Reduce the Reported SOC by 1%%\n", + __func__); + current_soc = fg_read_percent(fuelgauge, SOCREP_REG) / 10; + + if (current_soc) { + pr_info("%s: Returning to Normal discharge path\n", + __func__); + pr_info("%s: Actual SOC(%d) non-zero\n", + __func__, current_soc); + fuelgauge->info.is_low_batt_alarm = false; + } else { + temperature = fg_read_temp(fuelgauge); + avsoc = fg_read_percent(fuelgauge, SOCAV_REG); + + if ((fuelgauge->info.soc > avsoc) || + (temperature < 0)) { + fuelgauge->info.soc -= + LOW_BATTERY_SOC_REDUCE_UNIT; + pr_err("%s: New Reduced RepSOC (%d)\n", + __func__, fuelgauge->info.soc); + } else + pr_info("%s: Waiting for recovery (AvSOC:%d)\n", + __func__, avsoc); + } + } + + return fuelgauge->info.is_low_batt_alarm; +} + +static int get_fuelgauge_soc(struct max77823_fuelgauge_data *fuelgauge) +{ + union power_supply_propval value; + int fg_soc = 0; + int fg_vfsoc; + int fg_vcell; + int fg_current; + int avg_current; + ktime_t current_time; + struct timespec ts; + int fullcap_check_interval; + + if (fuelgauge->info.is_low_batt_alarm) + if (fuelgauge_recovery_handler(fuelgauge)) { + fg_soc = fuelgauge->info.soc; + goto return_soc; + } + +#if defined(ANDROID_ALARM_ACTIVATED) + current_time = alarm_get_elapsed_realtime(); + ts = ktime_to_timespec(current_time); +#else + current_time = ktime_get_boottime(); + ts = ktime_to_timespec(current_time); +#endif + + /* check fullcap range */ + fullcap_check_interval = + (ts.tv_sec - fuelgauge->info.fullcap_check_interval); + if (fullcap_check_interval > + VFFULLCAP_CHECK_INTERVAL) { + pr_debug("%s: check fullcap range (interval:%d)\n", + __func__, fullcap_check_interval); + fg_check_vf_fullcap_range(fuelgauge); + fuelgauge->info.fullcap_check_interval = ts.tv_sec; + } + + fg_soc = fg_read_percent(fuelgauge, SOCREP_REG); + if (fg_soc < 0) { + pr_info("Can't read soc!!!"); + fg_soc = fuelgauge->info.soc; + } + + if (fuelgauge->info.low_batt_boot_flag) { + fg_soc = 0; + + if (fuelgauge->pdata->check_cable_callback && + fuelgauge->pdata->check_cable_callback() != + POWER_SUPPLY_TYPE_BATTERY && + !is_booted_in_low_battery(fuelgauge)) { + fg_adjust_capacity(fuelgauge); + fuelgauge->info.low_batt_boot_flag = 0; + } + + if (fuelgauge->pdata->check_cable_callback && + fuelgauge->pdata->check_cable_callback() == + POWER_SUPPLY_TYPE_BATTERY) + fuelgauge->info.low_batt_boot_flag = 0; + } + + fg_vcell = max77823_get_vcell(fuelgauge); + fg_current = fg_read_current(fuelgauge)/1000; + avg_current = fg_read_avg_current(fuelgauge)/1000; + fg_vfsoc = fg_read_vfsoc(fuelgauge); + + value.intval = max77823_get_status(fuelgauge); + + /* Algorithm for reducing time to fully charged (from MAXIM) */ + if (value.intval != POWER_SUPPLY_STATUS_DISCHARGING && + value.intval != POWER_SUPPLY_STATUS_FULL && + fuelgauge->cable_type != POWER_SUPPLY_TYPE_USB && + /* Skip when first check after boot up */ + !fuelgauge->info.is_first_check && + (fg_vfsoc > VFSOC_FOR_FULLCAP_LEARNING && + (fg_current > LOW_CURRENT_FOR_FULLCAP_LEARNING && + fg_current < HIGH_CURRENT_FOR_FULLCAP_LEARNING) && + (avg_current > LOW_AVGCURRENT_FOR_FULLCAP_LEARNING && + avg_current < HIGH_AVGCURRENT_FOR_FULLCAP_LEARNING))) { + + if (fuelgauge->info.full_check_flag == 2) { + pr_info("%s: force fully charged SOC !! (%d)", + __func__, fuelgauge->info.full_check_flag); + fg_set_full_charged(fuelgauge); + fg_soc = fg_read_percent(fuelgauge, SOCREP_REG); + } else if (fuelgauge->info.full_check_flag < 2) + pr_info("%s: full_check_flag (%d)", + __func__, fuelgauge->info.full_check_flag); + + /* prevent overflow */ + if (fuelgauge->info.full_check_flag++ > 10000) + fuelgauge->info.full_check_flag = 3; + } else + fuelgauge->info.full_check_flag = 0; + + /* Checks vcell level and tries to compensate SOC if needed.*/ + /* If jig cable is connected, then skip low batt compensation check. */ + if (fuelgauge->pdata->check_jig_status && + !fuelgauge->pdata->check_jig_status() && + value.intval == POWER_SUPPLY_STATUS_DISCHARGING) + fg_soc = low_batt_compensation( + fuelgauge, fg_soc, fg_vcell, fg_current); + + if (fuelgauge->info.is_first_check) + fuelgauge->info.is_first_check = false; + + fuelgauge->info.soc = fg_soc; + +return_soc: + pr_debug("%s: soc(%d), low_batt_alarm(%d)\n", + __func__, fuelgauge->info.soc, + fuelgauge->info.is_low_batt_alarm); + + return fg_soc; +} + +static void full_comp_work_handler(struct work_struct *work) +{ + struct max77823_fuelgauge_info *fg_info = + container_of(work, struct max77823_fuelgauge_info, full_comp_work.work); + struct max77823_fuelgauge_data *fuelgauge = + container_of(fg_info, struct max77823_fuelgauge_data, info); + int avg_current; + union power_supply_propval value; + + avg_current = fg_read_avg_current(fuelgauge)/1000; + psy_get_prop(fuelgauge, PS_BATT, POWER_SUPPLY_PROP_STATUS, &value); + + if (avg_current >= 25) { + cancel_delayed_work(&fuelgauge->info.full_comp_work); + schedule_delayed_work(&fuelgauge->info.full_comp_work, 100); + } else { + pr_info("%s: full charge compensation start (avg_current %d)\n", + __func__, avg_current); + fg_fullcharged_compensation(fuelgauge, + (int)(value.intval == + POWER_SUPPLY_STATUS_FULL), false); + } +} + +static irqreturn_t max77823_jig_irq_thread(int irq, void *irq_data) +{ + struct max77823_fuelgauge_data *fuelgauge = irq_data; + + if (fuelgauge->pdata->check_jig_status && + fuelgauge->pdata->check_jig_status()) + fg_reset_capacity_by_jig_connection(fuelgauge); + else + pr_info("%s: jig removed\n", __func__); + return IRQ_HANDLED; +} + +bool max77823_fg_init(struct max77823_fuelgauge_data *fuelgauge) +{ + ktime_t current_time; + struct timespec ts; + int ret; + int vempty; + +#if defined(ANDROID_ALARM_ACTIVATED) + current_time = alarm_get_elapsed_realtime(); + ts = ktime_to_timespec(current_time); +#else + current_time = ktime_get_boottime(); + ts = ktime_to_timespec(current_time); +#endif + + fuelgauge->info.fullcap_check_interval = ts.tv_sec; + + fuelgauge->info.is_low_batt_alarm = false; + fuelgauge->info.is_first_check = true; + + /* Init parameters to prevent wrong compensation. */ + fuelgauge->info.previous_fullcap = + max77823_read_word(fuelgauge->i2c, FULLCAPREP_REG); + fuelgauge->info.previous_vffullcap = + max77823_read_word(fuelgauge->i2c, FULLCAP_NOM_REG); + + if (fuelgauge->pdata->check_cable_callback && + (fuelgauge->pdata->check_cable_callback() != + POWER_SUPPLY_TYPE_BATTERY) && + is_booted_in_low_battery(fuelgauge)) + fuelgauge->info.low_batt_boot_flag = 1; + + if (fuelgauge->pdata->check_jig_status && + fuelgauge->pdata->check_jig_status()) + fg_reset_capacity_by_jig_connection(fuelgauge); + else { + if (fuelgauge->pdata->jig_irq) { + int ret; + ret = request_threaded_irq(fuelgauge->pdata->jig_irq, + NULL, max77823_jig_irq_thread, + fuelgauge->pdata->jig_irq_attr, + "jig-irq", fuelgauge); + if (ret) { + pr_info("%s: Failed to Request IRQ\n", + __func__); + } + } + } + + INIT_DELAYED_WORK(&fuelgauge->info.full_comp_work, + full_comp_work_handler); + + max77823_write_word(fuelgauge->i2c, MAX77823_REG_CONFIG, + (fuelgauge->pdata->thermal_source != SEC_BATTERY_THERMAL_SOURCE_FG) ? 0x2154 : 0x2254); + + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TGAIN, (u16)fuelgauge->pdata->tgain); + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TOFF, (u16)fuelgauge->pdata->toff); + max77823_write_word(fuelgauge->i2c, MAX77823_REG_TCURVE, (u16)fuelgauge->pdata->tcurve); + + ret = max77823_read_word(fuelgauge->i2c, MAX77823_REG_STATUS); + if ((ret < 0) || !(ret & 2)) + return true; + + /* Power on reset initialization needed */ + fg_reset_capacity_by_jig_connection(fuelgauge); + vempty = fuelgauge->pdata->empty_detect_voltage / 10; + vempty <<= 7; + vempty |= (fuelgauge->pdata->empty_recovery_voltage / 40) & 0x7f; + max77823_write_word(fuelgauge->i2c, MAX77823_V_EMPTY, vempty); + fg_reset_soc(fuelgauge); + + /* Clear POR condition */ + max77823_write_word(fuelgauge->i2c, MAX77823_REG_STATUS, ret & ~2); + return true; +} + +bool max77823_fg_fuelalert_init(struct max77823_fuelgauge_data *fuelgauge, + int soc) +{ + if (fg_alert_init(fuelgauge, soc) >= 0) + return true; + else + return false; +} + +bool max77823_fg_is_fuelalerted(struct max77823_fuelgauge_data *fuelgauge) +{ + if (fg_check_status_reg(fuelgauge) > 0) + return true; + else + return false; +} + +bool max77823_fg_fuelalert_process(void *irq_data, bool is_fuel_alerted) +{ + struct max77823_fuelgauge_data *fuelgauge = + (struct max77823_fuelgauge_data *)irq_data; + union power_supply_propval value; + int overcurrent_limit_in_soc; + int current_soc = fg_read_percent(fuelgauge, SOCREP_REG); + + psy_get_prop(fuelgauge, PS_BATT, POWER_SUPPLY_PROP_STATUS, &value); + if (value.intval == POWER_SUPPLY_STATUS_CHARGING) + return true; + + if (fuelgauge->info.soc <= STABLE_LOW_BATTERY_DIFF) + overcurrent_limit_in_soc = STABLE_LOW_BATTERY_DIFF_LOWBATT; + else + overcurrent_limit_in_soc = STABLE_LOW_BATTERY_DIFF; + + if (((int)fuelgauge->info.soc - current_soc) > + overcurrent_limit_in_soc) { + pr_info("%s: Abnormal Current Consumption jump by %d units\n", + __func__, (((int)fuelgauge->info.soc - current_soc))); + pr_info("%s: Last Reported SOC (%d).\n", + __func__, fuelgauge->info.soc); + + fuelgauge->info.is_low_batt_alarm = true; + + if (fuelgauge->info.soc >= + LOW_BATTERY_SOC_REDUCE_UNIT) + return true; + } + + if (value.intval == + POWER_SUPPLY_STATUS_DISCHARGING) { + pr_err("Set battery level as 0, power off.\n"); + fuelgauge->info.soc = 0; + value.intval = 0; + psy_set_prop(fuelgauge, PS_BATT, POWER_SUPPLY_PROP_CAPACITY, + &value); + } + + return true; +} + +bool max77823_fg_full_charged(struct max77823_fuelgauge_data *fuelgauge) +{ + union power_supply_propval value; + + psy_get_prop(fuelgauge, PS_BATT, POWER_SUPPLY_PROP_STATUS, &value); + + /* full charge compensation algorithm by MAXIM */ + fg_fullcharged_compensation(fuelgauge, + (int)(value.intval == POWER_SUPPLY_STATUS_FULL), true); + + cancel_delayed_work(&fuelgauge->info.full_comp_work); + schedule_delayed_work(&fuelgauge->info.full_comp_work, 100); + + return false; +} +#endif + +bool max77823_fg_reset(struct max77823_fuelgauge_data *fuelgauge) +{ + if (!fg_reset_soc(fuelgauge)) + return true; + else + return false; +} + +static void max77823_fg_get_scaled_capacity( + struct max77823_fuelgauge_data *fuelgauge, + union power_supply_propval *val) +{ + val->intval = (val->intval < fuelgauge->pdata->capacity_min) ? + 0 : ((val->intval - fuelgauge->pdata->capacity_min) * 1000 / + (fuelgauge->capacity_max - fuelgauge->pdata->capacity_min)); + + pr_debug("%s: scaled capacity (%d.%d)\n", + __func__, val->intval/10, val->intval%10); +} + +/* capacity is integer */ +static void max77823_fg_get_atomic_capacity( + struct max77823_fuelgauge_data *fuelgauge, + union power_supply_propval *val) +{ + if (fuelgauge->pdata->capacity_calculation_type & + SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC) { + if (fuelgauge->capacity_old < val->intval) + val->intval = fuelgauge->capacity_old + 1; + else if (fuelgauge->capacity_old > val->intval) + val->intval = fuelgauge->capacity_old - 1; + } + + /* keep SOC stable in abnormal status */ + if (fuelgauge->pdata->capacity_calculation_type & + SEC_FUELGAUGE_CAPACITY_TYPE_SKIP_ABNORMAL) { + pr_debug("%s:is_charging=%d cable_type=%d\n", __func__, fuelgauge->is_charging, fuelgauge->cable_type); + if (!fuelgauge->is_charging && + fuelgauge->capacity_old < val->intval) { + pr_err("%s: capacity (old %d : new %d)\n", + __func__, fuelgauge->capacity_old, val->intval); + val->intval = fuelgauge->capacity_old; + } + } + + /* updated old capacity */ + fuelgauge->capacity_old = val->intval; +} + +static int max77823_fg_calculate_dynamic_scale( + struct max77823_fuelgauge_data *fuelgauge) +{ + union power_supply_propval raw_soc_val; + +#ifdef CONFIG_FUELGAUGE_MAX77823_VOLTAGE_TRACKING + raw_soc_val.intval = max77823_get_soc(fuelgauge) / 10; +#else + raw_soc_val.intval = fg_read_percent(fuelgauge, SOCREP_REG); +#endif + + if (raw_soc_val.intval < + fuelgauge->pdata->capacity_max - + fuelgauge->pdata->capacity_max_margin) { + fuelgauge->capacity_max = + fuelgauge->pdata->capacity_max - + fuelgauge->pdata->capacity_max_margin; + pr_debug("%s: capacity_max (%d)", __func__, + fuelgauge->capacity_max); + } else { + fuelgauge->capacity_max = + (raw_soc_val.intval > + fuelgauge->pdata->capacity_max + + fuelgauge->pdata->capacity_max_margin) ? + (fuelgauge->pdata->capacity_max + + fuelgauge->pdata->capacity_max_margin) : + raw_soc_val.intval; + pr_debug("%s: raw soc (%d)", __func__, + fuelgauge->capacity_max); + } + + fuelgauge->capacity_max = + (fuelgauge->capacity_max * 99 / 100); + + /* update capacity_old for sec_fg_get_atomic_capacity algorithm */ + fuelgauge->capacity_old = 100; + + pr_info("%s: %d is used for capacity_max\n", + __func__, fuelgauge->capacity_max); + + return fuelgauge->capacity_max; +} + +static int max77823_fg_property_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + return 1; + default: + break; + } + + return 0; +} + + +#ifdef CONFIG_FUELGAUGE_MAX77823_VOLTAGE_TRACKING +static int max77823_fg_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret; + struct max77823_fuelgauge_data *fuelgauge = + container_of(psy, struct max77823_fuelgauge_data, psy_fg); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + ret = max77823_get_status(fuelgauge); + if (ret >= 0) + val->intval = ret; + break; + case POWER_SUPPLY_PROP_CHARGE_FULL: + val->intval = 0; + ret = max77823_read_word(fuelgauge->i2c, FULLCAP_REG); + if (ret < 0) + return ret; + val->intval = ret * 1000 / 2; + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = fuelgauge->cable_type; + pr_info("%s:is_charging=%d cable_type=%d\n", __func__, fuelgauge->is_charging, fuelgauge->cable_type); + break; + /* Cell voltage (VCELL, mV) */ + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = max77823_get_vcell(fuelgauge); + break; + /* Additional Voltage Information (uV) */ + case POWER_SUPPLY_PROP_VOLTAGE_AVG: + switch (val->intval) { + case SEC_BATTEY_VOLTAGE_AVERAGE: + val->intval = max77823_get_avgvcell(fuelgauge); + break; + case SEC_BATTEY_VOLTAGE_OCV: + val->intval = max77823_get_vfocv(fuelgauge); + break; + } + break; + /* Current (mA) */ + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = 0; + break; + /* Average Current (mA) */ + case POWER_SUPPLY_PROP_CURRENT_AVG: + val->intval = 0; + break; + /* SOC (%) */ + case POWER_SUPPLY_PROP_CAPACITY: + if (val->intval == SEC_FUELGAUGE_CAPACITY_TYPE_RAW) { + val->intval = max77823_get_soc(fuelgauge); + } else { + val->intval = max77823_get_soc(fuelgauge) / 10; + + if (fuelgauge->pdata->capacity_calculation_type & + (SEC_FUELGAUGE_CAPACITY_TYPE_SCALE | + SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE)) + max77823_fg_get_scaled_capacity(fuelgauge, val); + + /* capacity should be between 0% and 100% + * (0.1% degree) + */ + if (val->intval > 1000) + val->intval = 1000; + if (val->intval < 0) + val->intval = 0; + + /* get only integer part */ + val->intval /= 10; + + /* check whether doing the wake_unlock */ + if ((val->intval > fuelgauge->pdata->fuel_alert_soc) && + fuelgauge->is_fuel_alerted) { + wake_unlock(&fuelgauge->fuel_alert_wake_lock); + max77823_fg_fuelalert_init(fuelgauge, + fuelgauge->pdata->fuel_alert_soc); + } + + /* (Only for atomic capacity) + * In initial time, capacity_old is 0. + * and in resume from sleep, + * capacity_old is too different from actual soc. + * should update capacity_old + * by val->intval in booting or resume. + */ + if (fuelgauge->initial_update_of_soc) { + /* updated old capacity */ + fuelgauge->capacity_old = val->intval; + fuelgauge->initial_update_of_soc = false; + break; + } + + if (fuelgauge->pdata->capacity_calculation_type & + (SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC | + SEC_FUELGAUGE_CAPACITY_TYPE_SKIP_ABNORMAL)) + max77823_fg_get_atomic_capacity(fuelgauge, val); + } + break; + /* Battery Temperature */ + case POWER_SUPPLY_PROP_TEMP: + /* Target Temperature */ + case POWER_SUPPLY_PROP_TEMP_AMBIENT: + val->intval = max77823_get_temperature(fuelgauge); + break; + default: + return false; + } + return true; +} + + +static int max77823_fg_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct max77823_fuelgauge_data *fuelgauge = + container_of(psy, struct max77823_fuelgauge_data, psy_fg); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (val->intval == POWER_SUPPLY_STATUS_FULL) + max77823_fg_full_charged(fuelgauge); + break; + case POWER_SUPPLY_PROP_CHARGE_FULL: + if (val->intval == POWER_SUPPLY_TYPE_BATTERY) { + if (fuelgauge->pdata->capacity_calculation_type & + SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE) + max77823_fg_calculate_dynamic_scale(fuelgauge); + } + break; + case POWER_SUPPLY_PROP_ONLINE: + fuelgauge->cable_type = val->intval; + if (val->intval == POWER_SUPPLY_TYPE_BATTERY) + fuelgauge->is_charging = false; + else + fuelgauge->is_charging = true; + pr_info("%s:is_charging=%d cable_type=%d\n", __func__, fuelgauge->is_charging, fuelgauge->cable_type); + break; + /* Battery Temperature */ + case POWER_SUPPLY_PROP_CAPACITY: + if (val->intval == SEC_FUELGAUGE_CAPACITY_TYPE_RESET) { + fuelgauge->initial_update_of_soc = true; + if (!max77823_fg_reset(fuelgauge)) + return -EINVAL; + else + break; + } + /* Battery Temperature */ + case POWER_SUPPLY_PROP_TEMP: + /* Target Temperature */ + case POWER_SUPPLY_PROP_TEMP_AMBIENT: + max77823_set_temperature(fuelgauge, val->intval); + break; + default: + return false; + } + return true; +} +#endif + +#ifdef CONFIG_FUELGAUGE_MAX77823_COULOMB_COUNTING +static int max77823_fg_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret; + struct max77823_fuelgauge_data *fuelgauge = psy->drv_data; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + ret = max77823_get_status(fuelgauge); + if (ret >= 0) + val->intval = ret; + break; + case POWER_SUPPLY_PROP_CHARGE_FULL: + val->intval = 0; + ret = max77823_read_word(fuelgauge->i2c, FULLCAP_REG); + if (ret < 0) + return ret; + val->intval = ret * 1000 / 2; + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = fuelgauge->cable_type; + pr_info("%s:is_charging=%d cable_type=%d\n", __func__, fuelgauge->is_charging, fuelgauge->cable_type); + break; + /* Cell voltage (VCELL, mV) */ + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = max77823_get_vcell(fuelgauge); + break; + /* Additional Voltage Information (mV) */ + case POWER_SUPPLY_PROP_VOLTAGE_AVG: + switch (val->intval) { + case SEC_BATTEY_VOLTAGE_OCV: + val->intval = max77823_get_vfocv(fuelgauge); + break; + case SEC_BATTEY_VOLTAGE_AVERAGE: + default: + val->intval = max77823_get_avgvcell(fuelgauge); + break; + } + break; + /* Current */ + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = fg_read_current(fuelgauge); + break; + /* Average Current */ + case POWER_SUPPLY_PROP_CURRENT_AVG: + val->intval = fg_read_avg_current(fuelgauge); + break; + + case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN: + val->intval = fg_read_power(fuelgauge, DESIGNCAP_REG); + break; + case POWER_SUPPLY_PROP_ENERGY_FULL: + val->intval = fg_read_power(fuelgauge, FULLCAPREP_REG); + break; + case POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN: + val->intval = fg_read_power(fuelgauge, REMCAP_MIX_REG); /* nothing to do with empty, stole for sec_battery */ + break; + case POWER_SUPPLY_PROP_ENERGY_EMPTY: + val->intval = 0; + break; + + case POWER_SUPPLY_PROP_ENERGY_NOW: + val->intval = fg_read_power(fuelgauge, REMCAP_REP_REG); + break; + case POWER_SUPPLY_PROP_ENERGY_AVG: + val->intval = fg_read_power(fuelgauge, REMCAP_AV_REG); + break; + + /* SOC (%) */ + case POWER_SUPPLY_PROP_CAPACITY: + if (val->intval == SEC_FUELGAUGE_CAPACITY_TYPE_RAW) { + val->intval = fg_read_percent(fuelgauge, SOCREP_REG); + } else { + val->intval = get_fuelgauge_soc(fuelgauge); + + if (fuelgauge->pdata->capacity_calculation_type & + (SEC_FUELGAUGE_CAPACITY_TYPE_SCALE | + SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE)) + max77823_fg_get_scaled_capacity(fuelgauge, val); + + /* capacity should be between 0% and 100% + * (0.1% degree) + */ + if (val->intval > 1000) + val->intval = 1000; + if (val->intval < 0) + val->intval = 0; + + /* get only integer part */ + val->intval /= 10; + + /* check whether doing the wake_unlock */ + if ((val->intval > fuelgauge->pdata->fuel_alert_soc) && + fuelgauge->is_fuel_alerted) { + wake_unlock(&fuelgauge->fuel_alert_wake_lock); + max77823_fg_fuelalert_init(fuelgauge, + fuelgauge->pdata->fuel_alert_soc); + } + + /* (Only for atomic capacity) + * In initial time, capacity_old is 0. + * and in resume from sleep, + * capacity_old is too different from actual soc. + * should update capacity_old + * by val->intval in booting or resume. + */ + if (fuelgauge->initial_update_of_soc) { + /* updated old capacity */ + fuelgauge->capacity_old = val->intval; + fuelgauge->initial_update_of_soc = false; + break; + } + + if (fuelgauge->pdata->capacity_calculation_type & + (SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC | + SEC_FUELGAUGE_CAPACITY_TYPE_SKIP_ABNORMAL)) + max77823_fg_get_atomic_capacity(fuelgauge, val); + } + break; + /* Battery Temperature */ + case POWER_SUPPLY_PROP_TEMP: + /* Target Temperature */ + case POWER_SUPPLY_PROP_TEMP_AMBIENT: + val->intval = fg_read_temp(fuelgauge); + break; + default: + return -EINVAL; + } + return 0; +} + +static int max77823_fg_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct max77823_fuelgauge_data *fuelgauge = psy->drv_data; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (val->intval == POWER_SUPPLY_STATUS_FULL) + max77823_fg_full_charged(fuelgauge); + break; + case POWER_SUPPLY_PROP_CHARGE_FULL: + if (val->intval == POWER_SUPPLY_TYPE_BATTERY) { + if (fuelgauge->pdata->capacity_calculation_type & + SEC_FUELGAUGE_CAPACITY_TYPE_DYNAMIC_SCALE) + max77823_fg_calculate_dynamic_scale(fuelgauge); + } + break; + case POWER_SUPPLY_PROP_ONLINE: + fuelgauge->cable_type = val->intval; + if (val->intval == POWER_SUPPLY_TYPE_BATTERY) { + fuelgauge->is_charging = false; + } else { + fuelgauge->is_charging = true; + + if (fuelgauge->info.is_low_batt_alarm) { + pr_info("%s: Reset low_batt_alarm\n", + __func__); + fuelgauge->info.is_low_batt_alarm = false; + } + + reset_low_batt_comp_cnt(fuelgauge); + } + pr_info("%s:is_charging=%d cable_type=%d\n", __func__, fuelgauge->is_charging, fuelgauge->cable_type); + break; + /* Battery Temperature */ + case POWER_SUPPLY_PROP_CAPACITY: + if (val->intval == SEC_FUELGAUGE_CAPACITY_TYPE_RESET) { + fuelgauge->initial_update_of_soc = true; + if (!max77823_fg_reset(fuelgauge)) + return -EINVAL; + else + break; + } + case POWER_SUPPLY_PROP_TEMP: + /* Target Temperature */ + case POWER_SUPPLY_PROP_TEMP_AMBIENT: + fg_write_temp(fuelgauge, val->intval); + break; + case POWER_SUPPLY_PROP_ENERGY_NOW: + fg_reset_capacity_by_jig_connection(fuelgauge); + break; + default: + return -EINVAL; + } + return 0; +} +#endif + +static void max77823_fg_isr_work(struct work_struct *work) +{ + struct max77823_fuelgauge_data *fuelgauge = + container_of(work, struct max77823_fuelgauge_data, isr_work.work); + + /* process for fuel gauge chip */ + max77823_fg_fuelalert_process(fuelgauge, fuelgauge->is_fuel_alerted); + + /* process for others */ + if (fuelgauge->pdata->fuelalert_process != NULL) + fuelgauge->pdata->fuelalert_process(fuelgauge->is_fuel_alerted); +} + +static irqreturn_t max77823_fg_irq_thread(int irq, void *irq_data) +{ + struct max77823_fuelgauge_data *fuelgauge = irq_data; + bool fuel_alerted; + + if (fuelgauge->pdata->fuel_alert_soc >= 0) { + fuel_alerted = + max77823_fg_is_fuelalerted(fuelgauge); + + pr_info("%s: Fuel-alert %salerted!\n", + __func__, fuel_alerted ? "" : "NOT "); + + fg_test_print(fuelgauge); + + if (fuel_alerted == fuelgauge->is_fuel_alerted) { + if (!fuelgauge->pdata->repeated_fuelalert) { + pr_debug("%s: Fuel-alert Repeated (%d)\n", + __func__, fuelgauge->is_fuel_alerted); + return IRQ_HANDLED; + } + } + + if (fuel_alerted) + wake_lock(&fuelgauge->fuel_alert_wake_lock); + else + wake_unlock(&fuelgauge->fuel_alert_wake_lock); + + schedule_delayed_work(&fuelgauge->isr_work, 0); + + fuelgauge->is_fuel_alerted = fuel_alerted; + } + + return IRQ_HANDLED; +} + +static int max77823_fuelgauge_debugfs_show(struct seq_file *s, void *data) +{ + struct max77823_fuelgauge_data *fuelgauge = s->private; + int reg = 0; + u16 d[16]; + + seq_printf(s, "MAX77823 FUELGAUGE IC :\n"); + seq_printf(s, "===================\n"); + while (reg < 0x100) { + int i; + int base = reg; + for (i = 0; i < 0x10; i++) + d[i] = max77823_read_word(fuelgauge->i2c, reg++); + + seq_printf(s, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x " + "%04x %04x %04x %04x %04x %04x %04x %04x\n", + base, d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], + d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15]); + if (reg == 0x50) + reg = 0xb0; + else if (reg == 0xc0) + reg = 0xd0; + else if (reg == 0xe0) + reg = 0xf0; + } + return 0; +} + +static int max77823_fuelgauge_debugfs_open(struct inode *inode, struct file *file) +{ + return single_open(file, max77823_fuelgauge_debugfs_show, inode->i_private); +} + +static const struct file_operations max77823_fuelgauge_debugfs_fops = { + .open = max77823_fuelgauge_debugfs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +#ifdef CONFIG_OF +#define TFRAC_BITS 11 +static int calc_temp(int ain, int toff, int tgain, int tcurve) +{ + int x1; + int x = (toff << (TFRAC_BITS - 7)) + ((ain * tgain) >> (16 + 6 - TFRAC_BITS)); + s64 t64; + int t; + + x1 = x - (20 << TFRAC_BITS); + t64 = (tcurve * x1); + t = (t64 * x1) >> (10 + TFRAC_BITS + TFRAC_BITS - TFRAC_BITS); + if (x1 >= 0) + t = x + t; + else + t = x - t; + return t; +} + +struct best_s { + u64 sum; + int tcurve; + int toff; + int tgain; +}; + +static u64 calc_error(int tcurve, int tgain, int toff, u32 *pairs, int length) +{ + u64 sum = 0; + int i; + + /* calculate sum of error**2 */ + for (i = 0; i < length; i += 2) { + int temp = pairs[i] << (TFRAC_BITS - 8); + int ain = pairs[i + 1]; + int c = calc_temp(ain, toff, tgain, tcurve); + int err = temp - c; + u64 lerr; + + if (err < 0) + err = -err; + lerr = err; + lerr = lerr * err; + sum += lerr; + } +// pr_info("%s: tcurve=%d, tgain=%d, toff=%d, sum=%lld\n", __func__, tcurve, tgain, toff, sum); + return sum; +} + +static void get_best_toff(struct best_s *best, int tgain, u32 *pairs, int length) +{ + int toff1 = best->toff; + int toff = toff1; + int best_toff = best->toff; + u64 best_sum = 0xffffffffffffffffL; + int change = -32; + + while (1) { + u64 sum = calc_error(best->tcurve, tgain, toff, pairs, length); + + if (best_sum >= sum) { + best_sum = sum; + best_toff = toff; + } else { + toff = best_toff; + if (change == -1) { + change = 16; + } else { + change >>= 1; + if (!change) + break; + } + } + toff += change; + if (change > 0) { + if (toff >= 32768) { + toff = 32767; + change = toff - best_toff; + if (!change) + break; + } + } else { + if (toff < -32768) { + toff = -32768; + change = toff - best_toff; + if (!change) + change = 16; + } + } + } + + if (best->sum >= best_sum) { + best->sum = best_sum; + best->toff = best_toff; + best->tgain = tgain; + pr_info("%s: tcurve=%d, tgain=%d, toff=%d, sum=%lld\n", + __func__, best->tcurve, tgain, best_toff, best_sum); + } +} + +static void get_best_tgain(struct best_s *best, u32 *pairs, int length) +{ + int tgain = best->tgain; + int change = -32; + + while (1) { + get_best_toff(best, tgain, pairs, length); + + if (tgain != best->tgain) { + tgain = best->tgain; + if (change == -1) { + change = 16; + } else { + change >>= 1; + if (!change) + break; + } + } + tgain += change; + if (change > 0) { + if (tgain >= 32768) { + tgain = 32767; + change = tgain - best->tgain; + if (!change) + break; + } + } else { + if (tgain < -32768) { + tgain = -32768; + change = tgain - best->tgain; + if (!change) + change = 16; + } + } + } +} + +static void calibrate_temp(struct sec_battery_platform_data *pdata, u32 *pairs, int length) +{ + int i; + struct best_s best; + int tcurve = 0; + int sx = 0; + int sy = 0; + s64 sxx = 0; + s64 sxy = 0; + s64 t; + s64 s; + int d; + int len = length >> 1; + + for (i = 0; i < length; i += 2) { + int y = pairs[i]; + int x = pairs[i + 1]; + + y = (y << 8) / 10; + sx += x; + sy += y; + sxx += x * x; + sxy += x * y; + pairs[i] = y; + } + t = sx; + t *= sy; + s = (sxy * len - t); /* 24 fraction bits */ + t = sx; + t *= sx; + d = (sxx * len - t) >> 16; /* 16 fraction bits */ + s = div64_s64(s, d); /* 8 fraction bits */ + best.tcurve = 0; + best.tgain = s >> 2; /* units 1/64, not 1/256*/ + /* toff is units 1/128 not 1/256 */ + best.toff = ((sy - (int)((best.tgain * (s64)sx) >> (6 + 16 - 8))) / len) >> 1; + best.sum = calc_error(best.tcurve, best.tgain, best.toff, pairs, length); + pr_info("%s: tcurve=%d, tgain=%d, toff=%d, sum=%lld\n", + __func__, best.tcurve, best.tgain, best.toff, best.sum); + + for (tcurve = 0; tcurve < 256; tcurve++) { + struct best_s b; + + b.tcurve = tcurve; + b.tgain = best.tgain; + b.toff = best.toff; + b.sum = 0xffffffffffffffffL; + get_best_tgain(&b, pairs, length); + + if (best.sum < b.sum) + break; + best = b; + pr_info("%s: tcurve=%d, tgain=%d, toff=%d, sum=%lld\n", + __func__, best.tcurve, best.tgain, best.toff, best.sum); + } + pdata->tcurve = best.tcurve; + pdata->tgain = best.tgain; + pdata->toff = best.toff; + + for (i = 0; i < length; i += 2) { + unsigned temp = (pairs[i] * 10) >> 8; + unsigned ain = pairs[i + 1]; + unsigned c = calc_temp(ain, best.toff, best.tgain, best.tcurve); + + pr_info("%s: %d, 0x%x, %d\n", __func__, temp, ain, + (c * 10) >> TFRAC_BITS); + } +} + +struct dt_data { + const char* const field; + int offset; +}; + +#define BOFFSET(field) offsetof(struct sec_battery_platform_data, field) +const struct dt_data dt_fields[] = { + {"fuelgauge,capacity_max", BOFFSET(capacity_max) }, + {"fuelgauge,capacity_max_margin", BOFFSET(capacity_max_margin) }, + {"fuelgauge,capacity_min", BOFFSET(capacity_min) }, + {"fuelgauge,capacity_calculation_type", BOFFSET(capacity_calculation_type) }, + {"fuelgauge,fuel_alert_soc", BOFFSET(fuel_alert_soc) }, + {"empty_detect_voltage", BOFFSET(empty_detect_voltage) }, + {"empty_recovery_voltage", BOFFSET(empty_recovery_voltage) }, + {NULL, 0} +}; +static int max77823_fuelgauge_parse_dt( + struct max77823_fuelgauge_data *fuelgauge, + struct device_node *np) +{ + struct sec_battery_platform_data *pdata = fuelgauge->pdata; + int ret; + const struct dt_data *dtd = dt_fields; + struct property *prop; + int length; + u32 pairs[64]; + + /* reset, irq gpio info */ + if (np == NULL) { + pr_err("%s np NULL\n", __func__); + return -1; + } + + /* Overwrite battery capacity if provided (default is 2600mAh) */ + ret = of_property_read_u32(np, "fuelgauge,capacity_mAh", &pairs[0]); + if (ret >= 0) { + /* Cap register = X mAh * 10 mohms / 5 uVh*/ + fuelgauge->battery_data->Capacity = pairs[0] * 2; + pr_info("%s: fuelgauge,capacity_mAh=%d\n", __func__, pairs[0]); + } + + while (dtd->field) { + u32 *p = (u32 *)(((void *)pdata) + dtd->offset); + ret = of_property_read_u32(np, dtd->field, p); + if (ret < 0) + pr_err("%s: error reading %s(%d)\n", __func__, + dtd->field, ret); + else + pr_info("%s: %s=%d\n", __func__, dtd->field, *p); + dtd++; + } + pdata->repeated_fuelalert = of_property_read_bool(np, + "fuelgauge,repeated_fuelalert"); + pr_info("%s: fg_irq: %d, repeated_fuelalert: %d\n", + __func__, pdata->fg_irq, + pdata->repeated_fuelalert); + + prop = of_find_property(np, "temp-disabled", &length); + pdata->temp_disabled = prop ? 1 : 0; + + ret = of_property_read_u32_array(np, "temp-calibration", pairs, 3); + if (ret >= 0) { + pdata->tcurve = pairs[0]; + pdata->tgain = pairs[1]; + pdata->toff = pairs[2]; + pr_info("%s: tcurve:%d, tgain:%d toff:%d\n", + __func__, pdata->tcurve, pdata->tgain, pdata->toff); + return 0; + } + pr_err("%s: error reading temp-calibration %d\n", __func__, ret); + + prop = of_find_property(np, "temp-calibration-data", &length); + if (!prop) { + pr_err("%s: error reading temp-calibration-data\n", __func__); + return 0; + } + length >>= 2; + length &= ~1; + if (length > ARRAY_SIZE(pairs)) + length = ARRAY_SIZE(pairs); + ret = of_property_read_u32_array(np, "temp-calibration-data", pairs, length); + if (ret < 0) { + pr_err("%s: error reading temp-calibration-data %d\n", __func__, ret); + return 0; + } + calibrate_temp(pdata, pairs, length); + return 0; +} +#endif + +const struct power_supply_desc psy_fg_desc = { + .name = "max77823-fuelgauge", + .type = POWER_SUPPLY_TYPE_UNKNOWN, + .properties = max77823_fuelgauge_props, + .num_properties = ARRAY_SIZE(max77823_fuelgauge_props), + .get_property = max77823_fg_get_property, + .set_property = max77823_fg_set_property, + .property_is_writeable = max77823_fg_property_is_writeable, +}; + +struct power_supply_config psy_fg_config = { +}; + +static int max77823_fuelgauge_probe(struct platform_device *pdev) +{ + struct max77823_dev *max77823 = dev_get_drvdata(pdev->dev.parent); + struct max77823_platform_data *pdata = dev_get_platdata(max77823->dev); + struct max77823_fuelgauge_data *fuelgauge; + int ret = 0; + union power_supply_propval raw_soc_val; + + pr_info("%s: MAX77823 Fuelgauge Driver Loading\n", __func__); + + fuelgauge = kzalloc(sizeof(*fuelgauge), GFP_KERNEL); + if (!fuelgauge) + return -ENOMEM; + + pdata->fuelgauge_data = kzalloc(sizeof(sec_battery_platform_data_t), GFP_KERNEL); + if (!pdata->fuelgauge_data) { + kfree(fuelgauge); + return -ENOMEM; + } + + mutex_init(&fuelgauge->fg_lock); + + fuelgauge->dev = &pdev->dev; + fuelgauge->pdata = pdata->fuelgauge_data; + fuelgauge->i2c = max77823->fuelgauge; + fuelgauge->max77823_pdata = pdata; + + board_fuelgauge_init((void *)fuelgauge); + +#if defined(CONFIG_OF) + ret = max77823_fuelgauge_parse_dt(fuelgauge, pdev->dev.of_node); + if (ret < 0) { + pr_err("%s:dt error! ret[%d]\n", __func__, ret); + goto err_free; + } +#endif + + platform_set_drvdata(pdev, fuelgauge); + + fuelgauge->capacity_max = fuelgauge->pdata->capacity_max; +#ifdef CONFIG_FUELGAUGE_MAX77823_VOLTAGE_TRACKING + raw_soc_val.intval = max77823_get_soc(fuelgauge) / 10; +#else + raw_soc_val.intval = fg_read_percent(fuelgauge, SOCREP_REG); +#endif + + if(raw_soc_val.intval > fuelgauge->pdata->capacity_max) + max77823_fg_calculate_dynamic_scale(fuelgauge); + + (void) debugfs_create_file("max77823-fuelgauge-regs", + S_IRUGO, NULL, (void *)fuelgauge, &max77823_fuelgauge_debugfs_fops); + + if (!max77823_fg_init(fuelgauge)) { + pr_err("%s: Failed to Initialize Fuelgauge\n", __func__); + goto err_free; + } + + psy_fg_config.drv_data = fuelgauge; + fuelgauge->psy_fg = power_supply_register(&pdev->dev, &psy_fg_desc, &psy_fg_config); + if (IS_ERR(fuelgauge->psy_fg)) { + pr_err("%s: Failed to Register psy_fg\n", __func__); + ret = PTR_ERR(fuelgauge->psy_fg); + goto err_free; + } + + fuelgauge->fg_irq = pdata->irq_base + MAX77823_FG_IRQ_ALERT; + pr_info("[%s]IRQ_BASE(%d) FG_IRQ(%d)\n", + __func__, pdata->irq_base, fuelgauge->fg_irq); + + if (fuelgauge->fg_irq) { + INIT_DELAYED_WORK(&fuelgauge->isr_work, max77823_fg_isr_work); + + ret = request_threaded_irq(fuelgauge->fg_irq, + NULL, max77823_fg_irq_thread, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "fuelgauge-irq", fuelgauge); + if (ret) { + pr_err("%s: Failed to Request IRQ\n", __func__); + goto err_supply_unreg; + } + } + + fuelgauge->is_fuel_alerted = false; + if (fuelgauge->pdata->fuel_alert_soc >= 0) { + if (max77823_fg_fuelalert_init(fuelgauge, + fuelgauge->pdata->fuel_alert_soc)) + wake_lock_init(&fuelgauge->fuel_alert_wake_lock, + WAKE_LOCK_SUSPEND, "fuel_alerted"); + else { + pr_err("%s: Failed to Initialize Fuel-alert\n", + __func__); + ret = -ENODEV; + goto err_irq; + } + } + + fuelgauge->initial_update_of_soc = true; + + pr_info("%s: MAX77823 Fuelgauge Driver Loaded\n", __func__); + return 0; + +err_irq: + if (fuelgauge->fg_irq) + free_irq(fuelgauge->fg_irq, fuelgauge); +err_supply_unreg: + power_supply_unregister(fuelgauge->psy_fg); +err_free: + mutex_destroy(&fuelgauge->fg_lock); + kfree(pdata->fuelgauge_data); + kfree(fuelgauge); + + return ret; +} + +static int max77823_fuelgauge_remove(struct platform_device *pdev) +{ + struct max77823_fuelgauge_data *fuelgauge = + platform_get_drvdata(pdev); + + if (fuelgauge->pdata->fuel_alert_soc >= 0) + wake_lock_destroy(&fuelgauge->fuel_alert_wake_lock); + + return 0; +} + +static int max77823_fuelgauge_suspend(struct device *dev) +{ + return 0; +} + +static int max77823_fuelgauge_resume(struct device *dev) +{ + struct max77823_fuelgauge_data *fuelgauge = dev_get_drvdata(dev); + + fuelgauge->initial_update_of_soc = true; + + return 0; +} + +static void max77823_fuelgauge_shutdown(struct device *dev) +{ +} + +#if defined(CONFIG_OF) +static struct of_device_id max77823_fuelgauge_dt_ids[] = { + { .compatible = "samsung,max77823-fuelgauge" }, + { } +}; +MODULE_DEVICE_TABLE(of, max77823_fuelgauge_dt_ids); +#endif /* CONFIG_OF */ + +static SIMPLE_DEV_PM_OPS(max77823_fuelgauge_pm_ops, max77823_fuelgauge_suspend, + max77823_fuelgauge_resume); + +static struct platform_driver max77823_fuelgauge_driver = { + .driver = { + .name = "max77823-fuelgauge", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &max77823_fuelgauge_pm_ops, +#endif + .shutdown = max77823_fuelgauge_shutdown, +#if defined(CONFIG_OF) + .of_match_table = max77823_fuelgauge_dt_ids, +#endif /* CONFIG_OF */ + }, + .probe = max77823_fuelgauge_probe, + .remove = max77823_fuelgauge_remove, +}; + +static int __init max77823_fuelgauge_init(void) +{ + pr_info("%s: \n", __func__); + return platform_driver_register(&max77823_fuelgauge_driver); +} + +static void __exit max77823_fuelgauge_exit(void) +{ + platform_driver_unregister(&max77823_fuelgauge_driver); +} +module_init(max77823_fuelgauge_init); +module_exit(max77823_fuelgauge_exit); + +MODULE_DESCRIPTION("Samsung MAX778023 Fuel Gauge Driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:max77823-fuelgauge"); diff --git a/drivers/battery/sec_battery.c b/drivers/battery/sec_battery.c new file mode 100644 index 00000000000000..e82b93cde9cc26 --- /dev/null +++ b/drivers/battery/sec_battery.c @@ -0,0 +1,4922 @@ +/* + * sec_battery.c + * Samsung Mobile Battery Driver + * + * Copyright (C) 2012 Samsung Electronics + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#if defined(CONFIG_SENSORS_QPNP_ADC_VOLTAGE) +#include +#endif +#ifdef CONFIG_SAMSUNG_BATTERY_DISALLOW_DEEP_SLEEP +#include +#endif + +#if defined(CONFIG_TMM_CHG_CTRL) +#define TUNER_SWITCHED_ON_SIGNAL -1 +#define TUNER_SWITCHED_OFF_SIGNAL -2 +#define TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE 800 +#define TUNER_IS_ON 1 +#define TUNER_IS_OFF 0 +#endif + +#ifdef CONFIG_SAMSUNG_BATTERY_DISALLOW_DEEP_SLEEP +struct clk * xo_chr = NULL; +#endif + +#define MV_TO_UV(mv) (mv * 1000) + +static struct device_attribute sec_battery_attrs[] = { + SEC_BATTERY_ATTR(batt_reset_soc), + SEC_BATTERY_ATTR(batt_read_raw_soc), + SEC_BATTERY_ATTR(batt_read_adj_soc), + SEC_BATTERY_ATTR(batt_type), + SEC_BATTERY_ATTR(batt_vfocv), + SEC_BATTERY_ATTR(batt_vol_adc), + SEC_BATTERY_ATTR(batt_vol_adc_cal), + SEC_BATTERY_ATTR(batt_vol_aver), + SEC_BATTERY_ATTR(batt_vol_adc_aver), + SEC_BATTERY_ATTR(batt_current_ua_now), + SEC_BATTERY_ATTR(batt_current_ua_avg), + SEC_BATTERY_ATTR(batt_temp), + SEC_BATTERY_ATTR(batt_temp_adc), + SEC_BATTERY_ATTR(batt_temp_aver), + SEC_BATTERY_ATTR(batt_temp_adc_aver), + SEC_BATTERY_ATTR(chg_temp), + SEC_BATTERY_ATTR(chg_temp_adc), + SEC_BATTERY_ATTR(batt_vf_adc), + SEC_BATTERY_ATTR(batt_slate_mode), + + SEC_BATTERY_ATTR(batt_lp_charging), + SEC_BATTERY_ATTR(siop_activated), + SEC_BATTERY_ATTR(siop_level), + SEC_BATTERY_ATTR(batt_charging_source), + SEC_BATTERY_ATTR(fg_reg_dump), + SEC_BATTERY_ATTR(fg_reset_cap), + SEC_BATTERY_ATTR(fg_capacity), + SEC_BATTERY_ATTR(auth), + SEC_BATTERY_ATTR(chg_current_adc), + SEC_BATTERY_ATTR(wc_adc), + SEC_BATTERY_ATTR(wc_status), + SEC_BATTERY_ATTR(wc_enable), + SEC_BATTERY_ATTR(hv_charger_status), + SEC_BATTERY_ATTR(hv_charger_set), + SEC_BATTERY_ATTR(factory_mode), + SEC_BATTERY_ATTR(store_mode), + SEC_BATTERY_ATTR(update), + SEC_BATTERY_ATTR(test_mode), + + SEC_BATTERY_ATTR(call), + SEC_BATTERY_ATTR(2g_call), + SEC_BATTERY_ATTR(talk_gsm), + SEC_BATTERY_ATTR(3g_call), + SEC_BATTERY_ATTR(talk_wcdma), + SEC_BATTERY_ATTR(music), + SEC_BATTERY_ATTR(video), + SEC_BATTERY_ATTR(browser), + SEC_BATTERY_ATTR(hotspot), + SEC_BATTERY_ATTR(camera), + SEC_BATTERY_ATTR(camcorder), + SEC_BATTERY_ATTR(data_call), + SEC_BATTERY_ATTR(wifi), + SEC_BATTERY_ATTR(wibro), + SEC_BATTERY_ATTR(lte), + SEC_BATTERY_ATTR(lcd), + SEC_BATTERY_ATTR(gps), + SEC_BATTERY_ATTR(event), + SEC_BATTERY_ATTR(batt_temp_table), + SEC_BATTERY_ATTR(batt_high_current_usb), +#if defined(CONFIG_SAMSUNG_BATTERY_ENG_TEST) + SEC_BATTERY_ATTR(test_charge_current), +#endif + SEC_BATTERY_ATTR(set_stability_test), +}; +#if defined(CONFIG_QPNP_BMS) +static char *pm_batt_supplied_to[] = { + "bms", +}; +#endif + + +static enum power_supply_property sec_battery_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_CHARGE_TYPE, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_VOLTAGE_AVG, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CURRENT_AVG, + POWER_SUPPLY_PROP_CHARGE_NOW, + POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, + POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, + POWER_SUPPLY_PROP_ENERGY_FULL, + POWER_SUPPLY_PROP_ENERGY_EMPTY, + POWER_SUPPLY_PROP_ENERGY_NOW, + POWER_SUPPLY_PROP_ENERGY_AVG, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TEMP_AMBIENT, +}; + +static enum power_supply_property sec_power_props[] = { + POWER_SUPPLY_PROP_ONLINE, +}; + +static enum power_supply_property sec_ps_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, +}; + +static char *supply_list[] = { + "battery", +}; + +char *sec_bat_charging_mode_str[] = { + "None", + "Normal", + "Additional", + "Re-Charging", + "ABS" +}; + +char *sec_bat_status_str[] = { + "Unknown", + "Charging", + "Discharging", + "Not-charging", + "Full" +}; + +char *sec_bat_health_str[] = { + "Unknown", + "Good", + "Overheat", + "Warm", + "Dead", + "OverVoltage", + "UnspecFailure", + "Cold", + "Cool", + "UnderVoltage", + "OverheatLimit" +}; + +#if defined(CONFIG_TMM_CHG_CTRL) +static int tuner_running_status; +#endif + +int poweroff_charging; +static int sec_bat_is_lpm_check(char *str) +{ + if (strncmp(str, "charger", 7) == 0) + poweroff_charging = 1; + + pr_info("%s: Low power charging mode: %d\n", __func__, poweroff_charging); + + return poweroff_charging; +} +__setup("androidboot.mode=", sec_bat_is_lpm_check); + +static struct sec_charging_current *get_charging_info(struct sec_battery_info *battery, int index) +{ + struct sec_battery_platform_data *pdata = battery->pdata; + if (index >= pdata->charging_current_entries) { + pr_err("%s: invalid index %d\n", __func__, index); + index = POWER_SUPPLY_TYPE_UNKNOWN; /* 0 */ + } + return &pdata->charging_current[index]; +} + +static bool sec_bat_is_lpm(struct sec_battery_info *battery) +{ + if (battery->pdata->is_lpm) { + return battery->pdata->is_lpm(); + } else { + return (bool)poweroff_charging; + } +} + +static int sec_bat_set_charge( + struct sec_battery_info *battery, + bool enable) +{ + union power_supply_propval val; + + if (battery->cable_type == POWER_SUPPLY_TYPE_OTG) + return 0; + if (battery->prev_status != battery->status) { + val.intval = battery->prev_status = battery->status; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_STATUS, val); + } + + val.intval = enable ? battery->cable_type : POWER_SUPPLY_TYPE_BATTERY; + if (battery->prev_online == val.intval) + return 0; + battery->prev_online = val.intval; + if (enable) { + /*Reset charging start time only in initial charging start */ + if (battery->charging_start_time == 0) { + ktime_t current_time; + struct timespec ts; + +#if defined(ANDROID_ALARM_ACTIVATED) + current_time = alarm_get_elapsed_realtime(); + ts = ktime_to_timespec(current_time); +#else + current_time = ktime_get_boottime(); + ts = ktime_to_timespec(current_time); +#endif + if (ts.tv_sec < 1) + ts.tv_sec = 1; + battery->charging_start_time = ts.tv_sec; + battery->charging_next_time = + battery->pdata->charging_reset_time; + } + } else { + battery->charging_start_time = 0; + battery->charging_passed_time = 0; + battery->charging_next_time = 0; + battery->charging_fullcharged_time = 0; + battery->full_check_cnt = 0; + } + + battery->temp_highlimit_cnt = 0; + battery->temp_high_cnt = 0; + battery->temp_low_cnt = 0; + battery->temp_recover_cnt = 0; + +#if defined(CONFIG_TMM_CHG_CTRL) + if((tuner_running_status==TUNER_IS_ON) && + (get_charging_info(battery, val.intval)->input_current_limit + > TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE)) { + union power_supply_propval value; + + dev_dbg(battery->dev, + "%s: tmm chg current set!\n", __func__); + value.intval = TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_NOW, value); + } else { + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, val); + } +#else + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, val); +#endif + + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_ONLINE, val); + + return 0; +} + +static int evaluate_charge(struct sec_battery_info *battery) +{ + bool enable = false; + + if (battery->store_mode && battery->cable_type != POWER_SUPPLY_TYPE_BATTERY) { + dev_info(battery->dev, + "%s: @battery->capacity = (%d), battery->status= (%d), battery->store_mode=(%d)\n", + __func__, battery->capacity, battery->status, battery->store_mode); + + if ((battery->capacity >= 35) && (battery->status == POWER_SUPPLY_STATUS_CHARGING)) { + battery->store_mode_enable = false; + } else if ((battery->capacity <= 30) && (battery->status == POWER_SUPPLY_STATUS_DISCHARGING)) { + battery->store_mode_enable = true; + } + } + + if ((battery->health == POWER_SUPPLY_HEALTH_GOOD) && + (battery->charger_health == POWER_SUPPLY_HEALTH_GOOD)) + enable = true; + + if (battery->store_mode && !battery->store_mode_enable) + enable = false; + + if (battery->capacity >= 100) + battery->status = POWER_SUPPLY_STATUS_FULL; + else if (enable) + battery->status = POWER_SUPPLY_STATUS_CHARGING; + else if (battery->charger_health != POWER_SUPPLY_HEALTH_GOOD) + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + else + battery->status = POWER_SUPPLY_STATUS_NOT_CHARGING; + + return sec_bat_set_charge(battery, enable); +} + +static int sec_bat_get_adc_data(struct sec_battery_info *battery, + int adc_ch, int count) +{ + int adc_data; + int adc_max; + int adc_min; + int adc_total; + int i; + + adc_data = 0; + adc_max = 0; + adc_min = 0; + adc_total = 0; + + for (i = 0; i < count; i++) { + mutex_lock(&battery->adclock); +#ifdef CONFIG_OF + adc_data = adc_read(battery, adc_ch); +#else + adc_data = adc_read(battery->pdata, adc_ch); +#endif + mutex_unlock(&battery->adclock); + + if (adc_data < 0) + goto err; + + if (i != 0) { + if (adc_data > adc_max) + adc_max = adc_data; + else if (adc_data < adc_min) + adc_min = adc_data; + } else { + adc_max = adc_data; + adc_min = adc_data; + } + adc_total += adc_data; + } + + return (adc_total - adc_max - adc_min) / (count - 2); +err: + return adc_data; +} + +/* +static unsigned long calculate_average_adc( + struct sec_battery_info *battery, + int channel, int adc) +{ + unsigned int cnt = 0; + int total_adc = 0; + int average_adc = 0; + int index = 0; + + cnt = battery->adc_sample[channel].cnt; + total_adc = battery->adc_sample[channel].total_adc; + + if (adc < 0) { + dev_err(battery->dev, + "%s : Invalid ADC : %d\n", __func__, adc); + adc = battery->adc_sample[channel].average_adc; + } + + if (cnt < ADC_SAMPLE_COUNT) { + battery->adc_sample[channel].adc_arr[cnt] = adc; + battery->adc_sample[channel].index = cnt; + battery->adc_sample[channel].cnt = ++cnt; + + total_adc += adc; + average_adc = total_adc / cnt; + } else { + index = battery->adc_sample[channel].index; + if (++index >= ADC_SAMPLE_COUNT) + index = 0; + + total_adc = total_adc - + battery->adc_sample[channel].adc_arr[index] + adc; + average_adc = total_adc / ADC_SAMPLE_COUNT; + + battery->adc_sample[channel].adc_arr[index] = adc; + battery->adc_sample[channel].index = index; + } + + battery->adc_sample[channel].total_adc = total_adc; + battery->adc_sample[channel].average_adc = average_adc; + + return average_adc; +} +*/ +static int sec_bat_get_adc_value( + struct sec_battery_info *battery, int channel) +{ + int adc; + + adc = sec_bat_get_adc_data(battery, channel, + battery->pdata->adc_check_count); + + if (adc < 0) { + dev_err(battery->dev, + "%s: Error in ADC\n", __func__); + return adc; + } + + return adc; +} + +static int sec_bat_get_charger_type_adc + (struct sec_battery_info *battery) +{ + /* It is true something valid is + connected to the device for charging. + By default this something is considered to be USB.*/ + int result = POWER_SUPPLY_TYPE_USB; + + int adc = 0; + int i; + + /* Do NOT check cable type when cable_switch_check() returns false + * and keep current cable type + */ + if (battery->pdata->cable_switch_check && + !battery->pdata->cable_switch_check()) + return battery->cable_type; + + adc = sec_bat_get_adc_value(battery, + SEC_BAT_ADC_CHANNEL_CABLE_CHECK); + + /* Do NOT check cable type when cable_switch_normal() returns false + * and keep current cable type + */ + if (battery->pdata->cable_switch_normal && + !battery->pdata->cable_switch_normal()) + return battery->cable_type; + + for (i = 0; i < SEC_SIZEOF_POWER_SUPPLY_TYPE; i++) + if ((adc > battery->pdata->cable_adc_value[i].min) && + (adc < battery->pdata->cable_adc_value[i].max)) + break; + if (i >= SEC_SIZEOF_POWER_SUPPLY_TYPE) + dev_err(battery->dev, + "%s : default USB\n", __func__); + else + result = i; + + dev_dbg(battery->dev, "%s : result(%d), adc(%d)\n", + __func__, result, adc); + + return result; +} + +static bool sec_bat_check_vf_adc(struct sec_battery_info *battery) +{ + int adc; + + adc = sec_bat_get_adc_data(battery, + SEC_BAT_ADC_CHANNEL_BAT_CHECK, + battery->pdata->adc_check_count); + + if (adc < 0) { + dev_err(battery->dev, "%s: VF ADC error\n", __func__); + adc = battery->check_adc_value; + } else + battery->check_adc_value = adc; + + if ((battery->check_adc_value <= battery->pdata->check_adc_max) && + (battery->check_adc_value >= battery->pdata->check_adc_min)) + return true; + else { + dev_info(battery->dev, "%s: adc (%d)\n", __func__, battery->check_adc_value); + return false; + } +} + +static bool sec_bat_check_by_psy(struct sec_battery_info *battery) +{ + char *psy_name; + union power_supply_propval value; + bool ret; + ret = true; + + switch (battery->pdata->battery_check_type) { + case SEC_BATTERY_CHECK_PMIC: + psy_name = battery->pdata->pmic_name; + break; + case SEC_BATTERY_CHECK_FUELGAUGE: + psy_name = battery->pdata->fuelgauge_name; + break; + case SEC_BATTERY_CHECK_CHARGER: + psy_name = battery->pdata->charger_name; + break; + default: + dev_err(battery->dev, + "%s: Invalid Battery Check Type\n", __func__); + ret = false; + goto battery_check_error; + break; + } + + psy_do_property(psy_name, get, + POWER_SUPPLY_PROP_PRESENT, value); + ret = (bool)value.intval; + +battery_check_error: + return ret; +} + +static bool sec_bat_check(struct sec_battery_info *battery) +{ + bool ret; + ret = true; + + if (battery->factory_mode || sec_bat_check_jig_status()) { + dev_dbg(battery->dev, "%s: No need to check in factory mode\n", + __func__); + return ret; + } + + if (battery->health != POWER_SUPPLY_HEALTH_GOOD && + battery->health != POWER_SUPPLY_HEALTH_UNSPEC_FAILURE) { + dev_dbg(battery->dev, "%s: No need to check\n", __func__); + return ret; + } + + switch (battery->pdata->battery_check_type) { + case SEC_BATTERY_CHECK_ADC: + if(battery->cable_type == POWER_SUPPLY_TYPE_BATTERY) + ret = battery->present; + else + ret = sec_bat_check_vf_adc(battery); + break; + case SEC_BATTERY_CHECK_INT: + case SEC_BATTERY_CHECK_CALLBACK: + if(battery->cable_type == POWER_SUPPLY_TYPE_BATTERY) + ret = battery->present; + else + ret = sec_bat_check_callback(battery); + break; + case SEC_BATTERY_CHECK_PMIC: + case SEC_BATTERY_CHECK_FUELGAUGE: + case SEC_BATTERY_CHECK_CHARGER: + ret = sec_bat_check_by_psy(battery); + break; + case SEC_BATTERY_CHECK_NONE: + dev_dbg(battery->dev, "%s: No Check\n", __func__); + default: + break; + } + + return ret; +} + +static bool sec_bat_get_cable_type( + struct sec_battery_info *battery, + int cable_source_type) +{ + bool ret; + int cable_type; + + ret = false; + cable_type = battery->cable_type; + + if (cable_source_type & SEC_BATTERY_CABLE_SOURCE_CALLBACK) { + cable_type = sec_bat_check_cable_callback(battery); + } + + if (cable_source_type & SEC_BATTERY_CABLE_SOURCE_ADC) { + if (gpio_get_value_cansleep( + battery->pdata->bat_gpio_ta_nconnected) ^ + battery->pdata->bat_polarity_ta_nconnected) + cable_type = POWER_SUPPLY_TYPE_BATTERY; + else + cable_type = + sec_bat_get_charger_type_adc(battery); + } + + if (battery->cable_type == cable_type) { + dev_dbg(battery->dev, + "%s: No need to change cable status\n", __func__); + } else { + if (cable_type < POWER_SUPPLY_TYPE_BATTERY || + cable_type >= SEC_SIZEOF_POWER_SUPPLY_TYPE) { + dev_err(battery->dev, + "%s: Invalid cable type\n", __func__); + } else { + battery->cable_type = cable_type; + sec_bat_check_cable_result_callback(battery->dev, battery->cable_type); + + ret = true; + + dev_dbg(battery->dev, "%s: Cable Changed (%d)\n", + __func__, battery->cable_type); + } + } + + return ret; +} + +static bool sec_bat_battery_cable_check(struct sec_battery_info *battery) +{ + if (!sec_bat_check(battery)) { + if (battery->check_count < battery->pdata->check_count) + battery->check_count++; + else { + dev_err(battery->dev, + "%s: Battery Disconnected\n", __func__); + battery->present = false; + battery->health = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + evaluate_charge(battery); + + if (battery->pdata->check_battery_result_callback) + battery->pdata-> + check_battery_result_callback(); + return false; + } + } else + battery->check_count = 0; + + battery->present = true; + + if (battery->health == POWER_SUPPLY_HEALTH_UNSPEC_FAILURE) { + battery->health = POWER_SUPPLY_HEALTH_GOOD; + evaluate_charge(battery); + } + + dev_dbg(battery->dev, "%s: Battery Connected\n", __func__); + + if (battery->pdata->cable_check_type & + SEC_BATTERY_CABLE_CHECK_POLLING) { + if (sec_bat_get_cable_type(battery, + battery->pdata->cable_source_type)) { + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + } + } + return true; +}; + +static int sec_bat_ovp_uvlo_by_psy(struct sec_battery_info *battery) +{ + char *psy_name; + union power_supply_propval value; + + value.intval = POWER_SUPPLY_HEALTH_GOOD; + + switch (battery->pdata->ovp_uvlo_check_type) { + case SEC_BATTERY_OVP_UVLO_PMICPOLLING: + psy_name = battery->pdata->pmic_name; + break; + case SEC_BATTERY_OVP_UVLO_CHGPOLLING: + psy_name = battery->pdata->charger_name; + break; + default: + dev_err(battery->dev, + "%s: Invalid OVP/UVLO Check Type\n", __func__); + goto ovp_uvlo_check_error; + break; + } + + psy_do_property(psy_name, get, + POWER_SUPPLY_PROP_HEALTH, value); + +ovp_uvlo_check_error: + return value.intval; +} + +static bool sec_bat_ovp_uvlo_result( + struct sec_battery_info *battery, int charger_health) +{ + if (battery->charger_health != charger_health) { + battery->charger_health = charger_health; + switch (charger_health) { + case POWER_SUPPLY_HEALTH_GOOD: + dev_info(battery->dev, "%s: Safe voltage\n", __func__); + dev_info(battery->dev, "%s: is_recharging : %d\n", __func__, battery->is_recharging); + evaluate_charge(battery); + battery->charging_mode = SEC_BATTERY_CHARGING_1ST; + break; + case POWER_SUPPLY_HEALTH_OVERVOLTAGE: + case POWER_SUPPLY_HEALTH_UNDERVOLTAGE: + dev_info(battery->dev, + "%s: Unsafe voltage (%d)\n", + __func__, charger_health); + evaluate_charge(battery); + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + /* Take the wakelock during 10 seconds + when over-voltage status is detected */ + wake_lock_timeout(&battery->vbus_wake_lock, HZ * 10); + break; + } + power_supply_changed(battery->psy_bat); + return true; + } + + return false; +} + +static bool sec_bat_ovp_uvlo(struct sec_battery_info *battery) +{ + int charger_health; + + if (battery->factory_mode || sec_bat_check_jig_status()) { + dev_dbg(battery->dev, "%s: No need to check in factory mode\n", __func__); + return false; + } else if ((battery->status == POWER_SUPPLY_STATUS_FULL) && + (battery->charging_mode == SEC_BATTERY_CHARGING_NONE)) { + dev_dbg(battery->dev, "%s: No need to check in Full status", __func__); + return false; + } + + if (battery->charger_health != POWER_SUPPLY_HEALTH_GOOD && + battery->charger_health != POWER_SUPPLY_HEALTH_OVERVOLTAGE && + battery->charger_health != POWER_SUPPLY_HEALTH_UNDERVOLTAGE) { + dev_dbg(battery->dev, "%s: No need to check\n", __func__); + return false; + } + + charger_health = battery->charger_health; + + switch (battery->pdata->ovp_uvlo_check_type) { + case SEC_BATTERY_OVP_UVLO_CALLBACK: + if (battery->pdata->ovp_uvlo_callback) + charger_health = battery->pdata->ovp_uvlo_callback(); + break; + case SEC_BATTERY_OVP_UVLO_PMICPOLLING: + case SEC_BATTERY_OVP_UVLO_CHGPOLLING: + charger_health = sec_bat_ovp_uvlo_by_psy(battery); + break; + case SEC_BATTERY_OVP_UVLO_PMICINT: + case SEC_BATTERY_OVP_UVLO_CHGINT: + /* nothing for interrupt check */ + default: + break; + } + + return sec_bat_ovp_uvlo_result(battery, charger_health); +} + +static void update_charger_health(struct sec_battery_info *battery) +{ + int charger_health = battery->charger_health; + + switch (battery->pdata->ovp_uvlo_check_type) { + case SEC_BATTERY_OVP_UVLO_CALLBACK: + if (!battery->pdata->ovp_uvlo_callback) + return; + charger_health = battery->pdata->ovp_uvlo_callback(); + break; + case SEC_BATTERY_OVP_UVLO_PMICPOLLING: + case SEC_BATTERY_OVP_UVLO_CHGPOLLING: + case SEC_BATTERY_OVP_UVLO_PMICINT: + case SEC_BATTERY_OVP_UVLO_CHGINT: + charger_health = sec_bat_ovp_uvlo_by_psy(battery); + break; + default: + return; + } + + sec_bat_ovp_uvlo_result(battery, charger_health); + return; +} + +static bool sec_bat_check_recharge(struct sec_battery_info *battery) +{ +#if defined(CONFIG_BATTERY_SWELLING) + if (battery->swelling_mode) { + pr_info("%s: Skip normal recharge check routine for swelling mode\n", + __func__); + return false; + } +#endif + if ((battery->status == POWER_SUPPLY_STATUS_CHARGING) && + (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL) && + (battery->charging_mode == SEC_BATTERY_CHARGING_NONE)) { + dev_info(battery->dev, + "%s: Re-charging by NOTIMEFULL (%d)\n", + __func__, battery->capacity); + goto check_recharge_check_count; + } + + if (battery->status == POWER_SUPPLY_STATUS_FULL && + battery->charging_mode == SEC_BATTERY_CHARGING_NONE) { + if ((battery->pdata->recharge_condition_type & + SEC_BATTERY_RECHARGE_CONDITION_SOC) && + (battery->capacity <= + battery->pdata->recharge_condition_soc)) { + dev_info(battery->dev, + "%s: Re-charging by SOC (%d)\n", + __func__, battery->capacity); + goto check_recharge_check_count; + } + + if ((battery->pdata->recharge_condition_type & + SEC_BATTERY_RECHARGE_CONDITION_AVGVCELL) && + (battery->voltage_avg <= + battery->pdata->recharge_condition_avgvcell)) { + dev_info(battery->dev, + "%s: Re-charging by average VCELL (%d)\n", + __func__, battery->voltage_avg); + goto check_recharge_check_count; + } + + if ((battery->pdata->recharge_condition_type & + SEC_BATTERY_RECHARGE_CONDITION_VCELL) && + (battery->voltage_now <= + battery->pdata->recharge_condition_vcell)) { + dev_info(battery->dev, + "%s: Re-charging by VCELL (%d)\n", + __func__, battery->voltage_now); + goto check_recharge_check_count; + } + } + + battery->recharge_check_cnt = 0; + return false; + +check_recharge_check_count: + if (battery->recharge_check_cnt < + battery->pdata->recharge_check_count) + battery->recharge_check_cnt++; + dev_dbg(battery->dev, + "%s: recharge count = %d\n", + __func__, battery->recharge_check_cnt); + + if (battery->recharge_check_cnt >= + battery->pdata->recharge_check_count) + return true; + else + return false; +} + +static bool sec_bat_voltage_check(struct sec_battery_info *battery) +{ + if (battery->status == POWER_SUPPLY_STATUS_DISCHARGING) { + dev_dbg(battery->dev, + "%s: Charging Disabled\n", __func__); + return true; + } + + /* OVP/UVLO check */ + if (sec_bat_ovp_uvlo(battery)) { + if (battery->pdata->ovp_uvlo_result_callback) + battery->pdata-> + ovp_uvlo_result_callback(battery->charger_health); + return false; + } + + /* Re-Charging check */ + if (sec_bat_check_recharge(battery)) { + if (battery->pdata->full_check_type != + SEC_BATTERY_FULLCHARGED_NONE) + battery->charging_mode = SEC_BATTERY_CHARGING_1ST; + else + battery->charging_mode = SEC_BATTERY_CHARGING_2ND; + battery->is_recharging = true; + evaluate_charge(battery); + if (battery->status == POWER_SUPPLY_STATUS_FULL) { + if (battery->capacity < + battery->pdata->full_condition_soc && + battery->voltage_now < + (battery->pdata->recharge_condition_vcell - MV_TO_UV(50))) { + battery->status = POWER_SUPPLY_STATUS_CHARGING; + battery->voltage_now = MV_TO_UV(1080); + battery->voltage_avg = MV_TO_UV(1080); + power_supply_changed(battery->psy_bat); + dev_info(battery->dev, + "%s: battery status full -> charging\n", __func__); + } + } + return false; + } + + return true; +} + +static bool sec_bat_get_temperature_by_adc( + struct sec_battery_info *battery, + enum sec_battery_adc_channel channel, + union power_supply_propval *value) +{ + int temp = 0; + int temp_adc; + int low = 0; + int high = 0; + int mid = 0; + const sec_bat_adc_table_data_t *temp_adc_table; + unsigned int temp_adc_table_size; + + switch (channel) { + case SEC_BAT_ADC_CHANNEL_TEMP: + temp_adc_table = battery->pdata->temp_adc_table; + temp_adc_table_size = + battery->pdata->temp_adc_table_size; + break; + case SEC_BAT_ADC_CHANNEL_TEMP_AMBIENT: + temp_adc_table = battery->pdata->temp_amb_adc_table; + temp_adc_table_size = + battery->pdata->temp_amb_adc_table_size; + break; + case SEC_BAT_ADC_CHANNEL_CHG_TEMP: + temp_adc_table = battery->pdata->chg_temp_adc_table; + temp_adc_table_size = + battery->pdata->chg_temp_adc_table_size; + break; + default: + dev_err(battery->dev, + "%s: Invalid Property\n", __func__); + return false; + } + + temp_adc = sec_bat_get_adc_value(battery, channel); + if (temp_adc < 0) + return true; + + switch (channel) { + case SEC_BAT_ADC_CHANNEL_TEMP: + battery->temp_adc = temp_adc; + break; + case SEC_BAT_ADC_CHANNEL_TEMP_AMBIENT: + battery->temp_ambient_adc = temp_adc; + break; + case SEC_BAT_ADC_CHANNEL_CHG_TEMP: + battery->chg_temp_adc = temp_adc; + break; + default: + dev_err(battery->dev, + "%s: Invalid Property\n", __func__); + return false; + } + + if (temp_adc_table[0].adc >= temp_adc) { + temp = temp_adc_table[0].data; + goto temp_by_adc_goto; + } else if (temp_adc_table[temp_adc_table_size-1].adc <= temp_adc) { + temp = temp_adc_table[temp_adc_table_size-1].data; + goto temp_by_adc_goto; + } + + high = temp_adc_table_size - 1; + + while (low <= high) { + mid = (low + high) / 2; + if (temp_adc_table[mid].adc > temp_adc) + high = mid - 1; + else if (temp_adc_table[mid].adc < temp_adc) + low = mid + 1; + else { + temp = temp_adc_table[mid].data; + goto temp_by_adc_goto; + } + } + + temp = temp_adc_table[high].data; + temp += ((temp_adc_table[low].data - temp_adc_table[high].data) * + (temp_adc - temp_adc_table[high].adc)) / + (temp_adc_table[low].adc - temp_adc_table[high].adc); + +temp_by_adc_goto: + value->intval = temp; + + dev_dbg(battery->dev, + "%s: Temp(%d), Temp-ADC(%d)\n", + __func__, temp, temp_adc); + + return true; +} + +static bool sec_bat_temperature( + struct sec_battery_info *battery) +{ + bool ret; + ret = true; + + if (battery->pdata->event_check && battery->event) { + battery->temp_highlimit_threshold = + battery->pdata->temp_highlimit_threshold_event; + battery->temp_highlimit_recovery = + battery->pdata->temp_highlimit_recovery_event; + battery->temp_high_threshold = + battery->pdata->temp_high_threshold_event; + battery->temp_high_recovery = + battery->pdata->temp_high_recovery_event; + battery->temp_low_recovery = + battery->pdata->temp_low_recovery_event; + battery->temp_low_threshold = + battery->pdata->temp_low_threshold_event; + } else if (sec_bat_is_lpm(battery)) { + battery->temp_highlimit_threshold = + battery->pdata->temp_highlimit_threshold_lpm; + battery->temp_highlimit_recovery = + battery->pdata->temp_highlimit_recovery_lpm; + battery->temp_high_threshold = + battery->pdata->temp_high_threshold_lpm; + battery->temp_high_recovery = + battery->pdata->temp_high_recovery_lpm; + battery->temp_low_recovery = + battery->pdata->temp_low_recovery_lpm; + battery->temp_low_threshold = + battery->pdata->temp_low_threshold_lpm; + } else { + battery->temp_highlimit_threshold = + battery->pdata->temp_highlimit_threshold_normal; + battery->temp_highlimit_recovery = + battery->pdata->temp_highlimit_recovery_normal; + battery->temp_high_threshold = + battery->pdata->temp_high_threshold_normal; + battery->temp_high_recovery = + battery->pdata->temp_high_recovery_normal; + battery->temp_low_recovery = + battery->pdata->temp_low_recovery_normal; + battery->temp_low_threshold = + battery->pdata->temp_low_threshold_normal; + } + + dev_dbg(battery->dev, + "%s: HLT(%d) HLR(%d) HT(%d), HR(%d), LT(%d), LR(%d)\n", + __func__, battery->temp_highlimit_threshold, + battery->temp_highlimit_recovery, + battery->temp_high_threshold, + battery->temp_high_recovery, + battery->temp_low_threshold, + battery->temp_low_recovery); + return ret; +} + +#if defined(CONFIG_BATTERY_SWELLING) +static void sec_bat_swelling_check(struct sec_battery_info *battery, int temperature) +{ + union power_supply_propval val; + ktime_t current_time; + struct timespec ts; + + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_VOLTAGE_MAX, val); + + pr_info("%s: status(%d), swell_mode(%d), cv(0x%x), temp(%d)\n", + __func__, battery->status, battery->swelling_mode, val.intval, temperature); + + /* swelling_mode + under voltage over voltage, battery missing */ + if ((battery->status == POWER_SUPPLY_STATUS_DISCHARGING) ||\ + (battery->status == POWER_SUPPLY_STATUS_NOT_CHARGING)) { + pr_info("%s: DISCHARGING or NOT-CHARGING. stop swelling mode\n", __func__); + battery->swelling_mode = false; + battery->swelling_block = false; + goto skip_swelling_chek; + } + + if (!battery->swelling_mode) { + /*if ((temperature >= BATT_SWELLING_HIGH_TEMP_BLOCK) ||\ + (temperature <= BATT_SWELLING_LOW_TEMP_BLOCK)) {*/ + if (temperature >= BATT_SWELLING_HIGH_TEMP_BLOCK) { + pr_info("%s: swelling mode start. stop charging\n", __func__); + sec_bat_set_charge(battery, false); + battery->swelling_mode = true; + battery->swelling_block = true; + battery->swelling_full_check_cnt = 0; + /* Initialize swelling charging-block timer */ + current_time = ktime_get_boottime(); + ts = ktime_to_timespec(current_time); + battery->swelling_block_start = ts.tv_sec; + } + } else { + get_monotonic_boottime(&ts); + if (ts.tv_sec >= battery->swelling_block_start) + battery->swelling_block_passed= ts.tv_sec - battery->swelling_block_start; + else + battery->swelling_block_passed = 0xFFFFFFFF - battery->swelling_block_start + + ts.tv_sec; + + pr_info("%s: swelling block time : %ld secs\n", __func__, + battery->swelling_block_passed); + + if (battery->swelling_block_passed < BATT_SWELLING_BLOCK_TIME) { + pr_info("%s: swelling_timer doesn't reach 30 sec, stop charging\n", __func__); + } else { + /*if ((temperature <= BATT_SWELLING_HIGH_TEMP_RECOV) &&\ + (temperature >= BATT_SWELLING_LOW_TEMP_RECOV)) {*/ + if (temperature <= BATT_SWELLING_HIGH_TEMP_RECOV) { + pr_info("%s: swelling mode end. restart charging\n", __func__); + evaluate_charge(battery); + battery->swelling_block = false; + battery->swelling_mode = false; + /* restore 4.4V float voltage */ + val.intval = 4400; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_VOLTAGE_MAX, val); + } else if (battery->voltage_now < MV_TO_UV(BATT_SWELLING_RECHG_VOLTAGE)) { + pr_info("%s: swelling mode recharging start. Vbatt(%d)\n", + __func__, battery->voltage_now); + /* change 4.4V float voltage */ + val.intval = MV_TO_UV(4250); + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_VOLTAGE_MAX, val); + evaluate_charge(battery); + battery->swelling_block = false; + } + } + } +skip_swelling_chek: + dev_dbg(battery->dev, "%s end\n", __func__); +} +#endif + +#if defined(CONFIG_MACH_MONTBLANC) +extern unsigned int system_rev; +#endif +static bool sec_bat_temperature_check( + struct sec_battery_info *battery) +{ + int temp_value; + + if (battery->status == POWER_SUPPLY_STATUS_DISCHARGING) { + dev_dbg(battery->dev, + "%s: Charging Disabled\n", __func__); + return true; + } + + if (battery->health != POWER_SUPPLY_HEALTH_GOOD && + battery->health != POWER_SUPPLY_HEALTH_OVERHEAT && + battery->health != POWER_SUPPLY_HEALTH_COLD && + battery->health != POWER_SUPPLY_HEALTH_OVERHEATLIMIT) { + dev_dbg(battery->dev, "%s: No need to check\n", __func__); + return false; + } + + sec_bat_temperature(battery); + + switch (battery->pdata->temp_check_type) { + case SEC_BATTERY_TEMP_CHECK_ADC: + temp_value = battery->temp_adc; + break; + case SEC_BATTERY_TEMP_CHECK_TEMP: + temp_value = battery->temperature; + break; + case SEC_BATTERY_TEMP_CHECK_NONE: + temp_value = battery->temp_high_recovery; + break; + + default: + dev_err(battery->dev, + "%s: Invalid Temp Check Type\n", __func__); + return true; + } + + if (temp_value >= battery->temp_highlimit_threshold) { + if (battery->health != POWER_SUPPLY_HEALTH_OVERHEATLIMIT) { + if (battery->temp_highlimit_cnt < + battery->pdata->temp_check_count) + battery->temp_highlimit_cnt++; + dev_dbg(battery->dev, + "%s: highlimit count = %d\n", + __func__, battery->temp_highlimit_cnt); + } + } else if (temp_value >= battery->temp_high_threshold) { + if (battery->health == POWER_SUPPLY_HEALTH_OVERHEATLIMIT) { + if (temp_value <= battery->temp_highlimit_recovery) { + if (battery->temp_recover_cnt < + battery->pdata->temp_check_count) + battery->temp_recover_cnt++; + dev_dbg(battery->dev, + "%s: recovery count = %d\n", + __func__, battery->temp_recover_cnt); + } + } else if (battery->health != POWER_SUPPLY_HEALTH_OVERHEAT) { + if (battery->temp_high_cnt < + battery->pdata->temp_check_count) + battery->temp_high_cnt++; + dev_dbg(battery->dev, + "%s: high count = %d\n", + __func__, battery->temp_high_cnt); + } + } else if ((temp_value <= battery->temp_high_recovery) && + (temp_value >= battery->temp_low_recovery)) { + if (battery->health == POWER_SUPPLY_HEALTH_OVERHEAT || + battery->health == POWER_SUPPLY_HEALTH_COLD) { + if (battery->temp_recover_cnt < + battery->pdata->temp_check_count) + battery->temp_recover_cnt++; + dev_dbg(battery->dev, + "%s: recovery count = %d\n", + __func__, battery->temp_recover_cnt); + } + } else if (temp_value <= battery->temp_low_threshold) { + if (battery->health != POWER_SUPPLY_HEALTH_COLD) { + if (battery->temp_low_cnt < + battery->pdata->temp_check_count) + battery->temp_low_cnt++; + dev_dbg(battery->dev, + "%s: low count = %d\n", + __func__, battery->temp_low_cnt); + } + } else { + battery->temp_highlimit_cnt = 0; + battery->temp_high_cnt = 0; + battery->temp_low_cnt = 0; + battery->temp_recover_cnt = 0; + } + +#if defined(CONFIG_MACH_MONTBLANC) + if (battery->temp_high_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_OVERHEAT; + else if (battery->temp_low_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_COLD; + else if (battery->temp_recover_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_GOOD; +#else + if (battery->temp_highlimit_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_OVERHEATLIMIT; + else if (battery->temp_high_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_OVERHEAT; + else if (battery->temp_low_cnt >= + battery->pdata->temp_check_count) + battery->health = POWER_SUPPLY_HEALTH_COLD; + else if (battery->temp_recover_cnt >= + battery->pdata->temp_check_count) { + if (battery->health == POWER_SUPPLY_HEALTH_OVERHEATLIMIT) + battery->health = POWER_SUPPLY_HEALTH_OVERHEAT; + else + battery->health = POWER_SUPPLY_HEALTH_GOOD; + } +#endif + + if ((battery->health == POWER_SUPPLY_HEALTH_OVERHEAT) || + (battery->health == POWER_SUPPLY_HEALTH_COLD) || + (battery->health == POWER_SUPPLY_HEALTH_OVERHEATLIMIT)) { + if (battery->status != POWER_SUPPLY_STATUS_NOT_CHARGING) { + dev_info(battery->dev, + "%s: Unsafe Temperature\n", __func__); + /* change charging current to battery (default 0mA) */ + evaluate_charge(battery); + return false; + } + } else { + /* if recovered from not charging */ + if ((battery->health == POWER_SUPPLY_HEALTH_GOOD) && + (battery->charger_health == POWER_SUPPLY_HEALTH_GOOD) && + (battery->status == POWER_SUPPLY_STATUS_NOT_CHARGING)) { + dev_info(battery->dev, + "%s: Safe Temperature\n", __func__); + /* turn on charger by cable type */ + evaluate_charge(battery); + return false; + } + } + return true; +}; +#if !defined(CONFIG_SEC_FACTORY) +static void sec_bat_chg_temperature_check( + struct sec_battery_info *battery) +{ + if (battery->siop_level >= 100 && + ((battery->cable_type == POWER_SUPPLY_TYPE_HV_MAINS) || + (battery->cable_type == POWER_SUPPLY_TYPE_HV_ERR))) { + union power_supply_propval value; + if ((!battery->chg_limit) && + (battery->chg_temp > battery->pdata->chg_high_temp)) { + battery->chg_limit = true; + value.intval = battery->pdata->chg_charging_limit_current; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_MAX, value); + + dev_info(battery->dev,"%s: Chg current is reduced by Temp: %d\n", + __func__, battery->chg_temp); + } else if ((battery->chg_limit) && + (battery->chg_temp < battery->pdata->chg_high_temp_recovery)) { + battery->chg_limit = false; + value.intval = get_charging_info(battery, battery->cable_type)->input_current_limit; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_MAX, value); + + dev_info(battery->dev,"%s: Chg current is recovered by Temp: %d\n", + __func__, battery->chg_temp); + } + } else if (battery->chg_limit) { + battery->chg_limit = false; + } +} +#endif +static void sec_bat_event_program_alarm( + struct sec_battery_info *battery, int seconds) +{ +#if defined(ANDROID_ALARM_ACTIVATED) + ktime_t low_interval = ktime_set(seconds - 10, 0); + ktime_t slack = ktime_set(20, 0); + ktime_t next; + + next = ktime_add(battery->last_event_time, low_interval); + alarm_start_range(&battery->event_termination_alarm, + next, ktime_add(next, slack)); +#else + alarm_start(&battery->event_termination_alarm, + ktime_add(battery->last_event_time, ktime_set(seconds - 10, 0))); +#endif +} + +#if defined(ANDROID_ALARM_ACTIVATED) +static void sec_bat_event_expired_timer_func(struct alarm *alarm) +#else +static enum alarmtimer_restart sec_bat_event_expired_timer_func( + struct alarm *alarm, ktime_t now) +#endif +{ + struct sec_battery_info *battery = + container_of(alarm, struct sec_battery_info, + event_termination_alarm); + + battery->event &= (~battery->event_wait); + dev_info(battery->dev, + "%s: event expired (0x%x)\n", __func__, battery->event); + +#if !defined(ANDROID_ALARM_ACTIVATED) + return ALARMTIMER_NORESTART; +#endif +} + +static void sec_bat_event_set( + struct sec_battery_info *battery, int event, int enable) +{ + if (!battery->pdata->event_check) + return; + + /* ignore duplicated deactivation of same event + * only if the event is one last event + */ + if (!enable && (battery->event == battery->event_wait)) { + dev_info(battery->dev, + "%s: ignore duplicated deactivation of same event\n", + __func__); + return; + } + + alarm_cancel(&battery->event_termination_alarm); + battery->event &= (~battery->event_wait); + + if (enable) { + battery->event_wait = 0; + battery->event |= event; + + dev_info(battery->dev, + "%s: event set (0x%x)\n", __func__, battery->event); + } else { + if (battery->event == 0) { + dev_dbg(battery->dev, + "%s: nothing to clear\n", __func__); + return; /* nothing to clear */ + } + battery->event_wait = event; +#if defined(ANDROID_ALARM_ACTIVATED) + battery->last_event_time = alarm_get_elapsed_realtime(); +#else + battery->last_event_time = ktime_get_boottime(); +#endif + sec_bat_event_program_alarm(battery, + battery->pdata->event_waiting_time); + dev_info(battery->dev, + "%s: start timer (curr 0x%x, wait 0x%x)\n", + __func__, battery->event, battery->event_wait); + } +} + +static bool sec_bat_check_fullcharged_condition( + struct sec_battery_info *battery) +{ + int full_check_type; + + if (battery->charging_mode == SEC_BATTERY_CHARGING_1ST) + full_check_type = battery->pdata->full_check_type; + else + full_check_type = battery->pdata->full_check_type_2nd; + + switch (full_check_type) { + case SEC_BATTERY_FULLCHARGED_ADC: + case SEC_BATTERY_FULLCHARGED_FG_CURRENT: + case SEC_BATTERY_FULLCHARGED_SOC: + case SEC_BATTERY_FULLCHARGED_CHGGPIO: + case SEC_BATTERY_FULLCHARGED_CHGPSY: + break; + + /* If these is NOT full check type or NONE full check type, + * it is full-charged + */ + case SEC_BATTERY_FULLCHARGED_CHGINT: + case SEC_BATTERY_FULLCHARGED_TIME: + case SEC_BATTERY_FULLCHARGED_NONE: + default: + return true; + break; + } + + if (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_SOC) { + if (battery->capacity < + battery->pdata->full_condition_soc) { + dev_dbg(battery->dev, + "%s: Not enough SOC (%d%%)\n", + __func__, battery->capacity); + return false; + } + } + + if (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_VCELL) { + if (battery->voltage_now < + battery->pdata->full_condition_vcell) { + dev_dbg(battery->dev, + "%s: Not enough VCELL (%dmV)\n", + __func__, battery->voltage_now); + return false; + } + } + + if (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_AVGVCELL) { + if (battery->voltage_avg < + battery->pdata->full_condition_avgvcell) { + dev_dbg(battery->dev, + "%s: Not enough AVGVCELL (%dmV)\n", + __func__, battery->voltage_avg); + return false; + } + } + + if (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_OCV) { + if (battery->voltage_ocv < + battery->pdata->full_condition_ocv) { + dev_dbg(battery->dev, + "%s: Not enough OCV (%dmV)\n", + __func__, battery->voltage_ocv); + return false; + } + } + + return true; +} + +static void sec_bat_do_test_function( + struct sec_battery_info *battery) +{ + union power_supply_propval value; + + switch (battery->test_mode) { + case 1: + if (battery->status == POWER_SUPPLY_STATUS_CHARGING) { + sec_bat_set_charge(battery, false); + battery->status = + POWER_SUPPLY_STATUS_DISCHARGING; + } + break; + case 2: + if(battery->status == POWER_SUPPLY_STATUS_DISCHARGING) { + sec_bat_set_charge(battery, true); + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_STATUS, value); + battery->status = value.intval; + } + battery->test_mode = 0; + break; + case 3: // clear temp block + battery->health = POWER_SUPPLY_HEALTH_GOOD; + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + break; + case 4: + if(battery->status == POWER_SUPPLY_STATUS_DISCHARGING) { + sec_bat_set_charge(battery, true); + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_STATUS, value); + battery->status = value.intval; + } + break; + default: + pr_info("%s: error test: unknown state\n", __func__); + break; + } +} + +static bool sec_bat_time_management( + struct sec_battery_info *battery) +{ + unsigned long charging_time; + struct timespec ts; +#if defined(ANDROID_ALARM_ACTIVATED) + ktime_t current_time; + + current_time = alarm_get_elapsed_realtime(); + ts = ktime_to_timespec(current_time); +#else + get_monotonic_boottime(&ts); +#endif + + if (battery->charging_start_time == 0) { + dev_dbg(battery->dev, + "%s: Charging Disabled\n", __func__); + return true; + } + + if (ts.tv_sec >= battery->charging_start_time) + charging_time = ts.tv_sec - battery->charging_start_time; + else + charging_time = 0xFFFFFFFF - battery->charging_start_time + + ts.tv_sec; + + battery->charging_passed_time = charging_time; + + dev_dbg(battery->dev, + "%s: Charging Time : %ld secs\n", __func__, + battery->charging_passed_time); + + switch (battery->status) { + case POWER_SUPPLY_STATUS_FULL: + if (battery->is_recharging && (charging_time > + battery->pdata->recharging_total_time)) { + dev_info(battery->dev, + "%s: Recharging Timer Expired\n", __func__); + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + if (sec_bat_set_charge(battery, false)) { + dev_err(battery->dev, + "%s: Fail to Set Charger\n", __func__); + return true; + } + + return false; + } + break; + case POWER_SUPPLY_STATUS_CHARGING: + if ((battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL) && + (battery->is_recharging && (charging_time > + battery->pdata->recharging_total_time))) { + dev_info(battery->dev, + "%s: Recharging Timer Expired\n", __func__); + if (battery->capacity >= 100) + battery->status = POWER_SUPPLY_STATUS_FULL; + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + if (sec_bat_set_charge(battery, false)) { + dev_err(battery->dev, + "%s: Fail to Set Charger\n", __func__); + return true; + } + return false; + } else if (!battery->is_recharging && + (charging_time > battery->pdata->charging_total_time)) { + dev_info(battery->dev, + "%s: Charging Timer Expired\n", __func__); + if (battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_NOTIMEFULL) { + if (battery->capacity >= 100) + battery->status = + POWER_SUPPLY_STATUS_FULL; + } else + battery->status = POWER_SUPPLY_STATUS_FULL; + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + if (sec_bat_set_charge(battery, false)) { + dev_err(battery->dev, + "%s: Fail to Set Charger\n", __func__); + return true; + } + + return false; + } + if (battery->pdata->charging_reset_time) { + if (charging_time > battery->charging_next_time) { + /*reset current in charging status */ + battery->charging_next_time = + battery->charging_passed_time + + (battery->pdata->charging_reset_time); + + dev_dbg(battery->dev, + "%s: Reset charging current\n", + __func__); + if (evaluate_charge(battery)) { + dev_err(battery->dev, + "%s: Fail to Set Charger\n", + __func__); + return true; + } + } + } + break; + case POWER_SUPPLY_STATUS_DISCHARGING: + case POWER_SUPPLY_STATUS_NOT_CHARGING: + break; + default: + dev_err(battery->dev, + "%s: Undefine Battery Status\n", __func__); + return true; + } + + return true; +} + +static bool sec_bat_check_fullcharged( + struct sec_battery_info *battery) +{ + union power_supply_propval value; + int current_adc; + int full_check_type; + bool ret; + int err; + struct sec_charging_current *ci; + ret = false; + + if (!sec_bat_check_fullcharged_condition(battery)) + goto not_full_charged; + + if (battery->charging_mode == SEC_BATTERY_CHARGING_1ST) + full_check_type = battery->pdata->full_check_type; + else + full_check_type = battery->pdata->full_check_type_2nd; + + ci = get_charging_info(battery, battery->cable_type); + switch (full_check_type) { + case SEC_BATTERY_FULLCHARGED_ADC: + current_adc = + sec_bat_get_adc_value(battery, + SEC_BAT_ADC_CHANNEL_FULL_CHECK); + + dev_dbg(battery->dev, + "%s: Current ADC (%d)\n", + __func__, current_adc); + + if (current_adc < 0) + break; + battery->current_adc = current_adc; + + if (battery->current_adc < + (battery->charging_mode == + SEC_BATTERY_CHARGING_1ST ? + ci->full_check_current_1st : + ci->full_check_current_2nd)) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check ADC (%d)\n", + __func__, + battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; + + case SEC_BATTERY_FULLCHARGED_FG_CURRENT: + +#if defined(CONFIG_MACH_VIENNAEUR) || defined(CONFIG_MACH_VIENNAVZW) || defined(CONFIG_MACH_V2LTEEUR) + if ((battery->current_now > 0 && battery->current_now < + ci->full_check_current_1st) && + (battery->current_avg > 0 && battery->current_avg < + (battery->charging_mode == + SEC_BATTERY_CHARGING_1ST ? + ci->full_check_current_1st + 50 : + ci->full_check_current_2nd))) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check Current (%d)\n", + __func__, + battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; +#else + if ((battery->current_now > 0 && battery->current_now < + ci->full_check_current_1st) && + (battery->current_avg > 0 && battery->current_avg < + (battery->charging_mode == + SEC_BATTERY_CHARGING_1ST ? + ci->full_check_current_1st : + ci->full_check_current_2nd))) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check Current (%d)\n", + __func__, + battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; +#endif + + case SEC_BATTERY_FULLCHARGED_TIME: + if ((battery->charging_mode == + SEC_BATTERY_CHARGING_2ND ? + (battery->charging_passed_time - + battery->charging_fullcharged_time) : + battery->charging_passed_time) > + (battery->charging_mode == + SEC_BATTERY_CHARGING_1ST ? + ci->full_check_current_1st : + ci->full_check_current_2nd)) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check Time (%d)\n", + __func__, + battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; + + case SEC_BATTERY_FULLCHARGED_SOC: + if (battery->capacity <= + (battery->charging_mode == + SEC_BATTERY_CHARGING_1ST ? + ci->full_check_current_1st : + ci->full_check_current_2nd)) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check SOC (%d)\n", + __func__, + battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; + + case SEC_BATTERY_FULLCHARGED_CHGGPIO: + err = gpio_request( + battery->pdata->chg_gpio_full_check, + "GPIO_CHG_FULL"); + if (err) { + dev_err(battery->dev, + "%s: Error in Request of GPIO\n", __func__); + break; + } + if (!(gpio_get_value_cansleep( + battery->pdata->chg_gpio_full_check) ^ + !battery->pdata->chg_polarity_full_check)) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check GPIO (%d)\n", + __func__, battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + gpio_free(battery->pdata->chg_gpio_full_check); + break; + + case SEC_BATTERY_FULLCHARGED_CHGINT: + case SEC_BATTERY_FULLCHARGED_CHGPSY: + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_STATUS, value); + + if (value.intval == POWER_SUPPLY_STATUS_FULL) { + battery->full_check_cnt++; + dev_dbg(battery->dev, + "%s: Full Check Charger (%d)\n", + __func__, battery->full_check_cnt); + } else + battery->full_check_cnt = 0; + break; + + /* If these is NOT full check type or NONE full check type, + * it is full-charged + */ + case SEC_BATTERY_FULLCHARGED_NONE: + battery->full_check_cnt = 0; + ret = true; + break; + default: + dev_err(battery->dev, + "%s: Invalid Full Check\n", __func__); + break; + } + + if (battery->full_check_cnt >= + battery->pdata->full_check_count) { + battery->full_check_cnt = 0; + ret = true; + } + +not_full_charged: + return ret; +} + +static void sec_bat_do_fullcharged( + struct sec_battery_info *battery) +{ + union power_supply_propval value; + + /* To let charger/fuel gauge know the full status, + * set status before calling sec_bat_set_charge() + */ + battery->status = POWER_SUPPLY_STATUS_FULL; + + if (battery->charging_mode == SEC_BATTERY_CHARGING_1ST) { + battery->charging_mode = SEC_BATTERY_CHARGING_2ND; + battery->charging_fullcharged_time = + battery->charging_passed_time; + evaluate_charge(battery); + } else { + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + sec_bat_set_charge(battery, false); + + value.intval = POWER_SUPPLY_STATUS_FULL; + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_STATUS, value); + } + + /* platform can NOT get information of battery + * because wakeup time is too short to check uevent + * To make sure that target is wakeup if full-charged, + * activated wake lock in a few seconds + */ + if (battery->pdata->polling_type == SEC_BATTERY_MONITOR_ALARM) + wake_lock_timeout(&battery->vbus_wake_lock, HZ * 10); +} + +static bool sec_bat_fullcharged_check( + struct sec_battery_info *battery) +{ + if ((battery->charging_mode == SEC_BATTERY_CHARGING_NONE) || + (battery->status == POWER_SUPPLY_STATUS_NOT_CHARGING)) { + dev_dbg(battery->dev, + "%s: No Need to Check Full-Charged\n", __func__); + return true; + } + + if (sec_bat_check_fullcharged(battery)) + sec_bat_do_fullcharged(battery); + + dev_dbg(battery->dev, + "%s: Charging Mode : %s\n", __func__, + battery->is_recharging ? + sec_bat_charging_mode_str[SEC_BATTERY_CHARGING_RECHARGING] : + sec_bat_charging_mode_str[battery->charging_mode]); + + return true; +} + +static void sec_bat_get_battery_info( + struct sec_battery_info *battery) +{ + union power_supply_propval value; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_VOLTAGE_NOW, value); + battery->voltage_now = value.intval; + + value.intval = SEC_BATTEY_VOLTAGE_AVERAGE; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_VOLTAGE_AVG, value); + battery->voltage_avg = value.intval; + + value.intval = SEC_BATTEY_VOLTAGE_OCV; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_VOLTAGE_AVG, value); + battery->voltage_ocv = value.intval; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CURRENT_NOW, value); +#if defined(CONFIG_QPNP_BMS) + battery->current_now = value.intval / 1000; + battery->current_avg = value.intval / 1000; +#else + battery->current_now = value.intval / 1000; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CURRENT_AVG, value); + battery->current_avg = value.intval / 1000; +#endif + /* input current limit in charger */ + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_CURRENT_MAX, value); + battery->current_max = value.intval; + + switch (battery->pdata->thermal_source) { + case SEC_BATTERY_THERMAL_SOURCE_FG: + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_TEMP, value); + battery->temperature = value.intval; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_TEMP_AMBIENT, value); + battery->temper_amb = value.intval; + break; + case SEC_BATTERY_THERMAL_SOURCE_CALLBACK: + if (battery->pdata->get_temperature_callback) { + battery->pdata->get_temperature_callback( + POWER_SUPPLY_PROP_TEMP, &value); + battery->temperature = value.intval; + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_TEMP, value); + + battery->pdata->get_temperature_callback( + POWER_SUPPLY_PROP_TEMP_AMBIENT, &value); + battery->temper_amb = value.intval; + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_TEMP_AMBIENT, value); + } + break; + case SEC_BATTERY_THERMAL_SOURCE_ADC: + sec_bat_get_temperature_by_adc(battery, + SEC_BAT_ADC_CHANNEL_TEMP, &value); + battery->temperature = value.intval; +#if !defined(CONFIG_QPNP_BMS) + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_TEMP, value); +#endif + sec_bat_get_temperature_by_adc(battery, + SEC_BAT_ADC_CHANNEL_TEMP_AMBIENT, &value); + battery->temper_amb = value.intval; +#if !defined(CONFIG_QPNP_BMS) + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_TEMP_AMBIENT, value); +#endif + break; + default: + break; + } + + if (battery->pdata->chg_temp_check) { + sec_bat_get_temperature_by_adc(battery, + SEC_BAT_ADC_CHANNEL_CHG_TEMP, &value); + battery->chg_temp = value.intval; + } + /* To get SOC value (NOT raw SOC), need to reset value */ + value.intval = 0; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CAPACITY, value); + +#if defined(CONFIG_MACH_VIENNAEUR) || defined(CONFIG_MACH_VIENNAVZW) || defined(CONFIG_MACH_V2) || \ + defined(CONFIG_SEC_MILLET_PROJECT) || defined(CONFIG_SEC_MATISSE_PROJECT) || defined(CONFIG_SEC_TRLTE_PROJECT) || \ + defined(CONFIG_SEC_TBLTE_PROJECT) + /* if the battery status was full, and SOC wasn't 100% yet, + then ignore FG SOC, and report (previous SOC +1)% */ + if (battery->status != POWER_SUPPLY_STATUS_FULL) + battery->capacity = value.intval; + else if (battery->capacity != 100) { + battery->capacity++; + pr_info("%s: forced full-charged sequence for the capacity(%d)\n", __func__, battery->capacity); + } +#else + battery->capacity = value.intval; +#endif + + dev_dbg(battery->dev, + "%s:Vnow(%dmV),Inow(%dmA),Imax(%dmA),SOC(%d%%),Tbat(%d),is_hc_usb(%d)\n", + __func__, + battery->voltage_now, battery->current_now, + battery->current_max, battery->capacity, + battery->temperature, battery->is_hc_usb); + dev_dbg(battery->dev, + "%s,Vavg(%dmV),Vocv(%dmV),Tamb(%d)," + "Iavg(%dmA),Iadc(%d)\n", + battery->present ? "Connected" : "Disconnected", + battery->voltage_avg, battery->voltage_ocv, + battery->temper_amb, + battery->current_avg, battery->current_adc); +} + +static void sec_bat_polling_work(struct work_struct *work) +{ + struct sec_battery_info *battery = container_of( + work, struct sec_battery_info, polling_work.work); + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + dev_dbg(battery->dev, "%s: Activated\n", __func__); +} + +static void sec_bat_program_alarm( + struct sec_battery_info *battery, int seconds) +{ +#if defined(ANDROID_ALARM_ACTIVATED) + ktime_t low_interval = ktime_set(seconds, 0); + ktime_t slack = ktime_set(10, 0); + ktime_t next; + + next = ktime_add(battery->last_poll_time, low_interval); + alarm_start_range(&battery->polling_alarm, + next, ktime_add(next, slack)); +#else + alarm_start(&battery->polling_alarm, + ktime_add(battery->last_poll_time, ktime_set(seconds, 0))); +#endif +} + +static unsigned int sec_bat_get_polling_time( + struct sec_battery_info *battery) +{ + if (battery->status == + POWER_SUPPLY_STATUS_FULL) + battery->polling_time = + battery->pdata->polling_time[ + POWER_SUPPLY_STATUS_CHARGING]; + else + battery->polling_time = + battery->pdata->polling_time[ + battery->status]; + + battery->polling_short = true; + + switch (battery->status) { + case POWER_SUPPLY_STATUS_CHARGING: + if (battery->polling_in_sleep) + battery->polling_short = false; + break; + case POWER_SUPPLY_STATUS_DISCHARGING: + if (battery->polling_in_sleep && (battery->ps_enable != true)) + battery->polling_time = + battery->pdata->polling_time[ + SEC_BATTERY_POLLING_TIME_SLEEP]; + else + battery->polling_time = + battery->pdata->polling_time[ + battery->status]; + battery->polling_short = false; + break; + case POWER_SUPPLY_STATUS_FULL: + if (battery->polling_in_sleep) { + if (!(battery->pdata->full_condition_type & + SEC_BATTERY_FULL_CONDITION_NOSLEEPINFULL) && + battery->charging_mode == + SEC_BATTERY_CHARGING_NONE) + battery->polling_time = + battery->pdata->polling_time[ + SEC_BATTERY_POLLING_TIME_SLEEP]; + battery->polling_short = false; + } else { + if (battery->charging_mode == + SEC_BATTERY_CHARGING_NONE) + battery->polling_short = false; + } + break; + } + + if (battery->polling_short) + return battery->pdata->polling_time[ + SEC_BATTERY_POLLING_TIME_BASIC]; + /* set polling time to 46s to reduce current noise on wc */ + else if (battery->cable_type == POWER_SUPPLY_TYPE_WIRELESS && + battery->status == POWER_SUPPLY_STATUS_CHARGING) + battery->polling_time = 46; + + return battery->polling_time; +} + +static bool sec_bat_is_short_polling( + struct sec_battery_info *battery) +{ + /* Change the full and short monitoring sequence + * Originally, full monitoring was the last time of polling_count + * But change full monitoring to first time + * because temperature check is too late + */ + if (!battery->polling_short || battery->polling_count == 1) + return false; + else + return true; +} + +static void sec_bat_update_polling_count( + struct sec_battery_info *battery) +{ + /* do NOT change polling count in sleep + * even though it is short polling + * to keep polling count along sleep/wakeup + */ + if (battery->polling_short && battery->polling_in_sleep) + return; + + if (battery->polling_short && + ((battery->polling_time / + battery->pdata->polling_time[ + SEC_BATTERY_POLLING_TIME_BASIC]) + > battery->polling_count)) + battery->polling_count++; + else + battery->polling_count = 1; /* initial value = 1 */ +} + +static void sec_bat_set_polling( + struct sec_battery_info *battery) +{ + unsigned int polling_time_temp; + + dev_dbg(battery->dev, "%s: Start\n", __func__); + + polling_time_temp = sec_bat_get_polling_time(battery); + + dev_dbg(battery->dev, + "%s: Status:%s, Sleep:%s, Charging:%s, Short Poll:%s\n", + __func__, sec_bat_status_str[battery->status], + battery->polling_in_sleep ? "Yes" : "No", + (battery->charging_mode == + SEC_BATTERY_CHARGING_NONE) ? "No" : "Yes", + battery->polling_short ? "Yes" : "No"); + dev_dbg(battery->dev, + "%s: Polling time %d/%d sec.\n", __func__, + battery->polling_short ? + (polling_time_temp * battery->polling_count) : + polling_time_temp, battery->polling_time); + + /* To sync with log above, + * change polling count after log is displayed + * Do NOT update polling count in initial monitor + */ + if (!battery->pdata->monitor_initial_count) + sec_bat_update_polling_count(battery); + else + dev_dbg(battery->dev, + "%s: Initial monitor %d times left.\n", __func__, + battery->pdata->monitor_initial_count); + + switch (battery->pdata->polling_type) { + case SEC_BATTERY_MONITOR_WORKQUEUE: + if (battery->pdata->monitor_initial_count) { + battery->pdata->monitor_initial_count--; + schedule_delayed_work(&battery->polling_work, HZ); + } else + schedule_delayed_work(&battery->polling_work, + polling_time_temp * HZ); + break; + case SEC_BATTERY_MONITOR_ALARM: +#if defined(ANDROID_ALARM_ACTIVATED) + battery->last_poll_time = alarm_get_elapsed_realtime(); +#else + battery->last_poll_time = ktime_get_boottime(); +#endif + + if (battery->pdata->monitor_initial_count) { + battery->pdata->monitor_initial_count--; + sec_bat_program_alarm(battery, 1); + } else + sec_bat_program_alarm(battery, polling_time_temp); + break; + case SEC_BATTERY_MONITOR_TIMER: + break; + default: + break; + } + dev_dbg(battery->dev, "%s: End\n", __func__); +} +#if defined(CONFIG_BATTERY_SWELLING) +static void sec_bat_swelling_fullcharged_check(struct sec_battery_info *battery) +{ + union power_supply_propval value; + ktime_t current_time; + struct timespec ts; + + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_STATUS, value); + + if (value.intval == POWER_SUPPLY_STATUS_FULL) { + battery->swelling_full_check_cnt++; + pr_info("%s: Swelling mode full-charged check (%d)\n", + __func__, battery->swelling_full_check_cnt); + } else + battery->swelling_full_check_cnt = 0; + + if (battery->swelling_full_check_cnt >= + battery->pdata->full_check_count) { + battery->swelling_full_check_cnt = 0; + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + sec_bat_set_charge(battery, false); + battery->swelling_block = true; + /* Initialize swelling charging-block timer */ + current_time = ktime_get_boottime(); + ts = ktime_to_timespec(current_time); + battery->swelling_block_start = ts.tv_sec; + } +} +#endif +static void sec_bat_monitor_work( + struct work_struct *work) +{ + struct sec_battery_info *battery = + container_of(work, struct sec_battery_info, + monitor_work.work); + static struct timespec old_ts; + struct timespec c_ts; + + dev_dbg(battery->dev, "%s: Start\n", __func__); +#if defined(ANDROID_ALARM_ACTIVATED) + c_ts = ktime_to_timespec(alarm_get_elapsed_realtime()); +#else + c_ts = ktime_to_timespec(ktime_get_boottime()); +#endif + + /* monitor once after wakeup */ + if (battery->polling_in_sleep) { + battery->polling_in_sleep = false; + if ((battery->status == POWER_SUPPLY_STATUS_DISCHARGING) && + (battery->ps_enable != true)) { + if ((unsigned long)(c_ts.tv_sec - old_ts.tv_sec) < 10 * 60) { + pr_info("Skip monitor_work(%ld)\n", + c_ts.tv_sec - old_ts.tv_sec); + goto skip_monitor; + } + } + } + /* update last monitor time */ + old_ts = c_ts; + + sec_bat_get_battery_info(battery); + + /* 0. test mode */ + if (battery->test_mode) { + dev_err(battery->dev, "%s: Test Mode\n", __func__); + sec_bat_do_test_function(battery); + if (battery->test_mode != 0) + goto continue_monitor; + } + + /* 1. battery check */ + if (!sec_bat_battery_cable_check(battery)) + goto continue_monitor; + + /* 2. voltage check */ + if (!sec_bat_voltage_check(battery)) + goto continue_monitor; + + /* monitor short routine in initial monitor */ + if (battery->pdata->monitor_initial_count || + sec_bat_is_short_polling(battery)) + goto continue_monitor; + + /* 3. time management */ + if (!sec_bat_time_management(battery)) + goto continue_monitor; + + /* 4. temperature check */ + if (!sec_bat_temperature_check(battery)) + goto continue_monitor; + +#if defined(CONFIG_BATTERY_SWELLING) + sec_bat_swelling_check(battery, battery->temperature); + + if (battery->swelling_mode) + sec_bat_swelling_fullcharged_check(battery); + else +#endif + /* 5. full charging check */ + sec_bat_fullcharged_check(battery); + + /* 6. additional check */ + if (battery->pdata->monitor_additional_check) + battery->pdata->monitor_additional_check(); + +#if !defined(CONFIG_SEC_FACTORY) + /* 7. charger temperature check */ + if (battery->pdata->chg_temp_check) + sec_bat_chg_temperature_check(battery); +#endif + +continue_monitor: + dev_dbg(battery->dev, + "%s: Status(%s), Mode(%s), Health(%s), Cable(%d), Vendor(%s), level(%d%%)\n", + __func__, + sec_bat_status_str[battery->status], + sec_bat_charging_mode_str[battery->charging_mode], + sec_bat_health_str[battery->health], + battery->cable_type, battery->pdata->vendor, battery->siop_level); + + dev_dbg(battery->dev, + "%s: stability_test(%d), eng_not_full_status(%d) slate_mode(%d)\n", + __func__, battery->stability_test, battery->eng_not_full_status, + battery->slate_mode); + + evaluate_charge(battery); + + power_supply_changed(battery->psy_bat); + +skip_monitor: + sec_bat_set_polling(battery); + + wake_unlock(&battery->monitor_wake_lock); + + dev_dbg(battery->dev, "%s: End\n", __func__); + + return; +} + +#if defined(ANDROID_ALARM_ACTIVATED) +static void sec_bat_alarm(struct alarm *alarm) +#else +static enum alarmtimer_restart sec_bat_alarm( + struct alarm *alarm, ktime_t now) + +#endif +{ + struct sec_battery_info *battery = container_of(alarm, + struct sec_battery_info, polling_alarm); + + dev_dbg(battery->dev, + "%s\n", __func__); + + /* In wake up, monitor work will be queued in complete function + * To avoid duplicated queuing of monitor work, + * do NOT queue monitor work in wake up by polling alarm + */ + if (!battery->polling_in_sleep) { + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + dev_dbg(battery->dev, "%s: Activated\n", __func__); + } +#if !defined(ANDROID_ALARM_ACTIVATED) + return ALARMTIMER_NORESTART; +#endif +} + + +static void sec_bat_cable_work(struct work_struct *work) +{ + struct sec_battery_info *battery = container_of(work, + struct sec_battery_info, cable_work.work); + union power_supply_propval val; + int wl_cur, wr_cur, current_cable_type; + int sleep_check_count; + + dev_dbg(battery->dev, "%s: Start\n", __func__); + + /* check fuelgauge in sleep for i2c */ + sleep_check_count = 10; + while ((battery->fuelgauge_in_sleep == true) && (sleep_check_count > 0)) { + dev_info(battery->dev, "%s in suspend status count (%d)\n", + __func__, sleep_check_count); + sleep_check_count--; + msleep(50); + } + + wl_cur = get_charging_info(battery, POWER_SUPPLY_TYPE_WIRELESS)->input_current_limit; + wr_cur = get_charging_info(battery, battery->wire_status)->input_current_limit; + if (battery->wc_status && battery->wc_enable && + (wl_cur > wr_cur)) + current_cable_type = POWER_SUPPLY_TYPE_WIRELESS; + else + current_cable_type = battery->wire_status; + + if (current_cable_type == battery->cable_type) { + dev_dbg(battery->dev, + "%s: Cable is NOT Changed(%d)\n", + __func__, battery->cable_type); + /* Do NOT activate cable work for NOT changed */ + goto end_of_cable_work; + } + + battery->cable_type = current_cable_type; + sec_bat_check_cable_result_callback(battery->dev, battery->cable_type); + +#ifdef CONFIG_SAMSUNG_BATTERY_DISALLOW_DEEP_SLEEP + if (get_charging_info(battery, battery->cable_type)->fast_charging_current != 0) { + pr_info("QMCK: block xo shutdown\n"); + if (!xo_chr) + xo_chr = clk_get_sys("charger", "xo_chr"); // Disable xo shutdown + clk_prepare_enable(xo_chr); + clk_set_rate(xo_chr, 19200000); + } else { + pr_info("QMCK: Enable xo shutdown\n"); + if (xo_chr) { + clk_disable_unprepare(xo_chr); + clk_put(xo_chr); + } + } +#endif + + /* platform can NOT get information of cable connection + * because wakeup time is too short to check uevent + * To make sure that target is wakeup + * if cable is connected and disconnected, + * activated wake lock in a few seconds + */ + wake_lock_timeout(&battery->vbus_wake_lock, HZ * 10); + + if (battery->cable_type == POWER_SUPPLY_TYPE_BATTERY || + ((battery->pdata->cable_check_type & + SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE) && + battery->cable_type == POWER_SUPPLY_TYPE_UNKNOWN)) { + if (battery->status == POWER_SUPPLY_STATUS_FULL) { + val.intval = POWER_SUPPLY_TYPE_BATTERY; + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_CHARGE_FULL, val); + + /* To get SOC value (NOT raw SOC), need to reset value */ + val.intval = 0; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CAPACITY, val); + battery->capacity = val.intval; + } + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + battery->health = POWER_SUPPLY_HEALTH_GOOD; +#if defined(CONFIG_BATTERY_SWELLING) + battery->swelling_mode = false; +#endif + if (evaluate_charge(battery)) + goto end_of_cable_work; + } else if ((battery->slate_mode == true) && + (battery->cable_type == POWER_SUPPLY_TYPE_USB)) { + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + battery->wire_status = POWER_SUPPLY_TYPE_BATTERY; + battery->cable_type = POWER_SUPPLY_TYPE_BATTERY; + + val.intval = 0; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_NOW, val); + + dev_info(battery->dev, + "%s:slate mode on\n",__func__); + } else { + /* Do NOT display the charging icon when OTG is enabled */ + if (battery->cable_type == POWER_SUPPLY_TYPE_OTG) { + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + } else if (battery->cable_type == POWER_SUPPLY_TYPE_HV_PREPARE_MAINS) { + val.intval = battery->cable_type; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, val); + dev_info(battery->dev, + "%s: Prepare AFC cable plugin\n", __func__); + goto end_of_cable_work; + } else { + if (battery->pdata->full_check_type != + SEC_BATTERY_FULLCHARGED_NONE) + battery->charging_mode = + SEC_BATTERY_CHARGING_1ST; + else + battery->charging_mode = + SEC_BATTERY_CHARGING_2ND; + battery->status = POWER_SUPPLY_STATUS_CHARGING; + } + +#if defined(CONFIG_BATTERY_SWELLING) + if (!battery->swelling_block) +#endif + if (evaluate_charge(battery)) + goto end_of_cable_work; + +#if defined(ANDROID_ALARM_ACTIVATED) + /* No need for wakelock in Alarm */ + if (battery->pdata->polling_type != SEC_BATTERY_MONITOR_ALARM) + wake_lock(&battery->vbus_wake_lock); +#endif + } + + /* polling time should be reset when cable is changed + * polling_in_sleep should be reset also + * before polling time is re-calculated + * to prevent from counting 1 for events + * right after cable is connected + */ + battery->polling_in_sleep = false; + sec_bat_get_polling_time(battery); + + dev_dbg(battery->dev, + "%s: Status:%s, Sleep:%s, Charging:%s, Short Poll:%s\n", + __func__, sec_bat_status_str[battery->status], + battery->polling_in_sleep ? "Yes" : "No", + (battery->charging_mode == + SEC_BATTERY_CHARGING_NONE) ? "No" : "Yes", + battery->polling_short ? "Yes" : "No"); + dev_dbg(battery->dev, + "%s: Polling time is reset to %d sec.\n", __func__, + battery->polling_time); + + battery->polling_count = 1; /* initial value = 1 */ + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, + msecs_to_jiffies(500)); +end_of_cable_work: + wake_unlock(&battery->cable_wake_lock); + dev_dbg(battery->dev, "%s: End\n", __func__); +} + +static void sec_bat_vbus_detect_work(struct work_struct *work) +{ + struct sec_battery_info *battery = container_of(work, + struct sec_battery_info, vbus_detect_work.work); + + dev_dbg(battery->dev, "%s\n", __func__); + + sec_bat_check_cable_callback(battery); + wake_unlock(&battery->vbus_detect_wake_lock); +} + +ssize_t sec_bat_show_attrs(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sec_battery_info *battery = dev_get_drvdata(dev); + const ptrdiff_t offset = attr - sec_battery_attrs; + union power_supply_propval value; + int i = 0; + + switch (offset) { + case BATT_RESET_SOC: + break; + case BATT_READ_RAW_SOC: + { + union power_supply_propval value; + + value.intval = + SEC_FUELGAUGE_CAPACITY_TYPE_RAW; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CAPACITY, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + } + break; + case BATT_READ_ADJ_SOC: + break; + case BATT_TYPE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%s\n", + battery->pdata->vendor); + break; + case BATT_VFOCV: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->voltage_ocv); + break; + case BATT_VOL_ADC: + break; + case BATT_VOL_ADC_CAL: + break; + case BATT_VOL_AVER: + break; + case BATT_VOL_ADC_AVER: + break; + + case BATT_CURRENT_UA_NOW: + { + union power_supply_propval value; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CURRENT_NOW, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + } + break; + case BATT_CURRENT_UA_AVG: + { + union power_supply_propval value; + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_CURRENT_AVG, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + } + break; + + case BATT_TEMP: + switch (battery->pdata->thermal_source) { + case SEC_BATTERY_THERMAL_SOURCE_FG: + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_TEMP, value); + break; + case SEC_BATTERY_THERMAL_SOURCE_CALLBACK: + if (battery->pdata->get_temperature_callback) { + battery->pdata->get_temperature_callback( + POWER_SUPPLY_PROP_TEMP, &value); + } + break; + case SEC_BATTERY_THERMAL_SOURCE_ADC: + sec_bat_get_temperature_by_adc(battery, + SEC_BAT_ADC_CHANNEL_TEMP, &value); + break; + default: + break; + } + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + break; + case BATT_TEMP_ADC: + /* + If F/G is used for reading the temperature and + compensation table is used, + the raw value that isn't compensated can be read by + POWER_SUPPLY_PROP_TEMP_AMBIENT + */ + switch (battery->pdata->thermal_source) { + case SEC_BATTERY_THERMAL_SOURCE_FG: + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_TEMP_AMBIENT, value); + battery->temp_adc = value.intval; + break; + default: + break; + } + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->temp_adc); + break; + case BATT_TEMP_AVER: + break; + case BATT_TEMP_ADC_AVER: + break; + case BATT_CHG_TEMP: + if (battery->pdata->chg_temp_check) { + sec_bat_get_temperature_by_adc(battery, + SEC_BAT_ADC_CHANNEL_CHG_TEMP, &value); + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + } else { + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + 0); + } + break; + case BATT_CHG_TEMP_ADC: + if (battery->pdata->chg_temp_check) { + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->chg_temp_adc); + } else { + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + 0); + } + break; + case BATT_VF_ADC: + break; + case BATT_SLATE_MODE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->slate_mode); + break; + + case BATT_LP_CHARGING: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + sec_bat_is_lpm(battery) ? 1 : 0); + break; + case SIOP_ACTIVATED: + break; + case SIOP_LEVEL: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->siop_level); + break; + case BATT_CHARGING_SOURCE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->cable_type); + break; + case FG_REG_DUMP: + break; + case FG_RESET_CAP: + break; + case FG_CAPACITY: + { + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_ENERGY_FULL, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "0x%04x ", + value.intval/370); + + /* not empty, returns REMCAP_MIX_REG*/ + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "0x%04x ", + value.intval/370); + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_ENERGY_AVG, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "0x%04x ", + value.intval/370); + + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_ENERGY_NOW, value); + + i += scnprintf(buf + i, PAGE_SIZE - i, "0x%04x\n", + value.intval/370); + } + break; + case AUTH: + break; + case CHG_CURRENT_ADC: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->current_adc); + break; + case WC_ADC: + break; + case WC_STATUS: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->cable_type == POWER_SUPPLY_TYPE_WIRELESS)); + break; + case WC_ENABLE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->wc_enable); + break; + case HV_CHARGER_STATUS: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + ((battery->cable_type == POWER_SUPPLY_TYPE_HV_MAINS) || + (battery->cable_type == POWER_SUPPLY_TYPE_HV_ERR)) ? 1 : 0); + break; + case HV_CHARGER_SET: + break; + case FACTORY_MODE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->factory_mode); + break; + case STORE_MODE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->store_mode); + break; + case UPDATE: + break; + case TEST_MODE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->test_mode); + break; + + case BATT_EVENT_CALL: + case BATT_EVENT_2G_CALL: + case BATT_EVENT_TALK_GSM: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_2G_CALL) ? 1 : 0); + break; + case BATT_EVENT_3G_CALL: + case BATT_EVENT_TALK_WCDMA: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_3G_CALL) ? 1 : 0); + break; + case BATT_EVENT_MUSIC: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_MUSIC) ? 1 : 0); + break; + case BATT_EVENT_VIDEO: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_VIDEO) ? 1 : 0); + break; + case BATT_EVENT_BROWSER: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_BROWSER) ? 1 : 0); + break; + case BATT_EVENT_HOTSPOT: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_HOTSPOT) ? 1 : 0); + break; + case BATT_EVENT_CAMERA: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_CAMERA) ? 1 : 0); + break; + case BATT_EVENT_CAMCORDER: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_CAMCORDER) ? 1 : 0); + break; + case BATT_EVENT_DATA_CALL: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_DATA_CALL) ? 1 : 0); + break; + case BATT_EVENT_WIFI: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_WIFI) ? 1 : 0); + break; + case BATT_EVENT_WIBRO: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_WIBRO) ? 1 : 0); + break; + case BATT_EVENT_LTE: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_LTE) ? 1 : 0); + break; + case BATT_EVENT_LCD: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_LCD) ? 1 : 0); + break; + case BATT_EVENT_GPS: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + (battery->event & EVENT_GPS) ? 1 : 0); + break; + case BATT_EVENT: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->event); + break; + case BATT_TEMP_TABLE: + i += scnprintf(buf + i, PAGE_SIZE - i, + "%d %d %d %d %d %d %d %d %d %d %d %d\n", + battery->pdata->temp_high_threshold_event, + battery->pdata->temp_high_recovery_event, + battery->pdata->temp_low_threshold_event, + battery->pdata->temp_low_recovery_event, + battery->pdata->temp_high_threshold_normal, + battery->pdata->temp_high_recovery_normal, + battery->pdata->temp_low_threshold_normal, + battery->pdata->temp_low_recovery_normal, + battery->pdata->temp_high_threshold_lpm, + battery->pdata->temp_high_recovery_lpm, + battery->pdata->temp_low_threshold_lpm, + battery->pdata->temp_low_recovery_lpm); + break; + case BATT_HIGH_CURRENT_USB: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->is_hc_usb); + break; +#if defined(CONFIG_SAMSUNG_BATTERY_ENG_TEST) + case BATT_TEST_CHARGE_CURRENT: + { + union power_supply_propval value; + + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_CURRENT_NOW, value); + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + value.intval); + } + break; +#endif + case BATT_STABILITY_TEST: + i += scnprintf(buf + i, PAGE_SIZE - i, "%d\n", + battery->stability_test); + break; + default: + i = -EINVAL; + } + + return i; +} +void update_external_temp_table(struct sec_battery_info *battery, int temp[]) +{ + battery->pdata->temp_high_threshold_event = temp[0]; + battery->pdata->temp_high_recovery_event = temp[1]; + battery->pdata->temp_low_threshold_event = temp[2]; + battery->pdata->temp_low_recovery_event = temp[3]; + battery->pdata->temp_high_threshold_normal = temp[4]; + battery->pdata->temp_high_recovery_normal = temp[5]; + battery->pdata->temp_low_threshold_normal = temp[6]; + battery->pdata->temp_low_recovery_normal = temp[7]; + battery->pdata->temp_high_threshold_lpm = temp[8]; + battery->pdata->temp_high_recovery_lpm = temp[9]; + battery->pdata->temp_low_threshold_lpm = temp[10]; + battery->pdata->temp_low_recovery_lpm = temp[11]; + + if (battery->pdata->temp_high_threshold_event != + battery->pdata->temp_high_threshold_normal) + battery->pdata->event_check = 1; +} + +ssize_t sec_bat_store_attrs( + struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct sec_battery_info *battery = dev_get_drvdata(dev); + const ptrdiff_t offset = attr - sec_battery_attrs; + int ret = -EINVAL; + int x = 0; + int t[12]; + switch (offset) { + case BATT_RESET_SOC: + /* Do NOT reset fuel gauge in charging mode */ + if ((battery->cable_type == POWER_SUPPLY_TYPE_BATTERY) || + sec_bat_check_jig_status()) { +#if defined(CONFIG_QPNP_BMS) + extern void bms_quickstart(void); + battery->voltage_now = MV_TO_UV(1234); + battery->voltage_avg = MV_TO_UV(1234); + power_supply_changed(&battery->psy_bat); + bms_quickstart(); +#else + union power_supply_propval value; + battery->voltage_now = MV_TO_UV(1234); + battery->voltage_avg = MV_TO_UV(1234); + power_supply_changed(battery->psy_bat); + + value.intval = + SEC_FUELGAUGE_CAPACITY_TYPE_RESET; + psy_do_property(battery->pdata->fuelgauge_name, set, + POWER_SUPPLY_PROP_CAPACITY, value); +#endif + dev_info(battery->dev,"do reset SOC\n"); + /* update battery info */ + sec_bat_get_battery_info(battery); + } + ret = count; + break; + case BATT_READ_RAW_SOC: + break; + case BATT_READ_ADJ_SOC: + break; + case BATT_TYPE: + break; + case BATT_VFOCV: + break; + case BATT_VOL_ADC: + break; + case BATT_VOL_ADC_CAL: + break; + case BATT_VOL_AVER: + break; + case BATT_VOL_ADC_AVER: + break; + case BATT_CURRENT_UA_NOW: + break; + case BATT_CURRENT_UA_AVG: + break; + case BATT_TEMP: + break; + case BATT_TEMP_ADC: + break; + case BATT_TEMP_AVER: + break; + case BATT_TEMP_ADC_AVER: + break; + case BATT_CHG_TEMP: + break; + case BATT_CHG_TEMP_ADC: + break; + case BATT_VF_ADC: + break; + case BATT_SLATE_MODE: + if (sscanf(buf, "%d\n", &x) == 1) { + union power_supply_propval value; + if (x == 1) { + value.intval = POWER_SUPPLY_TYPE_BATTERY; + battery->slate_mode = true; + } else if (x == 0) { + value.intval = POWER_SUPPLY_TYPE_USB; + battery->slate_mode = false; + } else { + dev_info(battery->dev, + "%s: SLATE MODE unknown command\n", + __func__); + return -EINVAL; + } + psy_do_property("battery", set, + POWER_SUPPLY_PROP_ONLINE, value); + if(battery->slate_mode == true) { + value.intval = 0; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_NOW, + value); + } + ret = count; + } + break; + + case BATT_LP_CHARGING: + break; + case SIOP_ACTIVATED: + break; + case SIOP_LEVEL: + +#if defined(CONFIG_TMM_CHG_CTRL) + if(tuner_running_status==TUNER_IS_OFF) { + dev_dbg(battery->dev, + "%s: tmm tuner is off!\n", __func__); +#endif + + if (sscanf(buf, "%d\n", &x) == 1) { + union power_supply_propval value; + dev_info(battery->dev, + "%s: siop level: %d\n", __func__, x); + if (battery->capacity <= 5) + battery->siop_level = 100; + else if (x >= 0 && x <= 100) + battery->siop_level = x; + else + battery->siop_level = 100; + value.intval = battery->siop_level; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, value); + ret = count; + } + +#if defined(CONFIG_TMM_CHG_CTRL) + } +#endif + + break; + case BATT_CHARGING_SOURCE: + break; + case FG_REG_DUMP: + break; + case FG_RESET_CAP: + break; + case FG_CAPACITY: + break; + case AUTH: + break; + case CHG_CURRENT_ADC: + break; + case WC_ADC: + break; + case WC_STATUS: + break; + case WC_ENABLE: + if (sscanf(buf, "%d\n", &x) == 1) { + if (x == 0) { + battery->wc_enable = false; + } else if (x == 1) { + battery->wc_enable = true; + } else { + dev_info(battery->dev, + "%s: WPC ENABLE unknown command\n", + __func__); + return -EINVAL; + } + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + ret = count; + } + break; + case HV_CHARGER_STATUS: + break; + case HV_CHARGER_SET: + if (sscanf(buf, "%d\n", &x) == 1) { + dev_info(battery->dev, + "%s: HV_CHARGER_SET(%d)\n", __func__, x); + if (x == 1) { + battery->wire_status = POWER_SUPPLY_TYPE_HV_MAINS; + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->cable_work, 0); + } else { + battery->wire_status = POWER_SUPPLY_TYPE_BATTERY; + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->cable_work, 0); + } + ret = count; + } + break; + case FACTORY_MODE: + if (sscanf(buf, "%d\n", &x) == 1) { + battery->factory_mode = x ? true : false; + ret = count; + } + break; + case STORE_MODE: + if (sscanf(buf, "%d\n", &x) == 1) { + battery->store_mode = x ? true : false; + ret = count; + } + break; + case UPDATE: + if (sscanf(buf, "%d\n", &x) == 1) { + /* update battery info */ + sec_bat_get_battery_info(battery); + ret = count; + } + break; + case TEST_MODE: + if (sscanf(buf, "%d\n", &x) == 1) { + battery->test_mode = x; + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->monitor_work, 0); + ret = count; + } + break; + + case BATT_EVENT_CALL: + case BATT_EVENT_2G_CALL: + case BATT_EVENT_TALK_GSM: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_2G_CALL, x); + ret = count; + } + break; + case BATT_EVENT_3G_CALL: + case BATT_EVENT_TALK_WCDMA: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_3G_CALL, x); + ret = count; + } + break; + case BATT_EVENT_MUSIC: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_MUSIC, x); + ret = count; + } + break; + case BATT_EVENT_VIDEO: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_VIDEO, x); + ret = count; + } + break; + case BATT_EVENT_BROWSER: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_BROWSER, x); + ret = count; + } + break; + case BATT_EVENT_HOTSPOT: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_HOTSPOT, x); + ret = count; + } + break; + case BATT_EVENT_CAMERA: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_CAMERA, x); + ret = count; + } + break; + case BATT_EVENT_CAMCORDER: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_CAMCORDER, x); + ret = count; + } + break; + case BATT_EVENT_DATA_CALL: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_DATA_CALL, x); + ret = count; + } + break; + case BATT_EVENT_WIFI: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_WIFI, x); + ret = count; + } + break; + case BATT_EVENT_WIBRO: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_WIBRO, x); + ret = count; + } + break; + case BATT_EVENT_LTE: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_LTE, x); + ret = count; + } + break; + case BATT_EVENT_LCD: + if (sscanf(buf, "%d\n", &x) == 1) { + /* we need to test + sec_bat_event_set(battery, EVENT_LCD, x); + */ + ret = count; + } + break; + case BATT_EVENT_GPS: + if (sscanf(buf, "%d\n", &x) == 1) { + sec_bat_event_set(battery, EVENT_GPS, x); + ret = count; + } + break; + case BATT_TEMP_TABLE: + if (sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d\n", + &t[0], &t[1], &t[2], &t[3], &t[4], &t[5], &t[6], &t[7], &t[8], &t[9], &t[10], &t[11]) == 12) { + pr_info("%s: (new) %d %d %d %d %d %d %d %d %d %d %d %d\n", + __func__, t[0], t[1], t[2], t[3], t[4], t[5], t[6], t[7], t[8], t[9], t[10], t[11]); + pr_info("%s: (default) %d %d %d %d %d %d %d %d %d %d %d %d\n", + __func__, + battery->pdata->temp_high_threshold_event, + battery->pdata->temp_high_recovery_event, + battery->pdata->temp_low_threshold_event, + battery->pdata->temp_low_recovery_event, + battery->pdata->temp_high_threshold_normal, + battery->pdata->temp_high_recovery_normal, + battery->pdata->temp_low_threshold_normal, + battery->pdata->temp_low_recovery_normal, + battery->pdata->temp_high_threshold_lpm, + battery->pdata->temp_high_recovery_lpm, + battery->pdata->temp_low_threshold_lpm, + battery->pdata->temp_low_recovery_lpm); + update_external_temp_table(battery, t); + ret = count; + } + break; + case BATT_HIGH_CURRENT_USB: + if (sscanf(buf, "%d\n", &x) == 1) { + union power_supply_propval value; + battery->is_hc_usb = x ? true : false; + value.intval = battery->is_hc_usb; + + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_USB_HC, value); + + pr_info("%s: is_hc_usb (%d)\n", __func__, battery->is_hc_usb); + ret = count; + } + break; +#if defined(CONFIG_SAMSUNG_BATTERY_ENG_TEST) + case BATT_TEST_CHARGE_CURRENT: + if (sscanf(buf, "%d\n", &x) == 1) { + if (x >= 0 && x <= 2000) { + union power_supply_propval value; + dev_err(battery->dev, + "%s: BATT_TEST_CHARGE_CURRENT(%d)\n", __func__, x); + get_charging_info(battery, POWER_SUPPLY_TYPE_USB)->input_current_limit = x; + get_charging_info(battery, POWER_SUPPLY_TYPE_USB)->fast_charging_current = x; + if (x > 500) { + battery->eng_not_full_status = true; + battery->pdata->temp_check_type = + SEC_BATTERY_TEMP_CHECK_NONE; + } + if (battery->cable_type == POWER_SUPPLY_TYPE_USB) { + value.intval = x; + +#if defined(CONFIG_TMM_CHG_CTRL) + if(tuner_running_status==TUNER_IS_ON) { + dev_dbg(battery->dev, + "%s: tmm tuner is on!\n", __func__); + + if(value.intval > TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE) { + value.intval = TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE; + } + } +#endif + + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_NOW, + value); + } + } + ret = count; + } + break; +#endif + case BATT_STABILITY_TEST: + if (sscanf(buf, "%d\n", &x) == 1) { + dev_err(battery->dev, + "%s: BATT_STABILITY_TEST(%d)\n", __func__, x); + if (x) { + battery->stability_test = true; + battery->eng_not_full_status = true; + } + else { + battery->stability_test = false; + battery->eng_not_full_status = false; + } + } + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int sec_bat_create_attrs(struct device *dev) +{ + int i, rc; + + for (i = 0; i < ARRAY_SIZE(sec_battery_attrs); i++) { + rc = device_create_file(dev, &sec_battery_attrs[i]); + if (rc) + goto create_attrs_failed; + } + goto create_attrs_succeed; + +create_attrs_failed: + while (i--) + device_remove_file(dev, &sec_battery_attrs[i]); +create_attrs_succeed: + return rc; +} + +static int sec_bat_property_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + case POWER_SUPPLY_PROP_HEALTH: + case POWER_SUPPLY_PROP_ONLINE: + case POWER_SUPPLY_PROP_CAPACITY: + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + case POWER_SUPPLY_PROP_CHARGE_TYPE: + case POWER_SUPPLY_PROP_PRESENT: + return 1; + default: + break; + } + return 0; +} + +static int sec_bat_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + int current_cable_type; + int full_check_type; + + dev_dbg(battery->dev, + "%s: (%d,%d)\n", __func__, psp, val->intval); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (battery->charging_mode == SEC_BATTERY_CHARGING_1ST) + full_check_type = battery->pdata->full_check_type; + else + full_check_type = battery->pdata->full_check_type_2nd; + if ((full_check_type == SEC_BATTERY_FULLCHARGED_CHGINT) && + (val->intval == POWER_SUPPLY_STATUS_FULL)) + sec_bat_do_fullcharged(battery); + battery->status = val->intval; + break; + case POWER_SUPPLY_PROP_HEALTH: + battery->health = val->intval; + break; + case POWER_SUPPLY_PROP_ONLINE: + current_cable_type = val->intval; + + if (current_cable_type < 0) { + dev_info(battery->dev, + "%s: ignore event(%d)\n", + __func__, current_cable_type); +#if 0 + } else if (current_cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + battery->wc_status = true; + } else if (current_cable_type == POWER_SUPPLY_TYPE_WIRELESS_REMOVE) { + battery->wc_status = false; + if (battery->wire_status != POWER_SUPPLY_TYPE_BATTERY) + current_cable_type = battery->wire_status; +#endif + } else { + battery->wire_status = current_cable_type; + if ((battery->wire_status == POWER_SUPPLY_TYPE_BATTERY) + && battery->wc_status) + current_cable_type = POWER_SUPPLY_TYPE_WIRELESS; + } + dev_info(battery->dev, + "%s: current_cable(%d), wc_status(%d), wire_status(%d)\n", + __func__, current_cable_type, battery->wc_status, + battery->wire_status); + + /* cable is attached or detached + * if current_cable_type is minus value, + * check cable by sec_bat_get_cable_type() + * although SEC_BATTERY_CABLE_SOURCE_EXTERNAL is set + * (0 is POWER_SUPPLY_TYPE_UNKNOWN) + */ + if ((current_cable_type >= 0) && + (current_cable_type < SEC_SIZEOF_POWER_SUPPLY_TYPE) && + (battery->pdata->cable_source_type & + SEC_BATTERY_CABLE_SOURCE_EXTERNAL)) { + + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work,0); + } else { + if (sec_bat_get_cable_type(battery, + battery->pdata->cable_source_type)) { + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work,0); + } + } + break; + case POWER_SUPPLY_PROP_CAPACITY: + battery->capacity = val->intval; + power_supply_changed(battery->psy_bat); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + /* If JIG is attached, the voltage is set as 1079 */ + pr_info("%s : set to the battery history : (%d)\n",__func__, val->intval); + if(val->intval == MV_TO_UV(1079)) + { + battery->voltage_now = MV_TO_UV(1079); + battery->voltage_avg = MV_TO_UV(1079); + power_supply_changed(battery->psy_bat); + } + break; + +#if defined(CONFIG_TMM_CHG_CTRL) + case POWER_SUPPLY_PROP_CURRENT_NOW: + if((val->intval)==TUNER_SWITCHED_ON_SIGNAL) { + dev_dbg(battery->dev, + "%s: tmm switched on!\n", __func__); + if((battery->cable_type != POWER_SUPPLY_TYPE_UNKNOWN) && + (battery->cable_type != POWER_SUPPLY_TYPE_BATTERY)) { + + union power_supply_propval value_Check_CurrentNow; + int input_curr_limit; + + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_CURRENT_NOW, value_Check_CurrentNow); + + input_curr_limit = value_Check_CurrentNow.intval; + + if(input_curr_limit > TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE) { + union power_supply_propval value; + value.intval = TMM_CHG_CTRL_INPUT_LIMIT_CURRENT_VALUE; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_CURRENT_NOW, value); + } + } + tuner_running_status=TUNER_IS_ON; + }else if((val->intval)==TUNER_SWITCHED_OFF_SIGNAL) { + union power_supply_propval value; + + dev_dbg(battery->dev, + "%s: tmm switched off!\n", __func__); + value.intval = battery->cable_type; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, value); + tuner_running_status=TUNER_IS_OFF; + } + break; +#endif + case POWER_SUPPLY_PROP_CHARGE_TYPE: + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + break; + case POWER_SUPPLY_PROP_PRESENT: + battery->present = val->intval; + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sec_bat_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + union power_supply_propval value; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if ((battery->health == POWER_SUPPLY_HEALTH_OVERVOLTAGE) || + (battery->health == POWER_SUPPLY_HEALTH_UNDERVOLTAGE)) { + val->intval = + POWER_SUPPLY_STATUS_DISCHARGING; + } else { + if ((battery->pdata->cable_check_type & + SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE) && + !sec_bat_is_lpm(battery)) { + switch (battery->cable_type) { + case POWER_SUPPLY_TYPE_USB: + case POWER_SUPPLY_TYPE_USB_DCP: + case POWER_SUPPLY_TYPE_USB_CDP: + case POWER_SUPPLY_TYPE_USB_ACA: + val->intval = + POWER_SUPPLY_STATUS_DISCHARGING; + return 0; + } + } + +#if defined(CONFIG_MACH_VIENNAEUR) || defined(CONFIG_MACH_VIENNAVZW) || defined(CONFIG_MACH_V2LTEEUR) || \ + defined(CONFIG_SEC_TRLTE_PROJECT) || defined(CONFIG_SEC_TBLTE_PROJECT) + if (battery->status == POWER_SUPPLY_STATUS_FULL && + battery->capacity != 100) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + pr_info("%s: forced full-charged sequence progressing\n", __func__); + } else +#endif + val->intval = battery->status; + } + break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + if (battery->cable_type == POWER_SUPPLY_TYPE_BATTERY || + battery->cable_type == POWER_SUPPLY_TYPE_MHL_USB_100) { + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + } else { + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_CHARGE_TYPE, value); + if (value.intval == POWER_SUPPLY_CHARGE_TYPE_UNKNOWN) + /* if error in CHARGE_TYPE of charger + * set CHARGE_TYPE as NONE + */ + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + else + val->intval = value.intval; + } + break; + case POWER_SUPPLY_PROP_HEALTH: + update_charger_health(battery); + val->intval = battery->health; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = battery->present; + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = battery->cable_type; + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = battery->pdata->technology; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: +#ifdef CONFIG_SEC_FACTORY + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_VOLTAGE_NOW, value); + battery->voltage_now = value.intval; + dev_err(battery->dev, + "%s: voltage now(%d)\n", __func__, battery->voltage_now); +#endif + /* voltage value should be in uV */ + val->intval = battery->voltage_now; + break; + case POWER_SUPPLY_PROP_VOLTAGE_AVG: +#ifdef CONFIG_SEC_FACTORY + value.intval = SEC_BATTEY_VOLTAGE_AVERAGE; + psy_do_property(battery->pdata->fuelgauge_name, get, + POWER_SUPPLY_PROP_VOLTAGE_AVG, value); + battery->voltage_avg = value.intval; + dev_err(battery->dev, + "%s: voltage avg(%d)\n", __func__, battery->voltage_avg); +#endif + /* voltage value should be in uV */ + val->intval = battery->voltage_avg; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = battery->current_now; + break; + case POWER_SUPPLY_PROP_CURRENT_AVG: + val->intval = battery->current_avg; + break; + /* charging mode (differ from power supply) */ + case POWER_SUPPLY_PROP_CHARGE_NOW: + val->intval = battery->charging_mode; + break; + case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN: + case POWER_SUPPLY_PROP_ENERGY_FULL: + case POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN: + case POWER_SUPPLY_PROP_ENERGY_EMPTY: + case POWER_SUPPLY_PROP_ENERGY_NOW: + case POWER_SUPPLY_PROP_ENERGY_AVG: + psy_do_property(battery->pdata->fuelgauge_name, get, + psp, value); + val->intval = value.intval; + break; + + case POWER_SUPPLY_PROP_CAPACITY: +#if defined(CONFIG_MACH_VIENNAEUR) || defined(CONFIG_MACH_VIENNAVZW) || defined(CONFIG_MACH_V2LTEEUR) || \ + defined(CONFIG_SEC_TRLTE_PROJECT) || defined(CONFIG_SEC_TBLTE_PROJECT) + val->intval = battery->capacity; +#else + if (battery->status == POWER_SUPPLY_STATUS_FULL) { + if(battery->eng_not_full_status == true) + val->intval = battery->capacity; + else + val->intval = 100; + } else { + val->intval = battery->capacity; + } +#endif + break; + case POWER_SUPPLY_PROP_TEMP: + val->intval = battery->temperature; + break; + case POWER_SUPPLY_PROP_TEMP_AMBIENT: + val->intval = battery->temper_amb; + break; + default: + return -EINVAL; + } + return 0; +} + +static int sec_usb_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + + if (psp != POWER_SUPPLY_PROP_ONLINE) + return -EINVAL; + + if ((battery->health == POWER_SUPPLY_HEALTH_OVERVOLTAGE) || + (battery->health == POWER_SUPPLY_HEALTH_UNDERVOLTAGE)) { + val->intval = 0; + return 0; + } + /* Set enable=1 only if the USB charger is connected */ + switch (battery->wire_status) { + case POWER_SUPPLY_TYPE_USB: + case POWER_SUPPLY_TYPE_USB_DCP: + case POWER_SUPPLY_TYPE_USB_CDP: + case POWER_SUPPLY_TYPE_USB_ACA: + case POWER_SUPPLY_TYPE_MHL_USB: + case POWER_SUPPLY_TYPE_MHL_USB_100: + val->intval = 1; + break; + default: + val->intval = 0; + break; + } + + return 0; +} + +static int sec_ac_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + + if (psp != POWER_SUPPLY_PROP_ONLINE) + return -EINVAL; + + if ((battery->health == POWER_SUPPLY_HEALTH_OVERVOLTAGE) || + (battery->health == POWER_SUPPLY_HEALTH_UNDERVOLTAGE) || + (battery->charger_health == POWER_SUPPLY_HEALTH_OVERVOLTAGE) || + (battery->charger_health == POWER_SUPPLY_HEALTH_UNDERVOLTAGE)) { + val->intval = 0; + return 0; + } + /* Set enable=1 only if the AC charger is connected */ + switch (battery->cable_type) { + case POWER_SUPPLY_TYPE_MAINS: + case POWER_SUPPLY_TYPE_MISC: + case POWER_SUPPLY_TYPE_CARDOCK: + case POWER_SUPPLY_TYPE_UARTOFF: + case POWER_SUPPLY_TYPE_LAN_HUB: + case POWER_SUPPLY_TYPE_UNKNOWN: + case POWER_SUPPLY_TYPE_MHL_500: + case POWER_SUPPLY_TYPE_MHL_900: + case POWER_SUPPLY_TYPE_MHL_1500: + case POWER_SUPPLY_TYPE_MHL_2000: + case POWER_SUPPLY_TYPE_SMART_OTG: + case POWER_SUPPLY_TYPE_SMART_NOTG: + case POWER_SUPPLY_TYPE_HV_PREPARE_MAINS: + case POWER_SUPPLY_TYPE_HV_ERR: + case POWER_SUPPLY_TYPE_HV_UNKNOWN: + case POWER_SUPPLY_TYPE_HV_MAINS: +#if defined(CONFIG_MUIC_SUPPORT_MULTIMEDIA_DOCK) + case POWER_SUPPLY_TYPE_MDOCK_TA: +#endif + val->intval = 1; + break; + default: + val->intval = 0; + break; + } + + return 0; +} + +static int sec_wireless_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + + if (psp != POWER_SUPPLY_PROP_ONLINE) + return -EINVAL; + + if (battery->wc_status) + val->intval = 1; + else + val->intval = 0; + + return 0; +} + +static int sec_wireless_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + + if (psp != POWER_SUPPLY_PROP_ONLINE) + return -EINVAL; + + battery->wc_status = val->intval; + + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + + return 0; +} + +static int sec_ps_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + union power_supply_propval value; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (val->intval == 0) { + if (battery->ps_enable == true) { + battery->ps_enable = val->intval; + dev_info(battery->dev, + "%s: power sharing cable set (%d)\n", __func__, battery->ps_enable); + value.intval = POWER_SUPPLY_TYPE_POWER_SHARING; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, value); + } + } else if ((val->intval == 1) && (battery->ps_status == true)) { + battery->ps_enable = val->intval; + dev_info(battery->dev, + "%s: power sharing cable set (%d)\n", __func__, battery->ps_enable); + value.intval = POWER_SUPPLY_TYPE_POWER_SHARING; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, value); + } else { + dev_err(battery->dev, + "%s: invalid setting (%d) ps_status (%d)\n", + __func__, val->intval, battery->ps_status); + } + break; + case POWER_SUPPLY_PROP_ONLINE: + if (val->intval == POWER_SUPPLY_TYPE_POWER_SHARING) { + battery->ps_status = true; + battery->ps_enable = true; + battery->ps_changed = true; + dev_info(battery->dev, + "%s: power sharing cable plugin (%d)\n", __func__, battery->ps_status); + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + } else { + battery->ps_status = false; + battery->ps_enable = false; + battery->ps_changed = false; + dev_info(battery->dev, + "%s: power sharing cable plugout (%d)\n", __func__, battery->ps_status); + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sec_ps_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct sec_battery_info *battery = psy->drv_data; + union power_supply_propval value; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (battery->ps_enable) + val->intval = 1; + else + val->intval = 0; + break; + case POWER_SUPPLY_PROP_ONLINE: + if (battery->ps_status) { + if ((battery->ps_enable == true) && (battery->ps_changed == true)) { + battery->ps_changed = false; + + value.intval = POWER_SUPPLY_TYPE_POWER_SHARING; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, value); + } + val->intval = 1; + } else { + if (battery->ps_enable == true) { + battery->ps_enable = false; + dev_info(battery->dev, + "%s: power sharing cable disconnected! ps disable (%d)\n", + __func__, battery->ps_enable); + + value.intval = POWER_SUPPLY_TYPE_POWER_SHARING; + psy_do_property(battery->pdata->charger_name, set, + POWER_SUPPLY_PROP_ONLINE, value); + } + val->intval = 0; + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static irqreturn_t sec_bat_irq_thread(int irq, void *irq_data) +{ + struct sec_battery_info *battery = irq_data; + + if ((battery->pdata->battery_check_type == SEC_BATTERY_CHECK_INT) + || (battery->pdata->battery_check_type == SEC_BATTERY_CHECK_FUELGAUGE) + || (battery->pdata->battery_check_type == SEC_BATTERY_CHECK_ADC)) { + if (battery->pdata->check_battery_callback) + battery->present = battery->pdata->check_battery_callback(); + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + } + + return IRQ_HANDLED; +} + +static irqreturn_t sec_ta_irq_thread(int irq, void *irq_data) +{ + struct sec_battery_info *battery = irq_data; + + if (battery->pdata->cable_source_type & SEC_BATTERY_CABLE_SOURCE_CALLBACK) { + wake_lock(&battery->vbus_detect_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->vbus_detect_work, msecs_to_jiffies(750)); + } + + return IRQ_HANDLED; +} + +#ifdef CONFIG_EXTCON +//#define USE_EXTCON +#endif + +#ifdef USE_EXTCON +static int sec_bat_cable_check(struct sec_battery_info *battery, + enum extcon_cable_name attached_dev) +{ + int current_cable_type = -1; + + switch (attached_dev) + { + case EXTCON_JIG_UARTOFF: + case EXTCON_JIG_UARTON: + case EXTCON_DESKDOCK: + case EXTCON_SMARTDOCK: + current_cable_type = POWER_SUPPLY_TYPE_BATTERY; + break; + case EXTCON_USB_HOST: + current_cable_type = POWER_SUPPLY_TYPE_OTG; + break; + case EXTCON_USB: + case EXTCON_JIG_USBOFF: + case EXTCON_JIG_USBON: + case EXTCON_SMARTDOCK_USB: + current_cable_type = POWER_SUPPLY_TYPE_USB; + break; + case EXTCON_JIG_UARTOFF_VB: + current_cable_type = POWER_SUPPLY_TYPE_UARTOFF; + break; + case EXTCON_TA: + case EXTCON_DESKDOCK_VB: + case EXTCON_SMARTDOCK_TA: + current_cable_type = POWER_SUPPLY_TYPE_MAINS; + break; + case EXTCON_CHARGE_DOWNSTREAM: + current_cable_type = POWER_SUPPLY_TYPE_USB_CDP; + break; + case EXTCON_INCOMPATIBLE: + current_cable_type = POWER_SUPPLY_TYPE_UNKNOWN; + break; + case EXTCON_AUDIODOCK: + current_cable_type = POWER_SUPPLY_TYPE_MISC; + break; + case EXTCON_CHARGING_CABLE: + current_cable_type = POWER_SUPPLY_TYPE_POWER_SHARING; + break; + case EXTCON_HV_PREPARE: + current_cable_type = POWER_SUPPLY_TYPE_HV_PREPARE_MAINS; + break; + case EXTCON_HV_TA_ERR: + current_cable_type = POWER_SUPPLY_TYPE_HV_ERR; + break; + case EXTCON_HV_TA_1A: + current_cable_type = POWER_SUPPLY_TYPE_HV_UNKNOWN; + break; + case EXTCON_HV_TA: + current_cable_type = POWER_SUPPLY_TYPE_HV_MAINS; + break; + default: + pr_err("%s: invalid type for charger:%d\n", + __func__, attached_dev); + } + + return current_cable_type; +} + +static int batt_handle_notification(struct notifier_block *nb, + unsigned long action, void *data) +{ + const char *cmd; + int cable_type; + struct sec_battery_extcon_cable *obj = + container_of(nb, struct sec_battery_extcon_cable, batt_nb); + enum extcon_cable_name attached_dev = obj->cable_index; + struct sec_battery_info *battery = + container_of(nb, struct sec_battery_info, + extcon_cable_list[attached_dev].batt_nb); + + if (action) { + cmd = "ATTACH"; + cable_type = sec_bat_cable_check(battery, attached_dev); + } else { + cmd = "DETACH"; + cable_type = POWER_SUPPLY_TYPE_BATTERY; + } + + if (cable_type < 0) { + dev_info(battery->dev, "%s: ignore event(%d)\n", + __func__, cable_type); + } else if (cable_type == POWER_SUPPLY_TYPE_POWER_SHARING) { + battery->ps_status = true; + battery->ps_enable = true; + battery->ps_changed = true; + + dev_info(battery->dev, + "%s: power sharing cable plugin (%d)\n", __func__, battery->ps_status); + } else if (cable_type == POWER_SUPPLY_TYPE_WIRELESS) { + battery->wc_status = true; +#if 0 + } else if (cable_type == POWER_SUPPLY_TYPE_WIRELESS_REMOVE) { + battery->wc_status = false; + if (battery->wire_status != POWER_SUPPLY_TYPE_BATTERY) + cable_type = battery->wire_status; +#endif + } else { + battery->wire_status = cable_type; + if ((battery->wire_status == POWER_SUPPLY_TYPE_BATTERY) + && battery->wc_status && !battery->ps_status) + cable_type = POWER_SUPPLY_TYPE_WIRELESS; + } + dev_info(battery->dev, + "%s: current_cable(%d), wc_status(%d), wire_status(%d)\n", + __func__, cable_type, battery->wc_status, + battery->wire_status); + + if ((cable_type >= 0) && + cable_type < SEC_SIZEOF_POWER_SUPPLY_TYPE) { + if (cable_type == POWER_SUPPLY_TYPE_POWER_SHARING) { + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + } else if((cable_type == POWER_SUPPLY_TYPE_BATTERY) + && battery->ps_status) { + battery->ps_status = false; + dev_info(battery->dev, + "%s: power sharing cable plugout (%d)\n", __func__, battery->ps_status); + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + } else if(cable_type != battery->cable_type) { + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + } else { + dev_info(battery->dev, + "%s: Cable is Not Changed(%d)\n", + __func__, battery->cable_type); + } + } + + pr_info("%s: CMD=%s, attached_dev=%d\n", __func__, cmd, attached_dev); + + return 0; +} +#endif /* USE_EXTCON */ + +#ifdef CONFIG_OF +static int sec_bat_read_u32_index_dt(const struct device_node *np, + const char *propname, + u32 index, u32 *out_value) +{ + struct property *prop = of_find_property(np, propname, NULL); + u32 len = (index + 1) * sizeof(*out_value); + + if (!prop) + return (-EINVAL); + if (!prop->value) + return (-ENODATA); + if (len > prop->length) + return (-EOVERFLOW); + + *out_value = be32_to_cpup(((__be32 *)prop->value) + index); + + return 0; +} + +static int check_for_deferral(struct device_node *np) +{ + struct power_supply *psy; + char *charger_name; + char *fuelgauge_name; + int ret; + + ret = of_property_read_string(np, + "battery,charger_name", (char const **)&charger_name); + if (ret) + return 0; + psy = get_power_supply_by_name(charger_name); + if (!psy) + return -EPROBE_DEFER; + + ret = of_property_read_string(np, + "battery,fuelgauge_name", (char const **)&fuelgauge_name); + if (ret) + return 0; + psy = get_power_supply_by_name(fuelgauge_name); + if (!psy) + return -EPROBE_DEFER; + return 0; +} + +static int sec_bat_parse_dt(struct device *dev, + struct sec_battery_info *battery) +{ + struct device_node *np = dev->of_node; + sec_battery_platform_data_t *pdata = battery->pdata; + int ret, len; + unsigned int i; + const u32 *p; + + if (!np) { + pr_info("%s: np NULL\n", __func__); + return 1; + } + + ret = of_property_read_string(np, + "battery,vendor", (char const **)&pdata->vendor); + if (ret) + pr_info("%s: Vendor is Empty\n", __func__); + +#if defined(CONFIG_PM8926_BATTERY_CHECK_INTERRUPT) + ret = of_property_read_string(np, + "battery,pmic_name", (char const **)&pdata->pmic_name); + if (ret) + pr_info("%s: Vendor is Empty\n", __func__); +#endif + + ret = of_property_read_string(np, + "battery,charger_name", (char const **)&pdata->charger_name); + if (ret) + pr_info("%s: Vendor is Empty\n", __func__); + + ret = of_property_read_string(np, + "battery,fuelgauge_name", (char const **)&pdata->fuelgauge_name); + if (ret) + pr_info("%s: Vendor is Empty\n", __func__); + + ret = of_property_read_string(np, + "battery,chip_vendor", (char const **)&pdata->chip_vendor); + if (ret) + pr_info("%s: Vendor is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,technology", + &pdata->technology); + if (ret) + pr_info("%s: technology is Empty\n", __func__); + + ret = of_get_named_gpio(np, "battery,bat_int", 0); + if (ret > 0) { + pdata->bat_irq_gpio = ret; + pdata->bat_irq = gpio_to_irq(ret); + pr_info("%s reading bat_int_gpio = %d\n", __func__, ret); + } else { + pr_info("%s reading bat_int_gpio is empty\n", __func__); + } + + ret = of_property_read_u32(np, "battery,bat_irq_attr", + (unsigned int *)&pdata->bat_irq_attr); + if (ret) + pr_info("%s: bat_irq_attr is Empty\n", __func__); + + ret = of_get_named_gpio(np, "battery,ta_int", 0); + if (ret > 0) { + pdata->ta_irq_gpio = ret; + pdata->ta_irq = gpio_to_irq(ret); + pr_info("%s reading ta_int_gpio = %d\n", __func__, ret); + } + + ret = of_property_read_u32(np, "battery,ta_irq_attr", + (unsigned int *)&pdata->ta_irq_attr); + if (ret) + pr_info("%s: ta_irq_attr is Empty\n", __func__); + + p = of_get_property(np, "battery,polling_time", &len); + + len = len / sizeof(u32); + + pdata->polling_time = kzalloc(sizeof(*pdata->polling_time) * len, GFP_KERNEL); + + ret = of_property_read_u32_array(np, "battery,polling_time", + pdata->polling_time, len); + if (ret) + pr_info("%s: polling_time is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,adc_check_count", + &pdata->adc_check_count); + if (ret) + pr_info("%s: adc_check_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,temp_adc_type", + &pdata->temp_adc_type); + if (ret) + pr_info("%s: temp_adc_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,cable_check_type", + &pdata->cable_check_type); +#if defined(CONFIG_CHARGING_VZWCONCEPT) +#if !defined(CONFIG_MACH_VIENNAVZW) && !defined(CONFIG_MACH_LT03_VZW) + pdata->cable_check_type &= ~SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE; +#endif + pdata->cable_check_type |= SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE; +#endif + if (ret) + pr_info("%s: cable_check_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,cable_source_type", + &pdata->cable_source_type); + if (ret) + pr_info("%s: cable_source_type is Empty\n", __func__); + + pdata->event_check = of_property_read_bool(np, + "battery,event_check"); + pdata->chg_temp_check = of_property_read_bool(np, + "battery,chg_temp_check"); + pr_info("%s: chg_temp_check: %d \n", __func__, pdata->chg_temp_check); + if (pdata->chg_temp_check) { + ret = of_property_read_u32(np, "battery,chg_high_temp", + &pdata->chg_high_temp); + if (ret) + pr_info("%s: chg_high_temp is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,chg_high_temp_recovery", + &pdata->chg_high_temp_recovery); + if (ret) + pr_info("%s: chg_high_temp_recovery is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,chg_charging_limit_current", + &pdata->chg_charging_limit_current); + if (ret) + pr_info("%s: chg_charging_limit_current is Empty\n", __func__); + } + + ret = of_property_read_u32(np, "battery,event_waiting_time", + &pdata->event_waiting_time); + if (ret) + pr_info("%s: event_waiting_time is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,polling_type", + &pdata->polling_type); + if (ret) + pr_info("%s: polling_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,monitor_initial_count", + &pdata->monitor_initial_count); + if (ret) + pr_info("%s: monitor_initial_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,battery_check_type", + &pdata->battery_check_type); + if (ret) + pr_info("%s: battery_check_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,check_count", + &pdata->check_count); + if (ret) + pr_info("%s: check_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,check_adc_max", + &pdata->check_adc_max); + if (ret) + pr_info("%s: check_adc_max is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,check_adc_min", + &pdata->check_adc_min); + if (ret) + pr_info("%s: check_adc_min is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,ovp_uvlo_check_type", + &pdata->ovp_uvlo_check_type); + if (ret) + pr_info("%s: ovp_uvlo_check_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,thermal_source", + &pdata->thermal_source); + if (ret) + pr_info("%s: thermal_source is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,temp_check_type", + &pdata->temp_check_type); + if (ret) + pr_info("%s: temp_check_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,temp_check_count", + &pdata->temp_check_count); + if (ret) + pr_info("%s: temp_check_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_check_type", + &pdata->full_check_type); + if (ret) + pr_info("%s: full_check_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_check_type_2nd", + &pdata->full_check_type_2nd); + if (ret) + pr_info("%s: full_check_type_2nd is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_check_count", + &pdata->full_check_count); + if (ret) + pr_info("%s: full_check_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,chg_gpio_full_check", + &pdata->chg_gpio_full_check); + if (ret) + pr_info("%s: chg_gpio_full_check is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,chg_polarity_full_check", + &pdata->chg_polarity_full_check); + if (ret) + pr_info("%s: chg_polarity_full_check is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_condition_type", + &pdata->full_condition_type); + if (ret) + pr_info("%s: full_condition_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_condition_soc", + &pdata->full_condition_soc); + if (ret) + pr_info("%s: full_condition_soc is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,full_condition_vcell", + &pdata->full_condition_vcell); + if (ret) + pr_info("%s: full_condition_vcell is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,recharge_check_count", + &pdata->recharge_check_count); + if (ret) + pr_info("%s: recharge_check_count is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,recharge_condition_type", + &pdata->recharge_condition_type); + if (ret) + pr_info("%s: recharge_condition_type is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,recharge_condition_soc", + &pdata->recharge_condition_soc); + if (ret) + pr_info("%s: recharge_condition_soc is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,recharge_condition_vcell", + &pdata->recharge_condition_vcell); + if (ret) + pr_info("%s: recharge_condition_vcell is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,charging_total_time", + (unsigned int *)&pdata->charging_total_time); + if (ret) + pr_info("%s: charging_total_time is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,recharging_total_time", + (unsigned int *)&pdata->recharging_total_time); + if (ret) + pr_info("%s: recharging_total_time is Empty\n", __func__); + + ret = of_property_read_u32(np, "battery,charging_reset_time", + (unsigned int *)&pdata->charging_reset_time); + if (ret) + pr_info("%s: charging_reset_time is Empty\n", __func__); + + np = of_find_node_by_name(dev->parent->of_node, "charger"); + + if (!np) { + pr_info("%s : np NULL\n", __func__); + return 1; + } + + if (!pdata->charging_current) { + p = of_get_property(np, "battery,input_current_limit", &len); + + len = len / sizeof(u32); + + pdata->charging_current = kzalloc(sizeof(sec_charging_current_t) * len, + GFP_KERNEL); + + pdata->charging_current_entries = len; + for(i = 0; i < len; i++) { + struct sec_charging_current *scc = &pdata->charging_current[i]; + + ret = sec_bat_read_u32_index_dt(np, + "battery,input_current_limit", i, + &scc->input_current_limit); + ret = sec_bat_read_u32_index_dt(np, + "battery,fast_charging_current", i, + &scc->fast_charging_current); + ret = sec_bat_read_u32_index_dt(np, + "battery,full_check_current_1st", i, + &scc->full_check_current_1st); + ret = sec_bat_read_u32_index_dt(np, + "battery,full_check_current_2nd", i, + &scc->full_check_current_2nd); + } + } + pr_info("%s: vendor : %s, technology : %d, cable_check_type : %d\n" + "cable_source_type : %d, event_waiting_time : %d\n" + "polling_type : %d, initial_count : %d, check_count : %d\n" + "check_adc_max : %d, check_adc_min : %d\n" + "ovp_uvlo_check_type : %d, thermal_source : %d\n" + "temp_check_type : %d, temp_check_count : %d\n", + __func__, + pdata->vendor, pdata->technology,pdata->cable_check_type, + pdata->cable_source_type, pdata->event_waiting_time, + pdata->polling_type, pdata->monitor_initial_count, + pdata->check_count, pdata->check_adc_max, pdata->check_adc_min, + pdata->ovp_uvlo_check_type, pdata->thermal_source, + pdata->temp_check_type, pdata->temp_check_count); + + return ret; +} +#endif + +const struct power_supply_desc psy_bat_desc = { + .name = "battery", + .type = POWER_SUPPLY_TYPE_BATTERY, + .properties = sec_battery_props, + .num_properties = ARRAY_SIZE(sec_battery_props), + .get_property = sec_bat_get_property, + .set_property = sec_bat_set_property, + .property_is_writeable = sec_bat_property_is_writeable, +}; + +struct power_supply_config psy_bat_config = { +#if defined(CONFIG_QPNP_BMS) + .supplied_to = pm_batt_supplied_to, + .num_supplicants = ARRAY_SIZE(pm_batt_supplied_to), +#endif +}; + +const struct power_supply_desc psy_usb_desc = { + .name = "usb", + .type = POWER_SUPPLY_TYPE_USB, + .properties = sec_power_props, + .num_properties = ARRAY_SIZE(sec_power_props), + .get_property = sec_usb_get_property, +}; + +struct power_supply_config psy_usb_config = { + .supplied_to = supply_list, + .num_supplicants = ARRAY_SIZE(supply_list), +}; + +const struct power_supply_desc psy_ac_desc = { + .name = "ac", + .type = POWER_SUPPLY_TYPE_MAINS, + .properties = sec_power_props, + .num_properties = ARRAY_SIZE(sec_power_props), + .get_property = sec_ac_get_property, +}; + +struct power_supply_config psy_ac_config = { + .supplied_to = supply_list, + .num_supplicants = ARRAY_SIZE(supply_list), +}; + +const struct power_supply_desc psy_wireless_desc = { + .name = "wireless", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = sec_power_props, + .num_properties = ARRAY_SIZE(sec_power_props), + .get_property = sec_wireless_get_property, + .set_property = sec_wireless_set_property, +}; + +struct power_supply_config psy_wireless_config = { + .supplied_to = supply_list, + .num_supplicants = ARRAY_SIZE(supply_list), +}; + +const struct power_supply_desc psy_ps_desc = { + .name = "ps", + .type = POWER_SUPPLY_TYPE_POWER_SHARING, + .properties = sec_ps_props, + .num_properties = ARRAY_SIZE(sec_ps_props), + .get_property = sec_ps_get_property, + .set_property = sec_ps_set_property, +}; + +struct power_supply_config psy_ps_config = { + .supplied_to = supply_list, + .num_supplicants = ARRAY_SIZE(supply_list), +}; + +static int sec_battery_probe(struct platform_device *pdev) +{ + sec_battery_platform_data_t *pdata = NULL; + struct sec_battery_info *battery; + int ret = 0; +#if !defined(CONFIG_OF) || defined(USE_EXTCON) + int i; +#endif + +#if defined(CONFIG_TMM_CHG_CTRL) + tuner_running_status=TUNER_IS_OFF; +#endif + + ret = check_for_deferral(pdev->dev.of_node); + if (ret) + return ret; + + dev_dbg(&pdev->dev, + "%s: SEC Battery Driver Loading\n", __func__); + + battery = kzalloc(sizeof(*battery), GFP_KERNEL); + if (!battery) + return -ENOMEM; + + if (pdev->dev.of_node) { + pdata = devm_kzalloc(&pdev->dev, + sizeof(sec_battery_platform_data_t), + GFP_KERNEL); + if (!pdata) { + dev_err(&pdev->dev, "Failed to allocate memory\n"); + ret = -ENOMEM; + goto err_bat_free; + } + + battery->pdata = pdata; + ret = sec_bat_parse_dt(&pdev->dev, battery); + if (ret < 0) { + dev_err(&pdev->dev, "%s:dt error %d\n", __func__, ret); + goto err_bat_free; + } + } else { + pdata = dev_get_platdata(&pdev->dev); + battery->pdata = pdata; + } + + platform_set_drvdata(pdev, battery); + + battery->dev = &pdev->dev; + + mutex_init(&battery->adclock); + dev_dbg(battery->dev, "%s: ADC init\n", __func__); + +#if defined(CONFIG_SEC_TRLTE_PROJECT) || defined(CONFIG_SEC_TBLTE_PROJECT) + battery->pdata->temp_highlimit_threshold_event = TEMP_HIGHLIMIT_THRESHOLD; + battery->pdata->temp_highlimit_recovery_event = TEMP_HIGHLIMIT_RECOVERY; + battery->pdata->temp_highlimit_threshold_normal = TEMP_HIGHLIMIT_THRESHOLD; + battery->pdata->temp_highlimit_recovery_normal =TEMP_HIGHLIMIT_RECOVERY; + battery->pdata->temp_highlimit_threshold_lpm = TEMP_HIGHLIMIT_THRESHOLD; + battery->pdata->temp_highlimit_recovery_lpm = TEMP_HIGHLIMIT_RECOVERY; +#else + battery->pdata->temp_highlimit_threshold_event = TEMP_HIGHLIMIT_DEFAULT; + battery->pdata->temp_highlimit_recovery_event = TEMP_HIGHLIMIT_DEFAULT; + battery->pdata->temp_highlimit_threshold_normal = TEMP_HIGHLIMIT_DEFAULT; + battery->pdata->temp_highlimit_recovery_normal =TEMP_HIGHLIMIT_DEFAULT; + battery->pdata->temp_highlimit_threshold_lpm = TEMP_HIGHLIMIT_DEFAULT; + battery->pdata->temp_highlimit_recovery_lpm = TEMP_HIGHLIMIT_DEFAULT; +#endif + +#ifdef CONFIG_OF + board_battery_init(pdev, battery); +#else + for (i = 0; i < SEC_BAT_ADC_CHANNEL_NUM; i++) + adc_init(pdev, pdata, i); +#endif + wake_lock_init(&battery->monitor_wake_lock, WAKE_LOCK_SUSPEND, + "sec-battery-monitor"); + wake_lock_init(&battery->cable_wake_lock, WAKE_LOCK_SUSPEND, + "sec-battery-cable"); + wake_lock_init(&battery->vbus_wake_lock, WAKE_LOCK_SUSPEND, + "sec-battery-vbus"); + wake_lock_init(&battery->vbus_detect_wake_lock, WAKE_LOCK_SUSPEND, + "sec-battery-vbus-detect"); + + /* initialization of battery info */ + battery->status = POWER_SUPPLY_STATUS_DISCHARGING; + battery->health = POWER_SUPPLY_HEALTH_GOOD; + battery->charger_health = POWER_SUPPLY_HEALTH_GOOD; + battery->store_mode_enable = true; + battery->prev_online = battery->prev_status = -1; + battery->present = true; + + battery->polling_count = 1; /* initial value = 1 */ + battery->polling_time = pdata->polling_time[ + SEC_BATTERY_POLLING_TIME_DISCHARGING]; + battery->polling_in_sleep = false; + battery->polling_short = false; + battery->fuelgauge_in_sleep = false; + + battery->check_count = 0; + battery->check_adc_count = 0; + battery->check_adc_value = 0; + + battery->charging_start_time = 0; + battery->charging_passed_time = 0; + battery->charging_next_time = 0; + battery->charging_fullcharged_time = 0; + battery->siop_level = 100; + battery->wc_enable = 1; + battery->stability_test = 0; + battery->eng_not_full_status = 0; + battery->chg_limit = false; + + if (battery->pdata->check_batt_id) + battery->pdata->check_batt_id(); + + battery->wc_status = 0; + battery->ps_status= 0; + battery->ps_changed= 0; + battery->wire_status = POWER_SUPPLY_TYPE_BATTERY; + +#if defined(CONFIG_BATTERY_SWELLING) + battery->swelling_mode = false; + battery->swelling_block = false; +#endif +#if defined(ANDROID_ALARM_ACTIVATED) + alarm_init(&battery->event_termination_alarm, + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP, + sec_bat_event_expired_timer_func); +#else + alarm_init(&battery->event_termination_alarm, + ALARM_BOOTTIME, + sec_bat_event_expired_timer_func); +#endif + battery->temp_highlimit_threshold = + pdata->temp_highlimit_threshold_normal; + battery->temp_highlimit_recovery = + pdata->temp_highlimit_recovery_normal; + battery->temp_high_threshold = + pdata->temp_high_threshold_normal; + battery->temp_high_recovery = + pdata->temp_high_recovery_normal; + battery->temp_low_recovery = + pdata->temp_low_recovery_normal; + battery->temp_low_threshold = + pdata->temp_low_threshold_normal; + + + battery->charging_mode = SEC_BATTERY_CHARGING_NONE; + battery->is_recharging = false; + battery->cable_type = POWER_SUPPLY_TYPE_BATTERY; + battery->test_mode = 0; + battery->factory_mode = false; + battery->store_mode = false; + battery->slate_mode = false; + battery->is_hc_usb = false; + + /* create work queue */ + battery->monitor_wqueue = + create_singlethread_workqueue(dev_name(&pdev->dev)); + if (!battery->monitor_wqueue) { + dev_err(battery->dev, + "%s: Fail to Create Workqueue\n", __func__); + goto err_wake_lock; + } + + INIT_DELAYED_WORK(&battery->monitor_work, sec_bat_monitor_work); + INIT_DELAYED_WORK(&battery->cable_work, sec_bat_cable_work); + INIT_DELAYED_WORK(&battery->vbus_detect_work, sec_bat_vbus_detect_work); + + switch (pdata->polling_type) { + case SEC_BATTERY_MONITOR_WORKQUEUE: + INIT_DELAYED_WORK(&battery->polling_work, + sec_bat_polling_work); + break; + case SEC_BATTERY_MONITOR_ALARM: +#if defined(ANDROID_ALARM_ACTIVATED) + battery->last_poll_time = alarm_get_elapsed_realtime(); + alarm_init(&battery->polling_alarm, + ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP, + sec_bat_alarm); +#else + battery->last_poll_time = ktime_get_boottime(); + alarm_init(&battery->polling_alarm, ALARM_BOOTTIME, + sec_bat_alarm); +#endif + break; + default: + break; + } + + sec_bat_get_battery_info(battery); + + /* init power supplier framework */ + psy_ps_config.drv_data = battery; + battery->psy_ps = power_supply_register(&pdev->dev, &psy_ps_desc, &psy_ps_config); + if (IS_ERR(battery->psy_ps)) { + dev_err(battery->dev, + "%s: Failed to Register psy_ps\n", __func__); + ret = PTR_ERR(battery->psy_ps); + goto err_workqueue; + } + + psy_wireless_config.drv_data = battery; + battery->psy_wireless = power_supply_register(&pdev->dev, &psy_wireless_desc, &psy_wireless_config); + if (IS_ERR(battery->psy_wireless)) { + dev_err(battery->dev, + "%s: Failed to Register psy_wireless\n", __func__); + ret = PTR_ERR(battery->psy_wireless); + goto err_supply_unreg_ps; + } + + psy_usb_config.drv_data = battery; + battery->psy_usb = power_supply_register(&pdev->dev, &psy_usb_desc, &psy_usb_config); + if (IS_ERR(battery->psy_usb)) { + dev_err(battery->dev, + "%s: Failed to Register psy_usb\n", __func__); + ret = PTR_ERR(battery->psy_usb); + goto err_supply_unreg_wireless; + } + + psy_ac_config.drv_data = battery; + battery->psy_ac = power_supply_register(&pdev->dev, &psy_ac_desc, &psy_ac_config); + if (IS_ERR(battery->psy_ac)) { + dev_err(battery->dev, + "%s: Failed to Register psy_ac\n", __func__); + ret = PTR_ERR(battery->psy_ac); + goto err_supply_unreg_usb; + } + + psy_bat_config.drv_data = battery; + battery->psy_bat = power_supply_register(&pdev->dev, &psy_bat_desc, &psy_bat_config); + if (IS_ERR(battery->psy_bat)) { + dev_err(battery->dev, + "%s: Failed to Register psy_bat\n", __func__); + ret = PTR_ERR(battery->psy_bat); + goto err_supply_unreg_ac; + } + + if (battery->pdata->bat_gpio_init && !battery->pdata->bat_gpio_init()) { + dev_err(battery->dev, + "%s: Failed to Initialize GPIO\n", __func__); + goto err_supply_unreg_bat; + } + + if (battery->pdata->bat_irq) { + ret = request_threaded_irq(battery->pdata->bat_irq, + NULL, sec_bat_irq_thread, + battery->pdata->bat_irq_attr + | IRQF_ONESHOT, + "battery-irq", battery); + if (ret) { + dev_err(battery->dev, + "%s: Failed to Request IRQ (bat_int)\n", __func__); + goto err_supply_unreg_bat; + } + if (battery->pdata->bat_irq_gpio) { + ret = enable_irq_wake(battery->pdata->bat_irq); + if (ret < 0) + dev_err(battery->dev, + "%s: Failed to Enable Wakeup Source(%d)(bat_int)\n", + __func__, ret); + } + } + + if (battery->pdata->ta_irq) { + ret = request_threaded_irq(battery->pdata->ta_irq, + NULL, sec_ta_irq_thread, + battery->pdata->ta_irq_attr + | IRQF_ONESHOT, + "ta-irq", battery); + if (ret) { + dev_err(battery->dev, + "%s: Failed to Request IRQ (ta_int)\n", __func__); + goto err_req_irq; + } + if (battery->pdata->ta_irq_gpio) { + ret = enable_irq_wake(battery->pdata->ta_irq); + if (ret < 0) + dev_err(battery->dev, + "%s: Failed to Enable Wakeup Source(%d)(ta_int)\n", + __func__, ret); + } + } + + ret = sec_bat_create_attrs(battery->dev); + if (ret) { + dev_err(battery->dev, + "%s : Failed to create_attrs\n", __func__); + goto err_req_ta_irq; + } + +#if defined(USE_EXTCON) + for (i=0; i < EXTCON_NONE; i++) { + battery->extcon_cable_list[i].batt_nb.notifier_call = batt_handle_notification; + battery->extcon_cable_list[i].cable_index = i; + ret = extcon_register_interest(&battery->extcon_cable_list[i].extcon_nb, + EXTCON_DEV_NAME, + extcon_cable_name[i], + &battery->extcon_cable_list[i].batt_nb); + + if (ret) { + pr_err("%s: fail to register extcon notifier(%s, %d)\n", + __func__, extcon_cable_name[i], ret); + continue; + } + if (extcon_get_cable_state_(battery->extcon_cable_list[i].extcon_nb.edev, i)) { + battery->wire_status = sec_bat_cable_check(battery, i); + pr_info("%s: %s(wire_status = %d) attached from extcon\n", __func__, + extcon_cable_name[i], battery->wire_status); + } + } + + if ((battery->wire_status > POWER_SUPPLY_TYPE_BATTERY) && + (battery->wire_status < SEC_SIZEOF_POWER_SUPPLY_TYPE) && + (battery->pdata->cable_source_type & + SEC_BATTERY_CABLE_SOURCE_EXTERNAL)) { + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + } else { + union power_supply_propval value; + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_ONLINE, value); + if (value.intval == POWER_SUPPLY_TYPE_WIRELESS) { + battery->wc_status = 1; + wake_lock(&battery->cable_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->cable_work, 0); + } + } +#else + cable_initial_check(battery); +#endif + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, &battery->monitor_work, 0); + + sec_bat_check_cable_result_callback(battery->dev, POWER_SUPPLY_TYPE_MAINS); + battery->present = sec_bat_check(battery); + sec_bat_check_cable_result_callback(battery->dev, battery->cable_type); + + dev_info(battery->dev, + "%s: SEC Battery Driver Loaded\n", __func__); +#ifdef CONFIG_SAMSUNG_BATTERY_FACTORY + /* do not sleep in lpm mode & factory mode */ + if (sec_bat_is_lpm(battery)) { + wake_lock_init(&battery->lpm_wake_lock, WAKE_LOCK_SUSPEND, + "sec-lpm-monitor"); + wake_lock(&battery->lpm_wake_lock); + } +#endif + return 0; + + +err_req_ta_irq: + if (battery->pdata->ta_irq) + free_irq(battery->pdata->ta_irq, battery); +err_req_irq: + if (battery->pdata->bat_irq) + free_irq(battery->pdata->bat_irq, battery); +err_supply_unreg_bat: + power_supply_unregister(battery->psy_bat); +err_supply_unreg_ac: + power_supply_unregister(battery->psy_ac); +err_supply_unreg_usb: + power_supply_unregister(battery->psy_usb); +err_supply_unreg_wireless: + power_supply_unregister(battery->psy_wireless); +err_supply_unreg_ps: + power_supply_unregister(battery->psy_ps); +err_workqueue: + destroy_workqueue(battery->monitor_wqueue); +err_wake_lock: + wake_lock_destroy(&battery->monitor_wake_lock); + wake_lock_destroy(&battery->cable_wake_lock); + wake_lock_destroy(&battery->vbus_wake_lock); + wake_lock_destroy(&battery->vbus_detect_wake_lock); + mutex_destroy(&battery->adclock); +err_bat_free: + kfree(battery); + + return ret; +} + +static int sec_battery_remove(struct platform_device *pdev) +{ + struct sec_battery_info *battery = platform_get_drvdata(pdev); +#ifndef CONFIG_OF + int i; +#endif + + dev_dbg(battery->dev, "%s: Start\n", __func__); + + switch (battery->pdata->polling_type) { + case SEC_BATTERY_MONITOR_WORKQUEUE: + cancel_delayed_work(&battery->polling_work); + break; + case SEC_BATTERY_MONITOR_ALARM: + alarm_cancel(&battery->polling_alarm); + break; + default: + break; + } + + alarm_cancel(&battery->event_termination_alarm); + flush_workqueue(battery->monitor_wqueue); + destroy_workqueue(battery->monitor_wqueue); + wake_lock_destroy(&battery->monitor_wake_lock); + wake_lock_destroy(&battery->cable_wake_lock); + wake_lock_destroy(&battery->vbus_wake_lock); + wake_lock_destroy(&battery->vbus_detect_wake_lock); + + mutex_destroy(&battery->adclock); +#ifdef CONFIG_OF + adc_exit(battery); +#else + for (i = 0; i < SEC_BAT_ADC_CHANNEL_NUM; i++) + adc_exit(battery->pdata, i); +#endif + power_supply_unregister(battery->psy_ps); + power_supply_unregister(battery->psy_wireless); + power_supply_unregister(battery->psy_ac); + power_supply_unregister(battery->psy_usb); + power_supply_unregister(battery->psy_bat); + + dev_dbg(battery->dev, "%s: End\n", __func__); + kfree(battery); + + return 0; +} + +static int sec_battery_prepare(struct device *dev) +{ + struct sec_battery_info *battery + = dev_get_drvdata(dev); + + dev_dbg(battery->dev, "%s: Start\n", __func__); + + switch (battery->pdata->polling_type) { + case SEC_BATTERY_MONITOR_WORKQUEUE: + cancel_delayed_work(&battery->polling_work); + break; + case SEC_BATTERY_MONITOR_ALARM: + alarm_cancel(&battery->polling_alarm); + break; + default: + break; + } + cancel_delayed_work_sync(&battery->monitor_work); + + battery->polling_in_sleep = true; + + sec_bat_set_polling(battery); + + /* cancel work for polling + * that is set in sec_bat_set_polling() + * no need for polling in sleep + */ + if (battery->pdata->polling_type == + SEC_BATTERY_MONITOR_WORKQUEUE) + cancel_delayed_work(&battery->polling_work); + + dev_dbg(battery->dev, "%s: End\n", __func__); + + return 0; +} + +static int sec_battery_suspend(struct device *dev) +{ + return 0; +} + +static int sec_battery_resume(struct device *dev) +{ + return 0; +} + +static void sec_battery_complete(struct device *dev) +{ + struct sec_battery_info *battery + = dev_get_drvdata(dev); + + dev_dbg(battery->dev, "%s: Start\n", __func__); + + /* cancel current alarm and reset after monitor work */ + if (battery->pdata->polling_type == SEC_BATTERY_MONITOR_ALARM) + alarm_cancel(&battery->polling_alarm); + + wake_lock(&battery->monitor_wake_lock); + queue_delayed_work(battery->monitor_wqueue, + &battery->monitor_work, 0); + + dev_dbg(battery->dev, "%s: End\n", __func__); + + return; +} + +static void sec_battery_shutdown(struct device *dev) +{ +} + +#ifdef CONFIG_OF +static struct of_device_id sec_battery_dt_ids[] = { + { .compatible = "samsung,sec-battery" }, + { } +}; +MODULE_DEVICE_TABLE(of, sec_battery_dt_ids); +#endif /* CONFIG_OF */ + +static const struct dev_pm_ops sec_battery_pm_ops = { + .prepare = sec_battery_prepare, + .suspend = sec_battery_suspend, + .resume = sec_battery_resume, + .complete = sec_battery_complete, +}; + +static struct platform_driver sec_battery_driver = { + .driver = { + .name = "sec-battery", + .owner = THIS_MODULE, + .pm = &sec_battery_pm_ops, + .shutdown = sec_battery_shutdown, +#ifdef CONFIG_OF + .of_match_table = sec_battery_dt_ids, +#endif + }, + .probe = sec_battery_probe, + .remove = sec_battery_remove, +}; + +static int __init sec_battery_init(void) +{ + return platform_driver_register(&sec_battery_driver); +} + +static void __exit sec_battery_exit(void) +{ + platform_driver_unregister(&sec_battery_driver); +} + +late_initcall(sec_battery_init); +module_exit(sec_battery_exit); + +MODULE_DESCRIPTION("Samsung Battery Driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); diff --git a/drivers/battery/sec_board-mxc.c b/drivers/battery/sec_board-mxc.c new file mode 100644 index 00000000000000..e4a8733db83195 --- /dev/null +++ b/drivers/battery/sec_board-mxc.c @@ -0,0 +1,509 @@ +/* + * sec_board-mxc.c + * Samsung Mobile Battery Driver + * + * Copyright (C) 2012 Samsung Electronics + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include + +#if IS_ENABLED(CONFIG_FUELGAUGE_MAX17048) +#include +#endif + +#if IS_ENABLED(CONFIG_FUELGAUGE_MAX77823) || IS_ENABLED(CONFIG_FUELGAUGE_MAX77843) +#include +#endif + +//#include +//#include +#include +//#include + +#define SHORT_BATTERY_STANDARD 100 + +#if defined(CONFIG_EXTCON) +extern int get_jig_state(void); +#endif + +int current_cable_type = POWER_SUPPLY_TYPE_BATTERY; +extern unsigned int system_rev; + +#if defined(CONFIG_BATTERY_SAMSUNG_DATA) +#include CONFIG_BATTERY_SAMSUNG_DATA_FILE +#else //CONFIG_BATTERY_SAMSUNG_DATA +#if IS_ENABLED(CONFIG_FUELGAUGE_MAX17048) +static struct max17048_fuelgauge_battery_data_t max17048_battery_data[] = { + /* SDI battery data (High voltage 4.35V) */ + { + .RCOMP0 = 0x5D, + .RCOMP_charging = 0x5D, + .temp_cohot = -175, + .temp_cocold = -5825, + .is_using_model_data = true, + .type_str = "SDI", + } +}; +#endif + +#if IS_ENABLED(CONFIG_FUELGAUGE_MAX77823) || IS_ENABLED(CONFIG_FUELGAUGE_MAX77843) +static struct max77823_fuelgauge_battery_data_t max77823_battery_data[] = { + /* SDI battery data (High voltage 4.4V) */ + { + .Capacity = 5200, /* 2600 mAh * 10 mOhms / 5 uVh */ + .low_battery_comp_voltage = 2900000, + .low_battery_table = { + /* range, slope, offset */ + {-5000000, 0, 0}, /* dummy for top limit */ + {-1250000, 0, 3320}, + {-750000, 97, 3451}, + {-100000, 96, 3461}, + {0, 0, 3456}, + }, + .temp_adjust_table = { + /* range, slope, offset */ + {47000, 122, 8950}, + {60000, 200, 51000}, + {100000, 0, 0}, /* dummy for top limit */ + }, + .type_str = "SDI", + } +}; +#endif + +#define CAPACITY_MAX 990 +#define CAPACITY_MAX_MARGIN 50 +#define CAPACITY_MIN -7 + +static sec_bat_adc_table_data_t temp_table[] = { + {26009, 900}, + {26280, 850}, + {26600, 800}, + {26950, 750}, + {27325, 700}, + {27737, 650}, + {28180, 600}, + {28699, 550}, + {29360, 500}, + {29970, 450}, + {30995, 400}, + {32046, 350}, + {32985, 300}, + {34050, 250}, + {35139, 200}, + {36179, 150}, + {37208, 100}, + {38237, 50}, + {38414, 40}, + {38598, 30}, + {38776, 20}, + {38866, 10}, + {38956, 0}, + {39102, -10}, + {39247, -20}, + {39393, -30}, + {39538, -40}, + {39684, -50}, + {40490, -100}, + {41187, -150}, + {41652, -200}, + {42030, -250}, + {42327, -300}, +}; + +static sec_bat_adc_table_data_t chg_temp_table[] = { + {0, 0}, +}; + +#define TEMP_HIGH_THRESHOLD_EVENT 600 /* All temps in 1/10 C */ +#define TEMP_HIGH_RECOVERY_EVENT 460 +#define TEMP_LOW_THRESHOLD_EVENT -50 +#define TEMP_LOW_RECOVERY_EVENT 0 +#define TEMP_HIGH_THRESHOLD_NORMAL 600 +#define TEMP_HIGH_RECOVERY_NORMAL 460 +#define TEMP_LOW_THRESHOLD_NORMAL -50 +#define TEMP_LOW_RECOVERY_NORMAL 0 +#define TEMP_HIGH_THRESHOLD_LPM 600 +#define TEMP_HIGH_RECOVERY_LPM 460 +#define TEMP_LOW_THRESHOLD_LPM -50 +#define TEMP_LOW_RECOVERY_LPM 0 +#endif + +static void sec_bat_adc_ap_init(struct platform_device *pdev, + struct sec_battery_info *battery) +{ +} + +static int sec_bat_adc_ap_read(struct sec_battery_info *battery, int channel) +{ + int data = -1; + + switch (channel) + { + case SEC_BAT_ADC_CHANNEL_TEMP : + case SEC_BAT_ADC_CHANNEL_TEMP_AMBIENT: + data = 33000; + break; + default : + break; + } + + pr_debug("%s: data(%d)\n", __func__, data); + + return data; +} + +static void sec_bat_adc_ap_exit(void) +{ +} + +static void sec_bat_adc_none_init(struct platform_device *pdev, + struct sec_battery_info *battery) +{ +} + +static int sec_bat_adc_none_read(struct sec_battery_info *battery, int channel) +{ + return 0; +} + +static void sec_bat_adc_none_exit(void) +{ +} + +static void sec_bat_adc_ic_init(struct platform_device *pdev, + struct sec_battery_info *battery) +{ +} + +static int sec_bat_adc_ic_read(struct sec_battery_info *battery, int channel) +{ + return 0; +} + +static void sec_bat_adc_ic_exit(void) +{ +} +static int adc_read_type(struct sec_battery_info *battery, int channel) +{ + int adc = 0; + + switch (battery->pdata->temp_adc_type) + { + case SEC_BATTERY_ADC_TYPE_NONE : + adc = sec_bat_adc_none_read(battery, channel); + break; + case SEC_BATTERY_ADC_TYPE_AP : + adc = sec_bat_adc_ap_read(battery, channel); + break; + case SEC_BATTERY_ADC_TYPE_IC : + adc = sec_bat_adc_ic_read(battery, channel); + break; + case SEC_BATTERY_ADC_TYPE_NUM : + break; + default : + break; + } + pr_debug("[%s] ADC = %d\n", __func__, adc); + return adc; +} + +static void adc_init_type(struct platform_device *pdev, + struct sec_battery_info *battery) +{ + switch (battery->pdata->temp_adc_type) + { + case SEC_BATTERY_ADC_TYPE_NONE : + sec_bat_adc_none_init(pdev, battery); + break; + case SEC_BATTERY_ADC_TYPE_AP : + sec_bat_adc_ap_init(pdev, battery); + break; + case SEC_BATTERY_ADC_TYPE_IC : + sec_bat_adc_ic_init(pdev, battery); + break; + case SEC_BATTERY_ADC_TYPE_NUM : + break; + default : + break; + } +} + +static void adc_exit_type(struct sec_battery_info *battery) +{ + switch (battery->pdata->temp_adc_type) + { + case SEC_BATTERY_ADC_TYPE_NONE : + sec_bat_adc_none_exit(); + break; + case SEC_BATTERY_ADC_TYPE_AP : + sec_bat_adc_ap_exit(); + break; + case SEC_BATTERY_ADC_TYPE_IC : + sec_bat_adc_ic_exit(); + break; + case SEC_BATTERY_ADC_TYPE_NUM : + break; + default : + break; + } +} + +int adc_read(struct sec_battery_info *battery, int channel) +{ + int adc = 0; + + adc = adc_read_type(battery, channel); + + pr_debug("[%s]adc = %d\n", __func__, adc); + + return adc; +} + +void adc_exit(struct sec_battery_info *battery) +{ + adc_exit_type(battery); +} + +bool sec_bat_check_jig_status(void) +{ +#if defined(CONFIG_SEC_LENTIS_PROJECT) || defined(CONFIG_SEC_TRLTE_PROJECT) || defined(CONFIG_SEC_TBLTE_PROJECT) || \ + defined(CONFIG_SEC_KCCAT6_PROJECT) +#if defined(CONFIG_EXTCON) + return get_jig_state(); +#else + return false; +#endif +#else +#if 0 + if (!sec_fuelgauge) { + pr_err("%s: sec_fuelgauge is empty\n", __func__); + return false; + } + + if (sec_fuelgauge->pdata->jig_irq >= 0) { + if (gpio_get_value_cansleep(sec_fuelgauge->pdata->jig_irq)) + return true; + else + return false; + } else { + pr_err("%s: jig_irq is invalid\n", __func__); + return false; + } +#endif + return false; +#endif +} + +/* callback for battery check + * return : bool + * true - battery detected, false battery NOT detected + */ +bool sec_bat_check_callback(struct sec_battery_info *battery) +{ + struct power_supply *psy; + union power_supply_propval value; + + pr_debug("%s: battery->pdata->bat_irq_gpio(%d)\n", + __func__, battery->pdata->bat_irq_gpio); + psy = get_power_supply_by_name(battery->pdata->charger_name); + if (!psy) { + pr_err("%s: Failed to get psy (%s)\n", + __func__, battery->pdata->charger_name); + value.intval = 1; + } else { + int ret; + ret = psy->desc->get_property(psy, POWER_SUPPLY_PROP_PRESENT, &(value)); + if (ret < 0) { + pr_err("%s: Fail to sec-charger get_property (%d=>%d)\n", + __func__, POWER_SUPPLY_PROP_PRESENT, ret); + value.intval = 1; + } + } + return value.intval; +} + +void sec_bat_check_cable_result_callback(struct device *dev, + int cable_type) +{ + struct regulator *pma8084_lvs2; + int rc = 0; + current_cable_type = cable_type; + + if (current_cable_type == POWER_SUPPLY_TYPE_BATTERY) + { + pr_info("%s set lvs2 off\n", __func__); + pma8084_lvs2 = regulator_get(dev, "8084_lvs2"); + if (IS_ERR(pma8084_lvs2)) { + pr_err("%s: pma8084_lvs2 regulator_get fail\n", __func__); + return; + } else { + rc = regulator_disable(pma8084_lvs2); + if (rc) { + pr_err("%s: error for disabling regulator VF_1P8\n", __func__); + } + } + } + else + { + pr_info("%s set lvs2 on\n", __func__); + pma8084_lvs2 = regulator_get(dev, "8084_lvs2"); + if (IS_ERR(pma8084_lvs2)) { + pr_err("%s: pma8084_lvs2 regulator_get fail\n", __func__); + return; + } else { + if (!regulator_is_enabled(pma8084_lvs2)) { + rc = regulator_enable(pma8084_lvs2); + if (rc) { + pr_err("%s: error for enabling regulator VF_1P8\n", __func__); + } + } + } + } + regulator_put(pma8084_lvs2); +} + +int sec_bat_check_cable_callback(struct sec_battery_info *battery) +{ + union power_supply_propval value; + msleep(750); + + if (battery->pdata->ta_irq_gpio == 0) { + pr_err("%s: ta_int_gpio is 0 or not assigned yet(cable_type(%d))\n", + __func__, current_cable_type); + } else { + if (battery->cable_type == POWER_SUPPLY_TYPE_BATTERY && + !gpio_get_value_cansleep(battery->pdata->ta_irq_gpio)) { + pr_info("%s : VBUS IN\n", __func__); + + value.intval = POWER_SUPPLY_TYPE_UARTOFF; + psy_do_property("battery", set, POWER_SUPPLY_PROP_ONLINE, value); + current_cable_type = POWER_SUPPLY_TYPE_UARTOFF; + + return POWER_SUPPLY_TYPE_UARTOFF; + } + + if ((battery->cable_type == POWER_SUPPLY_TYPE_UARTOFF || + battery->cable_type == POWER_SUPPLY_TYPE_CARDOCK) && + gpio_get_value_cansleep(battery->pdata->ta_irq_gpio)) { + pr_info("%s : VBUS OUT\n", __func__); + + value.intval = POWER_SUPPLY_TYPE_BATTERY; + psy_do_property("battery", set, POWER_SUPPLY_PROP_ONLINE, value); + current_cable_type = POWER_SUPPLY_TYPE_BATTERY; + + return POWER_SUPPLY_TYPE_BATTERY; + } + } + + return current_cable_type; +} + +void board_battery_init(struct platform_device *pdev, struct sec_battery_info *battery) +{ + if ((!battery->pdata->temp_adc_table) && + (battery->pdata->thermal_source == SEC_BATTERY_THERMAL_SOURCE_ADC)) { + pr_info("%s : assign temp adc table\n", __func__); + + battery->pdata->temp_adc_table = temp_table; + battery->pdata->temp_amb_adc_table = temp_table; + + battery->pdata->temp_adc_table_size = sizeof(temp_table)/sizeof(sec_bat_adc_table_data_t); + battery->pdata->temp_amb_adc_table_size = sizeof(temp_table)/sizeof(sec_bat_adc_table_data_t); + } + + if ((!battery->pdata->chg_temp_adc_table) && + (battery->pdata->chg_temp_check)) { + pr_info("%s : assign chg temp adc table\n", __func__); + battery->pdata->chg_temp_adc_table = chg_temp_table; + battery->pdata->chg_temp_adc_table_size = sizeof(chg_temp_table)/sizeof(sec_bat_adc_table_data_t); + } + + battery->pdata->event_check = true; + battery->pdata->temp_high_threshold_event = TEMP_HIGH_THRESHOLD_EVENT; + battery->pdata->temp_high_recovery_event = TEMP_HIGH_RECOVERY_EVENT; + battery->pdata->temp_low_threshold_event = TEMP_LOW_THRESHOLD_EVENT; + battery->pdata->temp_low_recovery_event = TEMP_LOW_RECOVERY_EVENT; + battery->pdata->temp_high_threshold_normal = TEMP_HIGH_THRESHOLD_NORMAL; + battery->pdata->temp_high_recovery_normal = TEMP_HIGH_RECOVERY_NORMAL; + battery->pdata->temp_low_threshold_normal = TEMP_LOW_THRESHOLD_NORMAL; + battery->pdata->temp_low_recovery_normal = TEMP_LOW_RECOVERY_NORMAL; + battery->pdata->temp_high_threshold_lpm = TEMP_HIGH_THRESHOLD_LPM; + battery->pdata->temp_high_recovery_lpm = TEMP_HIGH_RECOVERY_LPM; + battery->pdata->temp_low_threshold_lpm = TEMP_LOW_THRESHOLD_LPM; + battery->pdata->temp_low_recovery_lpm = TEMP_LOW_RECOVERY_LPM; + + adc_init_type(pdev, battery); +} + +void board_fuelgauge_init(void *data) +{ +#if IS_ENABLED(CONFIG_FUELGAUGE_MAX17048) +#if defined(CONFIG_SEC_LENTIS_PROJECT) + if (system_rev >= 0x06) { +#endif + struct max17048_fuelgauge_data *fuelgauge = + (struct max17048_fuelgauge_data *)data; + + if (!fuelgauge->battery_data) { + pr_info("%s : assign battery data\n", __func__); + fuelgauge->battery_data = max17048_battery_data; + + pr_info("%s: RCOMP0: 0x%x, RCOMP_charging: 0x%x, " + "temp_cohot: %d, temp_cocold: %d, " + "is_using_model_data: %d, type_str: %s\n", __func__ , + fuelgauge->battery_data->RCOMP0, + fuelgauge->battery_data->RCOMP_charging, + fuelgauge->battery_data->temp_cohot, + fuelgauge->battery_data->temp_cocold, + fuelgauge->battery_data->is_using_model_data, + fuelgauge->battery_data->type_str + ); + } +#if defined(CONFIG_SEC_LENTIS_PROJECT) + } else { + struct max77823_fuelgauge_data *fuelgauge = + (struct max77823_fuelgauge_data *)data; + + if (!fuelgauge->battery_data) { + pr_info("%s : assign battery data\n", __func__); + fuelgauge->battery_data = max77823_battery_data; + } + } +#endif +#elif IS_ENABLED(CONFIG_FUELGAUGE_MAX77823) || IS_ENABLED(CONFIG_FUELGAUGE_MAX77843) + struct max77823_fuelgauge_data *fuelgauge = + (struct max77823_fuelgauge_data *)data; + + if (!fuelgauge->battery_data) { + pr_info("%s : assign battery data\n", __func__); + fuelgauge->battery_data = max77823_battery_data; + } +#endif +} +EXPORT_SYMBOL_GPL(board_fuelgauge_init); + +void cable_initial_check(struct sec_battery_info *battery) +{ + union power_supply_propval value; + + pr_info("%s : current_cable_type : (%d)\n", __func__, current_cable_type); + if (POWER_SUPPLY_TYPE_BATTERY != current_cable_type) { + value.intval = current_cable_type; + psy_do_property("battery", set, + POWER_SUPPLY_PROP_ONLINE, value); + } else { + psy_do_property(battery->pdata->charger_name, get, + POWER_SUPPLY_PROP_ONLINE, value); + if (value.intval == POWER_SUPPLY_TYPE_WIRELESS) { + value.intval = 1; + psy_do_property("wireless", set, + POWER_SUPPLY_PROP_ONLINE, value); + } + } +} +EXPORT_SYMBOL_GPL(cable_initial_check); diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index 3cc9bff9d99d9a..b7dca922daf4aa 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -76,6 +76,12 @@ config BT_HCIUART Say Y here to compile support for Bluetooth UART devices into the kernel or say M to compile it as module (hci_uart). +config BT_HCIUART_SERDEV + bool + depends on SERIAL_DEV_BUS && BT_HCIUART + depends on SERIAL_DEV_BUS=y || SERIAL_DEV_BUS=BT_HCIUART + default y + config BT_HCIUART_H4 bool "UART (H4) protocol support" depends on BT_HCIUART @@ -113,7 +119,7 @@ config BT_HCIUART_ATH3K config BT_HCIUART_LL bool "HCILL protocol support" - depends on BT_HCIUART + depends on BT_HCIUART_SERDEV help HCILL (HCI Low Level) is a serial protocol for communication between Bluetooth device and host. This protocol is required for @@ -148,6 +154,7 @@ config BT_HCIUART_INTEL config BT_HCIUART_BCM bool "Broadcom protocol support" depends on BT_HCIUART + depends on BT_HCIUART_SERDEV select BT_HCIUART_H4 select BT_BCM help diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index b1fc29a697b74a..32924458305c8c 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -29,6 +29,7 @@ btmrvl-y := btmrvl_main.o btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o hci_uart-y := hci_ldisc.o +hci_uart-$(CONFIG_BT_HCIUART_SERDEV) += hci_serdev.o hci_uart-$(CONFIG_BT_HCIUART_H4) += hci_h4.o hci_uart-$(CONFIG_BT_HCIUART_BCSP) += hci_bcsp.o hci_uart-$(CONFIG_BT_HCIUART_LL) += hci_ll.o diff --git a/drivers/bluetooth/btwilink.c b/drivers/bluetooth/btwilink.c index b6bb58c41df5b7..0cdb8961e9a129 100644 --- a/drivers/bluetooth/btwilink.c +++ b/drivers/bluetooth/btwilink.c @@ -262,7 +262,6 @@ static int ti_st_send_frame(struct hci_dev *hdev, struct sk_buff *skb) pkt_type = hci_skb_pkt_type(skb); len = hst->st_write(skb); if (len < 0) { - kfree_skb(skb); BT_ERR("ST write failed (%ld)", len); /* Try Again, would only fail if UART has gone bad */ return -EAGAIN; @@ -277,7 +276,7 @@ static int ti_st_send_frame(struct hci_dev *hdev, struct sk_buff *skb) static int bt_ti_probe(struct platform_device *pdev) { - static struct ti_st *hst; + struct ti_st *hst; struct hci_dev *hdev; int err; diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c index deed5801355524..9a6791d2137fd9 100644 --- a/drivers/bluetooth/hci_bcm.c +++ b/drivers/bluetooth/hci_bcm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -34,6 +36,7 @@ #include #include #include +#include #include #include @@ -41,11 +44,15 @@ #include "btbcm.h" #include "hci_uart.h" +#define BCM_NULL_PKT 0x00 +#define BCM_NULL_SIZE 0 + #define BCM_LM_DIAG_PKT 0x07 #define BCM_LM_DIAG_SIZE 63 #define BCM_AUTOSUSPEND_DELAY 5000 /* default autosleep delay */ +/* platform device driver resources */ struct bcm_device { struct list_head list; @@ -68,6 +75,12 @@ struct bcm_device { #endif }; +/* serdev driver resources */ +struct bcm_serdev { + struct hci_uart hu; +}; + +/* generic bcm uart resources */ struct bcm_data { struct sk_buff *rx_skb; struct sk_buff_head txq; @@ -79,6 +92,14 @@ struct bcm_data { static DEFINE_MUTEX(bcm_device_lock); static LIST_HEAD(bcm_device_list); +static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed) +{ + if (hu->serdev) + serdev_device_set_baudrate(hu->serdev, speed); + else + hci_uart_set_baudrate(hu, speed); +} + static int bcm_set_baudrate(struct hci_uart *hu, unsigned int speed) { struct hci_dev *hdev = hu->hdev; @@ -287,6 +308,14 @@ static int bcm_open(struct hci_uart *hu) hu->priv = bcm; + /* If this is a serdev defined device, then only use + * serdev open primitive and skip the rest. + */ + if (hu->serdev) { + serdev_device_open(hu->serdev); + goto out; + } + if (!hu->tty->dev) goto out; @@ -321,6 +350,12 @@ static int bcm_close(struct hci_uart *hu) bt_dev_dbg(hu->hdev, "hu %p", hu); + /* If this is a serdev defined device, only use serdev + * close primitive and then continue as usual. + */ + if (hu->serdev) + serdev_device_close(hu->serdev); + /* Protect bcm->dev against removal of the device or driver */ mutex_lock(&bcm_device_lock); if (bcm_device_exists(bdev)) { @@ -396,7 +431,7 @@ static int bcm_setup(struct hci_uart *hu) speed = 0; if (speed) - hci_uart_set_baudrate(hu, speed); + host_set_baudrate(hu, speed); /* Operational speed if any */ if (hu->oper_speed) @@ -409,7 +444,7 @@ static int bcm_setup(struct hci_uart *hu) if (speed) { err = bcm_set_baudrate(hu, speed); if (!err) - hci_uart_set_baudrate(hu, speed); + host_set_baudrate(hu, speed); } finalize: @@ -433,11 +468,19 @@ static int bcm_setup(struct hci_uart *hu) .lsize = 0, \ .maxlen = BCM_LM_DIAG_SIZE +#define BCM_RECV_NULL \ + .type = BCM_NULL_PKT, \ + .hlen = BCM_NULL_SIZE, \ + .loff = 0, \ + .lsize = 0, \ + .maxlen = BCM_NULL_SIZE + static const struct h4_recv_pkt bcm_recv_pkts[] = { { H4_RECV_ACL, .recv = hci_recv_frame }, { H4_RECV_SCO, .recv = hci_recv_frame }, { H4_RECV_EVENT, .recv = hci_recv_frame }, { BCM_RECV_LM_DIAG, .recv = hci_recv_diag }, + { BCM_RECV_NULL, .recv = hci_recv_diag }, }; static int bcm_recv(struct hci_uart *hu, const void *data, int count) @@ -860,9 +903,57 @@ static struct platform_driver bcm_driver = { }, }; +static int bcm_serdev_probe(struct serdev_device *serdev) +{ + struct bcm_serdev *bcmdev; + u32 speed; + int err; + + bcmdev = devm_kzalloc(&serdev->dev, sizeof(*bcmdev), GFP_KERNEL); + if (!bcmdev) + return -ENOMEM; + + bcmdev->hu.serdev = serdev; + serdev_device_set_drvdata(serdev, bcmdev); + + err = device_property_read_u32(&serdev->dev, "max-speed", &speed); + if (!err) + bcmdev->hu.oper_speed = speed; + + return hci_uart_register_device(&bcmdev->hu, &bcm_proto); +} + +static void bcm_serdev_remove(struct serdev_device *serdev) +{ + struct bcm_serdev *bcmdev = serdev_device_get_drvdata(serdev); + + hci_uart_unregister_device(&bcmdev->hu); +} + +#ifdef CONFIG_OF +static const struct of_device_id bcm_bluetooth_of_match[] = { + { .compatible = "brcm,bcm43438-bt" }, + { }, +}; +MODULE_DEVICE_TABLE(of, bcm_bluetooth_of_match); +#endif + +static struct serdev_device_driver bcm_serdev_driver = { + .probe = bcm_serdev_probe, + .remove = bcm_serdev_remove, + .driver = { + .name = "hci_uart_bcm", + .of_match_table = of_match_ptr(bcm_bluetooth_of_match), + }, +}; + int __init bcm_init(void) { + /* For now, we need to keep both platform device + * driver (ACPI generated) and serdev driver (DT). + */ platform_driver_register(&bcm_driver); + serdev_device_driver_register(&bcm_serdev_driver); return hci_uart_register_proto(&bcm_proto); } @@ -870,6 +961,7 @@ int __init bcm_init(void) int __exit bcm_deinit(void) { platform_driver_unregister(&bcm_driver); + serdev_device_driver_unregister(&bcm_serdev_driver); return hci_uart_unregister_proto(&bcm_proto); } diff --git a/drivers/bluetooth/hci_h4.c b/drivers/bluetooth/hci_h4.c index 635597b6e1681f..a98dd571f1ed23 100644 --- a/drivers/bluetooth/hci_h4.c +++ b/drivers/bluetooth/hci_h4.c @@ -171,9 +171,20 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, const unsigned char *buffer, int count, const struct h4_recv_pkt *pkts, int pkts_count) { + struct hci_uart *hu = hci_get_drvdata(hdev); + u8 alignment = hu->alignment ? hu->alignment : 1; + while (count) { int i, len; + /* remove padding bytes from buffer */ + for (; hu->padding && count > 0; hu->padding--) { + count--; + buffer++; + } + if (!count) + break; + if (!skb) { for (i = 0; i < pkts_count; i++) { if (buffer[0] != (&pkts[i])->type) @@ -253,11 +264,17 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, } if (!dlen) { + hu->padding = (skb->len - 1) % alignment; + hu->padding = (alignment - hu->padding) % alignment; + /* No more data, complete frame */ (&pkts[i])->recv(hdev, skb); skb = NULL; } } else { + hu->padding = (skb->len - 1) % alignment; + hu->padding = (alignment - hu->padding) % alignment; + /* Complete frame */ (&pkts[i])->recv(hdev, skb); skb = NULL; diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c index 9497c469efd225..23c53a04e740a9 100644 --- a/drivers/bluetooth/hci_ldisc.c +++ b/drivers/bluetooth/hci_ldisc.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -113,27 +114,42 @@ static inline struct sk_buff *hci_uart_dequeue(struct hci_uart *hu) { struct sk_buff *skb = hu->tx_skb; - if (!skb) - skb = hu->proto->dequeue(hu); - else + if (!skb) { + read_lock(&hu->proto_lock); + + if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) + skb = hu->proto->dequeue(hu); + + read_unlock(&hu->proto_lock); + } else { hu->tx_skb = NULL; + } return skb; } int hci_uart_tx_wakeup(struct hci_uart *hu) { + read_lock(&hu->proto_lock); + + if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) + goto no_schedule; + if (test_and_set_bit(HCI_UART_SENDING, &hu->tx_state)) { set_bit(HCI_UART_TX_WAKEUP, &hu->tx_state); - return 0; + goto no_schedule; } BT_DBG(""); schedule_work(&hu->write_work); +no_schedule: + read_unlock(&hu->proto_lock); + return 0; } +EXPORT_SYMBOL_GPL(hci_uart_tx_wakeup); static void hci_uart_write_work(struct work_struct *work) { @@ -176,6 +192,7 @@ static void hci_uart_init_work(struct work_struct *work) { struct hci_uart *hu = container_of(work, struct hci_uart, init_ready); int err; + struct hci_dev *hdev; if (!test_and_clear_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags)) return; @@ -183,9 +200,12 @@ static void hci_uart_init_work(struct work_struct *work) err = hci_register_dev(hu->hdev); if (err < 0) { BT_ERR("Can't register HCI device"); - hci_free_dev(hu->hdev); + hdev = hu->hdev; hu->hdev = NULL; + hci_free_dev(hdev); + clear_bit(HCI_UART_PROTO_READY, &hu->flags); hu->proto->close(hu); + return; } set_bit(HCI_UART_REGISTERED, &hu->flags); @@ -227,9 +247,13 @@ static int hci_uart_flush(struct hci_dev *hdev) tty_ldisc_flush(tty); tty_driver_flush_buffer(tty); + read_lock(&hu->proto_lock); + if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) hu->proto->flush(hu); + read_unlock(&hu->proto_lock); + return 0; } @@ -251,7 +275,15 @@ static int hci_uart_send_frame(struct hci_dev *hdev, struct sk_buff *skb) BT_DBG("%s: type %d len %d", hdev->name, hci_skb_pkt_type(skb), skb->len); + read_lock(&hu->proto_lock); + + if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) { + read_unlock(&hu->proto_lock); + return -EUNATCH; + } + hu->proto->enqueue(hu, skb); + read_unlock(&hu->proto_lock); hci_uart_tx_wakeup(hu); @@ -267,6 +299,12 @@ void hci_uart_set_flow_control(struct hci_uart *hu, bool enable) unsigned int set = 0; unsigned int clear = 0; + if (hu->serdev) { + serdev_device_set_flow_control(hu->serdev, !enable); + serdev_device_set_rts(hu->serdev, !enable); + return; + } + if (enable) { /* Disable hardware flow control */ ktermios = tty->termios; @@ -318,25 +356,6 @@ void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, hu->oper_speed = oper_speed; } -void hci_uart_init_tty(struct hci_uart *hu) -{ - struct tty_struct *tty = hu->tty; - struct ktermios ktermios; - - /* Bring the UART into a known 8 bits no parity hw fc state */ - ktermios = tty->termios; - ktermios.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | - INLCR | IGNCR | ICRNL | IXON); - ktermios.c_oflag &= ~OPOST; - ktermios.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); - ktermios.c_cflag &= ~(CSIZE | PARENB); - ktermios.c_cflag |= CS8; - ktermios.c_cflag |= CRTSCTS; - - /* tty_set_termios() return not checked as it is always 0 */ - tty_set_termios(tty, &ktermios); -} - void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed) { struct tty_struct *tty = hu->tty; @@ -459,9 +478,15 @@ static int hci_uart_tty_open(struct tty_struct *tty) hu->tty = tty; tty->receive_room = 65536; + /* disable alignment support by default */ + hu->alignment = 1; + hu->padding = 0; + INIT_WORK(&hu->init_ready, hci_uart_init_work); INIT_WORK(&hu->write_work, hci_uart_write_work); + rwlock_init(&hu->proto_lock); + /* Flush any pending characters in the driver */ tty_driver_flush_buffer(tty); @@ -477,6 +502,7 @@ static void hci_uart_tty_close(struct tty_struct *tty) { struct hci_uart *hu = tty->disc_data; struct hci_dev *hdev; + unsigned long flags; BT_DBG("tty %p", tty); @@ -490,9 +516,13 @@ static void hci_uart_tty_close(struct tty_struct *tty) if (hdev) hci_uart_close(hdev); - cancel_work_sync(&hu->write_work); + if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) { + write_lock_irqsave(&hu->proto_lock, flags); + clear_bit(HCI_UART_PROTO_READY, &hu->flags); + write_unlock_irqrestore(&hu->proto_lock, flags); + + cancel_work_sync(&hu->write_work); - if (test_and_clear_bit(HCI_UART_PROTO_READY, &hu->flags)) { if (hdev) { if (test_bit(HCI_UART_REGISTERED, &hu->flags)) hci_unregister_dev(hdev); @@ -551,13 +581,18 @@ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, if (!hu || tty != hu->tty) return; - if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) + read_lock(&hu->proto_lock); + + if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) { + read_unlock(&hu->proto_lock); return; + } /* It does not need a lock here as it is already protected by a mutex in * tty caller */ hu->proto->recv(hu, data, count); + read_unlock(&hu->proto_lock); if (hu->hdev) hu->hdev->stat.byte_rx += count; @@ -616,6 +651,7 @@ static int hci_uart_register_dev(struct hci_uart *hu) if (hci_register_dev(hdev) < 0) { BT_ERR("Can't register HCI device"); + hu->hdev = NULL; hci_free_dev(hdev); return -ENODEV; } diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c index 02692fe30279cb..60ec79d0bf9925 100644 --- a/drivers/bluetooth/hci_ll.c +++ b/drivers/bluetooth/hci_ll.c @@ -34,20 +34,25 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include #include +#include +#include #include +#include +#include #include #include +#include #include "hci_uart.h" @@ -76,6 +81,13 @@ struct hcill_cmd { u8 cmd; } __packed; +struct ll_device { + struct hci_uart hu; + struct serdev_device *serdev; + struct gpio_desc *enable_gpio; + struct clk *ext_clk; +}; + struct ll_struct { unsigned long rx_state; unsigned long rx_count; @@ -136,6 +148,13 @@ static int ll_open(struct hci_uart *hu) hu->priv = ll; + if (hu->serdev) { + struct ll_device *lldev = serdev_device_get_drvdata(hu->serdev); + serdev_device_open(hu->serdev); + if (!IS_ERR(lldev->ext_clk)) + clk_prepare_enable(lldev->ext_clk); + } + return 0; } @@ -164,6 +183,15 @@ static int ll_close(struct hci_uart *hu) kfree_skb(ll->rx_skb); + if (hu->serdev) { + struct ll_device *lldev = serdev_device_get_drvdata(hu->serdev); + gpiod_set_value_cansleep(lldev->enable_gpio, 0); + + clk_disable_unprepare(lldev->ext_clk); + + serdev_device_close(hu->serdev); + } + hu->priv = NULL; kfree(ll); @@ -505,9 +533,251 @@ static struct sk_buff *ll_dequeue(struct hci_uart *hu) return skb_dequeue(&ll->txq); } +#if IS_ENABLED(CONFIG_SERIAL_DEV_BUS) +static int read_local_version(struct hci_dev *hdev) +{ + int err = 0; + unsigned short version = 0; + struct sk_buff *skb; + struct hci_rp_read_local_version *ver; + + skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL, HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) { + bt_dev_err(hdev, "Reading TI version information failed (%ld)", + PTR_ERR(skb)); + return PTR_ERR(skb); + } + if (skb->len != sizeof(*ver)) { + err = -EILSEQ; + goto out; + } + + ver = (struct hci_rp_read_local_version *)skb->data; + if (le16_to_cpu(ver->manufacturer) != 13) { + err = -ENODEV; + goto out; + } + + version = le16_to_cpu(ver->lmp_subver); + +out: + if (err) bt_dev_err(hdev, "Failed to read TI version info: %d", err); + kfree_skb(skb); + return err ? err : version; +} + +/** + * download_firmware - + * internal function which parses through the .bts firmware + * script file intreprets SEND, DELAY actions only as of now + */ +static int download_firmware(struct ll_device *lldev) +{ + unsigned short chip, min_ver, maj_ver; + int version, err, len; + unsigned char *ptr, *action_ptr; + unsigned char bts_scr_name[40]; /* 40 char long bts scr name? */ + const struct firmware *fw; + struct sk_buff *skb; + struct hci_command *cmd; + + version = read_local_version(lldev->hu.hdev); + if (version < 0) + return version; + + chip = (version & 0x7C00) >> 10; + min_ver = (version & 0x007F); + maj_ver = (version & 0x0380) >> 7; + if (version & 0x8000) + maj_ver |= 0x0008; + + snprintf(bts_scr_name, sizeof(bts_scr_name), + "ti-connectivity/TIInit_%d.%d.%d.bts", + chip, maj_ver, min_ver); + + err = request_firmware(&fw, bts_scr_name, &lldev->serdev->dev); + if (err || !fw->data || !fw->size) { + bt_dev_err(lldev->hu.hdev, "request_firmware failed(errno %d) for %s", + err, bts_scr_name); + return -EINVAL; + } + ptr = (void *)fw->data; + len = fw->size; + /* bts_header to remove out magic number and + * version + */ + ptr += sizeof(struct bts_header); + len -= sizeof(struct bts_header); + + while (len > 0 && ptr) { + bt_dev_dbg(lldev->hu.hdev, " action size %d, type %d ", + ((struct bts_action *)ptr)->size, + ((struct bts_action *)ptr)->type); + + action_ptr = &(((struct bts_action *)ptr)->data[0]); + + switch (((struct bts_action *)ptr)->type) { + case ACTION_SEND_COMMAND: /* action send */ + bt_dev_dbg(lldev->hu.hdev, "S"); + cmd = (struct hci_command *)action_ptr; + if (cmd->opcode == 0xff36) { + /* ignore remote change + * baud rate HCI VS command */ + bt_dev_warn(lldev->hu.hdev, "change remote baud rate command in firmware"); + break; + } + if (cmd->prefix != 1) + bt_dev_dbg(lldev->hu.hdev, "command type %d\n", cmd->prefix); + + skb = __hci_cmd_sync(lldev->hu.hdev, cmd->opcode, cmd->plen, &cmd->speed, HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) { + bt_dev_err(lldev->hu.hdev, "send command failed\n"); + err = PTR_ERR(skb); + goto out_rel_fw; + } + kfree_skb(skb); + break; + case ACTION_WAIT_EVENT: /* wait */ + /* no need to wait as command was synchronous */ + bt_dev_dbg(lldev->hu.hdev, "W"); + break; + case ACTION_DELAY: /* sleep */ + bt_dev_info(lldev->hu.hdev, "sleep command in scr"); + mdelay(((struct bts_action_delay *)action_ptr)->msec); + break; + } + len -= (sizeof(struct bts_action) + + ((struct bts_action *)ptr)->size); + ptr += sizeof(struct bts_action) + + ((struct bts_action *)ptr)->size; + } + +out_rel_fw: + /* fw download complete */ + release_firmware(fw); + return err; +} + +static int ll_setup(struct hci_uart *hu) +{ + int err, retry = 3; + struct ll_device *lldev; + struct serdev_device *serdev = hu->serdev; + u32 speed; + + if (!serdev) + return 0; + + lldev = serdev_device_get_drvdata(serdev); + + serdev_device_set_flow_control(serdev, true); + + do { + /* Configure BT_EN to HIGH state */ + gpiod_set_value_cansleep(lldev->enable_gpio, 0); + msleep(5); + gpiod_set_value_cansleep(lldev->enable_gpio, 1); + msleep(100); + + err = download_firmware(lldev); + if (!err) + break; + + /* Toggle BT_EN and retry */ + bt_dev_err(hu->hdev, "download firmware failed, retrying..."); + } while (retry--); + + if (err) + return err; + + /* Operational speed if any */ + if (hu->oper_speed) + speed = hu->oper_speed; + else if (hu->proto->oper_speed) + speed = hu->proto->oper_speed; + else + speed = 0; + + if (speed) { + struct sk_buff *skb = __hci_cmd_sync(hu->hdev, 0xff36, sizeof(speed), &speed, HCI_INIT_TIMEOUT); + if (!IS_ERR(skb)) { + kfree_skb(skb); + serdev_device_set_baudrate(serdev, speed); + } + } + + return 0; +} + +static const struct hci_uart_proto llp; + +static int hci_ti_probe(struct serdev_device *serdev) +{ + struct hci_uart *hu; + struct ll_device *lldev; + u32 max_speed = 3000000; + + lldev = devm_kzalloc(&serdev->dev, sizeof(struct ll_device), GFP_KERNEL); + if (!lldev) + return -ENOMEM; + hu = &lldev->hu; + + serdev_device_set_drvdata(serdev, lldev); + lldev->serdev = hu->serdev = serdev; + + lldev->enable_gpio = devm_gpiod_get_optional(&serdev->dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(lldev->enable_gpio)) + return PTR_ERR(lldev->enable_gpio); + + lldev->ext_clk = devm_clk_get(&serdev->dev, "ext_clock"); + if (IS_ERR(lldev->ext_clk) && PTR_ERR(lldev->ext_clk) != -ENOENT) + return PTR_ERR(lldev->ext_clk); + + of_property_read_u32(serdev->dev.of_node, "max-speed", &max_speed); + hci_uart_set_speeds(hu, 115200, max_speed); + + return hci_uart_register_device(hu, &llp); +} + +static void hci_ti_remove(struct serdev_device *serdev) +{ + struct ll_device *lldev = serdev_device_get_drvdata(serdev); + + hci_uart_unregister_device(&lldev->hu); +} + +static const struct of_device_id hci_ti_of_match[] = { + { .compatible = "ti,wl1271-st" }, + { .compatible = "ti,wl1273-st" }, + { .compatible = "ti,wl1281-st" }, + { .compatible = "ti,wl1283-st" }, + { .compatible = "ti,wl1285-st" }, + { .compatible = "ti,wl1801-st" }, + { .compatible = "ti,wl1805-st" }, + { .compatible = "ti,wl1807-st" }, + { .compatible = "ti,wl1831-st" }, + { .compatible = "ti,wl1835-st" }, + { .compatible = "ti,wl1837-st" }, + {}, +}; +MODULE_DEVICE_TABLE(of, hci_ti_of_match); + +static struct serdev_device_driver hci_ti_drv = { + .driver = { + .name = "hci-ti", + .of_match_table = of_match_ptr(hci_ti_of_match), + }, + .probe = hci_ti_probe, + .remove = hci_ti_remove, +}; +#else +#define ll_setup NULL +#endif + static const struct hci_uart_proto llp = { .id = HCI_UART_LL, .name = "LL", + .setup = ll_setup, .open = ll_open, .close = ll_close, .recv = ll_recv, @@ -518,10 +788,14 @@ static const struct hci_uart_proto llp = { int __init ll_init(void) { + serdev_device_driver_register(&hci_ti_drv); + return hci_uart_register_proto(&llp); } int __exit ll_deinit(void) { + serdev_device_driver_unregister(&hci_ti_drv); + return hci_uart_unregister_proto(&llp); } diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c new file mode 100644 index 00000000000000..b725ac4f7ff67d --- /dev/null +++ b/drivers/bluetooth/hci_serdev.c @@ -0,0 +1,369 @@ +/* + * Bluetooth HCI serdev driver lib + * + * Copyright (C) 2017 Linaro, Ltd., Rob Herring + * + * Based on hci_ldisc.c: + * + * Copyright (C) 2000-2001 Qualcomm Incorporated + * Copyright (C) 2002-2003 Maxim Krasnyansky + * Copyright (C) 2004-2005 Marcel Holtmann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include "hci_uart.h" + +static struct serdev_device_ops hci_serdev_client_ops; + +static inline void hci_uart_tx_complete(struct hci_uart *hu, int pkt_type) +{ + struct hci_dev *hdev = hu->hdev; + + /* Update HCI stat counters */ + switch (pkt_type) { + case HCI_COMMAND_PKT: + hdev->stat.cmd_tx++; + break; + + case HCI_ACLDATA_PKT: + hdev->stat.acl_tx++; + break; + + case HCI_SCODATA_PKT: + hdev->stat.sco_tx++; + break; + } +} + +static inline struct sk_buff *hci_uart_dequeue(struct hci_uart *hu) +{ + struct sk_buff *skb = hu->tx_skb; + + if (!skb) + skb = hu->proto->dequeue(hu); + else + hu->tx_skb = NULL; + + return skb; +} + +static void hci_uart_write_work(struct work_struct *work) +{ + struct hci_uart *hu = container_of(work, struct hci_uart, write_work); + struct serdev_device *serdev = hu->serdev; + struct hci_dev *hdev = hu->hdev; + struct sk_buff *skb; + + /* REVISIT: + * should we cope with bad skbs or ->write() returning an error value? + */ + do { + clear_bit(HCI_UART_TX_WAKEUP, &hu->tx_state); + + while ((skb = hci_uart_dequeue(hu))) { + int len; + + len = serdev_device_write_buf(serdev, + skb->data, skb->len); + hdev->stat.byte_tx += len; + + skb_pull(skb, len); + if (skb->len) { + hu->tx_skb = skb; + break; + } + + hci_uart_tx_complete(hu, hci_skb_pkt_type(skb)); + kfree_skb(skb); + } + } while(test_bit(HCI_UART_TX_WAKEUP, &hu->tx_state)); + + clear_bit(HCI_UART_SENDING, &hu->tx_state); +} + +/* ------- Interface to HCI layer ------ */ + +/* Initialize device */ +static int hci_uart_open(struct hci_dev *hdev) +{ + BT_DBG("%s %p", hdev->name, hdev); + + return 0; +} + +/* Reset device */ +static int hci_uart_flush(struct hci_dev *hdev) +{ + struct hci_uart *hu = hci_get_drvdata(hdev); + + BT_DBG("hdev %p serdev %p", hdev, hu->serdev); + + if (hu->tx_skb) { + kfree_skb(hu->tx_skb); hu->tx_skb = NULL; + } + + /* Flush any pending characters in the driver and discipline. */ + serdev_device_write_flush(hu->serdev); + + if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) + hu->proto->flush(hu); + + return 0; +} + +/* Close device */ +static int hci_uart_close(struct hci_dev *hdev) +{ + BT_DBG("hdev %p", hdev); + + hci_uart_flush(hdev); + hdev->flush = NULL; + + return 0; +} + +/* Send frames from HCI layer */ +static int hci_uart_send_frame(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct hci_uart *hu = hci_get_drvdata(hdev); + + BT_DBG("%s: type %d len %d", hdev->name, hci_skb_pkt_type(skb), + skb->len); + + hu->proto->enqueue(hu, skb); + + hci_uart_tx_wakeup(hu); + + return 0; +} + +static int hci_uart_setup(struct hci_dev *hdev) +{ + struct hci_uart *hu = hci_get_drvdata(hdev); + struct hci_rp_read_local_version *ver; + struct sk_buff *skb; + unsigned int speed; + int err; + + /* Init speed if any */ + if (hu->init_speed) + speed = hu->init_speed; + else if (hu->proto->init_speed) + speed = hu->proto->init_speed; + else + speed = 0; + + if (speed) + serdev_device_set_baudrate(hu->serdev, speed); + + /* Operational speed if any */ + if (hu->oper_speed) + speed = hu->oper_speed; + else if (hu->proto->oper_speed) + speed = hu->proto->oper_speed; + else + speed = 0; + + if (hu->proto->set_baudrate && speed) { + err = hu->proto->set_baudrate(hu, speed); + if (err) + BT_ERR("%s: failed to set baudrate", hdev->name); + else + serdev_device_set_baudrate(hu->serdev, speed); + } + + if (hu->proto->setup) + return hu->proto->setup(hu); + + if (!test_bit(HCI_UART_VND_DETECT, &hu->hdev_flags)) + return 0; + + skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL, + HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) { + BT_ERR("%s: Reading local version information failed (%ld)", + hdev->name, PTR_ERR(skb)); + return 0; + } + + if (skb->len != sizeof(*ver)) { + BT_ERR("%s: Event length mismatch for version information", + hdev->name); + } + + kfree_skb(skb); + return 0; +} + +/** hci_uart_write_wakeup - transmit buffer wakeup + * @serdev: serial device + * + * This function is called by the serdev framework when it accepts + * more data being sent. + */ +static void hci_uart_write_wakeup(struct serdev_device *serdev) +{ + struct hci_uart *hu = serdev_device_get_drvdata(serdev); + + BT_DBG(""); + + if (!hu || serdev != hu->serdev) { + WARN_ON(1); + return; + } + + if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) + hci_uart_tx_wakeup(hu); +} + +/** hci_uart_receive_buf - receive buffer wakeup + * @serdev: serial device + * @data: pointer to received data + * @count: count of received data in bytes + * + * This function is called by the serdev framework when it received data + * in the RX buffer. + * + * Return: number of processed bytes + */ +static int hci_uart_receive_buf(struct serdev_device *serdev, const u8 *data, + size_t count) +{ + struct hci_uart *hu = serdev_device_get_drvdata(serdev); + + if (!hu || serdev != hu->serdev) { + WARN_ON(1); + return 0; + } + + if (!test_bit(HCI_UART_PROTO_READY, &hu->flags)) + return 0; + + /* It does not need a lock here as it is already protected by a mutex in + * tty caller + */ + hu->proto->recv(hu, data, count); + + if (hu->hdev) + hu->hdev->stat.byte_rx += count; + + return count; +} + +static struct serdev_device_ops hci_serdev_client_ops = { + .receive_buf = hci_uart_receive_buf, + .write_wakeup = hci_uart_write_wakeup, +}; + +int hci_uart_register_device(struct hci_uart *hu, + const struct hci_uart_proto *p) +{ + int err; + struct hci_dev *hdev; + + BT_DBG(""); + + serdev_device_set_client_ops(hu->serdev, &hci_serdev_client_ops); + + err = p->open(hu); + if (err) + return err; + + hu->proto = p; + set_bit(HCI_UART_PROTO_READY, &hu->flags); + + /* Initialize and register HCI device */ + hdev = hci_alloc_dev(); + if (!hdev) { + BT_ERR("Can't allocate HCI device"); + err = -ENOMEM; + goto err_alloc; + } + + hu->hdev = hdev; + + hdev->bus = HCI_UART; + hci_set_drvdata(hdev, hu); + + INIT_WORK(&hu->write_work, hci_uart_write_work); + + /* Only when vendor specific setup callback is provided, consider + * the manufacturer information valid. This avoids filling in the + * value for Ericsson when nothing is specified. + */ + if (hu->proto->setup) + hdev->manufacturer = hu->proto->manufacturer; + + hdev->open = hci_uart_open; + hdev->close = hci_uart_close; + hdev->flush = hci_uart_flush; + hdev->send = hci_uart_send_frame; + hdev->setup = hci_uart_setup; + SET_HCIDEV_DEV(hdev, &hu->serdev->dev); + + if (test_bit(HCI_UART_RAW_DEVICE, &hu->hdev_flags)) + set_bit(HCI_QUIRK_RAW_DEVICE, &hdev->quirks); + + if (test_bit(HCI_UART_EXT_CONFIG, &hu->hdev_flags)) + set_bit(HCI_QUIRK_EXTERNAL_CONFIG, &hdev->quirks); + + if (!test_bit(HCI_UART_RESET_ON_INIT, &hu->hdev_flags)) + set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks); + + if (test_bit(HCI_UART_CREATE_AMP, &hu->hdev_flags)) + hdev->dev_type = HCI_AMP; + else + hdev->dev_type = HCI_PRIMARY; + + if (test_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags)) + return 0; + + if (hci_register_dev(hdev) < 0) { + BT_ERR("Can't register HCI device"); + err = -ENODEV; + goto err_register; + } + + set_bit(HCI_UART_REGISTERED, &hu->flags); + + return 0; + +err_register: + hci_free_dev(hdev); +err_alloc: + clear_bit(HCI_UART_PROTO_READY, &hu->flags); + p->close(hu); + return err; +} +EXPORT_SYMBOL_GPL(hci_uart_register_device); + +void hci_uart_unregister_device(struct hci_uart *hu) +{ + struct hci_dev *hdev = hu->hdev; + + hci_unregister_dev(hdev); + hci_free_dev(hdev); + + cancel_work_sync(&hu->write_work); + + hu->proto->close(hu); +} +EXPORT_SYMBOL_GPL(hci_uart_unregister_device); diff --git a/drivers/bluetooth/hci_uart.h b/drivers/bluetooth/hci_uart.h index 070139513e6517..d9cd95d81149b1 100644 --- a/drivers/bluetooth/hci_uart.h +++ b/drivers/bluetooth/hci_uart.h @@ -58,6 +58,7 @@ #define HCI_UART_VND_DETECT 5 struct hci_uart; +struct serdev_device; struct hci_uart_proto { unsigned int id; @@ -77,6 +78,7 @@ struct hci_uart_proto { struct hci_uart { struct tty_struct *tty; + struct serdev_device *serdev; struct hci_dev *hdev; unsigned long flags; unsigned long hdev_flags; @@ -85,6 +87,7 @@ struct hci_uart { struct work_struct write_work; const struct hci_uart_proto *proto; + rwlock_t proto_lock; /* Stop work for proto close */ void *priv; struct sk_buff *tx_skb; @@ -92,6 +95,9 @@ struct hci_uart { unsigned int init_speed; unsigned int oper_speed; + + u8 alignment; + u8 padding; }; /* HCI_UART proto flag bits */ @@ -105,9 +111,11 @@ struct hci_uart { int hci_uart_register_proto(const struct hci_uart_proto *p); int hci_uart_unregister_proto(const struct hci_uart_proto *p); +int hci_uart_register_device(struct hci_uart *hu, const struct hci_uart_proto *p); +void hci_uart_unregister_device(struct hci_uart *hu); + int hci_uart_tx_wakeup(struct hci_uart *hu); int hci_uart_init_ready(struct hci_uart *hu); -void hci_uart_init_tty(struct hci_uart *hu); void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed); void hci_uart_set_flow_control(struct hci_uart *hu, bool enable); void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 8453a49471d72a..e4b99794113423 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -47,6 +47,7 @@ config SGI_MBCS say Y or M here, otherwise say N. source "drivers/tty/serial/Kconfig" +source "drivers/tty/serdev/Kconfig" config TTY_PRINTK tristate "TTY driver to output user messages via printk" @@ -91,6 +92,36 @@ config BFIN_OTP_WRITE_ENABLE If unsure, say N. +config FSL_OTP + tristate "Freescale On-Chip OTP Memory Support" + depends on HAS_IOMEM && OF + help + If you say Y here, you will get support for a character device + interface into the One Time Programmable memory pages that are + stored on the some Freescale i.MX processors. This will not get + you access to the secure memory pages however. You will need to + write your own secure code and reader for that. + + Note that default access is read-only. To enable writes, you + also need to select FSL_OTP_RW + + To compile this driver as a module, choose M here: the module + will be called fsl_otp. + + If unsure, it is safe to say Y. + +config FSL_OTP_RW + bool "Freescale On-Chip OTP Memory Write Access" + depends on FSL_OTP + default n + help + If you say Y here, you will get write access to the One Time + Programmable registers on certain Freescale i.MX processors. + Note that improper writes to these registers may prevent your + processor from booting. + + If unsure, say N + config PRINTER tristate "Parallel printer support" depends on PARPORT @@ -493,6 +524,17 @@ config RAW_DRIVER Applications should preferably open the device (eg /dev/hda1) with the O_DIRECT flag. +config MAGSTRIPE + tristate "Neuron magstripe reader support through GPIO" + default n + help + This driver enables support for a Neuron MCR-370T-1R-xxxx + insertion-style magnetic stripe card reader, connected via + GPIO. GPIO pin assignments are defined through the device tree. + Only a single instance is currently supported. + + If compiled as a module, it will be named magdecode.ko + config MAX_RAW_DEVS int "Maximum number of RAW devices to support (1-65536)" depends on RAW_DRIVER @@ -580,6 +622,21 @@ config DEVPORT source "drivers/s390/char/Kconfig" +config SAS + tristate "Slot Accounting Service driver" + default n + help + This driver enables support for a 9-bit serial driver that + uses MARK/SPACE parity to frame messages for the Slot Accounting + System (SAS) protocol. + + If compiled as a module, it will be named sas.ko + +config SAS_PARTIAL_RX + bool "Return received character without regard to message boundaries" + depends on SAS + default n + config TILE_SROM bool "Character-device access via hypervisor to the Tilera SPI ROM" depends on TILE @@ -593,5 +650,11 @@ config TILE_SROM source "drivers/char/xillybus/Kconfig" +source "drivers/char/imx_amp/Kconfig" + +config DUMMY_I2C_DEVICE + tristate "dummy clock/regulator/gpio consumer" + depends on I2C + endmenu diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 6e6c244a66a02c..979189b775c4d4 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o obj-$(CONFIG_IBM_BSR) += bsr.o obj-$(CONFIG_SGI_MBCS) += mbcs.o obj-$(CONFIG_BFIN_OTP) += bfin-otp.o +obj-$(CONFIG_FSL_OTP) += fsl_otp.o obj-$(CONFIG_PRINTER) += lp.o @@ -36,6 +37,8 @@ endif obj-$(CONFIG_TOSHIBA) += toshiba.o obj-$(CONFIG_DS1620) += ds1620.o obj-$(CONFIG_HW_RANDOM) += hw_random/ +obj-$(CONFIG_MAGSTRIPE) += magdecode.o +obj-$(CONFIG_SAS) += sas.o obj-$(CONFIG_PPDEV) += ppdev.o obj-$(CONFIG_NWBUTTON) += nwbutton.o obj-$(CONFIG_NWFLASH) += nwflash.o @@ -60,3 +63,5 @@ js-rtc-y = rtc.o obj-$(CONFIG_TILE_SROM) += tile-srom.o obj-$(CONFIG_XILLYBUS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o +obj-$(CONFIG_HAVE_IMX_AMP) += imx_amp/ +obj-$(CONFIG_DUMMY_I2C_DEVICE) += dummy_i2c_device.o diff --git a/drivers/char/dummy_i2c_device.c b/drivers/char/dummy_i2c_device.c new file mode 100644 index 00000000000000..7fcf79cf88af30 --- /dev/null +++ b/drivers/char/dummy_i2c_device.c @@ -0,0 +1,186 @@ +/* + * Boundary Devices FTx06 touch screen controller. + * + * Copyright (c) by Boundary Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +struct dummy_i2c_device { + struct clk *clk; + struct regulator *c1; + struct regulator *c2; + struct gpio_descs *reset_gpios; + struct gpio_descs *enable_gpios; +}; + +static const char reset_gpios[] = "reset"; +static const char enable_gpios[] = "enable"; + +static void di2cd_set_gpios(struct gpio_descs *d, int active) +{ + int i; + + for (i = 0; i < d->ndescs; i++) + gpiod_set_value(d->desc[i], active); +} + +static struct gpio_descs* di2cd_setup_gpios(struct device *dev, const char* name, int active) +{ + struct gpio_descs *d; + int i; + + d = devm_gpiod_get_array_optional(dev, name, active ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW); + + if (IS_ERR(d)) + return d; + if (!d) + return d; + for (i = 0; i < d->ndescs; i++) { + struct gpio_desc *gd = d->desc[i]; + + dev_info(dev, "%s: %d active %s\n", name, desc_to_gpio(gd), gpiod_is_active_low(gd) ? "low" : "high"); + } + return d; +} + +static int di2cd_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct clk *clk; + struct dummy_i2c_device *d; + struct device *dev = &client->dev; + struct regulator *c; + int ret; + + d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); + if (!d) { + dev_err(&client->dev, "Failed to allocate memory\n"); + return -ENOMEM; + } + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + /* assuming clock enabled by default */ + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(dev, "clk missing(%ld)\n", PTR_ERR(clk)); + return PTR_ERR(clk); + } + d->clk = clk; + + c = devm_regulator_get(dev, "c1"); + if (IS_ERR(c)) { + if (PTR_ERR(c) == -EPROBE_DEFER) + return PTR_ERR(c); + pr_err("%s: c1 devm_regulator_get failed(%ld), ignoring\n", __func__, PTR_ERR(c)); + c = NULL; + } + d->c1 = c; + + c = devm_regulator_get(dev, "c2"); + if (IS_ERR(c)) { + if (PTR_ERR(c) == -EPROBE_DEFER) + return PTR_ERR(c); + pr_err("%s: c2 devm_regulator_get failed(%ld), ignoring\n", __func__, PTR_ERR(c)); + c = NULL; + } + d->c2 = c; + i2c_set_clientdata(client, d); + + clk_prepare_enable(clk); + pr_info("%s: enabled\n", __func__); + if (d->c1) { + ret = regulator_enable(d->c1); + if (ret) { + pr_err("%s:c1 enable error\n", __func__); + return ret; + } + } + + if (d->c2) { + ret = regulator_enable(d->c2); + if (ret) { + pr_err("%s:c2 enable error\n", __func__); + return ret; + } + } + d->reset_gpios = di2cd_setup_gpios(dev, reset_gpios, 0); + d->enable_gpios = di2cd_setup_gpios(dev, enable_gpios, 1); + + return 0; +} + +static int di2cd_remove(struct i2c_client *client) +{ + struct dummy_i2c_device *d = i2c_get_clientdata(client); + + di2cd_set_gpios(d->reset_gpios, 1); + di2cd_set_gpios(d->enable_gpios, 0); + + clk_disable_unprepare(d->clk); + if (d->c1) + regulator_disable(d->c1); + if (d->c2) + regulator_disable(d->c2); + return 0; +} + +static const struct i2c_device_id di2cd_idtable[] = { + { "dummy_i2c_device", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, di2cd_idtable); + +static const struct of_device_id di2cd_dt_ids[] = { + { + .compatible = "dummy_i2c_device", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, di2cd_dt_ids); + +static struct i2c_driver di2cd_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "dummy_i2c_device", + .of_match_table = di2cd_dt_ids, + }, + .id_table = di2cd_idtable, + .probe = di2cd_probe, + .remove = di2cd_remove, +}; + +module_i2c_driver(di2cd_driver); + +MODULE_AUTHOR("Boundary Devices "); +MODULE_DESCRIPTION("I2C interface dummy device."); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/fsl_otp.c b/drivers/char/fsl_otp.c new file mode 100644 index 00000000000000..3374c2bf582d97 --- /dev/null +++ b/drivers/char/fsl_otp.c @@ -0,0 +1,744 @@ +/* + * Freescale On-Chip OTP driver + * + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HW_OCOTP_CTRL 0x00000000 +#define HW_OCOTP_CTRL_SET 0x00000004 +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00000400 +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000007F +#define BM_OCOTP_CTRL_ADDR_MX7D 0x0000000F +#define BP_OCOTP_CTRL_ADDR_MX7ULP 0 +#define BM_OCOTP_CTRL_ADDR_MX7ULP 0x000000FF + +#define HW_OCOTP_TIMING 0x00000010 +#define BP_OCOTP_TIMING_STROBE_READ 16 +#define BM_OCOTP_TIMING_STROBE_READ 0x003F0000 +#define BP_OCOTP_TIMING_RELAX 12 +#define BM_OCOTP_TIMING_RELAX 0x0000F000 +#define BP_OCOTP_TIMING_STROBE_PROG 0 +#define BM_OCOTP_TIMING_STROBE_PROG 0x00000FFF + +#define BP_TIMING_FSOURCE 12 +#define BM_TIMING_FSOURCE 0x0007F000 +#define BV_TIMING_FSOURCE_NS 1001 +#define BP_TIMING_PROG 0 +#define BM_TIMING_PROG 0x00000FFF +#define BV_TIMING_PROG_US 10 + +#define HW_OCOTP_DATA 0x00000020 + +#define HW_OCOTP_DATA0_MX7D 0x00000020 +#define HW_OCOTP_DATA1_MX7D 0x00000030 +#define HW_OCOTP_DATA2_MX7D 0x00000040 +#define HW_OCOTP_DATA3_MX7D 0x00000050 + +#define HW_OCOTP_PDN_ULP 0x00000010 +#define HW_OCOTP_OUT_STATUS_ULP 0x00000090 +#define HW_OCOTP_OUT_STATUS_CLR_ULP 0x00000098 + +#define BM_OUT_STATUS_DED_RELOAD_ULP (1 << 20) +#define BM_OUT_STATUS_SEC_RELOAD_ULP (1 << 19) +#define BM_OUT_STATUS_PROGFAIL (1 << 12) +#define BM_OUT_STATUS_LOCKED (1 << 11) +#define BM_OUT_STATUS_DED_ULP (1 << 10) + +#ifdef CONFIG_FSL_OTP_RW +#define SYSFS_MODE 0600 +#else +#define SYSFS_MODE 0400 +#endif + +#define HW_OCOTP_CUST_N(n) (0x00000400 + (n) * 0x10) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#define DEF_RELAX 20 /* > 16.5ns */ + +#define BANK8(a, b, c, d, e, f, g, h) { \ + "HW_OCOTP_"#a, "HW_OCOTP_"#b, "HW_OCOTP_"#c, "HW_OCOTP_"#d, \ + "HW_OCOTP_"#e, "HW_OCOTP_"#f, "HW_OCOTP_"#g, "HW_OCOTP_"#h, \ +} + +#define BANK4(a, b, c, d) { \ + "HW_OCOTP_"#a, "HW_OCOTP_"#b, "HW_OCOTP_"#c, "HW_OCOTP_"#d, \ +} + +static const char *imx6q_otp_desc[16][8] = { + BANK8(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK8(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK8(RESP0, HSJC_RESP1, MAC0, MAC1, HDCP_KSV0, HDCP_KSV1, GP1, GP2), + BANK8(DTCP_KEY0, DTCP_KEY1, DTCP_KEY2, DTCP_KEY3, DTCP_KEY4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK8(HDCP_KEY0, HDCP_KEY1, HDCP_KEY2, HDCP_KEY3, HDCP_KEY4, HDCP_KEY5, HDCP_KEY6, HDCP_KEY7), + BANK8(HDCP_KEY8, HDCP_KEY9, HDCP_KEY10, HDCP_KEY11, HDCP_KEY12, HDCP_KEY13, HDCP_KEY14, HDCP_KEY15), + BANK8(HDCP_KEY16, HDCP_KEY17, HDCP_KEY18, HDCP_KEY19, HDCP_KEY20, HDCP_KEY21, HDCP_KEY22, HDCP_KEY23), + BANK8(HDCP_KEY24, HDCP_KEY25, HDCP_KEY26, HDCP_KEY27, HDCP_KEY28, HDCP_KEY29, HDCP_KEY30, HDCP_KEY31), + BANK8(HDCP_KEY32, HDCP_KEY33, HDCP_KEY34, HDCP_KEY35, HDCP_KEY36, HDCP_KEY37, HDCP_KEY38, HDCP_KEY39), + BANK8(HDCP_KEY40, HDCP_KEY41, HDCP_KEY42, HDCP_KEY43, HDCP_KEY44, HDCP_KEY45, HDCP_KEY46, HDCP_KEY47), + BANK8(HDCP_KEY48, HDCP_KEY49, HDCP_KEY50, HDCP_KEY51, HDCP_KEY52, HDCP_KEY53, HDCP_KEY54, HDCP_KEY55), + BANK8(HDCP_KEY56, HDCP_KEY57, HDCP_KEY58, HDCP_KEY59, HDCP_KEY60, HDCP_KEY61, HDCP_KEY62, HDCP_KEY63), + BANK8(HDCP_KEY64, HDCP_KEY65, HDCP_KEY66, HDCP_KEY67, HDCP_KEY68, HDCP_KEY69, HDCP_KEY70, HDCP_KEY71), + BANK8(CRC0, CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7), +}; + +static const char *imx6sl_otp_desc[][8] = { + BANK8(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK8(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK8(SJC_RESP0, SJC_RESP1, MAC0, MAC1, CRC0, CRC1, GP1, GP2), + BANK8(SW_GP0, SW_GP1, SW_GP2, SW_GP3, SW_GP4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK8(GP_LO0, GP_LO1, GP_LO2, GP_LO3, GP_LO4, GP_LO5, GP_LO6, GP_LO7), + BANK8(GP_HI0, GP_HI1, GP_HI2, GP_HI3, GP_HI4, GP_HI5, GP_HI6, GP_HI7), +}; + +static const char *imx6sll_otp_desc[][8] = { + BANK8(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK8(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, USB), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK8(SJC_RESP0, SJC_RESP1, MAC0, MAC1, MAC2, CRC0, GP1, GP2), + BANK8(SW_GP0, SW_GP1, SW_GP2, SW_GP3, SW_GP4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK8(ROM_PATCH0, ROM_PATCH1, ROM_PATCH2, ROM_PATCH3, ROM_PATCH4, ROM_PATCH5, ROM_PATCH6, ROM_PATCH7), + BANK8(GP30, GP31, GP32, GP33, GP40, GP41, GP42, GP43), +}; + +static const char *imx6ul_otp_desc[][8] = { + BANK8(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK8(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK8(SJC_RESP0, SJC_RESP1, MAC0, MAC1, MAC2, CRC, GP1, GP2), + BANK8(SW_GP0, SW_GP1, SW_GP2, SW_GP3, SW_GP4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK8(ROM_PATCH0, ROM_PATCH1, ROM_PATCH2, ROM_PATCH3, ROM_PATCH4, ROM_PATCH5, ROM_PATCH6, ROM_PATCH7), + BANK8(ROM_PATCH8, ROM_PATCH9, ROM_PATCH10, ROM_PATCH11, ROM_PATCH12, ROM_PATCH13, ROM_PATCH14, ROM_PATCH15), + BANK8(GP30, GP31, GP32, GP33, GP34, GP35, GP36, GP37), + BANK8(GP38, GP39, GP310, GP311, GP312, GP313, GP314, GP315), + BANK8(GP40, GP41, GP42, GP43, GP44, GP45, GP46, GP47), + BANK8(GP48, GP49, GP410, GP411, GP412, GP413, GP414, GP415), + BANK8(GP50, GP51, GP52, GP53, GP54, GP55, GP56, GP57), + BANK8(GP58, GP59, GP510, GP511, GP512, GP513, GP514, GP515), + BANK8(GP60, GP61, GP62, GP63, GP64, GP65, GP66, GP67), + BANK8(GP70, GP71, GP72, GP73, GP80, GP81, GP82, GP83), +}; + +static const char *imx6ull_otp_desc[][8] = { + BANK8(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK8(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK8(SJC_RESP0, SJC_RESP1, MAC0, MAC1, MAC2, CRC, GP1, GP2), + BANK8(SW_GP0, SW_GP1, SW_GP2, SW_GP3, SW_GP4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK8(ROM_PATCH0, ROM_PATCH1, ROM_PATCH2, ROM_PATCH3, ROM_PATCH4, ROM_PATCH5, ROM_PATCH6, ROM_PATCH7), + BANK8(GP30, GP31, GP32, GP33, GP40, GP41, GP42, GP43), +}; + +static const char *imx7d_otp_desc[][4] = { + BANK4(LOCK, TESTER0, TESTER1, TESTER2), + BANK4(TESTER3, TESTER4, TESTER5, BOOT_CFG0), + BANK4(BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4), + BANK4(MEM_TRIM0, MEM_TRIM1, ANA0, ANA1), + BANK4(OTPMK0, OTPMK1, OTPMK2, OTPMK3), + BANK4(OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK4(SRK0, SRK1, SRK2, SRK3), + BANK4(SRK4, SRK5, SRK6, SRK7), + BANK4(SJC_RESP0, SJC_RESP1, USB_ID, FIELD_RETURN), + BANK4(MAC_ADDR0, MAC_ADDR1, MAC_ADDR2, SRK_REVOKE), + BANK4(MAU_KEY0, MAU_KEY1, MAU_KEY2, MAU_KEY3), + BANK4(MAU_KEY4, MAU_KEY5, MAU_KEY6, MAU_KEY7), + BANK4(ROM_PATCH0, ROM_PATCH1, ROM_PATCH2, ROM_PATCH3), + BANK4(ROM_PATCH4, ROM_PATCH5, ROM_PATCH6, ROM_PATCH7), + BANK4(GP10, GP11, GP20, GP21), + BANK4(CRC_GP10, CRC_GP11, CRC_GP20, CRC_GP21), +}; + +static const char *imx7ulp_otp_desc[][8] = { + BANK8(TESTER0, TESTER1, TESTER2, TESTER3, TESTER4, TESTER5, TESTER6, TESTER7), + BANK8(LOCK0, LOCK1, LOCK2, CFG0, CFG1, CFG2, CFG3, CFG4), + BANK8(BOOT0, BOOT1, BOOT2, BOOT3, BOOT4, BOOT5, BOOT6, BOOT7), + BANK8(MEM0, MEM1, MEM2, MEM3, ANA0, ANA1, ANA2, ANA3), + BANK8(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK8(A7_SRK0, A7_SRK1, A7_SRK2, A7_SRK3, A7_SRK4, A7_SRK5, A7_SRK6, A7_SRK7), + BANK8(M4_SRK0, M4_SRK1, M4_SRK2, M4_SRK3, M4_SRK4, M4_SRK5, M4_SRK6, M4_SRK7), + BANK8(SJC_RESP0, SJC_RESP1, GP0, GP1, GP2, GP3, GP4, GP5), + BANK8(MAU_KEY0, MAU_KEY1, MAU_KEY2, MAU_KEY3, MAU_KEY4, MAU_KEY5, MAU_KEY6, MAU_KEY7), + BANK8(TESTER10, TESTER11, TESTER12, TESTER13, TESTER14, TESTER15, FIELD_RETURN, SRK_REVOKE), + BANK8(PMU0, PMU1, PMU2, PMU3, PMU4, PMU5, PMU6, PMU7), + BANK8(A7_PATCH0, A7_PATCH1, A7_PATCH2, A7_PATCH3, A7_PATCH4, A7_PATCH5, A7_PATCH6, A7_PATCH7), + BANK8(A7_PATCH10, A7_PATCH11, A7_PATCH12, A7_PATCH13, A7_PATCH14, A7_PATCH15, A7_PATCH16, A7_PATCH17), + BANK8(A7_PATCH20, A7_PATCH21, A7_PATCH22, A7_PATCH23, A7_PATCH24, A7_PATCH25, A7_PATCH26, A7_PATCH27), + BANK8(A7_PATCH30, A7_PATCH31, A7_PATCH32, A7_PATCH33, A7_PATCH34, A7_PATCH35, A7_PATCH36, A7_PATCH37), + BANK8(GP10, GP11, GP12, GP13, GP14, GP15, GP16, GP17), + BANK8(GP20, GP21, GP22, GP23, GP24, GP25, GP26, GP27), + BANK8(GP30, GP31, GP32, GP33, GP34, GP35, GP36, GP37), + BANK8(GP40, GP41, GP42, GP43, GP44, GP45, GP46, GP47), + BANK8(GP50, GP51, GP52, GP53, GP54, GP55, GP56, GP57), + BANK8(M4_PATCH0, M4_PATCH1, M4_PATCH2, M4_PATCH3, M4_PATCH4, M4_PATCH5, M4_PATCH6, M4_PATCH7), + BANK8(M4_PATCH10, M4_PATCH11, M4_PATCH12, M4_PATCH13, M4_PATCH14, M4_PATCH15, M4_PATCH16, M4_PATCH17), + BANK8(M4_PATCH20, M4_PATCH21, M4_PATCH22, M4_PATCH23, M4_PATCH24, M4_PATCH25, M4_PATCH26, M4_PATCH27), + BANK8(M4_PATCH30, M4_PATCH31, M4_PATCH32, M4_PATCH33, M4_PATCH34, M4_PATCH35, M4_PATCH36, M4_PATCH37), + BANK8(GP60, GP61, GP62, GP63, GP64, GP65, GP66, GP67), + BANK8(GP70, GP71, GP72, GP73, GP74, GP75, GP76, GP77), + BANK8(GP80, GP81, GP82, GP83, GP84, GP85, GP86, GP87), + BANK8(GP90, GP91, GP92, GP93, GP94, GP95, GP96, GP97), + BANK8(TRIM0, TRIM1, TRIM2, TRIM3, TRIM4, TRIM5, TRIM6, TRIM7), + BANK8(OTFAD_KEY0, OTFAD_KEY1, OTFAD_KEY2, OTFAD_KEY3, OTFAD_CFG0, OTFAD_CFG1, OTFAD_CFG2, OTFAD_CFG3), + BANK8(CRC0, CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7), +}; + +static DEFINE_MUTEX(otp_mutex); +static void __iomem *otp_base; +static struct clk *otp_clk; +struct kobject *otp_kobj; +struct kobj_attribute *otp_kattr; +struct attribute_group *otp_attr_group; + +enum fsl_otp_devtype { + FSL_OTP_MX6Q, + FSL_OTP_MX6DL, + FSL_OTP_MX6SX, + FSL_OTP_MX6SL, + FSL_OTP_MX6SLL, + FSL_OTP_MX6UL, + FSL_OTP_MX6ULL, + FSL_OTP_MX7D, + FSL_OTP_MX7ULP, +}; + +struct fsl_otp_devtype_data { + enum fsl_otp_devtype devtype; + const char **bank_desc; + int fuse_nums; + void (*set_otp_timing)(void); +}; + +static struct fsl_otp_devtype_data *fsl_otp; + +/* + * fsl_otp_bank_physical and fsl_otp_word_physical are used to + * find the physical index of the word. Only used for calculating + * offset of the word, means only effective when reading fuse. + * Do not use the two functions for prog fuse. Always use the word + * index from fuse map to prog the fuse. + * + * Take i.MX6UL for example: + * there are holes between bank 5 and bank 6. The hole is 0x100 bytes. + * To bank 15, word 7, the word index is 15 * 8 + 7. The physical word + * index is 15 * 8 + 0x100 / 0x10 + 7, 0x100 contains 16 words. + * So use 15 * 8 + 7 to prog the fuse. And when reading, account the hole + * using offset 0x400 + (15 * 8 + 0x100 / 0x10 + 7) * 0x10. + * + * There is a hole in shadow registers address map of size 0x100 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. + * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, + * account for this hole in address space. + * + * Similar hole exists between bank 14 and bank 15 of size 0x80 + * on iMX6QP, iMX6DQ, iMX6SDL, i.MX6SLL and iMX6SX. + * Note: iMX6SL has only 0-7 banks and there is no hole. + * Note: iMX6UL doesn't have this one. + * + * To i.MX6SLL, there are 9 banks. bank 7 and bank8 only contain 4 words + * each. Other banks contains 8 words. + */ +static u32 fsl_otp_bank_physical(struct fsl_otp_devtype_data *d, int bank) +{ + u32 phy_bank; + + if ((bank == 0) || (d->devtype == FSL_OTP_MX6SL) || + (d->devtype == FSL_OTP_MX7D) || (d->devtype == FSL_OTP_MX7ULP)) + phy_bank = bank; + else if ((d->devtype == FSL_OTP_MX6UL) || + (d->devtype == FSL_OTP_MX6ULL) || + (d->devtype == FSL_OTP_MX6SLL)) { + if (bank >= 6) + phy_bank = fsl_otp_bank_physical(d, 5) + bank - 3; + else + phy_bank = bank; + } else { + if (bank >= 15) + phy_bank = fsl_otp_bank_physical(d, 14) + bank - 13; + else if (bank >= 6) + phy_bank = fsl_otp_bank_physical(d, 5) + bank - 3; + else + phy_bank = bank; + } + + return phy_bank; +} + +static u32 fsl_otp_word_physical(struct fsl_otp_devtype_data *d, int index) +{ + u32 phy_bank_off; + u32 word_off, bank_off; + u32 words_per_bank; + + if (d->devtype == FSL_OTP_MX7D) + words_per_bank = 4; + else + words_per_bank = 8; + + bank_off = index / words_per_bank; + word_off = index % words_per_bank; + phy_bank_off = fsl_otp_bank_physical(d, bank_off); + + return phy_bank_off * words_per_bank + word_off; +} + +static void imx6_set_otp_timing(void) +{ + unsigned long clk_rate = 0; + unsigned long strobe_read, relex, strobe_prog; + u32 timing = 0; + + clk_rate = clk_get_rate(otp_clk); + + /* do optimization for too many zeros */ + relex = clk_rate / (1000000000 / DEF_RELAX) - 1; + strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; + strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; + + timing = BF(relex, OCOTP_TIMING_RELAX); + timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); + timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); + + __raw_writel(timing, otp_base + HW_OCOTP_TIMING); +} + +static void imx7_set_otp_timing(void) +{ + unsigned long clk_rate; + u32 fsource, prog; + u32 timing = 0; + u32 reg; + + clk_rate = clk_get_rate(otp_clk); + + fsource = DIV_ROUND_UP((clk_rate / 1000) * BV_TIMING_FSOURCE_NS, + 1000000) + 1; + prog = DIV_ROUND_CLOSEST(clk_rate * BV_TIMING_PROG_US, 1000000) + 1; + timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); + reg = __raw_readl(otp_base + HW_OCOTP_TIMING); + reg &= ~(BM_TIMING_FSOURCE | BM_TIMING_PROG); + reg |= timing; + __raw_writel(reg, otp_base + HW_OCOTP_TIMING); +} + +static void imx7ulp_set_otp_timing(void) +{ + /* No need to setup timing for ULP */ +} + +static struct fsl_otp_devtype_data imx6q_data = { + .devtype = FSL_OTP_MX6Q, + .bank_desc = (const char **)imx6q_otp_desc, + .fuse_nums = 16 * 8, + .set_otp_timing = imx6_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx6sl_data = { + .devtype = FSL_OTP_MX6SL, + .bank_desc = (const char **)imx6sl_otp_desc, + .fuse_nums = 8 * 8, + .set_otp_timing = imx6_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx6sll_data = { + .devtype = FSL_OTP_MX6SLL, + .bank_desc = (const char **)imx6sll_otp_desc, + /* Bank 7 and Bank 8 are 4 words each */ + .fuse_nums = 8 * 8, + .set_otp_timing = imx6_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx6ul_data = { + .devtype = FSL_OTP_MX6UL, + .bank_desc = (const char **)imx6ul_otp_desc, + .fuse_nums = 16 * 8, + .set_otp_timing = imx6_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx6ull_data = { + .devtype = FSL_OTP_MX6ULL, + .bank_desc = (const char **)imx6ull_otp_desc, + /* Bank 7 and Bank 8 are 4 words each */ + .fuse_nums = 8 * 8, + .set_otp_timing = imx6_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx7d_data = { + .devtype = FSL_OTP_MX7D, + .bank_desc = (const char **)imx7d_otp_desc, + .fuse_nums = 16 * 4, + .set_otp_timing = imx7_set_otp_timing, +}; + +static struct fsl_otp_devtype_data imx7ulp_data = { + .devtype = FSL_OTP_MX7ULP, + .bank_desc = (const char **)imx7ulp_otp_desc, + .fuse_nums = 31 * 8, + .set_otp_timing = imx7ulp_set_otp_timing, +}; + +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(otp_base + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + + if (count < 0) + return -ETIMEDOUT; + + return 0; +} + +static ssize_t fsl_otp_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + unsigned int index = attr - otp_kattr; + unsigned int phy_index; + u32 value = 0; + int ret; + + if (!fsl_otp) + return -ENODEV; + + ret = clk_prepare_enable(otp_clk); + if (ret) + return -ENODEV; + + mutex_lock(&otp_mutex); + + phy_index = fsl_otp_word_physical(fsl_otp, index); + fsl_otp->set_otp_timing(); + ret = otp_wait_busy(0); + if (ret) + goto out; + + if (fsl_otp->devtype == FSL_OTP_MX7ULP) { + value = __raw_readl(otp_base + HW_OCOTP_OUT_STATUS_ULP); + if (value & BM_OUT_STATUS_DED_ULP) { + __raw_writel(BM_OUT_STATUS_DED_ULP, otp_base + HW_OCOTP_OUT_STATUS_CLR_ULP); + goto out; + } + } + + value = __raw_readl(otp_base + HW_OCOTP_CUST_N(phy_index)); + + if (fsl_otp->devtype == FSL_OTP_MX7ULP) { + __raw_writel(1, otp_base + HW_OCOTP_PDN_ULP); + } + +out: + mutex_unlock(&otp_mutex); + clk_disable_unprepare(otp_clk); + return ret ? 0 : sprintf(buf, "0x%x\n", value); +} + +static int imx6_otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(otp_base + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(addr, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, otp_base + HW_OCOTP_CTRL); + + /* init the data register */ + __raw_writel(data, otp_base + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + + return 0; +} + +static int imx7ulp_otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(otp_base + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR_MX7ULP; + c |= BF(addr, OCOTP_CTRL_ADDR_MX7ULP); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, otp_base + HW_OCOTP_CTRL); + + /* init the data register */ + __raw_writel(data, otp_base + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + + return 0; +} + +static int imx7_otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(otp_base + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR_MX7D; + /* convert to bank address */ + c |= BF((addr >> 2), OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, otp_base + HW_OCOTP_CTRL); + + /* init the data register */ + switch (addr & 0x3) { + case 0: + __raw_writel(0, otp_base + HW_OCOTP_DATA1_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA2_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA3_MX7D); + __raw_writel(data, otp_base + HW_OCOTP_DATA0_MX7D); + break; + case 1: + __raw_writel(data, otp_base + HW_OCOTP_DATA1_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA2_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA3_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA0_MX7D); + break; + case 2: + __raw_writel(0, otp_base + HW_OCOTP_DATA1_MX7D); + __raw_writel(data, otp_base + HW_OCOTP_DATA2_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA3_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA0_MX7D); + break; + case 3: + __raw_writel(0, otp_base + HW_OCOTP_DATA1_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA2_MX7D); + __raw_writel(data, otp_base + HW_OCOTP_DATA3_MX7D); + __raw_writel(0, otp_base + HW_OCOTP_DATA0_MX7D); + break; + } + __raw_writel(data, otp_base + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + + return 0; + +} + +static ssize_t fsl_otp_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int index = attr - otp_kattr; + unsigned int phy_index; + unsigned long value; + unsigned long tmp; + int ret; + + if (!fsl_otp) + return -ENODEV; + + ret = kstrtoul(buf, 16, &value); + if (ret < 0) + return -EINVAL; + + ret = clk_prepare_enable(otp_clk); + if (ret) + return -ENODEV; + + mutex_lock(&otp_mutex); + + phy_index = fsl_otp_word_physical(fsl_otp, index); + if ((fsl_otp->devtype == FSL_OTP_MX7ULP) && (phy_index > 15)) { + fsl_otp->set_otp_timing(); + ret = otp_wait_busy(0); + if (ret) + goto out; + + tmp = __raw_readl(otp_base + HW_OCOTP_OUT_STATUS_ULP); + if (tmp & BM_OUT_STATUS_DED_ULP) { + __raw_writel(BM_OUT_STATUS_DED_ULP, otp_base + HW_OCOTP_OUT_STATUS_CLR_ULP); + goto out; + } + + tmp = __raw_readl(otp_base + HW_OCOTP_CUST_N(phy_index)); + + __raw_writel(1, otp_base + HW_OCOTP_PDN_ULP); + + if (tmp != 0) { + ret = -EPERM; + goto out; + } + } + + fsl_otp->set_otp_timing(); + ret = otp_wait_busy(0); + if (ret) + goto out; + + if (fsl_otp->devtype == FSL_OTP_MX7D) + imx7_otp_write_bits(index, value, 0x3e77); + else if (fsl_otp->devtype == FSL_OTP_MX7ULP) + imx7ulp_otp_write_bits(index, value, 0x3e77); + else + imx6_otp_write_bits(index, value, 0x3e77); + + if (fsl_otp->devtype == FSL_OTP_MX7ULP) { + value = __raw_readl(otp_base + HW_OCOTP_OUT_STATUS_ULP); + if (value & (BM_OUT_STATUS_LOCKED | BM_OUT_STATUS_PROGFAIL)) + printk("ulp prog fail\n"); + + otp_wait_busy(0); + } + + /* Reload all the shadow registers */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + otp_base + HW_OCOTP_CTRL_SET); + udelay(1); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + + if (fsl_otp->devtype == FSL_OTP_MX7ULP) { + __raw_writel(1, otp_base + HW_OCOTP_PDN_ULP); + } + +out: + mutex_unlock(&otp_mutex); + clk_disable_unprepare(otp_clk); + return ret ? ret : count; +} + +static const struct of_device_id fsl_otp_dt_ids[] = { + { .compatible = "fsl,imx6q-ocotp", .data = (void *)&imx6q_data, }, + { .compatible = "fsl,imx6sl-ocotp", .data = (void *)&imx6sl_data, }, + { .compatible = "fsl,imx6sll-ocotp", .data = (void *)&imx6sll_data, }, + { .compatible = "fsl,imx6ul-ocotp", .data = (void *)&imx6ul_data, }, + { .compatible = "fsl,imx6ull-ocotp", .data = (void *)&imx6ull_data, }, + { .compatible = "fsl,imx7d-ocotp", .data = (void *)&imx7d_data, }, + { .compatible = "fsl,imx7ulp-ocotp", .data = (void *)&imx7ulp_data, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_otp_dt_ids); + +static int fsl_otp_probe(struct platform_device *pdev) +{ + struct resource *res; + struct attribute **attrs; + const char **desc; + int i, num; + int ret; + const struct of_device_id *of_id = + of_match_device(fsl_otp_dt_ids, &pdev->dev); + + fsl_otp = (struct fsl_otp_devtype_data *)of_id->data; + if (!fsl_otp) { + dev_err(&pdev->dev, "No driver data provided!\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + otp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(otp_base)) { + ret = PTR_ERR(otp_base); + dev_err(&pdev->dev, "failed to ioremap resource: %d\n", ret); + return ret; + } + + otp_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(otp_clk)) { + ret = PTR_ERR(otp_clk); + dev_err(&pdev->dev, "failed to get clock: %d\n", ret); + return ret; + } + + desc = fsl_otp->bank_desc; + num = fsl_otp->fuse_nums; + + /* The last one is NULL, which is used to detect the end */ + attrs = devm_kzalloc(&pdev->dev, (num + 1) * sizeof(*attrs), + GFP_KERNEL); + otp_kattr = devm_kzalloc(&pdev->dev, num * sizeof(*otp_kattr), + GFP_KERNEL); + otp_attr_group = devm_kzalloc(&pdev->dev, sizeof(*otp_attr_group), + GFP_KERNEL); + if (!attrs || !otp_kattr || !otp_attr_group) + return -ENOMEM; + + for (i = 0; i < num; i++) { + sysfs_attr_init(&otp_kattr[i].attr); + otp_kattr[i].attr.name = desc[i]; + otp_kattr[i].attr.mode = SYSFS_MODE; + otp_kattr[i].show = fsl_otp_show; + otp_kattr[i].store = fsl_otp_store; + attrs[i] = &otp_kattr[i].attr; + } + otp_attr_group->attrs = attrs; + + otp_kobj = kobject_create_and_add("fsl_otp", NULL); + if (!otp_kobj) { + dev_err(&pdev->dev, "failed to add kobject\n"); + return -ENOMEM; + } + + ret = sysfs_create_group(otp_kobj, otp_attr_group); + if (ret) { + dev_err(&pdev->dev, "failed to create sysfs group: %d\n", ret); + kobject_put(otp_kobj); + return ret; + } + + mutex_init(&otp_mutex); + + return 0; +} + +static int fsl_otp_remove(struct platform_device *pdev) +{ + sysfs_remove_group(otp_kobj, otp_attr_group); + kobject_put(otp_kobj); + + return 0; +} + +static struct platform_driver fsl_otp_driver = { + .driver = { + .name = "imx-ocotp", + .owner = THIS_MODULE, + .of_match_table = fsl_otp_dt_ids, + }, + .probe = fsl_otp_probe, + .remove = fsl_otp_remove, +}; +module_platform_driver(fsl_otp_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huang Shijie "); +MODULE_DESCRIPTION("Freescale i.MX OCOTP driver"); diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 200dab5136a7f9..7969d2f36a14f3 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -255,6 +255,18 @@ config HW_RANDOM_MXC_RNGA If unsure, say Y. +config HW_RANDOM_IMX_RNG + tristate "Freescale RNG B/C Random Number Generator" + depends on HW_RANDOM && ARCH_MXC && HAVE_IMX_RNG + ---help--- + This driver provides kernel-side support for the Random Number + Generator (RNGBB and RNGC) hardware found on Freescale i.MX processors. + + To compile this driver as a module, choose M here: the + module will be called fsl-rngc. + + If unsure, say Y. + config HW_RANDOM_NOMADIK tristate "ST-Ericsson Nomadik Random Number Generator support" depends on ARCH_NOMADIK diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index 5f52b1e4e7bed9..d9d76206788e62 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o +obj-$(CONFIG_HW_RANDOM_IMX_RNG) += imx-rng.o obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o diff --git a/drivers/char/hw_random/imx-rng.c b/drivers/char/hw_random/imx-rng.c new file mode 100644 index 00000000000000..df9c13f7d32563 --- /dev/null +++ b/drivers/char/hw_random/imx-rng.c @@ -0,0 +1,440 @@ +/* + * RNG driver for Freescale RNG B/C + * + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) + * (c) Copyright 2003 Red Hat Inc + * + * derived from + * + * Hardware driver for the AMD 768 Random Number Generator (RNG) + * (c) Copyright 2001 Red Hat Inc + * + * derived from + * + * Hardware driver for Intel i810 Random Number Generator (RNG) + * Copyright 2000,2001 Jeff Garzik + * Copyright 2000,2001 Philipp Rumpf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MODULE_NAME "imx-rng" + +#define RNGC_VERSION_MAJOR3 3 + +#define RNGC_VERSION_ID 0x0000 +#define RNGC_COMMAND 0x0004 +#define RNGC_CONTROL 0x0008 +#define RNGC_STATUS 0x000C +#define RNGC_ERROR 0x0010 +#define RNGC_FIFO 0x0014 +#define RNGC_VERIF_CTRL 0x0020 +#define RNGC_OSC_CTRL_COUNT 0x0028 +#define RNGC_OSC_COUNT 0x002C +#define RNGC_OSC_COUNT_STATUS 0x0030 + +#define RNGC_VERID_ZEROS_MASK 0x0f000000 +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000 +#define RNGC_VERID_RNG_TYPE_SHIFT 28 +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000 +#define RNGC_VERID_CHIP_VERSION_SHIFT 16 +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00 +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8 +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff +#define RNGC_VERID_VERSION_MINOR_SHIFT 0 + +#define RNGC_CMD_ZEROS_MASK 0xffffff8c +#define RNGC_CMD_SW_RST 0x00000040 +#define RNGC_CMD_CLR_ERR 0x00000020 +#define RNGC_CMD_CLR_INT 0x00000010 +#define RNGC_CMD_SEED 0x00000002 +#define RNGC_CMD_SELF_TEST 0x00000001 + +#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c +#define RNGC_CTRL_CTL_ACC 0x00000200 +#define RNGC_CTRL_VERIF_MODE 0x00000100 +#define RNGC_CTRL_MASK_ERROR 0x00000040 + +#define RNGC_CTRL_MASK_DONE 0x00000020 +#define RNGC_CTRL_AUTO_SEED 0x00000010 +#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003 +#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0 + +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1 +#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3 + +#define RNGC_STATUS_ST_PF_MASK 0x00c00000 +#define RNGC_STATUS_ST_PF_SHIFT 22 +#define RNGC_STATUS_ST_PF_TRNG 0x00800000 +#define RNGC_STATUS_ST_PF_PRNG 0x00400000 +#define RNGC_STATUS_ERROR 0x00010000 +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000 +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12 +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040 +#define RNGC_STATUS_SEED_DONE 0x00000020 +#define RNGC_STATUS_ST_DONE 0x00000010 +#define RNGC_STATUS_RESEED 0x00000008 +#define RNGC_STATUS_SLEEP 0x00000004 +#define RNGC_STATUS_BUSY 0x00000002 +#define RNGC_STATUS_SEC_STATE 0x00000001 + +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0 +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040 +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020 +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010 +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004 +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002 +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001 + +#define RNG_ADDR_RANGE 0x34 + +static DECLARE_COMPLETION(rng_self_testing); +static DECLARE_COMPLETION(rng_seed_done); + +static struct platform_device *imx_rng_dev; + +struct imx_rng_priv_data { + void __iomem *reg_base; +}; + +int irq_rng; + +static int imx_rng_data_present(struct hwrng *rng, int wait) +{ + int level; + struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv; + + /* how many random numbers are in FIFO? [0-16] */ + level = (readl(prv->reg_base + RNGC_STATUS) & + RNGC_STATUS_FIFO_LEVEL_MASK) >> RNGC_STATUS_FIFO_LEVEL_SHIFT; + + return level > 0 ? 1 : 0; +} + +static int imx_rng_data_read(struct hwrng *rng, u32 *data) +{ + int err; + struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv; + + /* retrieve a random number from FIFO */ + *data = readl(prv->reg_base + RNGC_FIFO); + + /* is there some error while reading this random number? */ + err = readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + + /* if error happened doesn't return random number */ + return err ? 0 : 4; +} + +static irqreturn_t imx_rng_irq(int irq, void *dev) +{ + int handled = 0; + struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)dev; + + /* is the seed creation done? */ + if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) { + complete(&rng_seed_done); + writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + prv->reg_base + RNGC_COMMAND); + handled = 1; + } + + /* is the self test done? */ + if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) { + complete(&rng_self_testing); + writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + prv->reg_base + RNGC_COMMAND); + handled = 1; + } + + /* is there any error? */ + if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR) { + /* clear interrupt */ + writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + prv->reg_base + RNGC_COMMAND); + handled = 1; + } + + return handled; +} + +static int imx_rng_init(struct hwrng *rng) +{ + int err; + struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv; + u32 cmd, ctrl, osc; + + reinit_completion(&rng_self_testing); + reinit_completion(&rng_seed_done); + + err = readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + if (err) { + /* is this a bad keys error ? */ + if (readl(prv->reg_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_BAD_KEY) { + dev_err(&imx_rng_dev->dev, "Can't start, Bad Keys.\n"); + return -EIO; + } + } + + /* mask all interrupts, will be unmasked soon */ + ctrl = readl(prv->reg_base + RNGC_CONTROL); + writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR, + prv->reg_base + RNGC_CONTROL); + + /* verify if oscillator is working */ + osc = readl(prv->reg_base + RNGC_ERROR); + if (osc & RNGC_ERROR_STATUS_OSC_ERR) { + dev_err(&imx_rng_dev->dev, "RNGC Oscillator is dead!\n"); + return -EIO; + } + + err = request_irq(irq_rng, imx_rng_irq, + 0, "imx-rng", (void *)rng->priv); + if (err) { + dev_err(&imx_rng_dev->dev, "Can't get interrupt working.\n"); + return -EIO; + } + + /* do self test, repeat until get success */ + do { + /* clear error */ + cmd = readl(prv->reg_base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_CLR_ERR, prv->reg_base + RNGC_COMMAND); + + /* unmask all interrupt */ + ctrl = readl(prv->reg_base + RNGC_CONTROL); + writel(ctrl & ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR), + prv->reg_base + RNGC_CONTROL); + + /* run self test */ + cmd = readl(prv->reg_base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_SELF_TEST, + prv->reg_base + RNGC_COMMAND); + + wait_for_completion(&rng_self_testing); + + } while (readl(prv->reg_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_ST_ERR); + + /* clear interrupt. Is it really necessary here? */ + writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + prv->reg_base + RNGC_COMMAND); + + /* create seed, repeat while there is some statistical error */ + do { + /* clear error */ + cmd = readl(prv->reg_base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_CLR_ERR, prv->reg_base + RNGC_COMMAND); + + /* seed creation */ + cmd = readl(prv->reg_base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_SEED, prv->reg_base + RNGC_COMMAND); + + wait_for_completion(&rng_seed_done); + + } while (readl(prv->reg_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_STAT_ERR); + + err = readl(prv->reg_base + RNGC_ERROR) & + (RNGC_ERROR_STATUS_STAT_ERR | + RNGC_ERROR_STATUS_RAND_ERR | + RNGC_ERROR_STATUS_FIFO_ERR | + RNGC_ERROR_STATUS_ST_ERR | + RNGC_ERROR_STATUS_OSC_ERR | + RNGC_ERROR_STATUS_LFSR_ERR); + + if (err) { + dev_err(&imx_rng_dev->dev, "iMX RNG appears inoperable.\n"); + return -EIO; + } + + return 0; +} + +static struct hwrng imx_rng = { + .name = "imx-rng", + .init = imx_rng_init, + .data_present = imx_rng_data_present, + .data_read = imx_rng_data_read +}; + +static int __init imx_rng_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk *clk; + struct imx_rng_priv_data *priv; + int err = -ENODEV; + + if (imx_rng_dev) + return -EBUSY; + + /* Enable the clock */ + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + dev_err(dev, "Can not get clock.\n"); + return PTR_ERR(clk); + } + clk_enable(clk); + + /* Allocate private data memory */ + priv = kzalloc(sizeof(struct imx_rng_priv_data), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + imx_rng.priv = (unsigned long)priv; + dev_set_drvdata(dev, priv); + + /* ioremap that register space */ + priv->reg_base = of_iomap(np, 0); + if (!priv->reg_base) { + kfree(priv); + dev_err(dev, "Failed to remap register space.\n"); + return -ENODEV; + } + + irq_rng = platform_get_irq(pdev, 0); + + err = hwrng_register(&imx_rng); + if (err) { + iounmap(priv->reg_base); + kfree(priv); + dev_err(dev, "failed to register hwrng (%d)\n", err); + return err; + } + + imx_rng_dev = pdev; + dev_info(dev, "iMX RNG Registered.\n"); + + return 0; +} + +static int __exit imx_rng_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk *clk; + struct imx_rng_priv_data *priv = dev_get_drvdata(dev); + + /* Disable the clock */ + clk = of_clk_get(np, 0); + + if (IS_ERR(clk)) + dev_err(dev, "Can not get clock.\n"); + else + clk_disable(clk); + + hwrng_unregister(&imx_rng); + + iounmap(priv->reg_base); + + kfree(priv); + + return 0; +} + +static int imx_rng_suspend(struct platform_device *pdev, pm_message_t state) +{ +#ifdef CONFIG_PM + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk *clk = of_clk_get(np, 0); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + return PTR_ERR(clk); + } + + clk_disable(clk); +#endif + + return 0; +} + +static int imx_rng_resume(struct platform_device *pdev) +{ +#ifdef CONFIG_PM + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk *clk = of_clk_get(np, 0); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + return PTR_ERR(clk); + } + + clk_enable(clk); +#endif + + return 0; +} + +static struct of_device_id imx_rng_dt_ids[] = { + { .compatible = "imx-rng",}, + { .compatible = "fsl,imx-rng",}, + { .compatible = "fsl,imx6sl-rng",}, + { }, +}; + +MODULE_DEVICE_TABLE(of, imx_rng_dt_ids); + +static struct platform_driver imx_rng_driver = { + .driver = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = imx_rng_dt_ids, + }, + .remove = __exit_p(imx_rng_remove), + .suspend = imx_rng_suspend, + .resume = imx_rng_resume, +}; + +static int __init mod_init(void) +{ + return platform_driver_probe(&imx_rng_driver, imx_rng_probe); +} + +static void __exit mod_exit(void) +{ + platform_driver_unregister(&imx_rng_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("H/W RNG(B/C) driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/imx_amp/Kconfig b/drivers/char/imx_amp/Kconfig new file mode 100644 index 00000000000000..1f892f8daccbcd --- /dev/null +++ b/drivers/char/imx_amp/Kconfig @@ -0,0 +1,9 @@ +# +# imx mcc +# + +config IMX_SEMA4 + bool "IMX SEMA4 driver" + depends on SOC_IMX6SX + help + Support for IMX SEMA4 driver, most people should say N here. diff --git a/drivers/char/imx_amp/Makefile b/drivers/char/imx_amp/Makefile new file mode 100644 index 00000000000000..4e7a91691b3903 --- /dev/null +++ b/drivers/char/imx_amp/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for imx mcc +# +# +obj-$(CONFIG_IMX_SEMA4) += imx_sema4.o diff --git a/drivers/char/imx_amp/imx_sema4.c b/drivers/char/imx_amp/imx_sema4.c new file mode 100644 index 00000000000000..412202f11cbb2d --- /dev/null +++ b/drivers/char/imx_amp/imx_sema4.c @@ -0,0 +1,413 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct imx_sema4_mutex_device *imx6_sema4; + +/*! + * \brief mutex create function. + * + * This function allocates imx_sema4_mutex structure and returns a handle + * to it. The mutex to be created is identified by SEMA4 device number and mutex + * (gate) number. The handle is used to reference the created mutex in calls to + * other imx_sema4_mutex API functions. This function is to be called only + * once for each mutex. + * + * \param[in] dev_num SEMA4 device (module) number. + * \param[in] mutex_num Mutex (gate) number. + * + * \return NULL (Failure.) + * \return imx_sema4_mutex (Success.) + */ +struct imx_sema4_mutex * +imx_sema4_mutex_create(u32 dev_num, u32 mutex_num) +{ + struct imx_sema4_mutex *mutex_ptr = NULL; + + if (mutex_num >= SEMA4_NUM_GATES || dev_num >= SEMA4_NUM_DEVICES) + goto out; + + if (imx6_sema4->cpine_val & (1 < mutex_num)) { + pr_err("Error: requiring a allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + mutex_ptr = kzalloc(sizeof(*mutex_ptr), GFP_KERNEL); + if (!mutex_ptr) + goto out; + imx6_sema4->mutex_ptr[mutex_num] = mutex_ptr; + imx6_sema4->alloced |= 1 < mutex_num; + imx6_sema4->cpine_val |= idx_sema4[mutex_num]; + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + mutex_ptr->valid = CORE_MUTEX_VALID; + mutex_ptr->gate_num = mutex_num; + init_waitqueue_head(&mutex_ptr->wait_q); + +out: + return mutex_ptr; +} +EXPORT_SYMBOL(imx_sema4_mutex_create); + +/*! + * \brief mutex destroy function. + * + * This function destroys a mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_COMPONENT_DOES_NOT_EXIST (mutex component not installed.) + * \return MQX_INVALID_PARAMETER (Wrong input parameter.) + * \return COREMUTEX_OK (Success.) + * + */ +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + u32 mutex_num; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + mutex_num = mutex_ptr->gate_num; + if ((imx6_sema4->cpine_val & idx_sema4[mutex_num]) == 0) { + pr_err("Error: trying to destroy a un-allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + imx6_sema4->mutex_ptr[mutex_num] = NULL; + imx6_sema4->alloced &= ~(1 << mutex_num); + imx6_sema4->cpine_val &= ~(idx_sema4[mutex_num]); + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + kfree(mutex_ptr); + + return 0; +} +EXPORT_SYMBOL(imx_sema4_mutex_destroy); + +/*! + * \brief Lock the mutex, shouldn't be interruted by INT. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function return -EBUSY, and tell invoker wait until + * it is possible to lock the mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_INVALID_POINTER (Wrong pointer to the mutex structure provided.) + * \return COREMUTEX_OK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int _imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* Check to see if this core already own it */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* return -EBUSY, invoker should be in sleep, and re-lock ag */ + pr_err("%s -> %s %d already locked, wait! num %d val %d.\n", + __FILE__, __func__, __LINE__, + i, mutex_ptr->gate_val); + ret = -EBUSY; + goto out; + } else { + /* try to lock the mutex */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* double check the mutex is locked, otherwise, return -EBUSY */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_debug("wait-locked num %d val %d.\n", + i, mutex_ptr->gate_val); + ret = -EBUSY; + } + } +out: + return ret; +} + +/* ! + * \brief Try to lock the core mutex. + * + * This function attempts to lock a mutex. If the mutex is successfully locked + * for the calling task, SEMA4_A9_LOCK is returned. If the mutex is already + * locked by another task, the function does not block but rather returns + * negative immediately. + * + * \param[in] mutex_ptr Pointer to core_mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * \return negative (mutex not locked.) + * + */ +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + + ret = _imx_sema4_mutex_lock(mutex_ptr); + if (ret == 0) + return SEMA4_A9_LOCK; + else + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_trylock); + +/*! + * \brief Invoke _imx_sema4_mutex_lock to lock the mutex. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function, sleep itself and schedule out. + * Wait until it is possible to lock the mutex. + * + * Invoker should add its own wait queue into the wait queue header of the + * required semaphore, set TASK_INTERRUPTIBLE and sleep on itself by + * schedule() when the lock is failed. Re-try to lock the semaphore when + * it is woke up by the sema4 isr. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&imx6_sema4->lock, flags); + ret = _imx_sema4_mutex_lock(mutex_ptr); + spin_unlock_irqrestore(&imx6_sema4->lock, flags); + while (-EBUSY == ret) { + spin_lock_irqsave(&imx6_sema4->lock, flags); + ret = _imx_sema4_mutex_lock(mutex_ptr); + spin_unlock_irqrestore(&imx6_sema4->lock, flags); + if (ret == 0) + break; + } + + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_lock); + +/*! + * \brief Unlock the mutex. + * + * This function unlocks the specified mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return -EINVAL (Wrong pointer to the mutex structure provided.) + * \return -EINVAL (This mutex has not been locked by this core.) + * \return 0 (mutex successfully unlocked.) + * + * \see imx_sema4_mutex_lock + */ +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_err("%d Trying to unlock an unlock mutex.\n", __LINE__); + ret = -EINVAL; + goto out; + } + /* unlock it */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + writeb(mutex_ptr->gate_val | SEMA4_UNLOCK, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) + pr_err("%d ERROR, failed to unlock the mutex.\n", __LINE__); + +out: + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_unlock); + +/* + * isr used by SEMA4, wake up the sleep tasks if there are the tasks waiting + * for locking semaphore. + * FIXME the bits order of the gatn, cpnie, cpnntf are not exact identified yet! + */ +static irqreturn_t imx_sema4_isr(int irq, void *dev_id) +{ + int i; + struct imx_sema4_mutex *mutex_ptr; + unsigned int mask; + struct imx_sema4_mutex_device *imx6_sema4 = dev_id; + + imx6_sema4->cpntf_val = readw(imx6_sema4->ioaddr + SEMA4_CP0NTF); + for (i = 0; i < SEMA4_NUM_GATES; i++) { + mask = idx_sema4[i]; + if ((imx6_sema4->cpntf_val) & mask) { + mutex_ptr = imx6_sema4->mutex_ptr[i]; + /* + * An interrupt is pending on this mutex, the only way + * to clear it is to lock it (either by this core or + * another). + */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* + * wake up the wait queue, whatever there + * are wait task or not. + * NOTE: check gate is locted or not in + * sema4_lock func by wait task. + */ + mutex_ptr->gate_val = + readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_UNLOCK; + + writeb(mutex_ptr->gate_val, + imx6_sema4->ioaddr + i); + wake_up(&mutex_ptr->wait_q); + } else { + pr_debug("can't lock gate%d %s retry!\n", i, + mutex_ptr->gate_val ? + "locked by m4" : ""); + } + } + } + + return IRQ_HANDLED; +} + +static const struct of_device_id imx_sema4_dt_ids[] = { + { .compatible = "fsl,imx6sx-sema4", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_sema4_dt_ids); + +static int imx_sema4_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + imx6_sema4 = devm_kzalloc(&pdev->dev, sizeof(*imx6_sema4), GFP_KERNEL); + if (!imx6_sema4) + return -ENOMEM; + + imx6_sema4->dev = &pdev->dev; + imx6_sema4->cpine_val = 0; + spin_lock_init(&imx6_sema4->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "unable to get imx sema4 resource 0\n"); + ret = -ENODEV; + goto err; + } + + imx6_sema4->ioaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(imx6_sema4->ioaddr)) { + ret = PTR_ERR(imx6_sema4->ioaddr); + goto err; + } + + imx6_sema4->irq = platform_get_irq(pdev, 0); + if (!imx6_sema4->irq) { + dev_err(&pdev->dev, "failed to get irq\n"); + ret = -ENODEV; + goto err; + } + + ret = devm_request_irq(&pdev->dev, imx6_sema4->irq, imx_sema4_isr, + IRQF_SHARED, "imx6sx-sema4", imx6_sema4); + if (ret) { + dev_err(&pdev->dev, "failed to request imx sema4 irq\n"); + ret = -ENODEV; + goto err; + } + + platform_set_drvdata(pdev, imx6_sema4); + +err: + return ret; +} + +static int imx_sema4_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_sema4_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "imx-sema4", + .of_match_table = imx_sema4_dt_ids, + }, + .probe = imx_sema4_probe, + .remove = imx_sema4_remove, +}; + +static int __init imx_sema4_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_sema4_driver); + if (ret) + pr_err("Unable to initialize sema4 driver\n"); + else + pr_info("imx sema4 driver is registered.\n"); + + return ret; +} + +static void __exit imx_sema4_exit(void) +{ + pr_info("imx sema4 driver is unregistered.\n"); + platform_driver_unregister(&imx_sema4_driver); +} + +module_exit(imx_sema4_exit); +module_init(imx_sema4_init); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IMX SEMA4 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/magdecode.c b/drivers/char/magdecode.c new file mode 100644 index 00000000000000..74d7ddd29a102c --- /dev/null +++ b/drivers/char/magdecode.c @@ -0,0 +1,809 @@ +/* + * Simple Magstripe Reader and Decoder + * + * Driver for a Neuron MCR-370T-1R-xxxx card reader + * ------------------------------------------------ + * This reader accepts a single-track card with a + * 21-character BCD string encoded in the stripe. + * + * When read, the driver will decode and return the + * entire track of the card. Partial swipes, bad + * stripe data, or swipes which take too long will + * cause the driver to return an empty line. The + * driver returns 'F/f' or 'R/r' when the device's + * switches transition: F for front, R for rear, + * upper-case for open, lower-case for closed. + * + * See this blog post for an old description: + * http://boundarydevices.com/magnetic-stripe-driver-for-linux-gpio/ + * + * Author: Ryan Stewart (ryan@boundarydevices.com) + * + * Copyright (C) 2011-2015, Boundary Devices + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INSERT 1 +#define REMOVE 0 + +#define DATASIZE 32 +#define EVENTSIZE 32 +#define MAXREAD 85 +#define DATAMASK (DATASIZE - 1) +#define DATABITMASK (DATASIZE * 8 - 1) +#define EVENTMASK (EVENTSIZE - 1) +#define BITS_PER_CHAR 5 + +static int mag_major; +static dev_t devnum; +static struct class *magdecode_class; + +#define DRIVER_NAME "magdecode" + +struct event { + u8 type; + u8 ptr; /* for data events, holds end of data string */ +}; + +/* + * Device structure, to keep track of everything device-specific here + */ +struct mag_dev { + struct cdev cdev; + struct device *chrdev; + struct platform_device *pdev; + wait_queue_head_t queue; + spinlock_t lock; /* only one IRQ at a time */ + struct timer_list data_timer, front_timer, rear_timer; + int open_count; + + /* + * gpio pin numbers and flags + */ + int front_pin; + int front_pin_close_high; + int rear_pin; + int rear_pin_close_high; + int clock_pin; + int clock_pin_active_high; + int data_pin; + int data_pin_active_high; + char edge; + char last_front; + char last_rear; + int timeout; + + /* + * Event buffer - Records the order of switch open/close events and + * data string completion events, so that we can distinguish between + * insertion and removal. + */ + struct event events[EVENTSIZE]; + u8 e_add; /* Buffer index at which data is to be added */ + u8 e_take; /* Buffer index from which data is to be read */ + + /* + * Data buffer - Records bits in the order that they are read from the + * stripe; bits packed into unsigned chars + */ + u8 data[DATASIZE]; + u8 d_add; /* Bit index at which data is to be added */ + u8 d_take; /* Bit index from which data is to be read */ + u8 d_addprime; /* Bit index of data strings */ + + /* + * the data buffer, and helps us to keep from pushing meaningless data + * events into the event buffer + */ + u8 dd; /* Swipe direction (INSERT or REMOVE) */ + + /* + * Used for sysfs entries + */ + u8 take_start; + u8 take_end; + u8 take_dd; +}; + +static void flush_data(struct mag_dev *dev) +{ + if (dev->d_add != dev->d_addprime) { + int bitcount = (dev->d_add - dev->d_take) & DATABITMASK; + if (bitcount >= 2*BITS_PER_CHAR) { + dev->events[dev->e_add].type = 'd'; + dev->events[dev->e_add].ptr = dev->d_add; + dev->e_add = (dev->e_add + 1) & EVENTMASK; + wake_up(&dev->queue); + } + dev->d_addprime = dev->d_add; + } +} + +static void data_timer(unsigned long arg) +{ + unsigned long flags; + struct mag_dev *dev = (struct mag_dev *)arg; + + spin_lock_irqsave(&dev->lock, flags); + + flush_data(dev); + + spin_unlock_irqrestore(&dev->lock, flags); +} + +static void check_pin(struct mag_dev *dev, + int pin, int active_high) +{ + u8 level, event; + level = (0 != gpio_get_value(pin)) ^ active_high; + + /* Determine which switch it was, and whether it was opened or closed */ + if (pin == dev->front_pin) + dev->last_front = event = 'F' | (level << 5); + else + dev->last_rear = event = 'R' | (level << 5); + + /* Add to event queue */ + dev->events[dev->e_add].type = event; + + /* advance e_add */ + dev->e_add = (dev->e_add + 1) & EVENTMASK; + wake_up(&dev->queue); +} + +static void mag_switch_handler(struct mag_dev *dev, + int pin, int active_high) +{ + check_pin(dev, pin, active_high); +} + +static void front_timer(unsigned long arg) +{ + unsigned long flags; + struct mag_dev *dev = (struct mag_dev *)arg; + + spin_lock_irqsave(&dev->lock, flags); + + mag_switch_handler(dev, dev->front_pin, + dev->front_pin_close_high); + + spin_unlock_irqrestore(&dev->lock, flags); +} + +static irqreturn_t front_switch_handler(int irq, void *dev_id) +{ + struct mag_dev *dev = dev_id; + mod_timer(&dev->front_timer, jiffies + dev->timeout); + return IRQ_HANDLED; +} + +static void rear_timer(unsigned long arg) +{ + unsigned long flags; + struct mag_dev *dev = (struct mag_dev *)arg; + + spin_lock_irqsave(&dev->lock, flags); + + mag_switch_handler(dev, dev->rear_pin, + dev->rear_pin_close_high); + + spin_unlock_irqrestore(&dev->lock, flags); +} + +static irqreturn_t rear_switch_handler(int irq, void *dev_id) +{ + struct mag_dev *dev = dev_id; + mod_timer(&dev->rear_timer, jiffies + dev->timeout); + return IRQ_HANDLED; +} + +static irqreturn_t mag_clock_handler(int irq, void *dev_id) +{ + struct mag_dev *dev = dev_id; + int level = (0 != gpio_get_value(dev->data_pin)); + + /* save data value to buffer */ + if (level ^ dev->data_pin_active_high) + dev->data[dev->d_add / 8] |= 1 << (dev->d_add & 0x07); + else + dev->data[dev->d_add / 8] &= ~(1 << (dev->d_add & 0x07)); + + /* advance d_add */ + dev->d_add = (dev->d_add + 1) & DATABITMASK; + + /* (re)start data_timer */ + mod_timer(&dev->data_timer, jiffies + dev->timeout); + + return IRQ_HANDLED; +} + +static int mag_open(struct inode *inode, struct file *file) +{ + int result; + struct mag_dev *dev; + + dev = container_of(inode->i_cdev, struct mag_dev, cdev); + file->private_data = dev; + + /* Set up on first open */ + if (!dev->open_count) { + /* init wait queue and spinlock */ + init_waitqueue_head(&dev->queue); + spin_lock_init(&dev->lock); + init_timer(&dev->data_timer); + dev->data_timer.function = data_timer; + dev->data_timer.data = (unsigned long) dev; + + init_timer(&dev->front_timer); + dev->front_timer.function = front_timer; + dev->front_timer.data = (unsigned long) dev; + + init_timer(&dev->rear_timer); + dev->rear_timer.function = rear_timer; + dev->rear_timer.data = (unsigned long) dev; + + check_pin(dev, dev->rear_pin, dev->rear_pin_close_high); + check_pin(dev, dev->front_pin, dev->front_pin_close_high); + result = devm_request_irq(&dev->pdev->dev, + gpio_to_irq(dev->front_pin), + front_switch_handler, + IRQ_TYPE_EDGE_BOTH, + "magfront", + file->private_data); + if (result) + goto fail_rirq1; + + result = devm_request_irq(&dev->pdev->dev, + gpio_to_irq(dev->rear_pin), + rear_switch_handler, + IRQ_TYPE_EDGE_BOTH, + "magrear", + file->private_data); + if (result) + goto fail_rirq2; + + result = devm_request_irq(&dev->pdev->dev, + gpio_to_irq(dev->clock_pin), + mag_clock_handler, + dev->clock_pin_active_high + ? IRQ_TYPE_EDGE_RISING + : IRQ_TYPE_EDGE_FALLING, + "magclock", + file->private_data); + if (result) + goto fail_rirq3; + } + + dev->open_count++; + return 0; + +fail_rirq3: + devm_free_irq(&dev->pdev->dev, + gpio_to_irq(dev->rear_pin), file->private_data); +fail_rirq2: + devm_free_irq(&dev->pdev->dev, + gpio_to_irq(dev->front_pin), file->private_data); +fail_rirq1: + return result; +} + +static int mag_release(struct inode *inode, struct file *file) +{ + struct mag_dev *dev = file->private_data; + + dev->open_count--; + + /* Clean up on last close */ + if (!dev->open_count) { + /* IRQ release */ + devm_free_irq(&dev->pdev->dev, + gpio_to_irq(dev->front_pin), dev); + devm_free_irq(&dev->pdev->dev, + gpio_to_irq(dev->rear_pin), dev); + devm_free_irq(&dev->pdev->dev, + gpio_to_irq(dev->clock_pin), dev); + } + + return 0; +} + +static const char lut_bcdp[64] = { + 'X', '0', '8', 'X', '4', 'X', 'X', '<', + '2', 'X', 'X', ':', 'X', '6', '>', 'X', + '1', 'X', 'X', '9', 'X', '5', '=', 'X', + 'X', '3', ';', 'X', '7', 'X', 'X', '?', + 'X', '1', '2', 'X', '4', 'X', 'X', '7', + '8', 'X', 'X', ';', 'X', '=', '>', 'X', + '0', 'X', 'X', '3', 'X', '5', '6', 'X', + 'X', '9', ':', 'X', '<', 'X', 'X', '?', +}; + +/* + * Translate an unaligned 5-bit BCD character + * (4 bits + parity) + */ +static char mag_charat(char *data, int index, char dd) +{ + /* + * The idea is to treat data[] as a continuous ring of bits and + * treat index as a true bit index into that ring, reading a 5-bit + * character that starts at index rather than being forced to pull the + * data out in 8-bit chunks. + */ + + /* We grab the byte at the bit index and the one above it */ + unsigned char thischar, nextchar, result = 0x00; + thischar = data[(index / 8) & DATAMASK]; + nextchar = data[(index / 8 + 1) & DATAMASK]; + + /* first bit in LSB */ + thischar >>= (index & 0x7); + /* above first byte's MSB */ + nextchar <<= 8 - (index & 0x7); + + /* Combine and cut off high 3 bits. This is our 5-bit character. */ + result = (thischar | nextchar) & 0x1F; + + /* Translate using the LUT, and return */ + return lut_bcdp[result | (dd << 5)]; +} + +static int mag_decode(struct mag_dev *dev, char *buf) +{ + char *data = dev->data; + char dd = dev->dd; + int bitcount, scale, bi, starti, endi, i, sc, bc; + + dev->take_end = dev->events[dev->e_take].ptr; + dev->take_start = dev->d_take; + dev->take_dd = dd; + + bitcount = (dev->take_end - dev->take_start) & DATABITMASK; + if (dd == INSERT) { + scale = 1; + bi = dev->d_take; + } else { + scale = -1; + bi = dev->d_take + bitcount - 5; + } + starti = -1; + endi = -1; + i = 0; + sc = 0; + + /* Step through circular buffer looking for valid data */ + for (bc = 0; bc < bitcount && i < MAXREAD; bi += scale, + bc += (dd ? scale : -scale)) { + char c = mag_charat(data, bi, dd); + if (starti >= 0) { + if (c == '?') { + /* end reached, so quit loop */ + buf[i] = '\n'; + endi = bi; + break; + } else if (c == 'X') { + /* + * lookup table returns X on parity error + * if that happens, forget everything and + * start looking for sentinels again + */ + bi = starti; + bc = sc; + scale /= 5; + starti = -1; + i = 0; + continue; + } else { + /* else put this character into the buffer */ + buf[i] = c; + i++; + } + /* + * If we haven't recorded start sentinel position yet, + * check whether character at this bit is start sentinel + */ + } else if (c == ';') { + /* If so, start stepping 5 bits at a time */ + scale *= 5; + /* Save bc and bi in case this is the wrong sentinel */ + sc = bc; + starti = bi; + } + } + + /* Return an empty line on faulty output */ + if (starti < 0 || endi < 0) { + dev_dbg(dev->chrdev, "decode err(%d) dir(%d) at [%d..%d]\n", + i, dev->take_dd, dev->take_start, dev->take_end); + dev_dbg(dev->chrdev, "starti %d, endi %d\n", starti, endi); + i = 0; + buf[i] = '\n'; + } else { + dev_dbg(dev->chrdev, "decode(%d) dir(%d) at [%d..%d]\n", + i, dev->take_dd, dev->take_start, dev->take_end); + } + return i + 1; +} + +static ssize_t mag_read + (struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + ssize_t result; + struct mag_dev *dev = (struct mag_dev *)file->private_data; + + if (dev == NULL) + return -EINVAL; + + if ((dev->e_add == dev->e_take) && !(file->f_flags & O_NONBLOCK)) + wait_event_interruptible(dev->queue, + (dev->e_add != dev->e_take)); + if (dev->e_add != dev->e_take) { + /* read! */ + u8 event = dev->events[dev->e_take].type; + + if (event == 'd') { + char temp[MAXREAD]; + result = mag_decode(dev, temp); + dev->d_take = dev->events[dev->e_take].ptr; + if (result) { + if (copy_to_user(buf, temp, result)) + return -EFAULT; + } + } else { /* switch closure */ + /* determine direction of card swipe */ + char temp[2] = { event, '\n' }; + + if (event == 'F') /* F = front switch closed */ + dev->dd = INSERT; + else if (event == 'f') /* f = front switch open */ + dev->dd = REMOVE; + else if (event == 'R') /* R = rear switch closed */ + dev->dd = INSERT; + else if (event == 'r') /* r = rear switch open */ + dev->dd = REMOVE; + + result = 2; + if (copy_to_user(buf, temp, result)) + return -EFAULT; + } + dev->e_take = (dev->e_take + 1) & EVENTMASK; + + return result; + } else { + return -EINTR; + } +} + +static unsigned int mag_poll(struct file *file, struct poll_table_struct *table) +{ + struct mag_dev *dev = (struct mag_dev *)file->private_data; + if (!dev) + return -EINVAL; + + poll_wait(file, &dev->queue, table); + + if (dev->e_add != dev->e_take) + return POLLIN | POLLRDNORM; + else + return 0; +} + +static struct file_operations const mag_fops = { + .owner = THIS_MODULE, + .read = mag_read, + .poll = mag_poll, + .open = mag_open, + .release = mag_release, +}; + +struct gpio_def { + char const *name; + int *gpio_pin; + int *active_high; +}; + +static ssize_t show_front(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mag_dev *mag = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", + (0 != gpio_get_value(mag->front_pin)) + ^ mag->front_pin_close_high); +} + +static struct kobj_attribute front = +__ATTR(front, 0644, (void *)show_front, NULL); + +static ssize_t show_rear(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mag_dev *mag = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", + (0 != gpio_get_value(mag->rear_pin)) + ^ mag->rear_pin_close_high); +} + +static struct kobj_attribute rear = +__ATTR(rear, 0644, (void *)show_rear, NULL); + +static ssize_t show_last_front(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mag_dev *mag = dev_get_drvdata(dev); + return sprintf(buf, "%c\n", mag->last_front); +} + +static struct kobj_attribute last_front = +__ATTR(last_front, 0644, (void *)show_last_front, NULL); + +static ssize_t show_last_rear(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mag_dev *mag = dev_get_drvdata(dev); + return sprintf(buf, "%c\n", mag->last_rear); +} + +static struct kobj_attribute last_rear = +__ATTR(last_rear, 0644, (void *)show_last_rear, NULL); + +static ssize_t show_raw(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mag_dev *mag = dev_get_drvdata(dev); + int const max = PAGE_SIZE - 20; + int i = 0; + int count; + u8 next = mag->take_start; + buf += sprintf(buf, "%d:%d-%d:", mag->take_dd, mag->take_start, mag->take_end); + count = (mag->take_end - next + DATASIZE) & DATABITMASK; + if (count > max) + count = max; + + for (i=0; i < count; i++) { + char bit = (0 != (mag->data[next/8] & (1 << (next&7)))); + *buf++ = '0' + bit; + next = (next + 1) & DATABITMASK; + } + *buf = '\n'; + return i+1; +} + +static struct kobj_attribute raw = +__ATTR(raw, 0644, (void *)show_raw, NULL); + +static struct attribute *mag_attrs[] = { + &front.attr, + &rear.attr, + &last_front.attr, + &last_rear.attr, + &raw.attr, + NULL, +}; + +static struct attribute_group mag_attr_grp = { + .attrs = mag_attrs, +}; + +static int mag_of_probe(struct platform_device *pdev, + struct device_node *np, + struct mag_dev *dev) +{ + int i; + struct gpio_def pins[] = { + { "front_pin", + &dev->front_pin, + &dev->front_pin_close_high } + , { "rear_pin", + &dev->rear_pin, + &dev->rear_pin_close_high} + , { "clock_pin", + &dev->clock_pin, + &dev->clock_pin_active_high} + , { "data_pin", + &dev->data_pin, + &dev->data_pin_active_high} + }; + for (i = 0; i < ARRAY_SIZE(pins); i++) + *pins[i].gpio_pin = -1; + + for (i = 0; i < ARRAY_SIZE(pins); i++) { + int rv; + enum of_gpio_flags gpio_flags; + int pin = of_get_named_gpio_flags(np, pins[i].name, + 0, &gpio_flags); + if (!gpio_is_valid(pin)) { + dev_err(&pdev->dev, "Invalid %s\n", pins[i].name); + break; + } + *pins[i].gpio_pin = pin; + *pins[i].active_high = !(gpio_flags & OF_GPIO_ACTIVE_LOW); + rv = devm_gpio_request(&pdev->dev, pin, pins[i].name); + if (rv) { + dev_err(&pdev->dev, "Error %d requesting pin %d:%s\n", + rv, pin, pins[i].name); + break; + } + } + if (i < ARRAY_SIZE(pins)) { + while (0 <= i) { + devm_gpio_free(&pdev->dev, *pins[i].gpio_pin); + *pins[i].gpio_pin = -1; + i--; + } + } + + return (i == ARRAY_SIZE(pins)) ? 0 : -EINVAL; +} + +static int mag_probe(struct platform_device *pdev) +{ + int result = 0; + struct mag_dev *dev; + struct device_node *np = pdev->dev.of_node; + + if (!np) + return -ENODEV; + + dev = devm_kzalloc(&pdev->dev, sizeof(struct mag_dev), GFP_KERNEL); + if (!dev) { + dev_err(&pdev->dev, "%s: alloc failure", DRIVER_NAME); + result = -ENOMEM; + goto fail_entry; + } + + dev->pdev = pdev; + dev->timeout = 10; + cdev_init(&dev->cdev, &mag_fops); + dev->cdev.owner = THIS_MODULE; + dev->cdev.ops = &mag_fops; + + if (0 != mag_of_probe(pdev, np, dev)) { + dev_err(&pdev->dev, "Invalid dt spec\n"); + result = -ENODEV; + goto fail_cdevadd; + } + + result = cdev_add(&dev->cdev, devnum, 1); + if (result < 0) { + dev_err(&pdev->dev, "%s: couldn't add device: err %d\n", + DRIVER_NAME, result); + goto fail_cdevadd; + } + + dev->chrdev = device_create(magdecode_class, &platform_bus, + devnum, 0, "%s", DRIVER_NAME); + platform_set_drvdata(pdev, dev); + + result = sysfs_create_group(&pdev->dev.kobj, &mag_attr_grp); + if (result) + dev_err(&pdev->dev, "failed to create sysfs entries"); + + return 0; + +fail_cdevadd: + devm_kfree(&pdev->dev, dev); +fail_entry: + return result; +} + +static int mag_remove(struct platform_device *pdev) +{ + struct mag_dev *dev = platform_get_drvdata(pdev); + if (dev) { + int i; + int pins[] = { + dev->front_pin, + dev->rear_pin, + dev->clock_pin, + dev->data_pin, + }; + + sysfs_remove_group(&pdev->dev.kobj, &mag_attr_grp); + if (!IS_ERR(dev->chrdev)) { + device_destroy(magdecode_class, devnum); + dev->chrdev = 0; + } + for (i = 0; i < ARRAY_SIZE(pins); i++) + if (gpio_is_valid(pins[i])) + devm_gpio_free(&pdev->dev, pins[i]); + } + return 0; +} + +static const struct of_device_id magdecode_ids[] = { + { .compatible = "boundary,magdecode", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, magdecode_ids); + +static struct platform_driver mag_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = magdecode_ids, + }, + .probe = mag_probe, + .remove = mag_remove, +}; + +static char *magdecode_devnode(struct device *dev, umode_t *mode) +{ + if (mode) + *mode = S_IRUGO | S_IWUSR; + return kasprintf(GFP_KERNEL, "%s", DRIVER_NAME); +} + +int __init magdecode_init(void) +{ + int result; + + /* Create a sysfs class. */ + magdecode_class = class_create(THIS_MODULE, "magdecode"); + if (IS_ERR(magdecode_class)) { + result = PTR_ERR(magdecode_class); + goto fail_class; + } + magdecode_class->devnode = magdecode_devnode; + + result = alloc_chrdev_region(&devnum, 0, 1, DRIVER_NAME); + if (result < 0) { + pr_err("%s: couldn't chrdevs: err %d\n", + DRIVER_NAME, result); + goto fail_chrdev; + } + mag_major = MAJOR(devnum); + + result = platform_driver_register(&mag_driver); + if (result < 0) { + pr_err("%s: couldn't register driver, err %d\n", + DRIVER_NAME, result); + goto fail_platform; + } + + pr_info("driver %s registered\n", DRIVER_NAME); + + return 0; + +fail_platform: + unregister_chrdev_region(devnum, 1); + +fail_chrdev: + class_destroy(magdecode_class); + magdecode_class = 0; + +fail_class: + return result; +} + +void __exit magdecode_cleanup(void) +{ + platform_driver_unregister(&mag_driver); + + unregister_chrdev_region(devnum, 1); + + if (!IS_ERR(magdecode_class)) + class_destroy(magdecode_class); + pr_info("%s unloaded\n", DRIVER_NAME); +} + +module_init(magdecode_init); +module_exit(magdecode_cleanup); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/sas.c b/drivers/char/sas.c new file mode 100644 index 00000000000000..7a16562203c5d9 --- /dev/null +++ b/drivers/char/sas.c @@ -0,0 +1,1219 @@ +/* + * sas: a simple 9-bit serial driver suitable for + * us in implementing the Slot Accounting System (SAS) + * protocol. + * + * - The driver exposes character devices /dev/sas0-N, + * which use the 9-bit support of the UARTs on i.MX + * SOCs to implement the framing portion of the protocol. + * + * - Each write() call is translated into a message with + * MARK parity on the first byte and SPACE parity for the + * remaining bytes of the message. + * + * Received data is parsed according to the same protocol, + * such that a "message" is defined as a set of incoming + * data that starts with a byte with MARK parity and + * terminates when either a timeout occurs or another + * byte with MARK parity is received + * + * - Each read() call returns zero or one complete + * messages. + * + * - Improperly framed incoming messages are reported + * through printk but are not returned to userspace. + * e.g. if a timeout occurs to terminate a message and + * is followed by data with SPACE parity, the characters + * will be dropped. + * + * The driver supports poll(). + * + * POLLIN is signalled when a complete message is available. + * + * POLLOUT is signalled when space for a maximum sized message + * is available (device tree maxtxmsg). + * + * Copyright (C) 2015, Boundary Devices + */ + +#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register definitions */ +#define URXD0 0x0 /* Receiver Register */ +#define URTX0 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define IMX21_ONEMS 0xb0 /* One Millisecond register */ +#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ +#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ +#define UMCR_MDEN 1 /* 9-bit/Multidrop enable */ +#define UMCR_TXB8 (1<<2) /* parity bit goes here */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto detect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ +#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_ATEN (1<<3) /* Aging Timer Enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ +#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +static int sas_major; +static dev_t devnum; +static struct class *sas_class; + +#define DRIVER_NAME "sas" + +#define MS_TO_NS(msec) ((msec) * 1000 * 1000) + +#ifndef CONFIG_SAS_PARTIAL_RX +static void hrtimer_mod(struct hrtimer *timer, u32 ms) +{ + ktime_t ktime = ktime_set(0, MS_TO_NS(ms)); + hrtimer_try_to_cancel(timer); + hrtimer_start(timer, ktime, HRTIMER_MODE_REL); +} + +struct msg_t { + int start; + int end; +}; +#endif + +struct imx_sas_devdata { + unsigned umcr_reg; +}; + +/* + * Device structure, to keep track of everything device-specific here + */ +struct sas_dev { + struct cdev cdev; + struct device *chrdev; + struct platform_device *pdev; + void __iomem *base; + wait_queue_head_t queue; + spinlock_t lock; /* only one IRQ at a time */ + struct mutex rx_lock; /* only one reader */ + struct mutex tx_lock; /* only one writer */ + int open_count; + + struct clk *clk_ipg; + struct clk *clk_per; + unsigned umcr_reg; + int irq; + int rxirq; + int txirq; + u32 baud; + u32 rxbufsize; + u32 txbufsize; + u32 maxtxmsg; + struct circ_buf rxbuf; +#ifndef CONFIG_SAS_PARTIAL_RX + u32 flush_on_mark; + struct hrtimer timer; + u32 maxrxmsgs; + u32 interbyte_delay; + struct msg_t *rxmsgs; + u32 rxmsgadd; + u32 rxmsgtake; +#endif + struct circ_buf txbuf; + u8 *txpbuf; /* parity for outbound characters */ + u8 last_parity; + u8 force_tx_par_err; +}; + +#define CIRC_NEXT(index, size) ((index + 1) & (size - 1)) +#define CIRC_PREV(index, size) ((index - 1) & (size - 1)) + +#ifndef CONFIG_SAS_PARTIAL_RX +/* end of last messsage added */ +#define PREVMSGEND(dev) (dev->rxmsgs[CIRC_PREV(dev->rxmsgadd, \ + dev->maxrxmsgs)].end) + +/* start of next message */ +#define NEXTMSGSTART(dev) (dev->rxmsgs[dev->rxmsgadd].start) + +//#define DEBUG_READS + +static void flush_msg(struct sas_dev *dev) +{ + if (dev->rxbuf.head != NEXTMSGSTART(dev)) { + int nextmsg = CIRC_NEXT(dev->rxmsgadd, dev->maxrxmsgs); + int end = CIRC_PREV(dev->rxbuf.head, dev->rxbufsize); + if (dev->rxmsgtake != nextmsg) { + dev->rxmsgs[dev->rxmsgadd].end = end; + dev->rxmsgadd = nextmsg; + dev->rxmsgs[nextmsg].start = dev->rxbuf.head; + } else { + /* append to the previous message, but whine */ + dev_err(&dev->pdev->dev, "message overflow\n"); + PREVMSGEND(dev) = end; + } + wake_up(&dev->queue); + } +} + +static enum hrtimer_restart rx_timer(struct hrtimer *timer) +{ + struct sas_dev *dev = container_of(timer, struct sas_dev, timer); + flush_msg(dev); + return HRTIMER_NORESTART; +} +#endif + +static int get_rx_length(struct sas_dev *dev, int *pstart) +{ + int len = 0; + +#ifndef CONFIG_SAS_PARTIAL_RX + if (dev->rxmsgadd != dev->rxmsgtake) { + struct msg_t *msg = dev->rxmsgs + dev->rxmsgtake; + + *pstart = msg->start; + len = (msg->end - msg->start + 1) + & (dev->rxbufsize - 1); + } +#else + len = (dev->rxbuf.head - dev->rxbuf.tail) + & (dev->rxbufsize - 1); + *pstart = dev->rxbuf.tail; +#endif + return len; +} + +static ssize_t sas_read + (struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ +#ifdef DEBUG_READS + unsigned char dbg_buf[4]; + unsigned char *p = dbg_buf; + int rem = 4; + int len; +#endif + struct sas_dev *dev = (struct sas_dev *)file->private_data; + ssize_t numread = 0; + int firstseg; + int start; + int msgleft; + + mutex_lock(&dev->rx_lock); + + msgleft = get_rx_length(dev, &start); + if (msgleft) { + if (msgleft > count) { + numread = -ENOBUFS; + goto out; + } + firstseg = dev->rxbufsize - start; + if (firstseg > msgleft) + firstseg = msgleft; +#ifdef DEBUG_READS + len = firstseg < rem ? firstseg : rem; + memcpy(p, dev->rxbuf.buf+start, len); + p += len; + rem -= len; +#endif + if (copy_to_user(buf, dev->rxbuf.buf+start, firstseg)) { + numread = -EFAULT; + goto out; + } + count = msgleft; + msgleft -= firstseg; + numread = firstseg; + if (0 < msgleft) { + /* wrap: need to copy a second segment */ + buf += firstseg; +#ifdef DEBUG_READS + len = msgleft < rem ? msgleft : rem; + memcpy(p, dev->rxbuf.buf+0, len); + p += len; + rem -= len; +#endif + if (copy_to_user(buf, dev->rxbuf.buf+0, msgleft)) { + numread = -EFAULT; + goto out; + } + dev->rxbuf.tail = msgleft; + numread += msgleft; + } else { + dev->rxbuf.tail = start + firstseg; + } +#ifndef CONFIG_SAS_PARTIAL_RX + dev->rxmsgtake = CIRC_NEXT(dev->rxmsgtake, dev->maxrxmsgs); +#endif + } /* have a message */ +out: + mutex_unlock(&dev->rx_lock); +#ifdef DEBUG_READS + p = dbg_buf; + if (numread >= 4) { + pr_info("%s: %02x %02x %02x %02x\n", __func__, + p[0], p[1], p[2], p[3]); + } else if (numread == 3) { + pr_info("%s: %02x %02x %02x\n", __func__, + p[0], p[1], p[2]); + } else if (numread == 2) { + pr_info("%s: %02x %02x\n", __func__, + p[0], p[1]); + } else if (numread == 1) { + pr_info("%s: %02x\n", __func__, + p[0]); + } else { + pr_info("%s: returning %d\n", __func__, numread); + + } +#endif + return numread; +} + +static ssize_t sas_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + int written = 0; + u32 reg; + struct sas_dev *dev = (struct sas_dev *)file->private_data; + + mutex_lock(&dev->tx_lock); + if (CIRC_SPACE(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize) >= count) { + int start = dev->txbuf.head; + int firstseg = dev->txbufsize - start; + if (firstseg > count) + firstseg = count; + if (copy_from_user(dev->txbuf.buf+start, buf, firstseg)) { + written = -EFAULT; + } else if (count > firstseg) { + /* wrap: copy second segment */ + + int left = count - firstseg; + buf += firstseg; + if (copy_from_user(dev->txbuf.buf, buf, left)) + written = -EFAULT; + } + if (0 == written) { + u32 nextbyte = start / 8; + u32 const pbytemask = (dev->txbufsize / 8) - 1; + u8 mask = 1 << (start & 7); + u8 byteval = dev->txpbuf[start/8] | mask; + mask = ~(mask << 1); + written = 1; + while (--count) { + if ('\xff' == mask) { + dev->txpbuf[nextbyte] = byteval; + nextbyte = (nextbyte + 1) & pbytemask; + byteval = dev->txpbuf[nextbyte]; + mask = (u8)~1; + } + byteval &= mask; + mask = (mask << 1) | 1; + written++; + } + dev->txpbuf[nextbyte] = byteval; + dev->txbuf.head = (dev->txbuf.head + written) + & (dev->txbufsize - 1); + reg = readl(dev->base + UCR1); + if (!(reg & UCR1_TRDYEN)) { + reg = readl(dev->base + UCR4); + if (!(reg & UCR4_TCEN)) { + reg |= UCR4_TCEN; + writel(reg, dev->base + UCR4); + } + } + } + } + + mutex_unlock(&dev->tx_lock); + return written; +} + +static unsigned int sas_poll(struct file *file, struct poll_table_struct *table) +{ + unsigned int flags = 0; + struct sas_dev *dev = (struct sas_dev *)file->private_data; + if (!dev) + return -EINVAL; + + poll_wait(file, &dev->queue, table); + + if (dev->rxbuf.head != dev->rxbuf.tail) + flags |= POLLIN | POLLRDNORM; + if (CIRC_SPACE(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize) >= dev->maxtxmsg) { + flags |= POLLOUT; + } + return flags; +} + +static void sas_rxint(struct sas_dev *dev) +{ + int space = CIRC_SPACE(dev->rxbuf.head, + dev->rxbuf.tail, + dev->rxbufsize); + while (space >= 3) { + u32 in = readl(dev->base + URXD0); + if (!(in & URXD_CHARRDY)) + break; + if (!dev->umcr_reg) { + u32 ch_parity = in; + + ch_parity ^= ch_parity >> 4; + ch_parity ^= ch_parity >> 2; + ch_parity ^= ch_parity >> 1; + ch_parity &= 1; + /* URXD_PRERR is bit 10 */ + in ^= (ch_parity << 10); + } + if (in & URXD_PRERR) { + /* + * if a part of a message is present, terminate it + * and notify userspace + */ +#ifndef CONFIG_SAS_PARTIAL_RX + if (dev->flush_on_mark) + flush_msg(dev); +#endif + dev->rxbuf.buf[dev->rxbuf.head] = 0xff; + dev->rxbuf.head = CIRC_NEXT(dev->rxbuf.head, + dev->rxbufsize); + dev->rxbuf.buf[dev->rxbuf.head] = 0; + dev->rxbuf.head = CIRC_NEXT(dev->rxbuf.head, + dev->rxbufsize); + dev->rxbuf.buf[dev->rxbuf.head] = in; + dev->rxbuf.head = CIRC_NEXT(dev->rxbuf.head, + dev->rxbufsize); + + space -= 3; + } else { + dev->rxbuf.buf[dev->rxbuf.head] = in; + dev->rxbuf.head = CIRC_NEXT(dev->rxbuf.head, + dev->rxbufsize); + space--; + } + +#ifndef CONFIG_SAS_PARTIAL_RX + hrtimer_mod(&dev->timer, dev->interbyte_delay); +#endif + if (!(readl(dev->base + USR2) & USR2_RDR)) + break; + } + if (3 >= space) { + dev_err(&dev->pdev->dev, "overrun"); + while (readl(dev->base + URXD0) & URXD_CHARRDY) + ; + } +#ifdef CONFIG_SAS_PARTIAL_RX + wake_up(&dev->queue); +#endif +} + +static void sas_txint(struct sas_dev *dev) +{ + u32 reg; + while (CIRC_CNT(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize) && + !(readl(dev->base + IMX21_UTS) & UTS_TXFULL)) { + u8 ch = dev->txbuf.buf[dev->txbuf.tail]; + u8 shift = dev->txbuf.tail & 7; + u8 mark_space = (dev->txpbuf[dev->txbuf.tail/8] >> shift) & 1; + u8 change_needed; + + if (dev->umcr_reg) { + change_needed = mark_space ^ dev->last_parity; + } else { + unsigned ch_parity = dev->force_tx_par_err ^ mark_space ^ ch; + ch_parity ^= ch_parity >> 4; + ch_parity ^= ch_parity >> 2; + ch_parity ^= ch_parity >> 1; + change_needed = ch_parity & 1; + } + if (change_needed) { + reg = readl(dev->base + USR2); + if (!(reg & USR2_TXDC)) { + /* + * must wait until tx complete to change force + * parity error status or + * TXB8 status + */ + reg = readl(dev->base + UCR4); + if (!(reg & UCR4_TCEN)) { + reg |= UCR4_TCEN; + writel(reg, dev->base + UCR4); + } + reg = readl(dev->base + UCR1); + writel(reg & ~(UCR1_TXMPTYEN | UCR1_TRDYEN), dev->base + UCR1); + return; + } + if (dev->umcr_reg) { + reg = readl(dev->base + dev->umcr_reg); + if (mark_space) + reg |= UMCR_TXB8; + else + reg &= ~UMCR_TXB8; + writel(reg, dev->base + dev->umcr_reg); + dev->last_parity = mark_space; + } else { + reg = readl(dev->base + IMX21_UTS); + dev->force_tx_par_err ^= 1; + if (dev->force_tx_par_err) + reg |= UTS_FRCPERR; + else + reg &= ~UTS_FRCPERR; + writel(reg, dev->base + IMX21_UTS); + } + } + + writel(ch, dev->base + URTX0); + dev->txbuf.tail = CIRC_NEXT(dev->txbuf.tail, dev->txbufsize); + if (CIRC_SPACE(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize) >= dev->maxtxmsg) + wake_up(&dev->queue); + } + if (!CIRC_CNT(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize)) { + reg = readl(dev->base + UCR1); + if (reg & (UCR1_TRDYEN | UCR1_TXMPTYEN)) { + reg &= ~(UCR1_TRDYEN | UCR1_TXMPTYEN); + writel(reg, dev->base + UCR1); + } + reg = readl(dev->base + UCR4); + if (reg & UCR4_TCEN) { + reg &= ~UCR4_TCEN; + writel(reg, dev->base + UCR4); + } + if (CIRC_CNT(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize)) { + /* Turn interrupt back on */ + reg |= UCR4_TCEN; + writel(reg, dev->base + UCR4); + } + } else { + reg = readl(dev->base + UCR1); + if (!(reg & UCR1_TRDYEN)) { + reg |= UCR1_TRDYEN; + writel(reg, dev->base + UCR1); + } + } +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + struct sas_dev *dev = dev_id; + unsigned int sts; + + sts = readl(dev->base + USR1); + if (sts & USR1_RRDY) + sas_rxint(dev_id); + + if (sts & USR1_TRDY) + sas_txint(dev_id); + + sts = readl(dev->base + USR2); + if (sts & USR2_ORE) + writel(USR2_ORE, dev->base + USR2); + return IRQ_HANDLED; +} + +/* + * We don't want address detection, so force an + * address match by entering loopback and transmitting + * a character with the mark bit set. + */ +static void force_address_match(struct sas_dev *dev) +{ + if (!dev->umcr_reg) + return; + writel(UCR1_UARTEN, dev->base + UCR1); + + /* loopback */ + writel(UTS_LOOP, dev->base + IMX21_UTS); + + /* mark parity */ + writel(UMCR_TXB8 | UMCR_MDEN, dev->base + dev->umcr_reg); + + /* transmit a null */ + writel(0, dev->base + URTX0); + + /* wait for receiver ready */ + usleep_range(1000, 2000); + (void)readl(dev->base + URXD0); + + /* out of loopback */ + writel(0, dev->base + IMX21_UTS); + + /* and space parity */ + writel(UMCR_MDEN, dev->base + dev->umcr_reg); +} + +static int sas_open(struct inode *inode, struct file *file) +{ + int rval = 0; + unsigned long flags; + unsigned cnt; + struct sas_dev *dev = container_of(inode->i_cdev, + struct sas_dev, cdev); + file->private_data = dev; + spin_lock_irqsave(&dev->lock, flags); + cnt = ++dev->open_count; + spin_unlock_irqrestore(&dev->lock, flags); + + if (1 == cnt) { + rval = clk_prepare_enable(dev->clk_per); + if (rval) + goto out; + rval = clk_prepare_enable(dev->clk_ipg); + if (rval) { + clk_disable_unprepare(dev->clk_per); + goto out; + } + writel(0x0, dev->base + UCR1); + writel(0x0, dev->base + UCR2); + + while (!(readl(dev->base + UCR2) & UCR2_SRST)) + ; + + writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP, + dev->base + UCR3); + writel(0x8000, dev->base + UCR4); + writel(0x002b, dev->base + UESC); + writel(0x0, dev->base + UTIM); + writel(0x0, dev->base + IMX1_UTS); + writel(0, dev->base + IMX21_UTS); + dev->force_tx_par_err = 0; + + /* divide input clock by 2, receive fifo 1, txtl 2 */ + writel((4 << 7) | 0x801, dev->base + UFCR); + writel(0xf, dev->base + UBIR); + writel(clk_get_rate(dev->clk_per) / (2 * dev->baud), + dev->base + UBMR); + + if (dev->umcr_reg) { + writel(UMCR_MDEN, dev->base + dev->umcr_reg); + } + writel(UCR2_WS | UCR2_IRTS + | UCR2_RXEN | UCR2_TXEN + | UCR2_SRST | UCR2_PREN, + dev->base + UCR2); + + dev->rxbuf.head = + dev->rxbuf.tail = + dev->txbuf.head = + dev->txbuf.tail = 0; +#ifndef CONFIG_SAS_PARTIAL_RX + dev->rxmsgadd = + dev->rxmsgtake = 0; + dev->rxmsgs[0].start = 0; +#endif + dev->last_parity = 0; + force_address_match(dev); + + rval = devm_request_irq(&dev->pdev->dev, + dev->irq, irq_handler, + IRQF_TRIGGER_PROBE, DRIVER_NAME, dev); + if (!rval) { + writel(UCR1_UARTEN | UCR1_RRDYEN, dev->base + UCR1); + } else { + writel(0x0, dev->base + UCR1); + clk_disable_unprepare(dev->clk_ipg); + clk_disable_unprepare(dev->clk_per); + dev_err(&dev->pdev->dev, + "Error %d requesting irq %d\n", + rval, dev->irq); + --dev->open_count; + } + } +out: + return rval; +} + +static int sas_release(struct inode *inode, struct file *file) +{ + int loop = 0; + unsigned long flags; + struct sas_dev *dev = container_of(inode->i_cdev, + struct sas_dev, cdev); + + while (1) { + int cnt = CIRC_CNT(dev->txbuf.head, + dev->txbuf.tail, + dev->txbufsize); + if (!cnt) + break; + if (loop++ > 10) + break; + msleep(100); + } + spin_lock_irqsave(&dev->lock, flags); + if (0 == --dev->open_count) { + writel(0x0, dev->base + UCR1); + writel(0x0, dev->base + UCR2); + devm_free_irq(&dev->pdev->dev, dev->irq, dev); + clk_disable_unprepare(dev->clk_ipg); + clk_disable_unprepare(dev->clk_per); + } + + spin_unlock_irqrestore(&dev->lock, flags); + return -1; +} + +static struct file_operations const sas_fops = { + .owner = THIS_MODULE, + .read = sas_read, + .write = sas_write, + .poll = sas_poll, + .open = sas_open, + .release = sas_release, +}; + +static ssize_t show_rxhead(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", sas ? sas->rxbuf.head : -1); +} + +static struct kobj_attribute rxhead = +__ATTR(rxhead, 0644, (void *)show_rxhead, NULL); + +static ssize_t show_rxtail(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", sas ? sas->rxbuf.tail : -1); +} + +static struct kobj_attribute rxtail = +__ATTR(rxtail, 0644, (void *)show_rxtail, NULL); + +static ssize_t show_txhead(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", sas ? sas->txbuf.head : -1); +} + +static struct kobj_attribute txhead = +__ATTR(txhead, 0644, (void *)show_txhead, NULL); + +static ssize_t show_txtail(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", sas ? sas->txbuf.tail : -1); +} + +static struct kobj_attribute txtail = +__ATTR(txtail, 0644, (void *)show_txtail, NULL); + +#ifndef CONFIG_SAS_PARTIAL_RX +static ssize_t show_ibdelay(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", sas ? sas->interbyte_delay : -1); +} + +static ssize_t store_ibdelay(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + u32 val; + struct sas_dev *sas = dev_get_drvdata(dev); + if (1 == sscanf(buf, "%u", &val)) { + if (sas) { + sas->interbyte_delay = val; + return count; + } else { + return -ENODEV; + } + } else { + return -EINVAL; + } +} + +static struct kobj_attribute ibdelay = +__ATTR(ibdelay, 0644, (void *)show_ibdelay, (void *)store_ibdelay); + +static ssize_t show_rxmsgadd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d: [%d:%d]\n", + sas ? sas->rxmsgadd : -1, + sas ? sas->rxmsgs[sas->rxmsgadd].start : -1, + sas ? sas->rxmsgs[sas->rxmsgadd].end : -1); +} + +static struct kobj_attribute rxmsgadd = +__ATTR(rxmsgadd, 0644, (void *)show_rxmsgadd, NULL); + +static ssize_t show_rxmsgtake(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sas_dev *sas = dev_get_drvdata(dev); + return sprintf(buf, "%d: [%d:%d]\n", + sas ? sas->rxmsgtake : -1, + sas ? sas->rxmsgs[sas->rxmsgtake].start : -1, + sas ? sas->rxmsgs[sas->rxmsgtake].end : -1); +} + +static struct kobj_attribute rxmsgtake = +__ATTR(rxmsgtake, 0644, (void *)show_rxmsgtake, NULL); +#endif + +static struct attribute *sas_attrs[] = { + &rxhead.attr, + &rxtail.attr, + &txhead.attr, + &txtail.attr, +#ifndef CONFIG_SAS_PARTIAL_RX + &ibdelay.attr, + &rxmsgadd.attr, + &rxmsgtake.attr, +#endif + NULL, +}; + +static struct attribute_group sas_attr_grp = { + .attrs = sas_attrs, +}; + +static int sas_of_probe(struct platform_device *pdev, + struct device_node *np, + struct sas_dev *dev) +{ + dev->irq = irq_of_parse_and_map(np, 0); + if (of_property_read_u32(np, "baud", &dev->baud)) + return -EINVAL; + if (of_property_read_u32(np, "rxbufsize", &dev->rxbufsize)) + return -EINVAL; +#ifndef CONFIG_SAS_PARTIAL_RX + if (of_property_read_u32(np, "interbyte_delay", &dev->interbyte_delay)) + return -EINVAL; + if (of_property_read_u32(np, "flush_on_mark", &dev->flush_on_mark)) + return -EINVAL; + dev->maxrxmsgs = dev->rxbufsize / 4; +#endif + if ((dev->rxbufsize < 4) || + (dev->rxbufsize & (dev->rxbufsize-1))) { + dev_err(&pdev->dev, + "rxbufsize %u must be a non-zero power of 2\n", + dev->rxbufsize); + } + if (of_property_read_u32(np, "txbufsize", &dev->txbufsize)) + return -EINVAL; + if (of_property_read_u32(np, "maxtxmsg", &dev->maxtxmsg)) + return -EINVAL; + /* force power of two for transmit and receive buffers */ + if ((dev->rxbufsize & (dev->rxbufsize-1)) || + (dev->rxbufsize == 0) || + (dev->txbufsize & (dev->txbufsize-1)) || + (dev->txbufsize == 0)) { + dev_err(&pdev->dev, + "rx/txbufsize must be a non-zero power of 2\n"); + return -EINVAL; + } + return 0; +} + +static struct imx_sas_devdata imx51_sas_data = { + .umcr_reg = 0, +}; + +static struct imx_sas_devdata imx6_sas_data = { + .umcr_reg = 0xb8, +}; + +static const struct of_device_id sas_ids[] = { + { .compatible = "boundary,imx51-sas", .data = &imx51_sas_data, }, + { .compatible = "boundary,sas", .data = &imx6_sas_data }, + { /* sentinel */ } +}; + +static int sas_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = of_match_device(sas_ids, &pdev->dev); + int result = 0; + struct sas_dev *dev; + struct device_node *np = pdev->dev.of_node; + void __iomem *base; + struct resource *res; + + if (!np) + return -ENODEV; + + dev = devm_kzalloc(&pdev->dev, sizeof(struct sas_dev), GFP_KERNEL); + if (!dev) { + dev_err(&pdev->dev, "%s: alloc failure", DRIVER_NAME); + result = -ENOMEM; + goto fail_entry; + } + + dev->pdev = pdev; + cdev_init(&dev->cdev, &sas_fops); + dev->cdev.owner = THIS_MODULE; + dev->cdev.ops = &sas_fops; + + if (of_id) { + const struct imx_sas_devdata *pdata = of_id->data; + + if (pdata) + dev->umcr_reg = pdata->umcr_reg; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "%s: IORESOURCE_MEM", DRIVER_NAME); + result = -ENODEV; + goto fail_entry; + } + + base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE); + if (!base) { + dev_err(&pdev->dev, "%s: ioremap", DRIVER_NAME); + result = -ENOMEM; + goto fail_entry; + } + dev->base = base; + + dev->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); + if (IS_ERR(dev->clk_ipg)) { + result = PTR_ERR(dev->clk_ipg); + dev_err(&pdev->dev, "failed to get ipg clk: %d\n", result); + return result; + } + + dev->clk_per = devm_clk_get(&pdev->dev, "per"); + if (IS_ERR(dev->clk_per)) { + result = PTR_ERR(dev->clk_per); + dev_err(&pdev->dev, "failed to get per clk: %d\n", result); + return result; + } + + if (0 != sas_of_probe(pdev, np, dev)) { + dev_err(&pdev->dev, "Invalid dt spec\n"); + result = -ENODEV; + goto fail_entry; + } + + dev->rxbuf.buf = devm_kzalloc(&pdev->dev, dev->rxbufsize, GFP_KERNEL); + if (!dev->rxbuf.buf) { + dev_err(&pdev->dev, "%s: allocating rxbuf(%d)", + DRIVER_NAME, dev->rxbufsize); + goto fail_entry; + } + +#ifndef CONFIG_SAS_PARTIAL_RX + dev->rxmsgs = devm_kzalloc(&pdev->dev, + dev->maxrxmsgs * sizeof(dev->rxmsgs[0]), + GFP_KERNEL); + if (!dev->rxmsgs) { + dev_err(&pdev->dev, "%s: allocating rxmsgs(%d)", + DRIVER_NAME, dev->maxrxmsgs); + goto fail_entry; + } +#endif + dev->txbuf.buf = devm_kzalloc(&pdev->dev, dev->txbufsize, GFP_KERNEL); + if (!dev->txbuf.buf) { + dev_err(&pdev->dev, "%s: allocating txbuf(%d)", + DRIVER_NAME, dev->txbufsize); + goto fail_entry; + } + + dev->txpbuf = devm_kzalloc(&pdev->dev, + (dev->txbufsize+7)/8, + GFP_KERNEL); + if (!dev->txpbuf) { + dev_err(&pdev->dev, "%s: allocating txbuf(%d)", DRIVER_NAME, + (dev->txbufsize+7)/8); + goto fail_entry; + } + + mutex_init(&dev->rx_lock); + mutex_init(&dev->tx_lock); + + init_waitqueue_head(&dev->queue); + +#ifndef CONFIG_SAS_PARTIAL_RX + hrtimer_init(&dev->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + dev->timer.function = rx_timer; +#endif + + result = cdev_add(&dev->cdev, devnum, 1); + if (result < 0) { + dev_err(&pdev->dev, "%s: couldn't add device: err %d\n", + DRIVER_NAME, result); + goto fail_cdevadd; + } + + result = sysfs_create_group(&pdev->dev.kobj, &sas_attr_grp); + if (result) { + pr_err("failed to create sysfs entries"); + goto fail_cdevadd; + } + + spin_lock_init(&dev->lock); + + dev->chrdev = device_create(sas_class, &platform_bus, + devnum, NULL, "%s", DRIVER_NAME); + platform_set_drvdata(pdev, dev); + + dev_dbg(&pdev->dev, "%s: uart_clk == %ld\n", + DRIVER_NAME, clk_get_rate(dev->clk_per)); + dev_dbg(&pdev->dev, "%s: ipg_clk == %ld\n", + DRIVER_NAME, clk_get_rate(dev->clk_per)); + dev_dbg(&pdev->dev, "%s: irq == %d\n", + DRIVER_NAME, dev->irq); + dev_dbg(&pdev->dev, "%s: rxirq == %d\n", + DRIVER_NAME, dev->rxirq); + dev_dbg(&pdev->dev, "%s: txirq == %d\n", + DRIVER_NAME, dev->txirq); + dev_dbg(&pdev->dev, "%s: baud == %u\n", + DRIVER_NAME, dev->baud); +#ifndef CONFIG_SAS_PARTIAL_RX + dev_dbg(&pdev->dev, "%s: ib_delay == %u ms\n", + DRIVER_NAME, dev->interbyte_delay); + dev_dbg(&pdev->dev, "%s: flush_on_mark == %d\n", + DRIVER_NAME, dev->flush_on_mark); + dev_dbg(&pdev->dev, "%s: maxrxmsgs == %u\n", + DRIVER_NAME, dev->maxrxmsgs); +#endif + dev_dbg(&pdev->dev, "%s: clks == %p/%p\n", + DRIVER_NAME, dev->clk_ipg, dev->clk_per); + dev_dbg(&pdev->dev, "%s: mem == %p\n", + DRIVER_NAME, (void *)res->start); + dev_dbg(&pdev->dev, "%s: rxbufsize == %u\n", + DRIVER_NAME, dev->rxbufsize); + dev_dbg(&pdev->dev, "%s: txbufsize == %u\n", + DRIVER_NAME, dev->txbufsize); + dev_dbg(&pdev->dev, "%s: maxtxmsg == %u\n", + DRIVER_NAME, dev->maxtxmsg); + dev_dbg(&pdev->dev, "%s: sas_dev == %p\n", + DRIVER_NAME, dev); + dev_dbg(&pdev->dev, "%s: umcr_reg == 0x%x\n", + DRIVER_NAME, dev->umcr_reg); + dev_info(&pdev->dev, "sas driver installed\n"); + return 0; + +fail_cdevadd: + devm_kfree(&pdev->dev, dev); +fail_entry: + return result; +} + +static int sas_remove(struct platform_device *pdev) +{ + struct sas_dev *dev = platform_get_drvdata(pdev); + if (dev) { + sysfs_remove_group(&pdev->dev.kobj, &sas_attr_grp); + cdev_del(&dev->cdev); + } + + dev_info(&pdev->dev, "sas driver released\n"); + return 0; +} + +MODULE_DEVICE_TABLE(of, sas_ids); + +static struct platform_driver sas_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = sas_ids, + }, + .probe = sas_probe, + .remove = sas_remove, +}; + +static char *sas_devnode(struct device *dev, umode_t *mode) +{ + if (mode) + *mode = S_IRUGO | S_IWUSR; + return kasprintf(GFP_KERNEL, "%s", DRIVER_NAME); +} + +static int __init sas_init(void) +{ + int result; + + /* Create a sysfs class. */ + sas_class = class_create(THIS_MODULE, "sas"); + if (IS_ERR(sas_class)) { + result = PTR_ERR(sas_class); + goto fail_class; + } + sas_class->devnode = sas_devnode; + + result = alloc_chrdev_region(&devnum, 0, 1, DRIVER_NAME); + if (result < 0) { + pr_err("%s: couldn't chrdevs: err %d\n", + DRIVER_NAME, result); + goto fail_chrdev; + } + sas_major = MAJOR(devnum); + + result = platform_driver_register(&sas_driver); + if (result < 0) { + pr_err("%s: couldn't register driver, err %d\n", + DRIVER_NAME, result); + goto fail_platform; + } + + return 0; + +fail_platform: + unregister_chrdev_region(devnum, 1); + +fail_chrdev: + class_destroy(sas_class); + sas_class = NULL; + +fail_class: + return result; +} + +static void __exit sas_cleanup(void) +{ + platform_driver_unregister(&sas_driver); + + unregister_chrdev_region(devnum, 1); + + if (!IS_ERR(sas_class)) + class_destroy(sas_class); +} + +module_init(sas_init); +module_exit(sas_cleanup); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 1ada68abb158a0..bb27b178c8c1bf 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -10,7 +10,13 @@ obj-y += \ clk-pllv1.o \ clk-pllv2.o \ clk-pllv3.o \ - clk-pfd.o + clk-pfd.o \ + clk-gate-exclusive.o \ + clk-composite.o \ + clk-frac-divider.o \ + clk-pllv4.o \ + clk-pllv5.o \ + clk-pfdv2.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o @@ -21,7 +27,9 @@ obj-$(CONFIG_SOC_IMX35) += clk-imx35.o obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o +obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o +obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c index 5cc99590f9a33a..59a133d291ee87 100644 --- a/drivers/clk/imx/clk-busy.c +++ b/drivers/clk/imx/clk-busy.c @@ -101,7 +101,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, init.name = name; init.ops = &clk_busy_divider_ops; - init.flags = CLK_SET_RATE_PARENT; + init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; init.parent_names = &parent_name; init.num_parents = 1; diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c new file mode 100644 index 00000000000000..7482bb923a153d --- /dev/null +++ b/drivers/clk/imx/clk-composite.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include "clk.h" + +#define PCG_CGC BIT(30) +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +struct clk *imx_clk_composite(const char *name, const char **parent_name, + int num_parents, bool mux_present, bool rate_present, bool gate_present, + void __iomem *reg) +{ + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + struct clk_frac_divider *div = NULL; + struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; + struct clk *clk; + + /* check if the mux is present in this composite clk. */ + if (mux_present) { + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) { + pr_err("%s: could not allocate mux clk\n", __func__); + return ERR_PTR(-ENOMEM); + } + mux_hw = &mux->hw; + /* init the mux struct */ + mux->reg = reg; + mux->shift = PCG_PCS_SHIFT; + mux->mask = PCG_PCS_MASK; + /* mux->lock */ + } + + if (rate_present) { + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + pr_err("%s: counld not allocate divider clk\n", __func__); + kfree(mux); + return ERR_PTR(-ENOMEM); + } + div_hw = &div->hw; + /* init the div struct */ + div->reg = reg; + div->mshift = 3; + div->mwidth = 1; + div->mmask = (0x1) << 3; + div->nshift = 0; + div->nwidth = 3; + div->nmask = 0x7; + } + + if (gate_present) { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + pr_err("%s: could not allocate gate clk\n", __func__); + kfree(mux); + kfree(div); + return ERR_PTR(-ENOMEM); + } + gate_hw = &gate->hw; + /* init the gate struct */ + gate->reg = reg; + gate->bit_idx = 30; + /* gate->lock */ + } + + /* register the composite clk itself */ + clk = clk_register_composite(NULL, name, parent_name, num_parents, + mux_hw, &clk_mux_ops, div_hw, &clk_frac_divider_ops, + gate_hw, &clk_gate_ops, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE); + + if (IS_ERR(clk)) { + kfree(mux); + kfree(div); + kfree(gate); + } + + return clk; +} diff --git a/drivers/clk/imx/clk-frac-divider.c b/drivers/clk/imx/clk-frac-divider.c new file mode 100644 index 00000000000000..0850ba2e26e53d --- /dev/null +++ b/drivers/clk/imx/clk-frac-divider.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Based on driver/clk/clk-fractional-divider.c + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define to_clk_frac_divider(_hw) container_of(_hw, struct clk_frac_divider, hw) + +static unsigned long clk_frac_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_frac_divider *fd = to_clk_frac_divider(hw); + u32 val, m, n; + u64 ret; + + val = readl_relaxed(fd->reg); + + m = (val & fd->mmask) >> fd->mshift; + n = (val & fd->nmask) >> fd->nshift; + + ret = (u64)parent_rate * (m + 1); + do_div(ret, n + 1); + + return ret; +} + +static long clk_frac_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_frac_divider *fd = to_clk_frac_divider(hw); + unsigned long scale; + unsigned long m, n; + u64 ret; + + if (!rate || rate >= *parent_rate) + return *parent_rate; + + scale = fls_long(*parent_rate / rate - 1); + if (scale > 4) + rate <<= scale - fd->nwidth; + + rational_best_approximation(rate, *parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + &m, &n); + + ret = (u64)*parent_rate * m; + do_div(ret, n); + + return ret; +} + +static int clk_frac_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_frac_divider *fd = to_clk_frac_divider(hw); + unsigned long m, n; + u32 val; + + rational_best_approximation(rate, parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + &m, &n); + m = m - 1; + n = n - 1; + if (m && !n) + return -EINVAL; + + val = readl_relaxed(fd->reg); + val &= ~(fd->mmask | fd->nmask); + val |= (m << fd->mshift) | (n << fd->nshift); + writel_relaxed(val, fd->reg); + + return 0; +} + +const struct clk_ops clk_frac_divider_ops = { + .recalc_rate = clk_frac_divider_recalc_rate, + .round_rate = clk_frac_divider_round_rate, + .set_rate = clk_frac_divider_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_frac_divider_ops); diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index db44a198a0d999..b9bd5938d44a9c 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2010-2011 Canonical Ltd * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -10,11 +11,13 @@ */ #include +#include #include #include #include #include #include +#include #include "clk.h" /** @@ -38,11 +41,56 @@ struct clk_gate2 { }; #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) +#define CCM_CCGR_FULL_ENABLE 0x3 + +static void clk_gate2_do_hardware(struct clk_gate2 *gate, bool enable) +{ + u32 reg; + + reg = readl(gate->reg); + if (enable) + reg |= CCM_CCGR_FULL_ENABLE << gate->bit_idx; + else + reg &= ~(CCM_CCGR_FULL_ENABLE << gate->bit_idx); + writel(reg, gate->reg); +} + +static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) +{ + struct clk_gate2 *gate = to_clk_gate2(hw); + + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_gate2_do_hardware(gate, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_gate2_do_hardware(gate, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_gate2_do_hardware(gate, enable); + } +} static int clk_gate2_enable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); - u32 reg; unsigned long flags = 0; spin_lock_irqsave(gate->lock, flags); @@ -50,11 +98,7 @@ static int clk_gate2_enable(struct clk_hw *hw) if (gate->share_count && (*gate->share_count)++ > 0) goto out; - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - reg |= gate->cgr_val << gate->bit_idx; - writel(reg, gate->reg); - + clk_gate2_do_shared_clks(hw, true); out: spin_unlock_irqrestore(gate->lock, flags); @@ -64,7 +108,6 @@ static int clk_gate2_enable(struct clk_hw *hw) static void clk_gate2_disable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); - u32 reg; unsigned long flags = 0; spin_lock_irqsave(gate->lock, flags); @@ -76,10 +119,7 @@ static void clk_gate2_disable(struct clk_hw *hw) goto out; } - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - writel(reg, gate->reg); - + clk_gate2_do_shared_clks(hw, false); out: spin_unlock_irqrestore(gate->lock, flags); } @@ -105,15 +145,11 @@ static void clk_gate2_disable_unused(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); unsigned long flags = 0; - u32 reg; spin_lock_irqsave(gate->lock, flags); - if (!gate->share_count || *gate->share_count == 0) { - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - writel(reg, gate->reg); - } + if (!gate->share_count || *gate->share_count == 0) + clk_gate2_do_shared_clks(hw, false); spin_unlock_irqrestore(gate->lock, flags); } diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c index 1e3c9ea5f9dcf9..b6ff2b9a3a1796 100644 --- a/drivers/clk/imx/clk-imx51-imx53.c +++ b/drivers/clk/imx/clk-imx51-imx53.c @@ -245,10 +245,10 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); - clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); + clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu1", "ipu_sel", MXC_CCM_CCGR5, 10); clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); - clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); - clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); + clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu1_di0", "ipu_di0_sel", MXC_CCM_CCGR6, 10); + clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu1_di1", "ipu_di1_sel", MXC_CCM_CCGR6, 12); clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); @@ -431,7 +431,13 @@ static void __init mx51_clocks_init(struct device_node *np) clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); - clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); + + clk[IMX5_CLK_HSI2C_SEL] = imx_clk_mux("hsi2c_sel", MXC_CCM_CSCMR2, 14, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_HSI2C_PRED] = imx_clk_divider("hsi2c_pred", "hsi2c_sel", MXC_CCM_CSCDR3, 16, 3); + clk[IMX5_CLK_HSI2C_PODF] = imx_clk_divider("hsi2c_podf", "hsi2c_pred", MXC_CCM_CSCDR3, 9, 6); + clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "hsi2c_podf", MXC_CCM_CCGR1, 22); + clk[IMX5_CLK_HSI2C_IPG_GATE] = imx_clk_gate2("hsi2c_ipg_gate", "ipg", MXC_CCM_CCGR1, 24); clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); @@ -459,6 +465,8 @@ static void __init mx51_clocks_init(struct device_node *np) clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); + clk_set_rate(clk[IMX5_CLK_HSI2C_PODF], 2000000); + clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 93a19667003d46..af7d4f2573cd55 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -1,6 +1,7 @@ /* - * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -31,7 +32,8 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; +static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = { "periph", "axi_alt_sel", }; static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *pre_axi_sels[] = { "axi", "ahb", }; @@ -41,15 +43,17 @@ static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_p static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; +static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; +static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; @@ -65,7 +69,7 @@ static const char *ipg_per_sels[] = { "ipg", "osc", }; static const char *ecspi_sels[] = { "pll3_60m", "osc", }; static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", }; static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", - "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", + "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; static const char *cko2_sels[] = { "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", @@ -95,11 +99,14 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clk[IMX6QDL_CLK_END]; static struct clk_onecell_data clk_data; +static void __iomem *ccm_base; static unsigned int const clks_init_on[] __initconst = { IMX6QDL_CLK_MMDC_CH0_AXI, IMX6QDL_CLK_ROM, IMX6QDL_CLK_ARM, + IMX6QDL_CLK_OCRAM, + IMX6QDL_CLK_AXI, }; static struct clk_div_table clk_enet_ref_table[] = { @@ -156,12 +163,340 @@ static struct clk ** const uart_clks[] __initconst = { NULL }; +static int ldb_di_sel_by_clock_id(int clock_id) +{ + switch (clock_id) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + if (clk_on_imx6q() && + imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + return -ENOENT; + return 0; + case IMX6QDL_CLK_PLL2_PFD0_352M: + return 1; + case IMX6QDL_CLK_PLL2_PFD2_396M: + return 2; + case IMX6QDL_CLK_MMDC_CH1_AXI: + return 3; + case IMX6QDL_CLK_PLL3_USB_OTG: + return 4; + default: + return -ENOENT; + } +} + +static void of_assigned_ldb_sels(struct device_node *node, + unsigned int *ldb_di0_sel, + unsigned int *ldb_di1_sel) +{ + struct of_phandle_args clkspec; + int index, rc, num_parents; + int parent, child, sel; + + num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", + "#clock-cells"); + for (index = 0; index < num_parents; index++) { + rc = of_parse_phandle_with_args(node, "assigned-clock-parents", + "#clock-cells", index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return; + } + if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { + pr_err("ccm: parent clock %d not in ccm\n", index); + return; + } + parent = clkspec.args[0]; + + rc = of_parse_phandle_with_args(node, "assigned-clocks", + "#clock-cells", index, &clkspec); + if (rc < 0) + return; + if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { + pr_err("ccm: child clock %d not in ccm\n", index); + return; + } + child = clkspec.args[0]; + + if (child != IMX6QDL_CLK_LDB_DI0_SEL && + child != IMX6QDL_CLK_LDB_DI1_SEL) + continue; + + sel = ldb_di_sel_by_clock_id(parent); + if (sel < 0) { + pr_err("ccm: invalid ldb_di%d parent clock: %d\n", + child == IMX6QDL_CLK_LDB_DI1_SEL, parent); + continue; + } + + if (child == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = sel; + if (child == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = sel; + } +} + +#define CCM_CCDR 0x04 +#define CCM_CCSR 0x0c +#define CCM_CS2CDR 0x2c +#define CCM_CSCDR3 0x3c +#define CCM_CCGR0 0x68 +#define CCM_CCGR3 0x74 + +#define ANATOP_PLL3_PFD 0xf0 + + +#define CCDR_MMDC_CH1_MASK BIT(16) +#define CCSR_PLL3_SW_CLK_SEL BIT(0) + +#define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 +#define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 + +#define OCOTP_CFG3 0x440 +#define OCOTP_CFG3_SPEED_SHIFT 16 +#define OCOTP_CFG3_SPEED_1P2GHZ 0x3 + +static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base) +{ + unsigned int reg; + + reg = readl_relaxed(ccm_base + CCM_CCDR); + reg |= CCDR_MMDC_CH1_MASK; + writel_relaxed(reg, ccm_base + CCM_CCDR); +} + +/* + * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk + * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the + * bypass clock source, since there is no CG bit for mmdc_ch1. + */ +static void mmdc_ch1_disable(void __iomem *ccm_base) +{ + unsigned int reg; + + clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], + clk[IMX6QDL_CLK_PLL3_USB_OTG]); + + /* + * Handshake with mmdc_ch1 module must be masked when changing + * periph2_clk_sel. + */ + clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]); + + /* Disable pll3_sw_clk by selecting the bypass clock source */ + reg = readl_relaxed(ccm_base + CCM_CCSR); + reg |= CCSR_PLL3_SW_CLK_SEL; + writel_relaxed(reg, ccm_base + CCM_CCSR); +} + +static void mmdc_ch1_reenable(void __iomem *ccm_base) +{ + unsigned int reg; + + /* Enable pll3_sw_clk by disabling the bypass */ + reg = readl_relaxed(ccm_base + CCM_CCSR); + reg &= ~CCSR_PLL3_SW_CLK_SEL; + writel_relaxed(reg, ccm_base + CCM_CCSR); + + clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]); +} + +/* + * We have to follow a strict procedure when changing the LDB clock source, + * otherwise we risk introducing a glitch that can lock up the LDB divider. + * Things to keep in mind: + * + * 1. The current and new parent clock inputs to the mux must be disabled. + * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which + * has no CG bit. + * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. + * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four + * options are in one mux and the PLL3 option along with three unused + * inputs is in a second mux. There is a third mux with two inputs used + * to decide between the first and second 4-port mux: + * + * pll5_video_div 0 --|\ + * pll2_pfd0_352m 1 --| |_ + * pll2_pfd2_396m 2 --| | `-|\ + * mmdc_ch1_axi 3 --|/ | | + * | |-- + * pll3_usb_otg 4 --|\ | | + * 5 --| |_,-|/ + * 6 --| | + * 7 --|/ + * + * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. + * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below + * switches the parent to the bottom mux first and then manipulates the top + * mux to ensure that no glitch will enter the divider. + */ +static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) +{ + unsigned int reg; + unsigned int sel[2][4]; + int i; + + reg = readl_relaxed(ccm_base + CCM_CS2CDR); + sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; + sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; + + sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; + sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; + + of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]); + + for (i = 0; i < 2; i++) { + /* Warn if a glitch might have been introduced already */ + if (sel[i][0] != 3) { + pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n", + i, sel[i][0]); + } + + if (sel[i][0] == sel[i][3]) + continue; + + /* Only switch to or from pll2_pfd2_396m if it is disabled */ + if ((sel[i][0] == 2 || sel[i][3] == 2) && + (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == + clk[IMX6QDL_CLK_PLL2_PFD2_396M])) { + pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n", + i); + sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; + continue; + } + + /* First switch to the bottom mux */ + sel[i][1] = sel[i][0] | 4; + + /* Then configure the top mux before switching back to it */ + sel[i][2] = sel[i][3] | 4; + + pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, + sel[i][0], sel[i][1], sel[i][2], sel[i][3]); + } + + if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) + return; + + mmdc_ch1_disable(ccm_base); + + for (i = 1; i < 4; i++) { + reg = readl_relaxed(ccm_base + CCM_CS2CDR); + reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | + (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); + reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | + (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); + writel_relaxed(reg, ccm_base + CCM_CS2CDR); + } + + mmdc_ch1_reenable(ccm_base); +} + +#define CCM_ANALOG_PLL_VIDEO 0xa0 +#define CCM_ANALOG_PFD_480 0xf0 +#define CCM_ANALOG_PFD_528 0x100 + +#define PLL_ENABLE BIT(13) + +#define PFD0_CLKGATE BIT(7) +#define PFD1_CLKGATE BIT(15) +#define PFD2_CLKGATE BIT(23) +#define PFD3_CLKGATE BIT(31) + +/* + * workaround for ERR010579, when switching the clock source of IPU clock + * root in CCM. even setting CCGR3[CG0]=0x0 to gate off clock before + * switching, IPU may hang due to no IPU clock from CCM. + */ +static void __init init_ipu_clk(void __iomem *anatop_base) +{ + u32 val, origin_podf; + + /* gate off the IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val &= ~0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* gate off IPU DCIC1/2 clocks */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val &= ~(0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); + + /* set IPU_PODF to 3'b000 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + origin_podf = val & (0x7 << 11); + val &= ~(0x7 << 11); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* disable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val &= ~(0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* switch IPU_SEL clock to PLL3_PFD1 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= (0x3 << 9); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* restore the IPU PODF*/ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= origin_podf; + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* enable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val |= (0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* enable IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val |= 0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* enable IPU DCIC1/2 clock */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val |= (0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); +} + +static void disable_anatop_clocks(void __iomem *anatop_base) +{ + unsigned int reg; + struct clk *parent = clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]); + + /* Make sure PLL2 PFDs 0-2 are gated */ + reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); + reg |= PFD1_CLKGATE; /* Disable PFD1 */ + + /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ + if (parent == clk[IMX6QDL_CLK_PLL2_PFD0_352M]) { + reg |= PFD2_CLKGATE; /* Disable PFD2 */ + } else { + reg |= PFD0_CLKGATE; /* Disable PFD0 */ + if (parent == clk[IMX6QDL_CLK_PLL2_BUS]) + reg |= PFD2_CLKGATE; /* Disable PFD2 */ + } + writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); + + /* Make sure PLL3 PFDs 0-3 are gated */ + reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); + reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; + writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); + + /* Make sure PLL5 is disabled */ + reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); + reg &= ~PLL_ENABLE; + writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); +} + static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; - void __iomem *base; + void __iomem *anatop_base, *base; int i; - int ret; + u32 val; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); @@ -172,7 +507,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); - base = of_iomap(np, 0); + anatop_base = base = of_iomap(np, 0); WARN_ON(!base); /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ @@ -193,7 +528,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* type name parent_name base div_mask */ clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); - clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); + clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_PLL2, "pll2", "osc", base + 0x30, 0x1); clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); @@ -217,7 +552,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); - clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); + clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); @@ -288,23 +623,26 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); } - clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); - clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); - clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); - clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); + clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); np = ccm_node; base = of_iomap(np, 0); + ccm_base = base; WARN_ON(!base); + imx6q_mmdc_ch1_mask_handshake(base); /* name reg shift width parent_names num_parents */ clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); + clk[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); + clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); @@ -330,8 +668,25 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); + + if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { + clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); + clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); + } else { + disable_anatop_clocks(anatop_base); + + /* + * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware + * bug. Set the muxes to the requested values before registering the + * ldb_di_sel clocks. + */ + init_ldb_clks(np, base); + + clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + } + clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); + clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); @@ -397,6 +752,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); + clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0", 1, 7); + clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1", 1, 7); } else { clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); @@ -404,6 +761,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); + clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7); } if (clk_on_imx6dl()) clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); @@ -470,6 +829,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); + clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24); + clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26); clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); @@ -487,7 +848,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); - clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4); + clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); @@ -580,17 +941,27 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG], "ipg", "imx-gpt.0"); + clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG_PER], "per", "imx-gpt.0"); + clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0"); clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || - clk_on_imx6dl()) { - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - } - clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); - if (clk_on_imx6dl()) + if (clk_on_imx6dl()) { + init_ipu_clk(anatop_base); clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); + clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); + clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]); + /* set epdc/pxp axi clock to 200Mhz */ + clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); + clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000); + } else { + /* set eim_slow to 132Mhz for i.MX6Q */ + if (clk_on_imx6q()) + clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 132000000); + clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); + clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); + } clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); @@ -601,6 +972,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); + /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. @@ -608,30 +980,102 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) */ clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); + /* gpu clock initilazation */ + /* + * On mx6dl, 2d core clock sources(sel, podf) is from 3d + * shader core clock, but 3d shader clock multiplexer of + * mx6dl is different. For instance the equivalent of + * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl. + * Make a note here. + */ + if (clk_on_imx6dl()) { + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000); + /* for mx6dl, change gpu3d_core parent to 594_PFD*/ + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000); + } else if (clk_on_imx6q()) { + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 720000000); + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 594000000); + clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 720000000); + } else { + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000); + clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000); + clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); + imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000); + } } /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. */ - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); - if (!ret) - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); - if (ret) - pr_warn("failed to set up CLKO: %d\n", ret); + imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); + imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); /* Audio-related clocks configuration */ clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); /* All existing boards with PCIe use LVDS1 */ - if (IS_ENABLED(CONFIG_PCI_IMX6)) + if (IS_ENABLED(CONFIG_PCI_IMX6)) { clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); + np = of_find_compatible_node(NULL, NULL, "snps,dw-pcie"); + /* external oscillator is used or not. */ + if (of_property_read_u32(np, "ext_osc", &val) < 0) + val = 0; + /* + * imx6qp sabresd revb board has the external osc used by pcie + * - pll6 should be set bypass mode later in driver. + * - lvds_clk1 should be selected as pll6 bypass src, set here. + */ + if (clk_on_imx6qp() && val == 1) + clk_set_parent(clk[IMX6QDL_PLL6_BYPASS_SRC], clk[IMX6QDL_CLK_LVDS1_IN]); + } + + /* + * Enable clocks only after both parent and rate are all initialized + * as needed + */ + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + imx_clk_prepare_enable(clk[clks_init_on[i]]); + + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { + imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); + imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); + } + + if (clk_on_imx6qp()) { + /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ + clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000); + } + +#ifdef CONFIG_MX6_VPU_352M + /* + * If VPU 352M is enabled, then PLL2_PDF2 need to be + * set to 352M, cpufreq will be disabled as VDDSOC/PU + * need to be at highest voltage, scaling cpu freq is + * not saving any power, and busfreq will be also disabled + * as the PLL2_PFD2 is not at default freq, in a word, + * all modules that sourceing clk from PLL2_PFD2 will + * be impacted. + */ + imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD2_396M], 352000000); + clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); + pr_info("VPU 352M is enabled!\n"); +#else + imx_clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); + + if (clk_on_imx6dl()) + imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 306000000); + else + imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 327000000); +#endif /* * Initialize the GPU clock muxes, so that the maximum specified clock @@ -652,5 +1096,35 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) } imx_register_uart_clocks(uart_clks); + + /* + * for i.MX6QP with speeding grading set to 1.2GHz, + * VPU should run at 396MHz. + */ + if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); + WARN_ON(!np); + + base = of_iomap(np, 0); + WARN_ON(!base); + + /* + * SPEED_GRADING[1:0] defines the max speed of ARM: + * 2b'11: 1200000000Hz; + * 2b'10: 996000000Hz; + * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. + * 2b'00: 792000000Hz; + * We need to set the max speed of ARM according to fuse map. + */ + val = readl_relaxed(base + OCOTP_CFG3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + if (val == OCOTP_CFG3_SPEED_1P2GHZ) { + imx_clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); + imx_clk_set_rate(clk[IMX6QDL_CLK_VPU_AXI_PODF], 396000000); + pr_info("VPU frequency set to 396MHz!\n"); + } + iounmap(base); + } } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 5fd4ddac1bf19c..bedbb7efa2d01d 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include @@ -18,6 +19,8 @@ #include "clk.h" #define CCSR 0xc +#define CCDR 0x04 +#define CCDR_CH0_HS_BYP 17 #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) #define CACRR 0x10 #define CDHIPR 0x48 @@ -55,7 +58,7 @@ static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_ static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; static const char *ecspi_sels[] = { "pll3_60m", "osc", }; -static const char *uart_sels[] = { "pll3_80m", "osc", }; +static const char *uart_sels[] = { "pll3_80m", "uart_osc_4m", }; static const char *lvds_sels[] = { "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video", "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1", @@ -143,46 +146,39 @@ static int imx6sl_get_arm_divider_for_wait(void) } } -static void imx6sl_enable_pll_arm(bool enable) -{ - static u32 saved_pll_arm; - u32 val; - - if (enable) { - saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); - val |= BM_PLL_ARM_ENABLE; - val &= ~BM_PLL_ARM_POWERDOWN; - writel_relaxed(val, anatop_base + PLL_ARM); - while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) - ; - } else { - writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); - } -} - void imx6sl_set_wait_clk(bool enter) { static unsigned long saved_arm_div; + u32 val; int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); - - /* - * According to hardware design, arm podf change need - * PLL1 clock enabled. - */ - if (arm_div_for_wait == ARM_WAIT_DIV_396M) - imx6sl_enable_pll_arm(true); + int mode = get_bus_freq_mode(); if (enter) { - saved_arm_div = readl_relaxed(ccm_base + CACRR); - writel_relaxed(arm_div_for_wait, ccm_base + CACRR); + /* + * If in this mode, the IPG clock is at 12MHz, we can + * only run ARM at a max 28.8MHz, so we need to run + * from the 24MHz OSC, as there is no way to get + * 28.8MHz, when ARM is sourced from PLl1. + */ + if (mode == BUS_FREQ_LOW) { + val = readl_relaxed(ccm_base + CCSR); + val |= BM_CCSR_PLL1_SW_CLK_SEL; + writel_relaxed(val, ccm_base + CCSR); + } else { + saved_arm_div = readl_relaxed(ccm_base + CACRR); + writel_relaxed(arm_div_for_wait, ccm_base + CACRR); + } } else { - writel_relaxed(saved_arm_div, ccm_base + CACRR); + if (mode == BUS_FREQ_LOW) { + val = readl_relaxed(ccm_base + CCSR); + val &= ~BM_CCSR_PLL1_SW_CLK_SEL; + writel_relaxed(val, ccm_base + CCSR); + } else { + writel_relaxed(saved_arm_div, ccm_base + CACRR); + } } while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) ; - - if (arm_div_for_wait == ARM_WAIT_DIV_396M) - imx6sl_enable_pll_arm(false); } static struct clk ** const uart_clks[] __initconst = { @@ -195,7 +191,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; + int i, reg; int ret; clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -227,7 +223,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); - clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags_bus("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); @@ -243,7 +239,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]); clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]); - clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); + clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); @@ -271,7 +267,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); - clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); /* name parent_name reg idx */ @@ -288,6 +284,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + clks[IMX6SL_CLK_UART_OSC_4M] = imx_clk_fixed_factor("uart_osc_4m", "osc", 1, 6); np = ccm_node; base = of_iomap(np, 0); @@ -296,13 +293,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* name reg shift width parent_names num_parents */ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); - clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); - clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); - clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux_bus("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); + clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux_bus("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); + clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); @@ -317,8 +314,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); - clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); - clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); + clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux_flags("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels), CLK_SET_RATE_PARENT); + clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux_flags("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels), CLK_SET_RATE_PARENT); clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); @@ -330,7 +327,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); /* name parent_name reg shift width */ - clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); + clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0); clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); @@ -420,6 +417,11 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + /* Ensure the CH0 handshake is bypassed */ + reg = readl_relaxed(base + CCDR); + reg |= 1 << CCDR_CH0_HS_BYP; + writel_relaxed(reg, base + CCDR); + /* Ensure the AHB clk is at 132MHz. */ ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); if (ret) @@ -441,6 +443,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* Audio-related clocks configuration */ clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + /* Initialize Video PLLs to valid frequency (650MHz). */ + imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000); /* set PLL5 video as lcdif pix parent clock */ clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); @@ -448,6 +452,18 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]); + /* Configure EPDC clocks */ + clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL], + clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); + clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], + clks[IMX6SL_CLK_PLL2_PFD2]); + clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000); + + /* Set the UART parent if needed */ + if (uart_from_osc) + imx_clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]); + imx_register_uart_clocks(uart_clks); + } CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c new file mode 100644 index 00000000000000..afb7819d5eec0c --- /dev/null +++ b/drivers/clk/imx/clk-imx6sll.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16) +#define CCDR 0x4 + +static const char *pll_bypass_src_sels[] = { "osc", "dummy", }; +static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; +static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; +static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; +static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; +static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; +static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; +static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; +static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; +static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; +static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = {"periph", "axi_alt_sel", }; +static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", }; +static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; +static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; +static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",}; +static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; +static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; +static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; +static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", }; +static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", }; +static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", }; +static const char *ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *uart_sels[] = { "pll3_80m", "osc", }; +static const char *perclk_sels[] = { "ipg", "osc", }; +static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; + +static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; + +static struct clk *clks[IMX6SLL_CLK_END]; +static struct clk_onecell_data clk_data; + +static int const clks_init_on[] __initconst = { + IMX6SLL_CLK_AIPSTZ1, IMX6SLL_CLK_AIPSTZ2, + IMX6SLL_CLK_OCRAM, IMX6SLL_CLK_ARM, IMX6SLL_CLK_ROM, + IMX6SLL_CLK_MMDC_P0_FAST, IMX6SLL_CLK_MMDC_P0_IPG, +}; + +static struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { } +}; + +static struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { } +}; + +static u32 share_count_audio; +static u32 share_count_ssi1; +static u32 share_count_ssi2; +static u32 share_count_ssi3; + +static void __init imx6sll_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + void __iomem *base; + int i; + + clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + + clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); + clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + + /* ipp_di clock is external input */ + clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); + clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + + clks[IMX6SLL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); + clks[IMX6SLL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); + clks[IMX6SLL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); + clks[IMX6SLL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); + clks[IMX6SLL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); + clks[IMX6SLL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); + clks[IMX6SLL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); + + clks[IMX6SLL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6SLL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); + + /* Do not bypass PLLs initially */ + clk_set_parent(clks[IMX6SLL_PLL1_BYPASS], clks[IMX6SLL_CLK_PLL1]); + clk_set_parent(clks[IMX6SLL_PLL2_BYPASS], clks[IMX6SLL_CLK_PLL2]); + clk_set_parent(clks[IMX6SLL_PLL3_BYPASS], clks[IMX6SLL_CLK_PLL3]); + clk_set_parent(clks[IMX6SLL_PLL4_BYPASS], clks[IMX6SLL_CLK_PLL4]); + clk_set_parent(clks[IMX6SLL_PLL5_BYPASS], clks[IMX6SLL_CLK_PLL5]); + clk_set_parent(clks[IMX6SLL_PLL6_BYPASS], clks[IMX6SLL_CLK_PLL6]); + clk_set_parent(clks[IMX6SLL_PLL7_BYPASS], clks[IMX6SLL_CLK_PLL7]); + + clks[IMX6SLL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); + clks[IMX6SLL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); + clks[IMX6SLL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); + clks[IMX6SLL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); + clks[IMX6SLL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); + clks[IMX6SLL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); + clks[IMX6SLL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); + + /* + * Bit 20 is the reserved and read-only bit, we do this only for: + * - Do nothing for usbphy clk_enable/disable + * - Keep refcount when do usbphy clk_enable/disable, in that case, + * the clk framework many need to enable/disable usbphy's parent + */ + clks[IMX6SLL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); + clks[IMX6SLL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); + + /* + * usbphy*_gate needs to be on after system boots up, and software + * never needs to control it anymore. + */ + clks[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); + clks[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); + + /* name parent_name reg idx */ + clks[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clks[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); + clks[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); + clks[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); + clks[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); + clks[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); + clks[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); + clks[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); + + clks[IMX6SLL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); + clks[IMX6SLL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + + /* name parent_name mult div */ + clks[IMX6SLL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); + clks[IMX6SLL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); + clks[IMX6SLL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + clks[IMX6SLL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + clks[IMX6SLL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); + + np = ccm_node; + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX6SLL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); + clks[IMX6SLL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[IMX6SLL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); + clks[IMX6SLL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); + clks[IMX6SLL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6SLL_CLK_PERIPH2_PRE] = imx_clk_mux_bus("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); + clks[IMX6SLL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6SLL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SLL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SLL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6SLL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SLL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SLL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); + clks[IMX6SLL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); + clks[IMX6SLL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); + clks[IMX6SLL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); + clks[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x30, 7, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); + clks[IMX6SLL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); + clks[IMX6SLL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); + clks[IMX6SLL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); + clks[IMX6SLL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); + clks[IMX6SLL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); + + clks[IMX6SLL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); + clks[IMX6SLL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); + + clks[IMX6SLL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); + clks[IMX6SLL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); + clks[IMX6SLL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); + clks[IMX6SLL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); + clks[IMX6SLL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6SLL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); + clks[IMX6SLL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); + clks[IMX6SLL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); + clks[IMX6SLL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); + clks[IMX6SLL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); + clks[IMX6SLL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); + clks[IMX6SLL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); + clks[IMX6SLL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); + clks[IMX6SLL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); + clks[IMX6SLL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); + clks[IMX6SLL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); + clks[IMX6SLL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); + clks[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x30, 12, 3); + clks[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9, 3); + clks[IMX6SLL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3); + clks[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); + clks[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); + + clks[IMX6SLL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); + clks[IMX6SLL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); + clks[IMX6SLL_CLK_AXI_PODF] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); + clks[IMX6SLL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); + + clks[IMX6SLL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); + clks[IMX6SLL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); + clks[IMX6SLL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + clks[IMX6SLL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7); + + clks[IMX6SLL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); + clks[IMX6SLL_CLK_LDB_DI1_SEL] = imx_clk_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels)); + clks[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); + clks[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); + + /* CCGR0 */ + clks[IMX6SLL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); + clks[IMX6SLL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10); + clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); + clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); + + /* CCGR1 */ + clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); + clks[IMX6SLL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); + clks[IMX6SLL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); + clks[IMX6SLL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); + clks[IMX6SLL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10); + clks[IMX6SLL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); + clks[IMX6SLL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); + clks[IMX6SLL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); + clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20); + clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); + clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); + clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); + + /* CCGR2 */ + clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2); + clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); + clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); + clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); + clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); + clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28); + clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30); + + /* CCGR3 */ + clks[IMX6SLL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); + clks[IMX6SLL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); + clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4); + clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); + clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); + clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); + clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); + clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); + clks[IMX6SLL_CLK_OCRAM] = imx_clk_gate("ocram", "ahb", base + 0x74, 28); + + /* CCGR4 */ + clks[IMX6SLL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); + clks[IMX6SLL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); + clks[IMX6SLL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); + clks[IMX6SLL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); + + /* CCGR5 */ + clks[IMX6SLL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6SLL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); + clks[IMX6SLL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); + clks[IMX6SLL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); + clks[IMX6SLL_CLK_EXTERN_AUDIO] = imx_clk_gate2_shared("extern_audio", "extern_audio_podf", base + 0x7c, 14, &share_count_audio); + clks[IMX6SLL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); + clks[IMX6SLL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); + clks[IMX6SLL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); + clks[IMX6SLL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); + clks[IMX6SLL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); + clks[IMX6SLL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); + clks[IMX6SLL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); + clks[IMX6SLL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); + clks[IMX6SLL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24); + clks[IMX6SLL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); + + /* CCGR6 */ + clks[IMX6SLL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); + clks[IMX6SLL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); + clks[IMX6SLL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); + clks[IMX6SLL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); + + /* mask handshake of mmdc */ + writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); + + for (i = 0; i < ARRAY_SIZE(clks); i++) + if (IS_ERR(clks[i])) + pr_err("i.MX6SLL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + /* set perclk to from OSC */ + clk_set_parent(clks[IMX6SLL_CLK_PERCLK_SEL], clks[IMX6SLL_CLK_OSC]); + + /* Set the UART parent if needed */ + if (uart_from_osc) + imx_clk_set_parent(clks[IMX6SLL_CLK_UART_SEL], clks[IMX6SLL_CLK_OSC]); + else + imx_clk_set_parent(clks[IMX6SLL_CLK_UART_SEL], clks[IMX6SLL_CLK_PLL3_80M]); + + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); + + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { + clk_prepare_enable(clks[IMX6SLL_CLK_USBPHY1_GATE]); + clk_prepare_enable(clks[IMX6SLL_CLK_USBPHY2_GATE]); + } + + /* Lower the AHB clock rate before changing the clock source. */ + imx_clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000); + + /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ + imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL], clks[IMX6SLL_CLK_PLL3_USB_OTG]); + imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_CLK2]); + imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE], clks[IMX6SLL_CLK_PLL2_BUS]); + imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]); + + imx_clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000); + + /* Configure EPDC clocks */ + imx_clk_set_rate(clks[IMX6SLL_CLK_PLL3_PFD2], 320000000); + clk_set_parent(clks[IMX6SLL_CLK_EPDC_PRE_SEL], + clks[IMX6SLL_CLK_PLL3_PFD2]); + +} + +CLK_OF_DECLARE(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index b5c96de41ccf95..a915e28056dd75 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -13,15 +14,19 @@ #include #include #include +#include #include #include #include #include #include #include +#include +#include #include "clk.h" +#define CCM_CCGR_OFFSET(index) (index * 2) #define CCDR 0x4 #define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16) @@ -80,7 +85,7 @@ static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", }; -static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", }; +static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; @@ -91,18 +96,19 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; static struct clk *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; +struct imx_sema4_mutex *amp_power_mutex; + +static int clks_shared[MAX_SHARED_CLK_NUMBER]; + +struct imx_shared_mem *shared_mem; +static unsigned int shared_mem_paddr, shared_mem_size; static int const clks_init_on[] __initconst = { IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3, IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4, - IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG, - IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5, - IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG, - IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1, - IMX6SX_CLK_EPIT2, + IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, }; static struct clk_div_table clk_enet_ref_table[] = { @@ -143,6 +149,38 @@ static struct clk ** const uart_clks[] __initconst = { NULL }; +/* + * As IMX6SX_CLK_M4_PRE_SEL is NOT a glitchless MUX, so when + * M4 is trying to change its clk parent, need to ask A9 to + * help do it, and M4 must be hold in wfi. To avoid glitch + * occur, need to gate M4 clk first before switching its parent. + */ +void imx6sx_set_m4_highfreq(bool high_freq) +{ + static struct clk *m4_high_freq_sel; + + imx_gpc_hold_m4_in_sleep(); + + clk_disable_unprepare(clks[IMX6SX_CLK_M4]); + imx_clk_set_parent(clks[IMX6SX_CLK_M4_SEL], + clks[IMX6SX_CLK_LDB_DI0]); + + if (high_freq) { + imx_clk_set_parent(clks[IMX6SX_CLK_M4_PRE_SEL], + m4_high_freq_sel); + } else { + m4_high_freq_sel = clk_get_parent(clks[IMX6SX_CLK_M4_PRE_SEL]); + imx_clk_set_parent(clks[IMX6SX_CLK_M4_PRE_SEL], + clks[IMX6SX_CLK_OSC]); + } + + imx_clk_set_parent(clks[IMX6SX_CLK_M4_SEL], + clks[IMX6SX_CLK_M4_PRE_SEL]); + clk_prepare_enable(clks[IMX6SX_CLK_M4]); + + imx_gpc_release_m4_in_sleep(); +} + static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -160,6 +198,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* Clock source from external clock via CLK1 PAD */ clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); + clks[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); @@ -175,7 +214,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* type name parent_name base div_mask */ clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); - clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); + clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_PLL2, "pll2", "osc", base + 0x30, 0x1); clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); @@ -191,15 +230,15 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); /* Do not bypass PLLs initially */ - clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]); - clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]); - clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]); - clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]); - clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]); - clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]); - clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]); - - clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); + imx_clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]); + imx_clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]); + imx_clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]); + imx_clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]); + imx_clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]); + imx_clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]); + imx_clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]); + + clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); @@ -228,7 +267,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); + clks[IMX6SX_CLK_LVDS2_OUT] = imx_clk_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13)); clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); + clks[IMX6SX_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, @@ -270,6 +311,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* name reg shift width parent_names num_parents */ clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + clks[IMX6SX_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); np = ccm_node; base = of_iomap(np, 0); @@ -277,12 +319,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* name reg shift width parent_names num_parents */ clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels)); - clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); - clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux_bus("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); + clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels)); @@ -294,13 +336,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT); + clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels)); clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); - clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT); + clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels)); clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels)); @@ -494,79 +536,196 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); + /* get those shared clk nodes if M4 is active */ + if (imx_src_is_m4_enabled()) { + u32 num; + + of_property_read_u32(np, "fsl,shared-clks-number", &num); + if (num > MAX_SHARED_CLK_NUMBER) + pr_err("clk: shared clk nodes exceed the max number!\n"); + of_property_read_u32_array(np, "fsl,shared-clks-index", + clks_shared, num); + if (of_property_read_u32(np, "fsl,shared-mem-addr", + &shared_mem_paddr)) + pr_err("clk: fsl,shared-mem-addr NOT found!\n"); + if (of_property_read_u32(np, "fsl,shared-mem-size", + &shared_mem_size)) + pr_err("clk: fsl,shared-mem-size NOT found!\n"); + } + /* mask handshake of mmdc */ writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); imx_check_clocks(clks, ARRAY_SIZE(clks)); + /* + * QSPI2/GPMI_IO share the same clock source but with the + * different gate, need explicitely gate the QSPI2 & GPMI_IO + * during the clock init phase according to the SOC design. + */ + if (!imx_src_is_m4_enabled()) { + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + } + clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + /* + * As some of the modules need to access ocotp in MSL, + * need to make sure ocotp clk(CCM_CCGR2_CG6) is enabled + * during MSL, as on i.MX6SX, accessing OCOTP registers + * needs its clk on, it will be disabled by clk late + * init and managed by ocotp driver. + */ + writel_relaxed(readl_relaxed(base + 0x70) | 1 << 12, base + 0x70); + + /* maintain M4 usecount */ + if (imx_src_is_m4_enabled()) + imx_clk_prepare_enable(clks[IMX6SX_CLK_M4]); + + /* set perclk to from OSC */ + imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); + imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); + imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } /* Set the default 132MHz for EIM module */ - clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); + imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); + imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + + /* set parent clock for LCDIF2 */ + imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF2_SEL], clks[IMX6SX_CLK_LDB_DI0]); /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ - if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) - pr_err("Failed to set pcie bus parent clk.\n"); - if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) - pr_err("Failed to set pcie parent clk.\n"); + imx_clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]); + imx_clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]); /* * Init enet system AHB clock, set to 200MHz * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB */ - clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); - clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); - clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); - clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); + imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); + imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); + imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); + imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); + imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); - clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); + imx_clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + imx_clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 24576000); - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + imx_clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + imx_clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); - clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); + imx_clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + imx_clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + imx_clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + imx_clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); + imx_clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); + imx_clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); - clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + imx_clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + imx_clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); - /* Set parent clock for vadc */ - clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + /* Set the UART parent if needed. */ + if (uart_from_osc) + clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]); + else + clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_PLL3_80M]); - /* default parent of can_sel clock is invalid, manually set it here */ - clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + /* Set parent clock for vadc */ + imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); /* Update gpu clock from default 528M to 720M */ - clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); - clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + imx_clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + imx_clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + /* Set the UART parent if needed. */ + if (uart_from_osc) + imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]); + + if (!imx_src_is_m4_enabled()) + /* default parent of can_sel clock is invalid, manually set it here */ + imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + imx_clk_prepare_enable(clks[clks_init_on[i]]); imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); + +int imx_update_shared_mem(struct clk_hw *hw, bool enable) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + if (shared_mem->imx_clk[i].self == hw->clk) + break; + } + + if (i >= ARRAY_SIZE(clks_shared)) + return 1; + + /* update ca9 clk status in shared memory */ + if (enable) + shared_mem->imx_clk[i].ca9_enabled = 1; + else + shared_mem->imx_clk[i].ca9_enabled = 0; + + if (shared_mem->imx_clk[i].cm4_enabled == 0) + return 1; + + return 0; +} + +static int __init imx_amp_power_init(void) +{ + int i; + void __iomem *shared_mem_base; + + if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) + return 0; + + amp_power_mutex = imx_sema4_mutex_create(0, MCC_POWER_SHMEM_NUMBER); + + shared_mem_base = ioremap_nocache(shared_mem_paddr, shared_mem_size); + + if (!amp_power_mutex) { + pr_err("Failed to create sema4 mutex!\n"); + return 0; + } + + shared_mem = (struct imx_shared_mem *)shared_mem_base; + + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + shared_mem->imx_clk[i].self = clks[clks_shared[i]]; + shared_mem->imx_clk[i].ca9_enabled = 1; + pr_debug("%d: name %s, addr 0x%x\n", i, + __clk_get_name(shared_mem->imx_clk[i].self), + (u32)&(shared_mem->imx_clk[i])); + } + /* enable amp power management */ + shared_mem->ca9_valid = SHARED_MEM_MAGIC_NUMBER; + + pr_info("A9-M4 sema4 num %d, A9-M4 magic number 0x%x - 0x%x.\n", + amp_power_mutex->gate_num, shared_mem->ca9_valid, + shared_mem->cm4_valid); + + return 0; +} +late_initcall(imx_amp_power_init); diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index d1d7787ce2113f..e2c1719d13efea 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -65,6 +66,11 @@ static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0 static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */ +static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; +static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; + static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data clk_data; @@ -102,6 +108,17 @@ static u32 share_count_audio; static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_esai; + +static inline int clk_on_imx6ul(void) +{ + return of_machine_is_compatible("fsl,imx6ul"); +} + +static inline int clk_on_imx6ull(void) +{ + return of_machine_is_compatible("fsl,imx6ull"); +} static void __init imx6ul_clocks_init(struct device_node *ccm_node) { @@ -131,7 +148,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); - clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); + clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_PLL2, "pll2", "osc", base + 0x30, 0x1); clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); @@ -145,7 +162,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); - clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); /* Do not bypass PLLs initially */ clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]); @@ -220,13 +236,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); + clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); - clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); - clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux_bus("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); + clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); @@ -238,15 +254,23 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); + if (clk_on_imx6ull()) + clks[IMX6UL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels)); clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); - clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); - clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); + clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + } else { + clks[IMX6UL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); + clks[IMX6UL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); + } clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); + clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); @@ -276,13 +300,20 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); + if (clk_on_imx6ull()) { + clks[IMX6UL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); + clks[IMX6UL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); + } clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); - clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); + if (clk_on_imx6ul()) + clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); + else + clks[IMX6UL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3); clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); @@ -298,9 +329,15 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); - clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); - clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); - clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + } else { + clks[IMX6UL_CLK_DCP_CLK] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x68, 12); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x68, 12); + } clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); @@ -309,7 +346,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26); clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); - clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + if (clk_on_imx6ul()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); /* CCGR1 */ clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -328,6 +366,11 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); /* CCGR2 */ + if (clk_on_imx6ull()) { + clks[IMX6UL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x70, 0, &share_count_esai); + clks[IMX6UL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x70, 0, &share_count_esai); + clks[IMX6UL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x70, 0, &share_count_esai); + } clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); @@ -340,8 +383,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) /* CCGR3 */ clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); - clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); - clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + } else { + clks[IMX6UL_CLK_EPDC_ACLK] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4); + clks[IMX6UL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); + } clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); @@ -385,12 +433,16 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); - clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); + clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + } clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14); + if (clk_on_imx6ull()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18); clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20); clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24); clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26); @@ -427,9 +479,16 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) /* set perclk to from OSC */ clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]); + /* Set the UART parent if needed */ + if (uart_from_osc) + imx_clk_set_parent(clks[IMX6UL_CLK_UART_SEL], clks[IMX6UL_CLK_OSC]); + else + imx_clk_set_parent(clks[IMX6UL_CLK_UART_SEL], clks[IMX6UL_CLK_PLL3_80M]); + clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000); clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); + clk_set_rate(clks[IMX6UL_CLK_PLL3_PFD2], 320000000); /* keep all the clks on just for bringup */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) @@ -441,9 +500,23 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) } clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]); - clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + if (clk_on_imx6ul()) + clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + else + clk_set_parent(clks[IMX6UL_CLK_EPDC_PRE_SEL], clks[IMX6UL_CLK_PLL3_PFD2]); clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); + + /* Lower the AHB clock rate before changing the clock source. */ + imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); + + /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]); + + imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000); } CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index e7c7353a86fc62..ccc2119895220d 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -19,12 +20,16 @@ #include #include #include +#include #include "clk.h" static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_pxp; +static u32 share_count_enet1; +static u32 share_count_enet2; static struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -50,25 +55,25 @@ static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", - "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", }; static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk", - "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", }; static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", }; + "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", }; static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", - "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", }; + "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", }; static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_dram_533m_clk", "pll_enet_250m_clk", - "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd4_clk", }; static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", @@ -78,8 +83,8 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", - "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div", - "pll_video_main_clk", }; + "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div", + "pll_video_post_div", }; static const char *dram_phym_sel[] = { "pll_dram_main_clk", "dram_phym_alt_clk", }; @@ -90,7 +95,7 @@ static const char *dram_sel[] = { "pll_dram_main_clk", static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", "pll_sys_main_clk", "pll_enet_500m_clk", "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div", - "pll_video_main_clk", }; + "pll_video_post_div", }; static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", "pll_sys_main_clk", "pll_enet_500m_clk", @@ -112,62 +117,62 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk", static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk", "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk", - "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", }; + "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", }; static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk", - "pll_sys_pfd2_270m_clk", "pll_video_main_clk", + "pll_sys_pfd2_270m_clk", "pll_video_post_div", "pll_usb_main_clk", }; static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", - "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; + "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", }; static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", - "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; + "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", }; static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", - "pll_video_main_clk", "ext_clk_3", }; + "pll_video_post_div", "ext_clk_3", }; static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", - "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", + "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", - "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", + "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", - "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", + "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", - "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", + "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", "pll_enet_50m_clk", "pll_enet_25m_clk", - "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div", "ext_clk_4", }; static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", - "ext_clk_4", "pll_video_main_clk", }; + "ext_clk_4", "pll_video_post_div", }; static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", "pll_enet_50m_clk", "pll_enet_25m_clk", - "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div", "ext_clk_4", }; static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", - "ext_clk_4", "pll_video_main_clk", }; + "ext_clk_4", "pll_video_post_div", }; static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", "pll_enet_50m_clk", "pll_enet_125m_clk", - "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd3_clk", }; static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", @@ -178,7 +183,7 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", static const char *nand_sel[] = { "osc", "pll_sys_main_clk", "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk", "pll_enet_500m_clk", "pll_enet_250m_clk", - "pll_video_main_clk", }; + "pll_video_post_div", }; static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk", "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk", @@ -208,22 +213,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_enet_50m_clk", "pll_dram_533m_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", + "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", "pll_sys_pfd2_135m_clk", }; static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_enet_50m_clk", "pll_dram_533m_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", + "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", "pll_sys_pfd2_135m_clk", }; static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_enet_50m_clk", "pll_dram_533m_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", + "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", "pll_sys_pfd2_135m_clk", }; static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", "pll_enet_50m_clk", "pll_dram_533m_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", + "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", "pll_sys_pfd2_135m_clk", }; static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", @@ -283,27 +288,27 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_1", "ref_1m_clk", "pll_video_post_div", }; static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_1", "ref_1m_clk", "pll_video_post_div", }; static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_2", "ref_1m_clk", "pll_video_post_div", }; static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_2", "ref_1m_clk", "pll_video_post_div", }; static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_3", "ref_1m_clk", "pll_video_post_div", }; static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", - "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; + "ext_clk_3", "ref_1m_clk", "pll_video_post_div", }; static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", "pll_sys_main_120m_clk", "pll_dram_533m_clk", @@ -312,23 +317,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", "pll_sys_main_120m_clk", "pll_dram_533m_clk", - "pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk", + "pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk", "pll_sys_pfd7_clk", }; static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", - "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", + "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", }; static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", - "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", + "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", }; static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", - "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", + "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", }; static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", - "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", + "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", }; static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", @@ -343,12 +348,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", "pll_sys_main_120m_clk", "pll_dram_533m_clk", - "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", }; static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", "pll_sys_main_120m_clk", "pll_dram_533m_clk", - "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", + "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", }; static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", @@ -362,13 +367,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", - "pll_audio_post_div", "pll_video_main_clk", "ckil", }; + "pll_audio_post_div", "pll_video_post_div", "ckil", }; static const char *lvds1_sel[] = { "pll_arm_main_clk", "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", - "pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk", + "pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk", "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", "pll_dram_main_clk", }; @@ -386,7 +391,7 @@ static int const clks_init_on[] __initconst = { IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, - IMX7D_AHB_CHANNEL_ROOT_CLK, + IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK, }; static struct clk_onecell_data clk_data; @@ -424,11 +429,11 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); - clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_dram_main", "osc", base + 0x70, 0x7f); + clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f); clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1); clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0); - clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f); - clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f); + clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f); + clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f); clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); @@ -437,23 +442,22 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); - clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); - clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); - clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); - clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); - clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); - clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); - clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); - clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); + clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13); clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); - clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); - clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); + clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_test_div", base + 0xf0, 13); + clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_test_div", base + 0x130, 13); - clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", + clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); + clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_bypass", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); - clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", + clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_main_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_bypass", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock); + clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_main_clk", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); @@ -523,7 +527,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); - clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); + clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); @@ -718,14 +722,15 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); - clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); + clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider_flags("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider2("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3); - clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); + clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider_flags("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6, CLK_OPS_PARENT_ENABLE); clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); - clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); - clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); + clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_divider2("nand_usdhc_root_clk", "nand_usdhc_pre_div", base + 0x8980, 0, 6); + clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_divider_flags("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6, CLK_OPS_PARENT_ENABLE); + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2); clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3); clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); @@ -736,7 +741,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); - clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); + clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6); clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); @@ -789,21 +794,23 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); - clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); + clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0); clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate4("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0); - clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); - clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); - clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk", "ahb_post_div", base + 0x4200, 0); + clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0); + clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0); clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); - clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); + clks[IMX7D_MU_ROOT_CLK] = imx_clk_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0); + clks[IMX7D_SEMA4_HS_ROOT_CLK] = imx_clk_gate4("sema4_hs_root_clk", "ipg_root_clk", base + 0x4280, 0); + clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0); + clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0); clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); @@ -812,6 +819,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); + clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1); + clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1); + clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2); + clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2); clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1); clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1); clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2); @@ -819,13 +830,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3); clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3); clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); - clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0); - clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0); - clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0); - clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); - clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); - clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0); + clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2_flags("nand_root_clk", "nand_post_div", base + 0x4140, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); @@ -867,7 +873,12 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); + clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0); + clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); + clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); + clks[IMX7D_PXP_IPG_CLK] = imx_clk_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp); + clks[IMX7D_PXP_AXI_CLK] = imx_clk_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp); clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); @@ -886,13 +897,57 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); + if (imx_src_is_m4_enabled()) { + imx_clk_set_parent(clks[IMX7D_ARM_M4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + imx_clk_prepare_enable(clks[IMX7D_ARM_M4_ROOT_CLK]); + } + + imx_clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); + imx_clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); + imx_clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); + imx_clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); + imx_clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); + imx_clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); + /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ - clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); + imx_clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); - /* set uart module clock's parent clock source that must be great then 80MHz */ - clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); + /* + * init enet clock source: + * AXI clock source is 250Mhz + * Phy refrence clock is 25Mhz + * 1588 time clock source is 100Mhz + */ + imx_clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); + imx_clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 267000000); + imx_clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]); - imx_register_uart_clocks(uart_clks); + /* set pcie root's parent clk source */ + imx_clk_set_parent(clks[IMX7D_PCIE_CTRL_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); + imx_clk_set_parent(clks[IMX7D_PCIE_PHY_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); + + /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */ + clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); + clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1); + + /* set parent of EPDC pixel clock */ + imx_clk_set_parent(clks[IMX7D_EPDC_PIXEL_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_CLK]); + /* set lcdif pixel root clock source to get the required 33Mhz clock */ + imx_clk_set_parent(clks[IMX7D_LCDIF_PIXEL_ROOT_SRC], clks[IMX7D_PLL_VIDEO_POST_DIV]); + + imx_clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]); + + /* set parent of SIM1 root clock */ + imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); + + imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); + imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); + imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000); + + imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c new file mode 100644 index 00000000000000..0de0b161a1e38e --- /dev/null +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char *pll_pre_sels[] = { "osc", "firc", }; +static const char *spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", }; +static const char *spll_sels[] = { "spll", "spll_pfd_sel", }; +static const char *apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", }; +static const char *apll_sels[] = { "apll", "apll_pfd_sel", }; +static const char *sys_sels[] = { "dummy", "osc", "sirc", "firc", "ckil", "apll_sel", "spll_sel", "upll", }; +static const char *arm_sels[] = { "core_div", "hsrun_core", }; +static const char *ddr_sels[] = { "apll_pfd_sel", "upll", }; +static const char *nic_sels[] = { "firc", "ddr_div", }; +static const char *periph_plat_sels[] = { "dummy", "nic1_bus", "nic1_div", "ddr_div", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; +/* the dummy in only a space holder of spll_bus clk */ +static const char *periph_slow_sels[] = { "dummy", "osc", "dummy", "firc", "ckil", "nic1_bus", "nic1_div", "dummy", }; +static struct clk *clks[IMX7ULP_CLK_END]; +static struct clk_onecell_data clk_data; + +static const char *cm4_pll_pre_sels[] = { "cm4_osc", "cm4_firc", }; +static const char *cm4_spll_pfd_sels[] = { "cm4_spll_pfd0", "cm4_spll_pfd1", "cm4_spll_pfd2", "cm4_spll_pfd3", }; +static const char *cm4_spll_sels[] = { "cm4_spll_vco", "cm4_spll_pfd_sel", }; +static const char *cm4_apll_pfd_sels[] = { "cm4_apll_pfd0", "cm4_apll_pfd1", "cm4_apll_pfd2", "cm4_apll_pfd3", }; +static const char *cm4_apll_sels[] = { "cm4_apll_vco_post_div2", "cm4_apll_pfd_sel", }; +static const char *cm4_sys_sels[] = { "cm4_dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_apll_sel", "cm4_spll_sel", "cm4_dummy", }; +static const char *cm4_periph_slow_sels[] = { "cm4_dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_bus_div", "cm4_spll_pfd2", "cm4_apll_pfd0_pre_div", }; +static const char *scg0_clkout_sels[] = { "dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_apll_sel", "cm4_spll_sel", "dummy"}; +static struct clk *clks_cm4[IMX7ULP_CM4_CLK_END]; +static struct clk_onecell_data clk_data_cm4; + + +static int const clks_init_on[] __initconst = { + IMX7ULP_CLK_BUS_DIV, + IMX7ULP_CLK_ARM, + IMX7ULP_CLK_NIC0_DIV, + IMX7ULP_CLK_NIC1_DIV, + IMX7ULP_CLK_NIC1_BUS_DIV, + IMX7ULP_CLK_MMDC, + IMX7ULP_CLK_RGPIO2P1, + IMX7ULP_CLK_PCTLC, + IMX7ULP_CLK_PCTLD, + IMX7ULP_CLK_PCTLE, + IMX7ULP_CLK_PCTLF, +}; + +static void __init imx7ulp_clocks_init(struct device_node *scg_node) +{ + struct device_node *np; + void __iomem *base; + int i; + + clks[IMX7ULP_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + + clks[IMX7ULP_CLK_CKIL] = of_clk_get_by_name(scg_node, "ckil"); + clks[IMX7ULP_CLK_OSC] = of_clk_get_by_name(scg_node, "osc"); + clks[IMX7ULP_CLK_SIRC] = of_clk_get_by_name(scg_node, "sirc"); + clks[IMX7ULP_CLK_FIRC] = of_clk_get_by_name(scg_node, "firc"); + clks[IMX7ULP_CLK_MIPI_PLL] = of_clk_get_by_name(scg_node, "mpll"); + clks[IMX7ULP_CLK_UPLL] = of_clk_get_by_name(scg_node, "upll"); + + np = scg_node; + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_mux("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels)); + clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels)); + /* name parent_name reg shift width */ + clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_divider("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3); + clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_divider("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3); + /* name parent_name base*/ + clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600); + clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500); + + /* SPLL PFDs */ + clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0); + clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1); + clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2); + clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3); + /* APLL PFDs */ + clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50C, 0); + clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50C, 1); + clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50C, 2); + clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50C, 3); + + clks[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_mux("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels)); + clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_mux("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels)); + + clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels)); + clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_mux("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels)); + + clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_mux_glitchless("sys_sel", base + 0x14, 24, 4, sys_sels, ARRAY_SIZE(sys_sels)); + clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_mux_glitchless("hsrun_sys_sel", base + 0x1c, 24, 4, sys_sels, ARRAY_SIZE(sys_sels)); + clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); + clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_mux("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels)); + + clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_divider_flags("core_div", "sys_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); + clks[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_divider_flags("hsrun_core", "hsrun_sys_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); + clks[IMX7ULP_CLK_PLAT_DIV] = imx_clk_divider("plat_div", "core_div", base + 0x14, 12, 4); + /* Fake mux */ + clks[IMX7ULP_CLK_ARM] = imx_clk_mux_glitchless("arm", base + 0x14, 5, 1, arm_sels, ARRAY_SIZE(arm_sels)); + + clks[IMX7ULP_CLK_DDR_DIV] = clk_register_divider(NULL, "ddr_div", "ddr_sel", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x30, 0, 3, CLK_DIVIDER_ONE_BASED, &imx_ccm_lock); + clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_divider("nic0_div", "nic_sel", base + 0x40, 24, 4); + clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_divider("gpu_div", "nic0_div", base + 0x40, 20, 4); + clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_divider("nic1_div", "nic0_div", base + 0x40, 16, 4); + clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_divider("nic1_bus", "nic1_div", base + 0x40, 4, 4); + + /* PCC2 */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX7ULP_CLK_DMA1] = imx_clk_gate("dma1", "nic1_bus", base + 0x20, 30); + clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_gate("gpio", "nic1_bus", base + 0x3c, 30); + clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_gate("dma_mux1", "nic1_bus", base + 0x84, 30); + clks[IMX7ULP_CLK_SNVS] = imx_clk_gate("snvs", "nic1_bus", base + 0x8c, 30); + clks[IMX7ULP_CLK_CAAM] = imx_clk_gate("caam", "nic1_div", base + 0x90, 30); + clks[IMX7ULP_CLK_LPTPM4] = imx_clk_composite("lptpm4", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x94); + clks[IMX7ULP_CLK_LPTPM5] = imx_clk_composite("lptmp5", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x98); + clks[IMX7ULP_CLK_LPIT1] = imx_clk_composite("lpit1", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x9C); + clks[IMX7ULP_CLK_LPSPI2] = imx_clk_composite("lpspi2", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xA4); + clks[IMX7ULP_CLK_LPSPI3] = imx_clk_composite("lpspi3", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xA8); + clks[IMX7ULP_CLK_LPI2C4] = imx_clk_composite("lpi2c4", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xAC); + clks[IMX7ULP_CLK_LPI2C5] = imx_clk_composite("lpi2c5", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xB0); + clks[IMX7ULP_CLK_LPUART4] = imx_clk_composite("lpuart4", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xB4); + clks[IMX7ULP_CLK_LPUART5] = imx_clk_composite("lpuart5", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xB8); + clks[IMX7ULP_CLK_FLEXIO1] = imx_clk_composite("flexio", periph_slow_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0xC4); + clks[IMX7ULP_CLK_USB0] = imx_clk_composite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xCC); + clks[IMX7ULP_CLK_USB1] = imx_clk_composite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xD0); + clks[IMX7ULP_CLK_USB_PHY] = imx_clk_gate("usb_phy", "nic1_bus", base + 0xD4, 30); + clks[IMX7ULP_CLK_USDHC0] = imx_clk_composite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xDC); + clks[IMX7ULP_CLK_USDHC1] = imx_clk_composite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xE0); + clks[IMX7ULP_CLK_WDG1] = imx_clk_composite("wdg1", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, true, true, base + 0xF4); + clks[IMX7ULP_CLK_WDG2] = imx_clk_composite("sdg2", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, true, true, base + 0x10C); + + /* PCC3 */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX7ULP_CLK_LPTPM6] = imx_clk_composite("lptpm6", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x84); + clks[IMX7ULP_CLK_LPTPM7] = imx_clk_composite("lptpm7", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x88); + clks[IMX7ULP_CLK_LPI2C6] = imx_clk_composite("lpi2c6", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x90); + clks[IMX7ULP_CLK_LPI2C7] = imx_clk_composite("lpi2c7", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x94); + clks[IMX7ULP_CLK_LPUART6] = imx_clk_composite("lpuart6", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x98); + clks[IMX7ULP_CLK_LPUART7] = imx_clk_composite("lpuart7", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0x9C); + clks[IMX7ULP_CLK_VIU] = imx_clk_gate("viu", "nic1_div", base + 0xA0, 30); + clks[IMX7ULP_CLK_DSI] = imx_clk_composite("dsi", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, true, true, base + 0xA4); + clks[IMX7ULP_CLK_LCDIF] = imx_clk_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xA8); + clks[IMX7ULP_CLK_MMDC] = imx_clk_gate("mmdc", "nic1_div", base + 0xAC, 30); + clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); + clks[IMX7ULP_CLK_PCTLC] = imx_clk_composite("pctlc", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xb8); + clks[IMX7ULP_CLK_PCTLD] = imx_clk_composite("pctld", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xbc); + clks[IMX7ULP_CLK_PCTLE] = imx_clk_composite("pctle", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xc0); + clks[IMX7ULP_CLK_PCTLF] = imx_clk_composite("pctlf", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xc4); + clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); + + imx_check_clocks(clks, ARRAY_SIZE(clks)); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(scg_node, of_clk_src_onecell_get, &clk_data); + + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + imx_clk_prepare_enable(clks[clks_init_on[i]]); + imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]); + imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]); + + /* make sure PFD is gated before setting its rate */ + clk_prepare_enable(clks[IMX7ULP_CLK_APLL_PFD2]); + clk_disable_unprepare(clks[IMX7ULP_CLK_APLL_PFD2]); + imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000); + + pr_info("i.MX7ULP clock tree init done.\n"); +} + +CLK_OF_DECLARE(imx7ulp, "fsl,imx7ulp-scg1", imx7ulp_clocks_init); + +static struct clk_div_table apll_pfd0_div_table[] = { + { .val = 1, .div = 1, }, + { .val = 0, .div = 2, }, + { /* sentinel */ } +}; + +static u32 share_count_sai0; +static u32 share_count_sai1; + +static void __init imx7ulp_cm4_clocks_init(struct device_node *scg_node) +{ + struct device_node *np, *np_sim; + void __iomem *base; + void __iomem *base_sim; + + clks_cm4[IMX7ULP_CM4_CLK_DUMMY] = imx_clk_fixed("cm4_dummy", 0); + + clks_cm4[IMX7ULP_CM4_CLK_CKIL] = of_clk_get_by_name(scg_node, "cm4_ckil"); + clks_cm4[IMX7ULP_CM4_CLK_OSC] = of_clk_get_by_name(scg_node, "cm4_osc"); + clks_cm4[IMX7ULP_CM4_CLK_SIRC] = of_clk_get_by_name(scg_node, "cm4_sirc"); + clks_cm4[IMX7ULP_CM4_CLK_FIRC] = of_clk_get_by_name(scg_node, "cm4_firc"); + + np = scg_node; + base = of_iomap(np, 0); + WARN_ON(!base); + + np_sim = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-sim"); + base_sim = of_iomap(np_sim, 0); + WARN_ON(!base_sim); + + clks_cm4[IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL] = imx_clk_mux("cm4_spll_vco_pre_sel", base + 0x608, 0, 1, cm4_pll_pre_sels, ARRAY_SIZE(cm4_pll_pre_sels)); + clks_cm4[IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL] = imx_clk_mux("cm4_apll_vco_pre_sel", base + 0x508, 0, 1, cm4_pll_pre_sels, ARRAY_SIZE(cm4_pll_pre_sels)); + /* name parent_name reg shift width */ + clks_cm4[IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV] = imx_clk_divider("cm4_spll_vco_pre_div", "cm4_spll_vco_pre_sel", base + 0x608, 8, 3); + clks_cm4[IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV] = imx_clk_divider("cm4_apll_vco_pre_div", "cm4_apll_vco_pre_sel", base + 0x508, 8, 3); + /* name parent_name base*/ + clks_cm4[IMX7ULP_CM4_CLK_SPLL_VCO] = imx_clk_pllv5("cm4_spll_vco", "cm4_spll_vco_pre_div", base + 0x600); + clks_cm4[IMX7ULP_CM4_CLK_APLL_VCO] = imx_clk_pllv4("cm4_apll_vco", "cm4_apll_vco_pre_div", base + 0x500); + + clks_cm4[IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1] = imx_clk_divider("cm4_apll_vco_post_div1", "cm4_apll_vco", base + 0x508, 24, 4); + clks_cm4[IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2] = imx_clk_divider("cm4_apll_vco_post_div2", "cm4_apll_vco_post_div1", base + 0x508, 28, 4); + + /* SPLL PFDs */ + clks_cm4[IMX7ULP_CM4_CLK_SPLL_PFD0] = imx_clk_pfdv2("cm4_spll_pfd0", "cm4_spll_vco", base + 0x60C, 0); + clks_cm4[IMX7ULP_CM4_CLK_SPLL_PFD1] = imx_clk_pfdv2("cm4_spll_pfd1", "cm4_spll_vco", base + 0x60C, 1); + clks_cm4[IMX7ULP_CM4_CLK_SPLL_PFD2] = imx_clk_pfdv2("cm4_spll_pfd2", "cm4_spll_vco", base + 0x60C, 2); + clks_cm4[IMX7ULP_CM4_CLK_SPLL_PFD3] = imx_clk_pfdv2("cm4_spll_pfd3", "cm4_spll_vco", base + 0x60C, 3); + /* APLL PFDs */ + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD0] = imx_clk_pfdv2("cm4_apll_pfd0", "cm4_apll_vco", base + 0x50C, 0); + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD1] = imx_clk_pfdv2("cm4_apll_pfd1", "cm4_apll_vco", base + 0x50C, 1); + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD2] = imx_clk_pfdv2("cm4_apll_pfd2", "cm4_apll_vco", base + 0x50C, 2); + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD3] = imx_clk_pfdv2("cm4_apll_pfd3", "cm4_apll_vco", base + 0x50C, 3); + + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV] = clk_register_divider_table(NULL, "cm4_apll_pfd0_pre_div", "cm4_apll_pfd0", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base_sim + 0x2c, 5, 1, 0, apll_pfd0_div_table, &imx_ccm_lock); + + clks_cm4[IMX7ULP_CM4_CLK_SPLL_PFD_SEL] = imx_clk_mux("cm4_spll_pfd_sel", base + 0x608, 14, 2, cm4_spll_pfd_sels, ARRAY_SIZE(cm4_spll_pfd_sels)); + clks_cm4[IMX7ULP_CM4_CLK_APLL_PFD_SEL] = imx_clk_mux("cm4_apll_pfd_sel", base + 0x508, 14, 2, cm4_apll_pfd_sels, ARRAY_SIZE(cm4_apll_pfd_sels)); + + clks_cm4[IMX7ULP_CM4_CLK_SPLL_SEL] = imx_clk_mux("cm4_spll_sel", base + 0x608, 1, 1, cm4_spll_sels, ARRAY_SIZE(cm4_spll_sels)); + clks_cm4[IMX7ULP_CM4_CLK_APLL_SEL] = imx_clk_mux("cm4_apll_sel", base + 0x508, 1, 1, cm4_apll_sels, ARRAY_SIZE(cm4_apll_sels)); + + clks_cm4[IMX7ULP_CM4_CLK_SYS_SEL] = imx_clk_mux("cm4_sys_sel", base + 0x14, 24, 4, cm4_sys_sels, ARRAY_SIZE(cm4_sys_sels)); + + clks_cm4[IMX7ULP_CM4_CLK_CORE_DIV] = imx_clk_divider("cm4_core_div", "cm4_sys_sel", base + 0x14, 16, 4); + clks_cm4[IMX7ULP_CM4_CLK_PLAT_DIV] = imx_clk_divider("cm4_plat_div", "cm4_core_div", base + 0x14, 12, 4); + clks_cm4[IMX7ULP_CM4_CLK_BUS_DIV] = imx_clk_divider("cm4_bus_div", "cm4_core_div", base + 0x14, 4, 4); + clks_cm4[IMX7ULP_CM4_CLK_SLOW_DIV] = imx_clk_divider("cm4_slow_div", "cm4_core_div", base + 0x14, 0, 4); + + clks_cm4[IMX7ULP_CLK_SCG0_CLKOUT] = imx_clk_mux("scg0_clkout", base + 0x20, 24, 4, scg0_clkout_sels, ARRAY_SIZE(scg0_clkout_sels)); + + /* PCG0 */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc0"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks_cm4[IMX7ULP_CM4_CLK_SAI0_SEL] = imx_clk_mux("cm4_sai0_sel", base + 0xDC, 24, 3, cm4_periph_slow_sels, ARRAY_SIZE(cm4_periph_slow_sels)); + clks_cm4[IMX7ULP_CM4_CLK_SAI0_DIV] = imx_clk_divider("cm4_sai0_div", "cm4_sai0_sel", base + 0xDC, 0, 8); + clks_cm4[IMX7ULP_CM4_CLK_SAI0_ROOT] = imx_clk_gate2_shared("cm4_sai0_root", "cm4_sai0_div", base + 0xDC, 30, &share_count_sai0); + clks_cm4[IMX7ULP_CM4_CLK_SAI0_IPG] = imx_clk_gate2_shared("cm4_sai0_ipg", "cm4_bus_div", base + 0xDC, 30, &share_count_sai0); + + /* PCG1 */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc1"); + base = of_iomap(np, 0); + WARN_ON(!base); + + + clks_cm4[IMX7ULP_CM4_CLK_SAI1_SEL] = imx_clk_mux("cm4_sai1_sel", base + 0xA8, 24, 3, cm4_periph_slow_sels, ARRAY_SIZE(cm4_periph_slow_sels)); + clks_cm4[IMX7ULP_CM4_CLK_SAI1_DIV] = imx_clk_divider("cm4_sai1_div", "cm4_sai1_sel", base + 0xA8, 0, 8); + clks_cm4[IMX7ULP_CM4_CLK_SAI1_ROOT] = imx_clk_gate2_shared("cm4_sai1_root", "cm4_sai1_div", base + 0xA8, 30, &share_count_sai1); + clks_cm4[IMX7ULP_CM4_CLK_SAI1_IPG] = imx_clk_gate2_shared("cm4_sai1_ipg", "cm4_bus_div", base + 0xA8, 30, &share_count_sai1); + + imx_check_clocks(clks_cm4, ARRAY_SIZE(clks_cm4)); + + clk_data_cm4.clks = clks_cm4; + clk_data_cm4.clk_num = ARRAY_SIZE(clks_cm4); + of_clk_add_provider(scg_node, of_clk_src_onecell_get, &clk_data_cm4); + + imx_clk_prepare_enable(clks_cm4[IMX7ULP_CM4_CLK_SYS_SEL]); + + pr_info("i.MX7ULP cm4 clock tree init.\n"); +} +CLK_OF_DECLARE(imx7ulp_cm4, "fsl,imx7ulp-scg0", imx7ulp_cm4_clocks_init); diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 04a3e78ea1bc32..e29bd792522fb6 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -11,11 +11,14 @@ */ #include +#include #include #include #include +#include #include "clk.h" + /** * struct clk_pfd - IMX PFD clock * @clk_hw: clock source @@ -38,20 +41,57 @@ struct clk_pfd { #define CLR 0x8 #define OTG 0xc -static int clk_pfd_enable(struct clk_hw *hw) +static void clk_pfd_do_hardware(struct clk_pfd *pfd, bool enable) +{ + if (enable) + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + else + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); +} + +static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable) { struct clk_pfd *pfd = to_clk_pfd(hw); - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pfd_do_hardware(pfd, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_pfd_do_hardware(pfd, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pfd_do_hardware(pfd, enable); + } +} + +static int clk_pfd_enable(struct clk_hw *hw) +{ + clk_pfd_do_shared_clks(hw, true); return 0; } static void clk_pfd_disable(struct clk_hw *hw) { - struct clk_pfd *pfd = to_clk_pfd(hw); - - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); + clk_pfd_do_shared_clks(hw, false); } static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c new file mode 100644 index 00000000000000..b74f0809a03b9f --- /dev/null +++ b/drivers/clk/imx/clk-pfdv2.c @@ -0,0 +1,172 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +/** + * struct clk_pfdv2 - IMX PFD clock + * @clk_hw: clock source + * @reg: PFD register address + * @idx: the index of PFD encoded in the register + * + */ + +struct clk_pfdv2 { + struct clk_hw hw; + void __iomem *reg; + u8 idx; +}; + +#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw) + +static int clk_pfd_enable(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + u32 val; + + val = readl_relaxed(pfd->reg); + val &= ~(1 << ((pfd->idx + 1) * 8 - 1)); + writel_relaxed(val, pfd->reg); + + return 0; +} + +static void clk_pfd_disable(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + u32 val; + + val = readl_relaxed(pfd->reg); + val |= 1 << ((pfd->idx + 1) * 8 - 1); + writel_relaxed(val, pfd->reg); +} + +static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + u64 tmp = parent_rate; + u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; + + /* + * The reset value of pfd field is zero, so add one to avoid div + * by zero, optimize this late. + */ + if (!frac) + frac += 1; + + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u64 tmp = *prate; + u8 frac; + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + tmp = *prate; + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + u64 tmp = parent_rate; + u32 val; + u8 frac; + + /* PFD can NOT change rate without gating */ + WARN_ON(!(readl_relaxed(pfd->reg) & + (1 << ((pfd->idx + 1) * 8 - 1)))); + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + + val = readl_relaxed(pfd->reg); + val &= ~(0x3f << (pfd->idx * 8)); + val |= frac << (pfd->idx * 8); + writel_relaxed(val, pfd->reg); + + return 0; +} + +static int clk_pfd_is_enabled(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + + if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) + return 0; + + return 1; +} + +static const struct clk_ops clk_pfdv2_ops = { + .enable = clk_pfd_enable, + .disable = clk_pfd_disable, + .recalc_rate = clk_pfd_recalc_rate, + .round_rate = clk_pfd_round_rate, + .set_rate = clk_pfd_set_rate, + .is_enabled = clk_pfd_is_enabled, +}; + +struct clk *imx_clk_pfdv2(const char *name, const char *parent_name, + void __iomem *reg, u8 idx) +{ + struct clk_pfdv2 *pfd; + struct clk *clk; + struct clk_init_data init; + + pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); + if (!pfd) + return ERR_PTR(-ENOMEM); + + pfd->reg = reg; + pfd->idx = idx; + + init.name = name; + init.ops = &clk_pfdv2_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pfd->hw.init = &init; + + clk = clk_register(NULL, &pfd->hw); + if (IS_ERR(clk)) + kfree(pfd); + + return clk; +} diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 7a6acc3e4a927c..d8b481936f20cd 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -11,15 +11,20 @@ */ #include -#include +#include #include #include #include #include +#include #include "clk.h" -#define PLL_NUM_OFFSET 0x10 -#define PLL_DENOM_OFFSET 0x20 +#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x20 +#define PLL_AV_IMX7_NUM_OFFSET 0x20 +#define PLL_AV_IMX7_DENOM_OFFSET 0x30 +#define PLL_PLL2_NUM_OFFSET 0x20 +#define PLL_PLL2_DENOM_OFFSET 0x30 #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) @@ -45,6 +50,8 @@ struct clk_pllv3 { u32 div_mask; u32 div_shift; unsigned long ref_clock; + u32 num_offset; + u32 denom_offset; }; #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) @@ -64,38 +71,79 @@ static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) break; if (time_after(jiffies, timeout)) break; - usleep_range(50, 500); } while (1); return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; } -static int clk_pllv3_prepare(struct clk_hw *hw) +static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); + int ret; u32 val; val = readl_relaxed(pll->base); - if (pll->powerup_set) - val |= pll->power_bit; - else - val &= ~pll->power_bit; - writel_relaxed(val, pll->base); + if (enable) { + if (pll->powerup_set) + val |= pll->power_bit; + else + val &= ~pll->power_bit; + writel_relaxed(val, pll->base); + + ret = clk_pllv3_wait_lock(pll); + if (ret) + return ret; + } else { + if (pll->powerup_set) + val &= ~pll->power_bit; + else + val |= pll->power_bit; + writel_relaxed(val, pll->base); + } - return clk_pllv3_wait_lock(pll); + return 0; } -static void clk_pllv3_unprepare(struct clk_hw *hw) +static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable) { - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pllv3_do_hardware(hw, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + clk_pllv3_do_hardware(hw, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pllv3_do_hardware(hw, enable); + } +} - val = readl_relaxed(pll->base); - if (pll->powerup_set) - val &= ~pll->power_bit; - else - val |= pll->power_bit; - writel_relaxed(val, pll->base); +static int clk_pllv3_prepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, true); + + return 0; +} + +static void clk_pllv3_unprepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, false); } static int clk_pllv3_is_prepared(struct clk_hw *hw) @@ -215,8 +263,8 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); - u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); + u32 mfn = readl_relaxed(pll->base + pll->num_offset); + u32 mfd = readl_relaxed(pll->base + pll->denom_offset); u32 div = readl_relaxed(pll->base) & pll->div_mask; u64 temp64 = (u64)parent_rate; @@ -277,8 +325,8 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); - writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); - writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); + writel_relaxed(mfn, pll->base + pll->num_offset); + writel_relaxed(mfd, pll->base + pll->denom_offset); return clk_pllv3_wait_lock(pll); } @@ -307,6 +355,28 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; +static unsigned long clk_pllv3_pll2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(hw); + u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; + u32 mfn = readl_relaxed(pll->base + pll->num_offset); + u32 mfd = readl_relaxed(pll->base + pll->denom_offset); + u64 temp64 = (u64)parent_rate; + + temp64 *= mfn; + do_div(temp64, mfd); + + return (parent_rate * ((div == 1) ? 22 : 20)) + (u32)temp64; +} + +static const struct clk_ops clk_pllv3_pll2_ops = { + .prepare = clk_pllv3_prepare, + .unprepare = clk_pllv3_unprepare, + .is_prepared = clk_pllv3_is_prepared, + .recalc_rate = clk_pllv3_pll2_recalc_rate, +}; + struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -321,17 +391,28 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, return ERR_PTR(-ENOMEM); pll->power_bit = BM_PLL_POWER; + pll->num_offset = PLL_NUM_OFFSET; + pll->denom_offset = PLL_DENOM_OFFSET; switch (type) { case IMX_PLLV3_SYS: ops = &clk_pllv3_sys_ops; break; + case IMX_PLLV3_PLL2: + pll->num_offset = PLL_PLL2_NUM_OFFSET; + pll->denom_offset = PLL_PLL2_DENOM_OFFSET; + ops = &clk_pllv3_pll2_ops; + break; case IMX_PLLV3_USB_VF610: pll->div_shift = 1; case IMX_PLLV3_USB: ops = &clk_pllv3_ops; pll->powerup_set = true; break; + case IMX_PLLV3_AV_IMX7: + pll->num_offset = PLL_AV_IMX7_NUM_OFFSET; + pll->denom_offset = PLL_AV_IMX7_DENOM_OFFSET; + /* fall through */ case IMX_PLLV3_AV: ops = &clk_pllv3_av_ops; break; diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c new file mode 100644 index 00000000000000..4f4c02bd6d4e4a --- /dev/null +++ b/drivers/clk/imx/clk-pllv4.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include "clk.h" + +#define PLL_EN BIT(0) +#define BP_PLL_DIV 16 +#define BM_PLL_DIV (0x7f << 16) +#define PLL_CFG_OFFSET 0x08 +#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x14 + +struct clk_pllv4 { + struct clk_hw hw; + void __iomem *base; + u32 div_mask; + u32 div_shift; + u32 cfg_offset; + u32 num_offset; + u32 denom_offset; +}; + +#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw) + +static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pllv4 *pll = to_clk_pllv4(hw); + u32 mfn = readl_relaxed(pll->base + pll->num_offset); + u32 mfd = readl_relaxed(pll->base + pll->denom_offset); + u32 div = (readl_relaxed(pll->base + pll->cfg_offset) + & pll->div_mask) >> pll->div_shift; + u64 temp64 = (u64)parent_rate; + + temp64 *= mfn; + do_div(temp64, mfd); + + return (parent_rate * div) + (u32)temp64; +} + +static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + unsigned long min_rate = parent_rate * 16; + unsigned long max_rate = parent_rate * 30; + u32 div; + u32 mfn, mfd = 1000000; + u64 temp64; + + if (rate > max_rate) + rate = max_rate; + else if (rate < min_rate) + rate = min_rate; + + div = rate / parent_rate; + temp64 = (u64) (rate - div * parent_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + return parent_rate * div + parent_rate / mfd * mfn; +} + +static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv4 *pll = to_clk_pllv4(hw); + unsigned long min_rate = parent_rate * 16; + unsigned long max_rate = parent_rate * 30; + u32 val, div; + u32 mfn, mfd = 1000000; + u64 temp64; + + if (rate < min_rate || rate > max_rate) + return -EINVAL; + + div = rate / parent_rate; + temp64 = (u64) (rate - div * parent_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + val = readl_relaxed(pll->base + pll->cfg_offset); + val &= ~pll->div_mask; + val |= (div << pll->div_shift); + writel_relaxed(val, pll->base + pll->cfg_offset); + writel_relaxed(mfn, pll->base + pll->num_offset); + writel_relaxed(mfd, pll->base + pll->denom_offset); + + return 0; +} + +static int clk_pllv4_enable(struct clk_hw *hw) +{ + u32 val; + struct clk_pllv4 *pll = to_clk_pllv4(hw); + + val = readl_relaxed(pll->base); + val |= PLL_EN; + writel_relaxed(val, pll->base); + + return 0; +} + +static void clk_pllv4_disable(struct clk_hw *hw) +{ + u32 val; + struct clk_pllv4 *pll = to_clk_pllv4(hw); + + val = readl_relaxed(pll->base); + val &= ~PLL_EN; + writel_relaxed(val, pll->base); +} + +static int clk_pllv4_is_enabled(struct clk_hw *hw) +{ + struct clk_pllv4 *pll = to_clk_pllv4(hw); + + if (readl_relaxed(pll->base) & PLL_EN) + return 0; + + return 1; +} + +static const struct clk_ops clk_pllv4_ops = { + .recalc_rate = clk_pllv4_recalc_rate, + .round_rate = clk_pllv4_round_rate, + .set_rate = clk_pllv4_set_rate, + .enable = clk_pllv4_enable, + .disable = clk_pllv4_disable, + .is_enabled = clk_pllv4_is_enabled, +}; + +struct clk *imx_clk_pllv4(const char *name, const char *parent_name, + void __iomem *base) +{ + struct clk_pllv4 *pll; + struct clk *clk; + struct clk_init_data init; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->div_mask = BM_PLL_DIV; + pll->div_shift = BP_PLL_DIV; + pll->cfg_offset = PLL_CFG_OFFSET; + pll->num_offset = PLL_NUM_OFFSET; + pll->denom_offset = PLL_DENOM_OFFSET; + + init.name = name; + init.ops = &clk_pllv4_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk-pllv5.c b/drivers/clk/imx/clk-pllv5.c new file mode 100644 index 00000000000000..1bd3543dff2e6d --- /dev/null +++ b/drivers/clk/imx/clk-pllv5.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include "clk.h" + +#define PLL_EN BIT(0) +#define BP_PLL_DIV 16 +#define BM_PLL_DIV (0x7 << 16) +#define PLL_CFG_OFFSET 0x08 + +struct clk_pllv5 { + struct clk_hw hw; + void __iomem *base; + u32 div_mask; + u32 div_shift; + u32 cfg_offset; +}; + +#define to_clk_pllv5(__hw) container_of(__hw, struct clk_pllv5, hw) + +static unsigned long clk_pllv5_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pllv5 *pll = to_clk_pllv5(hw); + u32 val = (readl_relaxed(pll->base + pll->cfg_offset) & pll->div_mask) >> pll->div_shift; + u32 div; + + switch (val) { + case 1: + div = 15; + break; + case 2: + div = 16; + break; + case 3: + div = 20; + break; + case 4: + div = 22; + break; + case 5: + div = 25; + break; + case 6: + div = 30; + break; + default: + div = 20; + break; + } + + return parent_rate * div; +} + +static long clk_pllv5_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + u32 div; + + div = rate / parent_rate; + + if (div == 15 || div == 16 || + div == 20 || div == 22 || + div == 25 || div == 30) + return parent_rate * div; + else + return parent_rate * 20; +} + +static int clk_pllv5_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv5 *pll = to_clk_pllv5(hw); + unsigned long min_rate = parent_rate * 15; + unsigned long max_rate = parent_rate * 30; + u32 val, div, reg; + + if (rate < min_rate || rate > max_rate) + return -EINVAL; + + div = rate / parent_rate; + + switch (div) { + case 15: + val = 1; + break; + case 16: + val = 2; + break; + case 20: + val = 3; + break; + case 22: + val = 4; + break; + case 25: + val = 5; + break; + case 30: + val = 6; + break; + default: + val = 3; + break; + } + + reg = readl_relaxed(pll->base + pll->cfg_offset); + reg &= ~pll->div_mask; + reg |= (val << pll->div_shift); + writel_relaxed(val, pll->base + pll->cfg_offset); + + return 0; +} + +static int clk_pllv5_enable(struct clk_hw *hw) +{ + u32 val; + struct clk_pllv5 *pll = to_clk_pllv5(hw); + + val = readl_relaxed(pll->base); + val |= PLL_EN; + writel_relaxed(val, pll->base); + + return 0; +} + +static void clk_pllv5_disable(struct clk_hw *hw) +{ + u32 val; + struct clk_pllv5 *pll = to_clk_pllv5(hw); + + val = readl_relaxed(pll->base); + val &= ~PLL_EN; + writel_relaxed(val, pll->base); +} + +static int clk_pllv5_is_enabled(struct clk_hw *hw) +{ + struct clk_pllv5 *pll = to_clk_pllv5(hw); + + if (readl_relaxed(pll->base) & PLL_EN) + return 0; + + return 1; +} + +static const struct clk_ops clk_pllv5_ops = { + .recalc_rate = clk_pllv5_recalc_rate, + .round_rate = clk_pllv5_round_rate, + .set_rate = clk_pllv5_set_rate, + .enable = clk_pllv5_enable, + .disable = clk_pllv5_disable, + .is_enabled = clk_pllv5_is_enabled, +}; + +struct clk *imx_clk_pllv5(const char *name, const char *parent_name, + void __iomem *base) +{ + struct clk_pllv5 *pll; + struct clk *clk; + struct clk_init_data init; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->div_mask = BM_PLL_DIV; + pll->div_shift = BP_PLL_DIV; + pll->cfg_offset = PLL_CFG_OFFSET; + + init.name = name; + init.ops = &clk_pllv5_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index a634b1185be38a..ea109199187a8f 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -7,6 +7,8 @@ DEFINE_SPINLOCK(imx_ccm_lock); +bool uart_from_osc; + void __init imx_check_clocks(struct clk *clks[], unsigned int count) { unsigned i; @@ -111,3 +113,10 @@ static int __init imx_clk_disable_uart(void) return 0; } late_initcall_sync(imx_clk_disable_uart); + +static int __init setup_uart_clk(char *uart_rate) +{ + uart_from_osc = true; + return 1; +} +__setup("uart_from_osc", setup_uart_clk); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3799ff82a9b487..07232d4aaf35f4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -3,6 +3,8 @@ #include #include +#include +#include extern spinlock_t imx_ccm_lock; @@ -10,6 +12,10 @@ void imx_check_clocks(struct clk *clks[], unsigned int count); void imx_register_uart_clocks(struct clk ** const clks[]); extern void imx_cscmr1_fixup(u32 *val); +extern struct imx_sema4_mutex *amp_power_mutex; +extern struct imx_shared_mem *shared_mem; +extern bool uart_from_osc; +extern const struct clk_ops clk_frac_divider_ops; enum imx_pllv1_type { IMX_PLLV1_IMX1, @@ -34,11 +40,54 @@ enum imx_pllv3_type { IMX_PLLV3_AV, IMX_PLLV3_ENET, IMX_PLLV3_ENET_IMX7, + IMX_PLLV3_AV_IMX7, + IMX_PLLV3_PLL2, +}; + +/* + * frac_divider, found on i.MX7ULP PCC module. + * the output clock of the fractional divider is: + * Divider output clock = Input clock * (FRAC + 1) + * / (DIV + 1) + */ +struct clk_frac_divider { + struct clk_hw hw; + void __iomem *reg; + u8 mshift; + u8 mwidth; + u32 mmask; + u8 nshift; + u8 nwidth; + u32 nmask; +}; + +#define MAX_SHARED_CLK_NUMBER 100 +#define SHARED_MEM_MAGIC_NUMBER 0x12345678 +#define MCC_POWER_SHMEM_NUMBER (6) + +struct imx_shared_clk { + struct clk *self; + struct clk *parent; + void *m4_clk; + void *m4_clk_parent; + u8 ca9_enabled; + u8 cm4_enabled; +}; + +struct imx_shared_mem { + u32 ca9_valid; + u32 cm4_valid; + struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER]; }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); +struct clk *imx_clk_pllv4(const char *name, + const char *parent_name, void __iomem *base); +struct clk *imx_clk_pllv5(const char *name, const char *parent_name, + void __iomem *base); + struct clk *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, @@ -51,6 +100,33 @@ struct clk * imx_obtain_fixed_clock( struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); +static inline void imx_clk_prepare_enable(struct clk *clk) +{ + int ret = clk_prepare_enable(clk); + + if (ret) + pr_err("failed to prepare and enable clk %s: %d\n", + __clk_get_name(clk), ret); +} + +static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = clk_set_parent(clk, parent); + + if (ret) + pr_err("failed to set parent of clk %s to %s: %d\n", + __clk_get_name(clk), __clk_get_name(parent), ret); +} + +static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = clk_set_rate(clk, rate); + + if (ret) + pr_err("failed to set rate of clk %s to %ld: %d\n", + __clk_get_name(clk), rate, ret); +} + struct clk *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); @@ -62,6 +138,9 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); +struct clk *imx_clk_busy_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift); + struct clk *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); @@ -75,6 +154,14 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } +static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, + shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { @@ -85,23 +172,24 @@ static inline struct clk *imx_clk_fixed_factor(const char *name, static inline struct clk *imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + return clk_register_divider(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider_flags(const char *name, - const char *parent, void __iomem *reg, u8 shift, u8 width, - unsigned long flags) +static inline struct clk *imx_clk_divider2(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, flags, + return clk_register_divider(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider2(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) +static inline struct clk *imx_clk_divider_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 width, + unsigned long flags) { - return clk_register_divider(NULL, name, parent, - CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + return clk_register_divider(NULL, name, parent, flags, reg, shift, width, 0, &imx_ccm_lock); } @@ -122,7 +210,15 @@ static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, static inline struct clk *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, reg, + shift, 0x3, 0, &imx_ccm_lock, NULL); +} + +static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent, + void __iomem *reg, u8 shift, unsigned long flags) +{ + return clk_register_gate2(NULL, name, parent, flags, reg, shift, 0x3, 0, &imx_ccm_lock, NULL); } @@ -130,7 +226,8 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, reg, shift, 0x3, 0, &imx_ccm_lock, share_count); } @@ -139,8 +236,8 @@ static inline struct clk *imx_clk_gate2_shared2(const char *name, unsigned int *share_count) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | - CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, - &imx_ccm_lock, share_count); + CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE, + reg, shift, 0x3, 0, &imx_ccm_lock, share_count); } static inline struct clk *imx_clk_gate2_cgr(const char *name, @@ -153,7 +250,17 @@ static inline struct clk *imx_clk_gate2_cgr(const char *name, static inline struct clk *imx_clk_gate3(const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate(NULL, name, parent, + /* + * per design team's suggestion, clk root is NOT consuming + * much power, and clk root enable/disable does NOT have domain + * control, so they suggest to leave clk root always on when + * M4 is enabled. + */ + if (imx_src_is_m4_enabled()) + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, 1, 1); + else + return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0, &imx_ccm_lock); } @@ -162,16 +269,24 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, - CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, &imx_ccm_lock, NULL); } +static inline struct clk *imx_clk_mux_bus(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, - CLK_SET_RATE_NO_REPARENT, reg, shift, - width, 0, &imx_ccm_lock); + CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, + reg, shift, width, 0, &imx_ccm_lock); } static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, @@ -187,12 +302,43 @@ static inline struct clk *imx_clk_mux_flags(const char *name, int num_parents, unsigned long flags) { return clk_register_mux(NULL, name, parents, num_parents, - flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, - &imx_ccm_lock); + flags | CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, + reg, shift, width, 0, &imx_ccm_lock); +} + +static inline struct clk *imx_clk_mux_flags_bus(const char *name, + void __iomem *reg, u8 shift, u8 width, const char **paretns, + int num_parents, unsigned long flags) +{ + return clk_register_mux(NULL, name, paretns, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &imx_ccm_lock); +} + +static inline struct clk *imx_clk_mux_glitchless(const char *name, + void __iomem *reg, u8 shift, u8 width, const char **parents, + int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &imx_ccm_lock); } struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +int imx_update_shared_mem(struct clk_hw *hw, bool enable); + +static inline int clk_on_imx6sx(void) +{ + return of_machine_is_compatible("fsl,imx6sx"); +} + +struct clk *imx_clk_composite(const char *name, const char **parent_name, + int num_parents, bool mux_present, bool rate_present, + bool gate_present, void __iomem *reg); + +struct clk *imx_clk_pfdv2(const char *name, const char *parent_name, + void __iomem *reg, u8 idx); #endif diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index e2c6e43cf8ca31..daab8b22a9def6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -532,6 +532,11 @@ config CLKSRC_IMX_GPT depends on ARM && CLKDEV_LOOKUP select CLKSRC_MMIO +config CLKSRC_IMX_TPM + bool "Clocksource using i.MX TPM" if COMPILE_TEST + depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + config CLKSRC_ST_LPC bool "Low power clocksource found in the LPC" if COMPILE_TEST select CLKSRC_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cf87f407f1adbf..8015232448d7d7 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o +obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index f595460bfc589c..3c7f0685fb369c 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -32,6 +32,7 @@ #include #include #include +#include #include /* @@ -499,7 +500,9 @@ static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type t imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); /* Try osc_per first, and fall back to per otherwise */ - imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); + imxtm->clk_per = (of_machine_is_compatible("fsl,imx6q") && + imx_get_soc_revision() <= IMX_CHIP_REVISION_1_0) ? + ERR_PTR(-ENODEV) : of_clk_get_by_name(np, "osc_per"); if (IS_ERR(imxtm->clk_per)) imxtm->clk_per = of_clk_get_by_name(np, "per"); @@ -556,4 +559,7 @@ CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6sll_timer, "fsl,imx6sll-gpt", imx6dl_timer_init_dt); CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6ul_timer, "fsl,imx6ul-gpt", imx6dl_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(mx7d_timer, "fsl,imx7d-gpt", imx6dl_timer_init_dt); diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c new file mode 100644 index 00000000000000..aec9a67088d504 --- /dev/null +++ b/drivers/clocksource/timer-imx-tpm.c @@ -0,0 +1,188 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPM_GLOBAL 0x8 + +#define TPM_SC 0x10 +#define TPM_CNT 0x14 +#define TPM_MOD 0x18 +#define TPM_STATUS 0x1c +#define TPM_C0SC 0x20 +#define TPM_C0V 0x24 + +#define TPM_STATUS_CH0F 0x1 + +#define TPM_C0SC_MSA 0x4 + +static void __iomem *timer_base; +static struct clock_event_device clockevent_tpm; + +static inline void tpm_timer_disable(void) +{ + unsigned int val; + + val = __raw_readl(timer_base + TPM_C0SC); + val &= ~(0x5 << TPM_C0SC_MSA); + __raw_writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_timer_enable(void) +{ + unsigned int val; + + val = __raw_readl(timer_base + TPM_C0SC); + val |= (0x5 << TPM_C0SC_MSA); + __raw_writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_irq_acknowledge(void) +{ + __raw_writel(1, timer_base + TPM_STATUS); +} + +static struct delay_timer tpm_delay_timer; + +static unsigned long tpm_read_current_timer(void) +{ + return __raw_readl(timer_base + TPM_CNT); +} + +static u64 notrace tpm_read_sched_clock(void) +{ + return __raw_readl(timer_base + TPM_CNT); +} + +static int __init tpm_clocksource_init(unsigned long rate) +{ + tpm_delay_timer.read_current_timer = &tpm_read_current_timer; + tpm_delay_timer.freq = rate; + register_current_timer_delay(&tpm_delay_timer); + + sched_clock_register(tpm_read_sched_clock, 32, rate); + return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", + rate, 200, 32, clocksource_mmio_readl_up); +} + +static int tpm_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned long next, now, ret; + + now = __raw_readl(timer_base + TPM_CNT); + next = now + delta; + __raw_writel(next, timer_base + TPM_C0V); + now = __raw_readl(timer_base + TPM_CNT); + + ret = next - now; + return (ret > delta) ? -ETIME : 0; +} + +static int tpm_set_state_oneshot(struct clock_event_device *evt) +{ + /* enable timer */ + tpm_timer_enable(); + + return 0; +} + +static int tpm_set_state_shutdown(struct clock_event_device *evt) +{ + /* disable timer */ + tpm_timer_disable(); + + return 0; +} + +static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_tpm; + + tpm_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct clock_event_device clockevent_tpm = { + .name = "i.MX7ULP tpm timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_oneshot = tpm_set_state_oneshot, + .set_next_event = tpm_set_next_event, + .set_state_shutdown = tpm_set_state_shutdown, + .rating = 200, +}; + +static struct irqaction tpm_timer_irq = { + .name = "i.MX7ULP tpm timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = tpm_timer_interrupt, + .dev_id = &clockevent_tpm, +}; + +static int __init tpm_clockevent_init(unsigned long rate, int irq) +{ + /* init the channel */ + setup_irq(irq, &tpm_timer_irq); + + clockevent_tpm.cpumask = cpumask_of(0); + clockevent_tpm.irq = irq; + clockevents_config_and_register(&clockevent_tpm, + rate, 300, 0xfffffffe); + + return 0; +} + +static int __init tpm_timer_init(struct device_node *np) +{ + struct clk *clk; + uint32_t val; + int irq; + + timer_base = of_iomap(np, 0); + BUG_ON(!timer_base); + + irq = irq_of_parse_and_map(np, 0); + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + /* clock shoube be enabled before access to the timer registers */ + clk_prepare_enable(clk); + + /* Initialize tpm module to a known state(counter disabled). */ + __raw_writel(0, timer_base + TPM_SC); + __raw_writel(0, timer_base + TPM_CNT); + __raw_writel(0, timer_base + TPM_C0SC); + + /* set the prescale div, div by 8 = 3MHz */ + __raw_writel(0xb, timer_base + TPM_SC); + + /* set the MOD register to 0xffffffff for free running counter */ + __raw_writel(0xffffffff, timer_base + TPM_MOD); + + tpm_clocksource_init(clk_get_rate(clk) / 8); + tpm_clockevent_init(clk_get_rate(clk) / 8, irq); + + val = __raw_readl(timer_base); + + return 0; +} +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init); diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index cac26fb228912a..a8909df6ac57d5 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -112,6 +112,16 @@ config CPU_FREQ_DEFAULT_GOV_SCHEDUTIL have a look at the help section of that governor. The fallback governor will be 'performance'. +config CPU_FREQ_DEFAULT_GOV_INTERACTIVE + bool "interactive" + select CPU_FREQ_GOV_INTERACTIVE + select CPU_FREQ_GOV_PERFORMANCE + help + Use the CPUFreq governor 'interactive' as default. This allows + you to get a full dynamic cpu frequency capable system by simply + loading your cpufreq low-level hardware driver, using the + 'interactive' governor for latency-sensitive workloads. + endchoice config CPU_FREQ_GOV_PERFORMANCE @@ -210,6 +220,26 @@ config CPU_FREQ_GOV_SCHEDUTIL If in doubt, say N. +config CPU_FREQ_GOV_INTERACTIVE + tristate "'interactive' cpufreq policy governor" + depends on CPU_FREQ + select CPU_FREQ_GOV_ATTR_SET + select IRQ_WORK + help + 'interactive' - This driver adds a dynamic cpufreq policy governor + designed for latency-sensitive workloads. + + This governor attempts to reduce the latency of clock + increases so that the system is more responsive to + interactive workloads. + + To compile this driver as a module, choose M here: the + module will be called cpufreq_interactive. + + For details, take a look at linux/Documentation/cpu-freq. + + If in doubt, say N. + comment "CPU frequency scaling drivers" config CPUFREQ_DT diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index bc3917d6015a34..0fc6ad87a1b29e 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -60,6 +60,22 @@ config ARM_IMX6Q_CPUFREQ If in doubt, say N. +config ARM_IMX7D_CPUFREQ + tristate "Freescale i.MX7 cpufreq support" + depends on ARCH_MXC + help + This adds cpufreq driver support for Freescale i.MX7 series SoCs. + + If in doubt, say N. + +config ARM_IMX7ULP_CPUFREQ + tristate "NXP i.MX7ULP cpufreq support" + depends on ARCH_MXC + help + This adds cpufreq driver support for NXP i.MX7ULP series SoCs. + + If in doubt, say N. + config ARM_INTEGRATOR tristate "CPUfreq driver for ARM Integrator CPUs" depends on ARCH_INTEGRATOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 0a9b6a093646bd..4fc9f547ae6e53 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ_GOV_POWERSAVE) += cpufreq_powersave.o obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE) += cpufreq_userspace.o obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND) += cpufreq_ondemand.o obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) += cpufreq_conservative.o +obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o obj-$(CONFIG_CPU_FREQ_GOV_ATTR_SET) += cpufreq_governor_attr_set.o @@ -56,6 +57,8 @@ obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o +obj-$(CONFIG_ARM_IMX7D_CPUFREQ) += imx7-cpufreq.o +obj-$(CONFIG_ARM_IMX7ULP_CPUFREQ) += imx7ulp-cpufreq.o obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o diff --git a/drivers/cpufreq/cpufreq_governor.h b/drivers/cpufreq/cpufreq_governor.h index ef1037e9c92b10..3196ed9c1c0a63 100644 --- a/drivers/cpufreq/cpufreq_governor.h +++ b/drivers/cpufreq/cpufreq_governor.h @@ -70,14 +70,6 @@ static ssize_t show_##file_name \ return sprintf(buf, "%u\n", dbs_data->file_name); \ } -#define gov_attr_ro(_name) \ -static struct governor_attr _name = \ -__ATTR(_name, 0444, show_##_name, NULL) - -#define gov_attr_rw(_name) \ -static struct governor_attr _name = \ -__ATTR(_name, 0644, show_##_name, store_##_name) - /* Common to all CPUs of a policy */ struct policy_dbs_info { struct cpufreq_policy *policy; diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c new file mode 100644 index 00000000000000..3ff6f6a599c8b9 --- /dev/null +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -0,0 +1,1365 @@ +/* + * drivers/cpufreq/cpufreq_interactive.c + * + * Copyright (C) 2010-2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Author: Mike Chan (mike@android.com) + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include + +/* Separate instance required for each 'interactive' directory in sysfs */ +struct interactive_tunables { + struct gov_attr_set attr_set; + + /* Hi speed to bump to from lo speed when load burst (default max) */ + unsigned int hispeed_freq; + + /* Go to hi speed when CPU load at or above this value. */ +#define DEFAULT_GO_HISPEED_LOAD 99 + unsigned long go_hispeed_load; + + /* Target load. Lower values result in higher CPU speeds. */ + spinlock_t target_loads_lock; + unsigned int *target_loads; + int ntarget_loads; + + /* + * The minimum amount of time to spend at a frequency before we can ramp + * down. + */ +#define DEFAULT_MIN_SAMPLE_TIME (80 * USEC_PER_MSEC) + unsigned long min_sample_time; + + /* The sample rate of the timer used to increase frequency */ + unsigned long sampling_rate; + + /* + * Wait this long before raising speed above hispeed, by default a + * single timer interval. + */ + spinlock_t above_hispeed_delay_lock; + unsigned int *above_hispeed_delay; + int nabove_hispeed_delay; + + /* Non-zero means indefinite speed boost active */ + int boost; + /* Duration of a boot pulse in usecs */ + int boostpulse_duration; + /* End time of boost pulse in ktime converted to usecs */ + u64 boostpulse_endtime; + bool boosted; + + /* + * Max additional time to wait in idle, beyond sampling_rate, at speeds + * above minimum before wakeup to reduce speed, or -1 if unnecessary. + */ +#define DEFAULT_TIMER_SLACK (4 * DEFAULT_SAMPLING_RATE) + unsigned long timer_slack_delay; + unsigned long timer_slack; + bool io_is_busy; +}; + +/* Separate instance required for each 'struct cpufreq_policy' */ +struct interactive_policy { + struct cpufreq_policy *policy; + struct interactive_tunables *tunables; + struct list_head tunables_hook; +}; + +/* Separate instance required for each CPU */ +struct interactive_cpu { + struct update_util_data update_util; + struct interactive_policy *ipolicy; + + struct irq_work irq_work; + u64 last_sample_time; + bool work_in_progress; + + struct rw_semaphore enable_sem; + struct timer_list slack_timer; + + spinlock_t load_lock; /* protects the next 4 fields */ + u64 time_in_idle; + u64 time_in_idle_timestamp; + u64 cputime_speedadj; + u64 cputime_speedadj_timestamp; + + spinlock_t target_freq_lock; /*protects target freq */ + unsigned int target_freq; + + unsigned int floor_freq; + u64 pol_floor_val_time; /* policy floor_validate_time */ + u64 loc_floor_val_time; /* per-cpu floor_validate_time */ + u64 pol_hispeed_val_time; /* policy hispeed_validate_time */ + u64 loc_hispeed_val_time; /* per-cpu hispeed_validate_time */ +}; + +static DEFINE_PER_CPU(struct interactive_cpu, interactive_cpu); + +/* Realtime thread handles frequency scaling */ +static struct task_struct *speedchange_task; +static cpumask_t speedchange_cpumask; +static spinlock_t speedchange_cpumask_lock; + +/* Target load. Lower values result in higher CPU speeds. */ +#define DEFAULT_TARGET_LOAD 90 +static unsigned int default_target_loads[] = {DEFAULT_TARGET_LOAD}; + +#define DEFAULT_SAMPLING_RATE (20 * USEC_PER_MSEC) +#define DEFAULT_ABOVE_HISPEED_DELAY DEFAULT_SAMPLING_RATE +static unsigned int default_above_hispeed_delay[] = { + DEFAULT_ABOVE_HISPEED_DELAY +}; + +/* Iterate over interactive policies for tunables */ +#define for_each_ipolicy(__ip) \ + list_for_each_entry(__ip, &tunables->attr_set.policy_list, tunables_hook) + +static struct interactive_tunables *global_tunables; +static DEFINE_MUTEX(global_tunables_lock); + +static inline void update_slack_delay(struct interactive_tunables *tunables) +{ + tunables->timer_slack_delay = usecs_to_jiffies(tunables->timer_slack + + tunables->sampling_rate); +} + +static bool timer_slack_required(struct interactive_cpu *icpu) +{ + struct interactive_policy *ipolicy = icpu->ipolicy; + struct interactive_tunables *tunables = ipolicy->tunables; + + if (tunables->timer_slack < 0) + return false; + + if (icpu->target_freq > ipolicy->policy->min) + return true; + + return false; +} + +static void gov_slack_timer_start(struct interactive_cpu *icpu, int cpu) +{ + struct interactive_tunables *tunables = icpu->ipolicy->tunables; + + icpu->slack_timer.expires = jiffies + tunables->timer_slack_delay; + add_timer_on(&icpu->slack_timer, cpu); +} + +static void gov_slack_timer_modify(struct interactive_cpu *icpu) +{ + struct interactive_tunables *tunables = icpu->ipolicy->tunables; + + mod_timer(&icpu->slack_timer, jiffies + tunables->timer_slack_delay); +} + +static void slack_timer_resched(struct interactive_cpu *icpu, int cpu, + bool modify) +{ + struct interactive_tunables *tunables = icpu->ipolicy->tunables; + unsigned long flags; + + spin_lock_irqsave(&icpu->load_lock, flags); + + icpu->time_in_idle = get_cpu_idle_time(cpu, + &icpu->time_in_idle_timestamp, + tunables->io_is_busy); + icpu->cputime_speedadj = 0; + icpu->cputime_speedadj_timestamp = icpu->time_in_idle_timestamp; + + if (timer_slack_required(icpu)) { + if (modify) + gov_slack_timer_modify(icpu); + else + gov_slack_timer_start(icpu, cpu); + } + + spin_unlock_irqrestore(&icpu->load_lock, flags); +} + +static unsigned int +freq_to_above_hispeed_delay(struct interactive_tunables *tunables, + unsigned int freq) +{ + unsigned long flags; + unsigned int ret; + int i; + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + + for (i = 0; i < tunables->nabove_hispeed_delay - 1 && + freq >= tunables->above_hispeed_delay[i + 1]; i += 2) + ; + + ret = tunables->above_hispeed_delay[i]; + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + + return ret; +} + +static unsigned int freq_to_targetload(struct interactive_tunables *tunables, + unsigned int freq) +{ + unsigned long flags; + unsigned int ret; + int i; + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + + for (i = 0; i < tunables->ntarget_loads - 1 && + freq >= tunables->target_loads[i + 1]; i += 2) + ; + + ret = tunables->target_loads[i]; + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + return ret; +} + +/* + * If increasing frequencies never map to a lower target load then + * choose_freq() will find the minimum frequency that does not exceed its + * target load given the current load. + */ +static unsigned int choose_freq(struct interactive_cpu *icpu, + unsigned int loadadjfreq) +{ + struct cpufreq_policy *policy = icpu->ipolicy->policy; + struct cpufreq_frequency_table *freq_table = policy->freq_table; + unsigned int prevfreq, freqmin = 0, freqmax = UINT_MAX, tl; + unsigned int freq = policy->cur; + int index; + + do { + prevfreq = freq; + tl = freq_to_targetload(icpu->ipolicy->tunables, freq); + + /* + * Find the lowest frequency where the computed load is less + * than or equal to the target load. + */ + + index = cpufreq_frequency_table_target(policy, loadadjfreq / tl, + CPUFREQ_RELATION_L); + if (index < 0) + break; + + freq = freq_table[index].frequency; + + if (freq > prevfreq) { + /* The previous frequency is too low */ + freqmin = prevfreq; + + if (freq < freqmax) + continue; + + /* Find highest frequency that is less than freqmax */ + index = cpufreq_frequency_table_target(policy, + freqmax - 1, CPUFREQ_RELATION_H); + if (index < 0) + break; + + freq = freq_table[index].frequency; + + if (freq == freqmin) { + /* + * The first frequency below freqmax has already + * been found to be too low. freqmax is the + * lowest speed we found that is fast enough. + */ + freq = freqmax; + break; + } + } else if (freq < prevfreq) { + /* The previous frequency is high enough. */ + freqmax = prevfreq; + + if (freq > freqmin) + continue; + + /* Find lowest frequency that is higher than freqmin */ + index = cpufreq_frequency_table_target(policy, + freqmin + 1, CPUFREQ_RELATION_L); + if (index < 0) + break; + + freq = freq_table[index].frequency; + + /* + * If freqmax is the first frequency above + * freqmin then we have already found that + * this speed is fast enough. + */ + if (freq == freqmax) + break; + } + + /* If same frequency chosen as previous then done. */ + } while (freq != prevfreq); + + return freq; +} + +static u64 update_load(struct interactive_cpu *icpu, int cpu) +{ + struct interactive_tunables *tunables = icpu->ipolicy->tunables; + unsigned int delta_idle, delta_time; + u64 now_idle, now, active_time; + + now_idle = get_cpu_idle_time(cpu, &now, tunables->io_is_busy); + delta_idle = (unsigned int)(now_idle - icpu->time_in_idle); + delta_time = (unsigned int)(now - icpu->time_in_idle_timestamp); + + if (delta_time <= delta_idle) + active_time = 0; + else + active_time = delta_time - delta_idle; + + icpu->cputime_speedadj += active_time * icpu->ipolicy->policy->cur; + + icpu->time_in_idle = now_idle; + icpu->time_in_idle_timestamp = now; + + return now; +} + +/* Re-evaluate load to see if a frequency change is required or not */ +static void eval_target_freq(struct interactive_cpu *icpu) +{ + struct interactive_tunables *tunables = icpu->ipolicy->tunables; + struct cpufreq_policy *policy = icpu->ipolicy->policy; + struct cpufreq_frequency_table *freq_table = policy->freq_table; + u64 cputime_speedadj, now, max_fvtime; + unsigned int new_freq, loadadjfreq, index, delta_time; + unsigned long flags; + int cpu_load; + int cpu = smp_processor_id(); + + spin_lock_irqsave(&icpu->load_lock, flags); + now = update_load(icpu, smp_processor_id()); + delta_time = (unsigned int)(now - icpu->cputime_speedadj_timestamp); + cputime_speedadj = icpu->cputime_speedadj; + spin_unlock_irqrestore(&icpu->load_lock, flags); + + if (WARN_ON_ONCE(!delta_time)) + return; + + spin_lock_irqsave(&icpu->target_freq_lock, flags); + do_div(cputime_speedadj, delta_time); + loadadjfreq = (unsigned int)cputime_speedadj * 100; + cpu_load = loadadjfreq / policy->cur; + tunables->boosted = tunables->boost || + now < tunables->boostpulse_endtime; + + if (cpu_load >= tunables->go_hispeed_load || tunables->boosted) { + if (policy->cur < tunables->hispeed_freq) { + new_freq = tunables->hispeed_freq; + } else { + new_freq = choose_freq(icpu, loadadjfreq); + + if (new_freq < tunables->hispeed_freq) + new_freq = tunables->hispeed_freq; + } + } else { + new_freq = choose_freq(icpu, loadadjfreq); + if (new_freq > tunables->hispeed_freq && + policy->cur < tunables->hispeed_freq) + new_freq = tunables->hispeed_freq; + } + + if (policy->cur >= tunables->hispeed_freq && + new_freq > policy->cur && + now - icpu->pol_hispeed_val_time < freq_to_above_hispeed_delay(tunables, policy->cur)) { + trace_cpufreq_interactive_notyet(cpu, cpu_load, + icpu->target_freq, policy->cur, new_freq); + goto exit; + } + + icpu->loc_hispeed_val_time = now; + + index = cpufreq_frequency_table_target(policy, new_freq, + CPUFREQ_RELATION_L); + new_freq = freq_table[index].frequency; + + /* + * Do not scale below floor_freq unless we have been at or above the + * floor frequency for the minimum sample time since last validated. + */ + max_fvtime = max(icpu->pol_floor_val_time, icpu->loc_floor_val_time); + if (new_freq < icpu->floor_freq && icpu->target_freq >= policy->cur) { + if (now - max_fvtime < tunables->min_sample_time) { + trace_cpufreq_interactive_notyet(cpu, cpu_load, + icpu->target_freq, policy->cur, new_freq); + goto exit; + } + } + + /* + * Update the timestamp for checking whether speed has been held at + * or above the selected frequency for a minimum of min_sample_time, + * if not boosted to hispeed_freq. If boosted to hispeed_freq then we + * allow the speed to drop as soon as the boostpulse duration expires + * (or the indefinite boost is turned off). + */ + + if (!tunables->boosted || new_freq > tunables->hispeed_freq) { + icpu->floor_freq = new_freq; + if (icpu->target_freq >= policy->cur || new_freq >= policy->cur) + icpu->loc_floor_val_time = now; + } + + if (icpu->target_freq == new_freq && + icpu->target_freq <= policy->cur) { + trace_cpufreq_interactive_already(cpu, cpu_load, + icpu->target_freq, policy->cur, new_freq); + goto exit; + } + + trace_cpufreq_interactive_target(cpu, cpu_load, icpu->target_freq, + policy->cur, new_freq); + + icpu->target_freq = new_freq; + spin_unlock_irqrestore(&icpu->target_freq_lock, flags); + + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + cpumask_set_cpu(cpu, &speedchange_cpumask); + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags); + + wake_up_process(speedchange_task); + return; + +exit: + spin_unlock_irqrestore(&icpu->target_freq_lock, flags); +} + +static void cpufreq_interactive_update(struct interactive_cpu *icpu) +{ + eval_target_freq(icpu); + slack_timer_resched(icpu, smp_processor_id(), true); +} + +static void cpufreq_interactive_get_policy_info(struct cpufreq_policy *policy, + unsigned int *pmax_freq, + u64 *phvt, u64 *pfvt) +{ + struct interactive_cpu *icpu; + u64 hvt = ~0ULL, fvt = 0; + unsigned int max_freq = 0, i; + + for_each_cpu(i, policy->cpus) { + icpu = &per_cpu(interactive_cpu, i); + + fvt = max(fvt, icpu->loc_floor_val_time); + if (icpu->target_freq > max_freq) { + max_freq = icpu->target_freq; + hvt = icpu->loc_hispeed_val_time; + } else if (icpu->target_freq == max_freq) { + hvt = min(hvt, icpu->loc_hispeed_val_time); + } + } + + *pmax_freq = max_freq; + *phvt = hvt; + *pfvt = fvt; +} + +static void cpufreq_interactive_adjust_cpu(unsigned int cpu, + struct cpufreq_policy *policy) +{ + struct interactive_cpu *icpu; + u64 hvt, fvt; + unsigned int max_freq; + int i; + + cpufreq_interactive_get_policy_info(policy, &max_freq, &hvt, &fvt); + + for_each_cpu(i, policy->cpus) { + icpu = &per_cpu(interactive_cpu, i); + icpu->pol_floor_val_time = fvt; + } + + if (max_freq != policy->cur) { + __cpufreq_driver_target(policy, max_freq, CPUFREQ_RELATION_H); + for_each_cpu(i, policy->cpus) { + icpu = &per_cpu(interactive_cpu, i); + icpu->pol_hispeed_val_time = hvt; + } + } + + trace_cpufreq_interactive_setspeed(cpu, max_freq, policy->cur); +} + +static int cpufreq_interactive_speedchange_task(void *data) +{ + unsigned int cpu; + cpumask_t tmp_mask; + unsigned long flags; + +again: + set_current_state(TASK_INTERRUPTIBLE); + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + + if (cpumask_empty(&speedchange_cpumask)) { + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags); + schedule(); + + if (kthread_should_stop()) + return 0; + + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + } + + set_current_state(TASK_RUNNING); + tmp_mask = speedchange_cpumask; + cpumask_clear(&speedchange_cpumask); + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags); + + for_each_cpu(cpu, &tmp_mask) { + struct interactive_cpu *icpu = &per_cpu(interactive_cpu, cpu); + struct cpufreq_policy *policy = icpu->ipolicy->policy; + + if (unlikely(!down_read_trylock(&icpu->enable_sem))) + continue; + + if (likely(icpu->ipolicy)) + cpufreq_interactive_adjust_cpu(cpu, policy); + + up_read(&icpu->enable_sem); + } + + goto again; +} + +static void cpufreq_interactive_boost(struct interactive_tunables *tunables) +{ + struct interactive_policy *ipolicy; + struct cpufreq_policy *policy; + struct interactive_cpu *icpu; + unsigned long flags[2]; + bool wakeup = false; + int i; + + tunables->boosted = true; + + spin_lock_irqsave(&speedchange_cpumask_lock, flags[0]); + + for_each_ipolicy(ipolicy) { + policy = ipolicy->policy; + + for_each_cpu(i, policy->cpus) { + icpu = &per_cpu(interactive_cpu, i); + + if (!down_read_trylock(&icpu->enable_sem)) + continue; + + if (!icpu->ipolicy) { + up_read(&icpu->enable_sem); + continue; + } + + spin_lock_irqsave(&icpu->target_freq_lock, flags[1]); + if (icpu->target_freq < tunables->hispeed_freq) { + icpu->target_freq = tunables->hispeed_freq; + cpumask_set_cpu(i, &speedchange_cpumask); + icpu->pol_hispeed_val_time = ktime_to_us(ktime_get()); + wakeup = true; + } + spin_unlock_irqrestore(&icpu->target_freq_lock, flags[1]); + + up_read(&icpu->enable_sem); + } + } + + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags[0]); + + if (wakeup) + wake_up_process(speedchange_task); +} + +static int cpufreq_interactive_notifier(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct cpufreq_freqs *freq = data; + struct interactive_cpu *icpu = &per_cpu(interactive_cpu, freq->cpu); + unsigned long flags; + + if (val != CPUFREQ_POSTCHANGE) + return 0; + + if (!down_read_trylock(&icpu->enable_sem)) + return 0; + + if (!icpu->ipolicy) { + up_read(&icpu->enable_sem); + return 0; + } + + spin_lock_irqsave(&icpu->load_lock, flags); + update_load(icpu, freq->cpu); + spin_unlock_irqrestore(&icpu->load_lock, flags); + + up_read(&icpu->enable_sem); + + return 0; +} + +static struct notifier_block cpufreq_notifier_block = { + .notifier_call = cpufreq_interactive_notifier, +}; + +static unsigned int *get_tokenized_data(const char *buf, int *num_tokens) +{ + const char *cp = buf; + int ntokens = 1, i = 0; + unsigned int *tokenized_data; + int err = -EINVAL; + + while ((cp = strpbrk(cp + 1, " :"))) + ntokens++; + + if (!(ntokens & 0x1)) + goto err; + + tokenized_data = kcalloc(ntokens, sizeof(*tokenized_data), GFP_KERNEL); + if (!tokenized_data) { + err = -ENOMEM; + goto err; + } + + cp = buf; + while (i < ntokens) { + if (kstrtouint(cp, 0, &tokenized_data[i++]) < 0) + goto err_kfree; + + cp = strpbrk(cp, " :"); + if (!cp) + break; + cp++; + } + + if (i != ntokens) + goto err_kfree; + + *num_tokens = ntokens; + return tokenized_data; + +err_kfree: + kfree(tokenized_data); +err: + return ERR_PTR(err); +} + +/* Interactive governor sysfs interface */ +static struct interactive_tunables *to_tunables(struct gov_attr_set *attr_set) +{ + return container_of(attr_set, struct interactive_tunables, attr_set); +} + +#define show_one(file_name, type) \ +static ssize_t show_##file_name(struct gov_attr_set *attr_set, char *buf) \ +{ \ + struct interactive_tunables *tunables = to_tunables(attr_set); \ + return sprintf(buf, type "\n", tunables->file_name); \ +} + +static ssize_t show_target_loads(struct gov_attr_set *attr_set, char *buf) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long flags; + ssize_t ret = 0; + int i; + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + + for (i = 0; i < tunables->ntarget_loads; i++) + ret += sprintf(buf + ret, "%u%s", tunables->target_loads[i], + i & 0x1 ? ":" : " "); + + sprintf(buf + ret - 1, "\n"); + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + + return ret; +} + +static ssize_t store_target_loads(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned int *new_target_loads; + unsigned long flags; + int ntokens; + + new_target_loads = get_tokenized_data(buf, &ntokens); + if (IS_ERR(new_target_loads)) + return PTR_ERR(new_target_loads); + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + if (tunables->target_loads != default_target_loads) + kfree(tunables->target_loads); + tunables->target_loads = new_target_loads; + tunables->ntarget_loads = ntokens; + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + + return count; +} + +static ssize_t show_above_hispeed_delay(struct gov_attr_set *attr_set, + char *buf) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long flags; + ssize_t ret = 0; + int i; + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + + for (i = 0; i < tunables->nabove_hispeed_delay; i++) + ret += sprintf(buf + ret, "%u%s", + tunables->above_hispeed_delay[i], + i & 0x1 ? ":" : " "); + + sprintf(buf + ret - 1, "\n"); + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + + return ret; +} + +static ssize_t store_above_hispeed_delay(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned int *new_above_hispeed_delay = NULL; + unsigned long flags; + int ntokens; + + new_above_hispeed_delay = get_tokenized_data(buf, &ntokens); + if (IS_ERR(new_above_hispeed_delay)) + return PTR_ERR(new_above_hispeed_delay); + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + if (tunables->above_hispeed_delay != default_above_hispeed_delay) + kfree(tunables->above_hispeed_delay); + tunables->above_hispeed_delay = new_above_hispeed_delay; + tunables->nabove_hispeed_delay = ntokens; + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + + return count; +} + +static ssize_t store_hispeed_freq(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long int val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->hispeed_freq = val; + + return count; +} + +static ssize_t store_go_hispeed_load(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->go_hispeed_load = val; + + return count; +} + +static ssize_t store_min_sample_time(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->min_sample_time = val; + + return count; +} + +static ssize_t show_timer_rate(struct gov_attr_set *attr_set, char *buf) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + + return sprintf(buf, "%lu\n", tunables->sampling_rate); +} + +static ssize_t store_timer_rate(struct gov_attr_set *attr_set, const char *buf, + size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val, val_round; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + val_round = jiffies_to_usecs(usecs_to_jiffies(val)); + if (val != val_round) + pr_warn("timer_rate not aligned to jiffy. Rounded up to %lu\n", + val_round); + + tunables->sampling_rate = val_round; + + return count; +} + +static ssize_t store_timer_slack(struct gov_attr_set *attr_set, const char *buf, + size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtol(buf, 10, &val); + if (ret < 0) + return ret; + + tunables->timer_slack = val; + update_slack_delay(tunables); + + return count; +} + +static ssize_t store_boost(struct gov_attr_set *attr_set, const char *buf, + size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boost = val; + + if (tunables->boost) { + trace_cpufreq_interactive_boost("on"); + if (!tunables->boosted) + cpufreq_interactive_boost(tunables); + } else { + tunables->boostpulse_endtime = ktime_to_us(ktime_get()); + trace_cpufreq_interactive_unboost("off"); + } + + return count; +} + +static ssize_t store_boostpulse(struct gov_attr_set *attr_set, const char *buf, + size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boostpulse_endtime = ktime_to_us(ktime_get()) + + tunables->boostpulse_duration; + trace_cpufreq_interactive_boost("pulse"); + if (!tunables->boosted) + cpufreq_interactive_boost(tunables); + + return count; +} + +static ssize_t store_boostpulse_duration(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boostpulse_duration = val; + + return count; +} + +static ssize_t store_io_is_busy(struct gov_attr_set *attr_set, const char *buf, + size_t count) +{ + struct interactive_tunables *tunables = to_tunables(attr_set); + unsigned long val; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->io_is_busy = val; + + return count; +} + +show_one(hispeed_freq, "%u"); +show_one(go_hispeed_load, "%lu"); +show_one(min_sample_time, "%lu"); +show_one(timer_slack, "%lu"); +show_one(boost, "%u"); +show_one(boostpulse_duration, "%u"); +show_one(io_is_busy, "%u"); + +gov_attr_rw(target_loads); +gov_attr_rw(above_hispeed_delay); +gov_attr_rw(hispeed_freq); +gov_attr_rw(go_hispeed_load); +gov_attr_rw(min_sample_time); +gov_attr_rw(timer_rate); +gov_attr_rw(timer_slack); +gov_attr_rw(boost); +gov_attr_wo(boostpulse); +gov_attr_rw(boostpulse_duration); +gov_attr_rw(io_is_busy); + +static struct attribute *interactive_attributes[] = { + &target_loads.attr, + &above_hispeed_delay.attr, + &hispeed_freq.attr, + &go_hispeed_load.attr, + &min_sample_time.attr, + &timer_rate.attr, + &timer_slack.attr, + &boost.attr, + &boostpulse.attr, + &boostpulse_duration.attr, + &io_is_busy.attr, + NULL +}; + +static struct kobj_type interactive_tunables_ktype = { + .default_attrs = interactive_attributes, + .sysfs_ops = &governor_sysfs_ops, +}; + +/* Interactive Governor callbacks */ +struct interactive_governor { + struct cpufreq_governor gov; + unsigned int usage_count; +}; + +static struct interactive_governor interactive_gov; + +#define CPU_FREQ_GOV_INTERACTIVE (&interactive_gov.gov) + +static void irq_work(struct irq_work *irq_work) +{ + struct interactive_cpu *icpu = container_of(irq_work, struct + interactive_cpu, irq_work); + + cpufreq_interactive_update(icpu); + icpu->work_in_progress = false; +} + +static void update_util_handler(struct update_util_data *data, u64 time, + unsigned int flags) +{ + struct interactive_cpu *icpu = container_of(data, + struct interactive_cpu, update_util); + struct interactive_policy *ipolicy = icpu->ipolicy; + struct interactive_tunables *tunables = ipolicy->tunables; + u64 delta_ns; + + /* + * The irq-work may not be allowed to be queued up right now. + * Possible reasons: + * - Work has already been queued up or is in progress. + * - It is too early (too little time from the previous sample). + */ + if (icpu->work_in_progress) + return; + + delta_ns = time - icpu->last_sample_time; + if ((s64)delta_ns < tunables->sampling_rate * NSEC_PER_USEC) + return; + + icpu->last_sample_time = time; + + icpu->work_in_progress = true; + irq_work_queue(&icpu->irq_work); +} + +static void gov_set_update_util(struct interactive_policy *ipolicy) +{ + struct cpufreq_policy *policy = ipolicy->policy; + struct interactive_cpu *icpu; + int cpu; + + for_each_cpu(cpu, policy->cpus) { + icpu = &per_cpu(interactive_cpu, cpu); + + icpu->last_sample_time = 0; + cpufreq_add_update_util_hook(cpu, &icpu->update_util, + update_util_handler); + } +} + +static inline void gov_clear_update_util(struct cpufreq_policy *policy) +{ + int i; + + for_each_cpu(i, policy->cpus) + cpufreq_remove_update_util_hook(i); + + synchronize_sched(); +} + +static void icpu_cancel_work(struct interactive_cpu *icpu) +{ + irq_work_sync(&icpu->irq_work); + icpu->work_in_progress = false; + del_timer_sync(&icpu->slack_timer); +} + +static struct interactive_policy * +interactive_policy_alloc(struct cpufreq_policy *policy) +{ + struct interactive_policy *ipolicy; + + ipolicy = kzalloc(sizeof(*ipolicy), GFP_KERNEL); + if (!ipolicy) + return NULL; + + ipolicy->policy = policy; + + return ipolicy; +} + +static void interactive_policy_free(struct interactive_policy *ipolicy) +{ + kfree(ipolicy); +} + +static struct interactive_tunables * +interactive_tunables_alloc(struct interactive_policy *ipolicy) +{ + struct interactive_tunables *tunables; + + tunables = kzalloc(sizeof(*tunables), GFP_KERNEL); + if (!tunables) + return NULL; + + gov_attr_set_init(&tunables->attr_set, &ipolicy->tunables_hook); + if (!have_governor_per_policy()) + global_tunables = tunables; + + ipolicy->tunables = tunables; + + return tunables; +} + +static void interactive_tunables_free(struct interactive_tunables *tunables) +{ + if (!have_governor_per_policy()) + global_tunables = NULL; + + kfree(tunables); +} + +int cpufreq_interactive_init(struct cpufreq_policy *policy) +{ + struct interactive_policy *ipolicy; + struct interactive_tunables *tunables; + int ret; + + /* State should be equivalent to EXIT */ + if (policy->governor_data) + return -EBUSY; + + ipolicy = interactive_policy_alloc(policy); + if (!ipolicy) + return -ENOMEM; + + mutex_lock(&global_tunables_lock); + + if (global_tunables) { + if (WARN_ON(have_governor_per_policy())) { + ret = -EINVAL; + goto free_int_policy; + } + + policy->governor_data = ipolicy; + ipolicy->tunables = global_tunables; + + gov_attr_set_get(&global_tunables->attr_set, + &ipolicy->tunables_hook); + goto out; + } + + tunables = interactive_tunables_alloc(ipolicy); + if (!tunables) { + ret = -ENOMEM; + goto free_int_policy; + } + + tunables->hispeed_freq = policy->max; + tunables->above_hispeed_delay = default_above_hispeed_delay; + tunables->nabove_hispeed_delay = + ARRAY_SIZE(default_above_hispeed_delay); + tunables->go_hispeed_load = DEFAULT_GO_HISPEED_LOAD; + tunables->target_loads = default_target_loads; + tunables->ntarget_loads = ARRAY_SIZE(default_target_loads); + tunables->min_sample_time = DEFAULT_MIN_SAMPLE_TIME; + tunables->boostpulse_duration = DEFAULT_MIN_SAMPLE_TIME; + tunables->sampling_rate = DEFAULT_SAMPLING_RATE; + tunables->timer_slack = DEFAULT_TIMER_SLACK; + update_slack_delay(tunables); + + spin_lock_init(&tunables->target_loads_lock); + spin_lock_init(&tunables->above_hispeed_delay_lock); + + policy->governor_data = ipolicy; + + ret = kobject_init_and_add(&tunables->attr_set.kobj, + &interactive_tunables_ktype, + get_governor_parent_kobj(policy), "%s", + interactive_gov.gov.name); + if (ret) + goto fail; + + /* One time initialization for governor */ + if (!interactive_gov.usage_count++) { + cpufreq_register_notifier(&cpufreq_notifier_block, + CPUFREQ_TRANSITION_NOTIFIER); + } + + out: + mutex_unlock(&global_tunables_lock); + return 0; + + fail: + policy->governor_data = NULL; + interactive_tunables_free(tunables); + + free_int_policy: + mutex_unlock(&global_tunables_lock); + + interactive_policy_free(ipolicy); + pr_err("governor initialization failed (%d)\n", ret); + + return ret; +} + +void cpufreq_interactive_exit(struct cpufreq_policy *policy) +{ + struct interactive_policy *ipolicy = policy->governor_data; + struct interactive_tunables *tunables = ipolicy->tunables; + unsigned int count; + + mutex_lock(&global_tunables_lock); + + /* Last policy using the governor ? */ + if (!--interactive_gov.usage_count) { + cpufreq_unregister_notifier(&cpufreq_notifier_block, + CPUFREQ_TRANSITION_NOTIFIER); + } + + count = gov_attr_set_put(&tunables->attr_set, &ipolicy->tunables_hook); + policy->governor_data = NULL; + if (!count) + interactive_tunables_free(tunables); + + mutex_unlock(&global_tunables_lock); + + interactive_policy_free(ipolicy); +} + +int cpufreq_interactive_start(struct cpufreq_policy *policy) +{ + struct interactive_policy *ipolicy = policy->governor_data; + struct interactive_cpu *icpu; + unsigned int cpu; + + for_each_cpu(cpu, policy->cpus) { + icpu = &per_cpu(interactive_cpu, cpu); + + icpu->target_freq = policy->cur; + icpu->floor_freq = icpu->target_freq; + icpu->pol_floor_val_time = ktime_to_us(ktime_get()); + icpu->loc_floor_val_time = icpu->pol_floor_val_time; + icpu->pol_hispeed_val_time = icpu->pol_floor_val_time; + icpu->loc_hispeed_val_time = icpu->pol_floor_val_time; + + down_write(&icpu->enable_sem); + icpu->ipolicy = ipolicy; + up_write(&icpu->enable_sem); + + slack_timer_resched(icpu, cpu, false); + } + + gov_set_update_util(ipolicy); + return 0; +} + +void cpufreq_interactive_stop(struct cpufreq_policy *policy) +{ + struct interactive_policy *ipolicy = policy->governor_data; + struct interactive_cpu *icpu; + unsigned int cpu; + + gov_clear_update_util(ipolicy->policy); + + for_each_cpu(cpu, policy->cpus) { + icpu = &per_cpu(interactive_cpu, cpu); + + icpu_cancel_work(icpu); + + down_write(&icpu->enable_sem); + icpu->ipolicy = NULL; + up_write(&icpu->enable_sem); + } +} + +void cpufreq_interactive_limits(struct cpufreq_policy *policy) +{ + struct interactive_cpu *icpu; + unsigned int cpu; + unsigned long flags; + + cpufreq_policy_apply_limits(policy); + + for_each_cpu(cpu, policy->cpus) { + icpu = &per_cpu(interactive_cpu, cpu); + + spin_lock_irqsave(&icpu->target_freq_lock, flags); + + if (policy->max < icpu->target_freq) + icpu->target_freq = policy->max; + else if (policy->min > icpu->target_freq) + icpu->target_freq = policy->min; + + spin_unlock_irqrestore(&icpu->target_freq_lock, flags); + } +} + +static struct interactive_governor interactive_gov = { + .gov = { + .name = "interactive", + .max_transition_latency = TRANSITION_LATENCY_LIMIT, + .owner = THIS_MODULE, + .init = cpufreq_interactive_init, + .exit = cpufreq_interactive_exit, + .start = cpufreq_interactive_start, + .stop = cpufreq_interactive_stop, + .limits = cpufreq_interactive_limits, + } +}; + +static void cpufreq_interactive_nop_timer(unsigned long data) +{ + /* + * The purpose of slack-timer is to wake up the CPU from IDLE, in order + * to decrease its frequency if it is not set to minimum already. + * + * This is important for platforms where CPU with higher frequencies + * consume higher power even at IDLE. + */ +} + +static int __init cpufreq_interactive_gov_init(void) +{ + struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; + struct interactive_cpu *icpu; + unsigned int cpu; + + for_each_possible_cpu(cpu) { + icpu = &per_cpu(interactive_cpu, cpu); + + init_irq_work(&icpu->irq_work, irq_work); + spin_lock_init(&icpu->load_lock); + spin_lock_init(&icpu->target_freq_lock); + init_rwsem(&icpu->enable_sem); + + /* Initialize per-cpu slack-timer */ + init_timer_pinned(&icpu->slack_timer); + icpu->slack_timer.function = cpufreq_interactive_nop_timer; + } + + spin_lock_init(&speedchange_cpumask_lock); + speedchange_task = kthread_create(cpufreq_interactive_speedchange_task, + NULL, "cfinteractive"); + if (IS_ERR(speedchange_task)) + return PTR_ERR(speedchange_task); + + sched_setscheduler_nocheck(speedchange_task, SCHED_FIFO, ¶m); + get_task_struct(speedchange_task); + + /* wake up so the thread does not look hung to the freezer */ + wake_up_process(speedchange_task); + + return cpufreq_register_governor(CPU_FREQ_GOV_INTERACTIVE); +} + +#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE +struct cpufreq_governor *cpufreq_default_governor(void) +{ + return CPU_FREQ_GOV_INTERACTIVE; +} + +fs_initcall(cpufreq_interactive_gov_init); +#else +module_init(cpufreq_interactive_gov_init); +#endif + +static void __exit cpufreq_interactive_gov_exit(void) +{ + cpufreq_unregister_governor(CPU_FREQ_GOV_INTERACTIVE); + kthread_stop(speedchange_task); + put_task_struct(speedchange_task); +} +module_exit(cpufreq_interactive_gov_exit); + +MODULE_AUTHOR("Mike Chan "); +MODULE_DESCRIPTION("'cpufreq_interactive' - A dynamic cpufreq governor for Latency sensitive workloads"); +MODULE_LICENSE("GPL"); diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c index 3a1f49f5f4c68a..7cb87c33ca671c 100644 --- a/drivers/cpufreq/cpufreq_ondemand.c +++ b/drivers/cpufreq/cpufreq_ondemand.c @@ -37,7 +37,8 @@ static unsigned int default_powersave_bias; * efficient idling at a higher frequency/voltage is. * Pavel Machek says this is not so for various generations of AMD and old * Intel systems. - * Mike Chan (android.com) claims this is also not true for ARM. + * ARM systems v7 and later generally good idle power management as well, so + * treat them the same. * Because of this, whitelist specific known (series) of CPUs by default, and * leave all others up to the user. */ @@ -51,6 +52,9 @@ static int should_io_be_busy(void) boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model >= 15) return 1; +#endif +#if defined(CONFIG_ARM) && defined(CPU_V7) + return 1; #endif return 0; } diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index ef1fa8145419cd..dbcf35b456b848 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -1,28 +1,39 @@ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include #include #include #include +#include #include #include #include #include +#include #define PU_SOC_VOLTAGE_NORMAL 1250000 #define PU_SOC_VOLTAGE_HIGH 1275000 +#define DC_VOLTAGE_MIN 1300000 +#define DC_VOLTAGE_MAX 1400000 #define FREQ_1P2_GHZ 1200000000 +#define FREQ_396_MHZ 396000 +#define FREQ_528_MHZ 528000 +#define FREQ_198_MHZ 198000 +#define FREQ_24_MHZ 24000 -static struct regulator *arm_reg; +struct regulator *arm_reg; static struct regulator *pu_reg; -static struct regulator *soc_reg; +struct regulator *soc_reg; +static struct regulator *dc_reg; static struct clk *arm_clk; static struct clk *pll1_sys_clk; @@ -31,6 +42,9 @@ static struct clk *step_clk; static struct clk *pll2_pfd2_396m_clk; /* clk used by i.MX6UL */ +static struct clk *pll1_bypass; +static struct clk *pll1_bypass_src; +static struct clk *pll1; static struct clk *pll2_bus_clk; static struct clk *secondary_sel_clk; @@ -38,9 +52,11 @@ static struct device *cpu_dev; static bool free_opp; static struct cpufreq_frequency_table *freq_table; static unsigned int transition_latency; - +static struct mutex set_cpufreq_lock; static u32 *imx6_soc_volt; static u32 soc_opp_count; +static bool ignore_dc_reg; +static bool low_power_run_support; static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { @@ -49,15 +65,29 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) unsigned int old_freq, new_freq; int ret; + mutex_lock(&set_cpufreq_lock); + new_freq = freq_table[index].frequency; freq_hz = new_freq * 1000; - old_freq = clk_get_rate(arm_clk) / 1000; + old_freq = policy->cur; + + /* + * ON i.MX6ULL, the 24MHz setpoint is not seen by cpufreq + * so we neet to prevent the cpufreq change frequency + * from 24MHz to 198Mhz directly. busfreq will handle this + * when exit from low bus mode. + */ + if (old_freq == FREQ_24_MHZ && new_freq == FREQ_198_MHZ) { + mutex_unlock(&set_cpufreq_lock); + return 0; + }; rcu_read_lock(); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { rcu_read_unlock(); dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); + mutex_unlock(&set_cpufreq_lock); return PTR_ERR(opp); } @@ -68,6 +98,16 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", old_freq / 1000, volt_old / 1000, new_freq / 1000, volt / 1000); + /* + * CPU freq is increasing, so need to ensure + * that bus frequency is increased too. + */ + if (low_power_run_support) { + if (old_freq == freq_table[0].frequency) + request_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } /* scaling up? scale voltage before frequency */ if (new_freq > old_freq) { @@ -75,18 +115,21 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); if (ret) { dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); + mutex_unlock(&set_cpufreq_lock); return ret; } } ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); if (ret) { dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); + mutex_unlock(&set_cpufreq_lock); return ret; } ret = regulator_set_voltage_tol(arm_reg, volt, 0); if (ret) { dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); + mutex_unlock(&set_cpufreq_lock); return ret; } } @@ -102,7 +145,8 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it * - Disable pll2_pfd2_396m_clk */ - if (of_machine_is_compatible("fsl,imx6ul")) { + if (of_machine_is_compatible("fsl,imx6ul") || + of_machine_is_compatible("fsl,imx6ull")) { /* * When changing pll1_sw_clk's parent to pll1_sys_clk, * CPU may run at higher than 528MHz, this will lead to @@ -118,12 +162,28 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); clk_set_parent(step_clk, secondary_sel_clk); clk_set_parent(pll1_sw_clk, step_clk); + if (freq_hz > clk_get_rate(pll2_bus_clk)) { + clk_set_rate(pll1, new_freq * 1000); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + } } else { clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { + /* Ensure that pll1_bypass is set back to + * pll1. We have to do this first so that the + * change rate done to pll1_sys_clk done below + * can propagate up to pll1. + */ + clk_set_parent(pll1_bypass, pll1); clk_set_rate(pll1_sys_clk, new_freq * 1000); clk_set_parent(pll1_sw_clk, pll1_sys_clk); + } else { + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass, pll1_bypass_src); } } @@ -132,6 +192,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) if (ret) { dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); regulator_set_voltage_tol(arm_reg, volt_old, 0); + mutex_unlock(&set_cpufreq_lock); return ret; } @@ -156,14 +217,40 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) } } } + /* + * If CPU is dropped to the lowest level, release the need + * for a high bus frequency. + */ + if (low_power_run_support) { + if (new_freq == freq_table[0].frequency) + release_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ) { + release_bus_freq(BUS_FREQ_HIGH); + } + mutex_unlock(&set_cpufreq_lock); return 0; } static int imx6q_cpufreq_init(struct cpufreq_policy *policy) { + int ret; + policy->clk = arm_clk; - return cpufreq_generic_init(policy, freq_table, transition_latency); + policy->cur = clk_get_rate(arm_clk) / 1000; + + ret = cpufreq_generic_init(policy, freq_table, transition_latency); + if (ret) { + dev_err(cpu_dev, "imx6 cpufreq init failed!\n"); + return ret; + } + if (low_power_run_support && policy->cur > freq_table[0].frequency) { + request_bus_freq(BUS_FREQ_HIGH); + } else if (policy->cur > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } + + return 0; } static struct cpufreq_driver imx6q_cpufreq_driver = { @@ -176,15 +263,61 @@ static struct cpufreq_driver imx6q_cpufreq_driver = { .attr = cpufreq_generic_attr, }; +static int imx6_cpufreq_pm_notify(struct notifier_block *nb, + unsigned long event, void *dummy) +{ + struct cpufreq_policy *data = cpufreq_cpu_get(0); + static u32 cpufreq_policy_min_pre_suspend; + + /* + * During suspend/resume, When cpufreq driver try to increase + * voltage/freq, it needs to control I2C/SPI to communicate + * with external PMIC to adjust voltage, but these I2C/SPI + * devices may be already suspended, to avoid such scenario, + * we just increase cpufreq to highest setpoint before suspend. + */ + if (!data) + return NOTIFY_BAD; + + switch (event) { + case PM_SUSPEND_PREPARE: + cpufreq_policy_min_pre_suspend = data->user_policy.min; + data->user_policy.min = data->user_policy.max; + + if (!IS_ERR(dc_reg) && !ignore_dc_reg) + regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); + break; + case PM_POST_SUSPEND: + data->user_policy.min = cpufreq_policy_min_pre_suspend; + + if (!IS_ERR(dc_reg) && !ignore_dc_reg) + regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + break; + default: + break; + } + + cpufreq_update_policy(0); + cpufreq_cpu_put(data); + + return NOTIFY_OK; +} + +static struct notifier_block imx6_cpufreq_pm_notifier = { + .notifier_call = imx6_cpufreq_pm_notify, +}; + static int imx6q_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; struct dev_pm_opp *opp; + struct clk *vpu_axi_podf; unsigned long min_volt, max_volt; int num, ret; const struct property *prop; const __be32 *val; - u32 nr, i, j; + u32 nr, j, i = 0; + u32 vpu_axi_rate = 0; cpu_dev = get_cpu_device(0); if (!cpu_dev) { @@ -203,14 +336,19 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) pll1_sw_clk = clk_get(cpu_dev, "pll1_sw"); step_clk = clk_get(cpu_dev, "step"); pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m"); + pll1 = clk_get(cpu_dev, "pll1"); + pll1_bypass = clk_get(cpu_dev, "pll1_bypass"); + pll1_bypass_src = clk_get(cpu_dev, "pll1_bypass_src"); if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || - IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { + IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk) || IS_ERR(pll1) || + IS_ERR(pll1_bypass) || IS_ERR(pll1_bypass_src)) { dev_err(cpu_dev, "failed to get clocks\n"); ret = -ENOENT; goto put_clk; } - if (of_machine_is_compatible("fsl,imx6ul")) { + if (of_machine_is_compatible("fsl,imx6ul") || + of_machine_is_compatible("fsl,imx6ull")) { pll2_bus_clk = clk_get(cpu_dev, "pll2_bus"); secondary_sel_clk = clk_get(cpu_dev, "secondary_sel"); if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) { @@ -220,15 +358,40 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) } } + vpu_axi_podf = clk_get(cpu_dev, "vpu_axi_podf"); + if (!IS_ERR(vpu_axi_podf)) { + vpu_axi_rate = clk_get_rate(vpu_axi_podf); + clk_put(vpu_axi_podf); + } + arm_reg = regulator_get(cpu_dev, "arm"); pu_reg = regulator_get_optional(cpu_dev, "pu"); soc_reg = regulator_get(cpu_dev, "soc"); if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { - dev_err(cpu_dev, "failed to get regulators\n"); - ret = -ENOENT; + ret = IS_ERR(arm_reg)?PTR_ERR(arm_reg):PTR_ERR(soc_reg); + if (ret == -EPROBE_DEFER) + dev_warn(cpu_dev, "regulators not ready, retry\n"); + else + dev_err(cpu_dev, "failed to get regulators: %d\n", ret); goto put_reg; } + dc_reg = regulator_get_optional(cpu_dev, "dc"); + + /* + * soc_reg sync with arm_reg if arm shares the same regulator + * with soc. Otherwise, regulator common framework will refuse to update + * this consumer's voltage right now while another consumer voltage + * still keep in old one. For example, imx6sx-sdb with pfuze200 in + * ldo-bypass mode. + */ + of_property_read_u32(np, "fsl,arm-soc-shared", &i); + if (i == 1) + soc_reg = arm_reg; + + /* On i.MX6ULL, check the 24MHz low power run mode support */ + low_power_run_support = of_property_read_bool(np, "fsl,low-power-run"); + /* * We expect an OPP table supplied by platform. * Just, incase the platform did not supply the OPP @@ -259,8 +422,17 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto put_reg; } + /* + * On i.MX6UL/ULL EVK board, if the SOC is run in overide frequency, + * the dc_regulator voltage should not be touched. + */ + if (freq_table[num - 1].frequency > FREQ_528_MHZ) + ignore_dc_reg = true; + if (!IS_ERR(dc_reg) && !ignore_dc_reg) + regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + /* Make imx6_soc_volt array's size same as arm opp number */ - imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); + imx6_soc_volt = kzalloc(sizeof(*imx6_soc_volt) * num, GFP_KERNEL); if (imx6_soc_volt == NULL) { ret = -ENOMEM; goto free_freq_table; @@ -285,6 +457,19 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) unsigned long volt = be32_to_cpup(val++); if (freq_table[j].frequency == freq) { imx6_soc_volt[soc_opp_count++] = volt; +#ifdef CONFIG_MX6_VPU_352M + if (freq == 792000) { + pr_info("increase SOC/PU voltage for VPU352MHz\n"); + imx6_soc_volt[soc_opp_count - 1] = 1250000; + } +#endif + if (vpu_axi_rate == 396000000) { + if (freq <= 996000) { + pr_info("increase SOC/PU voltage for VPU396MHz at %ld MHz\n", + freq / 1000); + imx6_soc_volt[soc_opp_count - 1] = 1275000; + } + } break; } } @@ -333,16 +518,22 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) if (ret > 0) transition_latency += ret * 1000; + mutex_init(&set_cpufreq_lock); + ret = cpufreq_register_driver(&imx6q_cpufreq_driver); if (ret) { dev_err(cpu_dev, "failed register driver: %d\n", ret); goto free_freq_table; } + register_pm_notifier(&imx6_cpufreq_pm_notifier); + of_node_put(np); + dev_info(cpu_dev, "Registered imx6q-cpufreq\n"); return 0; free_freq_table: + kfree(imx6_soc_volt); dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); out_free_opp: if (free_opp) @@ -354,6 +545,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) regulator_put(pu_reg); if (!IS_ERR(soc_reg)) regulator_put(soc_reg); + if (!IS_ERR(dc_reg)) + regulator_put(dc_reg); put_clk: if (!IS_ERR(arm_clk)) clk_put(arm_clk); @@ -365,6 +558,12 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) clk_put(step_clk); if (!IS_ERR(pll2_pfd2_396m_clk)) clk_put(pll2_pfd2_396m_clk); + if (!IS_ERR(pll1)) + clk_put(pll1); + if (!IS_ERR(pll1_bypass)) + clk_put(pll1_bypass); + if (!IS_ERR(pll1_bypass_src)) + clk_put(pll1_bypass_src); if (!IS_ERR(pll2_bus_clk)) clk_put(pll2_bus_clk); if (!IS_ERR(secondary_sel_clk)) @@ -376,6 +575,7 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) static int imx6q_cpufreq_remove(struct platform_device *pdev) { cpufreq_unregister_driver(&imx6q_cpufreq_driver); + kfree(imx6_soc_volt); dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); if (free_opp) dev_pm_opp_of_remove_table(cpu_dev); @@ -383,10 +583,15 @@ static int imx6q_cpufreq_remove(struct platform_device *pdev) if (!IS_ERR(pu_reg)) regulator_put(pu_reg); regulator_put(soc_reg); + if (!IS_ERR(dc_reg)) + regulator_put(dc_reg); clk_put(arm_clk); clk_put(pll1_sys_clk); clk_put(pll1_sw_clk); clk_put(step_clk); + clk_put(pll1); + clk_put(pll1_bypass); + clk_put(pll1_bypass_src); clk_put(pll2_pfd2_396m_clk); clk_put(pll2_bus_clk); clk_put(secondary_sel_clk); diff --git a/drivers/cpufreq/imx7-cpufreq.c b/drivers/cpufreq/imx7-cpufreq.c new file mode 100644 index 00000000000000..32f30cec04ff86 --- /dev/null +++ b/drivers/cpufreq/imx7-cpufreq.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +static struct clk *arm_clk; + +static struct regulator *arm_reg; + +static struct device *cpu_dev; +static struct cpufreq_frequency_table *freq_table; +static unsigned int transition_latency; +static struct mutex set_cpufreq_lock; + +static int imx7d_set_target(struct cpufreq_policy *policy, unsigned int index) +{ + struct dev_pm_opp *opp; + unsigned long freq_hz, volt, volt_old; + unsigned int old_freq, new_freq; + int ret; + + mutex_lock(&set_cpufreq_lock); + + new_freq = freq_table[index].frequency; + freq_hz = new_freq * 1000; + old_freq = clk_get_rate(arm_clk) / 1000; + + rcu_read_lock(); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); + mutex_unlock(&set_cpufreq_lock); + return PTR_ERR(opp); + } + volt = dev_pm_opp_get_voltage(opp); + + rcu_read_unlock(); + volt_old = regulator_get_voltage(arm_reg); + + dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", + old_freq / 1000, volt_old / 1000, + new_freq / 1000, volt / 1000); + + /* Scaling up? scale voltage before frequency */ + if (new_freq > old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); + mutex_unlock(&set_cpufreq_lock); + return ret; + } + } + + /* change the cpu frequency */ + ret = clk_set_rate(arm_clk, new_freq * 1000); + if (ret) { + dev_err(cpu_dev, " failed to set clock rate: %d\n", ret); + regulator_set_voltage_tol(arm_reg, volt_old, 0); + mutex_unlock(&set_cpufreq_lock); + return ret; + } + + /* scaling down? scaling voltage after frequency */ + if (new_freq < old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_warn(cpu_dev, "failed to scale vddarm down: %d\n", ret); + ret = 0; + } + } + + mutex_unlock(&set_cpufreq_lock); + return 0; +} + +static int imx7d_cpufreq_init(struct cpufreq_policy *policy) +{ + int ret; + policy->clk = arm_clk; + policy->cur = clk_get_rate(arm_clk) / 1000; + + ret = cpufreq_generic_init(policy, freq_table, transition_latency); + if (ret) { + dev_err(cpu_dev, "imx7d cpufreq init failed!\n"); + return ret; + } + + return 0; +} + +static struct cpufreq_driver imx7d_cpufreq_driver = { + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = imx7d_set_target, + .get = cpufreq_generic_get, + .init = imx7d_cpufreq_init, + .name = "imx7d-cpufreq", + .attr = cpufreq_generic_attr, +}; + +static int imx7_cpufreq_pm_notify(struct notifier_block *nb, + unsigned long event, void *dummy) +{ + struct cpufreq_policy *data = cpufreq_cpu_get(0); + static u32 cpufreq_policy_min_pre_suspend; + + /* + * During suspend/resume, when cpufreq driver try to increase + * voltage/freq, it needs to control I2C/SPI to communicate + * with external PMIC to adjust voltage, but these I2C/SPI + * devices may be already suspended, to avoid such scenario, + * we just increase cpufreq to highest setpoint before suspend. + */ + if (!data) + return NOTIFY_BAD; + + switch (event) { + case PM_SUSPEND_PREPARE: + cpufreq_policy_min_pre_suspend = data->user_policy.min; + data->user_policy.min = data->user_policy.max; + break; + case PM_POST_SUSPEND: + data->user_policy.min = cpufreq_policy_min_pre_suspend; + break; + default: + break; + } + + cpufreq_update_policy(0); + cpufreq_cpu_put(data); + + return NOTIFY_OK; +} + +static struct notifier_block imx7_cpufreq_pm_notifier = { + .notifier_call = imx7_cpufreq_pm_notify, +}; + +static int imx7d_cpufreq_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct dev_pm_opp *opp; + unsigned long min_volt, max_volt; + int num, ret; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) { + pr_err("failed to get cpu0 device\n"); + return -ENODEV; + } + + np = of_node_get(cpu_dev->of_node); + if (!np) { + dev_err(cpu_dev, "failed to find the cpu0 node\n"); + return -ENOENT; + } + + arm_clk = devm_clk_get(cpu_dev, "arm"); + if (IS_ERR(arm_clk)) { + dev_err(cpu_dev, "failed to get arm clock\n"); + ret = PTR_ERR(arm_clk); + goto put_node; + } + + arm_reg = devm_regulator_get(cpu_dev, "arm"); + if (IS_ERR(arm_reg)) { + dev_err(cpu_dev, "failed to get the regulator\n"); + ret = -ENOENT; + goto put_node; + } + + /* We expect an OPP table supplied by platform. + * Just incase the platform did not supply the OPP + * table, it will try to get it. + */ + num = dev_pm_opp_get_opp_count(cpu_dev); + if (num < 0) { + ret = dev_pm_opp_of_add_table(cpu_dev); + if (ret < 0) { + dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); + goto put_node; + } + num = dev_pm_opp_get_opp_count(cpu_dev); + if (num < 0) { + ret = num; + dev_err(cpu_dev, "no OPP table is found: %d\n", ret); + goto put_node; + } + } + + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); + if (ret) { + dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); + goto put_node; + } + + if (of_property_read_u32(np, "clock-latency", &transition_latency)) + transition_latency = CPUFREQ_ETERNAL; + + /* OPP is maintained in order of increasing frequency, and + * freq_table initialized from OPP is therefore sorted in the + * same order + */ + rcu_read_lock(); + opp = dev_pm_opp_find_freq_exact(cpu_dev, + freq_table[0].frequency * 1000, true); + min_volt = dev_pm_opp_get_voltage(opp); + opp = dev_pm_opp_find_freq_exact(cpu_dev, + freq_table[--num].frequency * 1000, true); + max_volt = dev_pm_opp_get_voltage(opp); + rcu_read_unlock(); + ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); + if (ret > 0) + transition_latency += ret * 1000; + + mutex_init(&set_cpufreq_lock); + + ret = cpufreq_register_driver(&imx7d_cpufreq_driver); + if (ret) { + dev_err(cpu_dev, "failed register driver: %d\n", ret); + goto free_freq_table; + } + + register_pm_notifier(&imx7_cpufreq_pm_notifier); + + of_node_put(np); + return 0; + +free_freq_table: + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); +put_node: + of_node_put(np); + + return ret; +} + +static int imx7d_cpufreq_remove(struct platform_device *pdev) +{ + cpufreq_unregister_driver(&imx7d_cpufreq_driver); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); + + return 0; +} + +static struct platform_driver imx7d_cpufreq_platdrv = { + .driver = { + .name = "imx7d-cpufreq", + .owner = THIS_MODULE, + }, + .probe = imx7d_cpufreq_probe, + .remove = imx7d_cpufreq_remove, +}; + +module_platform_driver(imx7d_cpufreq_platdrv); + +MODULE_DESCRIPTION("Freescale i.MX7D cpufreq driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/cpufreq/imx7ulp-cpufreq.c b/drivers/cpufreq/imx7ulp-cpufreq.c new file mode 100644 index 00000000000000..844a95e73ee7ba --- /dev/null +++ b/drivers/cpufreq/imx7ulp-cpufreq.c @@ -0,0 +1,284 @@ + /* + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_RUN_FREQ 528000 +#define SMC_PMPROT 0x8 +#define SMC_PMCTRL 0x10 + +static struct clk *arm_clk; +static struct clk *core_div; +static struct clk *sys_sel; +static struct clk *hsrun_sys_sel; +static struct clk *hsrun_core; +static struct clk *spll_pfd0; +static struct clk *spll_sel; +static struct clk *firc_clk; + +static struct pm_qos_request pm_qos_hsrun; + +static void __iomem *smc_base; + +static struct regulator *arm_reg; +static struct device *cpu_dev; +static struct cpufreq_frequency_table *freq_table; +static unsigned int transition_latency; +static struct mutex set_cpufreq_lock; + +static int imx7ulp_set_target(struct cpufreq_policy *policy, unsigned int index) +{ + struct dev_pm_opp *opp; + unsigned long freq_hz, volt, volt_old; + unsigned int old_freq, new_freq; + u32 val; + int ret; + + mutex_lock(&set_cpufreq_lock); + + new_freq = freq_table[index].frequency; + freq_hz = new_freq * 1000; + old_freq = clk_get_rate(arm_clk) / 1000; + + rcu_read_lock(); + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); + mutex_unlock(&set_cpufreq_lock); + return PTR_ERR(opp); + } + volt = dev_pm_opp_get_voltage(opp); + + rcu_read_unlock(); + volt_old = regulator_get_voltage(arm_reg); + + dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", + old_freq / 1000, volt_old / 1000, + new_freq / 1000, volt / 1000); + + /* Scaling up? scale voltage before frequency */ + if (new_freq > old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); + mutex_unlock(&set_cpufreq_lock); + return ret; + } + } + + /* before changing pll_arm rate, change the arm_src's soure + * to firc clk first. + */ + if (new_freq > MAX_RUN_FREQ) { + pm_qos_add_request(&pm_qos_hsrun, PM_QOS_CPU_DMA_LATENCY, 0); + clk_set_parent(sys_sel, firc_clk); + /* switch to HSRUN mode */ + val = readl_relaxed(smc_base + SMC_PMCTRL); + val |= (0x3 << 8); + writel_relaxed(val, smc_base + SMC_PMCTRL); + /* change the clock rate in HSRUN */ + clk_set_rate(spll_pfd0, new_freq * 1000); + clk_set_parent(hsrun_sys_sel, spll_sel); + clk_set_parent(arm_clk, hsrun_core); + } else { + /* change the HSRUN clock to firc */ + clk_set_parent(hsrun_sys_sel, firc_clk); + /* switch to RUN mode */ + val = readl_relaxed(smc_base + SMC_PMCTRL); + val &= ~(0x3 << 8); + writel_relaxed(val, smc_base + SMC_PMCTRL); + + clk_set_rate(spll_pfd0, new_freq * 1000); + clk_set_parent(sys_sel, spll_sel); + clk_set_parent(arm_clk, core_div); + if (old_freq > MAX_RUN_FREQ) + pm_qos_remove_request(&pm_qos_hsrun); + } + + /* scaling down? scaling voltage after frequency */ + if (new_freq < old_freq) { + ret = regulator_set_voltage_tol(arm_reg, volt, 0); + if (ret) { + dev_warn(cpu_dev, "failed to scale vddarm down: %d\n", ret); + ret = 0; + } + } + + mutex_unlock(&set_cpufreq_lock); + return 0; +} + +static int imx7ulp_cpufreq_init(struct cpufreq_policy *policy) +{ + int ret; + policy->clk = arm_clk; + policy->cur = clk_get_rate(arm_clk) / 1000; + policy->suspend_freq = freq_table[0].frequency; + + ret = cpufreq_generic_init(policy, freq_table, transition_latency); + + if (ret) { + dev_err(cpu_dev, "imx7ulp cpufreq init failed\n"); + return ret; + } + + return 0; +} + +static struct cpufreq_driver imx7ulp_cpufreq_driver = { + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = imx7ulp_set_target, + .get = cpufreq_generic_get, + .init = imx7ulp_cpufreq_init, + .name = "imx7ulp-cpufreq", + .attr = cpufreq_generic_attr, +#ifdef CONFIG_PM + .suspend = cpufreq_generic_suspend, +#endif +}; + +static int imx7ulp_cpufreq_probe(struct platform_device *pdev) +{ + struct device_node *np; + int ret; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) { + pr_err("failed to get cpu0 device\n"); + return -ENOENT; + } + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); + smc_base = of_iomap(np, 0); + of_node_put(np); + if (!smc_base) + return -ENOMEM; + + np = of_node_get(cpu_dev->of_node); + if (!np) { + dev_err(cpu_dev, "failed to find the cpu0 node\n"); + return -ENOENT; + } + + arm_clk = clk_get(cpu_dev, "arm"); + sys_sel = clk_get(cpu_dev, "sys_sel"); + core_div = clk_get(cpu_dev, "core_div"); + hsrun_sys_sel = clk_get(cpu_dev, "hsrun_sys_sel"); + hsrun_core = clk_get(cpu_dev, "hsrun_core"); + spll_pfd0 = clk_get(cpu_dev, "spll_pfd0"); + spll_sel = clk_get(cpu_dev, "spll_sel"); + firc_clk = clk_get(cpu_dev, "firc"); + + if (IS_ERR(arm_clk) || IS_ERR(sys_sel) || IS_ERR(spll_sel) || + IS_ERR(spll_sel) || IS_ERR(firc_clk) || IS_ERR(hsrun_sys_sel) || + IS_ERR(hsrun_core)) { + dev_err(cpu_dev, "failed to get cpu clock\n"); + ret = -ENOENT; + goto put_clk; + } + + arm_reg = regulator_get(cpu_dev, "arm"); + if (IS_ERR(arm_reg)) { + dev_err(cpu_dev, "failed to get regulator\n"); + ret = -ENOENT; + goto put_reg; + } + + ret = dev_pm_opp_of_add_table(cpu_dev); + if (ret < 0) { + dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); + goto put_reg; + } + + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); + if (ret) { + dev_err(cpu_dev, "failed to init cpufreq table\n"); + goto put_reg; + } + + if (of_property_read_u32(np, "clock-latency", &transition_latency)) + transition_latency = CPUFREQ_ETERNAL; + + mutex_init(&set_cpufreq_lock); + ret = cpufreq_register_driver(&imx7ulp_cpufreq_driver); + if (ret) { + dev_err(cpu_dev, "failed to register driver\n"); + goto free_opp_table; + } + + return 0; + +free_opp_table: + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); +put_reg: + regulator_put(arm_reg); +put_clk: + if (!IS_ERR(arm_clk)) + clk_put(arm_clk); + if (!IS_ERR(sys_sel)) + clk_put(sys_sel); + if (!IS_ERR(core_div)) + clk_put(core_div); + if (!IS_ERR(hsrun_sys_sel)) + clk_put(hsrun_sys_sel); + if (!IS_ERR(hsrun_core)) + clk_put(hsrun_core); + if (!IS_ERR(spll_pfd0)) + clk_put(spll_pfd0); + if (!IS_ERR(spll_sel)) + clk_put(spll_sel); + if (!IS_ERR(firc_clk)) + clk_put(firc_clk); + + return ret; +} + +static int imx7ulp_cpufreq_remove(struct platform_device *pdev) +{ + cpufreq_unregister_driver(&imx7ulp_cpufreq_driver); + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); + + regulator_put(arm_reg); + clk_put(arm_clk); + clk_put(sys_sel); + clk_put(core_div); + clk_put(hsrun_sys_sel); + clk_put(hsrun_core); + clk_put(spll_pfd0); + clk_put(spll_sel); + clk_put(firc_clk); + + return 0; +} + +static struct platform_driver imx7ulp_cpufreq_platdrv = { + .driver = { + .name = "imx7ulp-cpufreq", + .owner = THIS_MODULE, + }, + .probe = imx7ulp_cpufreq_probe, + .remove = imx7ulp_cpufreq_remove, +}; + +module_platform_driver(imx7ulp_cpufreq_platdrv); + +MODULE_DESCRIPTION("NXP i.MX7ULP cpufreq driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig index 64bf3024b68084..6741be76b20b5c 100644 --- a/drivers/crypto/caam/Kconfig +++ b/drivers/crypto/caam/Kconfig @@ -79,6 +79,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API select CRYPTO_AEAD select CRYPTO_AUTHENC select CRYPTO_BLKCIPHER + select CRYPTO_DES help Selecting this will offload crypto for users of the scatterlist crypto API (such as the linux native IPSec @@ -128,6 +129,57 @@ config CRYPTO_DEV_FSL_CAAM_IMX def_bool SOC_IMX6 || SOC_IMX7D depends on CRYPTO_DEV_FSL_CAAM + +config CRYPTO_DEV_FSL_CAAM_RNG_TEST + boolean "Test caam rng" + depends on CRYPTO_DEV_FSL_CAAM_RNG_API + default n + help + Selecting this will enable a self-test to run for the + caam RNG. This test is several minutes long and executes + just before the RNG is registered with the hw_random API. + +config CRYPTO_DEV_FSL_CAAM_SM + tristate "CAAM Secure Memory / Keystore API (EXPERIMENTAL)" + default n + help + Enables use of a prototype kernel-level Keystore API with CAAM + Secure Memory for insertion/extraction of bus-protected secrets. + +config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE + int "Size of each keystore slot in Secure Memory" + depends on CRYPTO_DEV_FSL_CAAM_SM + range 5 9 + default 7 + help + Select size of allocation units to divide Secure Memory pages into + (the size of a "slot" as referenced inside the API code). + Established as powers of two. + Examples: + 5 => 32 bytes + 6 => 64 bytes + 7 => 128 bytes + 8 => 256 bytes + 9 => 512 bytes + +config CRYPTO_DEV_FSL_CAAM_SM_TEST + tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)" + depends on CRYPTO_DEV_FSL_CAAM_SM + default n + help + Example thread to exercise the Keystore API and to verify that + stored and recovered secrets can be used for general purpose + encryption/decryption. + +config CRYPTO_DEV_FSL_CAAM_SECVIO + tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)" + depends on CRYPTO_DEV_FSL_CAAM + default n + help + Enables installation of an interrupt handler with registrable + handler functions which can be specified to act on the consequences + of a security violation. + config CRYPTO_DEV_FSL_CAAM_DEBUG bool "Enable debug output in CAAM driver" depends on CRYPTO_DEV_FSL_CAAM diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile index 08bf5515ae8a00..e09e7e20f76787 100644 --- a/drivers/crypto/caam/Makefile +++ b/drivers/crypto/caam/Makefile @@ -11,6 +11,9 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o caam-objs := ctrl.o caam_jr-objs := jr.o key_gen.o error.o diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index 0d743c634f25aa..04adcd33ef73ea 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -163,6 +163,9 @@ struct caam_aead_alg { bool registered; }; +static uint8_t *ecb_zero_iv; +static dma_addr_t ecb_ziv_dma; + /* Set DK bit in class 1 operation if shared */ static inline void append_dec_op1(u32 *desc, u32 type) { @@ -1755,6 +1758,33 @@ static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, return ret; } + +static int ablkcipher_des_setkey(struct crypto_ablkcipher *ablkcipher, + const u8 *key, unsigned int keylen) +{ + u32 tmp[DES_EXPKEY_WORDS]; + u32 flags; + int ret; + + if (keylen != DES_KEY_SIZE) { + crypto_ablkcipher_set_flags(ablkcipher, + CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + } + + ret = des_ekey(tmp, key); + + flags = crypto_ablkcipher_get_flags(ablkcipher); + if (!ret && (flags & CRYPTO_TFM_REQ_WEAK_KEY)) { + crypto_ablkcipher_set_flags(ablkcipher, + CRYPTO_TFM_RES_WEAK_KEY); + return -EINVAL; + } + + return ablkcipher_setkey(ablkcipher, key, keylen); +} + + static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, const u8 *key, unsigned int keylen) { @@ -2015,7 +2045,10 @@ static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, struct ablkcipher_request *req = context; struct ablkcipher_edesc *edesc; struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); + int bsize = crypto_ablkcipher_blocksize(ablkcipher); int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + size_t ivcopy = min_t(size_t, bsize, ivsize); #ifdef DEBUG dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); @@ -2047,6 +2080,12 @@ static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, kfree(edesc); + /* Pass IV along for cbc */ + if ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_CBC) { + scatterwalk_map_and_copy(req->info, req->dst, + req->nbytes - bsize, ivcopy, 0); + } + ablkcipher_request_complete(req, err); } @@ -2626,6 +2665,7 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request int sgc; int ivsize = crypto_ablkcipher_ivsize(ablkcipher); int sec4_sg_index; + uint32_t c1_alg_typ = ctx->class1_alg_type; src_nents = sg_count(req->src, req->nbytes); @@ -2642,10 +2682,17 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request DMA_FROM_DEVICE); } - iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE); - if (dma_mapping_error(jrdev, iv_dma)) { - dev_err(jrdev, "unable to map IV\n"); - return ERR_PTR(-ENOMEM); + if ((!req->info && ivsize) && + ((c1_alg_typ & OP_ALG_ALGSEL_MASK) == OP_ALG_ALGSEL_AES) && + ((c1_alg_typ & OP_ALG_AAI_MASK) == OP_ALG_AAI_ECB)) { + iv_dma = ecb_ziv_dma; + } else { + iv_dma = dma_map_single(jrdev, req->info, ivsize, + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, iv_dma)) { + dev_err(jrdev, "unable to map IV\n"); + return ERR_PTR(-ENOMEM); + } } /* @@ -2955,6 +3002,22 @@ static struct caam_alg_template driver_algs[] = { }, .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, }, + { + .name = "ecb(aes)", + .driver_name = "ecb-aes-caam", + .blocksize = AES_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, + }, { .name = "cbc(des3_ede)", .driver_name = "cbc-3des-caam", @@ -2972,6 +3035,22 @@ static struct caam_alg_template driver_algs[] = { }, .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, }, + { + .name = "ecb(des3_ede)", + .driver_name = "ecb-des3-caam", + .blocksize = DES3_EDE_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB, + }, { .name = "cbc(des)", .driver_name = "cbc-des-caam", @@ -2989,6 +3068,22 @@ static struct caam_alg_template driver_algs[] = { }, .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, }, + { + .name = "ecb(des)", + .driver_name = "ecb-des-caam", + .blocksize = DES_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_des_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB, + }, { .name = "ctr(aes)", .driver_name = "ctr-aes-caam", @@ -3040,6 +3135,23 @@ static struct caam_alg_template driver_algs[] = { }, .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS, }, + { + .name = "ecb(arc4)", + .driver_name = "ecb-arc4-caam", + .blocksize = ARC4_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = ARC4_MIN_KEY_SIZE, + .max_keysize = ARC4_MAX_KEY_SIZE, + .ivsize = ARC4_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB + }, + }; static struct caam_aead_alg driver_aeads[] = { @@ -4455,10 +4567,35 @@ static void caam_aead_exit(struct crypto_aead *tfm) static void __exit caam_algapi_exit(void) { - + struct device_node *dev_node; + struct platform_device *pdev; + struct device *ctrldev; struct caam_crypto_alg *t_alg, *n; int i; + if (!ecb_zero_iv) + goto skip_ecb_ziv; + + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + goto skip_ecb_ziv; + } + + pdev = of_find_device_by_node(dev_node); + + if (!pdev) { + of_node_put(dev_node); + goto skip_ecb_ziv; + } + + ctrldev = &pdev->dev; + + dma_unmap_single(ctrldev, ecb_ziv_dma, AES_BLOCK_SIZE, DMA_TO_DEVICE); + kfree(ecb_zero_iv); + +skip_ecb_ziv: for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) { struct caam_aead_alg *t_alg = driver_aeads + i; @@ -4500,8 +4637,12 @@ static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct caam_ctx); - alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | - template->type; + alg->cra_flags = CRYPTO_ALG_ASYNC | template->type; + +#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY + alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY; +#endif + switch (template->type) { case CRYPTO_ALG_TYPE_GIVCIPHER: alg->cra_type = &crypto_givcipher_type; @@ -4559,6 +4700,14 @@ static int __init caam_algapi_init(void) ctrldev = &pdev->dev; priv = dev_get_drvdata(ctrldev); + if (!priv) { + dev_err(ctrldev, "dev_get_drvdata failed\n"); + msleep(10); + priv = dev_get_drvdata(ctrldev); + if (!priv) + return -ENODEV; + dev_err(ctrldev, "dev_get_drvdata succeeded after pause\n"); + } of_node_put(dev_node); /* @@ -4568,6 +4717,16 @@ static int __init caam_algapi_init(void) if (!priv) return -ENODEV; + ecb_zero_iv = kzalloc(AES_BLOCK_SIZE, GFP_KERNEL); + if (!ecb_zero_iv) + return -ENOMEM; + + ecb_ziv_dma = dma_map_single(ctrldev, ecb_zero_iv, AES_BLOCK_SIZE, + DMA_TO_DEVICE); + if (dma_mapping_error(ctrldev, ecb_ziv_dma)) { + kfree(ecb_zero_iv); + return -ENOMEM; + } INIT_LIST_HEAD(&alg_list); diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c index 631337c2e4a74e..c0fe91d80ef507 100644 --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c @@ -62,6 +62,7 @@ #include "error.h" #include "sg_sw_sec4.h" #include "key_gen.h" +#include #define CAAM_CRA_PRIORITY 3000 @@ -115,6 +116,7 @@ struct caam_hash_ctx { u8 key[CAAM_MAX_HASH_KEY_SIZE]; dma_addr_t key_dma; int ctx_len; + unsigned int key_len; unsigned int split_key_len; unsigned int split_key_pad_len; }; @@ -232,6 +234,13 @@ static inline void append_key_ahash(u32 *desc, struct caam_hash_ctx *ctx) KEY_DEST_MDHA_SPLIT | KEY_ENC); } +static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx) +{ + append_key_as_imm(desc, ctx->key, ctx->key_len, + ctx->key_len, CLASS_1 | + KEY_DEST_CLASS_REG); +} + /* Append key if it has been set */ static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx) { @@ -253,6 +262,25 @@ static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx) append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); } +static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx) +{ + u32 *key_jump_cmd; + + init_sh_desc(desc, HDR_SHARE_SERIAL); + + if (ctx->key_len) { + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + append_key_axcbc(desc, ctx); + + set_jump_tgt_here(desc, key_jump_cmd); + } + + /* Propagate errors from shared to job descriptor */ + append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); + +} /* * For ahash read data from seqin following state->caam_ctx, * and write resulting class2 context to seqout, which may be state->caam_ctx @@ -272,6 +300,20 @@ static inline void ahash_append_load_str(u32 *desc, int digestsize) LDST_SRCDST_BYTE_CONTEXT); } +static inline void axcbc_append_load_str(u32 *desc, int digestsize) +{ + /* Calculate remaining bytes to read */ + append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); + + /* Read remaining bytes */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 | + FIFOLD_TYPE_MSG | KEY_VLF); + + /* Store class1 context bytes */ + append_seq_store(desc, digestsize, LDST_CLASS_1_CCB | + LDST_SRCDST_BYTE_CONTEXT); +} + /* * For ahash update, final and finup, import context, read and write to seqout */ @@ -294,6 +336,27 @@ static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state, ahash_append_load_str(desc, digestsize); } +/* + * For ahash update, final and finup, import context, read and write to seqout + */ +static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state, + int digestsize, + struct caam_hash_ctx *ctx) +{ + init_sh_desc_key_axcbc(desc, ctx); + + /* Import context from software */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | + LDST_CLASS_1_CCB | ctx->ctx_len); + + /* Class 1 operation */ + append_operation(desc, op | state | OP_ALG_ENCRYPT); + + /* + * Load from buf and/or src and write to req->result or state->context + */ + axcbc_append_load_str(desc, digestsize); +} /* For ahash firsts and digest, read and write to seqout */ static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state, int digestsize, struct caam_hash_ctx *ctx) @@ -309,6 +372,21 @@ static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state, ahash_append_load_str(desc, digestsize); } +/* For ahash firsts and digest, read and write to seqout */ +static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state, + int digestsize, struct caam_hash_ctx *ctx) +{ + init_sh_desc_key_axcbc(desc, ctx); + + /* Class 1 operation */ + append_operation(desc, op | state | OP_ALG_ENCRYPT); + + /* + * Load from buf and/or src and write to req->result or state->context + */ + axcbc_append_load_str(desc, digestsize); +} + static int ahash_set_sh_desc(struct crypto_ahash *ahash) { struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); @@ -426,6 +504,124 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash) return 0; } +static int axcbc_set_sh_desc(struct crypto_ahash *ahash) +{ + struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); + int digestsize = crypto_ahash_digestsize(ahash); + struct device *jrdev = ctx->jrdev; + u32 have_key = 0; + u32 *desc; + + /* ahash_update shared descriptor */ + desc = ctx->sh_desc_update; + + init_sh_desc(desc, HDR_SHARE_SERIAL); + + /* Import context from software */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | + LDST_CLASS_1_CCB | ctx->ctx_len); + + /* Class 1 operation */ + append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE | + OP_ALG_ENCRYPT); + + /* Load data and write to result or context */ + axcbc_append_load_str(desc, ctx->ctx_len); + + ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ahash update shdesc@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); +#endif + + /* ahash_update_first shared descriptor */ + desc = ctx->sh_desc_update_first; + + axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT, + ctx->ctx_len, ctx); + + ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ahash update first shdesc@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + /* ahash_final shared descriptor */ + desc = ctx->sh_desc_fin; + + axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type, + OP_ALG_AS_FINALIZE, digestsize, ctx); + + ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + /* ahash_finup shared descriptor */ + desc = ctx->sh_desc_finup; + + axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type, + OP_ALG_AS_FINALIZE, digestsize, ctx); + + ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + /* ahash_digest shared descriptor */ + desc = ctx->sh_desc_digest; + + axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL, + digestsize, ctx); + + ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ahash digest shdesc@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + return 0; +} static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in, u32 keylen) { @@ -582,6 +778,25 @@ static int ahash_setkey(struct crypto_ahash *ahash, return -EINVAL; } +static int axcbc_setkey(struct crypto_ahash *ahash, + const u8 *key, unsigned int keylen) +{ + struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); + int ret = 0; + + ctx->key_len = keylen; + memcpy(ctx->key, key, keylen); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, + ctx->key_len, 1); +#endif + + ret = axcbc_set_sh_desc(ahash); + + return ret; +} /* * ahash_edesc - s/w-extended ahash descriptor * @dst_dma: physical mapped address of req->result @@ -1826,6 +2041,29 @@ static struct caam_hash_template driver_hash[] = { .alg_type = OP_ALG_ALGSEL_MD5, .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC, }, + { + .name = "xcbc(aes)", + .driver_name = "xcbc-aes-caam", + .hmac_name = "xcbc(aes)", + .hmac_driver_name = "xcbc-aes-caam", + .blocksize = XCBC_MAC_BLOCK_WORDS * 4, + .template_ahash = { + .init = ahash_init, + .update = ahash_update, + .final = ahash_final, + .finup = ahash_finup, + .digest = ahash_digest, + .export = ahash_export, + .import = ahash_import, + .setkey = axcbc_setkey, + .halg = { + .digestsize = XCBC_MAC_DIGEST_SIZE, + .statesize = sizeof(struct caam_export_state), + }, + }, + .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC, + .alg_op = OP_ALG_ALGSEL_AES, + }, }; struct caam_hash_alg { @@ -1875,6 +2113,41 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) return ahash_set_sh_desc(ahash); } +static int caam_axcbc_cra_init(struct crypto_tfm *tfm) +{ + struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); + struct crypto_alg *base = tfm->__crt_alg; + struct hash_alg_common *halg = + container_of(base, struct hash_alg_common, base); + struct ahash_alg *alg = + container_of(halg, struct ahash_alg, halg); + struct caam_hash_alg *caam_hash = + container_of(alg, struct caam_hash_alg, ahash_alg); + struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); + int ret = 0; + + /* + * Get a Job ring from Job Ring driver to ensure in-order + * crypto request processing per tfm + */ + ctx->jrdev = caam_jr_alloc(); + if (IS_ERR(ctx->jrdev)) { + pr_err("Job Ring Device allocation for transform failed\n"); + return PTR_ERR(ctx->jrdev); + } + + /* copy descriptor header template value */ + ctx->alg_type = OP_TYPE_CLASS1_ALG | caam_hash->alg_type; + ctx->alg_op = OP_TYPE_CLASS1_ALG | caam_hash->alg_op; + + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), + sizeof(struct caam_hash_state)); + + ret = axcbc_set_sh_desc(ahash); + + return ret; +} + static void caam_hash_cra_exit(struct crypto_tfm *tfm) { struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); @@ -1951,7 +2224,11 @@ caam_hash_alloc(struct caam_hash_template *template, t_alg->ahash_alg.setkey = NULL; } alg->cra_module = THIS_MODULE; - alg->cra_init = caam_hash_cra_init; + + if (strstr(alg->cra_name, "xcbc") > 0) + alg->cra_init = caam_axcbc_cra_init; + else + alg->cra_init = caam_hash_cra_init; alg->cra_exit = caam_hash_cra_exit; alg->cra_ctxsize = sizeof(struct caam_hash_ctx); alg->cra_priority = CAAM_CRA_PRIORITY; @@ -2046,6 +2323,9 @@ static int __init caam_algapi_hash_init(void) } else list_add_tail(&t_alg->entry, &hash_list); + if (alg->alg_op == OP_ALG_ALGSEL_AES) + continue; + /* register unkeyed version */ t_alg = caam_hash_alloc(alg, false); if (IS_ERR(t_alg)) { diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c index 9b92af2c72412f..601381c239d8fc 100644 --- a/drivers/crypto/caam/caamrng.c +++ b/drivers/crypto/caam/caamrng.c @@ -256,6 +256,49 @@ static void caam_cleanup(struct hwrng *rng) rng_unmap_ctx(rng_ctx); } +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST +static inline void test_len(struct hwrng *rng, size_t len, bool wait) +{ + u8 *buf; + int real_len; + + buf = kzalloc(sizeof(u8) * len, GFP_KERNEL); + real_len = rng->read(rng, buf, len, wait); + if (real_len == 0 && wait) + pr_err("WAITING FAILED\n"); + pr_info("wanted %d bytes, got %d\n", len, real_len); + print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS, + 16, 4, buf, real_len, 1); + kfree(buf); +} + +static inline void test_mode_once(struct hwrng *rng, bool wait) +{ +#define TEST_CHUNK (RN_BUF_SIZE / 4) + + test_len(rng, TEST_CHUNK, wait); + test_len(rng, RN_BUF_SIZE * 2, wait); + test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait); +} + +static inline void test_mode(struct hwrng *rng, bool wait) +{ +#define TEST_PASS 1 + int i; + + for (i = 0; i < TEST_PASS; i++) + test_mode_once(rng, wait); +} + +static void self_test(struct hwrng *rng) +{ + pr_info("testing without waiting\n"); + test_mode(rng, false); + pr_info("testing with waiting\n"); + test_mode(rng, true); +} +#endif + static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) { struct buf_data *bd = &ctx->bufs[buf_id]; @@ -360,6 +403,10 @@ static int __init caam_rng_init(void) if (err) goto free_rng_ctx; +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST + self_test(&caam_rng); +#endif + dev_info(dev, "registering rng-caam\n"); return hwrng_register(&caam_rng); diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 98468b96c32f81..e3147d7a416f23 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -15,6 +15,7 @@ #include "desc_constr.h" #include "error.h" #include "ctrl.h" +#include "sm.h" bool caam_little_end; EXPORT_SYMBOL(caam_little_end); @@ -378,8 +379,8 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) wr_reg32(&r4tst->rtsdctl, val); /* min. freq. count, equal to 1/4 of the entropy sample length */ wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); - /* disable maximum frequency count */ - wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); + /* max. freq. count, equal to 16 times the entropy sample length */ + wr_reg32(&r4tst->rtfrqmax, ent_delay << 4); /* read the control register */ val = rd_reg32(&r4tst->rtmctl); /* @@ -393,23 +394,115 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) wr_reg32(&r4tst->rtmctl, val); } -/** - * caam_get_era() - Return the ERA of the SEC on SoC, based - * on "sec-era" propery in the DTS. This property is updated by u-boot. - **/ -int caam_get_era(void) +static void detect_era(struct caam_drv_private *ctrlpriv) { + int ret, i; + u32 caam_era; + u32 caam_id_ms; + char *era_source; struct device_node *caam_node; - int ret; - u32 prop; - + struct sec_vid sec_vid; + static const struct { + u16 ip_id; + u8 maj_rev; + u8 era; + } caam_eras[] = { + {0x0A10, 1, 1}, + {0x0A10, 2, 2}, + {0x0A12, 1, 3}, + {0x0A14, 1, 3}, + {0x0A10, 3, 4}, + {0x0A11, 1, 4}, + {0x0A14, 2, 4}, + {0x0A16, 1, 4}, + {0x0A18, 1, 4}, + {0x0A11, 2, 5}, + {0x0A12, 2, 5}, + {0x0A13, 1, 5}, + {0x0A1C, 1, 5}, + {0x0A12, 4, 6}, + {0x0A13, 2, 6}, + {0x0A16, 2, 6}, + {0x0A17, 1, 6}, + {0x0A18, 2, 6}, + {0x0A1A, 1, 6}, + {0x0A1C, 2, 6}, + {0x0A14, 3, 7}, + {0x0A10, 4, 8}, + {0x0A11, 3, 8}, + {0x0A11, 4, 8}, + {0x0A12, 5, 8}, + {0x0A16, 3, 8}, + }; + + /* If the user or bootloader has set the property we'll use that */ caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); + ret = of_property_read_u32(caam_node, "fsl,sec-era", &caam_era); of_node_put(caam_node); - return ret ? -ENOTSUPP : prop; + if (!ret) { + era_source = "device tree"; + goto era_found; + } + + /* If ccbvid has the era, use that (era 6 and onwards) */ + caam_era = rd_reg32(&ctrlpriv->ctrl->perfmon.ccb_id); + caam_era = caam_era >> CCB_VID_ERA_SHIFT & CCB_VID_ERA_MASK; + + if (caam_era) { + era_source = "CCBVID"; + goto era_found; + } + + /* If we can match caamvid to known versions, use that */ + caam_id_ms = rd_reg32(&ctrlpriv->ctrl->perfmon.caam_id_ms); + sec_vid.ip_id = caam_id_ms >> SEC_VID_IPID_SHIFT; + sec_vid.maj_rev = (caam_id_ms & SEC_VID_MAJ_MASK) >> SEC_VID_MAJ_SHIFT; + + for (i = 0; i < ARRAY_SIZE(caam_eras); i++) + if (caam_eras[i].ip_id == sec_vid.ip_id && + caam_eras[i].maj_rev == sec_vid.maj_rev) { + caam_era = caam_eras[i].era; + era_source = "CAAMVID"; + goto era_found; + } + + ctrlpriv->era = -ENOTSUPP; + return; + +era_found: + ctrlpriv->era = caam_era; + dev_info(&ctrlpriv->pdev->dev, "ERA source: %s.\n", era_source); +} + +static void handle_imx6_err005766(struct caam_drv_private *ctrlpriv) +{ + /* + * ERRATA: mx6 devices have an issue wherein AXI bus transactions + * may not occur in the correct order. This isn't a problem running + * single descriptors, but can be if running multiple concurrent + * descriptors. Reworking the driver to throttle to single requests + * is impractical, thus the workaround is to limit the AXI pipeline + * to a depth of 1 (from it's default of 4) to preclude this situation + * from occurring. + */ + + u32 mcr_val; + + if (ctrlpriv->era != IMX_ERR005766_ERA) + return; + + if (of_machine_is_compatible("fsl,imx6q") || + of_machine_is_compatible("fsl,imx6dl") || + of_machine_is_compatible("fsl,imx6qp")) { + dev_info(&ctrlpriv->pdev->dev, + "AXI pipeline throttling enabled.\n"); + mcr_val = rd_reg32(&ctrlpriv->ctrl->mcr); + wr_reg32(&ctrlpriv->ctrl->mcr, + (mcr_val & ~(MCFGR_AXIPIPE_MASK)) | + ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK)); + } } -EXPORT_SYMBOL(caam_get_era); #ifdef CONFIG_DEBUG_FS static int caam_debugfs_u64_get(void *data, u64 *val) @@ -465,57 +558,63 @@ static int caam_probe(struct platform_device *pdev) } ctrlpriv->caam_ipg = clk; - clk = caam_drv_identify_clk(&pdev->dev, "mem"); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - dev_err(&pdev->dev, - "can't identify CAAM mem clk: %d\n", ret); + ret = clk_prepare_enable(ctrlpriv->caam_ipg); + if (ret < 0) { + dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); return ret; } - ctrlpriv->caam_mem = clk; clk = caam_drv_identify_clk(&pdev->dev, "aclk"); if (IS_ERR(clk)) { ret = PTR_ERR(clk); dev_err(&pdev->dev, "can't identify CAAM aclk clk: %d\n", ret); - return ret; + goto disable_clocks; } ctrlpriv->caam_aclk = clk; - clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - dev_err(&pdev->dev, - "can't identify CAAM emi_slow clk: %d\n", ret); - return ret; - } - ctrlpriv->caam_emi_slow = clk; - - ret = clk_prepare_enable(ctrlpriv->caam_ipg); - if (ret < 0) { - dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(ctrlpriv->caam_mem); + ret = clk_prepare_enable(ctrlpriv->caam_aclk); if (ret < 0) { - dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", + dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); - goto disable_caam_ipg; + goto disable_clocks; } - ret = clk_prepare_enable(ctrlpriv->caam_aclk); - if (ret < 0) { - dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); - goto disable_caam_mem; - } + if (!(of_find_compatible_node(NULL, NULL, "fsl,imx7d-caam"))) { - ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); - if (ret < 0) { - dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", - ret); - goto disable_caam_aclk; + clk = caam_drv_identify_clk(&pdev->dev, "mem"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(&pdev->dev, + "can't identify CAAM mem clk: %d\n", ret); + goto disable_clocks; + } + ctrlpriv->caam_mem = clk; + + ret = clk_prepare_enable(ctrlpriv->caam_mem); + if (ret < 0) { + dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", + ret); + goto disable_clocks; + } + + if (!(of_find_compatible_node(NULL, NULL, "fsl,imx6ul-caam"))) { + clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(&pdev->dev, + "can't identify CAAM emi_slow clk: %d\n", ret); + goto disable_clocks; + } + ctrlpriv->caam_emi_slow = clk; + + ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); + if (ret < 0) { + dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", + ret); + goto disable_clocks; + } + } } /* Get configuration properties from device tree */ @@ -524,7 +623,7 @@ static int caam_probe(struct platform_device *pdev) if (ctrl == NULL) { dev_err(dev, "caam: of_iomap() failed\n"); ret = -ENOMEM; - goto disable_caam_emi_slow; + goto disable_clocks; } caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & @@ -552,8 +651,15 @@ static int caam_probe(struct platform_device *pdev) BLOCK_OFFSET * DECO_BLOCK_NUMBER ); - /* Get the IRQ of the controller (for security violations only) */ - ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); + detect_era(ctrlpriv); + + /* Get CAAM-SM node and of_iomap() and save */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (!np) + return -ENODEV; + + ctrlpriv->sm_base = of_iomap(np, 0); + ctrlpriv->sm_size = 0x3fff; /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, @@ -564,6 +670,8 @@ static int caam_probe(struct platform_device *pdev) MCFGR_WDENABLE | MCFGR_LARGE_BURST | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + handle_imx6_err005766(ctrlpriv); + /* * Read the Compile Time paramters and SCFGR to determine * if Virtualization is enabled for this platform @@ -590,6 +698,7 @@ static int caam_probe(struct platform_device *pdev) JRSTART_JR1_START | JRSTART_JR2_START | JRSTART_JR3_START); + /* Set DMA masks according to platform ranging */ if (sizeof(dma_addr_t) == sizeof(u64)) if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); @@ -728,9 +837,9 @@ static int caam_probe(struct platform_device *pdev) caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); - /* Report "alive" for developer to see */ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, - caam_get_era()); + ctrlpriv->era); + dev_info(dev, "job rings = %d, qi = %d\n", ctrlpriv->total_jobrs, ctrlpriv->qi_present); @@ -833,13 +942,10 @@ static int caam_probe(struct platform_device *pdev) iounmap_ctrl: iounmap(ctrl); -disable_caam_emi_slow: +disable_clocks: clk_disable_unprepare(ctrlpriv->caam_emi_slow); -disable_caam_aclk: clk_disable_unprepare(ctrlpriv->caam_aclk); -disable_caam_mem: clk_disable_unprepare(ctrlpriv->caam_mem); -disable_caam_ipg: clk_disable_unprepare(ctrlpriv->caam_ipg); return ret; } diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h index cac5402a46ebab..d52e8830d409d9 100644 --- a/drivers/crypto/caam/ctrl.h +++ b/drivers/crypto/caam/ctrl.h @@ -1,13 +1,12 @@ /* * CAAM control-plane driver backend public-level include definitions * - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2015 Freescale Semiconductor, Inc. */ #ifndef CTRL_H #define CTRL_H /* Prototypes for backend-level services exposed to APIs */ -int caam_get_era(void); #endif /* CTRL_H */ diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h index 513b6646bb36ae..62474d9c2f72eb 100644 --- a/drivers/crypto/caam/desc.h +++ b/drivers/crypto/caam/desc.h @@ -2,7 +2,7 @@ * CAAM descriptor composition header * Definitions to support CAAM descriptor instruction generation * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. */ #ifndef DESC_H @@ -400,7 +400,10 @@ struct sec4_sg_entry { #define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) -#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT) @@ -1104,6 +1107,23 @@ struct sec4_sg_entry { #define OP_PCL_PKPROT_ECC 0x0002 #define OP_PCL_PKPROT_F2M 0x0001 +/* Blob protocol protinfo bits */ +#define OP_PCL_BLOB_TK 0x0200 +#define OP_PCL_BLOB_EKT 0x0100 + +#define OP_PCL_BLOB_K2KR_MEM 0x0000 +#define OP_PCL_BLOB_K2KR_C1KR 0x0010 +#define OP_PCL_BLOB_K2KR_C2KR 0x0030 +#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 +#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 + +#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 +#define OP_PCL_BLOB_BLACK 0x0004 + +#define OP_PCL_BLOB_FMT_NORMAL 0x0000 +#define OP_PCL_BLOB_FMT_MSTR 0x0002 +#define OP_PCL_BLOB_FMT_TEST 0x0003 + /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) @@ -1629,4 +1649,12 @@ struct sec4_sg_entry { /* Frame Descriptor Command for Replacement Job Descriptor */ #define FD_CMD_REPLACE_JOB_DESC 0x20000000 +#define ARC4_BLOCK_SIZE 1 +#define ARC4_MAX_KEY_SIZE 256 +#define ARC4_MIN_KEY_SIZE 1 + +#define XCBC_MAC_DIGEST_SIZE 16 +#define XCBC_MAC_BLOCK_WORDS 16 + + #endif /* DESC_H */ diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c index 33e41ea83fcca2..918061db4134d4 100644 --- a/drivers/crypto/caam/error.c +++ b/drivers/crypto/caam/error.c @@ -117,6 +117,20 @@ static const char * const rng_err_id_list[] = { "Secure key generation", }; +#define SPRINTFCAT(str, format, param, max_alloc) \ +{ \ + char *tmp; \ + \ + tmp = kmalloc(sizeof(format) + max_alloc, GFP_ATOMIC); \ + if (likely(tmp)) { \ + sprintf(tmp, format, param); \ + strcat(str, tmp); \ + kfree(tmp); \ + } else { \ + strcat(str, "kmalloc failure in SPRINTFCAT"); \ + } \ +} + static void report_ccb_status(struct device *jrdev, const u32 status, const char *error) { diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index e2bcacc1a92167..785876439b9bbd 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h @@ -66,15 +66,25 @@ struct caam_drv_private_jr { struct caam_drv_private { struct device *dev; + struct device *smdev; struct platform_device **jrpdev; /* Alloc'ed array per sub-device */ struct platform_device *pdev; + /* + * ERA of the CAAM block, + * -ENOTSUPP if no era version was supplied or detected. + */ +#define IMX_ERR005766_ERA 4 /* ERA affected by i.mx AXI errata */ + int era; + /* Physical-presence section */ struct caam_ctrl __iomem *ctrl; /* controller region */ struct caam_deco __iomem *deco; /* DECO/CCB views */ struct caam_assurance __iomem *assure; struct caam_queue_if __iomem *qi; /* QI control region */ struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ + dma_addr_t __iomem *sm_base; /* Secure memory storage base */ + u32 sm_size; /* * Detected geometry block. Filled in from device tree if powerpc, @@ -82,7 +92,6 @@ struct caam_drv_private { */ u8 total_jobrs; /* Total Job Rings in device */ u8 qi_present; /* Nonzero if QI present in device */ - int secvio_irq; /* Security violation interrupt number */ int virt_en; /* Virtualization enabled in CAAM */ #define RNG4_MAX_HANDLES 2 diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 9e7f28122bb7fe..0a88728a1bd9a6 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -2,7 +2,7 @@ * CAAM/SEC 4.x transport/backend driver * JobR backend functionality * - * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Copyright 2008-2015 Freescale Semiconductor, Inc. */ #include @@ -296,8 +296,7 @@ EXPORT_SYMBOL(caam_jr_free); * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, * -EBUSY if the queue is full, -EIO if it cannot map the caller's * descriptor. - * @dev: device of the job ring to be used. This device should have - * been assigned prior by caam_jr_register(). + * @dev: device of the job ring to be used. * @desc: points to a job descriptor that execute our request. All * descriptors (and all referenced data) must be in a DMAable * region, and all data references must be physical addresses @@ -508,6 +507,10 @@ static int caam_jr_probe(struct platform_device *pdev) /* Identify the interrupt */ jrpriv->irq = irq_of_parse_and_map(nprop, 0); + if (jrpriv->irq <= 0) { + kfree(jrpriv); + return -EINVAL; + } /* Now do the platform independent part */ error = caam_jr_init(jrdev); /* now turn on hardware */ @@ -515,7 +518,7 @@ static int caam_jr_probe(struct platform_device *pdev) irq_dispose_mapping(jrpriv->irq); iounmap(ctrl); return error; - } + } jrpriv->dev = jrdev; spin_lock(&driver_data.jr_alloc_lock); @@ -524,9 +527,39 @@ static int caam_jr_probe(struct platform_device *pdev) atomic_set(&jrpriv->tfm_count, 0); + device_init_wakeup(&pdev->dev, 1); + device_set_wakeup_enable(&pdev->dev, false); + + return 0; +} + +#ifdef CONFIG_PM +static int caam_jr_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + + if (device_may_wakeup(&pdev->dev)) + enable_irq_wake(jrpriv->irq); + + return 0; +} + +static int caam_jr_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + + if (device_may_wakeup(&pdev->dev)) + disable_irq_wake(jrpriv->irq); + return 0; } +static SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend, + caam_jr_resume); +#endif + static struct of_device_id caam_jr_match[] = { { .compatible = "fsl,sec-v4.0-job-ring", @@ -542,6 +575,9 @@ static struct platform_driver caam_jr_driver = { .driver = { .name = "caam_jr", .of_match_table = caam_jr_match, +#ifdef CONFIG_PM + .pm = &caam_jr_pm_ops, +#endif }, .probe = caam_jr_probe, .remove = caam_jr_remove, diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 84d2f838a063cc..0565a07e3fd40b 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -271,12 +271,26 @@ struct jr_outentry { #define CHA_ID_MS_JR_SHIFT 28 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) +/* + * caam_perfmon - Performance Monitor/Secure Memory Status/ + * CAAM Global Status/Component Version IDs + * + * Spans f00-fff wherever instantiated + */ + struct sec_vid { u16 ip_id; u8 maj_rev; u8 min_rev; }; +#define SEC_VID_IPID_SHIFT 16 +#define SEC_VID_MAJ_SHIFT 8 +#define SEC_VID_MAJ_MASK 0x0000FF00 + +#define CCB_VID_ERA_SHIFT 24 +#define CCB_VID_ERA_MASK 0x000000FF + struct caam_perfmon { /* Performance Monitor Registers f00-f9f */ u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ @@ -299,17 +313,22 @@ struct caam_perfmon { #define CTPR_MS_PG_SZ_SHIFT 4 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ - u64 rsvd1[2]; + /* Secure Memory State Visibility */ + u32 rsvd1; + u32 smstatus; /* Secure memory status */ + u32 rsvd2; + u32 smpartown; /* Secure memory partition owner */ /* CAAM Global Status fc0-fdf */ u64 faultaddr; /* FAR - Fault Address */ u32 faultliodn; /* FALR - Fault Address LIODN */ u32 faultdetail; /* FADR - Fault Addr Detail */ - u32 rsvd2; #define CSTA_PLEND BIT(10) #define CSTA_ALT_PLEND BIT(18) + u32 rsvd3; u32 status; /* CSTA - CAAM Status */ - u64 rsvd3; + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ /* Component Instantiation Parameters fe0-fff */ u32 rtic_id; /* RVID - RTIC Version ID */ @@ -322,6 +341,62 @@ struct caam_perfmon { u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ }; +#define SMSTATUS_PART_SHIFT 28 +#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) +#define SMSTATUS_PAGE_SHIFT 16 +#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) +#define SMSTATUS_MID_SHIFT 8 +#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) +#define SMSTATUS_ACCERR_SHIFT 4 +#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) +#define SMSTATUS_ACCERR_NONE 0 +#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ +#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ +#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ +#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ +#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ +#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ +#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ +#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ +#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ +#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ +#define SMSTATUS_STATE_SHIFT 0 +#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) +#define SMSTATUS_STATE_RESET 0 +#define SMSTATUS_STATE_INIT 1 +#define SMSTATUS_STATE_NORMAL 2 +#define SMSTATUS_STATE_FAIL 3 + +/* up to 15 rings, 2 bits shifted by ring number */ +#define SMPARTOWN_RING_SHIFT 2 +#define SMPARTOWN_RING_MASK 3 +#define SMPARTOWN_AVAILABLE 0 +#define SMPARTOWN_NOEXIST 1 +#define SMPARTOWN_UNAVAILABLE 2 +#define SMPARTOWN_OURS 3 + +/* Maximum number of pages possible */ +#define SMPART_MAX_NUMPG_SHIFT 16 +#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) + +/* Maximum partition number */ +#define SMPART_MAX_PNUM_SHIFT 12 +#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) + +/* Highest possible page number */ +#define SMPART_MAX_PG_SHIFT 0 +#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) + +/* Max size of a page */ +#define SMVID_PG_SIZE_SHIFT 16 +#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) + +/* Major/Minor Version ID */ +#define SMVID_MAJ_VERS_SHIFT 8 +#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) +#define SMVID_MIN_VERS_SHIFT 0 +#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) + /* LIODN programming for DMA configuration */ #define MSTRID_LOCK_LIODN 0x80000000 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ @@ -523,6 +598,35 @@ struct caam_ctrl { #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ +/* Secure Memory Configuration - if you have it */ +/* Secure Memory Register Offset from JR Base Reg*/ +#define SM_V1_OFFSET 0x0f4 +#define SM_V2_OFFSET 0xa00 + +/* Minimum SM Version ID requiring v2 SM register mapping */ +#define SMVID_V2 0x20105 + +struct caam_secure_mem_v1 { + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd1; + u32 sm_status; /* SMCSJRx - Secure memory status */ + u32 rsvd2; + + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ +}; + +struct caam_secure_mem_v2 { + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ + u32 rsvd1[118]; + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd2; + u32 sm_status; /* SMCSJRx - Secure memory status */ +}; + /* * caam_job_ring - direct job ring setup * 1-4 possible per instantiation, base + 1000/2000/3000/4000 @@ -564,8 +668,7 @@ struct caam_job_ring { /* Command/control */ u32 rsvd11; u32 jrcommand; /* JRCRx - JobR command */ - - u32 rsvd12[932]; + u32 rsvd12[931]; /* Performance Monitor f00-fff */ struct caam_perfmon perfmon; @@ -688,6 +791,62 @@ struct caam_job_ring { #define JRCR_RESET 0x01 +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) +#define SMC_PART_SHIFT 8 +#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) +#define SMC_CMD_SHIFT 0 +#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ +#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ + +/* secure memory (command) status */ +#define SMCS_PAGE_SHIFT 16 +#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) +#define SMCS_CMDERR_SHIFT 14 +#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) +#define SMCS_ALCERR_SHIFT 12 +#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) +#define SMCS_PGOWN_SHIFT 6 +#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) +#define SMCS_PART_SHIFT 0 +#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) + +#define SMCS_CMDERR_NONE 0 +#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ +#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ +#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ + +#define SMCS_ALCERR_NONE 0 +#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ +#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ +#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ + +#define SMCS_PGOWN_AVAIL 0 /* Page is available */ +#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ +#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ +#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ + +/* secure memory access permissions */ +#define SMCS_PERM_KEYMOD_SHIFT 16 +#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) +#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ +#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ +#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ +#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ +#define SMCA_PERM_RINGID_SHIFT 10 +#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) +#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ +#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ +#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ +#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ +#define SMCA_PERM_G1_WRITE 0x0002 +#define SMCA_PERM_G1_READ 0x0001 + /* * caam_assurance - Assurance Controller View * base + 0x6000 padded out to 0x1000 diff --git a/drivers/crypto/caam/secvio.c b/drivers/crypto/caam/secvio.c new file mode 100644 index 00000000000000..4bbebb9d341d6e --- /dev/null +++ b/drivers/crypto/caam/secvio.c @@ -0,0 +1,332 @@ + +/* + * SNVS Security Violation Handler + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc., All Rights Reserved + */ + +#include "compat.h" +#include "intern.h" +#include "secvio.h" +#include "regs.h" +#include +#include +#include +/* + * These names are associated with each violation handler. + * The source names were taken from MX6, and are based on recommendations + * for most common SoCs. + */ +static const u8 *violation_src_name[] = { + "CAAM Internal Security Violation", + "JTAG Alarm", + "Watchdog", + "(reserved)", + "External Boot", + "External Tamper Detect", +}; + +/* These names help describe security monitor state for the console */ +static const u8 *snvs_ssm_state_name[] = { + "init", + "hard fail", + "(undef:2)", + "soft fail", + "(undef:4)", + "(undef:5)", + "(undef:6)", + "(undef:7)", + "transition", + "check", + "(undef:10)", + "non-secure", + "(undef:12)", + "trusted", + "(undef:14)", + "secure", +}; + +/* Top-level security violation interrupt */ +static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev) +{ + struct device *dev = snvsdev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + clk_enable(svpriv->clk); + /* Check the HP secvio status register */ + svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) & + HP_SECVIOST_SECVIOMASK; + + if (!svpriv->irqcause) { + clk_disable(svpriv->clk); + return IRQ_NONE; + } + + /* Now ACK cause */ + clrsetbits_32(&svpriv->svregs->hp.secvio_status, 0, svpriv->irqcause); + + /* And run deferred service */ + preempt_disable(); + tasklet_schedule(&svpriv->irqtask[smp_processor_id()]); + preempt_enable(); + + clk_disable(svpriv->clk); + + return IRQ_HANDLED; +} + +/* Deferred service handler. Tasklet arg is simply the SNVS dev */ +static void snvs_secvio_dispatch(unsigned long indev) +{ + struct device *dev = (struct device *)indev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + unsigned long flags; + int i; + + + /* Look through stored causes, call each handler if exists */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) + if (svpriv->irqcause & (1 << i)) { + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[i].handler(dev, i, + svpriv->intsrc[i].ext); + spin_unlock_irqrestore(&svpriv->svlock, flags); + }; + + /* Re-enable now-serviced interrupts */ + clrsetbits_32(&svpriv->svregs->hp.secvio_intcfg, 0, svpriv->irqcause); +} + +/* + * Default cause handler, used in lieu of an application-defined handler. + * All it does at this time is print a console message. It could force a halt. + */ +static void snvs_secvio_default(struct device *dev, u32 cause, void *ext) +{ + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n", + cause, svpriv->intsrc[cause].intname); +} + +/* + * Install an application-defined handler for a specified cause + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + * - handler application-defined handler, gets called with dev + * source cause, and locally-defined handler argument + * - cause_description points to a string to override the default cause + * name, this can be used as an alternate for error + * messages and such. If left NULL, the default + * description string is used. + * - ext pointer to any extra data needed by the handler. + */ +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5)) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].handler = handler; + if (cause_description != NULL) + svpriv->intsrc[cause].intname = cause_description; + if (ext != NULL) + svpriv->intsrc[cause].ext = ext; + spin_unlock_irqrestore(&svpriv->svlock, flags); + + return 0; +} +EXPORT_SYMBOL(snvs_secvio_install_handler); + +/* + * Remove an application-defined handler for a specified cause (and, by + * implication, restore the "default". + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + */ +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if (cause > SECVIO_CAUSE_SOURCE_5) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].intname = violation_src_name[cause]; + svpriv->intsrc[cause].handler = snvs_secvio_default; + svpriv->intsrc[cause].ext = NULL; + spin_unlock_irqrestore(&svpriv->svlock, flags); + return 0; +} +EXPORT_SYMBOL(snvs_secvio_remove_handler); + +static int snvs_secvio_remove(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + int i; + + svdev = &pdev->dev; + svpriv = dev_get_drvdata(svdev); + + clk_enable(svpriv->clk); + /* Set all sources to nonfatal */ + wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0); + + /* Remove tasklets and release interrupt */ + for_each_possible_cpu(i) + tasklet_kill(&svpriv->irqtask[i]); + + clk_disable_unprepare(svpriv->clk); + free_irq(svpriv->irq, svdev); + iounmap(svpriv->svregs); + kfree(svpriv); + + return 0; +} + +static int snvs_secvio_probe(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + struct device_node *np, *npirq; + struct snvs_full __iomem *snvsregs; + int i, error; + u32 hpstate; + const void *jtd, *wtd, *itd, *etd; + u32 td_en; + + svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL); + if (!svpriv) + return -ENOMEM; + + svdev = &pdev->dev; + dev_set_drvdata(svdev, svpriv); + svpriv->pdev = pdev; + np = pdev->dev.of_node; + + npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio"); + if (!npirq) { + dev_err(svdev, "can't identify secvio interrupt\n"); + kfree(svpriv); + return -EINVAL; + } + svpriv->irq = irq_of_parse_and_map(npirq, 0); + if (svpriv->irq <= 0) { + kfree(svpriv); + return -EINVAL; + } + + jtd = of_get_property(npirq, "jtag-tamper", NULL); + wtd = of_get_property(npirq, "watchdog-tamper", NULL); + itd = of_get_property(npirq, "internal-boot-tamper", NULL); + etd = of_get_property(npirq, "external-pin-tamper", NULL); + if (!jtd | !wtd | !itd | !etd ) { + dev_err(svdev, "can't identify tamper alarm configuration\n"); + kfree(svpriv); + return -EINVAL; + } + + /* + * Configure all sources according to device tree property. + * If the property is enabled then the source is ser as + * fatal violations except LP section, + * source #5 (typically used as an external tamper detect), and + * source #3 (typically unused). Whenever the transition to + * secure mode has occurred, these will now be "fatal" violations + */ + td_en = HP_SECVIO_INTEN_SRC0; + if (!strcmp(jtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC1; + if (!strcmp(wtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC2; + if (!strcmp(itd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC4; + if (!strcmp(etd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC5; + + snvsregs = of_iomap(np, 0); + if (!snvsregs) { + dev_err(svdev, "register mapping failed\n"); + return -ENOMEM; + } + svpriv->svregs = (struct snvs_full __force *)snvsregs; + + svpriv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(svpriv->clk)) { + dev_err(&pdev->dev, "can't get snvs clock\n"); + svpriv->clk = NULL; + } + + /* Write the Secvio Enable Config the SVCR */ + wr_reg32(&svpriv->svregs->hp.secvio_ctl, td_en); + wr_reg32(&svpriv->svregs->hp.secvio_intcfg, td_en); + + /* Device data set up. Now init interrupt source descriptions */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) { + svpriv->intsrc[i].intname = violation_src_name[i]; + svpriv->intsrc[i].handler = snvs_secvio_default; + } + /* Connect main handler */ + for_each_possible_cpu(i) + tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch, + (unsigned long)svdev); + + error = request_irq(svpriv->irq, snvs_secvio_interrupt, + IRQF_SHARED, "snvs-secvio", svdev); + if (error) { + dev_err(svdev, "can't connect secvio interrupt\n"); + irq_dispose_mapping(svpriv->irq); + svpriv->irq = 0; + iounmap(svpriv->svregs); + kfree(svpriv); + return -EINVAL; + } + + clk_prepare_enable(svpriv->clk); + + hpstate = (rd_reg32(&svpriv->svregs->hp.status) & + HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT; + dev_info(svdev, "violation handlers armed - %s state\n", + snvs_ssm_state_name[hpstate]); + + clk_disable(svpriv->clk); + + return 0; +} + +static struct of_device_id snvs_secvio_match[] = { + { + .compatible = "fsl,imx6q-caam-snvs", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, snvs_secvio_match); + +static struct platform_driver snvs_secvio_driver = { + .driver = { + .name = "snvs-secvio", + .owner = THIS_MODULE, + .of_match_table = snvs_secvio_match, + }, + .probe = snvs_secvio_probe, + .remove = snvs_secvio_remove, +}; + +module_platform_driver(snvs_secvio_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL SNVS Security Violation Handler"); +MODULE_AUTHOR("Freescale Semiconductor - MCU"); diff --git a/drivers/crypto/caam/secvio.h b/drivers/crypto/caam/secvio.h new file mode 100644 index 00000000000000..97eb2723f19ce1 --- /dev/null +++ b/drivers/crypto/caam/secvio.h @@ -0,0 +1,67 @@ + +/* + * CAAM Security Violation Handler + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved + */ + +#ifndef SECVIO_H +#define SECVIO_H + +#include "snvsregs.h" + + +/* + * Defines the published interfaces to install/remove application-specified + * handlers for catching violations + */ + +#define MAX_SECVIO_SOURCES 6 + +/* these are the untranslated causes */ +enum secvio_cause { + SECVIO_CAUSE_SOURCE_0, + SECVIO_CAUSE_SOURCE_1, + SECVIO_CAUSE_SOURCE_2, + SECVIO_CAUSE_SOURCE_3, + SECVIO_CAUSE_SOURCE_4, + SECVIO_CAUSE_SOURCE_5 +}; + +/* These are common "recommended" cause definitions for most devices */ +#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0 +#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1 +#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2 +#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4 +#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5 + +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext); +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause); + +/* + * Private data definitions for the secvio "driver" + */ + +struct secvio_int_src { + const u8 *intname; /* Points to a descriptive name for source */ + void *ext; /* Extended data to pass to the handler */ + void (*handler)(struct device *dev, u32 cause, void *ext); +}; + +struct snvs_secvio_drv_private { + struct platform_device *pdev; + spinlock_t svlock ____cacheline_aligned; + struct tasklet_struct irqtask[NR_CPUS]; + struct snvs_full __iomem *svregs; /* both HP and LP domains */ + struct clk *clk; + int irq; + u32 irqcause; /* stashed cause of violation interrupt */ + + /* Registered handlers for each violation */ + struct secvio_int_src intsrc[MAX_SECVIO_SOURCES]; + +}; + +#endif /* SECVIO_H */ diff --git a/drivers/crypto/caam/sm.h b/drivers/crypto/caam/sm.h new file mode 100644 index 00000000000000..65ec9d75ef5647 --- /dev/null +++ b/drivers/crypto/caam/sm.h @@ -0,0 +1,125 @@ + +/* + * CAAM Secure Memory/Keywrap API Definitions + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. + */ + +#ifndef SM_H +#define SM_H + + +/* Storage access permissions */ +#define SM_PERM_READ 0x01 +#define SM_PERM_WRITE 0x02 +#define SM_PERM_BLOB 0x03 + +/* Define treatment of secure memory vs. general memory blobs */ +#define SM_SECMEM 0 +#define SM_GENMEM 1 + +/* Define treatment of red/black keys */ +#define RED_KEY 0 +#define BLACK_KEY 1 + +/* Define key encryption/covering options */ +#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ +#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ + +/* + * Round a key size up to an AES blocksize boundary so to allow for + * padding out to a full block + */ +#define AES_BLOCK_PAD(x) ((x % 16) ? ((x >> 4) + 1) << 4 : x) + +/* Define space required for BKEK + MAC tag storage in any blob */ +#define BLOB_OVERHEAD (32 + 16) + +/* Keystore maintenance functions */ +void sm_init_keystore(struct device *dev); +u32 sm_detect_keystore_units(struct device *dev); +int sm_establish_keystore(struct device *dev, u32 unit); +void sm_release_keystore(struct device *dev, u32 unit); +void caam_sm_shutdown(struct platform_device *pdev); +int caam_sm_example_init(struct platform_device *pdev); + +/* Keystore accessor functions */ +extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, + u32 *slot); +extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot); +extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length); +extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data); +extern int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth); +extern int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *outbuf, + u16 keylen, u8 *keymod); +extern int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *inbuf, + u16 keylen, u8 *keymod); + +/* Prior functions from legacy API, deprecated */ +extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); +extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); + +/* Data structure to hold per-slot information */ +struct keystore_data_slot_info { + u8 allocated; /* Track slot assignments */ + u32 key_length; /* Size of the key */ +}; + +/* Data structure to hold keystore information */ +struct keystore_data { + void *base_address; /* Virtual base of secure memory pages */ + void *phys_address; /* Physical base of secure memory pages */ + u32 slot_count; /* Number of slots in the keystore */ + struct keystore_data_slot_info *slot; /* Per-slot information */ +}; + +/* store the detected attributes of a secure memory page */ +struct sm_page_descriptor { + u16 phys_pagenum; /* may be discontiguous */ + u16 own_part; /* Owning partition */ + void *pg_base; /* Calculated virtual address */ + void *pg_phys; /* Calculated physical address */ + struct keystore_data *ksdata; +}; + +struct caam_drv_private_sm { + struct device *parentdev; /* this ends up as the controller */ + struct device *smringdev; /* ring that owns this instance */ + struct platform_device *sm_pdev; /* Secure Memory platform device */ + spinlock_t kslock ____cacheline_aligned; + + /* SM Register offset from JR base address */ + u32 sm_reg_offset; + + /* Default parameters for geometry */ + u32 max_pages; /* maximum pages this instance can support */ + u32 top_partition; /* highest partition number in this instance */ + u32 top_page; /* highest page number in this instance */ + u32 page_size; /* page size */ + u32 slot_size; /* selected size of each storage block */ + + /* Partition/Page Allocation Map */ + u32 localpages; /* Number of pages we can access */ + struct sm_page_descriptor *pagedesc; /* Allocated per-page */ + + /* Installed handlers for keystore access */ + int (*data_init)(struct device *dev, u32 unit); + void (*data_cleanup)(struct device *dev, u32 unit); + int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot); + int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot); + void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle); + void *(*slot_get_physical)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle); +}; + +#endif /* SM_H */ diff --git a/drivers/crypto/caam/sm_store.c b/drivers/crypto/caam/sm_store.c new file mode 100644 index 00000000000000..8d30e3c93a5a4b --- /dev/null +++ b/drivers/crypto/caam/sm_store.c @@ -0,0 +1,1248 @@ +/* + * CAAM Secure Memory Storage Interface + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. + * + * Loosely based on the SHW Keystore API for SCC/SCC2 + * Experimental implementation and NOT intended for upstream use. Expect + * this interface to be amended significantly in the future once it becomes + * integrated into live applications. + * + * Known issues: + * + * - Executes one instance of an secure memory "driver". This is tied to the + * fact that job rings can't run as standalone instances in the present + * configuration. + * + * - It does not expose a userspace interface. The value of a userspace + * interface for access to secrets is a point for further architectural + * discussion. + * + * - Partition/permission management is not part of this interface. It + * depends on some level of "knowledge" agreed upon between bootloader, + * provisioning applications, and OS-hosted software (which uses this + * driver). + * + * - No means of identifying the location or purpose of secrets managed by + * this interface exists; "slot location" and format of a given secret + * needs to be agreed upon between bootloader, provisioner, and OS-hosted + * application. + */ + +#include "compat.h" +#include "regs.h" +#include "jr.h" +#include "desc.h" +#include "intern.h" +#include "error.h" +#include "sm.h" +#include + +#define SECMEM_KEYMOD_LEN 8 +#define GENMEM_KEYMOD_LEN 16 + +#ifdef SM_DEBUG_CONT +void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + u32 i, *smdata; + + dev_info(dev, "physical page %d content at 0x%08x\n", + pgdesc->phys_pagenum, pgdesc->pg_base); + smdata = pgdesc->pg_base; + for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4) + dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", + (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2], + smdata[i+3]); +} +#endif + +#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ + +static __always_inline int sm_set_cmd_reg(struct caam_drv_private_sm *smpriv, + struct caam_drv_private_jr *jrpriv, + u32 val) +{ + + if (smpriv->sm_reg_offset == SM_V1_OFFSET) { + struct caam_secure_mem_v1 *sm_regs_v1; + sm_regs_v1 = (struct caam_secure_mem_v1 *) + ((void *)jrpriv->rregs + SM_V1_OFFSET); + wr_reg32(&sm_regs_v1->sm_cmd, val); + + } else if (smpriv->sm_reg_offset == SM_V2_OFFSET) { + struct caam_secure_mem_v2 *sm_regs_v2; + sm_regs_v2 = (struct caam_secure_mem_v2 *) + ((void *)jrpriv->rregs + SM_V2_OFFSET); + wr_reg32(&sm_regs_v2->sm_cmd, val); + } else { + return -EINVAL; + } + + return 0; +} + +static __always_inline u32 sm_get_status_reg(struct caam_drv_private_sm *smpriv, + struct caam_drv_private_jr *jrpriv, + u32 *val) +{ + if (smpriv->sm_reg_offset == SM_V1_OFFSET) { + struct caam_secure_mem_v1 *sm_regs_v1; + sm_regs_v1 = (struct caam_secure_mem_v1 *) + ((void *)jrpriv->rregs + SM_V1_OFFSET); + *val = rd_reg32(&sm_regs_v1->sm_status); + } else if (smpriv->sm_reg_offset == SM_V2_OFFSET) { + struct caam_secure_mem_v2 *sm_regs_v2; + sm_regs_v2 = (struct caam_secure_mem_v2 *) + ((void *)jrpriv->rregs + SM_V2_OFFSET); + *val = rd_reg32(&sm_regs_v2->sm_status); + } else { + return -EINVAL; + } + + return 0; +} + +/* + * Construct a black key conversion job descriptor + * + * This function constructs a job descriptor capable of performing + * a key blackening operation on a plaintext secure memory resident object. + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - key physical pointer to the plaintext, which will also hold + * the result. Since encryption occurs in place, caller must + * ensure that the space is large enough to accommodate the + * blackened key + * - keysz size of the plaintext + * - auth if a CCM-covered key is required, use KEY_COVER_CCM, else + * use KEY_COVER_ECB. + * + * KEY to key1 from @key_addr LENGTH 16 BYTES; + * FIFO STORE from key1[ecb] TO @key_addr LENGTH 16 BYTES; + * + * Note that this variant uses the JDKEK only; it does not accommodate the + * trusted key encryption key at this time. + * + */ +static int blacken_key_jobdesc(u32 **desc, void *key, u16 keysz, bool auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key to class 1 key register */ + tmpdesc[idx++] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK); + tmpdesc[idx++] = (u32)key; + + /* ...and write back out via FIFO store*/ + tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | (keysz & KEY_LENGTH_MASK); + + /* plus account for ECB/CCM option in FIFO_STORE */ + if (auth == KEY_COVER_ECB) + tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK; + else + tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK; + + idx++; + tmpdesc[idx++] = (u32)key; + + /* finish off the job header */ + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + /* now allocate execution buffer and coat it with executable */ + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + + return dsize; +} + +/* + * Construct a blob encapsulation job descriptor + * + * This function dynamically constructs a blob encapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - secretbuf Physical pointer to a secret, normally a black or red key, + * possibly residing within an accessible secure memory page, + * of the secret to be encapsulated to an output blob. + * - outbuf Physical pointer to the destination buffer to receive the + * encapsulated output. This buffer will need to be 48 bytes + * larger than the input because of the added encapsulation data. + * The generated descriptor will account for the increase in size, + * but the caller must also account for this increase in the + * buffer allocator. + * - secretsz Size of input secret, in bytes. This is limited to 65536 + * less the size of blob overhead, since the length embeds into + * DECO pointer in/out instructions. + * - keycolor Determines if the source data is covered (black key) or + * plaintext (red key). RED_KEY or BLACK_KEY are defined in + * for this purpose. + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If BLACK_KEY source is covered via AES-CCM, specify + * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job + * descriptor which encapsulates data into an externally-storable blob + * suitable for use across power cycles. + * + * This is an example of a black key encapsulation job into a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note + * the output 48 bytes longer than the input: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08144891 ptr->@0x08144891 + * [03] F800003A seqoutptr: len=58 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000000A seqinptr: len=10 + * [06] 09745090 in_ptr->@0x09745090 + * [07] 870D0004 operation: encap blob reg=memory, black, format=normal + * + * This is an example of a red key encapsulation job for storing a red key + * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction; this accounts for blob permission storage: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 087D0784 ptr->@0x087d0784 + * [03] F8000050 seqoutptr: len=80 + * [04] 09251BB2 out_ptr->@0x09251bb2 + * [05] F0000020 seqinptr: len=32 + * [06] 40000F31 in_ptr->@0x40000f31 + * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod, + void *secretbuf, dma_addr_t outbuf, + u16 secretsz, u8 keycolor, u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* + * Key modifier works differently for secure/general memory blobs + * This accounts for the permission/protection data encapsulated + * within the blob if a secure memory blob is requested + */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* + * Encapsulation output must include space for blob key encryption + * key and MAC tag + */ + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)outbuf; + + /* Input data, should be somewhere in secure memory */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; + tmpdesc[idx++] = (u32)secretbuf; + + /* Set blob encap, then color */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Construct a blob decapsulation job descriptor + * + * This function dynamically constructs a blob decapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - blobbuf Physical pointer (into external memory) of the blob to + * be decapsulated. Blob must reside in a contiguous memory + * segment. + * - outbuf Physical pointer of the decapsulated output, possibly into + * a location within a secure memory page. Must be contiguous. + * - secretsz Size of encapsulated secret in bytes (not the size of the + * input blob). + * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY) + * or left as plaintext (RED_KEY). + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If decapsulation path is specified by BLACK_KEY, then if + * AES-CCM is requested for key covering use KEY_COVER_CCM, else + * use AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job descriptor + * that decapsulates a key blob from external memory into a black (encrypted) + * key or red (plaintext) content. + * + * This is an example of a black key decapsulation job from a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08A63B7F ptr->@0x08a63b7f + * [03] F8000010 seqoutptr: len=16 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000003A seqinptr: len=58 + * [06] 01000010 in_ptr->@0x01000010 + * [07] 860D0004 operation: decap blob reg=memory, black, format=normal + * + * This is an example of a red key decapsulation job for restoring a red key + * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 01000000 ptr->@0x01000000 + * [03] F8000020 seqoutptr: len=32 + * [04] 400000E6 out_ptr->@0x400000e6 + * [05] F0000050 seqinptr: len=80 + * [06] 08F0C0EA in_ptr->@0x08f0c0ea + * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf, + u8 *outbuf, u16 secretsz, u8 keycolor, + u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key modifier */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* Compensate BKEK + MAC tag over size of encapsulated secret */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)blobbuf; + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz; + tmpdesc[idx++] = (u32)outbuf; + + /* Decapsulate from secure memory partition to black blob */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Pseudo-synchronous ring access functions for carrying out key + * encapsulation and decapsulation + */ + +struct sm_key_job_result { + int error; + struct completion completion; +}; + +void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context) +{ + struct sm_key_job_result *res = context; + + res->error = err; /* save off the error for postprocessing */ + complete(&res->completion); /* mark us complete */ +} + +static int sm_key_job(struct device *ksdev, u32 *jobdesc) +{ + struct sm_key_job_result testres; + struct caam_drv_private_sm *kspriv; + int rtn = 0; + + kspriv = dev_get_drvdata(ksdev); + + init_completion(&testres.completion); + + rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done, + &testres); + if (!rtn) { + wait_for_completion_interruptible(&testres.completion); + rtn = testres.error; + } + return rtn; +} + +/* + * Following section establishes the default methods for keystore access + * They are NOT intended for use external to this module + * + * In the present version, these are the only means for the higher-level + * interface to deal with the mechanics of accessing the phyiscal keystore + */ + + +int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u32 i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size); +#endif + + if (size > smpriv->slot_size) + return -EKEYREJECTED; + + for (i = 0; i < ksdata->slot_count; i++) { + if (ksdata->slot[i].allocated == 0) { + ksdata->slot[i].allocated = 1; + (*slot) = i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): new slot %d allocated\n", + *slot); +#endif + return 0; + } + } + + return -ENOSPC; +} +EXPORT_SYMBOL(slot_alloc); + +int slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u8 __iomem *slotdata; + +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot); +#endif + if (slot >= ksdata->slot_count) + return -EINVAL; + slotdata = ksdata->base_address + slot * smpriv->slot_size; + + if (ksdata->slot[slot].allocated == 1) { + /* Forcibly overwrite the data from the keystore */ + memset(ksdata->base_address + slot * smpriv->slot_size, 0, + smpriv->slot_size); + + ksdata->slot[slot].allocated = 0; +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): slot %d released\n", slot); +#endif + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(slot_dealloc); + +void *slot_get_address(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot, + (u32)ksdata->base_address + slot * smpriv->slot_size); +#endif + + return ksdata->base_address + slot * smpriv->slot_size; +} + +void *slot_get_physical(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_physical(): slot %d is 0x%08x\n", slot, + (u32)ksdata->phys_address + slot * smpriv->slot_size); +#endif + + return ksdata->phys_address + slot * smpriv->slot_size; +} + +u32 slot_get_base(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + /* + * There could potentially be more than one secure partition object + * associated with this keystore. For now, there is just one. + */ + + (void)slot; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n", + slot, (u32)ksdata->base_address); +#endif + + return (u32)(ksdata->base_address); +} + +u32 slot_get_offset(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return -EINVAL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot, + slot * smpriv->slot_size); +#endif + + return slot * smpriv->slot_size; +} + +u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot, + smpriv->slot_size); +#endif + /* All slots are the same size in the default implementation */ + return smpriv->slot_size; +} + + + +int kso_init_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + struct keystore_data *keystore_data = NULL; + u32 slot_count; + u32 keystore_data_size; + + /* + * Calculate the required size of the keystore data structure, based + * on the number of keys that can fit in the partition. + */ + slot_count = smpriv->page_size / smpriv->slot_size; +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count); +#endif + + keystore_data_size = sizeof(struct keystore_data) + + slot_count * + sizeof(struct keystore_data_slot_info); + + keystore_data = kzalloc(keystore_data_size, GFP_KERNEL); + + if (keystore_data == NULL) { + retval = -ENOSPC; + goto out; + } + +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: keystore data size = %d\n", + keystore_data_size); +#endif + + /* + * Place the slot information structure directly after the keystore data + * structure. + */ + keystore_data->slot = (struct keystore_data_slot_info *) + (keystore_data + 1); + keystore_data->slot_count = slot_count; + + smpriv->pagedesc[unit].ksdata = keystore_data; + smpriv->pagedesc[unit].ksdata->base_address = + smpriv->pagedesc[unit].pg_base; + smpriv->pagedesc[unit].ksdata->phys_address = + smpriv->pagedesc[unit].pg_phys; + + retval = 0; + +out: + if (retval != 0) + if (keystore_data != NULL) + kfree(keystore_data); + + + return retval; +} + +void kso_cleanup_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *keystore_data = NULL; + + if (smpriv->pagedesc[unit].ksdata != NULL) + keystore_data = smpriv->pagedesc[unit].ksdata; + + /* Release the allocated keystore management data */ + kfree(smpriv->pagedesc[unit].ksdata); + + return; +} + + + +/* + * Keystore management section + */ + +void sm_init_keystore(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + smpriv->data_init = kso_init_data; + smpriv->data_cleanup = kso_cleanup_data; + smpriv->slot_alloc = slot_alloc; + smpriv->slot_dealloc = slot_dealloc; + smpriv->slot_get_address = slot_get_address; + smpriv->slot_get_physical = slot_get_physical; + smpriv->slot_get_base = slot_get_base; + smpriv->slot_get_offset = slot_get_offset; + smpriv->slot_get_slot_size = slot_get_slot_size; +#ifdef SM_DEBUG + dev_info(dev, "sm_init_keystore(): handlers installed\n"); +#endif +} +EXPORT_SYMBOL(sm_init_keystore); + +/* Return available pages/units */ +u32 sm_detect_keystore_units(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + return smpriv->localpages; +} +EXPORT_SYMBOL(sm_detect_keystore_units); + +/* + * Do any keystore specific initializations + */ +int sm_establish_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit); +#endif + + if (smpriv->data_init == NULL) + return -EINVAL; + + /* Call the data_init function for any user setup */ + return smpriv->data_init(dev, unit); +} +EXPORT_SYMBOL(sm_establish_keystore); + +void sm_release_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit); +#endif + if ((smpriv != NULL) && (smpriv->data_cleanup != NULL)) + smpriv->data_cleanup(dev, unit); + + return; +} +EXPORT_SYMBOL(sm_release_keystore); + +/* + * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to + * the keystore + */ +int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_alloc(dev, unit, size, slot); + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_alloc); + +int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_dealloc(dev, unit, slot); +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_dealloc); + +int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u32 slot_size; + u32 i; + u8 __iomem *slot_location; + + spin_lock(&smpriv->kslock); + + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EFBIG; + goto out; + } + + slot_location = smpriv->slot_get_address(dev, unit, slot); + + for (i = 0; i < key_length; i++) + slot_location[i] = key_data[i]; + + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_load); + +int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u8 __iomem *slot_addr; + u32 slot_size; + + spin_lock(&smpriv->kslock); + + slot_addr = smpriv->slot_get_address(dev, unit, slot); + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EKEYREJECTED; + goto out; + } + + memcpy(key_data, slot_addr, key_length); + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_read); + +/* + * Blacken a clear key in a slot. Operates "in place". + * Limited to class 1 keys at the present time + */ +int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr; + void *slotphys; + u32 dsize, jstat; + u32 __iomem *coverdesc = NULL; + + /* Get the address of the object in the slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = (u8 *)smpriv->slot_get_physical(dev, unit, slot); + + dsize = blacken_key_jobdesc(&coverdesc, slotphys, key_length, keyauth); + if (!dsize) + return -ENOMEM; + jstat = sm_key_job(dev, coverdesc); + if (jstat) + retval = -EIO; + + kfree(coverdesc); + return retval; +} +EXPORT_SYMBOL(sm_keystore_cover_key); + +/* Export a black/red key to a blob in external memory */ +int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *outbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, outbuf_dma; + u32 dsize, jstat; + u32 __iomem *encapdesc = NULL; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Build/map/flush the key modifier */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + keymod_dma = dma_map_single(dev, lkeymod, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + dma_sync_single_for_device(dev, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + + outbuf_dma = dma_map_single(dev, outbuf, keylen + BLOB_OVERHEAD, + DMA_FROM_DEVICE); + + /* Build the encapsulation job descriptor */ + dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, slotphys, outbuf_dma, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc an encapsulation descriptor\n"); + retval = -ENOMEM; + goto out; + } + jstat = sm_key_job(dev, encapdesc); + dma_sync_single_for_cpu(dev, outbuf_dma, keylen + BLOB_OVERHEAD, + DMA_FROM_DEVICE); + if (jstat) + retval = -EIO; + +out: + dma_unmap_single(dev, outbuf_dma, keylen + BLOB_OVERHEAD, + DMA_FROM_DEVICE); + dma_unmap_single(dev, keymod_dma, SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + kfree(encapdesc); + + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_export); + +/* Import a black/red key from a blob residing in external memory */ +int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *inbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, inbuf_dma; + u32 dsize, jstat; + u32 __iomem *decapdesc = NULL; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Build/map/flush the key modifier */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + keymod_dma = dma_map_single(dev, lkeymod, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + dma_sync_single_for_device(dev, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + + inbuf_dma = dma_map_single(dev, inbuf, keylen + BLOB_OVERHEAD, + DMA_TO_DEVICE); + dma_sync_single_for_device(dev, inbuf_dma, keylen + BLOB_OVERHEAD, + DMA_TO_DEVICE); + + /* Build the encapsulation job descriptor */ + dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, inbuf_dma, slotphys, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc a decapsulation descriptor\n"); + retval = -ENOMEM; + goto out; + } + + jstat = sm_key_job(dev, decapdesc); + + /* + * May want to expand upon error meanings a bit. Any CAAM status + * is reported as EIO, but we might want to look for something more + * meaningful for something like an ICV error on restore, otherwise + * the caller is left guessing. + */ + if (jstat) + retval = -EIO; + +out: + dma_unmap_single(dev, inbuf_dma, keylen + BLOB_OVERHEAD, + DMA_TO_DEVICE); + dma_unmap_single(dev, keymod_dma, SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + kfree(decapdesc); + + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_import); + +/* + * Initialization/shutdown subsystem + * Assumes statically-invoked startup/shutdown from the controller driver + * for the present time, to be reworked when a device tree becomes + * available. This code will not modularize in present form. + * + * Also, simply uses ring 0 for execution at the present + */ + +int caam_sm_startup(struct platform_device *pdev) +{ + struct device *ctrldev, *smdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *smpriv; + struct caam_drv_private_jr *jrpriv; /* need this for reg page */ + struct platform_device *sm_pdev; + struct sm_page_descriptor *lpagedesc; + u32 page, pgstat, lpagect, detectedpage, smvid; + int i = 0; + struct device_node *np; + ctrldev = &pdev->dev; + ctrlpriv = dev_get_drvdata(ctrldev); + + while (!ctrlpriv) { + if (i >= 1000) { + pr_err("%s: no private data\n", __func__); + return -EINVAL; + } + i++; + msleep(1); + } + + /* + * If ctrlpriv is NULL, it's probably because the caam driver wasn't + * properly initialized (e.g. RNG4 init failed). Thus, bail out here. + */ + if (!ctrlpriv) + return -ENODEV; + + /* + * Set up the private block for secure memory + * Only one instance is possible + */ + smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL); + if (smpriv == NULL) { + dev_err(ctrldev, "can't alloc private mem for secure memory\n"); + return -ENOMEM; + } + smpriv->parentdev = ctrldev; /* copy of parent dev is handy */ + spin_lock_init(&smpriv->kslock); + + /* Create the dev */ +#ifdef CONFIG_OF + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (np) + of_node_clear_flag(np, OF_POPULATED); + sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev); +#else + sm_pdev = platform_device_register_data(ctrldev, "caam_sm", 0, + smpriv, + sizeof(struct caam_drv_private_sm)); +#endif + if (sm_pdev == NULL) { + kfree(smpriv); + return -EINVAL; + } + + /* Save a pointer to the platform device for Secure Memory */ + smpriv->sm_pdev = sm_pdev; + smdev = &sm_pdev->dev; + dev_set_drvdata(smdev, smpriv); + ctrlpriv->smdev = smdev; + + /* Set the Secure Memory Register Map Version */ + smvid = rd_reg32(&ctrlpriv->ctrl->perfmon.smvid); + if (smvid < SMVID_V2) + smpriv->sm_reg_offset = SM_V1_OFFSET; + else + smpriv->sm_reg_offset = SM_V2_OFFSET; + + /* + * Collect configuration limit data for reference + * This batch comes from the partition data/vid registers in perfmon + */ + smpriv->max_pages = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) + & SMPART_MAX_NUMPG_MASK) >> + SMPART_MAX_NUMPG_SHIFT) + 1; + smpriv->top_partition = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) + & SMPART_MAX_PNUM_MASK) >> + SMPART_MAX_PNUM_SHIFT) + 1; + smpriv->top_page = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) + & SMPART_MAX_PG_MASK) >> SMPART_MAX_PG_SHIFT) + 1; + smpriv->page_size = 1024 << ((rd_reg32(&ctrlpriv->ctrl->perfmon.smvid) + & SMVID_PG_SIZE_MASK) >> SMVID_PG_SIZE_SHIFT); + smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE; + +#ifdef SM_DEBUG + dev_info(smdev, "max pages = %d, top partition = %d\n", + smpriv->max_pages, smpriv->top_partition); + dev_info(smdev, "top page = %d, page size = %d (total = %d)\n", + smpriv->top_page, smpriv->page_size, + smpriv->top_page * smpriv->page_size); + dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size); +#endif + + /* + * Now probe for partitions/pages to which we have access. Note that + * these have likely been set up by a bootloader or platform + * provisioning application, so we have to assume that we "inherit" + * a configuration and work within the constraints of what it might be. + * + * Assume use of the zeroth ring in the present iteration (until + * we can divorce the controller and ring drivers, and then assign + * an SM instance to any ring instance). + */ + smpriv->smringdev = &ctrlpriv->jrpdev[0]->dev; + jrpriv = dev_get_drvdata(smpriv->smringdev); + if (!jrpriv) { + kfree(smpriv); + dev_err(smdev, "dev_get_drvdata failed\n"); + return -EINVAL; + } + lpagect = 0; + pgstat = 0; + lpagedesc = kzalloc(sizeof(struct sm_page_descriptor) + * smpriv->max_pages, GFP_KERNEL); + if (lpagedesc == NULL) { + kfree(smpriv); + return -ENOMEM; + } + + for (page = 0; page < smpriv->max_pages; page++) { + if (sm_set_cmd_reg(smpriv, jrpriv, + ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) | + (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK))) + return -EINVAL; + if (sm_get_status_reg(smpriv, jrpriv, &pgstat)) + return -EINVAL; + + if (((pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT) + == SMCS_PGOWN_OWNED) { /* our page? */ + lpagedesc[page].phys_pagenum = + (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT; + lpagedesc[page].own_part = + (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK; + lpagedesc[page].pg_base = ctrlpriv->sm_base + + ((smpriv->page_size * page) / sizeof(u32)); + /* FIXME: get base address from platform property... */ + lpagedesc[page].pg_phys = (u32 *)0x00100000 + + ((smpriv->page_size * page) / sizeof(u32)); + lpagect++; +#ifdef SM_DEBUG + dev_info(smdev, + "physical page %d, owning partition = %d\n", + lpagedesc[page].phys_pagenum, + lpagedesc[page].own_part); +#endif + } + } + + smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect, + GFP_KERNEL); + if (smpriv->pagedesc == NULL) { + kfree(lpagedesc); + kfree(smpriv); + return -ENOMEM; + } + smpriv->localpages = lpagect; + + detectedpage = 0; + for (page = 0; page < smpriv->max_pages; page++) { + if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */ + memcpy(&smpriv->pagedesc[detectedpage], + &lpagedesc[page], + sizeof(struct sm_page_descriptor)); +#ifdef SM_DEBUG_CONT + sm_show_page(smdev, &smpriv->pagedesc[detectedpage]); +#endif + detectedpage++; + } + } + + kfree(lpagedesc); + + sm_init_keystore(smdev); + + return 0; +} + +void caam_sm_shutdown(struct platform_device *pdev) +{ + struct device *ctrldev, *smdev; + struct caam_drv_private *priv; + struct caam_drv_private_sm *smpriv; + + ctrldev = &pdev->dev; + priv = dev_get_drvdata(ctrldev); + smdev = priv->smdev; + + /* Return if resource not initialized by startup */ + if (smdev == NULL) + return; + + smpriv = dev_get_drvdata(smdev); + + /* Remove Secure Memory Platform Device */ + of_device_unregister(smpriv->sm_pdev); + + kfree(smpriv->pagedesc); + kfree(smpriv); +} +EXPORT_SYMBOL(caam_sm_shutdown); +#ifdef CONFIG_OF +static void __exit caam_sm_exit(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return; + + of_node_put(dev_node); + + caam_sm_shutdown(pdev); + + return; +} + +static int __init caam_sm_init(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return -ENODEV; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return -ENODEV; + + of_node_get(dev_node); + + caam_sm_startup(pdev); + + return 0; +} + +module_init(caam_sm_init); +module_exit(caam_sm_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore"); +MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); +#endif diff --git a/drivers/crypto/caam/sm_test.c b/drivers/crypto/caam/sm_test.c new file mode 100644 index 00000000000000..3c5eba4c6fbcb3 --- /dev/null +++ b/drivers/crypto/caam/sm_test.c @@ -0,0 +1,524 @@ +/* + * Secure Memory / Keystore Exemplification Module + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved + * + * This module has been overloaded as an example to show: + * - Secure memory subsystem initialization/shutdown + * - Allocation/deallocation of "slots" in a secure memory page + * - Loading and unloading of key material into slots + * - Covering of secure memory objects into "black keys" (ECB only at present) + * - Verification of key covering (by differentiation only) + * - Exportation of keys into secure memory blobs (with display of result) + * - Importation of keys from secure memory blobs (with display of result) + * - Verification of re-imported keys where possible. + * + * The module does not show the use of key objects as working key register + * source material at this time. + * + * This module can use a substantial amount of refactoring, which may occur + * after the API gets some mileage. Furthermore, expect this module to + * eventually disappear once the API is integrated into "real" software. + */ + +#include "compat.h" +#include "intern.h" +#include "desc.h" +#include "error.h" +#include "jr.h" +#include "sm.h" + +/* Fixed known pattern for a key modifier */ +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* Fixed known pattern for a key */ +static u8 clrkey[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff +}; + +static void key_display(struct device *dev, u8 *label, u16 size, u8 *key) +{ + unsigned i; + + dev_info(dev, label); + for (i = 0; i < size; i += 8) + dev_info(dev, + "[%04d] %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, key[i], key[i + 1], key[i + 2], key[i + 3], + key[i + 4], key[i + 5], key[i + 6], key[i + 7]); +} + +int caam_sm_example_init(struct platform_device *pdev) +{ + struct device *ctrldev, *ksdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *kspriv; + u32 unit, units; + int rtnval = 0; + u8 clrkey8[8], clrkey16[16], clrkey24[24], clrkey32[32]; + u8 blkkey8[AES_BLOCK_PAD(8)], blkkey16[AES_BLOCK_PAD(16)]; + u8 blkkey24[AES_BLOCK_PAD(24)], blkkey32[AES_BLOCK_PAD(32)]; + u8 rstkey8[AES_BLOCK_PAD(8)], rstkey16[AES_BLOCK_PAD(16)]; + u8 rstkey24[AES_BLOCK_PAD(24)], rstkey32[AES_BLOCK_PAD(32)]; + u8 __iomem *blob8, *blob16, *blob24, *blob32; + u32 keyslot8, keyslot16, keyslot24, keyslot32 = 0; + + blob8 = blob16 = blob24 = blob32 = NULL; + + /* + * 3.5.x and later revs for MX6 should be able to ditch this + * and detect via dts property + */ + ctrldev = &pdev->dev; + ctrlpriv = dev_get_drvdata(ctrldev); + + /* + * If ctrlpriv is NULL, it's probably because the caam driver wasn't + * properly initialized (e.g. RNG4 init failed). Thus, bail out here. + */ + if (!ctrlpriv) + return -ENODEV; + + ksdev = ctrlpriv->smdev; + kspriv = dev_get_drvdata(ksdev); + if (kspriv == NULL) + return -ENODEV; + + /* What keystores are available ? */ + units = sm_detect_keystore_units(ksdev); + if (!units) + dev_err(ksdev, "blkkey_ex: no keystore units available\n"); + + /* + * MX6 bootloader stores some stuff in unit 0, so let's + * use 1 or above + */ + if (units < 2) { + dev_err(ksdev, "blkkey_ex: insufficient keystore units\n"); + return -ENODEV; + } + unit = 1; + + dev_info(ksdev, "blkkey_ex: %d keystore units available\n", units); + + /* Initialize/Establish Keystore */ + sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */ + + /* + * Now let's set up buffers for blobs in DMA-able memory. All are + * larger than need to be so that blob size can be seen. + */ + blob8 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob16 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob24 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob32 = kzalloc(128, GFP_KERNEL | GFP_DMA); + + if ((blob8 == NULL) || (blob16 == NULL) || (blob24 == NULL) || + (blob32 == NULL)) { + rtnval = -ENOMEM; + dev_err(ksdev, "blkkey_ex: can't get blob buffers\n"); + goto freemem; + } + + /* Initialize clear keys with a known and recognizable pattern */ + memcpy(clrkey8, clrkey, 8); + memcpy(clrkey16, clrkey, 16); + memcpy(clrkey24, clrkey, 24); + memcpy(clrkey32, clrkey, 32); + + memset(blkkey8, 0, AES_BLOCK_PAD(8)); + memset(blkkey16, 0, AES_BLOCK_PAD(16)); + memset(blkkey24, 0, AES_BLOCK_PAD(24)); + memset(blkkey32, 0, AES_BLOCK_PAD(32)); + + memset(rstkey8, 0, AES_BLOCK_PAD(8)); + memset(rstkey16, 0, AES_BLOCK_PAD(16)); + memset(rstkey24, 0, AES_BLOCK_PAD(24)); + memset(rstkey32, 0, AES_BLOCK_PAD(32)); + + /* + * Allocate keyslots. Since we're going to blacken keys in-place, + * we want slots big enough to pad out to the next larger AES blocksize + * so pad them out. + */ + if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(8), &keyslot8)) + goto dealloc; + + if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(16), &keyslot16)) + goto dealloc; + + if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(24), &keyslot24)) + goto dealloc; + + if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(32), &keyslot32)) + goto dealloc; + + + /* Now load clear key data into the newly allocated slots */ + if (sm_keystore_slot_load(ksdev, unit, keyslot8, clrkey8, 8)) + goto dealloc; + + if (sm_keystore_slot_load(ksdev, unit, keyslot16, clrkey16, 16)) + goto dealloc; + + if (sm_keystore_slot_load(ksdev, unit, keyslot24, clrkey24, 24)) + goto dealloc; + + if (sm_keystore_slot_load(ksdev, unit, keyslot32, clrkey32, 32)) + goto dealloc; + + /* + * All cleartext keys are loaded into slots (in an unprotected + * partition at this time) + * + * Cover keys in-place + */ + if (sm_keystore_cover_key(ksdev, unit, keyslot8, 8, KEY_COVER_ECB)) { + dev_info(ksdev, "blkkey_ex: can't cover 64-bit key\n"); + goto dealloc; + } + + if (sm_keystore_cover_key(ksdev, unit, keyslot16, 16, KEY_COVER_ECB)) { + dev_info(ksdev, "blkkey_ex: can't cover 128-bit key\n"); + goto dealloc; + } + + if (sm_keystore_cover_key(ksdev, unit, keyslot24, 24, KEY_COVER_ECB)) { + dev_info(ksdev, "blkkey_ex: can't cover 192-bit key\n"); + goto dealloc; + } + + if (sm_keystore_cover_key(ksdev, unit, keyslot32, 32, KEY_COVER_ECB)) { + dev_info(ksdev, "blkkey_ex: can't cover 256-bit key\n"); + goto dealloc; + } + + /* + * Keys should be covered and appear sufficiently "random" + * as a result of the covering (blackening) process. Assuming + * non-secure mode, read them back out for examination; they should + * appear as random data, completely differing from the clear + * inputs. So, this will read them back from secure memory and + * compare them. If they match the clear key, then the covering + * operation didn't occur. + */ + + if (sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + blkkey8)) { + dev_info(ksdev, "blkkey_ex: can't read 64-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot16, AES_BLOCK_PAD(16), + blkkey16)) { + dev_info(ksdev, "blkkey_ex: can't read 128-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot24, AES_BLOCK_PAD(24), + blkkey24)) { + dev_info(ksdev, "blkkey_ex: can't read 192-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot32, AES_BLOCK_PAD(32), + blkkey32)) { + dev_info(ksdev, "blkkey_ex: can't read 256-bit black key\n"); + goto dealloc; + } + + + if (!memcmp(blkkey8, clrkey8, 8)) { + dev_info(ksdev, "blkkey_ex: 64-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey16, clrkey16, 16)) { + dev_info(ksdev, "blkkey_ex: 128-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey24, clrkey24, 24)) { + dev_info(ksdev, "blkkey_ex: 192-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey32, clrkey32, 32)) { + dev_info(ksdev, "blkkey_ex: 256-bit key cover failed\n"); + goto dealloc; + } + + + key_display(ksdev, "64-bit clear key:", 8, clrkey8); + key_display(ksdev, "64-bit black key:", AES_BLOCK_PAD(8), blkkey8); + + key_display(ksdev, "128-bit clear key:", 16, clrkey16); + key_display(ksdev, "128-bit black key:", AES_BLOCK_PAD(16), blkkey16); + + key_display(ksdev, "192-bit clear key:", 24, clrkey24); + key_display(ksdev, "192-bit black key:", AES_BLOCK_PAD(24), blkkey24); + + key_display(ksdev, "256-bit clear key:", 32, clrkey32); + key_display(ksdev, "256-bit black key:", AES_BLOCK_PAD(32), blkkey32); + + /* + * Now encapsulate all keys as SM blobs out to external memory + * Blobs will appear as random-looking blocks of data different + * from the original source key, and 48 bytes longer than the + * original key, to account for the extra data encapsulated within. + */ + key_display(ksdev, "64-bit unwritten blob:", 96, blob8); + key_display(ksdev, "128-bit unwritten blob:", 96, blob16); + key_display(ksdev, "196-bit unwritten blob:", 96, blob24); + key_display(ksdev, "256-bit unwritten blob:", 96, blob32); + + if (sm_keystore_slot_export(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't encapsulate 64-bit key\n"); + goto dealloc; + } + + if (sm_keystore_slot_export(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't encapsulate 128-bit key\n"); + goto dealloc; + } + + if (sm_keystore_slot_export(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't encapsulate 192-bit key\n"); + goto dealloc; + } + + if (sm_keystore_slot_export(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't encapsulate 256-bit key\n"); + goto dealloc; + } + + key_display(ksdev, "64-bit black key in blob:", 96, blob8); + key_display(ksdev, "128-bit black key in blob:", 96, blob16); + key_display(ksdev, "192-bit black key in blob:", 96, blob24); + key_display(ksdev, "256-bit black key in blob:", 96, blob32); + + /* + * Now re-import black keys from secure-memory blobs stored + * in general memory from the previous operation. Since we are + * working with black keys, and since power has not cycled, the + * restored black keys should match the original blackened keys + * (this would not be true if the blobs were save in some non-volatile + * store, and power was cycled between the save and restore) + */ + if (sm_keystore_slot_import(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't decapsulate 64-bit blob\n"); + goto dealloc; + } + + if (sm_keystore_slot_import(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't decapsulate 128-bit blob\n"); + goto dealloc; + } + + if (sm_keystore_slot_import(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't decapsulate 196-bit blob\n"); + goto dealloc; + } + + if (sm_keystore_slot_import(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod)) { + dev_info(ksdev, "blkkey_ex: can't decapsulate 256-bit blob\n"); + goto dealloc; + } + + + /* + * Blobs are now restored as black keys. Read those black keys back + * for a comparison with the original black key, they should match + */ + if (sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + rstkey8)) { + dev_info(ksdev, + "blkkey_ex: can't read restored 64-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot16, AES_BLOCK_PAD(16), + rstkey16)) { + dev_info(ksdev, + "blkkey_ex: can't read restored 128-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot24, AES_BLOCK_PAD(24), + rstkey24)) { + dev_info(ksdev, + "blkkey_ex: can't read restored 196-bit black key\n"); + goto dealloc; + } + + if (sm_keystore_slot_read(ksdev, unit, keyslot32, AES_BLOCK_PAD(32), + rstkey32)) { + dev_info(ksdev, + "blkkey_ex: can't read restored 256-bit black key\n"); + goto dealloc; + } + + key_display(ksdev, "restored 64-bit black key:", AES_BLOCK_PAD(8), + rstkey8); + key_display(ksdev, "restored 128-bit black key:", AES_BLOCK_PAD(16), + rstkey16); + key_display(ksdev, "restored 192-bit black key:", AES_BLOCK_PAD(24), + rstkey24); + key_display(ksdev, "restored 256-bit black key:", AES_BLOCK_PAD(32), + rstkey32); + + /* + * Compare the restored black keys with the original blackened keys + * As long as we're operating within the same power cycle, a black key + * restored from a blob should match the original black key IF the + * key happens to be of a size that matches a multiple of the AES + * blocksize. Any key that is padded to fill the block size will not + * match, excepting a key that exceeds a block; only the first full + * blocks will match (assuming ECB). + * + * Therefore, compare the 16 and 32 bit keys, they should match. + * The 24 bit key can only match within the first 16 byte block. + */ + + if (memcmp(rstkey16, blkkey16, AES_BLOCK_PAD(16))) { + dev_info(ksdev, "blkkey_ex: 128-bit restored key mismatch\n"); + rtnval--; + } + + /* Only first AES block will match, remainder subject to padding */ + if (memcmp(rstkey24, blkkey24, 16)) { + dev_info(ksdev, "blkkey_ex: 192-bit restored key mismatch\n"); + rtnval--; + } + + if (memcmp(rstkey32, blkkey32, AES_BLOCK_PAD(32))) { + dev_info(ksdev, "blkkey_ex: 256-bit restored key mismatch\n"); + rtnval--; + } + + + /* Remove keys from keystore */ +dealloc: + sm_keystore_slot_dealloc(ksdev, unit, keyslot8); + sm_keystore_slot_dealloc(ksdev, unit, keyslot16); + sm_keystore_slot_dealloc(ksdev, unit, keyslot24); + sm_keystore_slot_dealloc(ksdev, unit, keyslot32); + + + /* Free resources */ +freemem: + kfree(blob8); + kfree(blob16); + kfree(blob24); + kfree(blob32); + + /* Disconnect from keystore and leave */ + sm_release_keystore(ksdev, unit); + + return rtnval; +} +EXPORT_SYMBOL(caam_sm_example_init); + +void caam_sm_example_shutdown(void) +{ + /* unused in present version */ + struct device_node *dev_node; + struct platform_device *pdev; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return; + + of_node_get(dev_node); + +} + +static int __init caam_sm_test_init(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return -ENODEV; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return -ENODEV; + + of_node_put(dev_node); + + caam_sm_example_init(pdev); + + return 0; +} + + +/* Module-based initialization needs to wait for dev tree */ +#ifdef CONFIG_OF +module_init(caam_sm_test_init); +module_exit(caam_sm_example_shutdown); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL CAAM Black Key Usage Example"); +MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); +#endif diff --git a/drivers/crypto/caam/snvsregs.h b/drivers/crypto/caam/snvsregs.h new file mode 100644 index 00000000000000..eef6b8930db583 --- /dev/null +++ b/drivers/crypto/caam/snvsregs.h @@ -0,0 +1,237 @@ +/* + * SNVS hardware register-level view + * + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved + */ + +#ifndef SNVSREGS_H +#define SNVSREGS_H + +#include +#include + +/* + * SNVS High Power Domain + * Includes security violations, HA counter, RTC, alarm + */ +struct snvs_hp { + u32 lock; /* HPLR - HP Lock */ + u32 cmd; /* HPCOMR - HP Command */ + u32 ctl; /* HPCR - HP Control */ + u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */ + u32 secvio_ctl; /* HPSVCR - Security Violation Control */ + u32 status; /* HPSR - HP Status */ + u32 secvio_status; /* HPSVSR - Security Violation Status */ + u32 ha_counteriv; /* High Assurance Counter IV */ + u32 ha_counter; /* High Assurance Counter */ + u32 rtc_msb; /* Real Time Clock/Counter MSB */ + u32 rtc_lsb; /* Real Time Counter LSB */ + u32 time_alarm_msb; /* Time Alarm MSB */ + u32 time_alarm_lsb; /* Time Alarm LSB */ +}; + +#define HP_LOCK_HAC_LCK 0x00040000 +#define HP_LOCK_HPSICR_LCK 0x00020000 +#define HP_LOCK_HPSVCR_LCK 0x00010000 +#define HP_LOCK_MKEYSEL_LCK 0x00000200 +#define HP_LOCK_TAMPCFG_LCK 0x00000100 +#define HP_LOCK_TAMPFLT_LCK 0x00000080 +#define HP_LOCK_SECVIO_LCK 0x00000040 +#define HP_LOCK_GENP_LCK 0x00000020 +#define HP_LOCK_MONOCTR_LCK 0x00000010 +#define HP_LOCK_CALIB_LCK 0x00000008 +#define HP_LOCK_SRTC_LCK 0x00000004 +#define HP_LOCK_ZMK_RD_LCK 0x00000002 +#define HP_LOCK_ZMK_WT_LCK 0x00000001 + +#define HP_CMD_NONPRIV_AXS 0x80000000 +#define HP_CMD_HAC_STOP 0x00080000 +#define HP_CMD_HAC_CLEAR 0x00040000 +#define HP_CMD_HAC_LOAD 0x00020000 +#define HP_CMD_HAC_CFG_EN 0x00010000 +#define HP_CMD_SNVS_MSTR_KEY 0x00002000 +#define HP_CMD_PROG_ZMK 0x00001000 +#define HP_CMD_SW_LPSV 0x00000400 +#define HP_CMD_SW_FSV 0x00000200 +#define HP_CMD_SW_SV 0x00000100 +#define HP_CMD_LP_SWR_DIS 0x00000020 +#define HP_CMD_LP_SWR 0x00000010 +#define HP_CMD_SSM_SFNS_DIS 0x00000004 +#define HP_CMD_SSM_ST_DIS 0x00000002 +#define HP_CMD_SMM_ST 0x00000001 + +#define HP_CTL_TIME_SYNC 0x00010000 +#define HP_CTL_CAL_VAL_SHIFT 10 +#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT) +#define HP_CTL_CALIB_EN 0x00000100 +#define HP_CTL_PI_FREQ_SHIFT 4 +#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT) +#define HP_CTL_PI_EN 0x00000008 +#define HP_CTL_TIMEALARM_EN 0x00000002 +#define HP_CTL_RTC_EN 0x00000001 + +#define HP_SECVIO_INTEN_EN 0x10000000 +#define HP_SECVIO_INTEN_SRC5 0x00000020 +#define HP_SECVIO_INTEN_SRC4 0x00000010 +#define HP_SECVIO_INTEN_SRC3 0x00000008 +#define HP_SECVIO_INTEN_SRC2 0x00000004 +#define HP_SECVIO_INTEN_SRC1 0x00000002 +#define HP_SECVIO_INTEN_SRC0 0x00000001 +#define HP_SECVIO_INTEN_ALL 0x8000003f + +#define HP_SECVIO_ICTL_CFG_SHIFT 30 +#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT) +#define HP_SECVIO_ICTL_CFG5_SHIFT 5 +#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT) +#define HP_SECVIO_ICTL_CFG_DISABLE 0 +#define HP_SECVIO_ICTL_CFG_NONFATAL 1 +#define HP_SECVIO_ICTL_CFG_FATAL 2 +#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010 +#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008 +#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004 +#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002 +#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001 + +#define HP_STATUS_ZMK_ZERO 0x80000000 +#define HP_STATUS_OTPMK_ZERO 0x08000000 +#define HP_STATUS_OTPMK_SYN_SHIFT 16 +#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT) +#define HP_STATUS_SSM_ST_SHIFT 8 +#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT) +#define HP_STATUS_SSM_ST_INIT 0 +#define HP_STATUS_SSM_ST_HARDFAIL 1 +#define HP_STATUS_SSM_ST_SOFTFAIL 3 +#define HP_STATUS_SSM_ST_INITINT 8 +#define HP_STATUS_SSM_ST_CHECK 9 +#define HP_STATUS_SSM_ST_NONSECURE 11 +#define HP_STATUS_SSM_ST_TRUSTED 13 +#define HP_STATUS_SSM_ST_SECURE 15 + +#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */ +#define HP_SECVIOST_ZMK_SYN_SHIFT 16 +#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT) +#define HP_SECVIOST_SECVIO5 0x00000020 +#define HP_SECVIOST_SECVIO4 0x00000010 +#define HP_SECVIOST_SECVIO3 0x00000008 +#define HP_SECVIOST_SECVIO2 0x00000004 +#define HP_SECVIOST_SECVIO1 0x00000002 +#define HP_SECVIOST_SECVIO0 0x00000001 +#define HP_SECVIOST_SECVIOMASK 0x0000003f + +/* + * SNVS Low Power Domain + * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK + */ +struct snvs_lp { + u32 lock; + u32 ctl; + u32 mstr_key_ctl; /* Master Key Control */ + u32 secvio_ctl; /* Security Violation Control */ + u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */ + u32 tamper_det_cfg; /* Tamper Detectors Configuration */ + u32 status; + u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */ + u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */ + u32 time_alarm; /* Time Alarm */ + u32 smc_msb; /* Secure Monotonic Counter MSB */ + u32 smc_lsb; /* Secure Monotonic Counter LSB */ + u32 pwr_glitch_det; /* Power Glitch Detector */ + u32 gen_purpose; + u32 zmk[8]; /* Zeroizable Master Key */ +}; + +#define LP_LOCK_MKEYSEL_LCK 0x00000200 +#define LP_LOCK_TAMPDET_LCK 0x00000100 +#define LP_LOCK_TAMPFLT_LCK 0x00000080 +#define LP_LOCK_SECVIO_LCK 0x00000040 +#define LP_LOCK_GENP_LCK 0x00000020 +#define LP_LOCK_MONOCTR_LCK 0x00000010 +#define LP_LOCK_CALIB_LCK 0x00000008 +#define LP_LOCK_SRTC_LCK 0x00000004 +#define LP_LOCK_ZMK_RD_LCK 0x00000002 +#define LP_LOCK_ZMK_WT_LCK 0x00000001 + +#define LP_CTL_CAL_VAL_SHIFT 10 +#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT) +#define LP_CTL_CALIB_EN 0x00000100 +#define LP_CTL_SRTC_INVAL_EN 0x00000010 +#define LP_CTL_WAKE_INT_EN 0x00000008 +#define LP_CTL_MONOCTR_EN 0x00000004 +#define LP_CTL_TIMEALARM_EN 0x00000002 +#define LP_CTL_SRTC_EN 0x00000001 + +#define LP_MKEYCTL_ZMKECC_SHIFT 8 +#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT) +#define LP_MKEYCTL_ZMKECC_EN 0x00000010 +#define LP_MKEYCTL_ZMKECC_VAL 0x00000008 +#define LP_MKEYCTL_ZMKECC_PROG 0x00000004 +#define LP_MKEYCTL_MKSEL_SHIFT 0 +#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT) +#define LP_MKEYCTL_MK_OTP 0 +#define LP_MKEYCTL_MK_ZMK 2 +#define LP_MKEYCTL_MK_COMB 3 + +#define LP_SECVIO_CTL_SRC5 0x20 +#define LP_SECVIO_CTL_SRC4 0x10 +#define LP_SECVIO_CTL_SRC3 0x08 +#define LP_SECVIO_CTL_SRC2 0x04 +#define LP_SECVIO_CTL_SRC1 0x02 +#define LP_SECVIO_CTL_SRC0 0x01 + +#define LP_TAMPFILT_EXT2_EN 0x80000000 +#define LP_TAMPFILT_EXT2_SHIFT 24 +#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT) +#define LP_TAMPFILT_EXT1_EN 0x00800000 +#define LP_TAMPFILT_EXT1_SHIFT 16 +#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT) +#define LP_TAMPFILT_WM_EN 0x00000080 +#define LP_TAMPFILT_WM_SHIFT 0 +#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT) + +#define LP_TAMPDET_OSC_BPS 0x10000000 +#define LP_TAMPDET_VRC_SHIFT 24 +#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT) +#define LP_TAMPDET_HTDC_SHIFT 20 +#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT) +#define LP_TAMPDET_LTDC_SHIFT 16 +#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT) +#define LP_TAMPDET_POR_OBS 0x00008000 +#define LP_TAMPDET_PFD_OBS 0x00004000 +#define LP_TAMPDET_ET2_EN 0x00000400 +#define LP_TAMPDET_ET1_EN 0x00000200 +#define LP_TAMPDET_WMT2_EN 0x00000100 +#define LP_TAMPDET_WMT1_EN 0x00000080 +#define LP_TAMPDET_VT_EN 0x00000040 +#define LP_TAMPDET_TT_EN 0x00000020 +#define LP_TAMPDET_CT_EN 0x00000010 +#define LP_TAMPDET_MCR_EN 0x00000004 +#define LP_TAMPDET_SRTCR_EN 0x00000002 + +#define LP_STATUS_SECURE +#define LP_STATUS_NONSECURE +#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */ +#define LP_STATUS_EXT_SECVIO 0x00010000 +#define LP_STATUS_ET2 0x00000400 +#define LP_STATUS_ET1 0x00000200 +#define LP_STATUS_WMT2 0x00000100 +#define LP_STATUS_WMT1 0x00000080 +#define LP_STATUS_VTD 0x00000040 +#define LP_STATUS_TTD 0x00000020 +#define LP_STATUS_CTD 0x00000010 +#define LP_STATUS_PGD 0x00000008 +#define LP_STATUS_MCR 0x00000004 +#define LP_STATUS_SRTCR 0x00000002 +#define LP_STATUS_LPTA 0x00000001 + +/* Full SNVS register page, including version/options */ +struct snvs_full { + struct snvs_hp hp; + struct snvs_lp lp; + u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */ + + /* Version / Revision / Option ID space - end of register page */ + u32 vid; /* 0xbf8 HP Version ID (VID 1) */ + u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */ +}; + +#endif /* SNVSREGS_H */ diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index 625ee50fd78bf4..093a99ce8c64e3 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -28,9 +29,25 @@ #define DCP_MAX_CHANS 4 #define DCP_BUF_SZ PAGE_SIZE +#define DCP_SHA_PAY_SZ 64 #define DCP_ALIGNMENT 64 + +/* + * Null hashes to align with hw behavior on imx6sl and ull + * these are flipped for consistency with hw output + */ +const uint8_t sha1_null_hash[] = + "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf" + "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda"; + +const uint8_t sha256_null_hash[] = + "\x55\xb8\x52\x78\x1b\x99\x95\xa4" + "\x4c\x93\x9b\x64\xe4\x41\xae\x27" + "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a" + "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3"; + /* DCP DMA descriptor. */ struct dcp_dma_desc { uint32_t next_cmd_addr; @@ -48,6 +65,7 @@ struct dcp_coherent_block { uint8_t aes_in_buf[DCP_BUF_SZ]; uint8_t aes_out_buf[DCP_BUF_SZ]; uint8_t sha_in_buf[DCP_BUF_SZ]; + uint8_t sha_out_buf[DCP_SHA_PAY_SZ]; uint8_t aes_key[2 * AES_KEYSIZE_128]; @@ -66,6 +84,10 @@ struct dcp { struct mutex mutex[DCP_MAX_CHANS]; struct task_struct *thread[DCP_MAX_CHANS]; struct crypto_queue queue[DCP_MAX_CHANS]; +#ifdef CONFIG_ARM + struct clk *dcp_clk; +#endif + int enable_sha_workaround; }; enum dcp_chan { @@ -99,6 +121,11 @@ struct dcp_sha_req_ctx { unsigned int fini:1; }; +struct dcp_export_state { + struct dcp_sha_req_ctx req_ctx; + struct dcp_async_ctx async_ctx; +}; + /* * There can even be only one instance of the MXS DCP due to the * design of Linux Crypto API. @@ -209,6 +236,12 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf, DCP_BUF_SZ, DMA_FROM_DEVICE); + if (actx->fill % AES_BLOCK_SIZE) { + dev_err(sdcp->dev, "Invalid block size!\n"); + ret = -EINVAL; + goto aes_done_run; + } + /* Fill in the DMA descriptor. */ desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | MXS_DCP_CONTROL0_INTERRUPT | @@ -238,6 +271,7 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, ret = mxs_dcp_start_dma(actx); +aes_done_run: dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, DMA_TO_DEVICE); dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE); @@ -264,13 +298,15 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) uint8_t *out_tmp, *src_buf, *dst_buf = NULL; uint32_t dst_off = 0; + uint32_t last_out_len = 0; uint8_t *key = sdcp->coh->aes_key; int ret = 0; int split = 0; - unsigned int i, len, clen, rem = 0; + unsigned int i, len, clen, rem = 0, tlen = 0; int init = 0; + bool limit_hit = false; actx->fill = 0; @@ -289,6 +325,11 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) for_each_sg(req->src, src, nents, i) { src_buf = sg_virt(src); len = sg_dma_len(src); + tlen += len; + limit_hit = tlen > req->nbytes; + + if (limit_hit) + len = req->nbytes - (tlen - len); do { if (actx->fill + len > out_off) @@ -305,13 +346,15 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) * If we filled the buffer or this is the last SG, * submit the buffer. */ - if (actx->fill == out_off || sg_is_last(src)) { + if (actx->fill == out_off || sg_is_last(src) || + limit_hit) { ret = mxs_dcp_run_aes(actx, req, init); if (ret) return ret; init = 0; out_tmp = out_buf; + last_out_len = actx->fill; while (dst && actx->fill) { if (!split) { dst_buf = sg_virt(dst); @@ -334,6 +377,13 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) } } } while (len); + + if (limit_hit) + break; + } + if (last_out_len >= AES_BLOCK_SIZE) { + memcpy(req->info, out_buf+(last_out_len-AES_BLOCK_SIZE), + AES_BLOCK_SIZE); } return ret; @@ -509,8 +559,6 @@ static int mxs_dcp_run_sha(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); - struct hash_alg_common *halg = crypto_hash_alg_common(tfm); - struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; dma_addr_t digest_phys = 0; @@ -532,10 +580,24 @@ static int mxs_dcp_run_sha(struct ahash_request *req) desc->payload = 0; desc->status = 0; + /* + * Align driver with hw behavior when generating null hashes + */ + if (rctx->init && rctx->fini && desc->size == 0 && + sdcp->enable_sha_workaround) { + struct hash_alg_common *halg = crypto_hash_alg_common(tfm); + const uint8_t *sha_buf = + (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ? + sha1_null_hash : sha256_null_hash; + memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize); + ret = 0; + goto done_run; + } + /* Set HASH_TERM bit for last transfer block. */ if (rctx->fini) { - digest_phys = dma_map_single(sdcp->dev, req->result, - halg->digestsize, DMA_FROM_DEVICE); + digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf, + DCP_SHA_PAY_SZ, DMA_FROM_DEVICE); desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM; desc->payload = digest_phys; } @@ -543,9 +605,10 @@ static int mxs_dcp_run_sha(struct ahash_request *req) ret = mxs_dcp_start_dma(actx); if (rctx->fini) - dma_unmap_single(sdcp->dev, digest_phys, halg->digestsize, + dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ, DMA_FROM_DEVICE); +done_run: dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE); return ret; @@ -563,6 +626,7 @@ static int dcp_sha_req_to_buf(struct crypto_async_request *arq) const int nents = sg_nents(req->src); uint8_t *in_buf = sdcp->coh->sha_in_buf; + uint8_t *out_buf = sdcp->coh->sha_out_buf; uint8_t *src_buf; @@ -617,11 +681,9 @@ static int dcp_sha_req_to_buf(struct crypto_async_request *arq) actx->fill = 0; - /* For some reason, the result is flipped. */ - for (i = 0; i < halg->digestsize / 2; i++) { - swap(req->result[i], - req->result[halg->digestsize - i - 1]); - } + /* For some reason the result is flipped */ + for (i = 0; i < halg->digestsize; i++) + req->result[i] = out_buf[halg->digestsize - i - 1]; } return 0; @@ -748,6 +810,35 @@ static int dcp_sha_finup(struct ahash_request *req) return dcp_sha_update_fx(req, 1); } +static int dcp_sha_export(struct ahash_request *req, void *out) +{ + struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm); + struct dcp_export_state *export = out; + + memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx)); + memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx)); + + return 0; +} + +static int dcp_sha_import(struct ahash_request *req, const void *in) +{ + struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); + const struct dcp_export_state *export = in; + + memset(rctx, 0, sizeof(struct dcp_sha_req_ctx)); + memset(actx, 0, sizeof(struct dcp_async_ctx)); + + memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx)); + memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx)); + + return 0; +} + static int dcp_sha_digest(struct ahash_request *req) { int ret; @@ -829,8 +920,11 @@ static struct ahash_alg dcp_sha1_alg = { .final = dcp_sha_final, .finup = dcp_sha_finup, .digest = dcp_sha_digest, + .export = dcp_sha_export, + .import = dcp_sha_import, .halg = { .digestsize = SHA1_DIGEST_SIZE, + .statesize = sizeof(struct dcp_export_state), .base = { .cra_name = "sha1", .cra_driver_name = "sha1-dcp", @@ -853,8 +947,11 @@ static struct ahash_alg dcp_sha256_alg = { .final = dcp_sha_final, .finup = dcp_sha_finup, .digest = dcp_sha_digest, + .export = dcp_sha_export, + .import = dcp_sha_import, .halg = { .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct dcp_export_state), .base = { .cra_name = "sha256", .cra_driver_name = "sha256-dcp", @@ -924,6 +1021,26 @@ static int mxs_dcp_probe(struct platform_device *pdev) if (IS_ERR(sdcp->base)) return PTR_ERR(sdcp->base); +#ifdef CONFIG_ARM + sdcp->dcp_clk = devm_clk_get(dev, "dcp"); + + if (IS_ERR(sdcp->dcp_clk)) { + ret = PTR_ERR(sdcp->dcp_clk); + dev_err(dev, "can't identify DCP clk: %d\n", ret); + return -ENODEV; + } + + ret = clk_prepare(sdcp->dcp_clk); + if (ret < 0) { + dev_err(&pdev->dev, "can't prepare DCP clock: %d\n", ret); + return -ENODEV; + } + ret = clk_enable(sdcp->dcp_clk); + if (ret < 0) { + dev_err(&pdev->dev, "can't enable DCP clock: %d\n", ret); + return -ENODEV; + } +#endif ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0, "dcp-vmi-irq", sdcp); @@ -984,6 +1101,11 @@ static int mxs_dcp_probe(struct platform_device *pdev) crypto_init_queue(&sdcp->queue[i], 50); } + /* + * Enable driver alignment with hw behavior for sha generation + */ + sdcp->enable_sha_workaround = 1; + /* Create the SHA and AES handler threads. */ sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha, NULL, "mxs_dcp_chan/sha"); @@ -1065,6 +1187,11 @@ static int mxs_dcp_remove(struct platform_device *pdev) kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); +#ifdef CONFIG_ARM + /* shut clocks off before finalizing shutdown */ + clk_disable(sdcp->dcp_clk); +#endif + platform_set_drvdata(pdev, NULL); global_sdcp = NULL; @@ -1075,6 +1202,7 @@ static int mxs_dcp_remove(struct platform_device *pdev) static const struct of_device_id mxs_dcp_dt_ids[] = { { .compatible = "fsl,imx23-dcp", .data = NULL, }, { .compatible = "fsl,imx28-dcp", .data = NULL, }, + { .compatible = "fsl,imx6sl-dcp", .data = NULL, }, { /* sentinel */ } }; diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 141aefbe37ec93..a7974b2914127b 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -224,6 +224,7 @@ config IMX_SDMA tristate "i.MX SDMA support" depends on ARCH_MXC select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS help Support the i.MX SDMA engine. This engine is integrated into Freescale i.MX25/31/35/51/53/6 chips. @@ -354,7 +355,7 @@ config MV_XOR_V2 config MXS_DMA bool "MXS DMA support" - depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q || SOC_IMX6UL + depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6 select STMP_DEVICE select DMA_ENGINE help @@ -362,6 +363,8 @@ config MXS_DMA and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL/MX6UL chips. +source "drivers/dma/pxp/Kconfig" + config MX3_IPU bool "MX3x Image Processing Unit support" depends on ARCH_MXC diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index e4dc9cac7ee842..0f4da5b7b3be30 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -53,6 +53,8 @@ obj-$(CONFIG_PCH_DMA) += pch_dma.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_PXA_DMA) += pxa_dma.o +obj-$(CONFIG_MXC_PXP_V2) += pxp/ +obj-$(CONFIG_MXC_PXP_V3) += pxp/ obj-$(CONFIG_RENESAS_DMA) += sh/ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 6775f2c74e25b7..1847add29fa277 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -2,6 +2,7 @@ * drivers/dma/fsl-edma.c * * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Driver for the Freescale eDMA engine with flexible channel multiplexing * capability for DMA request sources. The eDMA block can be found on some @@ -111,11 +112,18 @@ #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) #define DMAMUX_NR 2 +#define FSL_EDMA_REG_NUM 3 +#define FSL_DMAMUX_SLOTS 32 +#define FSL_DMAMUX_REG_NUM (DMAMUX_NR * FSL_DMAMUX_SLOTS) #define FSL_EDMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) + +/* Controller will loss power in i.MX7ULP VLLS low power mode */ +#define FSL_EDMA_QUIRK_VLLS_MODE (1 << 0) + enum fsl_edma_pm_state { RUNNING = 0, SUSPENDED, @@ -158,6 +166,8 @@ struct fsl_edma_chan { struct fsl_edma_desc *edesc; struct fsl_edma_slave_config fsc; struct dma_pool *tcd_pool; + char chan_name[16]; + u32 chn_real_count; }; struct fsl_edma_desc { @@ -172,15 +182,79 @@ struct fsl_edma_engine { struct dma_device dma_dev; void __iomem *membase; void __iomem *muxbase[DMAMUX_NR]; + struct clk *dmaclk; struct clk *muxclk[DMAMUX_NR]; struct mutex fsl_edma_mutex; u32 n_chans; int txirq; int errirq; bool big_endian; + u32 dmamux_nr; + u32 version; + void (*mux_configure)(struct fsl_edma_chan *, + void __iomem *muxaddr, u32 off, + u32 slot, bool enable); + u32 edma_regs[FSL_EDMA_REG_NUM]; + u32 dmamux_regs[FSL_DMAMUX_REG_NUM]; + u32 quirks; struct fsl_edma_chan chans[]; }; +static struct platform_device_id fsl_edma_devtype[] = { + { + .name = "vf610-edma", + .driver_data = 0, + }, { + .name = "imx7ulp-edma", + .driver_data = FSL_EDMA_QUIRK_VLLS_MODE, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, fsl_edma_devtype); + +enum fsl_edma_type { + VF610_EDMA, + IMX7ULP_EDMA, +}; + +static const struct of_device_id fsl_edma_dt_ids[] = { + { + .compatible = "fsl,vf610-edma", + .data = &fsl_edma_devtype[VF610_EDMA], + }, { + .compatible = "nxp,imx7ulp-edma", + .data = &fsl_edma_devtype[IMX7ULP_EDMA], + }, { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); + +void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *muxaddr, + u32 off, u32 slot, bool enable) +{ + u8 val8; + + if (enable) + val8 = EDMAMUX_CHCFG_ENBL | slot; + else + val8 = EDMAMUX_CHCFG_DIS; + + iowrite8(val8, muxaddr + off); +} + +void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *muxaddr, + u32 off, u32 slot, bool enable) +{ + u32 val; + + if (enable) + val = EDMAMUX_CHCFG_ENBL << 24 | slot; + else + val = EDMAMUX_CHCFG_DIS; + + iowrite32(val, muxaddr + off * 4); +} + /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. @@ -257,15 +331,12 @@ static void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, void __iomem *muxaddr; unsigned chans_per_mux, ch_off; - chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR; + chans_per_mux = fsl_chan->edma->n_chans / fsl_chan->edma->dmamux_nr; ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; slot = EDMAMUX_CHCFG_SOURCE(slot); - if (enable) - iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off); - else - iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off); + fsl_chan->edma->mux_configure(fsl_chan, muxaddr, ch_off, slot, enable); } static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) @@ -312,7 +383,7 @@ static int fsl_edma_terminate_all(struct dma_chan *chan) return 0; } -static int fsl_edma_pause(struct dma_chan *chan) +static int fsl_edma_device_pause(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); unsigned long flags; @@ -327,7 +398,7 @@ static int fsl_edma_pause(struct dma_chan *chan) return 0; } -static int fsl_edma_resume(struct dma_chan *chan) +static int fsl_edma_device_resume(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); unsigned long flags; @@ -416,8 +487,12 @@ static enum dma_status fsl_edma_tx_status(struct dma_chan *chan, unsigned long flags; status = dma_cookie_status(chan, cookie, txstate); - if (status == DMA_COMPLETE) + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return status; + } if (!txstate) return fsl_chan->status; @@ -426,7 +501,7 @@ static enum dma_status fsl_edma_tx_status(struct dma_chan *chan, vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, true); - else if (vdesc) + else if (fsl_chan->edesc && vdesc) txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, false); else txstate->residue = 0; @@ -661,6 +736,11 @@ static void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) fsl_chan->idle = false; } +static void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true); +} + static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) { struct fsl_edma_engine *fsl_edma = dev_id; @@ -683,6 +763,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) spin_lock(&fsl_chan->vchan.lock); if (!fsl_chan->edesc->iscyclic) { + fsl_edma_get_realcnt(fsl_chan); list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc = NULL; @@ -712,6 +793,7 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) for (ch = 0; ch < fsl_edma->n_chans; ch++) { if (err & (0x1 << ch)) { + dev_err(fsl_edma->dma_dev.dev, "DMA CH%d Err!\n", ch); fsl_edma_disable_request(&fsl_edma->chans[ch]); edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), fsl_edma->membase + EDMA_CERR); @@ -755,7 +837,7 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; struct dma_chan *chan, *_chan; struct fsl_edma_chan *fsl_chan; - unsigned long chans_per_mux = fsl_edma->n_chans / DMAMUX_NR; + unsigned long chans_per_mux = fsl_edma->n_chans / fsl_edma->dmamux_nr; if (dma_spec->args_count != 2) return NULL; @@ -867,8 +949,51 @@ static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma) { int i; - for (i = 0; i < DMAMUX_NR; i++) + for (i = 0; i < fsl_edma->dmamux_nr; i++) clk_disable_unprepare(fsl_edma->muxclk[i]); + + if (fsl_edma->dmaclk) + clk_disable_unprepare(fsl_edma->dmaclk); +} + +static int +fsl_edma2_irq_init(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma) +{ + struct device_node *np = pdev->dev.of_node; + int i, ret, irq; + int count = 0; + + count = of_irq_count(np); + dev_info(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); + if(count < 2){ + dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); + return -EINVAL; + } + + for (i = 0; i < count; i++) { + irq = platform_get_irq(pdev, i); + if (irq < 0) + return -ENXIO; + + sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); + + /* The last IRQ is for eDMA err */ + if (i == count - 1) + ret = devm_request_irq(&pdev->dev, irq, + fsl_edma_err_handler, + 0, "eDMA2-ERR", fsl_edma); + else + + ret = devm_request_irq(&pdev->dev, irq, + fsl_edma_tx_handler, 0, + fsl_edma->chans[i].chan_name, + fsl_edma); + if(ret) + return ret; + } + + return 0; } static int fsl_edma_probe(struct platform_device *pdev) @@ -876,6 +1001,7 @@ static int fsl_edma_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct fsl_edma_engine *fsl_edma; struct fsl_edma_chan *fsl_chan; + const struct of_device_id *of_id; struct resource *res; int len, chans; int ret, i; @@ -891,6 +1017,11 @@ static int fsl_edma_probe(struct platform_device *pdev) if (!fsl_edma) return -ENOMEM; + of_id = of_match_device(fsl_edma_dt_ids, &pdev->dev); + if (of_id) + pdev->id_entry = of_id->data; + fsl_edma->quirks = pdev->id_entry->driver_data; + fsl_edma->n_chans = chans; mutex_init(&fsl_edma->fsl_edma_mutex); @@ -899,7 +1030,29 @@ static int fsl_edma_probe(struct platform_device *pdev) if (IS_ERR(fsl_edma->membase)) return PTR_ERR(fsl_edma->membase); - for (i = 0; i < DMAMUX_NR; i++) { + fsl_edma->dmamux_nr = DMAMUX_NR; + fsl_edma->mux_configure = mux_configure8; + fsl_edma->version = 1; + + if (of_device_is_compatible(np, "nxp,imx7ulp-edma")) { + fsl_edma->dmamux_nr = 1; + fsl_edma->mux_configure = mux_configure32; + fsl_edma->version = 2; + + fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); + if (IS_ERR(fsl_edma->dmaclk)) { + dev_err(&pdev->dev, "Missing DMA block clock.\n"); + return PTR_ERR(fsl_edma->dmaclk); + } + + ret = clk_prepare_enable(fsl_edma->dmaclk); + if (ret) { + dev_err(&pdev->dev, "DMA clk block failed.\n"); + return ret; + } + } + + for (i = 0; i < fsl_edma->dmamux_nr; i++) { char clkname[32]; res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i); @@ -926,6 +1079,14 @@ static int fsl_edma_probe(struct platform_device *pdev) } + edma_writel(fsl_edma, ~0, fsl_edma->membase + EDMA_INTR); + if (fsl_edma->version == 1) + ret = fsl_edma_irq_init(pdev, fsl_edma); + else + ret = fsl_edma2_irq_init(pdev, fsl_edma); + if (ret) + return ret; + fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); @@ -940,14 +1101,11 @@ static int fsl_edma_probe(struct platform_device *pdev) vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i)); + fsl_chan->vchan.chan.chan_id = i; fsl_edma_chan_mux(fsl_chan, 0, false); + fsl_chan->vchan.chan.chan_id = 0; } - edma_writel(fsl_edma, ~0, fsl_edma->membase + EDMA_INTR); - ret = fsl_edma_irq_init(pdev, fsl_edma); - if (ret) - return ret; - dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); @@ -961,8 +1119,8 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; fsl_edma->dma_dev.device_config = fsl_edma_slave_config; - fsl_edma->dma_dev.device_pause = fsl_edma_pause; - fsl_edma->dma_dev.device_resume = fsl_edma_resume; + fsl_edma->dma_dev.device_pause = fsl_edma_device_pause; + fsl_edma->dma_dev.device_resume = fsl_edma_device_resume; fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; @@ -1020,6 +1178,56 @@ static int fsl_edma_remove(struct platform_device *pdev) return 0; } +static int fsl_edma_register_save(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); + int i, j; + + if (!(fsl_edma->quirks & FSL_EDMA_QUIRK_VLLS_MODE)) + return 0; + + /* save regs */ + fsl_edma->edma_regs[0] = + edma_readl(fsl_edma, fsl_edma->membase + EDMA_CR); + fsl_edma->edma_regs[1] = + edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERQ); + fsl_edma->edma_regs[2] = + edma_readl(fsl_edma, fsl_edma->membase + EDMA_EEI); + for (i = 0; i < fsl_edma->dmamux_nr; i++) + for (j = 0; j < fsl_edma->n_chans; j++) + fsl_edma->dmamux_regs[i * fsl_edma->n_chans + j] = + edma_readl(fsl_edma, + fsl_edma->muxbase[i] + j * 4); + + return 0; +} + +static int fsl_edma_register_restore(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); + int i, j; + + if (!(fsl_edma->quirks & FSL_EDMA_QUIRK_VLLS_MODE)) + return 0; + + /* restore the regs */ + for (i = 0; i < fsl_edma->dmamux_nr; i++) + for (j = 0; j < fsl_edma->n_chans; j++) + edma_writel(fsl_edma, + fsl_edma->dmamux_regs[i * fsl_edma->n_chans + j], + fsl_edma->muxbase[i] + j * 4); + edma_writel(fsl_edma, fsl_edma->edma_regs[1], + fsl_edma->membase + EDMA_ERQ); + edma_writel(fsl_edma, fsl_edma->edma_regs[2], + fsl_edma->membase + EDMA_EEI); + edma_writel(fsl_edma, fsl_edma->edma_regs[0], + fsl_edma->membase + EDMA_CR); + + return 0; +} + static int fsl_edma_suspend_late(struct device *dev) { struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); @@ -1041,6 +1249,8 @@ static int fsl_edma_suspend_late(struct device *dev) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); } + fsl_edma_register_save(dev); + return 0; } @@ -1050,6 +1260,8 @@ static int fsl_edma_resume_early(struct device *dev) struct fsl_edma_chan *fsl_chan; int i; + fsl_edma_register_restore(dev); + for (i = 0; i < fsl_edma->n_chans; i++) { fsl_chan = &fsl_edma->chans[i]; fsl_chan->pm_state = RUNNING; @@ -1074,18 +1286,13 @@ static const struct dev_pm_ops fsl_edma_pm_ops = { .resume_early = fsl_edma_resume_early, }; -static const struct of_device_id fsl_edma_dt_ids[] = { - { .compatible = "fsl,vf610-edma", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); - static struct platform_driver fsl_edma_driver = { .driver = { .name = "fsl-edma", .of_match_table = fsl_edma_dt_ids, .pm = &fsl_edma_pm_ops, }, + .id_table = fsl_edma_devtype, .probe = fsl_edma_probe, .remove = fsl_edma_remove, }; diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index d1651a50c3491e..fabdc94f95bb25 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -7,7 +7,7 @@ * * Based on code from Freescale: * - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2016 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -30,7 +30,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -48,6 +50,7 @@ #include #include "dmaengine.h" +#include "virt-dma.h" /* SDMA registers */ #define SDMA_H_C0PTR 0x000 @@ -173,6 +176,8 @@ #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) #define SDMA_WATERMARK_LEVEL_SP BIT(11) #define SDMA_WATERMARK_LEVEL_DP BIT(12) +#define SDMA_WATERMARK_LEVEL_SD BIT(13) +#define SDMA_WATERMARK_LEVEL_DD BIT(14) #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) #define SDMA_WATERMARK_LEVEL_LWE BIT(28) #define SDMA_WATERMARK_LEVEL_HWE BIT(29) @@ -284,9 +289,22 @@ struct sdma_context_data { } __attribute__ ((packed)); #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) +#define SDMA_BD_MAX_CNT 0xfffc /* align with 4 bytes */ struct sdma_engine; +struct sdma_desc { + struct virt_dma_desc vd; + struct list_head node; + unsigned int num_bd; + dma_addr_t bd_phys; + bool bd_iram; + unsigned int buf_tail; + unsigned int buf_ptail; + struct sdma_channel *sdmac; + struct sdma_buffer_descriptor *bd; +}; + /** * struct sdma_channel - housekeeping for a SDMA channel * @@ -300,36 +318,37 @@ struct sdma_engine; * @buf_tail ID of the buffer that was processed * @buf_ptail ID of the previous buffer that was processed * @num_bd max NUM_BD. number of descriptors currently handling + * @bd_iram flag indicating the memory location of buffer descriptor */ struct sdma_channel { + struct virt_dma_chan vc; + struct list_head pending; struct sdma_engine *sdma; + struct sdma_desc *desc; unsigned int channel; enum dma_transfer_direction direction; enum sdma_peripheral_type peripheral_type; unsigned int event_id0; unsigned int event_id1; enum dma_slave_buswidth word_size; - unsigned int buf_tail; - unsigned int buf_ptail; - unsigned int num_bd; unsigned int period_len; - struct sdma_buffer_descriptor *bd; - dma_addr_t bd_phys; unsigned int pc_from_device, pc_to_device; unsigned int device_to_device; + unsigned int pc_to_pc; unsigned long flags; dma_addr_t per_address, per_address2; unsigned long event_mask[2]; unsigned long watermark_level; u32 shp_addr, per_addr; - struct dma_chan chan; - spinlock_t lock; - struct dma_async_tx_descriptor desc; enum dma_status status; + struct imx_dma_data data; unsigned int chn_count; unsigned int chn_real_count; - struct tasklet_struct tasklet; - struct imx_dma_data data; + bool context_loaded; + u32 bd_size_sum; + bool src_dualfifo; + bool dst_dualfifo; + struct dma_pool *bd_pool; }; #define IMX_DMA_SG_LOOP BIT(0) @@ -338,6 +357,14 @@ struct sdma_channel { #define MXC_SDMA_DEFAULT_PRIORITY 1 #define MXC_SDMA_MIN_PRIORITY 1 #define MXC_SDMA_MAX_PRIORITY 7 +/* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and + * can't be accessed. Skip these register touch in suspend/resume. Also below + * two macros are only used on i.mx6sx. + */ +#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4) +#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \ + MXC_SDMA_RESERVED_REG) / 4) #define SDMA_FIRMWARE_MAGIC 0x414d4453 @@ -376,6 +403,8 @@ struct sdma_engine { struct device_dma_parameters dma_parms; struct sdma_channel channel[MAX_DMA_CHANNELS]; struct sdma_channel_control *channel_control; + u32 save_regs[MXC_SDMA_SAVED_REG_NUM]; + const char *fw_name; void __iomem *regs; struct sdma_context_data *context; dma_addr_t context_phys; @@ -389,6 +418,12 @@ struct sdma_engine { u32 spba_start_addr; u32 spba_end_addr; unsigned int irq; + struct gen_pool *iram_pool; + /* channel0 bd */ + dma_addr_t bd0_phys; + bool bd0_iram; + struct sdma_buffer_descriptor *bd0; + bool suspend_off; }; static struct sdma_driver_data sdma_imx31 = { @@ -466,7 +501,6 @@ static struct sdma_script_start_addrs sdma_script_imx6q = { .ap_2_ap_addr = 642, .uart_2_mcu_addr = 817, .mcu_2_app_addr = 747, - .per_2_per_addr = 6331, .uartsh_2_mcu_addr = 1032, .mcu_2_shp_addr = 960, .app_2_mcu_addr = 683, @@ -481,6 +515,30 @@ static struct sdma_driver_data sdma_imx6q = { .script_addrs = &sdma_script_imx6q, }; +static struct sdma_script_start_addrs sdma_script_imx6sx = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1032, + .mcu_2_shp_addr = 960, + .app_2_mcu_addr = 683, + .shp_2_mcu_addr = 891, + .spdif_2_mcu_addr = 1100, + .mcu_2_spdif_addr = 1134, +}; + +static struct sdma_driver_data sdma_imx6sx = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, +}; + +static struct sdma_driver_data sdma_imx6ul = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, +}; + static struct sdma_script_start_addrs sdma_script_imx7d = { .ap_2_ap_addr = 644, .uart_2_mcu_addr = 819, @@ -518,6 +576,9 @@ static const struct platform_device_id sdma_devtypes[] = { }, { .name = "imx6q-sdma", .driver_data = (unsigned long)&sdma_imx6q, + }, { + .name = "imx6sx-sdma", + .driver_data = (unsigned long)&sdma_imx6sx, }, { .name = "imx7d-sdma", .driver_data = (unsigned long)&sdma_imx7d, @@ -528,6 +589,8 @@ static const struct platform_device_id sdma_devtypes[] = { MODULE_DEVICE_TABLE(platform, sdma_devtypes); static const struct of_device_id sdma_dt_ids[] = { + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, + { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, }, { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, @@ -544,6 +607,8 @@ MODULE_DEVICE_TABLE(of, sdma_dt_ids); #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ +static void sdma_start_desc(struct sdma_channel *sdmac); + static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) { u32 chnenbl0 = sdma->drvdata->chnenbl0; @@ -616,23 +681,25 @@ static int sdma_run_channel0(struct sdma_engine *sdma) static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, u32 address) { - struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; void *buf_virt; dma_addr_t buf_phys; int ret; unsigned long flags; + bool use_iram = true; - buf_virt = dma_alloc_coherent(NULL, - size, - &buf_phys, GFP_KERNEL); + buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys); if (!buf_virt) { - return -ENOMEM; + use_iram = false; + buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); + if (!buf_virt) + return -ENOMEM; } spin_lock_irqsave(&sdma->channel_0_lock, flags); bd0->mode.command = C0_SETPM; - bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; bd0->mode.count = size / 2; bd0->buffer_addr = buf_phys; bd0->ext_buffer_addr = address; @@ -643,7 +710,10 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - dma_free_coherent(NULL, size, buf_virt, buf_phys); + if (use_iram) + gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size); + else + dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); return ret; } @@ -675,6 +745,7 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) static void sdma_update_channel_loop(struct sdma_channel *sdmac) { struct sdma_buffer_descriptor *bd; + struct sdma_desc *desc = sdmac->desc; int error = 0; enum dma_status old_status = sdmac->status; @@ -682,8 +753,8 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac) * loop mode. Iterate over descriptors, re-setup them and * call callback function. */ - while (1) { - bd = &sdmac->bd[sdmac->buf_tail]; + while (desc) { + bd = &desc->bd[desc->buf_tail]; if (bd->mode.status & BD_DONE) break; @@ -702,36 +773,35 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac) sdmac->chn_real_count = bd->mode.count; bd->mode.status |= BD_DONE; bd->mode.count = sdmac->period_len; - sdmac->buf_ptail = sdmac->buf_tail; - sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd; - - /* - * The callback is called from the interrupt context in order - * to reduce latency and to avoid the risk of altering the - * SDMA transaction status by the time the client tasklet is - * executed. - */ - - dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); + desc->buf_ptail = desc->buf_tail; + desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; if (error) sdmac->status = old_status; + /* + * The callback is called from the interrupt context in order + * to reduce latency and to avoid the risk of altering the + * SDMA transaction status by the time the client tasklet is + * executed. + */ + spin_unlock(&sdmac->vc.lock); + dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); + spin_lock(&sdmac->vc.lock); } } -static void mxc_sdma_handle_channel_normal(unsigned long data) +static void mxc_sdma_handle_channel_normal(struct sdma_channel *data) { struct sdma_channel *sdmac = (struct sdma_channel *) data; struct sdma_buffer_descriptor *bd; int i, error = 0; - sdmac->chn_real_count = 0; /* * non loop mode. Iterate over all descriptors, collect * errors and call callback function */ - for (i = 0; i < sdmac->num_bd; i++) { - bd = &sdmac->bd[i]; + for (i = 0; i < sdmac->desc->num_bd; i++) { + bd = &sdmac->desc->bd[i]; if (bd->mode.status & (BD_DONE | BD_RROR)) error = -EIO; @@ -742,10 +812,6 @@ static void mxc_sdma_handle_channel_normal(unsigned long data) sdmac->status = DMA_ERROR; else sdmac->status = DMA_COMPLETE; - - dma_cookie_complete(&sdmac->desc); - - dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); } static irqreturn_t sdma_int_handler(int irq, void *dev_id) @@ -761,13 +827,26 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) while (stat) { int channel = fls(stat) - 1; struct sdma_channel *sdmac = &sdma->channel[channel]; - - if (sdmac->flags & IMX_DMA_SG_LOOP) - sdma_update_channel_loop(sdmac); - else - tasklet_schedule(&sdmac->tasklet); - + struct sdma_desc *desc; + + spin_lock(&sdmac->vc.lock); + desc = sdmac->desc; + if (desc) { + if (sdmac->flags & IMX_DMA_SG_LOOP) { + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + sdma_update_channel_loop(sdmac); + else + vchan_cyclic_callback(&desc->vd); + } else { + mxc_sdma_handle_channel_normal(sdmac); + vchan_cookie_complete(&desc->vd); + if (!list_empty(&sdmac->pending)) + list_del(&desc->node); + sdma_start_desc(sdmac); + } + } __clear_bit(channel, &stat); + spin_unlock(&sdmac->vc.lock); } return IRQ_HANDLED; @@ -785,14 +864,16 @@ static void sdma_get_pc(struct sdma_channel *sdmac, * These are needed once we start to support transfers between * two peripherals or memory-to-memory transfers */ - int per_2_per = 0; + int per_2_per = 0, emi_2_emi = 0; sdmac->pc_from_device = 0; sdmac->pc_to_device = 0; sdmac->device_to_device = 0; + sdmac->pc_to_pc = 0; switch (peripheral_type) { case IMX_DMATYPE_MEMORY: + emi_2_emi = sdma->script_addrs->ap_2_ap_addr; break; case IMX_DMATYPE_DSP: emi_2_per = sdma->script_addrs->bp_2_ap_addr; @@ -815,6 +896,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac, emi_2_per = sdma->script_addrs->mcu_2_ata_addr; break; case IMX_DMATYPE_CSPI: + per_2_emi = sdma->script_addrs->app_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; + break; case IMX_DMATYPE_EXT: case IMX_DMATYPE_SSI: case IMX_DMATYPE_SAI: @@ -858,6 +942,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac, case IMX_DMATYPE_IPU_MEMORY: emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; break; + case IMX_DMATYPE_HDMI: + emi_2_per = sdma->script_addrs->hdmi_dma_addr; + break; default: break; } @@ -865,6 +952,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac, sdmac->pc_from_device = per_2_emi; sdmac->pc_to_device = emi_2_per; sdmac->device_to_device = per_2_per; + sdmac->pc_to_pc = emi_2_emi; } static int sdma_load_context(struct sdma_channel *sdmac) @@ -873,14 +961,19 @@ static int sdma_load_context(struct sdma_channel *sdmac) int channel = sdmac->channel; int load_address; struct sdma_context_data *context = sdma->context; - struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; int ret; unsigned long flags; + if (sdmac->context_loaded) + return 0; + if (sdmac->direction == DMA_DEV_TO_MEM) load_address = sdmac->pc_from_device; else if (sdmac->direction == DMA_DEV_TO_DEV) load_address = sdmac->device_to_device; + else if (sdmac->direction == DMA_MEM_TO_MEM) + load_address = sdmac->pc_to_pc; else load_address = sdmac->pc_to_device; @@ -902,14 +995,19 @@ static int sdma_load_context(struct sdma_channel *sdmac) /* Send by context the event mask,base address for peripheral * and watermark level */ - context->gReg[0] = sdmac->event_mask[1]; - context->gReg[1] = sdmac->event_mask[0]; - context->gReg[2] = sdmac->per_addr; - context->gReg[6] = sdmac->shp_addr; - context->gReg[7] = sdmac->watermark_level; + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + context->gReg[4] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + } else { + context->gReg[0] = sdmac->event_mask[1]; + context->gReg[1] = sdmac->event_mask[0]; + context->gReg[2] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + context->gReg[7] = sdmac->watermark_level; + } bd0->mode.command = C0_SETDM; - bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; bd0->mode.count = sizeof(*context) / 4; bd0->buffer_addr = sdma->context_phys; bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; @@ -917,12 +1015,39 @@ static int sdma_load_context(struct sdma_channel *sdmac) spin_unlock_irqrestore(&sdma->channel_0_lock, flags); + sdmac->context_loaded = true; + + return ret; +} + +static int sdma_save_restore_context(struct sdma_engine *sdma, bool save) +{ + struct sdma_context_data *context = sdma->context; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; + unsigned long flags; + int ret; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); + + if (save) + bd0->mode.command = C0_GETDM; + else + bd0->mode.command = C0_SETDM; + + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = MAX_DMA_CHANNELS * sizeof(*context) / 4; + bd0->buffer_addr = sdma->context_phys; + bd0->ext_buffer_addr = 2048; + ret = sdma_run_channel0(sdma); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); + return ret; } static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) { - return container_of(chan, struct sdma_channel, chan); + return container_of(chan, struct sdma_channel, vc.chan); } static int sdma_disable_channel(struct dma_chan *chan) @@ -975,6 +1100,11 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; + + if (sdmac->src_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; + if (sdmac->dst_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; } static int sdma_config_channel(struct dma_chan *chan) @@ -989,11 +1119,9 @@ static int sdma_config_channel(struct dma_chan *chan) sdmac->shp_addr = 0; sdmac->per_addr = 0; - if (sdmac->event_id0) { - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id0); - } + if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) + return -EINVAL; + sdma_event_enable(sdmac, sdmac->event_id0); if (sdmac->event_id1) { if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) @@ -1022,8 +1150,15 @@ static int sdma_config_channel(struct dma_chan *chan) if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || sdmac->peripheral_type == IMX_DMATYPE_ASRC) sdma_set_watermarklevel_for_p2p(sdmac); - } else + } else { + /* ERR008517 fixed on i.mx6ul, no workaround needed */ + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI && + sdmac->direction == DMA_MEM_TO_DEV && + sdmac->sdma->drvdata == &sdma_imx6ul) + __set_bit(31, &sdmac->watermark_level); + __set_bit(sdmac->event_id0, sdmac->event_mask); + } /* Address */ sdmac->shp_addr = sdmac->per_address; @@ -1053,52 +1188,191 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac, return 0; } -static int sdma_request_channel(struct sdma_channel *sdmac) +static int sdma_alloc_bd(struct sdma_desc *desc) { - struct sdma_engine *sdma = sdmac->sdma; - int channel = sdmac->channel; - int ret = -EBUSY; + u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + int ret = -ENOMEM; + unsigned long flags; - sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, - GFP_KERNEL); - if (!sdmac->bd) { - ret = -ENOMEM; - goto out; + desc->bd_iram = true; + desc->bd = gen_pool_dma_alloc(desc->sdmac->sdma->iram_pool, bd_size, + &desc->bd_phys); + if (!desc->bd) { + desc->bd_iram = false; + desc->bd = dma_pool_alloc(desc->sdmac->bd_pool, GFP_ATOMIC, + &desc->bd_phys); + if (!desc->bd) + return ret; + } + spin_lock_irqsave(&desc->sdmac->vc.lock, flags); + desc->sdmac->bd_size_sum += bd_size; + spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags); + + memset(desc->bd, 0, bd_size); + + return 0; +} + +static void sdma_free_bd(struct sdma_desc *desc) +{ + u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + unsigned long flags; + + if (desc->bd) { + if (desc->bd_iram) + gen_pool_free(desc->sdmac->sdma->iram_pool, + (unsigned long)desc->bd, bd_size); + else + dma_pool_free(desc->sdmac->bd_pool, desc->bd, + desc->bd_phys); + spin_lock_irqsave(&desc->sdmac->vc.lock, flags); + desc->sdmac->bd_size_sum -= bd_size; + spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags); } +} + +static int sdma_request_channel0(struct sdma_engine *sdma) +{ + int ret = 0; + + sdma->bd0_iram = true; + sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, &sdma->bd0_phys); + if (!sdma->bd0) { + sdma->bd0_iram = false; + sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, + &sdma->bd0_phys, GFP_KERNEL); + if (!sdma->bd0) { + ret = -ENOMEM; + goto out; + } + } + + memset(sdma->bd0, 0, PAGE_SIZE); - sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; + sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; + sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; - sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); return 0; out: return ret; } -static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) +static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct sdma_desc, vd.tx); +} + +static void sdma_desc_free(struct virt_dma_desc *vd) { + struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd); + if (desc) { + sdma_free_bd(desc); + kfree(desc); + } +} + +static int sdma_channel_pause(struct dma_chan *chan) +{ + struct sdma_channel *sdmac = to_sdma_chan(chan); unsigned long flags; - struct sdma_channel *sdmac = to_sdma_chan(tx->chan); - dma_cookie_t cookie; - spin_lock_irqsave(&sdmac->lock, flags); + if (!(sdmac->flags & IMX_DMA_SG_LOOP)) + return -EINVAL; - cookie = dma_cookie_assign(tx); + sdma_disable_channel(chan); + spin_lock_irqsave(&sdmac->vc.lock, flags); + sdmac->status = DMA_PAUSED; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); - spin_unlock_irqrestore(&sdmac->lock, flags); + return 0; +} - return cookie; +static int sdma_channel_resume(struct dma_chan *chan) +{ + struct sdma_channel *sdmac = to_sdma_chan(chan); + struct sdma_engine *sdma = sdmac->sdma; + unsigned long flags; + + if (!(sdmac->flags & IMX_DMA_SG_LOOP)) + return -EINVAL; + + /* + * restore back context since context may loss if mega/fast OFF + */ + if (sdma->suspend_off) { + if (sdma_load_context(sdmac)) { + dev_err(sdmac->sdma->dev, "context load failed.\n"); + return -EINVAL; + } + } + + sdma_enable_channel(sdmac->sdma, sdmac->channel); + spin_lock_irqsave(&sdmac->vc.lock, flags); + sdmac->status = DMA_IN_PROGRESS; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); + + return 0; +} + +static int sdma_terminate_all(struct dma_chan *chan) +{ + struct sdma_channel *sdmac = to_sdma_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&sdmac->vc.lock, flags); + vchan_get_all_descriptors(&sdmac->vc, &head); + while (!list_empty(&sdmac->pending)) { + struct sdma_desc *desc = list_first_entry(&sdmac->pending, + struct sdma_desc, node); + + list_del(&desc->node); + spin_unlock_irqrestore(&sdmac->vc.lock, flags); + sdmac->vc.desc_free(&desc->vd); + spin_lock_irqsave(&sdmac->vc.lock, flags); + } + if (sdmac->desc) + sdmac->desc = NULL; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); + vchan_dma_desc_free_list(&sdmac->vc, &head); + sdma_disable_channel(chan); + sdmac->context_loaded = false; + + return 0; } static int sdma_alloc_chan_resources(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); struct imx_dma_data *data = chan->private; + struct imx_dma_data default_data; int prio, ret; - if (!data) - return -EINVAL; + ret = clk_enable(sdmac->sdma->clk_ipg); + if (ret) + return ret; + ret = clk_enable(sdmac->sdma->clk_ahb); + if (ret) + goto disable_clk_ipg; + + /* + * dmatest(memcpy) will never call slave_config before prep, so we need + * do some job in slave_config in this case. + */ + if (!data) { + sdmac->word_size = sdmac->sdma->dma_device.copy_align; + default_data.priority = 2; + default_data.peripheral_type = IMX_DMATYPE_MEMORY; + default_data.dma_request = 0; + default_data.dma_request2 = 0; + data = &default_data; + + sdma_config_ownership(sdmac, false, true, false); + sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); + sdma_load_context(sdmac); + } switch (data->priority) { case DMA_PRIO_HIGH: @@ -1116,26 +1390,18 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan) sdmac->peripheral_type = data->peripheral_type; sdmac->event_id0 = data->dma_request; sdmac->event_id1 = data->dma_request2; - - ret = clk_enable(sdmac->sdma->clk_ipg); - if (ret) - return ret; - ret = clk_enable(sdmac->sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; - - ret = sdma_request_channel(sdmac); - if (ret) - goto disable_clk_ahb; + sdmac->src_dualfifo = data->src_dualfifo; + sdmac->dst_dualfifo = data->dst_dualfifo; ret = sdma_set_channel_priority(sdmac, prio); if (ret) goto disable_clk_ahb; - dma_async_tx_descriptor_init(&sdmac->desc, chan); - sdmac->desc.tx_submit = sdma_tx_submit; - /* txd.flags will be overwritten in prep funcs */ - sdmac->desc.flags = DMA_CTRL_ACK; + sdmac->bd_size_sum = 0; + + sdmac->bd_pool = dma_pool_create("bd_pool", chan->device->dev, + sizeof(struct sdma_buffer_descriptor), + 32, 0); return 0; @@ -1151,10 +1417,9 @@ static void sdma_free_chan_resources(struct dma_chan *chan) struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - sdma_disable_channel(chan); + sdma_terminate_all(chan); - if (sdmac->event_id0) - sdma_event_disable(sdmac, sdmac->event_id0); + sdma_event_disable(sdmac, sdmac->event_id0); if (sdmac->event_id1) sdma_event_disable(sdmac, sdmac->event_id1); @@ -1163,115 +1428,242 @@ static void sdma_free_chan_resources(struct dma_chan *chan) sdma_set_channel_priority(sdmac, 0); - dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); - clk_disable(sdma->clk_ipg); clk_disable(sdma->clk_ahb); + + dma_pool_destroy(sdmac->bd_pool); + sdmac->bd_pool = NULL; } -static struct dma_async_tx_descriptor *sdma_prep_slave_sg( - struct dma_chan *chan, struct scatterlist *sgl, - unsigned int sg_len, enum dma_transfer_direction direction, - unsigned long flags, void *context) +static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, + enum dma_transfer_direction direction, u32 bds) +{ + struct sdma_desc *desc; + /* Now allocate and setup the descriptor. */ + desc = kzalloc((sizeof(*desc)), GFP_ATOMIC); + if (!desc) + goto err_out; + + sdmac->status = DMA_IN_PROGRESS; + sdmac->direction = direction; + sdmac->flags = 0; + sdmac->chn_count = 0; + sdmac->chn_real_count = 0; + + desc->sdmac = sdmac; + desc->num_bd = bds; + INIT_LIST_HEAD(&desc->node); + + if (sdma_alloc_bd(desc)) + goto err_desc_out; + + if (sdma_load_context(sdmac)) + goto err_desc_out; + + return desc; + +err_desc_out: + kfree(desc); +err_out: + return NULL; +} + +static int check_bd_buswidth(struct sdma_buffer_descriptor *bd, + struct sdma_channel *sdmac, int count, + dma_addr_t dma_dst, dma_addr_t dma_src) +{ + int ret = 0; + + switch (sdmac->word_size) { + case DMA_SLAVE_BUSWIDTH_4_BYTES: + bd->mode.command = 0; + if ((count | dma_dst | dma_src) & 3) + ret = -EINVAL; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + bd->mode.command = 2; + if ((count | dma_dst | dma_src) & 1) + ret = -EINVAL; + break; + case DMA_SLAVE_BUSWIDTH_1_BYTE: + bd->mode.command = 1; + break; + default: + return -EINVAL; + } + + return ret; +} + +static struct dma_async_tx_descriptor *sdma_prep_memcpy( + struct dma_chan *chan, dma_addr_t dma_dst, + dma_addr_t dma_src, size_t len, unsigned long flags) { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int ret, i, count; int channel = sdmac->channel; - struct scatterlist *sg; + size_t count; + int i = 0, param; + struct sdma_buffer_descriptor *bd; + struct sdma_desc *desc; - if (sdmac->status == DMA_IN_PROGRESS) + if (!chan || !len) return NULL; - sdmac->status = DMA_IN_PROGRESS; - sdmac->flags = 0; + dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", + &dma_src, &dma_dst, len, channel); - sdmac->buf_tail = 0; - sdmac->buf_ptail = 0; - sdmac->chn_real_count = 0; + desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, len / SDMA_BD_MAX_CNT + 1); + if (!desc) + goto err_out; - dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", - sg_len, channel); + do { + count = min_t(size_t, len, SDMA_BD_MAX_CNT); + bd = &desc->bd[i]; + bd->buffer_addr = dma_src; + bd->ext_buffer_addr = dma_dst; + bd->mode.count = count; + sdmac->chn_count += count; - sdmac->direction = direction; - ret = sdma_load_context(sdmac); - if (ret) - goto err_out; + if (check_bd_buswidth(bd, sdmac, count, dma_dst, dma_src)) + goto err_bd_out; - if (sg_len > NUM_BD) { - dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", - channel, sg_len, NUM_BD); - ret = -EINVAL; + dma_src += count; + dma_dst += count; + len -= count; + i++; + + param = BD_DONE | BD_EXTD | BD_CONT; + /* last bd */ + if (!len) { + param |= BD_INTR; + param |= BD_LAST; + param &= ~BD_CONT; + } + + dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%u %s%s\n", + i, count, bd->buffer_addr, + param & BD_WRAP ? "wrap" : "", + param & BD_INTR ? " intr" : ""); + + bd->mode.status = param; + } while (len); + + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); +err_bd_out: + sdma_free_bd(desc); + kfree(desc); +err_out: + return NULL; +} + +/* + * Please ensure dst_nents no smaller than src_nents , also every sg_len of + * dst_sg node no smaller than src_sg. To simply things, please use the same + * size of dst_sg as src_sg. + */ +static struct dma_async_tx_descriptor *sdma_prep_sg( + struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + enum dma_transfer_direction direction, unsigned long flags) +{ + struct sdma_channel *sdmac = to_sdma_chan(chan); + struct sdma_engine *sdma = sdmac->sdma; + int ret, i, count; + int channel = sdmac->channel; + struct scatterlist *sg_src = src_sg, *sg_dst = dst_sg; + struct sdma_desc *desc; + + if (!chan) + return NULL; + + dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", + src_nents, channel); + + desc = sdma_transfer_init(sdmac, direction, src_nents); + if (!desc) goto err_out; - } - sdmac->chn_count = 0; - for_each_sg(sgl, sg, sg_len, i) { - struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; + for_each_sg(src_sg, sg_src, src_nents, i) { + struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; - bd->buffer_addr = sg->dma_address; + bd->buffer_addr = sg_src->dma_address; + + if (direction == DMA_MEM_TO_MEM) { + BUG_ON(!sg_dst); + bd->ext_buffer_addr = sg_dst->dma_address; + } - count = sg_dma_len(sg); + count = sg_dma_len(sg_src); - if (count > 0xffff) { + if (count > SDMA_BD_MAX_CNT) { dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", - channel, count, 0xffff); + channel, count, SDMA_BD_MAX_CNT); ret = -EINVAL; - goto err_out; + goto err_bd_out; } bd->mode.count = count; sdmac->chn_count += count; - if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { - ret = -EINVAL; - goto err_out; - } - - switch (sdmac->word_size) { - case DMA_SLAVE_BUSWIDTH_4_BYTES: - bd->mode.command = 0; - if (count & 3 || sg->dma_address & 3) - return NULL; - break; - case DMA_SLAVE_BUSWIDTH_2_BYTES: - bd->mode.command = 2; - if (count & 1 || sg->dma_address & 1) - return NULL; - break; - case DMA_SLAVE_BUSWIDTH_1_BYTE: - bd->mode.command = 1; - break; - default: - return NULL; - } + if (direction == DMA_MEM_TO_MEM) + ret = check_bd_buswidth(bd, sdmac, count, + sg_dst->dma_address, + sg_src->dma_address); + else + ret = check_bd_buswidth(bd, sdmac, count, 0, + sg_src->dma_address); + if (ret) + goto err_bd_out; param = BD_DONE | BD_EXTD | BD_CONT; - if (i + 1 == sg_len) { + if (i + 1 == src_nents) { param |= BD_INTR; param |= BD_LAST; param &= ~BD_CONT; } - dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", - i, count, (u64)sg->dma_address, + dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%pad %s%s\n", + i, count, &sg_src->dma_address, param & BD_WRAP ? "wrap" : "", param & BD_INTR ? " intr" : ""); bd->mode.status = param; + if (direction == DMA_MEM_TO_MEM) + sg_dst = sg_next(sg_dst); } - sdmac->num_bd = sg_len; - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - return &sdmac->desc; +err_bd_out: + sdma_free_bd(desc); + kfree(desc); err_out: - sdmac->status = DMA_ERROR; + dev_dbg(sdma->dev, "Can't get desc.\n"); return NULL; } +static struct dma_async_tx_descriptor *sdma_prep_memcpy_sg( + struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags) +{ + return sdma_prep_sg(chan, dst_sg, dst_nents, src_sg, src_nents, + DMA_MEM_TO_MEM, flags); +} + +static struct dma_async_tx_descriptor *sdma_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + return sdma_prep_sg(chan, NULL, 0, sgl, sg_len, direction, flags); +} + static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, @@ -1279,42 +1671,42 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int num_periods = buf_len / period_len; int channel = sdmac->channel; - int ret, i = 0, buf = 0; + int i = 0, buf = 0; + int num_periods = 0; + struct sdma_desc *desc; dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); - if (sdmac->status == DMA_IN_PROGRESS) - return NULL; - - sdmac->status = DMA_IN_PROGRESS; + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + num_periods = buf_len / period_len; + /* Now allocate and setup the descriptor. */ + desc = sdma_transfer_init(sdmac, direction, num_periods); + if (!desc) + goto err_out; - sdmac->buf_tail = 0; - sdmac->buf_ptail = 0; - sdmac->chn_real_count = 0; sdmac->period_len = period_len; - sdmac->flags |= IMX_DMA_SG_LOOP; - sdmac->direction = direction; - ret = sdma_load_context(sdmac); - if (ret) - goto err_out; - if (num_periods > NUM_BD) { - dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", - channel, num_periods, NUM_BD); - goto err_out; - } + /* for hdmi-audio without BDs */ + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - if (period_len > 0xffff) { - dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", - channel, period_len, 0xffff); - goto err_out; + desc->buf_tail = 0; + desc->buf_ptail = 0; + sdmac->chn_real_count = 0; + + if (period_len > SDMA_BD_MAX_CNT) { + dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", + channel, period_len, SDMA_BD_MAX_CNT); + goto err_bd_out; } + if (sdmac->peripheral_type == IMX_DMATYPE_UART) + sdmac->chn_count = period_len; + while (buf < buf_len) { - struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; + struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; bd->buffer_addr = dma_addr; @@ -1322,7 +1714,7 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( bd->mode.count = period_len; if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) - goto err_out; + goto err_bd_out; if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) bd->mode.command = 0; else @@ -1332,8 +1724,8 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( if (i + 1 == num_periods) param |= BD_WRAP; - dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", - i, period_len, (u64)dma_addr, + dev_dbg(sdma->dev, "entry %d: count: %d dma: %pad %s%s\n", + i, period_len, &dma_addr, param & BD_WRAP ? "wrap" : "", param & BD_INTR ? " intr" : ""); @@ -1344,13 +1736,12 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( i++; } + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - sdmac->num_bd = num_periods; - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; - - return &sdmac->desc; +err_bd_out: + sdma_free_bd(desc); + kfree(desc); err_out: - sdmac->status = DMA_ERROR; return NULL; } @@ -1372,6 +1763,12 @@ static int sdma_config(struct dma_chan *chan, sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & SDMA_WATERMARK_LEVEL_HWML; sdmac->word_size = dmaengine_cfg->dst_addr_width; + } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + sdmac->per_address = dmaengine_cfg->dst_addr; + sdmac->per_address2 = dmaengine_cfg->src_addr; + sdmac->watermark_level = 0; + } else if (dmaengine_cfg->direction == DMA_MEM_TO_MEM) { + sdmac->word_size = dmaengine_cfg->dst_addr_width; } else { sdmac->per_address = dmaengine_cfg->dst_addr; sdmac->watermark_level = dmaengine_cfg->dst_maxburst * @@ -1382,32 +1779,92 @@ static int sdma_config(struct dma_chan *chan, return sdma_config_channel(chan); } +static void sdma_wait_tasklet(struct dma_chan *chan) +{ + struct sdma_channel *sdmac = to_sdma_chan(chan); + + tasklet_kill(&sdmac->vc.task); +} + static enum dma_status sdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct sdma_channel *sdmac = to_sdma_chan(chan); u32 residue; + struct virt_dma_desc *vd; + struct sdma_desc *desc; + enum dma_status ret; + unsigned long flags; - if (sdmac->flags & IMX_DMA_SG_LOOP) - residue = (sdmac->num_bd - sdmac->buf_ptail) * - sdmac->period_len - sdmac->chn_real_count; - else + ret = dma_cookie_status(chan, cookie, txstate); + if (!txstate) { + return ret; + } else if (ret == DMA_COMPLETE) { + spin_lock_irqsave(&sdmac->vc.lock, flags); + txstate->residue = sdmac->chn_count - sdmac->chn_real_count; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); + return ret; + } + + spin_lock_irqsave(&sdmac->vc.lock, flags); + vd = vchan_find_desc(&sdmac->vc, cookie); + desc = to_sdma_desc(&vd->tx); + if (vd) { + if ((sdmac->flags & IMX_DMA_SG_LOOP)) { + if (sdmac->peripheral_type != IMX_DMATYPE_UART) + residue = (desc->num_bd - desc->buf_ptail) * + sdmac->period_len - sdmac->chn_real_count; + else + residue = sdmac->chn_count - sdmac->chn_real_count; + } else + residue = sdmac->chn_count; + } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) residue = sdmac->chn_count - sdmac->chn_real_count; + else + residue = 0; - dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, - residue); + txstate->residue = residue; + ret = sdmac->status; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); - return sdmac->status; + return ret; +} + +static void sdma_start_desc(struct sdma_channel *sdmac) +{ + struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); + struct sdma_desc *desc; + struct sdma_engine *sdma = sdmac->sdma; + int channel = sdmac->channel; + + if (!vd) { + sdmac->desc = NULL; + return; + } + sdmac->desc = desc = to_sdma_desc(&vd->tx); + /* + * Do not delete the node in desc_issued list in cyclic mode, otherwise + * the desc alloced will never be freed in vchan_dma_desc_free_list + */ + if (!(sdmac->flags & IMX_DMA_SG_LOOP)) { + list_add_tail(&sdmac->desc->node, &sdmac->pending); + list_del(&vd->node); + } + sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; + sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; + sdma_enable_channel(sdma, sdmac->channel); } static void sdma_issue_pending(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); - struct sdma_engine *sdma = sdmac->sdma; + unsigned long flags; - if (sdmac->status == DMA_IN_PROGRESS) - sdma_enable_channel(sdma, sdmac->channel); + spin_lock_irqsave(&sdmac->vc.lock, flags); + if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) + sdma_start_desc(sdmac); + spin_unlock_irqrestore(&sdmac->vc.lock, flags); } #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 @@ -1573,7 +2030,7 @@ static int sdma_get_firmware(struct sdma_engine *sdma, static int sdma_init(struct sdma_engine *sdma) { - int i, ret; + int i, ret, ccbsize; dma_addr_t ccb_phys; ret = clk_enable(sdma->clk_ipg); @@ -1586,14 +2043,17 @@ static int sdma_init(struct sdma_engine *sdma) /* Be sure SDMA has not started yet */ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); - sdma->channel_control = dma_alloc_coherent(NULL, - MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + - sizeof(struct sdma_context_data), - &ccb_phys, GFP_KERNEL); + ccbsize = MAX_DMA_CHANNELS * (sizeof(struct sdma_channel_control) + + sizeof(struct sdma_context_data)); + sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys); if (!sdma->channel_control) { - ret = -ENOMEM; - goto err_dma_alloc; + sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, + &ccb_phys, GFP_KERNEL); + if (!sdma->channel_control) { + ret = -ENOMEM; + goto err_dma_alloc; + } } sdma->context = (void *)sdma->channel_control + @@ -1613,7 +2073,7 @@ static int sdma_init(struct sdma_engine *sdma) for (i = 0; i < MAX_DMA_CHANNELS; i++) writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); - ret = sdma_request_channel(&sdma->channel[0]); + ret = sdma_request_channel0(sdma); if (ret) goto err_dma_alloc; @@ -1668,17 +2128,11 @@ static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, if (dma_spec->args_count != 3) return NULL; + memset(&data, 0, sizeof(data)); + data.dma_request = dma_spec->args[0]; data.peripheral_type = dma_spec->args[1]; data.priority = dma_spec->args[2]; - /* - * init dma_request2 to zero, which is not used by the dts. - * For P2P, dma_request2 is init from dma_request_channel(), - * chan->private will point to the imx_dma_data, and in - * device_alloc_chan_resources(), imx_dma_data.dma_request2 will - * be set to sdmac->event_id1. - */ - data.dma_request2 = 0; return dma_request_channel(mask, sdma_filter_fn, &data); } @@ -1761,6 +2215,7 @@ static int sdma_probe(struct platform_device *pdev) dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); + dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); INIT_LIST_HEAD(&sdma->dma_device.channels); /* Initialize channel parameters */ @@ -1768,24 +2223,26 @@ static int sdma_probe(struct platform_device *pdev) struct sdma_channel *sdmac = &sdma->channel[i]; sdmac->sdma = sdma; - spin_lock_init(&sdmac->lock); - - sdmac->chan.device = &sdma->dma_device; - dma_cookie_init(&sdmac->chan); + sdmac->context_loaded = false; sdmac->channel = i; + sdmac->status = DMA_IN_PROGRESS; + sdmac->vc.desc_free = sdma_desc_free; + INIT_LIST_HEAD(&sdmac->pending); - tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal, - (unsigned long) sdmac); /* * Add the channel to the DMAC list. Do not add channel 0 though * because we need it internally in the SDMA driver. This also means * that channel 0 in dmaengine counting matches sdma channel 1. */ if (i) - list_add_tail(&sdmac->chan.device_node, - &sdma->dma_device.channels); + vchan_init(&sdmac->vc, &sdma->dma_device); } + if (np) + sdma->iram_pool = of_gen_pool_get(np, "iram", 0); + if (!sdma->iram_pool) + dev_warn(&pdev->dev, "no iram assigned, using external mem\n"); + ret = sdma_init(sdma); if (ret) goto err_init; @@ -1819,23 +2276,30 @@ static int sdma_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); } } + sdma->fw_name = fw_name; sdma->dma_device.dev = &pdev->dev; sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; sdma->dma_device.device_tx_status = sdma_tx_status; + sdma->dma_device.device_synchronize = sdma_wait_tasklet; sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; sdma->dma_device.device_config = sdma_config; - sdma->dma_device.device_terminate_all = sdma_disable_channel; + sdma->dma_device.device_terminate_all = sdma_terminate_all; + sdma->dma_device.device_pause = sdma_channel_pause; + sdma->dma_device.device_resume = sdma_channel_resume; sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; + sdma->dma_device.device_prep_dma_sg = sdma_prep_memcpy_sg; sdma->dma_device.device_issue_pending = sdma_issue_pending; sdma->dma_device.dev->dma_parms = &sdma->dma_parms; - dma_set_max_seg_size(sdma->dma_device.dev, 65535); + sdma->dma_device.copy_align = 2; + dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); platform_set_drvdata(pdev, sdma); @@ -1882,17 +2346,122 @@ static int sdma_remove(struct platform_device *pdev) for (i = 0; i < MAX_DMA_CHANNELS; i++) { struct sdma_channel *sdmac = &sdma->channel[i]; - tasklet_kill(&sdmac->tasklet); + tasklet_kill(&sdmac->vc.task); + sdma_free_chan_resources(&sdmac->vc.chan); } platform_set_drvdata(pdev, NULL); return 0; } +#ifdef CONFIG_PM_SLEEP +static int sdma_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret = 0; + + sdma->suspend_off = false; + + /* Do nothing if not i.MX6SX or i.MX7D*/ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul) + return 0; + + clk_enable(sdma->clk_ipg); + clk_enable(sdma->clk_ahb); + + ret = sdma_save_restore_context(sdma, true); + if (ret) { + dev_err(sdma->dev, "save context error!\n"); + return ret; + } + /* save regs */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + sdma->save_regs[i] = readl_relaxed(sdma->regs + + MXC_SDMA_RESERVED_REG + + 4 * i); + else + sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i); + } + + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + + return 0; +} + +static int sdma_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret; + + /* Do nothing if not i.MX6SX or i.MX7D*/ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul) + return 0; + + clk_enable(sdma->clk_ipg); + clk_enable(sdma->clk_ahb); + /* Do nothing if mega/fast mix not turned off */ + if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) { + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + return 0; + } + + sdma->suspend_off = true; + + /* restore regs and load firmware */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + writel_relaxed(sdma->save_regs[i], sdma->regs + + MXC_SDMA_RESERVED_REG + 4 * i); + else + writel_relaxed(sdma->save_regs[i] , sdma->regs + 4 * i); + } + + /* prepare priority for channel0 to start */ + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); + + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) { + dev_warn(&pdev->dev, "failed to get firware\n"); + return ret; + } + + ret = sdma_save_restore_context(sdma, false); + if (ret) { + dev_err(sdma->dev, "restore context error!\n"); + return ret; + } + + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + + return 0; +} +#endif + +static const struct dev_pm_ops sdma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume) +}; + static struct platform_driver sdma_driver = { .driver = { .name = "imx-sdma", .of_match_table = sdma_dt_ids, + .pm = &sdma_pm_ops, }, .id_table = sdma_devtypes, .remove = sdma_remove, diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index e217268c7098cc..0e90c17a4fdd24 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. * * Refer to drivers/dma/imx-sdma.c * @@ -28,7 +28,6 @@ #include #include #include - #include #include "dmaengine.h" @@ -135,6 +134,7 @@ enum mxs_dma_devtype { enum mxs_dma_id { IMX23_DMA, IMX28_DMA, + IMX7D_DMA, }; struct mxs_dma_engine { @@ -142,6 +142,7 @@ struct mxs_dma_engine { enum mxs_dma_devtype type; void __iomem *base; struct clk *clk; + struct clk *clk_io; struct dma_device dma_device; struct device_dma_parameters dma_parms; struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; @@ -167,6 +168,9 @@ static struct mxs_dma_type mxs_dma_types[] = { }, { .id = IMX28_DMA, .type = MXS_DMA_APBX, + }, { + .id = IMX7D_DMA, + .type = MXS_DMA_APBH, } }; @@ -183,6 +187,9 @@ static const struct platform_device_id mxs_dma_ids[] = { }, { .name = "imx28-dma-apbx", .driver_data = (kernel_ulong_t) &mxs_dma_types[3], + }, { + .name = "imx7d-dma-apbh", + .driver_data = (kernel_ulong_t) &mxs_dma_types[4], }, { /* end of list */ } @@ -193,6 +200,7 @@ static const struct of_device_id mxs_dma_dt_ids[] = { { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, + { .compatible = "fsl,imx7d-dma-apbh", .data = &mxs_dma_ids[4], }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); @@ -437,6 +445,12 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) if (ret) goto err_clk; + if (mxs_dma->dev_id == IMX7D_DMA) { + ret = clk_prepare_enable(mxs_dma->clk_io); + if (ret) + goto err_clk_unprepare; + } + mxs_dma_reset_chan(chan); dma_async_tx_descriptor_init(&mxs_chan->desc, chan); @@ -447,6 +461,8 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) return 0; +err_clk_unprepare: + clk_disable_unprepare(mxs_dma->clk); err_clk: free_irq(mxs_chan->chan_irq, mxs_dma); err_irq: @@ -468,6 +484,9 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan) dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, mxs_chan->ccw, mxs_chan->ccw_phys); + if (mxs_dma->dev_id == IMX7D_DMA) + clk_disable_unprepare(mxs_dma->clk_io); + clk_disable_unprepare(mxs_dma->clk); } @@ -690,7 +709,7 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, return mxs_chan->status; } -static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) +static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) { int ret; @@ -698,9 +717,15 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) if (ret) return ret; + if (mxs_dma->dev_id == IMX7D_DMA) { + ret = clk_prepare_enable(mxs_dma->clk_io); + if (ret) + goto err_clk_bch; + } + ret = stmp_reset_block(mxs_dma->base); if (ret) - goto err_out; + goto err_clk_io; /* enable apbh burst */ if (dma_is_apbh(mxs_dma)) { @@ -714,7 +739,10 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); -err_out: +err_clk_io: + if (mxs_dma->dev_id == IMX7D_DMA) + clk_disable_unprepare(mxs_dma->clk_io); +err_clk_bch: clk_disable_unprepare(mxs_dma->clk); return ret; } @@ -800,9 +828,19 @@ static int __init mxs_dma_probe(struct platform_device *pdev) if (IS_ERR(mxs_dma->base)) return PTR_ERR(mxs_dma->base); - mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(mxs_dma->clk)) - return PTR_ERR(mxs_dma->clk); + if (mxs_dma->dev_id == IMX7D_DMA) { + mxs_dma->clk = devm_clk_get(&pdev->dev, "dma_apbh_bch"); + if (IS_ERR(mxs_dma->clk)) + return PTR_ERR(mxs_dma->clk); + mxs_dma->clk_io = devm_clk_get(&pdev->dev, "dma_apbh_io"); + if (IS_ERR(mxs_dma->clk_io)) + return PTR_ERR(mxs_dma->clk_io); + + } else { + mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(mxs_dma->clk)) + return PTR_ERR(mxs_dma->clk); + } dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); @@ -832,6 +870,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev) mxs_dma->pdev = pdev; mxs_dma->dma_device.dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, mxs_dma); /* mxs_dma gets 65535 bytes maximum sg size */ mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; @@ -869,9 +908,34 @@ static int __init mxs_dma_probe(struct platform_device *pdev) return 0; } +static int mxs_dma_pm_suspend(struct device *dev) +{ + /* + * We do not save any registers here, since the gpmi will release its + * DMA channel. + */ + return 0; +} + +static int mxs_dma_pm_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = mxs_dma_init(mxs_dma); + if (ret) + return ret; + return 0; +} + +static const struct dev_pm_ops mxs_dma_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume) +}; + static struct platform_driver mxs_dma_driver = { .driver = { .name = "mxs-dma", + .pm = &mxs_dma_pm_ops, .of_match_table = mxs_dma_dt_ids, }, .id_table = mxs_dma_ids, diff --git a/drivers/dma/pxp/Kconfig b/drivers/dma/pxp/Kconfig new file mode 100644 index 00000000000000..5a280a88703ddd --- /dev/null +++ b/drivers/dma/pxp/Kconfig @@ -0,0 +1,21 @@ +config MXC_PXP_V2 + bool "MXC PxP V2 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite. + If unsure, select N. + +config MXC_PXP_V3 + bool "MXC PxP V3 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP V3(Pixel Pipeline) on i.MX7D. The PxP V3 supports + more functions than PxP V2, dithering, reagl/-D and etc. + If unsure, select N. + +config MXC_PXP_CLIENT_DEVICE + bool "MXC PxP Client Device" + default y + depends on MXC_PXP_V2 || MXC_PXP_V3 diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile new file mode 100644 index 00000000000000..42e4ace02fbda0 --- /dev/null +++ b/drivers/dma/pxp/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o +obj-$(CONFIG_MXC_PXP_V3) += pxp_dma_v3.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c new file mode 100644 index 00000000000000..1643fd22e88ee0 --- /dev/null +++ b/drivers/dma/pxp/pxp_device.c @@ -0,0 +1,878 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BUFFER_HASH_ORDER 4 + +static struct pxp_buffer_hash bufhash; +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; + +static int pxp_ht_create(struct pxp_buffer_hash *hash, int order) +{ + unsigned long i; + unsigned long table_size; + + table_size = 1U << order; + + hash->order = order; + hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL); + + if (!hash->hash_table) { + pr_err("%s: Out of memory for hash table\n", __func__); + return -ENOMEM; + } + + for (i = 0; i < table_size; i++) + INIT_HLIST_HEAD(&hash->hash_table[i]); + + return 0; +} + +static int pxp_ht_insert_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *new) +{ + unsigned long hashkey; + struct hlist_head *h_list; + + hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order); + h_list = &hash->hash_table[hashkey]; + + spin_lock(&hash->hash_lock); + hlist_add_head_rcu(&new->item, h_list); + spin_unlock(&hash->hash_lock); + + return 0; +} + +static int pxp_ht_remove_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *obj) +{ + spin_lock(&hash->hash_lock); + hlist_del_init_rcu(&obj->item); + spin_unlock(&hash->hash_lock); + return 0; +} + +static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash, + unsigned long key) +{ + struct pxp_buf_obj *entry; + struct hlist_head *h_list; + unsigned long hashkey; + + hashkey = hash_long(key, hash->order); + h_list = &hash->hash_table[hashkey]; + + hlist_for_each_entry_rcu(entry, h_list, item) { + if (entry->offset >> PAGE_SHIFT == key) + return &entry->item; + } + + return NULL; +} + +static void pxp_ht_destroy(struct pxp_buffer_hash *hash) +{ + kfree(hash->hash_table); + hash->hash_table = NULL; +} + +static int pxp_buffer_handle_create(struct pxp_file *file_priv, + struct pxp_buf_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->buffer_lock); + + ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->buffer_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_buf_obj * +pxp_buffer_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return NULL; + } + + spin_unlock(&file_priv->buffer_lock); + + return obj; +} + +static int pxp_buffer_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return -EINVAL; + } + + idr_remove(&file_priv->buffer_idr, handle); + spin_unlock(&file_priv->buffer_lock); + + return 0; +} + +static int pxp_channel_handle_create(struct pxp_file *file_priv, + struct pxp_chan_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->channel_lock); + + ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->channel_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_chan_obj * +pxp_channel_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return NULL; + } + + spin_unlock(&file_priv->channel_lock); + + return obj; +} + +static int pxp_channel_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return -EINVAL; + } + + idr_remove(&file_priv->channel_idr, handle); + spin_unlock(&file_priv->channel_lock); + + return 0; +} + +static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj) +{ + obj->virtual = dma_alloc_coherent(NULL, PAGE_ALIGN(obj->size), + (dma_addr_t *) (&obj->offset), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset); + + if (obj->virtual == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_buf_obj *obj) +{ + if (obj->virtual != NULL) { + dma_free_coherent(0, PAGE_ALIGN(obj->size), + obj->virtual, (dma_addr_t)obj->offset); + } +} + +static int +pxp_buffer_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_buf_obj *obj = ptr; + int ret; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret < 0) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + return 0; +} + +static int +pxp_channel_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_chan_obj *obj = ptr; + int chan_id; + + chan_id = obj->chan->chan_id; + wait_event(irq_info[chan_id].waitq, + atomic_read(&irq_info[chan_id].irq_pending) == 0); + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + return 0; +} + +static void pxp_free_buffers(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->buffer_idr, + &pxp_buffer_object_free, file_priv); + idr_destroy(&file_priv->buffer_idr); +} + +static void pxp_free_channels(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->channel_idr, + &pxp_channel_object_free, file_priv); + idr_destroy(&file_priv->channel_idr); +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + atomic_dec(&irq_info[chan_id].irq_pending); + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg) +{ + struct scatterlist *sg; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf; + dma_cookie_t cookie; + int handle, chan_id; + struct dma_chan *chan; + struct pxp_chan_obj *obj; + int i = 0, j = 0, k = 0, m = 0, length, ret, sg_len; + + pxp_conf = kzalloc(sizeof(*pxp_conf), GFP_KERNEL); + if (!pxp_conf) + return -ENOMEM; + + ret = copy_from_user(pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) { + kfree(pxp_conf); + return -EFAULT; + } + + handle = pxp_conf->handle; + obj = pxp_channel_object_lookup(priv, handle); + if (!obj) { + kfree(pxp_conf); + return -EINVAL; + } + chan = obj->chan; + chan_id = chan->chan_id; + + sg_len = pxp_conf->ol_param[0].pixel_fmt ? 3 : 2; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) + sg_len += 4; + + sg = kmalloc(sizeof(*sg) * sg_len, GFP_KERNEL); + if (!sg) { + kfree(pxp_conf); + return -ENOMEM; + } + + sg_init_table(sg, sg_len); + + txd = chan->device->device_prep_slave_sg(chan, + sg, sg_len, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT, + NULL); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf->proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 2) { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) && (j < 4)) { + for (j = 0; j < 4; j++) { + if (j == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH0; + } else if (j == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH1; + } else if (j == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE0; + } else if (j == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) && (m < 4)) { + for (m = 0; m < 4; m++) { + if (m == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH0; + } else if (m == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH1; + } else if (m == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE0; + } else if (m == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) && (k < 4)) { + for (k = 0; k < 4; k++) { + if (k == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH0; + } else if (k == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH1; + } else if (k == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE0; + } else if (k == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE1; + } + + desc = desc->next; + } + + i += 4; + } + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + atomic_inc(&irq_info[chan_id].irq_pending); + + kfree(pxp_conf); + kfree(sg); + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + filp->private_data = priv; + priv->filp = filp; + + idr_init(&priv->buffer_idr); + spin_lock_init(&priv->buffer_lock); + + idr_init(&priv->channel_idr); + spin_lock_init(&priv->channel_lock); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv = filp->private_data; + + if (priv) { + pxp_free_channels(priv); + pxp_free_buffers(priv); + kfree(priv); + filp->private_data = NULL; + } + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + int request_size; + struct hlist_node *node; + struct pxp_buf_obj *obj; + + request_size = vma->vm_end - vma->vm_start; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + node = pxp_ht_find_key(&bufhash, vma->vm_pgoff); + if (!node) + return -EINVAL; + + obj = list_entry(node, struct pxp_buf_obj, item); + if (obj->offset + (obj->size >> PAGE_SHIFT) < + (vma->vm_pgoff + vma_pages(vma))) + return -ENOMEM; + + switch (obj->mem_type) { + case MEMORY_TYPE_UNCACHED: + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + break; + case MEMORY_TYPE_WC: + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + break; + case MEMORY_TYPE_CACHED: + break; + default: + pr_err("%s: invalid memory type!\n", __func__); + return -EINVAL; + } + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static bool chan_filter(struct dma_chan *chan, void *arg) +{ + if (imx_dma_is_pxp(chan)) + return true; + else + return false; +} + +static long pxp_device_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct pxp_file *file_priv = filp->private_data; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + int ret; + struct dma_chan *chan = NULL; + dma_cap_mask_t mask; + struct pxp_chan_obj *obj = NULL; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + + chan = dma_request_channel(mask, chan_filter, NULL); + if (!chan) { + pr_err("Unsccessfully received channel!\n"); + return -EBUSY; + } + + pr_debug("Successfully received channel." + "chan_id %d\n", chan->chan_id); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) { + dma_release_channel(chan); + return -ENOMEM; + } + obj->chan = chan; + + ret = pxp_channel_handle_create(file_priv, obj, + &obj->handle); + if (ret) { + dma_release_channel(chan); + kfree(obj); + return ret; + } + + init_waitqueue_head(&(irq_info[chan->chan_id].waitq)); + if (put_user(obj->handle, (u32 __user *) arg)) { + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(chan); + kfree(obj); + return -EFAULT; + } + + break; + } + case PXP_IOC_PUT_CHAN: + { + int handle; + struct pxp_chan_obj *obj; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + pr_debug("%d release handle %d\n", __LINE__, handle); + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + int ret; + + ret = pxp_ioc_config_chan(file_priv, arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + int handle; + struct pxp_chan_obj *obj = NULL; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + dma_async_issue_pending(obj->chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct pxp_mem_desc buffer; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&buffer, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + buffer.size); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + obj->size = buffer.size; + obj->mem_type = buffer.mtype; + + ret = pxp_alloc_dma_buffer(obj); + if (ret == -1) { + printk(KERN_ERR + "Physical memory allocation error!\n"); + kfree(obj); + return ret; + } + + ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle); + if (ret) { + pxp_free_dma_buffer(obj); + kfree(obj); + return ret; + } + buffer.handle = obj->handle; + buffer.phys_addr = obj->offset; + + ret = copy_to_user((void __user *)arg, &buffer, + sizeof(struct pxp_mem_desc)); + if (ret) { + pxp_buffer_handle_delete(file_priv, buffer.handle); + pxp_free_dma_buffer(obj); + kfree(obj); + return -EFAULT; + } + + pxp_ht_insert_item(&bufhash, obj); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct pxp_mem_desc pxp_mem; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle); + if (!obj) + return -EINVAL; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + break; + } + case PXP_IOC_FLUSH_PHYMEM: + { + int ret; + struct pxp_mem_flush flush; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&flush, + (struct pxp_mem_flush *)arg, + sizeof(struct pxp_mem_flush)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, flush.handle); + if (!obj) + return -EINVAL; + + switch (flush.type) { + case CACHE_CLEAN: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + break; + case CACHE_INVALIDATE: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + case CACHE_FLUSH: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + default: + pr_err("%s: invalid cache flush type\n", __func__); + return -EINVAL; + } + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id, handle; + struct pxp_chan_obj *obj = NULL; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + handle = chan_handle.handle; + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + chan_id = obj->chan->chan_id; + + ret = wait_event_interruptible + (irq_info[chan_id].waitq, + (atomic_read(&irq_info[chan_id].irq_pending) == 0)); + if (ret < 0) + return -ERESTARTSYS; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .unlocked_ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +static struct miscdevice pxp_device_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "pxp_device", + .fops = &pxp_device_fops, +}; + +int register_pxp_device(void) +{ + int ret; + + ret = misc_register(&pxp_device_miscdev); + if (ret) + return ret; + + ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER); + if (ret) + return ret; + spin_lock_init(&(bufhash.hash_lock)); + + pr_debug("PxP_Device registered Successfully\n"); + return 0; +} + +void unregister_pxp_device(void) +{ + pxp_ht_destroy(&bufhash); + misc_deregister(&pxp_device_miscdev); +} diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c new file mode 100644 index 00000000000000..e8cc3f0df6aa33 --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v2.c @@ -0,0 +1,1872 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v2.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + struct clk *clk_disp_axi; /* may exist on some SoC for gating */ + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); + dev_dbg(pxp->dev, "PXP_POWER 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static bool is_yuv(u32 pix_fmt) +{ + switch (pix_fmt) { + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_Y41P: + case PXP_PIX_FMT_VUY444: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YVU410P: + case PXP_PIX_FMT_YUV410P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV420P2: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV422P: + return true; + default: + return false; + } +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_BGRA32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL); + + ctrl = 0; + if (proc_data->scaling) + ; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + /* In default, the block size is set to 8x8 + * But block size can be set to 16x16 due to + * blocksize variable modification + */ + ctrl |= block_size << 23; + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF); + + if ((out_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + dma_addr_t Y, U; + + Y = out_params->paddr; + U = Y + (out_params->width * out_params->height); + + __raw_writel(U, pxp->base + HW_PXP_OUT_BUF2); + } + + if (proc_data->rotate == 90 || proc_data->rotate == 270) + __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) | + BF_PXP_OUT_LRC_Y(out_params->width - 1), + pxp->base + HW_PXP_OUT_LRC); + else + __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) | + BF_PXP_OUT_LRC_Y(out_params->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) { + __raw_writel(out_params->stride * 3, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 || + out_params->pixel_fmt == PXP_PIX_FMT_XRGB32) { + __raw_writel(out_params->stride << 2, + pxp->base + HW_PXP_OUT_PITCH); + } else if ((out_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (out_params->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY || + (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY || + out_params->pixel_fmt == PXP_PIX_FMT_NV12 || + out_params->pixel_fmt == PXP_PIX_FMT_NV21 || + out_params->pixel_fmt == PXP_PIX_FMT_NV16 || + out_params->pixel_fmt == PXP_PIX_FMT_NV61) { + __raw_writel(out_params->stride, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) { + __raw_writel(out_params->stride >> 1, + pxp->base + HW_PXP_OUT_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH); + } + + /* set global alpha if necessary */ + if (out_params->global_alpha_enable) { + __raw_writel(out_params->global_alpha << 24, + pxp->base + HW_PXP_OUT_CTRL_SET); + __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, + pxp->base + HW_PXP_OUT_CTRL_SET); + } +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + u32 pitch = olparams_data->stride ? olparams_data->stride : + olparams_data->width; + + __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF); + + /* Fixme */ + if (olparams_data->width == 0 && olparams_data->height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } else { + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) | + BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1), + pxp->base + HW_PXP_OUT_AS_LRC); + } + + if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32)) { + __raw_writel(pitch << 2, + pxp->base + HW_PXP_AS_PITCH); + } else if ((olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(pitch << 1, + pxp->base + HW_PXP_AS_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_AS_PITCH); + } +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888); + if (!olparams_data->combine_enable) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + olparam |= 0x3 << 16; + } + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB555); + } + + if (olparams_data->global_alpha_enable) { + if (olparams_data->global_override) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Override); + } else { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply); + } + if (olparams_data->alpha_invert) + olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT; + } + if (olparams_data->color_key_enable) + olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY; + + __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + u32 s0param_ulc, s0param_lrc; + + /* contains the coordinate for the PS in the OUTPUT buffer. */ + if ((pxp_conf->s0_param).width == 0 && + (pxp_conf->s0_param).height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC); + } else { + switch (proc_data->rotate) { + case 0: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 90: + s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + case 180: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 270: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + default: + return; + } + __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC); + } + + /* Since user apps always pass the rotated drect + * to this driver, we need to first swap the width + * and height which is used to calculate the scale + * factors later. + */ + if (proc_data->rotate == 90 || proc_data->rotate == 270) { + int temp; + temp = proc_data->drect.width; + proc_data->drect.width = proc_data->drect.height; + proc_data->drect.height = temp; + } +} + +/* crop behavior is re-designed in h/w. */ +static void pxp_set_s0crop(struct pxps *pxp) +{ + /* + * place-holder, it's implemented in other functions in this driver. + * Refer to "Clipping source images" section in RM for detail. + */ +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + proc_data->scaling = 1; + + if (!proc_data->drect.width || !proc_data->drect.height) { + pr_err("Invalid drect width and height passed in\n"); + return -EINVAL; + } + + decx = proc_data->srect.width / proc_data->drect.width; + decy = proc_data->srect.height / proc_data->drect.height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = proc_data->srect.width * 0x1000 / + (proc_data->drect.width * decx); + } else { + if (!is_yuv(s0_params->pixel_fmt) || + (is_yuv(s0_params->pixel_fmt) == + is_yuv(out_params->pixel_fmt)) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) || + (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) { + if ((proc_data->srect.width > 1) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 1) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } else { + if ((proc_data->srect.width > 2) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 2) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = proc_data->srect.height * 0x1000 / + (proc_data->drect.height * decy); + } else { + if ((proc_data->srect.height > 1) && + (proc_data->drect.height > 1)) + yscale = (proc_data->srect.height - 1) * 0x1000 / + (proc_data->drect.height - 1); + else + yscale = proc_data->srect.height * 0x1000 / + proc_data->drect.height; + } + + __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE); + + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + int lut_op = pxp_conf->proc_data.lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = pxp_conf->proc_data.lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && pxp_conf->proc_data.lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp->lut_state = lut_op; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + dma_addr_t Y, U, V; + dma_addr_t Y1, U1, V1; + u32 offset, bpp = 1; + u32 pitch = s0_params->stride ? s0_params->stride : + s0_params->width; + + Y = s0_params->paddr; + + if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + bpp = 2; + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32) + bpp = 4; + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) * bpp; + /* clipping or cropping */ + Y1 = Y + offset; + __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) + s = 1; + + offset = proc_data->srect.top * s0_params->width / 4 + + proc_data->srect.left / 2; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + V = U + ((s0_params->width * s0_params->height) >> s); + V1 = V + offset; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) { + __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF); + } else { + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF); + } + } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + int s = 2; + if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) + s = 1; + + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) / s; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + } + + /* TODO: only support RGB565, Y8, Y4, YUV420 */ + if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P || + s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P || + s0_params->pixel_fmt == PXP_PIX_FMT_NV12 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV21 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV16 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV61 || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) { + __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH); + } + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(pitch >> 1, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32 || + s0_params->pixel_fmt == PXP_PIX_FMT_VUY444) + __raw_writel(pitch << 2, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUYV || + s0_params->pixel_fmt == PXP_PIX_FMT_VYUY || + s0_params->pixel_fmt == PXP_PIX_FMT_YVYU) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else + __raw_writel(0, pxp->base + HW_PXP_PS_PITCH); +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_s0colorkey(pxp); + + if (pxp_conf_data->layer_nr > 2) { + pxp_set_oln(0, pxp); + pxp_set_olparam(0, pxp); + pxp_set_olcolorkey(0, pxp); + } else { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } + + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + if (pxp->clk_disp_axi) + clk_prepare_enable(pxp->clk_disp_axi); + clk_prepare_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + pxp->clk_stat = CLK_STAT_OFF; + pm_runtime_put_sync_suspend(pxp->dev); + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(unsigned long arg) +{ + struct pxps *pxp = (struct pxps *)arg; + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + +// memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param) * 8); +// memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct pxps *pxp) +{ + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + /* set the SFTRST bit to be 1 to reset + * the PXP block to its default state. + */ + pxp_soft_reset(pxp); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx6dl-pxp-dma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + pxpdma_dostart_work(pxp); + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + } + + return 0; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + + pxp->pdev = pdev; + + pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi"); + if (IS_ERR(pxp->clk_disp_axi)) + pxp->clk_disp_axi = NULL; + pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); + + err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, + "pxp-dmaengine", pxp); + if (err) + goto exit; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + goto exit; + } + + device_create_file(&pdev->dev, &dev_attr_block_size); + pxp_clk_enable(pxp); + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + INIT_WORK(&pxp->work, clkoff_callback); + init_timer(&pxp->clk_timer); + pxp->clk_timer.function = pxp_clkoff_timer; + pxp->clk_timer.data = (unsigned long)pxp; + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + register_pxp_device(); + + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +module_platform_driver(pxp_driver); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c new file mode 100644 index 00000000000000..3959199764426b --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -0,0 +1,8106 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v3.h" +#include "reg_bitfields.h" + +#ifdef CONFIG_MXC_FPGA_M4_TEST +#include "cm4_image.c" +#define FPGA_TCML_ADDR 0x0C7F8000 +#define PINCTRL 0x0C018000 +#define PIN_DOUT 0x700 +void __iomem *fpga_tcml_base; +void __iomem *pinctrl_base; +#endif + + +#define PXP_FILL_TIMEOUT 3000 +#define busy_wait(cond) \ + ({ \ + unsigned long end_jiffies = jiffies + \ + msecs_to_jiffies(PXP_FILL_TIMEOUT); \ + bool succeeded = false; \ + do { \ + if (cond) { \ + succeeded = true; \ + break; \ + } \ + cpu_relax(); \ + } while (time_after(end_jiffies, jiffies)); \ + succeeded; \ + }) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +#define CONFIG_FB_MXC_EINK_FPGA + +/* define all the pxp 2d nodes */ +#define PXP_2D_PS 0 +#define PXP_2D_AS 1 +#define PXP_2D_INPUT_FETCH0 2 +#define PXP_2D_INPUT_FETCH1 3 +#define PXP_2D_CSC1 4 +#define PXP_2D_ROTATION1 5 +#define PXP_2D_ALPHA0_S0 6 +#define PXP_2D_ALPHA0_S1 7 +#define PXP_2D_ALPHA1_S0 8 +#define PXP_2D_ALPHA1_S1 9 +#define PXP_2D_CSC2 10 +#define PXP_2D_LUT 11 +#define PXP_2D_ROTATION0 12 +#define PXP_2D_OUT 13 +#define PXP_2D_INPUT_STORE0 14 +#define PXP_2D_INPUT_STORE1 15 +#define PXP_2D_NUM 16 + +#define PXP_2D_ALPHA0_S0_S1 0xaa +#define PXP_2D_ALPHA1_S0_S1 0xbb + +#define PXP_2D_MUX_BASE 50 +#define PXP_2D_MUX_MUX0 (PXP_2D_MUX_BASE + 0) +#define PXP_2D_MUX_MUX1 (PXP_2D_MUX_BASE + 1) +#define PXP_2D_MUX_MUX2 (PXP_2D_MUX_BASE + 2) +#define PXP_2D_MUX_MUX3 (PXP_2D_MUX_BASE + 3) +#define PXP_2D_MUX_MUX4 (PXP_2D_MUX_BASE + 4) +#define PXP_2D_MUX_MUX5 (PXP_2D_MUX_BASE + 5) +#define PXP_2D_MUX_MUX6 (PXP_2D_MUX_BASE + 6) +#define PXP_2D_MUX_MUX7 (PXP_2D_MUX_BASE + 7) +#define PXP_2D_MUX_MUX8 (PXP_2D_MUX_BASE + 8) +#define PXP_2D_MUX_MUX9 (PXP_2D_MUX_BASE + 9) +#define PXP_2D_MUX_MUX10 (PXP_2D_MUX_BASE + 10) +#define PXP_2D_MUX_MUX11 (PXP_2D_MUX_BASE + 11) +#define PXP_2D_MUX_MUX12 (PXP_2D_MUX_BASE + 12) +#define PXP_2D_MUX_MUX13 (PXP_2D_MUX_BASE + 13) +#define PXP_2D_MUX_MUX14 (PXP_2D_MUX_BASE + 14) +#define PXP_2D_MUX_MUX15 (PXP_2D_MUX_BASE + 15) + +/* define pxp 2d node types */ +#define PXP_2D_TYPE_INPUT 1 +#define PXP_2D_TYPE_ALU 2 +#define PXP_2D_TYPE_OUTPUT 3 + +#define DISTANCE_INFINITY 0xffff +#define NO_PATH_NODE 0xffffffff + +#define PXP_MAX_INPUT_NUM 2 +#define PXP_MAX_OUTPUT_NUM 2 + +#define FETCH_NOOP 0x01 +#define FETCH_EXPAND 0x02 +#define FETCH_SHIFT 0x04 + +#define STORE_NOOP 0x01 +#define STORE_SHIFT 0x02 +#define STORE_SHRINK 0x04 + +#define NEED_YUV_SWAP 0x02 + +#define IN_NEED_COMPOSITE (0x01 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_CSC (0x02 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_SCALE (0x04 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_ROTATE_FLIP (0x08 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_FMT_UNIFIED 0x10 +#define IN_NEED_SHIFT 0x20 +#define IN_NEED_LUT (0x40 | IN_NEED_UNIFIED) + +#define OUT_NEED_SHRINK 0x100 +#define OUT_NEED_SHIFT 0x200 + +#define PXP_ROTATE_0 0 +#define PXP_ROTATE_90 1 +#define PXP_ROTATE_180 2 +#define PXP_ROTATE_270 3 + +#define PXP_H_FLIP 1 +#define PXP_V_FLIP 2 + +#define PXP_OP_TYPE_2D 0x001 +#define PXP_OP_TYPE_DITHER 0x002 +#define PXP_OP_TYPE_WFE_A 0x004 +#define PXP_OP_TYPE_WFE_B 0x008 + +/* define store engine output mode */ +#define STORE_MODE_NORMAL 1 +#define STORE_MODE_BYPASS 2 +#define STORE_MODE_DUAL 3 +#define STORE_MODE_HANDSHAKE 4 + +/* define fetch engine input mode */ +#define FETCH_MODE_NORMAL 1 +#define FETCH_MODE_BYPASS 2 +#define FETCH_MODE_HANDSHAKE 3 + +#define COMMON_FMT_BPP 32 + +#define R_COMP 0 +#define G_COMP 1 +#define B_COMP 2 +#define A_COMP 3 + +#define Y_COMP 0 +#define U_COMP 1 +#define V_COMP 2 +#define Y1_COMP 4 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; +static struct kmem_cache *edge_node_cache; +static struct pxp_collision_info col_info; +static dma_addr_t paddr; +static bool v3p_flag; +static int alpha_blending_version; +static bool pxp_legacy; + +struct pxp_dma { + struct dma_device dma; +}; + +enum pxp_alpha_blending_version { + PXP_ALPHA_BLENDING_NONE = 0x0, + PXP_ALPHA_BLENDING_V1 = 0x1, + PXP_ALPHA_BLENDING_V2 = 0x2, +}; + +struct pxp_alpha_global { + unsigned int color_key_enable; + bool combine_enable; + bool global_alpha_enable; + bool global_override; + bool alpha_invert; + bool local_alpha_enable; + unsigned char global_alpha; + int comp_mask; +}; + +struct rectangle { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; +}; + +struct pxp_alpha_info { + uint8_t alpha_mode; + uint8_t rop_type; + + struct pxp_alpha s0_alpha; + struct pxp_alpha s1_alpha; +}; + +struct pxp_op_info{ + uint16_t op_type; + uint16_t rotation; + uint8_t flip; + uint8_t fill_en; + uint32_t fill_data; + uint8_t alpha_blending; + struct pxp_alpha_info alpha_info; + + /* Dithering specific data */ + uint32_t dither_mode; + uint32_t quant_bit; + + /* + * partial: + * 0 - full update + * 1 - partial update + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * lut: + * valid value 0-63 + * set to the lut used for next update + */ + bool partial_update; + bool alpha_en; + bool lut_update; + bool reagl_en; /* enable reagl/-d */ + bool reagl_d_en; /* enable reagl or reagl-d */ + bool detection_only; + int lut; + uint32_t lut_status_1; + uint32_t lut_status_2; +}; + +struct pxp_pixmap { + uint8_t channel_id; + uint8_t bpp; + int32_t pitch; + uint16_t width; + uint16_t height; + struct rectangle crop; + uint32_t rotate; + uint8_t flip; + uint32_t format; /* fourcc pixmap format */ + uint32_t flags; + bool valid; + dma_addr_t paddr; + struct pxp_alpha_global g_alpha; +}; + +struct pxp_task_info { + uint8_t input_num; + uint8_t output_num; + struct pxp_pixmap input[PXP_MAX_INPUT_NUM]; + struct pxp_pixmap output[PXP_MAX_OUTPUT_NUM]; + struct pxp_op_info op_info; + uint32_t pxp_2d_flags; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *ipg_clk; + struct clk *axi_clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + const struct pxp_devdata *devdata; + struct pxp_task_info task; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define to_pxp_task_info(op) container_of((op), struct pxp_task_info, op_info) +#define to_pxp_from_task(task) container_of((task), struct pxps, task) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +static uint8_t active_bpp(uint8_t bpp) +{ + switch(bpp) { + case 8: + return 0x0; + case 16: + return 0x1; + case 32: + return 0x2; + case 64: + return 0x3; + default: + return 0xff; + } +} + +static uint8_t rotate_map(uint32_t degree) +{ + switch (degree) { + case 0: + return PXP_ROTATE_0; + case 90: + return PXP_ROTATE_90; + case 180: + return PXP_ROTATE_180; + case 270: + return PXP_ROTATE_270; + default: + return 0; + } +} + +static uint8_t expand_format(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + return 0x0; + case PXP_PIX_FMT_RGB555: + return 0x1; + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + return 0x5; + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + return 0x6; + case PXP_PIX_FMT_NV16: + return 0x7; + default: + return 0xff; + } +} + +struct color_component { + uint8_t id; + uint8_t offset; + uint8_t length; + uint8_t mask; +}; + +struct color { + uint32_t format; + struct color_component comp[4]; +}; + +struct color rgb_colors[] = { + { + .format = PXP_PIX_FMT_RGB565, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR565, + .comp = { + { .id = R_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = B_COMP, .offset = 11, .length = 6, .mask = 0x3f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA555, + .comp = { + { .id = A_COMP, .offset = 0, .length = 1, .mask = 0x1, }, + { .id = B_COMP, .offset = 1, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 6, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA444, + .comp = { + { .id = A_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = B_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGB24, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR24, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_XBGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ABGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* only one plane yuv formats */ +struct color yuv_colors[] = { + { + .format = PXP_PIX_FMT_GREY, + .comp = { + { .id = Y_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 0, .mask = 0x00, }, + { .id = V_COMP, .offset = 16, .length = 0, .mask = 0x00, }, + { .id = A_COMP, .offset = 24, .length = 0, .mask = 0x00, }, + }, + }, { + .format = PXP_PIX_FMT_YUYV, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_UYVY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVYU, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_VYUY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YUV444, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVU444, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* 4 to 1 mux */ +struct mux { + uint32_t id; + uint8_t mux_inputs[4]; + uint8_t mux_outputs[2]; +}; + +/* Adjacent list structure */ +struct edge_node { + uint32_t adjvex; + uint32_t prev_vnode; + struct edge_node *next; + uint32_t mux_used; + struct mux_config muxes; +}; + +struct vetex_node { + uint8_t type; + struct edge_node *first; +}; + +struct path_node { + struct list_head node; + uint32_t id; + uint32_t distance; + uint32_t prev_node; +}; + +static struct vetex_node adj_list[PXP_2D_NUM]; +static struct path_node path_table[PXP_2D_NUM][PXP_2D_NUM]; + +static bool adj_array_v3[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0}, /* 2 */ + {0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + + +static struct mux muxes_v3[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_INPUT_FETCH0, PXP_2D_INPUT_FETCH1, 0xff}, + .mux_outputs = {PXP_2D_ROTATION1, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S1, PXP_2D_MUX_MUX5}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {PXP_2D_INPUT_FETCH1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S0, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {PXP_2D_MUX_MUX1, PXP_2D_ALPHA1_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX7, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {PXP_2D_ALPHA1_S0_S1, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_CSC2, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {PXP_2D_MUX_MUX5, PXP_2D_CSC2, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX10}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_LUT, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX15}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX14}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_MUX_MUX10, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ROTATION0, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {PXP_2D_INPUT_FETCH1, 0xff, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE1, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_MUX_MUX10, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE0, 0xff}, + }, +}; + +static bool adj_array_v3p[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + +static struct mux muxes_v3p[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {0xff, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_ROTATION0}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX14, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {0xff, PXP_2D_MUX_MUX12, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, +}; + +static void __iomem *pxp_reg_base; + +#define pxp_writel(val, reg) writel(val, pxp_reg_base + (reg)) + +static __attribute__((aligned (1024*4))) unsigned int active_matrix_data_8x8[64]={ + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004, + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004 + }; + +static __attribute__((aligned (1024*4))) unsigned int bit1_dither_data_8x8[64]={ + + 1, 49*2, 13*2, 61*2, 4*2, 52*2, 16*2, 64*2, + 33*2, 17*2, 45*2, 29*2, 36*2, 20*2, 48*2, 32*2, + 9*2, 57*2, 5*2, 53*2, 12*2, 60*2, 8*2, 56*2, + 41*2, 25*2, 37*2, 21*2, 44*2, 28*2, 40*2, 24*2, + 3*2, 51*2, 15*2, 63*2, 2*2, 50*2, 14*2, 62*2, + 35*2, 19*2, 47*2, 31*2, 34*2, 18*2, 46*2, 30*2, + 11*2, 59*2, 7*2, 55*2, 10*2, 58*2, 6*2, 54*2, + 43*2, 27*2, 39*2, 23*2, 42*2, 26*2, 38*2, 22*2 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit2_dither_data_8x8[64]={ + + 1, 49, 13, 61, 4, 52, 16, 64, + 33, 17, 45, 29, 36, 20, 48, 32, + 9, 57, 5, 53, 12, 60, 8, 56, + 41, 25, 37, 21, 44, 28, 40, 24, + 3, 51, 15, 63, 2, 50, 14, 62, + 35, 19, 47, 31, 34, 18, 46, 30, + 11, 59, 7, 55, 10, 58, 6, 54, + 43, 27, 39, 23, 42, 26, 38, 22 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit4_dither_data_8x8[64]={ + + 1, 49/4, 13/4, 61/4, 4/4, 52/4, 16/4, 64/4, + 33/4, 17/4, 45/4, 29/4, 36/4, 20/4, 48/4, 32/4, + 9/4, 57/4, 5/4, 53/4, 12/4, 60/4, 8/4, 56/4, + 41/4, 25/4, 37/4, 21/4, 44/4, 28/4, 40/4, 24/4, + 3/4, 51/4, 15/4, 63/4, 2/4, 50/4, 14/4, 62/4, + 35/4, 19/4, 47/4, 31/4, 34/4, 18/4, 46/4, 30/4, + 11/4, 59/4, 7/4, 55/4, 10/4, 58/4, 6/4, 54/4, + 43/4, 27/4, 39/4, 23/4, 42/4, 26/4, 38/4, 22/4 +}; + +static void pxp_dithering_configure(struct pxps *pxp); +static void pxp_dithering_configure_v3p(struct pxps *pxp); +static void pxp_dithering_process(struct pxps *pxp); +static void pxp_wfe_a_process(struct pxps *pxp); +static void pxp_wfe_a_process_v3p(struct pxps *pxp); +static void pxp_wfe_a_configure(struct pxps *pxp); +static void pxp_wfe_a_configure_v3p(struct pxps *pxp); +static void pxp_wfe_b_process(struct pxps *pxp); +static void pxp_wfe_b_configure(struct pxps *pxp); +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_clr(unsigned int lut); +static void pxp_lut_status_clr_v3p(unsigned int lut); +static void pxp_start2(struct pxps *pxp); +static void pxp_data_path_config_v3p(struct pxps *pxp); +static void pxp_soft_reset(struct pxps *pxp); +static void pxp_collision_detection_disable(struct pxps *pxp); +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status); +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info); +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status); +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_histogram_disable(struct pxps *pxp); +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set); +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set); +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status); +static void pxp_set_colorkey(struct pxps *pxp); + +enum { + DITHER0_LUT = 0x0, /* Select the LUT memory for access */ + DITHER0_ERR0 = 0x1, /* Select the ERR0 memory for access */ + DITHER0_ERR1 = 0x2, /* Select the ERR1 memory for access */ + DITHER1_LUT = 0x3, /* Select the LUT memory for access */ + DITHER2_LUT = 0x4, /* Select the LUT memory for access */ + ALU_A = 0x5, /* Select the ALU instr memory for access */ + ALU_B = 0x6, /* Select the ALU instr memory for access */ + WFE_A = 0x7, /* Select the WFE_A instr memory for access */ + WFE_B = 0x8, /* Select the WFE_B instr memory for access */ + RESERVED = 0x15, +}; + +enum pxp_devtype { + PXP_V3, + PXP_V3P, /* minor changes over V3, use WFE_B to replace WFE_A */ +}; + +#define pxp_is_v3(pxp) (pxp->devdata->version == 30) +#define pxp_is_v3p(pxp) (pxp->devdata->version == 31) + +struct pxp_devdata { + void (*pxp_wfe_a_configure)(struct pxps *pxp); + void (*pxp_wfe_a_process)(struct pxps *pxp); + void (*pxp_lut_status_set)(struct pxps *pxp, unsigned int lut); + void (*pxp_lut_status_clr)(unsigned int lut); + void (*pxp_dithering_configure)(struct pxps *pxp); + void (*pxp_lut_cleanup_multiple)(struct pxps *pxp, u64 lut, bool set); + void (*pxp_data_path_config)(struct pxps *pxp); + unsigned int version; +}; + +static const struct pxp_devdata pxp_devdata[] = { + [PXP_V3] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure, + .pxp_wfe_a_process = pxp_wfe_a_process, + .pxp_lut_status_set = pxp_lut_status_set, + .pxp_lut_status_clr = pxp_lut_status_clr, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, + .pxp_dithering_configure = pxp_dithering_configure, + .pxp_data_path_config = NULL, + .version = 30, + }, + [PXP_V3P] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure_v3p, + .pxp_wfe_a_process = pxp_wfe_a_process_v3p, + .pxp_lut_status_set = pxp_lut_status_set_v3p, + .pxp_lut_status_clr = pxp_lut_status_clr_v3p, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple_v3p, + .pxp_dithering_configure = pxp_dithering_configure_v3p, + .pxp_data_path_config = pxp_data_path_config_v3p, + .version = 31, + }, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND_0)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_ALPHA_A_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_A_CTRL)); + dev_dbg(pxp->dev, "PXP_ALPHA_B_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_B_CTRL)); + dev_dbg(pxp->dev, "PXP_POWER_REG0 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER_REG0)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static void dump_pxp_reg2(struct pxps *pxp) +{ +#ifdef DEBUG + int i = 0; + + for (i=0; i< ((0x33C0/0x10) + 1);i++) { + printk("0x%08x: 0x%08x\n", 0x10*i, __raw_readl(pxp->base + 0x10*i)); + } +#endif +} + +static void print_param(struct pxp_layer_param *p, char *s) +{ + pr_debug("%s: t/l/w/h/s %d/%d/%d/%d/%d, addr %x\n", s, + p->top, p->left, p->width, p->height, p->stride, p->paddr); +} + +/* when it is, return yuv plane number */ +static uint8_t is_yuv(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + return 1; + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + return 2; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YVU422P: + return 3; + default: + return 0; + } +} + +static u32 get_bpp_from_fmt(u32 pix_fmt) +{ + unsigned int bpp = 0; + + switch (pix_fmt) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + bpp = 8; + break; + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + bpp = 16; + break; + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_BGR24: + bpp = 24; + break; + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + bpp = 32; + break; + default: + pr_err("%s: pix_fmt unsupport yet: 0x%x\n", __func__, pix_fmt); + break; + } + + return bpp; +} + +static uint32_t pxp_parse_ps_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGBA888; + break; + default: + pr_debug("PS doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void pxp_set_colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_PS_CLRKEYHIGH_0); + } else { + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYHIGH_0); + } + + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYHIGH_0); + } else { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_AS_CLRKEYHIGH_0); + } +} + +static uint32_t pxp_parse_as_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGBA32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_ARGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB1555; + break; + case PXP_PIX_FMT_ARGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB4444; + break; + case PXP_PIX_FMT_RGBA555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA5551; + break; + case PXP_PIX_FMT_RGBA444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA4444; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_RGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB444; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB565; + break; + default: + pr_debug("AS doesn't support this format\n"); + fmt_ctrl = 0xf; + break; + } + + return fmt_ctrl; +} + +static uint32_t pxp_parse_out_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + pr_debug("OUT doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void set_mux(struct mux_config *path_ctrl) +{ + struct mux_config *mux = path_ctrl; + + *(uint32_t *)path_ctrl = 0xFFFFFFFF; + + mux->mux0_sel = 0; + mux->mux3_sel = 1; + mux->mux6_sel = 1; + mux->mux8_sel = 0; + mux->mux9_sel = 1; + mux->mux11_sel = 0; + mux->mux12_sel = 1; + mux->mux14_sel = 0; +} + +static void set_mux_val(struct mux_config *muxes, + uint32_t mux_id, + uint32_t mux_val) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + muxes->mux0_sel = mux_val; + break; + case 1: + muxes->mux1_sel = mux_val; + break; + case 2: + muxes->mux2_sel = mux_val; + break; + case 3: + muxes->mux3_sel = mux_val; + break; + case 4: + muxes->mux4_sel = mux_val; + break; + case 5: + muxes->mux5_sel = mux_val; + break; + case 6: + muxes->mux6_sel = mux_val; + break; + case 7: + muxes->mux7_sel = mux_val; + break; + case 8: + muxes->mux8_sel = mux_val; + break; + case 9: + muxes->mux9_sel = mux_val; + break; + case 10: + muxes->mux10_sel = mux_val; + break; + case 11: + muxes->mux11_sel = mux_val; + break; + case 12: + muxes->mux12_sel = mux_val; + break; + case 13: + muxes->mux13_sel = mux_val; + break; + case 14: + muxes->mux14_sel = mux_val; + break; + case 15: + muxes->mux15_sel = mux_val; + break; + default: + break; + } +} + +static uint32_t get_mux_val(struct mux_config *muxes, + uint32_t mux_id) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + return muxes->mux0_sel; + case 1: + return muxes->mux1_sel; + case 2: + return muxes->mux2_sel; + case 3: + return muxes->mux3_sel; + case 4: + return muxes->mux4_sel; + case 5: + return muxes->mux5_sel; + case 6: + return muxes->mux6_sel; + case 7: + return muxes->mux7_sel; + case 8: + return muxes->mux8_sel; + case 9: + return muxes->mux9_sel; + case 10: + return muxes->mux10_sel; + case 11: + return muxes->mux11_sel; + case 12: + return muxes->mux12_sel; + case 13: + return muxes->mux13_sel; + case 14: + return muxes->mux14_sel; + case 15: + return muxes->mux15_sel; + default: + return -EINVAL; + } +} + +static uint32_t pxp_store_ctrl_config(struct pxp_pixmap *out, uint8_t mode, + uint8_t fill_en, uint8_t combine_2ch) +{ + struct store_ctrl ctrl; + uint8_t output_active_bpp; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (combine_2ch) { + ctrl.combine_2channel = 1; + if (out) { + output_active_bpp = active_bpp(out->bpp); + ctrl.pack_in_sel = (output_active_bpp < 0x3) ? 1 : 0; + ctrl.store_memory_en = 1; + } + } else { + if (fill_en) { + ctrl.fill_data_en = 1; + ctrl.wr_num_bytes = 2; + } + ctrl.store_memory_en = 1; + } + + if (out->rotate || out->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_store_size_config(struct pxp_pixmap *out) +{ + struct store_size size; + + memset((void*)&size, 0x0, sizeof(size)); + + size.out_height = out->height - 1; + size.out_width = out->width - 1; + + return *(uint32_t *)&size; +} + +static uint32_t pxp_store_pitch_config(struct pxp_pixmap *out0, + struct pxp_pixmap *out1) +{ + struct store_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + pitch.ch0_out_pitch = out0->pitch; + pitch.ch1_out_pitch = out1 ? out1->pitch : 0; + + return *(uint32_t *)&pitch; +} + +static struct color *pxp_find_rgb_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(rgb_colors) / sizeof(struct color); i++) { + if (rgb_colors[i].format == format) + return &rgb_colors[i]; + } + + return NULL; +} + +static struct color_component *pxp_find_comp(struct color *color, uint8_t id) +{ + int i; + + for (i = 0; i < 4; i++) { + if (id == color->comp[i].id) + return &color->comp[i]; + } + + return NULL; +} + +static struct color *pxp_find_yuv_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(yuv_colors) / sizeof(struct color); i++) { + if (yuv_colors[i].format == format) + return &yuv_colors[i]; + } + + return NULL; +} + +static uint64_t pxp_store_d_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct store_d_mask *d_mask) +{ + int i, shift_width, shift_flag, drop = 0; + struct store_d_shift d_shift; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + BUG_ON((in_fmt == out_fmt)); + memset((void*)&d_shift, 0x0, sizeof(d_shift)); + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for (i = 0; i < 4; i++) { + input_comp = &input_color->comp[i]; + if (!input_comp->length) + continue; + + output_comp = pxp_find_comp(output_color, input_comp->id); + if (!output_comp->length) + continue; + + /* only rgb format can drop color bits */ + if (input_comp->length > output_comp->length) { + drop = input_comp->length - output_comp->length; + input_comp->offset += drop; + } + d_mask[i].d_mask_l = output_comp->mask << input_comp->offset; + + shift_width = input_comp->offset - output_comp->offset; + if (shift_width > 0) + shift_flag = 0; /* right shift */ + else if (shift_width < 0) { + shift_flag = 1; /* left shift */ + shift_width = -shift_width; + } else + shift_width = shift_flag = 0; /* no shift require */ + + switch (i) { + case 0: + d_shift.d_shift_width0 = shift_width; + d_shift.d_shift_flag0 = shift_flag; + break; + case 1: + d_shift.d_shift_width1 = shift_width; + d_shift.d_shift_flag1 = shift_flag; + break; + case 2: + d_shift.d_shift_width2 = shift_width; + d_shift.d_shift_flag2 = shift_flag; + break; + case 3: + d_shift.d_shift_width3 = shift_width; + d_shift.d_shift_flag3 = shift_flag; + break; + default: + printk(KERN_ERR "unsupport d shift\n"); + break; + } + + input_comp->offset -= drop; + } + + return *(uint64_t *)&d_shift; +} + +static uint32_t pxp_store_shift_ctrl_config(struct pxp_pixmap *out, + uint8_t shift_bypass) +{ + struct store_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.output_active_bpp = active_bpp(out->bpp); + /* Not general data */ + if (!shift_bypass) { + switch(out->format) { + case PXP_PIX_FMT_YUYV: + shift_bypass = 1; + case PXP_PIX_FMT_YVYU: + shift_ctrl.out_yuv422_1p_en = 1; + break; + case PXP_PIX_FMT_NV16: + shift_bypass = 1; + case PXP_PIX_FMT_NV61: + shift_ctrl.out_yuv422_2p_en = 1; + break; + default: + break; + } + } + shift_ctrl.shift_bypass = shift_bypass; + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_ctrl_config(struct pxp_pixmap *in, + uint8_t mode) +{ + struct fetch_ctrl ctrl; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (mode == FETCH_MODE_NORMAL) + ctrl.bypass_pixel_en = 0; + + if (in->flip == PXP_H_FLIP) + ctrl.hflip = 1; + else if (in->flip == PXP_V_FLIP) + ctrl.vflip = 1; + + ctrl.rotation_angle = rotate_map(in->rotate); + + if (in->rotate || in->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_fetch_active_size_ulc(struct pxp_pixmap *in) +{ + struct fetch_active_size_ulc size_ulc; + + memset((void*)&size_ulc, 0x0, sizeof(size_ulc)); + + size_ulc.active_size_ulc_x = 0; + size_ulc.active_size_ulc_y = 0; + + return *(uint32_t *)&size_ulc; +} + +static uint32_t pxp_fetch_active_size_lrc(struct pxp_pixmap *in) +{ + struct fetch_active_size_lrc size_lrc; + + memset((void*)&size_lrc, 0x0, sizeof(size_lrc)); + + size_lrc.active_size_lrc_x = in->crop.width - 1; + size_lrc.active_size_lrc_y = in->crop.height - 1; + + return *(uint32_t *)&size_lrc; +} + +static uint32_t pxp_fetch_pitch_config(struct pxp_pixmap *in0, + struct pxp_pixmap *in1) +{ + struct fetch_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + if (in0) + pitch.ch0_input_pitch = in0->pitch; + if (in1) + pitch.ch1_input_pitch = in1->pitch; + + return *(uint32_t *)&pitch; +} + +static uint32_t pxp_fetch_shift_ctrl_config(struct pxp_pixmap *in, + uint8_t shift_bypass, + uint8_t need_expand) +{ + uint8_t input_expand_format; + struct fetch_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.input_active_bpp = active_bpp(in->bpp); + shift_ctrl.shift_bypass = shift_bypass; + + if (in->bpp == 32) + need_expand = 0; + + if (need_expand) { + input_expand_format = expand_format(in->format); + + if (input_expand_format <= 0x7) { + shift_ctrl.expand_en = 1; + shift_ctrl.expand_format = input_expand_format; + } + } + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct fetch_shift_width *shift_width) +{ + int i; + struct fetch_shift_offset shift_offset; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + memset((void*)&shift_offset, 0x0, sizeof(shift_offset)); + memset((void*)shift_width, 0x0, sizeof(*shift_width)); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for(i = 0; i < 4; i++) { + output_comp = &output_color->comp[i]; + if (!output_comp->length) + continue; + + input_comp = pxp_find_comp(input_color, output_comp->id); + switch (i) { + case 0: + shift_offset.offset0 = input_comp->offset; + shift_width->width0 = input_comp->length; + break; + case 1: + shift_offset.offset1 = input_comp->offset; + shift_width->width1 = input_comp->length; + break; + case 2: + shift_offset.offset2 = input_comp->offset; + shift_width->width2 = input_comp->length; + break; + case 3: + shift_offset.offset3 = input_comp->offset; + shift_width->width3 = input_comp->length; + break; + } + } + + return *(uint32_t *)&shift_offset; +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_PS_AS_OUT | BM_PXP_CTRL_ENABLE_ROTATE0, + pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static bool fmt_ps_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + /* need word byte swap */ + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_VYUY: + /* need word byte swap */ + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + return true; + default: + return false; + } +} + +static bool fmt_as_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + return true; + default: + return false; + } +} + +static bool fmt_out_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + return true; + default: + return false; + } +} + +/* common means 'ARGB32/XRGB32/YUV444' */ +static uint8_t fmt_fetch_to_common(uint32_t in) +{ + switch (in) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return FETCH_NOOP; + + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_NV16: + return FETCH_EXPAND; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + return FETCH_SHIFT; + + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + return FETCH_EXPAND | FETCH_SHIFT; + + default: + return 0; + } +} + +static uint8_t fmt_store_from_common(uint32_t out) +{ + switch (out) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return STORE_NOOP; + + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_NV16: + return STORE_SHRINK; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_GREY: + return STORE_SHIFT; + + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_NV61: + return STORE_SHIFT | STORE_SHRINK; + + default: + return 0; + } +} + +static void filter_possible_inputs(struct pxp_pixmap *input, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + if (!fmt_ps_support(input->format)) + clear = PXP_2D_PS; + break; + case PXP_2D_AS: + if (!fmt_as_support(input->format)) + clear = PXP_2D_AS; + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((is_yuv(input->format) == 3)) { + clear = position; + break; + } + if ((input->flags & IN_NEED_FMT_UNIFIED) || + is_yuv(input->format) == 2) + if (!fmt_fetch_to_common(input->format)) + clear = position; + break; + default: + pr_err("invalid input node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static void filter_possible_outputs(struct pxp_pixmap *output, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_OUT: + if (!fmt_out_support(output->format)) + clear = PXP_2D_OUT; + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + if (output->flags) { + if (!fmt_store_from_common(output->format)) + clear = position; + } + break; + default: + pr_err("invalid output node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static uint32_t calc_shortest_path(uint32_t *nodes_used) +{ + uint32_t distance = 0; + uint32_t from = 0, to = 0, bypass, end; + + do { + from = find_next_bit((unsigned long *)nodes_used, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + if (path_table[to][from].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[to][from].distance; + /* backtrace */ + end = from; + while (1) { + bypass = path_table[to][end].prev_node; + if (bypass == to) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + } + + to = find_next_bit((unsigned long *)nodes_used, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + if (path_table[from][to].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[from][to].distance; + /* backtrace */ + end = to; + while (1) { + bypass = path_table[from][end].prev_node; + if (bypass == from) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + + from = to + 1; + } while (1); + + return distance; +} + +static uint32_t find_best_path(uint32_t inputs, + uint32_t outputs, + struct pxp_pixmap *in, + uint32_t *nodes_used) +{ + uint32_t outs; + uint32_t nodes_add, best_nodes_used = 0; + uint8_t in_pos = 0, out_pos = 0; + uint32_t nodes_in_path, best_nodes_in_path = 0; + uint32_t best_distance = DISTANCE_INFINITY, distance; + + do { + outs = outputs; + in_pos = find_next_bit((unsigned long *)&inputs, 32, in_pos); + if (in_pos >= sizeof(uint32_t) * 8) + break; + nodes_add = 0; + set_bit(in_pos, (unsigned long *)&nodes_add); + + switch (in_pos) { + case PXP_2D_PS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) { + if (is_yuv(in->format)) + set_bit(PXP_2D_CSC1, + (unsigned long *)&nodes_add); + else + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + } + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_AS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_OUT, (unsigned long *)&outs); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + break; + default: + /* alph0_s0/s1, alpha1_s0/s1 */ + break; + } + + nodes_add |= *nodes_used; + + do { + out_pos = find_next_bit((unsigned long *)&outs, 32, out_pos); + if (out_pos >= sizeof(uint32_t) * 8) + break; + set_bit(out_pos, (unsigned long *)&nodes_add); + + switch(out_pos) { + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S0: + case PXP_2D_ALPHA1_S1: + clear_bit(PXP_2D_CSC2, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_LUT, (unsigned long *)&nodes_add); + break; + default: + break; + } + + nodes_in_path = nodes_add; + distance = calc_shortest_path(&nodes_in_path); + if (best_distance > distance) { + best_distance = distance; + best_nodes_used = nodes_add; + best_nodes_in_path = nodes_in_path; + } + pr_debug("%s: out_pos = %d, nodes_in_path = 0x%x, nodes_add = 0x%x, distance = 0x%x\n", + __func__, out_pos, nodes_in_path, nodes_add, distance); + + clear_bit(out_pos, (unsigned long *)&nodes_add); + + out_pos++; + } while (1); + + in_pos++; + } while (1); + + *nodes_used = best_nodes_used; + + return best_nodes_in_path; +} + +static uint32_t ps_calc_scaling(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct ps_ctrl *ctrl) +{ + struct ps_scale scale; + uint32_t decx, decy; + + memset((void*)&scale, 0x0, sizeof(scale)); + + if (!output->crop.width || !output->crop.height) { + pr_err("Invalid drect width and height passed in\n"); + return 0; + } + + if ((input->rotate == 90) || (input->rotate == 270)) + swap(output->crop.width, output->crop.height); + + decx = input->crop.width / output->crop.width; + decy = input->crop.height / output->crop.height; + + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + ctrl->decx = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + ctrl->decx = 2; + } else if (decx >= 8) { + decx = 8; + ctrl->decx = 3; + } + scale.xscale = input->crop.width * 0x1000 / + (output->crop.width * decx); + } else { + if (!is_yuv(input->format) || + (is_yuv(input->format) == is_yuv(output->format)) || + (input->format == PXP_PIX_FMT_GREY) || + (input->format == PXP_PIX_FMT_GY04) || + (input->format == PXP_PIX_FMT_VUY444)) { + if ((input->crop.width > 1) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 1) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } else { + if ((input->crop.width > 2) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 2) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } + } + + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ctrl->decy = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ctrl->decy = 2; + } else if (decy >= 8) { + decy = 8; + ctrl->decy = 3; + } + scale.yscale = input->crop.height * 0x1000 / + (output->crop.height * decy); + } else { + if ((input->crop.height > 1) && (output->crop.height > 1)) + scale.yscale = (input->crop.height - 1) * 0x1000 / + (output->crop.height - 1); + else + scale.yscale = input->crop.height * 0x1000 / + output->crop.height; + } + + return *(uint32_t *)&scale; +} + +static int pxp_ps_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset, U, V; + struct ps_ctrl ctrl; + struct coordinate out_ps_ulc, out_ps_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_ps_fmt(input->format); + + switch (output->rotate) { + case 0: + out_ps_ulc.x = output->crop.x; + out_ps_ulc.y = output->crop.y; + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 90: + out_ps_ulc.x = output->crop.y; + out_ps_ulc.y = output->width - (output->crop.x + output->crop.width); + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + case 180: + out_ps_ulc.x = output->width - (output->crop.x + output->crop.width); + out_ps_ulc.y = output->height - (output->crop.y + output->crop.height); + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 270: + out_ps_ulc.x = output->height - (output->crop.y + output->crop.height); + out_ps_ulc.y = output->crop.x; + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + default: + pr_err("PxP only support rotate 0 90 180 270\n"); + return -EINVAL; + break; + } + + if ((input->format == PXP_PIX_FMT_YUYV) || + (input->format == PXP_PIX_FMT_YVYU)) + ctrl.wb_swap = 1; + + pxp_writel(ps_calc_scaling(input, output, &ctrl), + HW_PXP_PS_SCALE); + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_PS_CTRL); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + pxp_writel(input->paddr + offset, HW_PXP_PS_BUF); + + switch (is_yuv(input->format)) { + case 0: /* RGB */ + case 1: /* 1 Plane YUV */ + break; + case 2: /* NV16,NV61,NV12,NV21 */ + if ((input->format == PXP_PIX_FMT_NV16) || + (input->format == PXP_PIX_FMT_NV61)) { + U = input->paddr + input->width * input->height; + pxp_writel(U + offset, HW_PXP_PS_UBUF); + } + else { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + } + break; + case 3: /* YUV422P, YUV420P */ + if (input->format == PXP_PIX_FMT_YUV422P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 1); + pxp_writel(V + (offset >> 1), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YUV420P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 2), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 2); + pxp_writel(V + (offset >> 2), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YVU420P) { + U = input->paddr + input->width * input->height; + V = U + (input->width * input->height >> 2); + pxp_writel(U + (offset >> 2), HW_PXP_PS_VBUF); + pxp_writel(V + (offset >> 2), HW_PXP_PS_UBUF); + } + + break; + default: + break; + } + + pxp_writel(input->pitch, HW_PXP_PS_PITCH); + pxp_writel(*(uint32_t *)&out_ps_ulc, HW_PXP_OUT_PS_ULC); + pxp_writel(*(uint32_t *)&out_ps_lrc, HW_PXP_OUT_PS_LRC); + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_as_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset; + struct as_ctrl ctrl; + struct coordinate out_as_ulc, out_as_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_as_fmt(input->format); + + if (alpha_blending_version == PXP_ALPHA_BLENDING_V1) { + if (input->format == PXP_PIX_FMT_BGRA32) { + if (!input->g_alpha.combine_enable) { + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs; + ctrl.rop = 0x3; + } + } + + if (input->g_alpha.global_alpha_enable) { + if (input->g_alpha.global_override) + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Override; + else + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply; + + if (input->g_alpha.alpha_invert) + ctrl.alpha0_invert = 0x1; + } + + if (input->g_alpha.color_key_enable) { + ctrl.enable_colorkey = 1; + } + + ctrl.alpha = input->g_alpha.global_alpha; + } + + out_as_ulc.x = out_as_ulc.y = 0; + if (input->g_alpha.combine_enable) { + out_as_lrc.x = input->width - 1; + out_as_lrc.y = input->height - 1; + } else { + out_as_lrc.x = output->crop.width - 1; + out_as_lrc.y = output->crop.height - 1; + } + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + pxp_writel(input->paddr + offset, HW_PXP_AS_BUF); + + pxp_writel(input->pitch, HW_PXP_AS_PITCH); + pxp_writel(*(uint32_t *)&out_as_ulc, HW_PXP_OUT_AS_ULC); + pxp_writel(*(uint32_t *)&out_as_lrc, HW_PXP_OUT_AS_LRC); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_AS_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static uint32_t pxp_fetch_size_config(struct pxp_pixmap *input) +{ + struct fetch_size total_size; + + memset((void*)&total_size, 0x0, sizeof(total_size)); + + total_size.input_total_width = input->width - 1; + total_size.input_total_height = input->height - 1; + + return *(uint32_t *)&total_size; +} + +static int pxp_fetch_config(struct pxp_pixmap *input, + uint32_t fetch_index) +{ + uint8_t shift_bypass = 1, expand_en = 0; + uint32_t flags, pitch = 0, offset, UV = 0; + uint32_t in_fmt, out_fmt; + uint32_t size_ulc, size_lrc; + uint32_t fetch_ctrl, total_size; + uint32_t shift_ctrl, shift_offset = 0; + struct fetch_shift_width shift_width; + + memset((unsigned int *)&shift_width, 0x0, sizeof(shift_width)); + fetch_ctrl = pxp_fetch_ctrl_config(input, FETCH_MODE_NORMAL); + size_ulc = pxp_fetch_active_size_ulc(input); + size_lrc = pxp_fetch_active_size_lrc(input); + total_size = pxp_fetch_size_config(input); + + if (input->flags) { + flags = fmt_fetch_to_common(input->format); + shift_bypass = (flags & FETCH_SHIFT) ? 0 : 1; + expand_en = (flags & FETCH_EXPAND) ? 1 : 0; + + if (!shift_bypass) { + if (expand_en) { + if (is_yuv(input->format)) { + in_fmt = PXP_PIX_FMT_YVU444; + out_fmt = PXP_PIX_FMT_YUV444; + } else { + in_fmt = PXP_PIX_FMT_ABGR32; + out_fmt = PXP_PIX_FMT_ARGB32; + } + } else { + in_fmt = input->format; + out_fmt = is_yuv(input->format) ? + PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + } + + shift_offset = pxp_fetch_shift_calc(in_fmt, out_fmt, + &shift_width); + } + } + shift_ctrl = pxp_fetch_shift_ctrl_config(input, shift_bypass, expand_en); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + if (is_yuv(input->format) == 2) + UV = input->paddr + input->width * input->height; + + switch (fetch_index) { + case PXP_2D_INPUT_FETCH0: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(input, NULL); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH0); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0); + break; + case PXP_2D_INPUT_FETCH1: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(NULL, input); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH1); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH1); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1); + break; + default: + break; + } + + pxp_writel(pitch, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc1_config(struct pxp_pixmap *input, + bool is_ycbcr) +{ + BUG_ON(!is_yuv(input->format)); + + if (!is_ycbcr) { + /* YUV -> RGB */ + pxp_writel(0x04030000, HW_PXP_CSC1_COEF0); + pxp_writel(0x01230208, HW_PXP_CSC1_COEF1); + pxp_writel(0x076b079c, HW_PXP_CSC1_COEF2); + + return 0; + } + + /* YCbCr -> RGB */ + pxp_writel(0x84ab01f0, HW_PXP_CSC1_COEF0); + pxp_writel(0x01980204, HW_PXP_CSC1_COEF1); + pxp_writel(0x0730079c, HW_PXP_CSC1_COEF2); + + return 0; +} + +static int pxp_rotation1_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP1(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP1(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE1(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE1(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_rotation0_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP0(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP0(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE0(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE0(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc2_config(struct pxp_pixmap *output) +{ + if (is_yuv(output->format)) { + /* RGB -> YUV */ + pxp_writel(0x4, HW_PXP_CSC2_CTRL); + pxp_writel(0x0096004D, HW_PXP_CSC2_COEF0); + pxp_writel(0x05DA001D, HW_PXP_CSC2_COEF1); + pxp_writel(0x007005B6, HW_PXP_CSC2_COEF2); + pxp_writel(0x057C009E, HW_PXP_CSC2_COEF3); + pxp_writel(0x000005E6, HW_PXP_CSC2_COEF4); + pxp_writel(0x00000000, HW_PXP_CSC2_COEF5); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_CSC2(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_out_config(struct pxp_pixmap *output) +{ + uint32_t offset, UV; + struct out_ctrl ctrl; + struct coordinate out_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_out_fmt(output->format); + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_OUT_CTRL); + + pxp_writel(output->paddr, HW_PXP_OUT_BUF); + if (is_yuv(output->format) == 2) { + UV = output->paddr + output->width * output->height; + if ((output->format == PXP_PIX_FMT_NV16) || + (output->format == PXP_PIX_FMT_NV61)) + pxp_writel(UV + offset, HW_PXP_OUT_BUF2); + else + pxp_writel(UV + (offset >> 1), HW_PXP_OUT_BUF2); + } + + if (output->rotate == 90 || output->rotate == 270) { + out_lrc.y = output->width - 1; + out_lrc.x = output->height - 1; + } else { + out_lrc.x = output->width - 1; + out_lrc.y = output->height - 1; + } + + pxp_writel(*(uint32_t *)&out_lrc, HW_PXP_OUT_LRC); + + pxp_writel(output->pitch, HW_PXP_OUT_PITCH); + + /* set global alpha if necessary */ + if (output->g_alpha.global_alpha_enable) { + pxp_writel(output->g_alpha.global_alpha << 24, HW_PXP_OUT_CTRL_SET); + pxp_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, HW_PXP_OUT_CTRL_SET); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_store_config(struct pxp_pixmap *output, + struct pxp_op_info *op) +{ + uint8_t combine_2ch, flags; + uint32_t in_fmt, out_fmt, offset, UV = 0; + uint64_t d_shift = 0; + struct store_d_mask d_mask[8]; + uint32_t store_ctrl, store_size, store_pitch, shift_ctrl; + + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + combine_2ch = (output->bpp == 64) ? 1 : 0; + store_ctrl = pxp_store_ctrl_config(output, STORE_MODE_NORMAL, + op->fill_en, combine_2ch); + store_size = pxp_store_size_config(output); + store_pitch = pxp_store_pitch_config(output, NULL); + + pxp_writel(store_ctrl, HW_PXP_INPUT_STORE_CTRL_CH0); + + if (output->flags) { + flags = fmt_store_from_common(output->format); + if (flags == STORE_NOOP) + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + else if (flags & STORE_SHIFT) { + in_fmt = is_yuv(output->format) ? PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + out_fmt = (flags & STORE_SHRINK) ? PXP_PIX_FMT_YVU444 : + output->format; + d_shift = pxp_store_d_shift_calc(in_fmt, out_fmt, d_mask); + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + + if (flags & STORE_SHIFT) { + pxp_writel((uint32_t)d_shift, HW_PXP_INPUT_STORE_D_SHIFT_L_CH0); + /* TODO use only 4 masks */ + pxp_writel(d_mask[0].d_mask_l, HW_PXP_INPUT_STORE_D_MASK0_L_CH0); + pxp_writel(d_mask[0].d_mask_h, HW_PXP_INPUT_STORE_D_MASK0_H_CH0); + pxp_writel(d_mask[1].d_mask_l, HW_PXP_INPUT_STORE_D_MASK1_L_CH0); + pxp_writel(d_mask[1].d_mask_h, HW_PXP_INPUT_STORE_D_MASK1_H_CH0); + pxp_writel(d_mask[2].d_mask_l, HW_PXP_INPUT_STORE_D_MASK2_L_CH0); + pxp_writel(d_mask[2].d_mask_h, HW_PXP_INPUT_STORE_D_MASK2_H_CH0); + pxp_writel(d_mask[3].d_mask_l, HW_PXP_INPUT_STORE_D_MASK3_L_CH0); + pxp_writel(d_mask[3].d_mask_h, HW_PXP_INPUT_STORE_D_MASK3_H_CH0); + } + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + + pxp_writel(shift_ctrl, HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0); + pxp_writel(store_size, HW_PXP_INPUT_STORE_SIZE_CH0); + pxp_writel(store_pitch, HW_PXP_INPUT_STORE_PITCH); + if (op->fill_en) { + uint32_t lrc; + + lrc = (output->width - 1) | ((output->height - 1) << 16); + pxp_writel(op->fill_data, HW_PXP_INPUT_STORE_FILL_DATA_CH0); + + pxp_writel(0x1, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(0, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + } + + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + if (is_yuv(output->format == 2)) { + UV = output->paddr + output->width * output->height; + pxp_writel(UV + offset, HW_PXP_INPUT_STORE_ADDR_1_CH0); + } + pxp_writel(output->paddr + offset, HW_PXP_INPUT_STORE_ADDR_0_CH0); + + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_alpha_config(struct pxp_op_info *op, + uint8_t alpha_node) +{ + uint32_t as_ctrl; + struct pxp_alpha_ctrl alpha_ctrl; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_alpha *s0_alpha, *s1_alpha; + + memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); + + if (alpha_blending_version != PXP_ALPHA_BLENDING_V1) { + if (alpha->alpha_mode == ALPHA_MODE_ROP) { + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + as_ctrl = __raw_readl(pxp_reg_base + HW_PXP_AS_CTRL); + as_ctrl |= BF_PXP_AS_CTRL_ALPHA_CTRL(BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + as_ctrl |= BF_PXP_AS_CTRL_ROP(alpha->rop_type); + pxp_writel(as_ctrl, HW_PXP_AS_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE | + BF_PXP_ALPHA_B_CTRL_1_ROP(alpha->rop_type), + HW_PXP_ALPHA_B_CTRL_1); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + + return 0; + } + + s0_alpha = &alpha->s0_alpha; + s1_alpha = &alpha->s1_alpha; + + alpha_ctrl.poter_duff_enable = 1; + + alpha_ctrl.s0_s1_factor_mode = s1_alpha->factor_mode; + alpha_ctrl.s0_global_alpha_mode = s0_alpha->global_alpha_mode; + alpha_ctrl.s0_alpha_mode = s0_alpha->alpha_mode; + alpha_ctrl.s0_color_mode = s0_alpha->color_mode; + + alpha_ctrl.s1_s0_factor_mode = s0_alpha->factor_mode; + alpha_ctrl.s1_global_alpha_mode = s1_alpha->global_alpha_mode; + alpha_ctrl.s1_alpha_mode = s1_alpha->alpha_mode; + alpha_ctrl.s1_color_mode = s1_alpha->color_mode; + + alpha_ctrl.s0_global_alpha = s0_alpha->global_alpha_value; + alpha_ctrl.s1_global_alpha = s1_alpha->global_alpha_value; + + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_B_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + } + + return 0; +} + +static void pxp_lut_config(struct pxp_op_info *op) +{ + struct pxp_task_info *task = to_pxp_task_info(op); + struct pxps *pxp = to_pxp_from_task(task); + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + int lut_op = proc_data->lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = proc_data->lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && proc_data->lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT, + HW_PXP_CTRL_SET); + + pxp->lut_state = lut_op; +} + +static int pxp_2d_task_config(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct pxp_op_info *op, + uint32_t nodes_used) +{ + uint8_t position = 0; + + + do { + position = find_next_bit((unsigned long *)&nodes_used, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + pxp_ps_config(input, output); + break; + case PXP_2D_AS: + pxp_as_config(input, output); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + pxp_fetch_config(input, position); + break; + case PXP_2D_CSC1: + pxp_csc1_config(input, true); + break; + case PXP_2D_ROTATION1: + pxp_rotation1_config(input); + break; + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA1_S0: + pxp_alpha_config(op, position); + break; + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S1: + break; + case PXP_2D_CSC2: + pxp_csc2_config(output); + break; + case PXP_2D_LUT: + pxp_lut_config(op); + break; + case PXP_2D_ROTATION0: + pxp_rotation0_config(input); + break; + case PXP_2D_OUT: + pxp_out_config(output); + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + pxp_store_config(output, op); + break; + default: + break; + } + + position++; + } while (1); + + return 0; +} + +static void mux_config_helper(struct mux_config *path_ctrl, + struct edge_node *enode) +{ + uint32_t mux_val, mux_pos = 0; + + if (enode->mux_used) { + do { + mux_pos = find_next_bit((unsigned long *)&enode->mux_used, + 32, mux_pos); + if (mux_pos >= 16) + break; + + mux_val = get_mux_val(&enode->muxes, mux_pos); + pr_debug("%s: mux_pos = %d, mux_val = %d\n", + __func__, mux_pos, mux_val); + set_mux_val(path_ctrl, mux_pos, mux_val); + + mux_pos++; + } while (1); + } +} + +static void pxp_2d_calc_mux(uint32_t nodes, struct mux_config *path_ctrl) +{ + struct edge_node *enode; + uint8_t from = 0, to = 0; + + do { + from = find_next_bit((unsigned long *)&nodes, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + enode = adj_list[to].first; + while (enode) { + if (enode->adjvex == from) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + } + + to = find_next_bit((unsigned long *)&nodes, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + enode = adj_list[from].first; + while (enode) { + if (enode->adjvex == to) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + + from = to + 1; + } while (1); +} + +static int pxp_2d_op_handler(struct pxps *pxp) +{ + struct mux_config path_ctrl0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_pixmap *input, *output, *input_s0, *input_s1; + uint32_t possible_inputs, possible_outputs; + uint32_t possible_inputs_s0, possible_inputs_s1; + uint32_t inputs_filter_s0, inputs_filter_s1; + uint32_t nodes_used = 0, nodes_in_path; + uint32_t partial_nodes_used = 0; + uint32_t nodes_used_s0 = 0, nodes_used_s1 = 0; + uint32_t nodes_in_path_s0, nodes_in_path_s1; + + output = &task->output[0]; + if (!output->pitch) + return -EINVAL; + + *(unsigned int*)&path_ctrl0 = 0xffffffff; + +reparse: + switch (task->input_num) { + case 0: + /* Fill operation: use input store engine */ + if (is_yuv(output->format) > 1) + return -EINVAL; + + if (output->bpp > 32) + return -EINVAL; + + nodes_used = 1 << PXP_2D_INPUT_STORE0; + pxp_2d_task_config(NULL, output, op, nodes_used); + break; + case 1: + /* No Composite */ + possible_inputs = (1 << PXP_2D_PS) | + (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + input = &task->input[0]; + if (!input->pitch) + return -EINVAL; + + if (input->rotate || input->flip) { + input->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input->rotate; + output->flip = input->flip; + } + + if (!is_yuv(input->format) != !is_yuv(output->format)) + input->flags |= IN_NEED_CSC; + else if (input->format != output->format) + input->flags |= IN_NEED_FMT_UNIFIED; + + if ((input->rotate == 90) || (input->rotate == 270)) { + if ((input->crop.width != output->crop.height) || + (input->crop.height != output->crop.width)) + input->flags |= IN_NEED_SCALE; + } else { + if ((input->crop.width != output->crop.width) || + (input->crop.height != output->crop.height)) + input->flags |= IN_NEED_SCALE; + } + + if (input->flags) { + /* only ps has scaling function */ + if ((input->flags & IN_NEED_SCALE) == IN_NEED_SCALE) + possible_inputs = 1 << PXP_2D_PS; + output->flags |= (output->bpp < 32) ? OUT_NEED_SHRINK : + OUT_NEED_SHIFT; + } + + filter_possible_inputs(input, &possible_inputs); + filter_possible_outputs(output, &possible_outputs); + + if (!possible_inputs || !possible_outputs) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + if (proc_data->lut_transform) + nodes_used |= (1 << PXP_2D_LUT); + + nodes_in_path = find_best_path(possible_inputs, + possible_outputs, + input, &nodes_used); + + if (nodes_in_path & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path); + } + + if (nodes_used & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used); + } + + pr_debug("%s: nodes_in_path = 0x%x, nodes_used = 0x%x\n", + __func__, nodes_in_path, nodes_used); + if (!nodes_used) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + /* If use input fetch0, should use + * alpha b instead of alpha a */ + if (nodes_in_path & (1 << PXP_2D_ALPHA0_S0)) { + if (nodes_in_path & (1 << PXP_2D_INPUT_FETCH0)) { + clear_bit(PXP_2D_ALPHA0_S0, + (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ALPHA1_S1, + (unsigned long *)&nodes_in_path); + } + } + + /* In this case input read in + * by input fetch engine + */ + if ((nodes_in_path & (1 << PXP_2D_ALPHA1_S1)) || + (nodes_in_path & (1 << PXP_2D_ALPHA1_S0))) { + memcpy(&task->input[1], input, sizeof(*input)); + if (input->rotate == 90 || input->rotate == 270) { + uint32_t temp; + + input = &task->input[1]; + input->rotate = 0; + input->flags = 0; + temp = input->width; + input->width = input->height; + input->height = temp; + input->pitch = input->width * (input->bpp >> 3); + temp = input->crop.width; + input->crop.width = input->crop.height; + input->crop.height = temp; + } + + op->alpha_info.alpha_mode = ALPHA_MODE_ROP; + /* s0 AND s1 */ + op->alpha_info.rop_type = 0x0; + task->input_num = 2; + goto reparse; + } + + pxp_2d_calc_mux(nodes_in_path, &path_ctrl0); + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_2d_task_config(input, output, op, nodes_used); + break; + case 2: + /* Composite */ + input_s0 = &task->input[0]; + input_s1 = &task->input[1]; + if (!input_s0->pitch || !input_s1->pitch) + return -EINVAL; + + possible_inputs_s0 = (1 << PXP_2D_PS) | + (1 << PXP_2D_INPUT_FETCH0) | + (1 << PXP_2D_INPUT_FETCH1); + possible_inputs_s1 = (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + if (input_s0->rotate || input_s0->flip) { + input_s0->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input_s0->rotate; + output->flip = input_s0->flip; + } + if (input_s1->rotate || input_s1->flip) { + input_s1->flags |= IN_NEED_ROTATE_FLIP; + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + } + + if (is_yuv(input_s0->format) && is_yuv(input_s1->format)) + return -EINVAL; + + if (is_yuv(input_s0->format)){ + /* need do yuv -> rgb conversion by csc1 */ + possible_inputs_s0 = 1 << PXP_2D_PS; + input_s0->flags |= IN_NEED_CSC; + } else if (is_yuv(input_s1->format)) { + possible_inputs_s1 = 1 << PXP_2D_PS; + input_s1->flags |= IN_NEED_CSC; + } + + filter_possible_inputs(input_s0, &possible_inputs_s0); + filter_possible_inputs(input_s1, &possible_inputs_s1); + + if (!possible_inputs_s0 || !possible_inputs_s0) + return -EINVAL; + + filter_possible_outputs(output, &possible_outputs); + if (!possible_outputs) + return -EINVAL; + + pr_debug("%s: poss_s0 = 0x%x, poss_s1 = 0x%x, poss_out = 0x%x\n", + __func__, possible_inputs_s0, possible_inputs_s1, possible_outputs); + + inputs_filter_s0 = possible_inputs_s0; + inputs_filter_s1 = possible_inputs_s1; + + /* Using alpha0, possible cases: + * 1. PS --> S0, AS --> S1; + */ + if (possible_inputs_s1 & (1 << PXP_2D_AS)) { + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH1, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + goto alpha1; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA0_S0, + input_s0, + &partial_nodes_used); + if (!nodes_in_path_s0) + goto alpha1; + + nodes_used_s0 |= partial_nodes_used; + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA0_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + if (!(nodes_in_path_s0 & possible_outputs)) + goto alpha1; + nodes_used_s0 |= partial_nodes_used; + + possible_inputs_s1 = (1 << PXP_2D_AS); + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA0_S1, + input_s1, + &nodes_used_s1); + if (!nodes_in_path_s1) + goto alpha1; + + goto config; + } +alpha1: + partial_nodes_used = 0; + possible_inputs_s0 = inputs_filter_s0; + possible_inputs_s1 = inputs_filter_s1; + + /* Using alpha1, possible cases: + * 1. FETCH1 --> S0, FETCH0 --> S1; + */ + clear_bit(PXP_2D_PS, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_OUT, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + return -EINVAL; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA1_S0, + input_s0, + &partial_nodes_used); + pr_debug("%s: nodes_in_path_s0 = 0x%x\n", __func__, nodes_in_path_s0); + BUG_ON(!nodes_in_path_s0); + + nodes_used_s0 |= partial_nodes_used; + if ((nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH0)) || + (nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH1))) + clear_bit(PXP_2D_OUT, (unsigned long *)&possible_outputs); + else + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA1_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + BUG_ON(!(nodes_in_path_s0 & possible_outputs)); + nodes_used_s0 |= partial_nodes_used; + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0); + + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + BUG_ON(!possible_inputs_s1); + + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA1_S1, + input_s1, + &nodes_used_s1); + pr_debug("%s: poss_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, possible_inputs_s1, nodes_used_s1); + BUG_ON(!nodes_in_path_s1); + /* To workaround an IC bug */ + path_ctrl0.mux4_sel = 0x0; +config: + if (nodes_in_path_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path_s0); + } + + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x, nodes_in_path_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0, nodes_in_path_s1, nodes_used_s1); + pxp_2d_calc_mux(nodes_in_path_s0, &path_ctrl0); + pxp_2d_calc_mux(nodes_in_path_s1, &path_ctrl0); + + pr_debug("%s: s0 paddr = 0x%x, s1 paddr = 0x%x, out paddr = 0x%x\n", + __func__, input_s0->paddr, input_s1->paddr, output->paddr); + + if (nodes_used_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used_s0); + } + + pxp_2d_task_config(input_s0, output, op, nodes_used_s0); + pxp_2d_task_config(input_s1, output, op, nodes_used_s1); + break; + default: + break; + } + + __raw_writel(proc_data->bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND_0); + pxp_set_colorkey(pxp); + + if (proc_data->lut_transform && pxp_is_v3(pxp)) + set_mux(&path_ctrl0); + + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_writel(*(uint32_t *)&path_ctrl0, HW_PXP_DATA_PATH_CTRL0); + + return 0; +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + int ret = 0; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf_data->proc_data; + + switch (op->op_type) { + case PXP_OP_TYPE_2D: + pxp_writel(0xffffffff, HW_PXP_OUT_AS_ULC); + pxp_writel(0x0, HW_PXP_OUT_AS_LRC); + pxp_writel(0xffffffff, HW_PXP_OUT_PS_ULC); + pxp_writel(0x0, HW_PXP_OUT_PS_LRC); + pxp_writel(0x0, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(0x40000000, HW_PXP_CSC1_COEF0); + ret = pxp_2d_op_handler(pxp); + break; + case PXP_OP_TYPE_DITHER: + pxp_dithering_process(pxp); + if (pxp_is_v3p(pxp)) { + __raw_writel( + BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_DITHER | + BM_PXP_CTRL_ENABLE_CSC2 | + BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_PS_AS_OUT, + pxp->base + HW_PXP_CTRL_SET); + return 0; + } + break; + case PXP_OP_TYPE_WFE_A: + pxp_luts_deactivate(pxp, proc_data->lut_sels); + + if (proc_data->lut_cleanup == 0) { + /* We should enable histogram in standard mode + * in wfe_a processing for waveform mode selection + */ + pxp_histogram_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + + pxp_luts_activate(pxp, (u64)proc_data->lut_status_1 | + ((u64)proc_data->lut_status_2 << 32)); + + /* collision detection should be always enable in standard mode */ + pxp_collision_detection_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + } + + if (pxp->devdata && pxp->devdata->pxp_wfe_a_configure) + pxp->devdata->pxp_wfe_a_configure(pxp); + if (pxp->devdata && pxp->devdata->pxp_wfe_a_process) + pxp->devdata->pxp_wfe_a_process(pxp); + break; + case PXP_OP_TYPE_WFE_B: + pxp_wfe_b_configure(pxp); + pxp_wfe_b_process(pxp); + break; + default: + /* Unsupport */ + ret = -EINVAL; + pr_err("Invalid pxp operation type passed\n"); + break; + } + if (pxp_conf_data->layer_nr <= 2) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } + + return ret; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + clk_prepare_enable(pxp->ipg_clk); + clk_prepare_enable(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_OFF; + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + pm_runtime_put_sync_suspend(pxp->dev); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(unsigned long arg) +{ + struct pxps *pxp = (struct pxps *)arg; + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +static int convert_param_to_pixmap(struct pxp_pixmap *pixmap, + struct pxp_layer_param *param) +{ + if (!param->width || !param->height) + return -EINVAL; + + pixmap->width = param->width; + pixmap->height = param->height; + pixmap->format = param->pixel_fmt; + pixmap->paddr = param->paddr; + pixmap->bpp = get_bpp_from_fmt(pixmap->format); + + if (pxp_legacy) { + pixmap->pitch = (param->stride) ? (param->stride * pixmap->bpp >> 3) : + (param->width * pixmap->bpp >> 3); + } else { + if (!param->stride || (param->stride == param->width)) + pixmap->pitch = param->width * pixmap->bpp >> 3; + else + pixmap->pitch = param->stride; + } + + pixmap->crop.x = param->crop.left; + pixmap->crop.y = param->crop.top; + pixmap->crop.width = param->crop.width; + pixmap->crop.height = param->crop.height; + + pixmap->g_alpha.color_key_enable = param->color_key_enable; + pixmap->g_alpha.combine_enable = param->combine_enable; + pixmap->g_alpha.global_alpha_enable = param->global_alpha_enable; + pixmap->g_alpha.global_override = param->global_override; + pixmap->g_alpha.global_alpha = param->global_alpha; + pixmap->g_alpha.alpha_invert = param->alpha_invert; + pixmap->g_alpha.local_alpha_enable = param->local_alpha_enable; + pixmap->g_alpha.comp_mask = param->comp_mask; + + return 0; +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_layer_param *param = NULL; + struct pxp_pixmap *input, *output; + int i = 0, ret; + bool combine_enable = false; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + + memset(task, 0, sizeof(*task)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + if (proc_data->combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V2; + else + alpha_blending_version = PXP_ALPHA_BLENDING_NONE; + + pxp_legacy = (proc_data->pxp_legacy) ? true : false; + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + if (pxp->pxp_conf_state.ol_param[i - 1].width != 0 && + pxp->pxp_conf_state.ol_param[i - 1].height != 0) { + if (pxp->pxp_conf_state.ol_param[i - 1].combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V1; + } + } + + if (proc_data->engine_enable & PXP_ENABLE_DITHER) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH0) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH1) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE0) + memcpy(&pxp->pxp_conf_state.dither_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE1) + memcpy(&pxp->pxp_conf_state.dither_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_DITHER; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_A) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_A; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_B) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_B; + } + + i++; + } + + if (!op->op_type) { + op->op_type = PXP_OP_TYPE_2D; + + if ((alpha_blending_version == PXP_ALPHA_BLENDING_V1) || + (alpha_blending_version == PXP_ALPHA_BLENDING_V2)) + combine_enable = true; + + if (combine_enable) + task->input_num = 2; + else if (proc_data->fill_en) + task->input_num = 0; + else + task->input_num = 1; + + output = &task->output[0]; + switch (task->input_num) { + case 0: + op->fill_en = 1; + op->fill_data = proc_data->bgcolor; + break; + case 1: + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + if (ret < 0) { + param = &pxp->pxp_conf_state.ol_param[0]; + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + } else { + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + } + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + break; + case 2: + /* s0 */ + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + alpha->s0_alpha = param->alpha; + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + + /* overlay */ + param = &pxp->pxp_conf_state.ol_param[0]; + input = &task->input[1]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + alpha->s1_alpha = param->alpha; + alpha->alpha_mode = proc_data->alpha_mode; + break; + } + + param = &pxp->pxp_conf_state.out_param; + ret = convert_param_to_pixmap(output, param); + BUG_ON(ret < 0); + + output->crop.x = proc_data->drect.left; + output->crop.y = proc_data->drect.top; + output->crop.width = proc_data->drect.width; + output->crop.height = proc_data->drect.height; + } + + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d S0 crop (top, left)=(%d, %d), (width, height)=(%d, %d)\n", + __func__, __LINE__, + pxp->pxp_conf_state.s0_param.crop.top, + pxp->pxp_conf_state.s0_param.crop.left, + pxp->pxp_conf_state.s0_param.crop.width, + pxp->pxp_conf_state.s0_param.crop.height); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static int pxpdma_dostart_work(struct pxps *pxp) +{ + int ret; + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + dma_async_tx_callback callback; + void *callback_param; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *child, *_child; + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + ret = pxp_config(pxp, pxp_chan); + if (ret) { + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + callback(callback_param); + + /* Unsupport operation */ + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + spin_unlock_irqrestore(&pxp->lock, flags); + return -EINVAL; + } + + if (proc_data->working_mode & PXP_MODE_STANDARD) { + if(!pxp_is_v3p(pxp) || !(proc_data->engine_enable & PXP_ENABLE_DITHER)) + pxp_start2(pxp); + } else + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return 0; +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + int pxp_irq_status = 0; + + dump_pxp_reg(pxp); + + if (__raw_readl(pxp->base + HW_PXP_STAT) & BM_PXP_STAT_IRQ0) + __raw_writel(BM_PXP_STAT_IRQ0, pxp->base + HW_PXP_STAT_CLR); + else { + int irq_clr = 0; + + pxp_irq_status = __raw_readl(pxp->base + HW_PXP_IRQ); + BUG_ON(!pxp_irq_status); + + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_STORE_IRQ; + /*XXX other irqs status clear should be added below */ + + __raw_writel(irq_clr, pxp->base + HW_PXP_IRQ_CLR); + + pxp_writel(BM_PXP_CTRL_ENABLE, HW_PXP_CTRL_CLR); + } + pxp_collision_status_report(pxp, &col_info); + pxp_histogram_status_report(pxp, &hist_status); + /*XXX before a new update operation, we should + * always clear all the collision information + */ + pxp_collision_detection_disable(pxp); + pxp_histogram_disable(pxp); + + pxp_writel(0x0, HW_PXP_CTRL); + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static void pxp_data_path_config_v3p(struct pxps *pxp) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0), + pxp->base + HW_PXP_DATA_PATH_CTRL0); + + /* + * MUX17: HIST_B as histogram: 0: output buffer, 1: wfe_store + * MUX16: HIST_A as collision: 0: output buffer, 1: wfe_store + */ + if (pxp_is_v3(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1); + __raw_writel(val, pxp->base + HW_PXP_DATA_PATH_CTRL1); +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_sram_init(struct pxps *pxp, u32 select, + u32 buffer_addr, u32 length) +{ + u32 i; + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(1), + pxp->base + HW_PXP_INIT_MEM_CTRL); + + if ((select == WFE_A) || (select == WFE_B)) { + for (i = 0; i < length / 2; i++) { + __raw_writel(*(((u32*)buffer_addr) + 2 * i + 1), + pxp->base + HW_PXP_INIT_MEM_DATA_HIGH); + + __raw_writel(*(((u32*)buffer_addr) + 2 * i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } else { + for (i = 0; i < length; i++) { + __raw_writel(*(((u32*) buffer_addr) + i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(0), + pxp->base + HW_PXP_INIT_MEM_CTRL); +} + +/* + * wfe a configuration + * configure wfe a engine for waveform processing + * including its fetch and store module + */ +static void pxp_wfe_a_configure(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(8) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(10) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(15), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFA_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_A_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_H_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_L_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_A_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_A_PARAM_PARAM0(0) | + BF_PXP_ALU_A_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_A_PARAM); + + __raw_writel(BF_PXP_ALU_A_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_A_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_A_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_A_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_A_CTRL_BYPASS (1) | + BF_PXP_ALU_A_CTRL_ENABLE (1) | + BF_PXP_ALU_A_CTRL_START (0) | + BF_PXP_ALU_A_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_A_CTRL); + + /* WFE A */ + __raw_writel(0x3F3F0303, pxp->base + HW_PXP_WFE_A_STAGE1_MUX0); + __raw_writel(0x0C00000C, pxp->base + HW_PXP_WFE_A_STAGE1_MUX1); + __raw_writel(0x01040000, pxp->base + HW_PXP_WFE_A_STAGE1_MUX2); + __raw_writel(0x0A0A0904, pxp->base + HW_PXP_WFE_A_STAGE1_MUX3); + __raw_writel(0x00000B0B, pxp->base + HW_PXP_WFE_A_STAGE1_MUX4); + + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX0); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX1); + __raw_writel(0x280E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX2); + __raw_writel(0x00011800, pxp->base + HW_PXP_WFE_A_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX4); + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX5); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX6); + __raw_writel(0x1A0E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX7); + __raw_writel(0x1B012911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX8); + __raw_writel(0x00002911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX12); + + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_A_STAGE3_MUX0); + __raw_writel(0x3F3F3F08, pxp->base + HW_PXP_WFE_A_STAGE3_MUX1); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_A_STAGE3_MUX2); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_A_STAGE3_MUX3); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f030100, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_ADDR_0); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT3); + __raw_writel(0x071F1F1F, pxp->base + HW_PXP_WFE_A_STG2_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_7); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_3); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_4); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_5); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_6); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +static void pxp_wfe_a_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFB_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_L_CH0); + + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0x0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE A */ + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000003, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x04000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x0A090401, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x000B0B0A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x290C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00021901, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x1B0C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x1C022A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x02002A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x3b202c1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x003b202d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f232120, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_3); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_4); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_5); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_6); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_7); + + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_7); + + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +/* + * wfe a processing + * use wfe a to process an update + * x,y,width,height: + * coordinate and size of the update region + * wb: + * working buffer, 16bpp + * upd: + * update buffer, in Y4 with or without alpha, 8bpp + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * y4c: + * y4c buffer, {Y4[3:0],3'b000,collision}, 8bpp + * lut: + * valid value 0-63 + * set to the lut used for next update + * partial: + * 0 - full update + * 1 - partial update + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + */ +static void pxp_wfe_a_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFA_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFA_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFA_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFA_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_A_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_A_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_A_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_A_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_A_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_A_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_A_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_A_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_A_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_A_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_A_CTRL_ENABLE(1) | + BF_PXP_WFE_A_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_A_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); +} + +static void pxp_wfe_a_process_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); +} + +/* + * wfe b configuration + * + * configure wfe b engnine for reagl/-d waveform processing + */ +static void pxp_wfe_b_configure(struct pxps *pxp) +{ + /* Fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(2) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG8_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG9_MASK); + + pxp_sram_init(pxp, WFE_B, (u32)active_matrix_data_8x8, 64); + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xff), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(2)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(6)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel( + BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE */ + __raw_writel(0x00000402, pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + __raw_writel(0x02040608, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x050A040A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x070A060A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x0000000A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1C1E2022, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x1215181A, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x00000C0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0x01000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0x000C010B, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x00001211, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x00008000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x0000FFFE, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x00000F0F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x00007F7F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00FF00FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x000000FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0xFF3FFF3F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0xFFFFFF1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); +} + +/* wfe b processing + * use wfe b to process an update + * call this function only after pxp_wfe_a_processing + * x,y,width,height: + * coordinate and size of the update region + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * wb: + * working buffer, 16bpp + * lut: + * lut buffer, 8bpp + * lut_update: + * 0 - wfe_b is used for reagl/reagl-d operation + * 1 - wfe_b is used for lut update operation + * reagl_d_en: + * 0 - use reagl waveform algorithm + * 1 - use reagl/-d waveform algorithm + */ +static void pxp_wfe_b_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_b_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_b_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_b_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_b_store_param[1]; + static int comp_mask; + /* Fetch */ + + print_param(fetch_ch0, "wfe_b fetch_ch0"); + print_param(fetch_ch1, "wfe_b fetch_ch1"); + print_param(store_ch0, "wfe_b store_ch0"); + print_param(store_ch1, "wfe_b store_ch1"); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, + pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height-1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(fetch_ch1->stride * 2, + pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height-1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + if (!proc_data->lut_update) { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } + +#ifdef CONFIG_REAGLD_ALGO_CHECK + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((fetch_ch0->comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); +#else + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + /* comp_mask only need to be updated upon REAGL-D, 0,1,...7, 0,1,... */ + if (proc_data->reagl_d_en) { + comp_mask++; + if (comp_mask>7) + comp_mask = 0; + } +#endif + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride * 2)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr + + (store_ch0->left + store_ch0->top * store_ch0->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + if (proc_data->lut_update) { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x3f0000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x30)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(4)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } else { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(3)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } + + /* ALU */ + __raw_writel( + BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel( + BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + __raw_writel( /*TODO check*/ + BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch0->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch0->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel(proc_data->reagl_d_en, pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); +} + +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch) +{ + u32 active_bpp; + u32 pitch; + + if (bpp == 8) { + active_bpp = 0; + pitch = output_pitch; + } else if(bpp == 16) { + active_bpp = 1; + pitch = output_pitch * 2; + } else { + active_bpp = 2; + pitch = output_pitch * 4; + } + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(pitch)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(pitch), + pxp_reg_base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(value), + pxp_reg_base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(40)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (1) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (1) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp_reg_base + HW_PXP_CTRL2); + + if (busy_wait(BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ & + __raw_readl(pxp_reg_base + HW_PXP_IRQ)) == false) + printk("%s: wait for completion timeout\n", __func__); +} +EXPORT_SYMBOL(pxp_fill); + +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + } + } +} + +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + } + } +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +void m4_process(void) +{ + __raw_writel(0x7, pinctrl_base + PIN_DOUT); /* M4 Start */ + + while (!(__raw_readl(pxp_reg_base + HW_PXP_HANDSHAKE_CPU_STORE) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY)); + + __raw_writel(0x3, pinctrl_base + PIN_DOUT); /* M4 Stop */ + + +} +#else +void m4_process(void) {} +#endif +EXPORT_SYMBOL(m4_process); + +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_set) + pxp->devdata->pxp_lut_status_set(pxp, i); + } +} + +static void pxp_lut_status_clr(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_clr_v3p(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +/* this function should be called in the epdc + * driver explicitly when some epdc lut becomes + * idle. So it should be exported. + */ +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_clr) + pxp->devdata->pxp_lut_status_clr(i); + } +} + +/* use histogram_B engine to calculate histogram status */ +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + __raw_writel( + BF_PXP_HIST_B_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_B_BUF_SIZE_WIDTH(width), + pxp->base + HW_PXP_HIST_B_BUF_SIZE); + + __raw_writel( + BF_PXP_HIST_B_MASK_MASK_EN(1)| + BF_PXP_HIST_B_MASK_MASK_MODE(0)| + BF_PXP_HIST_B_MASK_MASK_OFFSET(64)| + BF_PXP_HIST_B_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_B_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_B_MASK_MASK_VALUE1(0), + pxp->base + HW_PXP_HIST_B_MASK); + + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(8)| + BF_PXP_HIST_B_CTRL_CLEAR(0)| + BF_PXP_HIST_B_CTRL_ENABLE(1), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status) +{ + BUG_ON(!hist_status); + + *hist_status = (__raw_readl(pxp->base + HW_PXP_HIST_B_CTRL) & BM_PXP_HIST_B_CTRL_STATUS) + >> BP_PXP_HIST_B_CTRL_STATUS; + dev_dbg(pxp->dev, "%d pixels are used to calculate histogram status %d\n", + __raw_readl(pxp->base + HW_PXP_HIST_B_TOTAL_PIXEL), *hist_status); +} + +static void pxp_histogram_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(4)| + BF_PXP_HIST_B_CTRL_CLEAR(1)| + BF_PXP_HIST_B_CTRL_ENABLE(0), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +/* the collision detection function will be + * called by epdc driver when required + */ +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + __raw_writel( + BF_PXP_HIST_A_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_A_BUF_SIZE_WIDTH(width), + pxp_reg_base + HW_PXP_HIST_A_BUF_SIZE); + + __raw_writel( + BF_PXP_HIST_A_MASK_MASK_EN(1)| + BF_PXP_HIST_A_MASK_MASK_MODE(0)| + BF_PXP_HIST_A_MASK_MASK_OFFSET(65)| + BF_PXP_HIST_A_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_A_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_A_MASK_MASK_VALUE1(0), + pxp_reg_base + HW_PXP_HIST_A_MASK); + + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(0)| + BF_PXP_HIST_A_CTRL_ENABLE(1), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +static void pxp_collision_detection_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(1)| + BF_PXP_HIST_A_CTRL_ENABLE(0), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +/* this function can be called in the epdc callback + * function in the pxp_irq() to let the epdc know + * the collision information for the previous working + * buffer update. + */ +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info) +{ + unsigned int count; + + BUG_ON(!info); + memset(info, 0x0, sizeof(*info)); + + info->pixel_cnt = count = __raw_readl(pxp->base + HW_PXP_HIST_A_TOTAL_PIXEL); + if (!count) + return false; + + dev_dbg(pxp->dev, "%s: pixel_cnt = %d\n", __func__, info->pixel_cnt); + info->rect_min_x = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_x = %d\n", __func__, info->rect_min_x); + info->rect_max_x = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_x = %d\n", __func__, info->rect_max_x); + info->rect_min_y = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_y = %d\n", __func__, info->rect_min_y); + info->rect_max_y = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_y = %d\n", __func__, info->rect_max_y); + + info->victim_luts[0] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT0); + dev_dbg(pxp->dev, "%s: victim_luts[0] = 0x%x\n", __func__, info->victim_luts[0]); + info->victim_luts[1] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT1); + dev_dbg(pxp->dev, "%s: victim_luts[1] = 0x%x\n", __func__, info->victim_luts[1]); + + return true; +} + +void pxp_get_collision_info(struct pxp_collision_info *info) +{ + BUG_ON(!info); + + memcpy(info, &col_info, sizeof(struct pxp_collision_info)); +} +EXPORT_SYMBOL(pxp_get_collision_info); + +static void dither_prefetch_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->dither_fetch_param[1]; + + print_param(fetch_ch0, "dither fetch_ch0"); + print_param(fetch_ch1, "dither fetch_ch1"); + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(2) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(fetch_ch0->stride) | + BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(fetch_ch1->stride), + pxp->base + HW_PXP_DITHER_FETCH_PITCH); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(fetch_ch0->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(fetch_ch1->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH1); +} + +static void dither_store_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->dither_store_param[1]; + + print_param(store_ch0, "dither store_ch0"); + print_param(store_ch1, "dither store_ch1"); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride), + pxp->base + HW_PXP_DITHER_STORE_PITCH); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(store_ch1->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_DITHER_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0xffffff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_DITHER_STORE_D_SHIFT_L_CH0); +} + +static void pxp_set_final_lut_data(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if(proc_data->quant_bit < 2) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit1_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xf0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else if(proc_data->quant_bit < 4) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit2_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x50), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xa0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit4_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x10) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x20) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x30), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x40) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x60) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x70), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0x80) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0x90) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xb0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xc0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xd0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xe0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } +} + +static void pxp_dithering_process(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 val = 0; + + if (pxp->devdata && pxp->devdata->pxp_dithering_configure) + pxp->devdata->pxp_dithering_configure(pxp); + + if (pxp_is_v3(pxp)) + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (0) | + BF_PXP_DITHER_CTRL_ENABLE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE1 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + else if (pxp_is_v3p(pxp)) { + if (proc_data->dither_mode != 0 && + proc_data->dither_mode != 3) { + dev_err(pxp->dev, "Not supported dithering mode. " + "Forced to be Orderred mode!\n"); + proc_data->dither_mode = 3; + } + + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (1) | + BF_PXP_DITHER_CTRL_ENABLE2 (1) | + BF_PXP_DITHER_CTRL_DITHER_MODE2(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE1(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (1) | + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + } + __raw_writel(val, pxp->base + HW_PXP_DITHER_CTRL); + + switch(proc_data->dither_mode) { + case PXP_DITHER_PASS_THROUGH: + /* no more settings required */ + break; + case PXP_DITHER_FLOYD: + case PXP_DITHER_ATKINSON: + case PXP_DITHER_ORDERED: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(1) | + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + pxp_set_final_lut_data(pxp); + + break; + case PXP_DITHER_QUANT_ONLY: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + break; + default: + /* unknown mode */ + dev_err(pxp->dev, "unknown dithering mode passed!\n"); + __raw_writel(0x0, pxp->base + HW_PXP_DITHER_CTRL); + return; + } +} + +static void pxp_dithering_configure(struct pxps *pxp) +{ + dither_prefetch_config(pxp); + dither_store_config(pxp); +} + +static void pxp_dithering_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + + __raw_writel(BF_PXP_CTRL_BLOCK_SIZE(BV_PXP_CTRL_BLOCK_SIZE__8X8) | + BF_PXP_CTRL_ROTATE0(BV_PXP_CTRL_ROTATE0__ROT_0) | + BM_PXP_CTRL_IRQ_ENABLE, + pxp->base + HW_PXP_CTRL); + + __raw_writel(BF_PXP_PS_CTRL_DECX(BV_PXP_PS_CTRL_DECX__DISABLE) | + BF_PXP_PS_CTRL_DECY(BV_PXP_PS_CTRL_DECY__DISABLE) | + BF_PXP_PS_CTRL_FORMAT(BV_PXP_PS_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_PS_CTRL); + + __raw_writel(BF_PXP_OUT_CTRL_FORMAT(BV_PXP_OUT_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_OUT_CTRL); + + __raw_writel(BF_PXP_PS_SCALE_YSCALE(4096) | + BF_PXP_PS_SCALE_XSCALE(4096), + pxp->base + HW_PXP_PS_SCALE); + + __raw_writel(store_ch0->paddr, pxp->base + HW_PXP_OUT_BUF); + + __raw_writel(store_ch0->stride, pxp->base + HW_PXP_OUT_PITCH); + + __raw_writel(BF_PXP_OUT_LRC_X(store_ch0->width - 1) | + BF_PXP_OUT_LRC_Y(store_ch0->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + __raw_writel(BF_PXP_OUT_AS_ULC_X(1) | + BF_PXP_OUT_AS_ULC_Y(1), + pxp->base + HW_PXP_OUT_AS_ULC); + + __raw_writel(BF_PXP_OUT_AS_LRC_X(0) | + BF_PXP_OUT_AS_LRC_Y(0), + pxp->base + HW_PXP_OUT_AS_LRC); + + __raw_writel(BF_PXP_OUT_PS_ULC_X(0) | + BF_PXP_OUT_PS_ULC_Y(0), + pxp->base + HW_PXP_OUT_PS_ULC); + + __raw_writel(BF_PXP_OUT_PS_LRC_X(fetch_ch0->width - 1) | + BF_PXP_OUT_PS_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_OUT_PS_LRC); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_PS_BUF); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_PS_PITCH); + + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + __raw_writel(BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel(BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1), + pxp->base + HW_PXP_DATA_PATH_CTRL0_CLR); +} + +static void pxp_start2(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + int dither_wfe_a_handshake = 0; + int wfe_a_b_handshake = 0; + int count = 0; + + int wfe_a_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_A) == PXP_ENABLE_WFE_A); + int wfe_b_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_B) == PXP_ENABLE_WFE_B); + int dither_enable = ((proc_data->engine_enable & PXP_ENABLE_DITHER) == PXP_ENABLE_DITHER); + int handshake = ((proc_data->engine_enable & PXP_ENABLE_HANDSHAKE) == PXP_ENABLE_HANDSHAKE); + int dither_bypass = ((proc_data->engine_enable & PXP_ENABLE_DITHER_BYPASS) == PXP_ENABLE_DITHER_BYPASS); + u32 val = 0; + + if (dither_enable) + count++; + if (wfe_a_enable) + count++; + if (wfe_b_enable) + count++; + + if (count == 0) + return; + if (handshake && (count == 1)) { + dev_warn(pxp->dev, "Warning: Can not use handshake mode when " + "only one sub-block is enabled!\n"); + handshake = 0; + } + + if (handshake && wfe_b_enable && (wfe_a_enable == 0)) { + dev_err(pxp->dev, "WFE_B only works when WFE_A is enabled!\n"); + return; + } + + if (handshake && dither_enable && wfe_a_enable) + dither_wfe_a_handshake = 1; + if (handshake && wfe_a_enable && wfe_b_enable) + wfe_a_b_handshake = 1; + + dev_dbg(pxp->dev, "handshake %d, dither_wfe_a_handshake %d, " + "wfe_a_b_handshake %d, dither_bypass %d\n", + handshake, + dither_wfe_a_handshake, + wfe_a_b_handshake, + dither_bypass); + + if (handshake) { + /* for handshake, we only enable the last completion INT */ + if (wfe_b_enable) + __raw_writel(0x8000, pxp->base + HW_PXP_IRQ_MASK); + else if (wfe_a_enable) + __raw_writel(0x4000, pxp->base + HW_PXP_IRQ_MASK); + + /* Dither fetch */ + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + if (dither_bypass) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(2) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + } else if (dither_wfe_a_handshake) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + } + + if (wfe_a_b_handshake) { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + /* WFE_B fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + /* trigger operation */ + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(1) | + BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(1) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0) | + BF_PXP_CTRL_BLOCK_SIZE(1) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(1) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + return; + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(0) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_BLOCK_SIZE(0) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(0) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (0) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_B(0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (0) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp->base + HW_PXP_CTRL2); + + dump_pxp_reg2(pxp); +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static struct platform_device_id imx_pxpdma_devtype[] = { + { + .name = "imx7d-pxp-dma", + .driver_data = PXP_V3, + }, { + .name = "imx6ull-pxp-dma", + .driver_data = PXP_V3P, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, imx_pxpdma_devtype); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx7d-pxp-dma", .data = &imx_pxpdma_devtype[0], }, + { .compatible = "fsl,imx6ull-pxp-dma", .data = &imx_pxpdma_devtype[1], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + ret = pxpdma_dostart_work(pxp); + if (ret) { + pxp->pxp_ongoing = 0; + continue; + } + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, 0, 0); + } + + return 0; +} + +static int pxp_init_interrupt(struct platform_device *pdev) +{ + int legacy_irq, std_irq, err; + struct pxps *pxp = platform_get_drvdata(pdev); + + legacy_irq = platform_get_irq(pdev, 0); + if (legacy_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp legacy irq: %d\n", + legacy_irq); + return legacy_irq; + } + + std_irq = platform_get_irq(pdev, 1); + if (std_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp standard irq: %d\n", + std_irq); + return std_irq; + } + + err = devm_request_irq(&pdev->dev, legacy_irq, pxp_irq, 0, + "pxp-dmaengine-legacy", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp legacy irq failed: %d\n", err); + return err; + } + + err = devm_request_irq(&pdev->dev, std_irq, pxp_irq, 0, + "pxp-dmaengine-std", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp standard irq failed: %d\n", err); + return err; + } + + pxp->irq = legacy_irq; + + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + return 0; +} + +static int pxp_create_attrs(struct platform_device *pdev) +{ + int ret = 0; + + if ((ret = device_create_file(&pdev->dev, &dev_attr_clk_off_timeout))) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + return ret; + } + + if ((ret = device_create_file(&pdev->dev, &dev_attr_block_size))) { + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + + dev_err(&pdev->dev, + "Unable to create file from block_size\n"); + return ret; + } + + return 0; +} + +static void pxp_remove_attrs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); +} + +static void pxp_init_timer(struct pxps *pxp) +{ + INIT_WORK(&pxp->work, clkoff_callback); + + init_timer(&pxp->clk_timer); + pxp->clk_timer.function = pxp_clkoff_timer; + pxp->clk_timer.data = (unsigned long)pxp; +} + +static bool is_mux_node(uint32_t node_id) +{ + if ((node_id < PXP_2D_MUX_MUX0) || + (node_id > PXP_2D_MUX_MUX15)) + return false; + + return true; +} + +static bool search_mux_chain(uint32_t mux_id, + struct edge_node *enode) +{ + bool found = false; + uint32_t i, j, next_mux = 0; + uint32_t output; + struct mux *muxes; + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 2; i++) { + output = muxes[mux_id].mux_outputs[i]; + if (output == 0xff) + break; + + if ((output == enode->adjvex)) { + /* found */ + found = true; + break; + } else if (is_mux_node(output)) { + next_mux = output - PXP_2D_MUX_BASE; + found = search_mux_chain(next_mux, enode); + + if (found) { + for (j = 0; j < 4; j++) { + if (muxes[next_mux].mux_inputs[j] == + (mux_id + PXP_2D_MUX_BASE)) + break; + } + + set_bit(next_mux, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, next_mux, j); + break; + } + } + } + + return found; +} + +static void enode_mux_config(unsigned int vnode_id, + struct edge_node *enode) +{ + uint32_t i, j; + bool via_mux = false, need_search = false; + struct mux *muxes; + + BUG_ON(vnode_id >= PXP_2D_NUM); + BUG_ON(enode->adjvex >= PXP_2D_NUM); + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 16; i++) { + for (j = 0; j < 4; j++) { + if (muxes[i].mux_inputs[j] == 0xff) + break; + + if (muxes[i].mux_inputs[j] == vnode_id) + need_search = true; + else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA0_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA0_S0) || + (vnode_id == PXP_2D_ALPHA0_S1)) + need_search = true; + } else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA1_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA1_S0) || + (vnode_id == PXP_2D_ALPHA1_S1)) + need_search = true; + } + + if (need_search) { + via_mux = search_mux_chain(i, enode); + need_search = false; + break; + } + } + + if (via_mux) { + set_bit(i, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, i, j); + break; + } + } +} + +static int pxp_create_initial_graph(struct platform_device *pdev) +{ + int i, j, first; + static bool (*adj_array)[PXP_2D_NUM]; + struct edge_node *enode, *curr = NULL; + + adj_array = (v3p_flag) ? adj_array_v3p : adj_array_v3; + + for (i = 0; i < PXP_2D_NUM; i++) { + switch (i) { + case PXP_2D_PS: + case PXP_2D_AS: + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + adj_list[i].type = PXP_2D_TYPE_INPUT; + break; + case PXP_2D_OUT: + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + adj_list[i].type = PXP_2D_TYPE_OUTPUT; + break; + default: + adj_list[i].type = PXP_2D_TYPE_ALU; + break; + } + + first = -1; + + for (j = 0; j < PXP_2D_NUM; j++) { + if (adj_array[i][j]) { + enode = kmem_cache_alloc(edge_node_cache, + GFP_KERNEL | __GFP_ZERO); + if (!enode) { + dev_err(&pdev->dev, "allocate edge node failed\n"); + return -ENOMEM; + } + enode->adjvex = j; + enode->prev_vnode = i; + + if (unlikely(first == -1)) { + first = j; + adj_list[i].first = enode; + } else + curr->next = enode; + + curr = enode; + enode_mux_config(i, enode); + dev_dbg(&pdev->dev, "(%d -> %d): mux_used 0x%x, mux_config 0x%x\n\n", + i, j, enode->mux_used, *(unsigned int*)&enode->muxes); + } + } + } + + return 0; +} + +/* Calculate the shortest paths start via + * 'from' node to other nodes + */ +static void pxp_find_shortest_path(unsigned int from) +{ + int i; + struct edge_node *enode; + struct path_node *pnode, *adjnode; + struct list_head queue; + + INIT_LIST_HEAD(&queue); + list_add_tail(&path_table[from][from].node, &queue); + + while(!list_empty(&queue)) { + pnode = list_entry(queue.next, struct path_node, node); + enode = adj_list[pnode->id].first; + while (enode) { + adjnode = &path_table[from][enode->adjvex]; + + if (adjnode->distance == DISTANCE_INFINITY) { + adjnode->distance = pnode->distance + 1; + adjnode->prev_node = pnode->id; + list_add_tail(&adjnode->node, &queue); + } + + enode = enode->next; + } + list_del_init(&pnode->node); + } + + for (i = 0; i < PXP_2D_NUM; i++) + pr_debug("From %u: to %d (id = %d, distance = 0x%x, prev_node = %d\n", + from, i, path_table[from][i].id, path_table[from][i].distance, + path_table[from][i].prev_node); +} + +static int pxp_gen_shortest_paths(struct platform_device *pdev) +{ + int i, j; + + for (i = 0; i < PXP_2D_NUM; i++) { + for (j = 0; j < PXP_2D_NUM; j++) { + path_table[i][j].id = j; + path_table[i][j].distance = DISTANCE_INFINITY; + path_table[i][j].prev_node = NO_PATH_NODE; + INIT_LIST_HEAD(&path_table[i][j].node); + } + + path_table[i][i].distance = 0; + + pxp_find_shortest_path(i); + } + + return 0; +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +static void pxp_config_m4(struct platform_device *pdev) +{ + fpga_tcml_base = ioremap(FPGA_TCML_ADDR, SZ_32K); + if (fpga_tcml_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + pinctrl_base = ioremap(PINCTRL, SZ_4K); + if (pinctrl_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + + __raw_writel(0xC0000000, pinctrl_base + 0x08); + __raw_writel(0x3, pinctrl_base + PIN_DOUT); + int i; + for (i = 0; i < 1024 * 32 / 4; i++) { + *(((unsigned int *)(fpga_tcml_base)) + i) = cm4_image[i]; + } +} +#endif + +static int pxp_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(imx_pxpdma_dt_ids, &pdev->dev); + struct pxps *pxp; + struct resource *res; + int err = 0; + + if (of_id) + pdev->id_entry = of_id->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + pxp_reg_base = pxp->base; + + pxp->pdev = pdev; + pxp->devdata = &pxp_devdata[pdev->id_entry->driver_data]; + + v3p_flag = (pxp_is_v3p(pxp)) ? true : false; + + pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); + pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); + + if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { + dev_err(&pdev->dev, "pxp clocks invalid\n"); + err = -EINVAL; + goto exit; + } + + pxp_soft_reset(pxp); + pxp_writel(0x0, HW_PXP_CTRL); + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + pxp_clk_enable(pxp); + pxp_soft_reset(pxp); + + /* Initialize PXP Interrupt */ + err = pxp_init_interrupt(pdev); + if (err < 0) + goto exit; + + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + pxp_init_timer(pxp); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + edge_node_cache = kmem_cache_create("edge_node", sizeof(struct edge_node), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!edge_node_cache) { + err = -ENOMEM; + kmem_cache_destroy(tx_desc_cache); + goto exit; + } + + err = pxp_create_attrs(pdev); + if (err) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + if ((err = pxp_create_initial_graph(pdev))) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + pxp_gen_shortest_paths(pdev); + +#ifdef CONFIG_MXC_FPGA_M4_TEST + pxp_config_m4(pdev); +#endif + register_pxp_device(); + pm_runtime_enable(pxp->dev); + + dma_alloc_coherent(NULL, PAGE_ALIGN(1920 * 1088 * 4), + &paddr, GFP_KERNEL); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp_remove_attrs(pdev); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp-v3", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} +late_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} +module_exit(pxp_exit); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/reg_bitfields.h b/drivers/dma/pxp/reg_bitfields.h new file mode 100644 index 00000000000000..95b5c83b4b1515 --- /dev/null +++ b/drivers/dma/pxp/reg_bitfields.h @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _REG_BITFIELDS_H +#define _REG_BITFIELDS_H +struct mux_config { + uint32_t mux0_sel : 2; + uint32_t mux1_sel : 2; + uint32_t mux2_sel : 2; + uint32_t mux3_sel : 2; + uint32_t mux4_sel : 2; + uint32_t mux5_sel : 2; + uint32_t mux6_sel : 2; + uint32_t mux7_sel : 2; + uint32_t mux8_sel : 2; + uint32_t mux9_sel : 2; + uint32_t mux10_sel : 2; + uint32_t mux11_sel : 2; + uint32_t mux12_sel : 2; + uint32_t mux13_sel : 2; + uint32_t mux14_sel : 2; + uint32_t mux15_sel : 2; +}; + +/* legacy engine registers */ +struct ps_ctrl { + uint32_t format : 6; + uint32_t wb_swap : 1; + uint32_t rsvd0 : 1; + uint32_t decy : 2; + uint32_t decx : 2; + uint32_t rsvd1 : 20; +}; + +struct ps_scale { + uint32_t xscale : 15; + uint32_t rsvd1 : 1; + uint32_t yscale : 15; + uint32_t rsvd2 : 1; +}; + +struct ps_offset { + uint32_t xoffset : 12; + uint32_t rsvd1 : 4; + uint32_t yoffset : 12; + uint32_t rsvd2 : 4; +}; + +struct as_ctrl { + uint32_t rsvd0 : 1; + uint32_t alpha_ctrl : 2; + uint32_t enable_colorkey : 1; + uint32_t format : 4; + uint32_t alpha : 8; + uint32_t rop : 4; + uint32_t alpha0_invert : 1; + uint32_t alpha1_invert : 1; + uint32_t rsvd1 : 10; +}; + +struct out_ctrl { + uint32_t format : 5; + uint32_t rsvd0 : 3; + uint32_t interlaced_output : 2; + uint32_t rsvd1 : 13; + uint32_t alpha_output : 1; + uint32_t alpha : 8; +}; + +struct coordinate { + uint32_t y : 14; + uint32_t rsvd0 : 2; + uint32_t x : 14; + uint32_t rsvd1 : 2; +}; + +struct pxp_alpha_ctrl { + uint32_t poter_duff_enable : 1; + uint32_t s0_s1_factor_mode : 2; + uint32_t s0_global_alpha_mode : 2; + uint32_t s0_alpha_mode : 1; + uint32_t s0_color_mode : 1; + uint32_t rsvd1 : 1; + uint32_t s1_s0_factor_mode : 2; + uint32_t s1_global_alpha_mode : 2; + uint32_t s1_alpha_mode : 1; + uint32_t s1_color_mode : 1; + uint32_t rsvd0 : 2; + uint32_t s0_global_alpha : 8; + uint32_t s1_global_alpha : 8; +}; + +/* store engine registers */ +struct store_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t array_en : 1; + uint32_t array_line_num : 2; + uint32_t rsvd3 : 1; + uint32_t store_bypass_en : 1; + uint32_t store_memory_en : 1; + uint32_t pack_in_sel : 1; + uint32_t fill_data_en : 1; + uint32_t rsvd2 : 4; + uint32_t wr_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t combine_2channel : 1; + uint32_t rsvd0 : 6; + uint32_t arbit_en : 1; +}; + +struct store_size { + uint32_t out_width : 16; + uint32_t out_height : 16; +}; + +struct store_pitch { + uint32_t ch0_out_pitch : 16; + uint32_t ch1_out_pitch : 16; +}; + +struct store_shift_ctrl { + uint32_t rsvd2 : 2; + uint32_t output_active_bpp : 2; + uint32_t out_yuv422_1p_en : 1; + uint32_t out_yuv422_2p_en : 1; + uint32_t rsvd1 : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 24; +}; + +struct store_d_shift { + uint64_t d_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t d_shift_flag0 : 1; + uint64_t d_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t d_shift_flag1 : 1; + uint64_t d_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t d_shift_flag2 : 1; + uint64_t d_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t d_shift_flag3 : 1; + + uint64_t d_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t d_shift_flag4 : 1; + uint64_t d_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t d_shift_flag5 : 1; + uint64_t d_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t d_shift_flag6 : 1; + uint64_t d_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t d_shift_flag7 : 1; +}; + +struct store_f_shift { + uint64_t f_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t f_shift_flag0 : 1; + uint64_t f_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t f_shift_flag1 : 1; + uint64_t f_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t f_shift_flag2 : 1; + uint64_t f_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t f_shift_flag3 : 1; + + uint64_t f_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t f_shift_flag4 : 1; + uint64_t f_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t f_shift_flag5 : 1; + uint64_t f_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t f_shift_flag6 : 1; + uint64_t f_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t f_shift_flag7 : 1; +}; + +struct store_d_mask { + uint64_t d_mask_l : 32; + uint64_t d_mask_h : 32; +}; + +/* fetch engine registers */ +struct fetch_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t bypass_pixel_en : 1; + uint32_t high_byte : 1; + uint32_t rsvd4 : 3; + uint32_t hflip : 1; + uint32_t vflip : 1; + uint32_t rsvd3 : 1; + uint32_t rotation_angle : 2; + uint32_t rsvd2 : 2; + uint32_t rd_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t handshake_scan_line_num : 2; + uint32_t rsvd0 : 5; + uint32_t arbit_en : 1; +}; + +struct fetch_active_size_ulc { + uint32_t active_size_ulc_x : 16; + uint32_t active_size_ulc_y : 16; +}; + +struct fetch_active_size_lrc { + uint32_t active_size_lrc_x : 16; + uint32_t active_size_lrc_y : 16; +}; + +struct fetch_size { + uint32_t input_total_width : 16; + uint32_t input_total_height : 16; +}; + +struct fetch_pitch { + uint32_t ch0_input_pitch : 16; + uint32_t ch1_input_pitch : 16; +}; + +struct fetch_shift_ctrl { + uint32_t input_active_bpp : 2; + uint32_t rsvd1 : 6; + uint32_t expand_format : 3; + uint32_t expand_en : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 19; +}; + +struct fetch_shift_offset { + uint32_t offset0 : 5; + uint32_t rsvd3 : 3; + uint32_t offset1 : 5; + uint32_t rsvd2 : 3; + uint32_t offset2 : 5; + uint32_t rsvd1 : 3; + uint32_t offset3 : 5; + uint32_t rsvd0 : 3; +}; + +struct fetch_shift_width { + uint32_t width0 : 4; + uint32_t width1 : 4; + uint32_t width2 : 4; + uint32_t width3 : 4; + uint32_t rsvd0 : 16; +}; +#endif diff --git a/drivers/dma/pxp/regs-pxp_v2.h b/drivers/dma/pxp/regs-pxp_v2.h new file mode 100644 index 00000000000000..8b20ddef395400 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v2.h @@ -0,0 +1,1152 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.29 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_RSVD3 26 +#define BM_PXP_CTRL_RSVD3 0x0C000000 +#define BF_PXP_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_CTRL_RSVD3) +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ROT_POS 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BP_PXP_CTRL_RSVD1 12 +#define BM_PXP_CTRL_RSVD1 0x001FF000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 5 +#define BM_PXP_CTRL_RSVD0 0x000000E0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010 +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 9 +#define BM_PXP_STAT_RSVD2 0x0000FE00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 9) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND (0x00000100) + +#define BP_PXP_PS_BACKGROUND_RSVD 24 +#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD) +#define BP_PXP_PS_BACKGROUND_COLOR 0 +#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 21 +#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000 +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_HIST_CTRL (0x00000290) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000002a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000002b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000002c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000002d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000002e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000002f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000300) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000310) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_POWER (0x00000320) + +#define BP_PXP_POWER_CTRL 12 +#define BM_PXP_POWER_CTRL 0xFFFFF000 +#define BF_PXP_POWER_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_CTRL) +#define BP_PXP_POWER_ROT_MEM_LP_STATE 9 +#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE) +#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/dma/pxp/regs-pxp_v3.h b/drivers/dma/pxp/regs-pxp_v3.h new file mode 100644 index 00000000000000..15a481151a13a1 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v3.h @@ -0,0 +1,26950 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.77 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BF_PXP_CTRL_SFTRST(v) \ + (((v) << 31) & BM_PXP_CTRL_SFTRST) +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BF_PXP_CTRL_CLKGATE(v) \ + (((v) << 30) & BM_PXP_CTRL_CLKGATE) +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BF_PXP_CTRL_RSVD4(v) \ + (((v) << 29) & BM_PXP_CTRL_RSVD4) +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BF_PXP_CTRL_EN_REPEAT(v) \ + (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) +#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) +#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) +#define BM_PXP_CTRL_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) +#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_RSVD1 0x00400000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) +#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) +#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) +#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) +#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 +#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ + (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) +#define BM_PXP_CTRL_VFLIP1 0x00008000 +#define BF_PXP_CTRL_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL_VFLIP1) +#define BM_PXP_CTRL_HFLIP1 0x00004000 +#define BF_PXP_CTRL_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL_HFLIP1) +#define BP_PXP_CTRL_ROTATE1 12 +#define BM_PXP_CTRL_ROTATE1 0x00003000 +#define BF_PXP_CTRL_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL_ROTATE1) +#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL_VFLIP0 0x00000800 +#define BF_PXP_CTRL_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL_VFLIP0) +#define BM_PXP_CTRL_HFLIP0 0x00000400 +#define BF_PXP_CTRL_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL_HFLIP0) +#define BP_PXP_CTRL_ROTATE0 8 +#define BM_PXP_CTRL_ROTATE0 0x00000300 +#define BF_PXP_CTRL_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE0) +#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 6 +#define BM_PXP_CTRL_RSVD0 0x000000C0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 6) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 +#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ + (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) +#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 +#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ + (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ + (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ + (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BF_PXP_CTRL_IRQ_ENABLE(v) \ + (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) +#define BM_PXP_CTRL_ENABLE 0x00000001 +#define BF_PXP_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL_ENABLE) + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_AXI_ERROR_ID_1 12 +#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 +#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ + (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) +#define BM_PXP_STAT_RSVD2 0x00000800 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 11) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 +#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ + (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) +#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 +#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ + (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ + (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) +#define BP_PXP_STAT_AXI_ERROR_ID_0 4 +#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BF_PXP_STAT_NEXT_IRQ(v) \ + (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) +#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 +#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ + (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) +#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 +#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ + (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) +#define BM_PXP_STAT_IRQ0 0x00000001 +#define BF_PXP_STAT_IRQ0(v) \ + (((v) << 0) & BM_PXP_STAT_IRQ0) + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ + (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BM_PXP_PS_CTRL_RSVD0 0x00000080 +#define BF_PXP_PS_CTRL_RSVD0(v) \ + (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) +#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 +#define BF_PXP_PS_CTRL_WB_SWAP(v) \ + (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000003F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F +#define BV_PXP_PS_CTRL_FORMAT__RGBA888 0x24 + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND_0 (0x00000100) + +#define BP_PXP_PS_BACKGROUND_0_RSVD 24 +#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) +#define BP_PXP_PS_BACKGROUND_0_COLOR 0 +#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BF_PXP_PS_SCALE_RSVD2(v) \ + (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BF_PXP_PS_SCALE_RSVD1(v) \ + (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 22 +#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 +#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) +#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 +#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ + (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGBA5551 0xA +#define BV_PXP_AS_CTRL_FORMAT__RGBA4444 0xB +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ + (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 +#define BF_PXP_AS_CTRL_RSVD0(v) \ + (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ + (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BF_PXP_CSC1_COEF0_BYPASS(v) \ + (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BF_PXP_CSC1_COEF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 +#define BF_PXP_CSC2_CTRL_BYPASS(v) \ + (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BF_PXP_LUT_CTRL_BYPASS(v) \ + (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BF_PXP_LUT_CTRL_SEL_8KB(v) \ + (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BF_PXP_LUT_CTRL_LRU_UPD(v) \ + (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BF_PXP_LUT_CTRL_INVALID(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 +#define BF_PXP_LUT_CTRL_DMA_START(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BF_PXP_LUT_ADDR_RSVD2(v) \ + (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_ALPHA_A_CTRL (0x00000290) + +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) +#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 +#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) +#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL (0x000002a0) + +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) +#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) + +#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 +#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) +#define BP_PXP_ALPHA_B_CTRL_1_ROP 4 +#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 +#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ + (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB +#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C +#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ + (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 +#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) +#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) + +#define HW_PXP_PS_BACKGROUND_1 (0x000002c0) + +#define BP_PXP_PS_BACKGROUND_1_RSVD 24 +#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) +#define BP_PXP_PS_BACKGROUND_1_COLOR 0 +#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) + +#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) + +#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) + +#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) + +#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) + +#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_CTRL2 (0x00000310) +#define HW_PXP_CTRL2_SET (0x00000314) +#define HW_PXP_CTRL2_CLR (0x00000318) +#define HW_PXP_CTRL2_TOG (0x0000031c) + +#define BP_PXP_CTRL2_RSVD3 28 +#define BM_PXP_CTRL2_RSVD3 0xF0000000 +#define BF_PXP_CTRL2_RSVD3(v) \ + (((v) << 28) & BM_PXP_CTRL2_RSVD3) +#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) +#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) +#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL2_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) +#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL2_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) +#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL2_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) +#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL2_RSVD2 0x00400000 +#define BF_PXP_CTRL2_RSVD2(v) \ + (((v) << 22) & BM_PXP_CTRL2_RSVD2) +#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) +#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) +#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) +#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL2_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) +#define BM_PXP_CTRL2_RSVD1 0x00010000 +#define BF_PXP_CTRL2_RSVD1(v) \ + (((v) << 16) & BM_PXP_CTRL2_RSVD1) +#define BM_PXP_CTRL2_VFLIP1 0x00008000 +#define BF_PXP_CTRL2_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL2_VFLIP1) +#define BM_PXP_CTRL2_HFLIP1 0x00004000 +#define BF_PXP_CTRL2_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL2_HFLIP1) +#define BP_PXP_CTRL2_ROTATE1 12 +#define BM_PXP_CTRL2_ROTATE1 0x00003000 +#define BF_PXP_CTRL2_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL2_ROTATE1) +#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL2_VFLIP0 0x00000800 +#define BF_PXP_CTRL2_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL2_VFLIP0) +#define BM_PXP_CTRL2_HFLIP0 0x00000400 +#define BF_PXP_CTRL2_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL2_HFLIP0) +#define BP_PXP_CTRL2_ROTATE0 8 +#define BM_PXP_CTRL2_ROTATE0 0x00000300 +#define BF_PXP_CTRL2_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL2_ROTATE0) +#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL2_RSVD0 1 +#define BM_PXP_CTRL2_RSVD0 0x000000FE +#define BF_PXP_CTRL2_RSVD0(v) \ + (((v) << 1) & BM_PXP_CTRL2_RSVD0) +#define BM_PXP_CTRL2_ENABLE 0x00000001 +#define BF_PXP_CTRL2_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL2_ENABLE) + +#define HW_PXP_POWER_REG0 (0x00000320) + +#define BP_PXP_POWER_REG0_CTRL 12 +#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 +#define BF_PXP_POWER_REG0_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_REG0_CTRL) +#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_POWER_REG1 (0x00000330) + +#define BP_PXP_POWER_REG1_RSVD0 24 +#define BM_PXP_POWER_REG1_RSVD0 0xFF000000 +#define BF_PXP_POWER_REG1_RSVD0(v) \ + (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) +#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 +#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 +#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ + (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 +#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 +#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ + (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 +#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 +#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ + (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 +#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 +#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ + (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 +#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 +#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ + (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 +#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 +#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ + (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 +#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 +#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ + (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 + +#define HW_PXP_DATA_PATH_CTRL0 (0x00000340) +#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) +#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) +#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) + +#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 +#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ + (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 +#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ + (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 +#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ + (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 +#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ + (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 +#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 +#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ + (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 +#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 +#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ + (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 +#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 +#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ + (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 +#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 +#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ + (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 +#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 +#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ + (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 +#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 +#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ + (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 +#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 +#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ + (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 +#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 +#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ + (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 +#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 +#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ + (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 +#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 +#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 +#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 +#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 + +#define HW_PXP_DATA_PATH_CTRL1 (0x00000350) +#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) +#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) +#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) + +#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 +#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 +#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) +#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 +#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 +#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 + +#define HW_PXP_INIT_MEM_CTRL (0x00000360) +#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) +#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) +#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) + +#define BM_PXP_INIT_MEM_CTRL_START 0x80000000 +#define BF_PXP_INIT_MEM_CTRL_START(v) \ + (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) +#define BP_PXP_INIT_MEM_CTRL_SELECT 27 +#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 +#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ + (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 +#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 +#define BP_PXP_INIT_MEM_CTRL_RSVD0 16 +#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 +#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ + (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) +#define BP_PXP_INIT_MEM_CTRL_ADDR 0 +#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF +#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) + +#define HW_PXP_INIT_MEM_DATA (0x00000370) + +#define BP_PXP_INIT_MEM_DATA_DATA 0 +#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_DATA(v) (v) + +#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) + +#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 +#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) + +#define HW_PXP_IRQ_MASK (0x00000390) +#define HW_PXP_IRQ_MASK_SET (0x00000394) +#define HW_PXP_IRQ_MASK_CLR (0x00000398) +#define HW_PXP_IRQ_MASK_TOG (0x0000039c) + +#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 +#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) +#define BP_PXP_IRQ_MASK_RSVD1 16 +#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_MASK_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) +#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 +#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ + (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 +#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ + (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 +#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ + (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 +#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ + (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 +#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ + (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 +#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ + (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 +#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ + (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 +#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ + (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 +#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ + (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 +#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ + (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 +#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 +#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 +#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ + (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 +#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ + (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 +#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 +#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) + +#define HW_PXP_IRQ (0x000003a0) +#define HW_PXP_IRQ_SET (0x000003a4) +#define HW_PXP_IRQ_CLR (0x000003a8) +#define HW_PXP_IRQ_TOG (0x000003ac) + +#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 +#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ + (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) +#define BP_PXP_IRQ_RSVD1 16 +#define BM_PXP_IRQ_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_RSVD1) +#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 +#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ + (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 +#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ + (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 +#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ + (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 +#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ + (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 +#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ + (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 +#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ + (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 +#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ + (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 +#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ + (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 +#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ + (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 +#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ + (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 +#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ + (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 +#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ + (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 +#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ + (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 +#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ + (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 +#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ + (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 +#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ + (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BF_PXP_NEXT_RSVD(v) \ + (((v) << 1) & BM_PXP_NEXT_RSVD) +#define BM_PXP_NEXT_ENABLED 0x00000001 +#define BF_PXP_NEXT_ENABLED(v) \ + (((v) << 0) & BM_PXP_NEXT_ENABLED) + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +#define HW_PXP_INPUT_FETCH_CTRL_CH0 (0x00000450) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_SET (0x00000454) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_CLR (0x00000458) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_TOG (0x0000045c) + +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_CTRL_CH1 (0x00000460) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_SET (0x00000464) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_CLR (0x00000468) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_TOG (0x0000046c) + +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_STATUS_CH0 (0x00000470) + +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_STATUS_CH1 (0x00000480) + +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000490) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000004a0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000004b0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000004c0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_SIZE_CH0 (0x000004d0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_SIZE_CH1 (0x000004e0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 (0x000004f0) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 (0x00000500) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_PITCH (0x00000510) + +#define BP_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 (0x00000520) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET (0x00000524) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR (0x00000528) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG (0x0000052c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 (0x00000530) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET (0x00000534) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR (0x00000538) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG (0x0000053c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 (0x00000540) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET (0x00000544) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000548) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000054c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 (0x00000550) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET (0x00000554) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000558) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000055c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 (0x00000560) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET (0x00000564) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000568) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000056c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 (0x00000570) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET (0x00000574) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000578) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000057c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH0 (0x00000580) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH0 (0x00000590) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH1 (0x000005a0) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH1 (0x000005b0) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_CTRL_CH0 (0x000005c0) +#define HW_PXP_INPUT_STORE_CTRL_CH0_SET (0x000005c4) +#define HW_PXP_INPUT_STORE_CTRL_CH0_CLR (0x000005c8) +#define HW_PXP_INPUT_STORE_CTRL_CH0_TOG (0x000005cc) + +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_CTRL_CH1 (0x000005d0) +#define HW_PXP_INPUT_STORE_CTRL_CH1_SET (0x000005d4) +#define HW_PXP_INPUT_STORE_CTRL_CH1_CLR (0x000005d8) +#define HW_PXP_INPUT_STORE_CTRL_CH1_TOG (0x000005dc) + +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_STATUS_CH0 (0x000005e0) + +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_STATUS_CH1 (0x000005f0) + +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_SIZE_CH0 (0x00000600) + +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_SIZE_CH1 (0x00000610) + +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_PITCH (0x00000620) + +#define BP_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 (0x00000630) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET (0x00000634) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR (0x00000638) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG (0x0000063c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 (0x00000640) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET (0x00000644) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR (0x00000648) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG (0x0000064c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH0 (0x00000690) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH0 (0x000006a0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_FILL_DATA_CH0 (0x000006b0) + +#define BP_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH1 (0x000006c0) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH1 (0x000006d0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_H_CH0 (0x000006e0) + +#define BP_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_L_CH0 (0x000006f0) + +#define BP_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_H_CH0 (0x00000700) + +#define BP_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_L_CH0 (0x00000710) + +#define BP_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_H_CH0 (0x00000720) + +#define BP_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_L_CH0 (0x00000730) + +#define BP_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_H_CH0 (0x00000740) + +#define BP_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_L_CH0 (0x00000750) + +#define BP_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_H_CH0 (0x00000760) + +#define BP_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_L_CH0 (0x00000770) + +#define BP_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_H_CH0 (0x00000780) + +#define BP_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_L_CH0 (0x00000790) + +#define BP_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_H_CH0 (0x000007a0) + +#define BP_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_L_CH0 (0x000007b0) + +#define BP_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_H_CH0 (0x000007c0) + +#define BP_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_L_CH0 (0x000007e0) + +#define BP_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 (0x000007f0) + +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 (0x00000800) + +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 (0x00000810) + +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 (0x00000820) + +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_MASK_L_CH0 (0x00000830) + +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_INPUT_STORE_F_MASK_H_CH0 (0x00000840) + +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_DITHER_FETCH_CTRL_CH0 (0x00000850) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_SET (0x00000854) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_CLR (0x00000858) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_TOG (0x0000085c) + +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_CTRL_CH1 (0x00000860) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_SET (0x00000864) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_CLR (0x00000868) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_TOG (0x0000086c) + +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_STATUS_CH0 (0x00000870) + +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_STATUS_CH1 (0x00000880) + +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000890) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000008a0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000008b0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000008c0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_SIZE_CH0 (0x000008d0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_SIZE_CH1 (0x000008e0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 (0x000008f0) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 (0x00000900) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_PITCH (0x00000910) + +#define BP_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 (0x00000920) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET (0x00000924) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR (0x00000928) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG (0x0000092c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 (0x00000930) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET (0x00000934) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR (0x00000938) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG (0x0000093c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 (0x00000940) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET (0x00000944) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000948) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000094c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 (0x00000950) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET (0x00000954) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000958) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000095c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 (0x00000960) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET (0x00000964) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000968) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000096c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 (0x00000970) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET (0x00000974) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000978) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000097c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH0 (0x00000980) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH0 (0x00000990) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH1 (0x000009a0) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH1 (0x000009b0) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_CTRL_CH0 (0x000009c0) +#define HW_PXP_DITHER_STORE_CTRL_CH0_SET (0x000009c4) +#define HW_PXP_DITHER_STORE_CTRL_CH0_CLR (0x000009c8) +#define HW_PXP_DITHER_STORE_CTRL_CH0_TOG (0x000009cc) + +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_CTRL_CH1 (0x000009d0) +#define HW_PXP_DITHER_STORE_CTRL_CH1_SET (0x000009d4) +#define HW_PXP_DITHER_STORE_CTRL_CH1_CLR (0x000009d8) +#define HW_PXP_DITHER_STORE_CTRL_CH1_TOG (0x000009dc) + +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_STATUS_CH0 (0x000009e0) + +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_STATUS_CH1 (0x000009f0) + +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_SIZE_CH0 (0x00000a00) + +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_SIZE_CH1 (0x00000a10) + +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_PITCH (0x00000a20) + +#define BP_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 (0x00000a30) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET (0x00000a34) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR (0x00000a38) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG (0x00000a3c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 (0x00000a40) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET (0x00000a44) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR (0x00000a48) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG (0x00000a4c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH0 (0x00000a90) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH0 (0x00000aa0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_FILL_DATA_CH0 (0x00000ab0) + +#define BP_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH1 (0x00000ac0) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH1 (0x00000ad0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_H_CH0 (0x00000ae0) + +#define BP_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_L_CH0 (0x00000af0) + +#define BP_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_H_CH0 (0x00000b00) + +#define BP_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_L_CH0 (0x00000b10) + +#define BP_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_H_CH0 (0x00000b20) + +#define BP_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_L_CH0 (0x00000b30) + +#define BP_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_H_CH0 (0x00000b40) + +#define BP_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_L_CH0 (0x00000b50) + +#define BP_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_H_CH0 (0x00000b60) + +#define BP_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_L_CH0 (0x00000b70) + +#define BP_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_H_CH0 (0x00000b80) + +#define BP_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_L_CH0 (0x00000b90) + +#define BP_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_H_CH0 (0x00000ba0) + +#define BP_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_L_CH0 (0x00000bb0) + +#define BP_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_H_CH0 (0x00000bc0) + +#define BP_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_L_CH0 (0x00000bd0) + +#define BP_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 (0x00000be0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 (0x00000bf0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 (0x00000c00) + +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 (0x00000c10) + +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_MASK_L_CH0 (0x00000c20) + +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_DITHER_STORE_F_MASK_H_CH0 (0x00000c30) + +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFA_FETCH_CTRL (0x00000c40) +#define HW_PXP_WFA_FETCH_CTRL_SET (0x00000c44) +#define HW_PXP_WFA_FETCH_CTRL_CLR (0x00000c48) +#define HW_PXP_WFA_FETCH_CTRL_TOG (0x00000c4c) + +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFA_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFA_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFA_FETCH_CTRL_RSVD0) +#define BP_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFA_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_CTRL_RSVD1) +#define BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFA_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFA_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFA_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFA_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFA_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFA_FETCH_CTRL_RSVD2) +#define BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFA_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFA_FETCH_BUF1_ADDR (0x00000c50) + +#define BP_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF1_PITCH (0x00000c60) + +#define BP_PXP_WFA_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF1_SIZE (0x00000c70) + +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_FETCH_BUF2_ADDR (0x00000c80) + +#define BP_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF2_PITCH (0x00000c90) + +#define BP_PXP_WFA_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF2_SIZE (0x00000ca0) + +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_ARRAY_PIXEL0_MASK (0x00000cb0) + +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL1_MASK (0x00000cc0) + +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL2_MASK (0x00000cd0) + +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL3_MASK (0x00000ce0) + +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL4_MASK (0x00000cf0) + +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL5_MASK (0x00000d00) + +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL6_MASK (0x00000d10) + +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL7_MASK (0x00000d20) + +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG0_MASK (0x00000d30) + +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG1_MASK (0x00000d40) + +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG2_MASK (0x00000d50) + +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG3_MASK (0x00000d60) + +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG4_MASK (0x00000d70) + +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG5_MASK (0x00000d80) + +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG6_MASK (0x00000d90) + +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG7_MASK (0x00000da0) + +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFA_FETCH_BUF1_CORD (0x00000db0) + +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFA_FETCH_BUF2_CORD (0x00000dc0) + +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFA_ARRAY_FLAG8_MASK (0x00000dd0) + +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG9_MASK (0x00000de0) + +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG10_MASK (0x00000df0) + +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG11_MASK (0x00000e00) + +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG12_MASK (0x00000e10) + +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG13_MASK (0x00000e20) + +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG14_MASK (0x00000e30) + +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG15_MASK (0x00000e40) + +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_REG0 (0x00000e50) + +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFA_ARRAY_REG1 (0x00000e60) + +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFA_ARRAY_REG2 (0x00000e70) + +#define BP_PXP_WFA_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFA_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFA_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG2_RSVD0) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_A_STORE_CTRL_CH0 (0x00000e80) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_SET (0x00000e84) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_CLR (0x00000e88) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_TOG (0x00000e8c) + +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_CTRL_CH1 (0x00000e90) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_SET (0x00000e94) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_CLR (0x00000e98) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_TOG (0x00000e9c) + +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_STATUS_CH0 (0x00000ea0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_STATUS_CH1 (0x00000eb0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_SIZE_CH0 (0x00000ec0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_SIZE_CH1 (0x00000ed0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_PITCH (0x00000ee0) + +#define BP_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0 (0x00000ef0) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET (0x00000ef4) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR (0x00000ef8) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG (0x00000efc) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1 (0x00000f00) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET (0x00000f04) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR (0x00000f08) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG (0x00000f0c) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH0 (0x00000f50) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH0 (0x00000f60) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_FILL_DATA_CH0 (0x00000f70) + +#define BP_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH1 (0x00000f80) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH1 (0x00000f90) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_H_CH0 (0x00000fa0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_L_CH0 (0x00000fb0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_H_CH0 (0x00000fc0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_L_CH0 (0x00000fd0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_H_CH0 (0x00000fe0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_L_CH0 (0x00000ff0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_H_CH0 (0x00001000) + +#define BP_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_L_CH0 (0x00001010) + +#define BP_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_H_CH0 (0x00001020) + +#define BP_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_L_CH0 (0x00001030) + +#define BP_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_H_CH0 (0x00001040) + +#define BP_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_L_CH0 (0x00001050) + +#define BP_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_H_CH0 (0x00001060) + +#define BP_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_L_CH0 (0x00001070) + +#define BP_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_H_CH0 (0x00001080) + +#define BP_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_L_CH0 (0x00001090) + +#define BP_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0 (0x000010a0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0 (0x000010b0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0 (0x000010c0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_H_CH0 (0x000010d0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_MASK_L_CH0 (0x000010e0) + +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_A_STORE_F_MASK_H_CH0 (0x000010f0) + +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFB_FETCH_CTRL (0x00001100) +#define HW_PXP_WFB_FETCH_CTRL_SET (0x00001104) +#define HW_PXP_WFB_FETCH_CTRL_CLR (0x00001108) +#define HW_PXP_WFB_FETCH_CTRL_TOG (0x0000110c) + +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFB_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFB_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFB_FETCH_CTRL_RSVD0) +#define BP_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFB_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_CTRL_RSVD1) +#define BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFB_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFB_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFB_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFB_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFB_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFB_FETCH_CTRL_RSVD2) +#define BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFB_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFB_FETCH_BUF1_ADDR (0x00001110) + +#define BP_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF1_PITCH (0x00001120) + +#define BP_PXP_WFB_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF1_SIZE (0x00001130) + +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_FETCH_BUF2_ADDR (0x00001140) + +#define BP_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF2_PITCH (0x00001150) + +#define BP_PXP_WFB_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF2_SIZE (0x00001160) + +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_ARRAY_PIXEL0_MASK (0x00001170) + +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL1_MASK (0x00001180) + +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL2_MASK (0x00001190) + +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL3_MASK (0x000011a0) + +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL4_MASK (0x000011b0) + +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL5_MASK (0x000011c0) + +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL6_MASK (0x000011d0) + +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL7_MASK (0x000011e0) + +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG0_MASK (0x000011f0) + +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG1_MASK (0x00001200) + +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG2_MASK (0x00001210) + +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG3_MASK (0x00001220) + +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG4_MASK (0x00001230) + +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG5_MASK (0x00001240) + +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG6_MASK (0x00001250) + +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG7_MASK (0x00001260) + +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFB_FETCH_BUF1_CORD (0x00001270) + +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFB_FETCH_BUF2_CORD (0x00001280) + +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFB_ARRAY_FLAG8_MASK (0x00001290) + +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG9_MASK (0x000012a0) + +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG10_MASK (0x000012b0) + +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG11_MASK (0x000012c0) + +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG12_MASK (0x000012d0) + +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG13_MASK (0x000012e0) + +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG14_MASK (0x000012f0) + +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG15_MASK (0x00001300) + +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_REG0 (0x00001310) + +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFB_ARRAY_REG1 (0x00001320) + +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFB_ARRAY_REG2 (0x00001330) + +#define BP_PXP_WFB_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFB_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFB_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG2_RSVD0) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_B_STORE_CTRL_CH0 (0x00001340) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_SET (0x00001344) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_CLR (0x00001348) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_TOG (0x0000134c) + +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_CTRL_CH1 (0x00001350) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_SET (0x00001354) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_CLR (0x00001358) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_TOG (0x0000135c) + +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_STATUS_CH0 (0x00001360) + +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_STATUS_CH1 (0x00001370) + +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_SIZE_CH0 (0x00001380) + +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_SIZE_CH1 (0x00001390) + +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_PITCH (0x000013a0) + +#define BP_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0 (0x000013b0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET (0x000013b4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR (0x000013b8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG (0x000013bc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1 (0x000013c0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET (0x000013c4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR (0x000013c8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG (0x000013cc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH0 (0x00001410) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH0 (0x00001420) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_FILL_DATA_CH0 (0x00001430) + +#define BP_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH1 (0x00001440) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH1 (0x00001450) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_H_CH0 (0x00001460) + +#define BP_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_L_CH0 (0x00001470) + +#define BP_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_H_CH0 (0x00001480) + +#define BP_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_L_CH0 (0x00001490) + +#define BP_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_H_CH0 (0x000014a0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_L_CH0 (0x000014b0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_H_CH0 (0x000014c0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_L_CH0 (0x000014d0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_H_CH0 (0x000014e0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_L_CH0 (0x000014f0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_H_CH0 (0x00001500) + +#define BP_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_L_CH0 (0x00001510) + +#define BP_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_H_CH0 (0x00001520) + +#define BP_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_L_CH0 (0x00001530) + +#define BP_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_H_CH0 (0x00001540) + +#define BP_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_L_CH0 (0x00001550) + +#define BP_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0 (0x00001560) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0 (0x00001570) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0 (0x00001580) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0 (0x00001590) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_MASK_L_CH0 (0x000015a0) + +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_B_STORE_F_MASK_H_CH0 (0x000015b0) + +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_FETCH_WFE_A_DEBUG (0x000015c0) + +#define BP_PXP_FETCH_WFE_A_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_A_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_A_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE) + +#define HW_PXP_FETCH_WFE_B_DEBUG (0x000015d0) + +#define BP_PXP_FETCH_WFE_B_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_B_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_B_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE) + +#define HW_PXP_DITHER_CTRL (0x00001670) +#define HW_PXP_DITHER_CTRL_SET (0x00001674) +#define HW_PXP_DITHER_CTRL_CLR (0x00001678) +#define HW_PXP_DITHER_CTRL_TOG (0x0000167c) + +#define BM_PXP_DITHER_CTRL_BUSY0 0x80000000 +#define BF_PXP_DITHER_CTRL_BUSY0(v) \ + (((v) << 31) & BM_PXP_DITHER_CTRL_BUSY0) +#define BM_PXP_DITHER_CTRL_BUSY1 0x40000000 +#define BF_PXP_DITHER_CTRL_BUSY1(v) \ + (((v) << 30) & BM_PXP_DITHER_CTRL_BUSY1) +#define BM_PXP_DITHER_CTRL_BUSY2 0x20000000 +#define BF_PXP_DITHER_CTRL_BUSY2(v) \ + (((v) << 29) & BM_PXP_DITHER_CTRL_BUSY2) +#define BP_PXP_DITHER_CTRL_RSVD0 25 +#define BM_PXP_DITHER_CTRL_RSVD0 0x1E000000 +#define BF_PXP_DITHER_CTRL_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_CTRL_RSVD0) +#define BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE 0x01000000 +#define BF_PXP_DITHER_CTRL_ORDERED_ROUND_MODE(v) \ + (((v) << 24) & BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE) +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__1 0x1 +#define BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE 0x00800000 +#define BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(v) \ + (((v) << 23) & BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE) +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Enabled 0x1 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 21 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 0x00600000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(v) \ + (((v) << 21) & BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 19 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 0x00180000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(v) \ + (((v) << 19) & BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 17 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 0x00060000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(v) \ + (((v) << 17) & BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_LUT_MODE 15 +#define BM_PXP_DITHER_CTRL_LUT_MODE 0x00018000 +#define BF_PXP_DITHER_CTRL_LUT_MODE(v) \ + (((v) << 15) & BM_PXP_DITHER_CTRL_LUT_MODE) +#define BV_PXP_DITHER_CTRL_LUT_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_LUT_MODE__1 0x1 +#define BV_PXP_DITHER_CTRL_LUT_MODE__2 0x2 +#define BV_PXP_DITHER_CTRL_LUT_MODE__3 0x3 +#define BP_PXP_DITHER_CTRL_NUM_QUANT_BIT 12 +#define BM_PXP_DITHER_CTRL_NUM_QUANT_BIT 0x00007000 +#define BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(v) \ + (((v) << 12) & BM_PXP_DITHER_CTRL_NUM_QUANT_BIT) +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__0 0x0 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__1 0x1 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__2 0x2 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__3 0x3 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__4 0x4 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__5 0x5 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__6 0x6 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE2 9 +#define BM_PXP_DITHER_CTRL_DITHER_MODE2 0x00000E00 +#define BF_PXP_DITHER_CTRL_DITHER_MODE2(v) \ + (((v) << 9) & BM_PXP_DITHER_CTRL_DITHER_MODE2) +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE1 6 +#define BM_PXP_DITHER_CTRL_DITHER_MODE1 0x000001C0 +#define BF_PXP_DITHER_CTRL_DITHER_MODE1(v) \ + (((v) << 6) & BM_PXP_DITHER_CTRL_DITHER_MODE1) +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE0 3 +#define BM_PXP_DITHER_CTRL_DITHER_MODE0 0x00000038 +#define BF_PXP_DITHER_CTRL_DITHER_MODE0(v) \ + (((v) << 3) & BM_PXP_DITHER_CTRL_DITHER_MODE0) +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__7 0x7 +#define BM_PXP_DITHER_CTRL_ENABLE2 0x00000004 +#define BF_PXP_DITHER_CTRL_ENABLE2(v) \ + (((v) << 2) & BM_PXP_DITHER_CTRL_ENABLE2) +#define BV_PXP_DITHER_CTRL_ENABLE2__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE2__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE1 0x00000002 +#define BF_PXP_DITHER_CTRL_ENABLE1(v) \ + (((v) << 1) & BM_PXP_DITHER_CTRL_ENABLE1) +#define BV_PXP_DITHER_CTRL_ENABLE1__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE1__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE0 0x00000001 +#define BF_PXP_DITHER_CTRL_ENABLE0(v) \ + (((v) << 0) & BM_PXP_DITHER_CTRL_ENABLE0) +#define BV_PXP_DITHER_CTRL_ENABLE0__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE0__Enabled 0x1 + +#define HW_PXP_DITHER_FINAL_LUT_DATA0 (0x00001680) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_SET (0x00001684) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_CLR (0x00001688) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_TOG (0x0000168c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA3 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA2 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA1 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0) + +#define HW_PXP_DITHER_FINAL_LUT_DATA1 (0x00001690) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_SET (0x00001694) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_CLR (0x00001698) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_TOG (0x0000169c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA7 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA6 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA5 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4) + +#define HW_PXP_DITHER_FINAL_LUT_DATA2 (0x000016a0) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_SET (0x000016a4) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_CLR (0x000016a8) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_TOG (0x000016ac) + +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA11 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA10 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA9 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8) + +#define HW_PXP_DITHER_FINAL_LUT_DATA3 (0x000016b0) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_SET (0x000016b4) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_CLR (0x000016b8) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_TOG (0x000016bc) + +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA15 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA14 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA13 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12) + +#define HW_PXP_WFE_A_CTRL (0x000016c0) +#define HW_PXP_WFE_A_CTRL_SET (0x000016c4) +#define HW_PXP_WFE_A_CTRL_CLR (0x000016c8) +#define HW_PXP_WFE_A_CTRL_TOG (0x000016cc) + +#define BM_PXP_WFE_A_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_A_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_A_CTRL_DONE) +#define BP_PXP_WFE_A_CTRL_RSVD0 3 +#define BM_PXP_WFE_A_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_A_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_A_CTRL_RSVD0) +#define BM_PXP_WFE_A_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_A_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_A_CTRL_SW_RESET) +#define BM_PXP_WFE_A_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_A_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_A_CTRL_RSVD1) +#define BM_PXP_WFE_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_A_CTRL_ENABLE) +#define BV_PXP_WFE_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_A_DIMENSIONS (0x000016d0) + +#define BP_PXP_WFE_A_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_A_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_A_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_A_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_A_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_A_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_A_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_A_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_A_OFFSET (0x000016e0) + +#define BP_PXP_WFE_A_OFFSET_RSVD0 28 +#define BM_PXP_WFE_A_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_OFFSET_RSVD0) +#define BP_PXP_WFE_A_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_A_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_A_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_A_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_A_OFFSET_RSVD1 12 +#define BM_PXP_WFE_A_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_OFFSET_RSVD1) +#define BP_PXP_WFE_A_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_A_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_A_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_A_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_A_SW_DATA_REGS (0x000016f0) + +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_A_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_A_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_A_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_A_SW_FLAG_REGS (0x00001700) + +#define BP_PXP_WFE_A_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_A_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_A_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_A_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_A_STAGE1_MUX0 (0x00001710) +#define HW_PXP_WFE_A_STAGE1_MUX0_SET (0x00001714) +#define HW_PXP_WFE_A_STAGE1_MUX0_CLR (0x00001718) +#define HW_PXP_WFE_A_STAGE1_MUX0_TOG (0x0000171c) + +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE1_MUX1 (0x00001720) +#define HW_PXP_WFE_A_STAGE1_MUX1_SET (0x00001724) +#define HW_PXP_WFE_A_STAGE1_MUX1_CLR (0x00001728) +#define HW_PXP_WFE_A_STAGE1_MUX1_TOG (0x0000172c) + +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX1_MUX7) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__NOP 0xc +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX1_MUX4) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__NOP 0xc + +#define HW_PXP_WFE_A_STAGE1_MUX2 (0x00001730) +#define HW_PXP_WFE_A_STAGE1_MUX2_SET (0x00001734) +#define HW_PXP_WFE_A_STAGE1_MUX2_CLR (0x00001738) +#define HW_PXP_WFE_A_STAGE1_MUX2_TOG (0x0000173c) + +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE1_MUX3 (0x00001740) +#define HW_PXP_WFE_A_STAGE1_MUX3_SET (0x00001744) +#define HW_PXP_WFE_A_STAGE1_MUX3_CLR (0x00001748) +#define HW_PXP_WFE_A_STAGE1_MUX3_TOG (0x0000174c) + +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE1_MUX4 (0x00001750) +#define HW_PXP_WFE_A_STAGE1_MUX4_SET (0x00001754) +#define HW_PXP_WFE_A_STAGE1_MUX4_CLR (0x00001758) +#define HW_PXP_WFE_A_STAGE1_MUX4_TOG (0x0000175c) + +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD0 24 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD0 0xFF000000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD1 16 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD1 0x00FF0000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD1(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX0 (0x00001760) +#define HW_PXP_WFE_A_STAGE2_MUX0_SET (0x00001764) +#define HW_PXP_WFE_A_STAGE2_MUX0_CLR (0x00001768) +#define HW_PXP_WFE_A_STAGE2_MUX0_TOG (0x0000176c) + +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE2_MUX1 (0x00001770) +#define HW_PXP_WFE_A_STAGE2_MUX1_SET (0x00001774) +#define HW_PXP_WFE_A_STAGE2_MUX1_CLR (0x00001778) +#define HW_PXP_WFE_A_STAGE2_MUX1_TOG (0x0000177c) + +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE2_MUX2 (0x00001780) +#define HW_PXP_WFE_A_STAGE2_MUX2_SET (0x00001784) +#define HW_PXP_WFE_A_STAGE2_MUX2_CLR (0x00001788) +#define HW_PXP_WFE_A_STAGE2_MUX2_TOG (0x0000178c) + +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE2_MUX3 (0x00001790) +#define HW_PXP_WFE_A_STAGE2_MUX3_SET (0x00001794) +#define HW_PXP_WFE_A_STAGE2_MUX3_CLR (0x00001798) +#define HW_PXP_WFE_A_STAGE2_MUX3_TOG (0x0000179c) + +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE2_MUX4 (0x000017a0) +#define HW_PXP_WFE_A_STAGE2_MUX4_SET (0x000017a4) +#define HW_PXP_WFE_A_STAGE2_MUX4_CLR (0x000017a8) +#define HW_PXP_WFE_A_STAGE2_MUX4_TOG (0x000017ac) + +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX5 (0x000017b0) +#define HW_PXP_WFE_A_STAGE2_MUX5_SET (0x000017b4) +#define HW_PXP_WFE_A_STAGE2_MUX5_CLR (0x000017b8) +#define HW_PXP_WFE_A_STAGE2_MUX5_TOG (0x000017bc) + +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_A_STAGE2_MUX6 (0x000017c0) +#define HW_PXP_WFE_A_STAGE2_MUX6_SET (0x000017c4) +#define HW_PXP_WFE_A_STAGE2_MUX6_CLR (0x000017c8) +#define HW_PXP_WFE_A_STAGE2_MUX6_TOG (0x000017cc) + +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_A_STAGE2_MUX7 (0x000017d0) +#define HW_PXP_WFE_A_STAGE2_MUX7_SET (0x000017d4) +#define HW_PXP_WFE_A_STAGE2_MUX7_CLR (0x000017d8) +#define HW_PXP_WFE_A_STAGE2_MUX7_TOG (0x000017dc) + +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_A_STAGE2_MUX8 (0x000017e0) +#define HW_PXP_WFE_A_STAGE2_MUX8_SET (0x000017e4) +#define HW_PXP_WFE_A_STAGE2_MUX8_CLR (0x000017e8) +#define HW_PXP_WFE_A_STAGE2_MUX8_TOG (0x000017ec) + +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_A_STAGE2_MUX9 (0x000017f0) +#define HW_PXP_WFE_A_STAGE2_MUX9_SET (0x000017f4) +#define HW_PXP_WFE_A_STAGE2_MUX9_CLR (0x000017f8) +#define HW_PXP_WFE_A_STAGE2_MUX9_TOG (0x000017fc) + +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_A_STAGE2_MUX10 (0x00001800) +#define HW_PXP_WFE_A_STAGE2_MUX10_SET (0x00001804) +#define HW_PXP_WFE_A_STAGE2_MUX10_CLR (0x00001808) +#define HW_PXP_WFE_A_STAGE2_MUX10_TOG (0x0000180c) + +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX10_MUX43) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__NOP 0xc +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_A_STAGE2_MUX11 (0x00001810) +#define HW_PXP_WFE_A_STAGE2_MUX11_SET (0x00001814) +#define HW_PXP_WFE_A_STAGE2_MUX11_CLR (0x00001818) +#define HW_PXP_WFE_A_STAGE2_MUX11_TOG (0x0000181c) + +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_A_STAGE2_MUX12 (0x00001820) +#define HW_PXP_WFE_A_STAGE2_MUX12_SET (0x00001824) +#define HW_PXP_WFE_A_STAGE2_MUX12_CLR (0x00001828) +#define HW_PXP_WFE_A_STAGE2_MUX12_TOG (0x0000182c) + +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD0 14 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD0 0xFFFFC000 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD0(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX49 8 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX49 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX49(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX12_MUX49) +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_A_STAGE3_MUX0 (0x00001830) +#define HW_PXP_WFE_A_STAGE3_MUX0_SET (0x00001834) +#define HW_PXP_WFE_A_STAGE3_MUX0_CLR (0x00001838) +#define HW_PXP_WFE_A_STAGE3_MUX0_TOG (0x0000183c) + +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE3_MUX1 (0x00001840) +#define HW_PXP_WFE_A_STAGE3_MUX1_SET (0x00001844) +#define HW_PXP_WFE_A_STAGE3_MUX1_CLR (0x00001848) +#define HW_PXP_WFE_A_STAGE3_MUX1_TOG (0x0000184c) + +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE3_MUX2 (0x00001850) +#define HW_PXP_WFE_A_STAGE3_MUX2_SET (0x00001854) +#define HW_PXP_WFE_A_STAGE3_MUX2_CLR (0x00001858) +#define HW_PXP_WFE_A_STAGE3_MUX2_TOG (0x0000185c) + +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE3_MUX3 (0x00001860) +#define HW_PXP_WFE_A_STAGE3_MUX3_SET (0x00001864) +#define HW_PXP_WFE_A_STAGE3_MUX3_CLR (0x00001868) +#define HW_PXP_WFE_A_STAGE3_MUX3_TOG (0x0000186c) + +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_0 (0x00001870) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_1 (0x00001880) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_2 (0x00001890) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_3 (0x000018a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_4 (0x000018b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_5 (0x000018c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_6 (0x000018d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_7 (0x000018e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_0 (0x000018f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_1 (0x00001900) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_2 (0x00001910) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_3 (0x00001920) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_4 (0x00001930) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_5 (0x00001940) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_6 (0x00001950) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_7 (0x00001960) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_0 (0x00001970) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_1 (0x00001980) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_2 (0x00001990) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_3 (0x000019a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_4 (0x000019b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_5 (0x000019c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_6 (0x000019d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_7 (0x000019e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_0 (0x000019f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_1 (0x00001a00) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_2 (0x00001a10) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_3 (0x00001a20) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_4 (0x00001a30) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_5 (0x00001a40) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_6 (0x00001a50) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_7 (0x00001a60) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_0 (0x00001a70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_1 (0x00001a80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_2 (0x00001a90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_3 (0x00001aa0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_4 (0x00001ab0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_5 (0x00001ac0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_6 (0x00001ad0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_7 (0x00001ae0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_0 (0x00001af0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_1 (0x00001b00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_2 (0x00001b10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_3 (0x00001b20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_4 (0x00001b30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_5 (0x00001b40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_6 (0x00001b50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_7 (0x00001b60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_0 (0x00001b70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_1 (0x00001b80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_2 (0x00001b90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_3 (0x00001ba0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_4 (0x00001bb0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_5 (0x00001bc0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_6 (0x00001bd0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_7 (0x00001be0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_0 (0x00001bf0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_1 (0x00001c00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_2 (0x00001c10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_3 (0x00001c20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_4 (0x00001c30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_5 (0x00001c40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_6 (0x00001c50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_7 (0x00001c60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_A_STAGE2_5X6_MASKS_0 (0x00001c70) + +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 29 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 0xE0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 29) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 21 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 0x00E00000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 21) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 0x0000E000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_A_STAGE2_5X6_ADDR_0 (0x00001c80) + +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT0 (0x00001c90) + +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT1 (0x00001ca0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT2 (0x00001cb0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT3 (0x00001cc0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_MASKS (0x00001cd0) + +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_CTRL (0x00001d00) +#define HW_PXP_WFE_B_CTRL_SET (0x00001d04) +#define HW_PXP_WFE_B_CTRL_CLR (0x00001d08) +#define HW_PXP_WFE_B_CTRL_TOG (0x00001d0c) + +#define BM_PXP_WFE_B_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_B_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_B_CTRL_DONE) +#define BP_PXP_WFE_B_CTRL_RSVD0 3 +#define BM_PXP_WFE_B_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_B_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_B_CTRL_RSVD0) +#define BM_PXP_WFE_B_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_B_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_B_CTRL_SW_RESET) +#define BM_PXP_WFE_B_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_B_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_B_CTRL_RSVD1) +#define BM_PXP_WFE_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_B_CTRL_ENABLE) +#define BV_PXP_WFE_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_B_DIMENSIONS (0x00001d10) + +#define BP_PXP_WFE_B_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_B_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_B_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_B_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_B_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_B_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_B_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_B_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_B_OFFSET (0x00001d20) + +#define BP_PXP_WFE_B_OFFSET_RSVD0 28 +#define BM_PXP_WFE_B_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_OFFSET_RSVD0) +#define BP_PXP_WFE_B_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_B_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_B_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_B_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_B_OFFSET_RSVD1 12 +#define BM_PXP_WFE_B_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_OFFSET_RSVD1) +#define BP_PXP_WFE_B_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_B_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_B_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_B_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_B_SW_DATA_REGS (0x00001d30) + +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_B_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_B_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_B_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_B_SW_FLAG_REGS (0x00001d40) + +#define BP_PXP_WFE_B_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_B_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_B_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_B_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_B_STAGE1_MUX0 (0x00001d50) +#define HW_PXP_WFE_B_STAGE1_MUX0_SET (0x00001d54) +#define HW_PXP_WFE_B_STAGE1_MUX0_CLR (0x00001d58) +#define HW_PXP_WFE_B_STAGE1_MUX0_TOG (0x00001d5c) + +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE1_MUX1 (0x00001d60) +#define HW_PXP_WFE_B_STAGE1_MUX1_SET (0x00001d64) +#define HW_PXP_WFE_B_STAGE1_MUX1_CLR (0x00001d68) +#define HW_PXP_WFE_B_STAGE1_MUX1_TOG (0x00001d6c) + +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE1_MUX2 (0x00001d70) +#define HW_PXP_WFE_B_STAGE1_MUX2_SET (0x00001d74) +#define HW_PXP_WFE_B_STAGE1_MUX2_CLR (0x00001d78) +#define HW_PXP_WFE_B_STAGE1_MUX2_TOG (0x00001d7c) + +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE1_MUX3 (0x00001d80) +#define HW_PXP_WFE_B_STAGE1_MUX3_SET (0x00001d84) +#define HW_PXP_WFE_B_STAGE1_MUX3_CLR (0x00001d88) +#define HW_PXP_WFE_B_STAGE1_MUX3_TOG (0x00001d8c) + +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE1_MUX4 (0x00001d90) +#define HW_PXP_WFE_B_STAGE1_MUX4_SET (0x00001d94) +#define HW_PXP_WFE_B_STAGE1_MUX4_CLR (0x00001d98) +#define HW_PXP_WFE_B_STAGE1_MUX4_TOG (0x00001d9c) + +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE1_MUX5 (0x00001da0) +#define HW_PXP_WFE_B_STAGE1_MUX5_SET (0x00001da4) +#define HW_PXP_WFE_B_STAGE1_MUX5_CLR (0x00001da8) +#define HW_PXP_WFE_B_STAGE1_MUX5_TOG (0x00001dac) + +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX5_MUX20) +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__INC 0x0 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__DEC 0x1 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__ADD 0x2 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__AND 0x4 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__OR 0x5 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__XOR 0x6 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__NOP 0xc + +#define HW_PXP_WFE_B_STAGE1_MUX6 (0x00001db0) +#define HW_PXP_WFE_B_STAGE1_MUX6_SET (0x00001db4) +#define HW_PXP_WFE_B_STAGE1_MUX6_CLR (0x00001db8) +#define HW_PXP_WFE_B_STAGE1_MUX6_TOG (0x00001dbc) + +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE1_MUX7 (0x00001dc0) +#define HW_PXP_WFE_B_STAGE1_MUX7_SET (0x00001dc4) +#define HW_PXP_WFE_B_STAGE1_MUX7_CLR (0x00001dc8) +#define HW_PXP_WFE_B_STAGE1_MUX7_TOG (0x00001dcc) + +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE1_MUX8 (0x00001dd0) +#define HW_PXP_WFE_B_STAGE1_MUX8_SET (0x00001dd4) +#define HW_PXP_WFE_B_STAGE1_MUX8_CLR (0x00001dd8) +#define HW_PXP_WFE_B_STAGE1_MUX8_TOG (0x00001ddc) + +#define BP_PXP_WFE_B_STAGE1_MUX8_RSVD0 6 +#define BM_PXP_WFE_B_STAGE1_MUX8_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE1_MUX8_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE1_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX0 (0x00001de0) +#define HW_PXP_WFE_B_STAGE2_MUX0_SET (0x00001de4) +#define HW_PXP_WFE_B_STAGE2_MUX0_CLR (0x00001de8) +#define HW_PXP_WFE_B_STAGE2_MUX0_TOG (0x00001dec) + +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE2_MUX1 (0x00001df0) +#define HW_PXP_WFE_B_STAGE2_MUX1_SET (0x00001df4) +#define HW_PXP_WFE_B_STAGE2_MUX1_CLR (0x00001df8) +#define HW_PXP_WFE_B_STAGE2_MUX1_TOG (0x00001dfc) + +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE2_MUX2 (0x00001e00) +#define HW_PXP_WFE_B_STAGE2_MUX2_SET (0x00001e04) +#define HW_PXP_WFE_B_STAGE2_MUX2_CLR (0x00001e08) +#define HW_PXP_WFE_B_STAGE2_MUX2_TOG (0x00001e0c) + +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE2_MUX3 (0x00001e10) +#define HW_PXP_WFE_B_STAGE2_MUX3_SET (0x00001e14) +#define HW_PXP_WFE_B_STAGE2_MUX3_CLR (0x00001e18) +#define HW_PXP_WFE_B_STAGE2_MUX3_TOG (0x00001e1c) + +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE2_MUX4 (0x00001e20) +#define HW_PXP_WFE_B_STAGE2_MUX4_SET (0x00001e24) +#define HW_PXP_WFE_B_STAGE2_MUX4_CLR (0x00001e28) +#define HW_PXP_WFE_B_STAGE2_MUX4_TOG (0x00001e2c) + +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE2_MUX5 (0x00001e30) +#define HW_PXP_WFE_B_STAGE2_MUX5_SET (0x00001e34) +#define HW_PXP_WFE_B_STAGE2_MUX5_CLR (0x00001e38) +#define HW_PXP_WFE_B_STAGE2_MUX5_TOG (0x00001e3c) + +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE2_MUX6 (0x00001e40) +#define HW_PXP_WFE_B_STAGE2_MUX6_SET (0x00001e44) +#define HW_PXP_WFE_B_STAGE2_MUX6_CLR (0x00001e48) +#define HW_PXP_WFE_B_STAGE2_MUX6_TOG (0x00001e4c) + +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE2_MUX7 (0x00001e50) +#define HW_PXP_WFE_B_STAGE2_MUX7_SET (0x00001e54) +#define HW_PXP_WFE_B_STAGE2_MUX7_CLR (0x00001e58) +#define HW_PXP_WFE_B_STAGE2_MUX7_TOG (0x00001e5c) + +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE2_MUX8 (0x00001e60) +#define HW_PXP_WFE_B_STAGE2_MUX8_SET (0x00001e64) +#define HW_PXP_WFE_B_STAGE2_MUX8_CLR (0x00001e68) +#define HW_PXP_WFE_B_STAGE2_MUX8_TOG (0x00001e6c) + +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX9 (0x00001e70) +#define HW_PXP_WFE_B_STAGE2_MUX9_SET (0x00001e74) +#define HW_PXP_WFE_B_STAGE2_MUX9_CLR (0x00001e78) +#define HW_PXP_WFE_B_STAGE2_MUX9_TOG (0x00001e7c) + +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE2_MUX10 (0x00001e80) +#define HW_PXP_WFE_B_STAGE2_MUX10_SET (0x00001e84) +#define HW_PXP_WFE_B_STAGE2_MUX10_CLR (0x00001e88) +#define HW_PXP_WFE_B_STAGE2_MUX10_TOG (0x00001e8c) + +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_B_STAGE2_MUX11 (0x00001e90) +#define HW_PXP_WFE_B_STAGE2_MUX11_SET (0x00001e94) +#define HW_PXP_WFE_B_STAGE2_MUX11_CLR (0x00001e98) +#define HW_PXP_WFE_B_STAGE2_MUX11_TOG (0x00001e9c) + +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_B_STAGE2_MUX12 (0x00001ea0) +#define HW_PXP_WFE_B_STAGE2_MUX12_SET (0x00001ea4) +#define HW_PXP_WFE_B_STAGE2_MUX12_CLR (0x00001ea8) +#define HW_PXP_WFE_B_STAGE2_MUX12_TOG (0x00001eac) + +#define BP_PXP_WFE_B_STAGE2_MUX12_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_MUX12_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE2_MUX12_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_B_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_B_STAGE3_MUX0 (0x00001eb0) +#define HW_PXP_WFE_B_STAGE3_MUX0_SET (0x00001eb4) +#define HW_PXP_WFE_B_STAGE3_MUX0_CLR (0x00001eb8) +#define HW_PXP_WFE_B_STAGE3_MUX0_TOG (0x00001ebc) + +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE3_MUX1 (0x00001ec0) +#define HW_PXP_WFE_B_STAGE3_MUX1_SET (0x00001ec4) +#define HW_PXP_WFE_B_STAGE3_MUX1_CLR (0x00001ec8) +#define HW_PXP_WFE_B_STAGE3_MUX1_TOG (0x00001ecc) + +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE3_MUX2 (0x00001ed0) +#define HW_PXP_WFE_B_STAGE3_MUX2_SET (0x00001ed4) +#define HW_PXP_WFE_B_STAGE3_MUX2_CLR (0x00001ed8) +#define HW_PXP_WFE_B_STAGE3_MUX2_TOG (0x00001edc) + +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE3_MUX3 (0x00001ee0) +#define HW_PXP_WFE_B_STAGE3_MUX3_SET (0x00001ee4) +#define HW_PXP_WFE_B_STAGE3_MUX3_CLR (0x00001ee8) +#define HW_PXP_WFE_B_STAGE3_MUX3_TOG (0x00001eec) + +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE3_MUX4 (0x00001ef0) +#define HW_PXP_WFE_B_STAGE3_MUX4_SET (0x00001ef4) +#define HW_PXP_WFE_B_STAGE3_MUX4_CLR (0x00001ef8) +#define HW_PXP_WFE_B_STAGE3_MUX4_TOG (0x00001efc) + +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE3_MUX5 (0x00001f00) +#define HW_PXP_WFE_B_STAGE3_MUX5_SET (0x00001f04) +#define HW_PXP_WFE_B_STAGE3_MUX5_CLR (0x00001f08) +#define HW_PXP_WFE_B_STAGE3_MUX5_TOG (0x00001f0c) + +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE3_MUX6 (0x00001f10) +#define HW_PXP_WFE_B_STAGE3_MUX6_SET (0x00001f14) +#define HW_PXP_WFE_B_STAGE3_MUX6_CLR (0x00001f18) +#define HW_PXP_WFE_B_STAGE3_MUX6_TOG (0x00001f1c) + +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE3_MUX7 (0x00001f20) +#define HW_PXP_WFE_B_STAGE3_MUX7_SET (0x00001f24) +#define HW_PXP_WFE_B_STAGE3_MUX7_CLR (0x00001f28) +#define HW_PXP_WFE_B_STAGE3_MUX7_TOG (0x00001f2c) + +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE3_MUX8 (0x00001f30) +#define HW_PXP_WFE_B_STAGE3_MUX8_SET (0x00001f34) +#define HW_PXP_WFE_B_STAGE3_MUX8_CLR (0x00001f38) +#define HW_PXP_WFE_B_STAGE3_MUX8_TOG (0x00001f3c) + +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE3_MUX9 (0x00001f40) +#define HW_PXP_WFE_B_STAGE3_MUX9_SET (0x00001f44) +#define HW_PXP_WFE_B_STAGE3_MUX9_CLR (0x00001f48) +#define HW_PXP_WFE_B_STAGE3_MUX9_TOG (0x00001f4c) + +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE3_MUX10 (0x00001f50) +#define HW_PXP_WFE_B_STAGE3_MUX10_SET (0x00001f54) +#define HW_PXP_WFE_B_STAGE3_MUX10_CLR (0x00001f58) +#define HW_PXP_WFE_B_STAGE3_MUX10_TOG (0x00001f5c) + +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX10_MUX40) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_0 (0x00001f60) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_1 (0x00001f70) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_2 (0x00001f80) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_3 (0x00001f90) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_4 (0x00001fa0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_5 (0x00001fb0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_6 (0x00001fc0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_7 (0x00001fd0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_0 (0x00001fe0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_1 (0x00001ff0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_2 (0x00002000) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_3 (0x00002010) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_4 (0x00002020) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_5 (0x00002030) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_6 (0x00002040) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_7 (0x00002050) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE1_5X8_MASKS_0 (0x00002060) + +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 0xFFFFE000 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STG1_5X1_OUT0 (0x00002070) + +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X1_MASKS (0x00002080) + +#define BP_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 0xFFFFFFE0 +#define BF_PXP_WFE_B_STG1_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG1_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_0 (0x00002090) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_1 (0x000020a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_2 (0x000020b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_3 (0x000020c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_4 (0x000020d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_5 (0x000020e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_6 (0x000020f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_7 (0x00002100) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_0 (0x00002110) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_1 (0x00002120) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_2 (0x00002130) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_3 (0x00002140) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_4 (0x00002150) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_5 (0x00002160) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_6 (0x00002170) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_7 (0x00002180) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_0 (0x00002190) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_1 (0x000021a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_2 (0x000021b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_3 (0x000021c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_4 (0x000021d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_5 (0x000021e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_6 (0x000021f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_7 (0x00002200) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_0 (0x00002210) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_1 (0x00002220) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_2 (0x00002230) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_3 (0x00002240) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_4 (0x00002250) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_5 (0x00002260) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_6 (0x00002270) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_7 (0x00002280) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_0 (0x00002290) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_1 (0x000022a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_2 (0x000022b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_3 (0x000022c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_4 (0x000022d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_5 (0x000022e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_6 (0x000022f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_7 (0x00002300) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_0 (0x00002310) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_1 (0x00002320) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_2 (0x00002330) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_3 (0x00002340) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_4 (0x00002350) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_5 (0x00002360) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_6 (0x00002370) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_7 (0x00002380) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_0 (0x00002390) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_1 (0x000023a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_2 (0x000023b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_3 (0x000023c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_4 (0x000023d0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_5 (0x000023e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_6 (0x000023f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_7 (0x00002400) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_0 (0x00002410) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_1 (0x00002420) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_2 (0x00002430) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_3 (0x00002440) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_4 (0x00002450) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_5 (0x00002460) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_6 (0x00002470) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_7 (0x00002480) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_0 (0x00002490) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_1 (0x000024a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_2 (0x000024b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_3 (0x000024c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_4 (0x000024e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_5 (0x000024f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_6 (0x00002500) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_7 (0x00002510) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE2_5X6_MASKS_0 (0x00002520) + +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 29 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 21 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 13 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 5 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STAGE2_5X6_ADDR_0 (0x00002530) + +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 30 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 22 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 14 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT0 (0x00002540) + +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT1 (0x00002550) + +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT2 (0x00002560) + +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT3 (0x00002570) + +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_MASKS (0x00002580) + +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_0 (0x00002590) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_1 (0x000025a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_2 (0x000025b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_3 (0x000025c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_4 (0x000025d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_5 (0x000025e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_6 (0x000025f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_7 (0x00002600) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_0 (0x00002610) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_1 (0x00002620) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_2 (0x00002630) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_3 (0x00002640) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_4 (0x00002650) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_5 (0x00002660) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_6 (0x00002670) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_7 (0x00002680) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_0 (0x00002690) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_1 (0x000026a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_2 (0x000026b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_3 (0x000026c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_4 (0x000026d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_5 (0x000026e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_6 (0x000026f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_7 (0x00002700) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_0 (0x00002710) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_1 (0x00002720) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_2 (0x00002730) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_3 (0x00002740) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_4 (0x00002750) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_5 (0x00002760) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_6 (0x00002770) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_7 (0x00002780) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_MASKS (0x00002790) + +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0x000000FF +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0) + +#define HW_PXP_ALU_A_CTRL (0x00002810) +#define HW_PXP_ALU_A_CTRL_SET (0x00002814) +#define HW_PXP_ALU_A_CTRL_CLR (0x00002818) +#define HW_PXP_ALU_A_CTRL_TOG (0x0000281c) + +#define BP_PXP_ALU_A_CTRL_RSVD0 29 +#define BM_PXP_ALU_A_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_A_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_A_CTRL_RSVD0) +#define BM_PXP_ALU_A_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_A_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_A_CTRL_DONE) +#define BP_PXP_ALU_A_CTRL_RSVD1 21 +#define BM_PXP_ALU_A_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_A_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_A_CTRL_RSVD1) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_A_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_A_CTRL_RSVD2 17 +#define BM_PXP_ALU_A_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_A_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_A_CTRL_RSVD2) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_A_CTRL_RSVD3 13 +#define BM_PXP_ALU_A_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_A_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_A_CTRL_RSVD3) +#define BM_PXP_ALU_A_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_A_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_A_CTRL_BYPASS) +#define BV_PXP_ALU_A_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_A_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_A_CTRL_RSVD4 9 +#define BM_PXP_ALU_A_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_A_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_A_CTRL_RSVD4) +#define BM_PXP_ALU_A_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_A_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_A_CTRL_SW_RESET) +#define BP_PXP_ALU_A_CTRL_RSVD5 5 +#define BM_PXP_ALU_A_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_A_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_A_CTRL_RSVD5) +#define BM_PXP_ALU_A_CTRL_START 0x00000010 +#define BF_PXP_ALU_A_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_A_CTRL_START) +#define BP_PXP_ALU_A_CTRL_RSVD6 1 +#define BM_PXP_ALU_A_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_A_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_A_CTRL_RSVD6) +#define BM_PXP_ALU_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_A_CTRL_ENABLE) +#define BV_PXP_ALU_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_A_BUF_SIZE (0x00002820) + +#define BP_PXP_ALU_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_A_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_A_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_A_INST_ENTRY (0x00002830) + +#define BP_PXP_ALU_A_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_A_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_A_PARAM (0x00002840) + +#define BP_PXP_ALU_A_PARAM_RSVD0 16 +#define BM_PXP_ALU_A_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_PARAM_RSVD0) +#define BP_PXP_ALU_A_PARAM_PARAM1 8 +#define BM_PXP_ALU_A_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_A_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_A_PARAM_PARAM1) +#define BP_PXP_ALU_A_PARAM_PARAM0 0 +#define BM_PXP_ALU_A_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_A_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_A_PARAM_PARAM0) + +#define HW_PXP_ALU_A_CONFIG (0x00002850) + +#define BP_PXP_ALU_A_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_A_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_A_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_A_LUT_CONFIG (0x00002860) +#define HW_PXP_ALU_A_LUT_CONFIG_SET (0x00002864) +#define HW_PXP_ALU_A_LUT_CONFIG_CLR (0x00002868) +#define HW_PXP_ALU_A_LUT_CONFIG_TOG (0x0000286c) + +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_A_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_A_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_A_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_A_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_A_LUT_CONFIG_MODE) +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_A_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_A_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_A_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_A_LUT_CONFIG_EN) + +#define HW_PXP_ALU_A_LUT_DATA0 (0x00002870) + +#define BP_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_A_LUT_DATA1 (0x00002880) + +#define BP_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_A_DBG (0x00002890) + +#define BP_PXP_ALU_A_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_A_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_A_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_A_DBG_DEBUG_SEL) +#define BP_PXP_ALU_A_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_A_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_A_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_A_DBG_DEBUG_VALUE) + +#define HW_PXP_ALU_B_CTRL (0x000028a0) +#define HW_PXP_ALU_B_CTRL_SET (0x000028a4) +#define HW_PXP_ALU_B_CTRL_CLR (0x000028a8) +#define HW_PXP_ALU_B_CTRL_TOG (0x000028ac) + +#define BP_PXP_ALU_B_CTRL_RSVD0 29 +#define BM_PXP_ALU_B_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_B_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_B_CTRL_RSVD0) +#define BM_PXP_ALU_B_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_B_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_B_CTRL_DONE) +#define BP_PXP_ALU_B_CTRL_RSVD1 21 +#define BM_PXP_ALU_B_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_B_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_B_CTRL_RSVD1) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_B_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_B_CTRL_RSVD2 17 +#define BM_PXP_ALU_B_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_B_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_B_CTRL_RSVD2) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_B_CTRL_RSVD3 13 +#define BM_PXP_ALU_B_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_B_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_B_CTRL_RSVD3) +#define BM_PXP_ALU_B_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_B_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_B_CTRL_BYPASS) +#define BV_PXP_ALU_B_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_B_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_B_CTRL_RSVD4 9 +#define BM_PXP_ALU_B_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_B_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_B_CTRL_RSVD4) +#define BM_PXP_ALU_B_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_B_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_B_CTRL_SW_RESET) +#define BP_PXP_ALU_B_CTRL_RSVD5 5 +#define BM_PXP_ALU_B_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_B_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_B_CTRL_RSVD5) +#define BM_PXP_ALU_B_CTRL_START 0x00000010 +#define BF_PXP_ALU_B_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_B_CTRL_START) +#define BP_PXP_ALU_B_CTRL_RSVD6 1 +#define BM_PXP_ALU_B_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_B_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_B_CTRL_RSVD6) +#define BM_PXP_ALU_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_B_CTRL_ENABLE) +#define BV_PXP_ALU_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_B_BUF_SIZE (0x000028b0) + +#define BP_PXP_ALU_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_B_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_B_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_B_INST_ENTRY (0x000028c0) + +#define BP_PXP_ALU_B_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_B_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_B_PARAM (0x000028d0) + +#define BP_PXP_ALU_B_PARAM_RSVD0 16 +#define BM_PXP_ALU_B_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_PARAM_RSVD0) +#define BP_PXP_ALU_B_PARAM_PARAM1 8 +#define BM_PXP_ALU_B_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_B_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_B_PARAM_PARAM1) +#define BP_PXP_ALU_B_PARAM_PARAM0 0 +#define BM_PXP_ALU_B_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_B_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_B_PARAM_PARAM0) + +#define HW_PXP_ALU_B_CONFIG (0x000028e0) + +#define BP_PXP_ALU_B_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_B_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_B_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_B_LUT_CONFIG (0x000028f0) +#define HW_PXP_ALU_B_LUT_CONFIG_SET (0x000028f4) +#define HW_PXP_ALU_B_LUT_CONFIG_CLR (0x000028f8) +#define HW_PXP_ALU_B_LUT_CONFIG_TOG (0x000028fc) + +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_B_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_B_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_B_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_B_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_B_LUT_CONFIG_MODE) +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_B_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_B_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_B_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_B_LUT_CONFIG_EN) + +#define HW_PXP_ALU_B_LUT_DATA0 (0x00002900) + +#define BP_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_B_LUT_DATA1 (0x00002910) + +#define BP_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_B_DBG (0x00002920) + +#define BP_PXP_ALU_B_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_B_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_B_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_B_DBG_DEBUG_SEL) +#define BP_PXP_ALU_B_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_B_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_B_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_B_DBG_DEBUG_VALUE) + +#define HW_PXP_HIST_A_CTRL (0x00002a00) + +#define BP_PXP_HIST_A_CTRL_RSVD4 27 +#define BM_PXP_HIST_A_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_A_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_A_CTRL_RSVD4) +#define BP_PXP_HIST_A_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_A_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_A_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_A_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_A_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_A_CTRL_RSVD3) +#define BP_PXP_HIST_A_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_A_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_A_CTRL_RSVD2 13 +#define BM_PXP_HIST_A_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_A_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_A_CTRL_RSVD2) +#define BP_PXP_HIST_A_CTRL_STATUS 8 +#define BM_PXP_HIST_A_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_A_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_A_CTRL_STATUS) +#define BP_PXP_HIST_A_CTRL_RSVD1 5 +#define BM_PXP_HIST_A_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_A_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_A_CTRL_RSVD1) +#define BM_PXP_HIST_A_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_A_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_A_CTRL_CLEAR) +#define BP_PXP_HIST_A_CTRL_RSVD0 1 +#define BM_PXP_HIST_A_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_A_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_CTRL_RSVD0) +#define BM_PXP_HIST_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_A_CTRL_ENABLE) + +#define HW_PXP_HIST_A_MASK (0x00002a10) + +#define BP_PXP_HIST_A_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_A_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_A_MASK_MASK_VALUE1) +#define BP_PXP_HIST_A_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_A_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_A_MASK_MASK_VALUE0) +#define BP_PXP_HIST_A_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_A_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_A_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_A_MASK_MASK_WIDTH) +#define BP_PXP_HIST_A_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_A_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_A_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_A_MASK_MASK_OFFSET) +#define BP_PXP_HIST_A_MASK_MASK_MODE 4 +#define BM_PXP_HIST_A_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_A_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_A_MASK_MASK_MODE) +#define BV_PXP_HIST_A_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_A_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_A_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_A_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_A_MASK_RSVD0 1 +#define BM_PXP_HIST_A_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_A_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_MASK_RSVD0) +#define BM_PXP_HIST_A_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_A_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_A_MASK_MASK_EN) + +#define HW_PXP_HIST_A_BUF_SIZE (0x00002a20) + +#define BP_PXP_HIST_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_A_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_A_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_A_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_A_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_A_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_A_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_A_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_A_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_A_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_A_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_A_TOTAL_PIXEL (0x00002a30) + +#define BP_PXP_HIST_A_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_A_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_A_ACTIVE_AREA_X (0x00002a40) + +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_A_ACTIVE_AREA_Y (0x00002a50) + +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_A_RAW_STAT0 (0x00002a60) + +#define BP_PXP_HIST_A_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_A_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_A_RAW_STAT1 (0x00002a70) + +#define BP_PXP_HIST_A_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_A_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST_B_CTRL (0x00002a80) + +#define BP_PXP_HIST_B_CTRL_RSVD4 27 +#define BM_PXP_HIST_B_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_B_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_B_CTRL_RSVD4) +#define BP_PXP_HIST_B_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_B_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_B_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_B_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_B_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_B_CTRL_RSVD3) +#define BP_PXP_HIST_B_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_B_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_B_CTRL_RSVD2 13 +#define BM_PXP_HIST_B_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_B_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_B_CTRL_RSVD2) +#define BP_PXP_HIST_B_CTRL_STATUS 8 +#define BM_PXP_HIST_B_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_B_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_B_CTRL_STATUS) +#define BP_PXP_HIST_B_CTRL_RSVD1 5 +#define BM_PXP_HIST_B_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_B_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_B_CTRL_RSVD1) +#define BM_PXP_HIST_B_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_B_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_B_CTRL_CLEAR) +#define BP_PXP_HIST_B_CTRL_RSVD0 1 +#define BM_PXP_HIST_B_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_B_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_CTRL_RSVD0) +#define BM_PXP_HIST_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_B_CTRL_ENABLE) + +#define HW_PXP_HIST_B_MASK (0x00002a90) + +#define BP_PXP_HIST_B_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_B_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_B_MASK_MASK_VALUE1) +#define BP_PXP_HIST_B_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_B_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_B_MASK_MASK_VALUE0) +#define BP_PXP_HIST_B_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_B_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_B_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_B_MASK_MASK_WIDTH) +#define BP_PXP_HIST_B_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_B_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_B_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_B_MASK_MASK_OFFSET) +#define BP_PXP_HIST_B_MASK_MASK_MODE 4 +#define BM_PXP_HIST_B_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_B_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_B_MASK_MASK_MODE) +#define BV_PXP_HIST_B_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_B_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_B_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_B_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_B_MASK_RSVD0 1 +#define BM_PXP_HIST_B_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_B_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_MASK_RSVD0) +#define BM_PXP_HIST_B_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_B_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_B_MASK_MASK_EN) + +#define HW_PXP_HIST_B_BUF_SIZE (0x00002aa0) + +#define BP_PXP_HIST_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_B_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_B_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_B_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_B_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_B_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_B_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_B_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_B_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_B_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_B_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_B_TOTAL_PIXEL (0x00002ab0) + +#define BP_PXP_HIST_B_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_B_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_B_ACTIVE_AREA_X (0x00002ac0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_B_ACTIVE_AREA_Y (0x00002ad0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_B_RAW_STAT0 (0x00002ae0) + +#define BP_PXP_HIST_B_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_B_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_B_RAW_STAT1 (0x00002af0) + +#define BP_PXP_HIST_B_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_B_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST2_PARAM (0x00002b00) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 14 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 6 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x00002b10) + +#define BP_PXP_HIST4_PARAM_RSVD3 30 +#define BM_PXP_HIST4_PARAM_RSVD3 0xC0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x3F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 22 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00C00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x003F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 14 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 6 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x00002b20) + +#define BP_PXP_HIST8_PARAM0_RSVD3 30 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 22 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 14 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 6 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x00002b30) + +#define BP_PXP_HIST8_PARAM1_RSVD7 30 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 22 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 14 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 6 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x00002b40) + +#define BP_PXP_HIST16_PARAM0_RSVD3 30 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 22 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 14 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 6 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x00002b50) + +#define BP_PXP_HIST16_PARAM1_RSVD7 30 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 22 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 14 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 6 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00002b60) + +#define BP_PXP_HIST16_PARAM2_RSVD11 30 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 22 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 14 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 6 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00002b70) + +#define BP_PXP_HIST16_PARAM3_RSVD15 30 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 22 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 14 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 6 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM0 (0x00002b80) + +#define BP_PXP_HIST32_PARAM0_RSVD3 30 +#define BM_PXP_HIST32_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM0_RSVD3) +#define BP_PXP_HIST32_PARAM0_VALUE3 24 +#define BM_PXP_HIST32_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST32_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM0_VALUE3) +#define BP_PXP_HIST32_PARAM0_RSVD2 22 +#define BM_PXP_HIST32_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM0_RSVD2) +#define BP_PXP_HIST32_PARAM0_VALUE2 16 +#define BM_PXP_HIST32_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST32_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM0_VALUE2) +#define BP_PXP_HIST32_PARAM0_RSVD1 14 +#define BM_PXP_HIST32_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM0_RSVD1) +#define BP_PXP_HIST32_PARAM0_VALUE1 8 +#define BM_PXP_HIST32_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST32_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM0_VALUE1) +#define BP_PXP_HIST32_PARAM0_RSVD0 6 +#define BM_PXP_HIST32_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM0_RSVD0) +#define BP_PXP_HIST32_PARAM0_VALUE0 0 +#define BM_PXP_HIST32_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST32_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM0_VALUE0) + +#define HW_PXP_HIST32_PARAM1 (0x00002b90) + +#define BP_PXP_HIST32_PARAM1_RSVD7 30 +#define BM_PXP_HIST32_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM1_RSVD7) +#define BP_PXP_HIST32_PARAM1_VALUE7 24 +#define BM_PXP_HIST32_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST32_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM1_VALUE7) +#define BP_PXP_HIST32_PARAM1_RSVD6 22 +#define BM_PXP_HIST32_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM1_RSVD6) +#define BP_PXP_HIST32_PARAM1_VALUE6 16 +#define BM_PXP_HIST32_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST32_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM1_VALUE6) +#define BP_PXP_HIST32_PARAM1_RSVD5 14 +#define BM_PXP_HIST32_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM1_RSVD5) +#define BP_PXP_HIST32_PARAM1_VALUE5 8 +#define BM_PXP_HIST32_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST32_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM1_VALUE5) +#define BP_PXP_HIST32_PARAM1_RSVD4 6 +#define BM_PXP_HIST32_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM1_RSVD4) +#define BP_PXP_HIST32_PARAM1_VALUE4 0 +#define BM_PXP_HIST32_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST32_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM1_VALUE4) + +#define HW_PXP_HIST32_PARAM2 (0x00002ba0) + +#define BP_PXP_HIST32_PARAM2_RSVD11 30 +#define BM_PXP_HIST32_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM2_RSVD11) +#define BP_PXP_HIST32_PARAM2_VALUE11 24 +#define BM_PXP_HIST32_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST32_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM2_VALUE11) +#define BP_PXP_HIST32_PARAM2_RSVD10 22 +#define BM_PXP_HIST32_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM2_RSVD10) +#define BP_PXP_HIST32_PARAM2_VALUE10 16 +#define BM_PXP_HIST32_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST32_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM2_VALUE10) +#define BP_PXP_HIST32_PARAM2_RSVD9 14 +#define BM_PXP_HIST32_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM2_RSVD9) +#define BP_PXP_HIST32_PARAM2_VALUE9 8 +#define BM_PXP_HIST32_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST32_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM2_VALUE9) +#define BP_PXP_HIST32_PARAM2_RSVD8 6 +#define BM_PXP_HIST32_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM2_RSVD8) +#define BP_PXP_HIST32_PARAM2_VALUE8 0 +#define BM_PXP_HIST32_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST32_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM2_VALUE8) + +#define HW_PXP_HIST32_PARAM3 (0x00002bb0) + +#define BP_PXP_HIST32_PARAM3_RSVD15 30 +#define BM_PXP_HIST32_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM3_RSVD15) +#define BP_PXP_HIST32_PARAM3_VALUE15 24 +#define BM_PXP_HIST32_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST32_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM3_VALUE15) +#define BP_PXP_HIST32_PARAM3_RSVD14 22 +#define BM_PXP_HIST32_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM3_RSVD14) +#define BP_PXP_HIST32_PARAM3_VALUE14 16 +#define BM_PXP_HIST32_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST32_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM3_VALUE14) +#define BP_PXP_HIST32_PARAM3_RSVD13 14 +#define BM_PXP_HIST32_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM3_RSVD13) +#define BP_PXP_HIST32_PARAM3_VALUE13 8 +#define BM_PXP_HIST32_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST32_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM3_VALUE13) +#define BP_PXP_HIST32_PARAM3_RSVD12 6 +#define BM_PXP_HIST32_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST32_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM3_RSVD12) +#define BP_PXP_HIST32_PARAM3_VALUE12 0 +#define BM_PXP_HIST32_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST32_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM4 (0x00002bc0) + +#define BP_PXP_HIST32_PARAM4_RSVD3 30 +#define BM_PXP_HIST32_PARAM4_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM4_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM4_RSVD3) +#define BP_PXP_HIST32_PARAM4_VALUE19 24 +#define BM_PXP_HIST32_PARAM4_VALUE19 0x3F000000 +#define BF_PXP_HIST32_PARAM4_VALUE19(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM4_VALUE19) +#define BP_PXP_HIST32_PARAM4_RSVD2 22 +#define BM_PXP_HIST32_PARAM4_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM4_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM4_RSVD2) +#define BP_PXP_HIST32_PARAM4_VALUE18 16 +#define BM_PXP_HIST32_PARAM4_VALUE18 0x003F0000 +#define BF_PXP_HIST32_PARAM4_VALUE18(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM4_VALUE18) +#define BP_PXP_HIST32_PARAM4_RSVD1 14 +#define BM_PXP_HIST32_PARAM4_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM4_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM4_RSVD1) +#define BP_PXP_HIST32_PARAM4_VALUE17 8 +#define BM_PXP_HIST32_PARAM4_VALUE17 0x00003F00 +#define BF_PXP_HIST32_PARAM4_VALUE17(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM4_VALUE17) +#define BP_PXP_HIST32_PARAM4_RSVD0 6 +#define BM_PXP_HIST32_PARAM4_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM4_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM4_RSVD0) +#define BP_PXP_HIST32_PARAM4_VALUE16 0 +#define BM_PXP_HIST32_PARAM4_VALUE16 0x0000003F +#define BF_PXP_HIST32_PARAM4_VALUE16(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM4_VALUE16) + +#define HW_PXP_HIST32_PARAM5 (0x00002bd0) + +#define BP_PXP_HIST32_PARAM5_RSVD7 30 +#define BM_PXP_HIST32_PARAM5_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM5_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM5_RSVD7) +#define BP_PXP_HIST32_PARAM5_VALUE23 24 +#define BM_PXP_HIST32_PARAM5_VALUE23 0x3F000000 +#define BF_PXP_HIST32_PARAM5_VALUE23(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM5_VALUE23) +#define BP_PXP_HIST32_PARAM5_RSVD6 22 +#define BM_PXP_HIST32_PARAM5_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM5_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM5_RSVD6) +#define BP_PXP_HIST32_PARAM5_VALUE22 16 +#define BM_PXP_HIST32_PARAM5_VALUE22 0x003F0000 +#define BF_PXP_HIST32_PARAM5_VALUE22(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM5_VALUE22) +#define BP_PXP_HIST32_PARAM5_RSVD5 14 +#define BM_PXP_HIST32_PARAM5_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM5_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM5_RSVD5) +#define BP_PXP_HIST32_PARAM5_VALUE21 8 +#define BM_PXP_HIST32_PARAM5_VALUE21 0x00003F00 +#define BF_PXP_HIST32_PARAM5_VALUE21(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM5_VALUE21) +#define BP_PXP_HIST32_PARAM5_RSVD4 6 +#define BM_PXP_HIST32_PARAM5_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM5_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM5_RSVD4) +#define BP_PXP_HIST32_PARAM5_VALUE20 0 +#define BM_PXP_HIST32_PARAM5_VALUE20 0x0000003F +#define BF_PXP_HIST32_PARAM5_VALUE20(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM5_VALUE20) + +#define HW_PXP_HIST32_PARAM6 (0x00002be0) + +#define BP_PXP_HIST32_PARAM6_RSVD11 30 +#define BM_PXP_HIST32_PARAM6_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM6_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM6_RSVD11) +#define BP_PXP_HIST32_PARAM6_VALUE27 24 +#define BM_PXP_HIST32_PARAM6_VALUE27 0x3F000000 +#define BF_PXP_HIST32_PARAM6_VALUE27(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM6_VALUE27) +#define BP_PXP_HIST32_PARAM6_RSVD10 22 +#define BM_PXP_HIST32_PARAM6_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM6_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM6_RSVD10) +#define BP_PXP_HIST32_PARAM6_VALUE26 16 +#define BM_PXP_HIST32_PARAM6_VALUE26 0x003F0000 +#define BF_PXP_HIST32_PARAM6_VALUE26(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM6_VALUE26) +#define BP_PXP_HIST32_PARAM6_RSVD9 14 +#define BM_PXP_HIST32_PARAM6_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM6_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM6_RSVD9) +#define BP_PXP_HIST32_PARAM6_VALUE25 8 +#define BM_PXP_HIST32_PARAM6_VALUE25 0x00003F00 +#define BF_PXP_HIST32_PARAM6_VALUE25(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM6_VALUE25) +#define BP_PXP_HIST32_PARAM6_RSVD8 6 +#define BM_PXP_HIST32_PARAM6_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM6_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM6_RSVD8) +#define BP_PXP_HIST32_PARAM6_VALUE24 0 +#define BM_PXP_HIST32_PARAM6_VALUE24 0x0000003F +#define BF_PXP_HIST32_PARAM6_VALUE24(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM6_VALUE24) + +#define HW_PXP_HIST32_PARAM7 (0x00002bf0) + +#define BP_PXP_HIST32_PARAM7_RSVD15 30 +#define BM_PXP_HIST32_PARAM7_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM7_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM7_RSVD15) +#define BP_PXP_HIST32_PARAM7_VALUE31 24 +#define BM_PXP_HIST32_PARAM7_VALUE31 0x3F000000 +#define BF_PXP_HIST32_PARAM7_VALUE31(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM7_VALUE31) +#define BP_PXP_HIST32_PARAM7_RSVD14 22 +#define BM_PXP_HIST32_PARAM7_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM7_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM7_RSVD14) +#define BP_PXP_HIST32_PARAM7_VALUE30 16 +#define BM_PXP_HIST32_PARAM7_VALUE30 0x003F0000 +#define BF_PXP_HIST32_PARAM7_VALUE30(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM7_VALUE30) +#define BP_PXP_HIST32_PARAM7_RSVD13 14 +#define BM_PXP_HIST32_PARAM7_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM7_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM7_RSVD13) +#define BP_PXP_HIST32_PARAM7_VALUE29 8 +#define BM_PXP_HIST32_PARAM7_VALUE29 0x00003F00 +#define BF_PXP_HIST32_PARAM7_VALUE29(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM7_VALUE29) +#define BP_PXP_HIST32_PARAM7_RSVD2 6 +#define BM_PXP_HIST32_PARAM7_RSVD2 0x000000C0 +#define BF_PXP_HIST32_PARAM7_RSVD2(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM7_RSVD2) +#define BP_PXP_HIST32_PARAM7_VALUE28 0 +#define BM_PXP_HIST32_PARAM7_VALUE28 0x0000003F +#define BF_PXP_HIST32_PARAM7_VALUE28(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM7_VALUE28) + +#define HW_PXP_COMP_CTRL (0x00002c00) +#define HW_PXP_COMP_CTRL_SET (0x00002c04) +#define HW_PXP_COMP_CTRL_CLR (0x00002c08) +#define HW_PXP_COMP_CTRL_TOG (0x00002c0c) + +#define BP_PXP_COMP_CTRL_RSVD0 9 +#define BM_PXP_COMP_CTRL_RSVD0 0xFFFFFE00 +#define BF_PXP_COMP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_PXP_COMP_CTRL_RSVD0) +#define BM_PXP_COMP_CTRL_SW_RESET 0x00000100 +#define BF_PXP_COMP_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_COMP_CTRL_SW_RESET) +#define BP_PXP_COMP_CTRL_RSVD1 1 +#define BM_PXP_COMP_CTRL_RSVD1 0x000000FE +#define BF_PXP_COMP_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_COMP_CTRL_RSVD1) +#define BM_PXP_COMP_CTRL_START 0x00000001 +#define BF_PXP_COMP_CTRL_START(v) \ + (((v) << 0) & BM_PXP_COMP_CTRL_START) + +#define HW_PXP_COMP_FORMAT0 (0x00002c10) +#define HW_PXP_COMP_FORMAT0_SET (0x00002c14) +#define HW_PXP_COMP_FORMAT0_CLR (0x00002c18) +#define HW_PXP_COMP_FORMAT0_TOG (0x00002c1c) + +#define BP_PXP_COMP_FORMAT0_RSVD0 28 +#define BM_PXP_COMP_FORMAT0_RSVD0 0xF0000000 +#define BF_PXP_COMP_FORMAT0_RSVD0(v) \ + (((v) << 28) & BM_PXP_COMP_FORMAT0_RSVD0) +#define BP_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 16 +#define BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 0x0FFF0000 +#define BF_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B) +#define BP_PXP_COMP_FORMAT0_RSVD1 10 +#define BM_PXP_COMP_FORMAT0_RSVD1 0x0000FC00 +#define BF_PXP_COMP_FORMAT0_RSVD1(v) \ + (((v) << 10) & BM_PXP_COMP_FORMAT0_RSVD1) +#define BP_PXP_COMP_FORMAT0_MASK_INDEX 8 +#define BM_PXP_COMP_FORMAT0_MASK_INDEX 0x00000300 +#define BF_PXP_COMP_FORMAT0_MASK_INDEX(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT0_MASK_INDEX) +#define BP_PXP_COMP_FORMAT0_RSVD2 6 +#define BM_PXP_COMP_FORMAT0_RSVD2 0x000000C0 +#define BF_PXP_COMP_FORMAT0_RSVD2(v) \ + (((v) << 6) & BM_PXP_COMP_FORMAT0_RSVD2) +#define BP_PXP_COMP_FORMAT0_FIELD_NUM 4 +#define BM_PXP_COMP_FORMAT0_FIELD_NUM 0x00000030 +#define BF_PXP_COMP_FORMAT0_FIELD_NUM(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT0_FIELD_NUM) +#define BP_PXP_COMP_FORMAT0_RSVD3 1 +#define BM_PXP_COMP_FORMAT0_RSVD3 0x0000000E +#define BF_PXP_COMP_FORMAT0_RSVD3(v) \ + (((v) << 1) & BM_PXP_COMP_FORMAT0_RSVD3) +#define BM_PXP_COMP_FORMAT0_FLAG_32B 0x00000001 +#define BF_PXP_COMP_FORMAT0_FLAG_32B(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT0_FLAG_32B) + +#define HW_PXP_COMP_FORMAT1 (0x00002c20) + +#define BP_PXP_COMP_FORMAT1_D_LEN 29 +#define BM_PXP_COMP_FORMAT1_D_LEN 0xE0000000 +#define BF_PXP_COMP_FORMAT1_D_LEN(v) \ + (((v) << 29) & BM_PXP_COMP_FORMAT1_D_LEN) +#define BP_PXP_COMP_FORMAT1_D_OFFSET 24 +#define BM_PXP_COMP_FORMAT1_D_OFFSET 0x1F000000 +#define BF_PXP_COMP_FORMAT1_D_OFFSET(v) \ + (((v) << 24) & BM_PXP_COMP_FORMAT1_D_OFFSET) +#define BP_PXP_COMP_FORMAT1_C_LEN 21 +#define BM_PXP_COMP_FORMAT1_C_LEN 0x00E00000 +#define BF_PXP_COMP_FORMAT1_C_LEN(v) \ + (((v) << 21) & BM_PXP_COMP_FORMAT1_C_LEN) +#define BP_PXP_COMP_FORMAT1_C_OFFSET 16 +#define BM_PXP_COMP_FORMAT1_C_OFFSET 0x001F0000 +#define BF_PXP_COMP_FORMAT1_C_OFFSET(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT1_C_OFFSET) +#define BP_PXP_COMP_FORMAT1_B_LEN 13 +#define BM_PXP_COMP_FORMAT1_B_LEN 0x0000E000 +#define BF_PXP_COMP_FORMAT1_B_LEN(v) \ + (((v) << 13) & BM_PXP_COMP_FORMAT1_B_LEN) +#define BP_PXP_COMP_FORMAT1_B_OFFSET 8 +#define BM_PXP_COMP_FORMAT1_B_OFFSET 0x00001F00 +#define BF_PXP_COMP_FORMAT1_B_OFFSET(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT1_B_OFFSET) +#define BP_PXP_COMP_FORMAT1_A_LEN 5 +#define BM_PXP_COMP_FORMAT1_A_LEN 0x000000E0 +#define BF_PXP_COMP_FORMAT1_A_LEN(v) \ + (((v) << 5) & BM_PXP_COMP_FORMAT1_A_LEN) +#define BP_PXP_COMP_FORMAT1_A_OFFSET 0 +#define BM_PXP_COMP_FORMAT1_A_OFFSET 0x0000001F +#define BF_PXP_COMP_FORMAT1_A_OFFSET(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT1_A_OFFSET) + +#define HW_PXP_COMP_FORMAT2 (0x00002c30) + +#define BP_PXP_COMP_FORMAT2_RSVD 16 +#define BM_PXP_COMP_FORMAT2_RSVD 0xFFFF0000 +#define BF_PXP_COMP_FORMAT2_RSVD(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT2_RSVD) +#define BP_PXP_COMP_FORMAT2_D_RUNLEN 12 +#define BM_PXP_COMP_FORMAT2_D_RUNLEN 0x0000F000 +#define BF_PXP_COMP_FORMAT2_D_RUNLEN(v) \ + (((v) << 12) & BM_PXP_COMP_FORMAT2_D_RUNLEN) +#define BP_PXP_COMP_FORMAT2_C_RUNLEN 8 +#define BM_PXP_COMP_FORMAT2_C_RUNLEN 0x00000F00 +#define BF_PXP_COMP_FORMAT2_C_RUNLEN(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT2_C_RUNLEN) +#define BP_PXP_COMP_FORMAT2_B_RUNLEN 4 +#define BM_PXP_COMP_FORMAT2_B_RUNLEN 0x000000F0 +#define BF_PXP_COMP_FORMAT2_B_RUNLEN(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT2_B_RUNLEN) +#define BP_PXP_COMP_FORMAT2_A_RUNLEN 0 +#define BM_PXP_COMP_FORMAT2_A_RUNLEN 0x0000000F +#define BF_PXP_COMP_FORMAT2_A_RUNLEN(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT2_A_RUNLEN) + +#define HW_PXP_COMP_MASK0 (0x00002c40) + +#define BP_PXP_COMP_MASK0_VLD_MASK_LOW 0 +#define BM_PXP_COMP_MASK0_VLD_MASK_LOW 0xFFFFFFFF +#define BF_PXP_COMP_MASK0_VLD_MASK_LOW(v) (v) + +#define HW_PXP_COMP_MASK1 (0x00002c50) + +#define BP_PXP_COMP_MASK1_VLD_MASK_HIGH 0 +#define BM_PXP_COMP_MASK1_VLD_MASK_HIGH 0xFFFFFFFF +#define BF_PXP_COMP_MASK1_VLD_MASK_HIGH(v) (v) + +#define HW_PXP_COMP_BUFFER_SIZE (0x00002c60) + +#define BP_PXP_COMP_BUFFER_SIZE_RSVD0 29 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD0 0xE0000000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD0(v) \ + (((v) << 29) & BM_PXP_COMP_BUFFER_SIZE_RSVD0) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 16 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 0x1FFF0000 +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(v) \ + (((v) << 16) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH) +#define BP_PXP_COMP_BUFFER_SIZE_RSVD1 13 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD1 0x0000E000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD1(v) \ + (((v) << 13) & BM_PXP_COMP_BUFFER_SIZE_RSVD1) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0x00001FFF +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(v) \ + (((v) << 0) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH) + +#define HW_PXP_COMP_SOURCE (0x00002c70) + +#define BP_PXP_COMP_SOURCE_SOURCE_ADDR 0 +#define BM_PXP_COMP_SOURCE_SOURCE_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_SOURCE_SOURCE_ADDR(v) (v) + +#define HW_PXP_COMP_TARGET (0x00002c80) + +#define BP_PXP_COMP_TARGET_TARGET_ADDR 0 +#define BM_PXP_COMP_TARGET_TARGET_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_TARGET_TARGET_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_A (0x00002c90) + +#define BP_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_A_A_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_B (0x00002ca0) + +#define BP_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_B_B_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_C (0x00002cb0) + +#define BP_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_C_C_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_D (0x00002cc0) + +#define BP_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_D_D_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_DEBUG (0x00002cd0) + +#define BP_PXP_COMP_DEBUG_DEBUG_VALUE 8 +#define BM_PXP_COMP_DEBUG_DEBUG_VALUE 0xFFFFFF00 +#define BF_PXP_COMP_DEBUG_DEBUG_VALUE(v) \ + (((v) << 8) & BM_PXP_COMP_DEBUG_DEBUG_VALUE) +#define BP_PXP_COMP_DEBUG_DEBUG_SEL 0 +#define BM_PXP_COMP_DEBUG_DEBUG_SEL 0x000000FF +#define BF_PXP_COMP_DEBUG_DEBUG_SEL(v) \ + (((v) << 0) & BM_PXP_COMP_DEBUG_DEBUG_SEL) + +#define HW_PXP_BUS_MUX (0x00002ce0) + +#define BP_PXP_BUS_MUX_RSVD1 24 +#define BM_PXP_BUS_MUX_RSVD1 0xFF000000 +#define BF_PXP_BUS_MUX_RSVD1(v) \ + (((v) << 24) & BM_PXP_BUS_MUX_RSVD1) +#define BP_PXP_BUS_MUX_WR_SEL 16 +#define BM_PXP_BUS_MUX_WR_SEL 0x00FF0000 +#define BF_PXP_BUS_MUX_WR_SEL(v) \ + (((v) << 16) & BM_PXP_BUS_MUX_WR_SEL) +#define BP_PXP_BUS_MUX_RSVD0 8 +#define BM_PXP_BUS_MUX_RSVD0 0x0000FF00 +#define BF_PXP_BUS_MUX_RSVD0(v) \ + (((v) << 8) & BM_PXP_BUS_MUX_RSVD0) +#define BP_PXP_BUS_MUX_RD_SEL 0 +#define BM_PXP_BUS_MUX_RD_SEL 0x000000FF +#define BF_PXP_BUS_MUX_RD_SEL(v) \ + (((v) << 0) & BM_PXP_BUS_MUX_RD_SEL) + +#define HW_PXP_HANDSHAKE_READY_MUX0 (0x00002cf0) + +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_READY_MUX1 (0x00002d00) + +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_DONE_MUX0 (0x00002d10) + +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_DONE_MUX1 (0x00002d20) + +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_CPU_FETCH (0x00002d30) +#define HW_PXP_HANDSHAKE_CPU_FETCH_SET (0x00002d34) +#define HW_PXP_HANDSHAKE_CPU_FETCH_CLR (0x00002d38) +#define HW_PXP_HANDSHAKE_CPU_FETCH_TOG (0x00002d3c) + +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY) + +#define HW_PXP_HANDSHAKE_CPU_STORE (0x00002d40) +#define HW_PXP_HANDSHAKE_CPU_STORE_SET (0x00002d44) +#define HW_PXP_HANDSHAKE_CPU_STORE_CLR (0x00002d48) +#define HW_PXP_HANDSHAKE_CPU_STORE_TOG (0x00002d4c) + +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/extcon/extcon-usb-gpio.c b/drivers/extcon/extcon-usb-gpio.c index a27d350f69e30c..d47573a31e17c8 100644 --- a/drivers/extcon/extcon-usb-gpio.c +++ b/drivers/extcon/extcon-usb-gpio.c @@ -24,10 +24,10 @@ #include #include #include -#include #include #include #include +#include #define USB_GPIO_DEBOUNCE_MS 20 /* ms */ @@ -36,7 +36,9 @@ struct usb_extcon_info { struct extcon_dev *edev; struct gpio_desc *id_gpiod; + struct gpio_desc *vbus_gpiod; int id_irq; + int vbus_irq; unsigned long debounce_jiffies; struct delayed_work wq_detcable; @@ -48,31 +50,47 @@ static const unsigned int usb_extcon_cable[] = { EXTCON_NONE, }; +/* + * "USB" = VBUS and "USB-HOST" = !ID, so we have: + * Both "USB" and "USB-HOST" can't be set as active at the + * same time so if "USB-HOST" is active (i.e. ID is 0) we keep "USB" inactive + * even if VBUS is on. + * + * State | ID | VBUS + * ---------------------------------------- + * [1] USB | H | H + * [2] none | H | L + * [3] USB-HOST | L | H + * [4] USB-HOST | L | L + * + * In case we have only one of these signals: + * - VBUS only - we want to distinguish between [1] and [2], so ID is always 1. + * - ID only - we want to distinguish between [1] and [4], so VBUS = ID. +*/ static void usb_extcon_detect_cable(struct work_struct *work) { - int id; + int id, vbus; struct usb_extcon_info *info = container_of(to_delayed_work(work), struct usb_extcon_info, wq_detcable); - /* check ID and update cable state */ - id = gpiod_get_value_cansleep(info->id_gpiod); - if (id) { - /* - * ID = 1 means USB HOST cable detached. - * As we don't have event for USB peripheral cable attached, - * we simulate USB peripheral attach here. - */ + /* check ID and VBUS and update cable state */ + id = info->id_gpiod ? + gpiod_get_value_cansleep(info->id_gpiod) : 1; + vbus = info->vbus_gpiod ? + gpiod_get_value_cansleep(info->vbus_gpiod) : id; + + /* at first we clean states which are no longer active */ + if (id) extcon_set_state_sync(info->edev, EXTCON_USB_HOST, false); - extcon_set_state_sync(info->edev, EXTCON_USB, true); - } else { - /* - * ID = 0 means USB HOST cable attached. - * As we don't have event for USB peripheral cable detached, - * we simulate USB peripheral detach here. - */ + if (!vbus) extcon_set_state_sync(info->edev, EXTCON_USB, false); + + if (!id) { extcon_set_state_sync(info->edev, EXTCON_USB_HOST, true); + } else { + if (vbus) + extcon_set_state_sync(info->edev, EXTCON_USB, true); } } @@ -101,12 +119,21 @@ static int usb_extcon_probe(struct platform_device *pdev) return -ENOMEM; info->dev = dev; - info->id_gpiod = devm_gpiod_get(&pdev->dev, "id", GPIOD_IN); - if (IS_ERR(info->id_gpiod)) { - dev_err(dev, "failed to get ID GPIO\n"); - return PTR_ERR(info->id_gpiod); + info->id_gpiod = devm_gpiod_get_optional(&pdev->dev, "id", GPIOD_IN); + info->vbus_gpiod = devm_gpiod_get_optional(&pdev->dev, "vbus", + GPIOD_IN); + + if (!info->id_gpiod && !info->vbus_gpiod) { + dev_err(dev, "failed to get gpios\n"); + return -ENODEV; } + if (IS_ERR(info->id_gpiod)) + return PTR_ERR(info->id_gpiod); + + if (IS_ERR(info->vbus_gpiod)) + return PTR_ERR(info->vbus_gpiod); + info->edev = devm_extcon_dev_allocate(dev, usb_extcon_cable); if (IS_ERR(info->edev)) { dev_err(dev, "failed to allocate extcon device\n"); @@ -119,32 +146,56 @@ static int usb_extcon_probe(struct platform_device *pdev) return ret; } - ret = gpiod_set_debounce(info->id_gpiod, - USB_GPIO_DEBOUNCE_MS * 1000); + if (info->id_gpiod) + ret = gpiod_set_debounce(info->id_gpiod, + USB_GPIO_DEBOUNCE_MS * 1000); + if (!ret && info->vbus_gpiod) + ret = gpiod_set_debounce(info->vbus_gpiod, + USB_GPIO_DEBOUNCE_MS * 1000); + if (ret < 0) info->debounce_jiffies = msecs_to_jiffies(USB_GPIO_DEBOUNCE_MS); INIT_DELAYED_WORK(&info->wq_detcable, usb_extcon_detect_cable); - info->id_irq = gpiod_to_irq(info->id_gpiod); - if (info->id_irq < 0) { - dev_err(dev, "failed to get ID IRQ\n"); - return info->id_irq; + if (info->id_gpiod) { + info->id_irq = gpiod_to_irq(info->id_gpiod); + if (info->id_irq < 0) { + dev_err(dev, "failed to get ID IRQ\n"); + return info->id_irq; + } + + ret = devm_request_threaded_irq(dev, info->id_irq, NULL, + usb_irq_handler, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + pdev->name, info); + if (ret < 0) { + dev_err(dev, "failed to request handler for ID IRQ\n"); + return ret; + } } - ret = devm_request_threaded_irq(dev, info->id_irq, NULL, - usb_irq_handler, - IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - pdev->name, info); - if (ret < 0) { - dev_err(dev, "failed to request handler for ID IRQ\n"); - return ret; + if (info->vbus_gpiod) { + info->vbus_irq = gpiod_to_irq(info->vbus_gpiod); + if (info->vbus_irq < 0) { + dev_err(dev, "failed to get VBUS IRQ\n"); + return info->vbus_irq; + } + + ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL, + usb_irq_handler, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + pdev->name, info); + if (ret < 0) { + dev_err(dev, "failed to request handler for VBUS IRQ\n"); + return ret; + } } platform_set_drvdata(pdev, info); - device_init_wakeup(dev, true); - dev_pm_set_wake_irq(dev, info->id_irq); + device_set_wakeup_capable(&pdev->dev, true); /* Perform initial detection */ usb_extcon_detect_cable(&info->wq_detcable.work); @@ -157,8 +208,6 @@ static int usb_extcon_remove(struct platform_device *pdev) struct usb_extcon_info *info = platform_get_drvdata(pdev); cancel_delayed_work_sync(&info->wq_detcable); - - dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); return 0; @@ -170,12 +219,35 @@ static int usb_extcon_suspend(struct device *dev) struct usb_extcon_info *info = dev_get_drvdata(dev); int ret = 0; + if (device_may_wakeup(dev)) { + if (info->id_gpiod) { + ret = enable_irq_wake(info->id_irq); + if (ret) + return ret; + } + if (info->vbus_gpiod) { + ret = enable_irq_wake(info->vbus_irq); + if (ret) { + if (info->id_gpiod) + disable_irq_wake(info->id_irq); + + return ret; + } + } + } + /* * We don't want to process any IRQs after this point * as GPIOs used behind I2C subsystem might not be * accessible until resume completes. So disable IRQ. */ - disable_irq(info->id_irq); + if (info->id_gpiod) + disable_irq(info->id_irq); + if (info->vbus_gpiod) + disable_irq(info->vbus_irq); + + if (!device_may_wakeup(dev)) + pinctrl_pm_select_sleep_state(dev); return ret; } @@ -185,10 +257,33 @@ static int usb_extcon_resume(struct device *dev) struct usb_extcon_info *info = dev_get_drvdata(dev); int ret = 0; - enable_irq(info->id_irq); if (!device_may_wakeup(dev)) - queue_delayed_work(system_power_efficient_wq, - &info->wq_detcable, 0); + pinctrl_pm_select_default_state(dev); + + if (device_may_wakeup(dev)) { + if (info->id_gpiod) { + ret = disable_irq_wake(info->id_irq); + if (ret) + return ret; + } + if (info->vbus_gpiod) { + ret = disable_irq_wake(info->vbus_irq); + if (ret) { + if (info->id_gpiod) + enable_irq_wake(info->id_irq); + + return ret; + } + } + } + + if (info->id_gpiod) + enable_irq(info->id_irq); + if (info->vbus_gpiod) + enable_irq(info->vbus_irq); + + queue_delayed_work(system_power_efficient_wq, + &info->wq_detcable, 0); return ret; } diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index d0e367959c916b..5d7be97777c237 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -36,7 +36,8 @@ #include #define SUPPORTED_CABLE_MAX 32 -#define CABLE_NAME_MAX 30 + +#define EMISC(_id, _name) [_id] = {.type = EXTCON_TYPE_MISC, .id = _id, .name = _name } struct __extcon_info { unsigned int type; @@ -189,7 +190,25 @@ struct __extcon_info { .id = EXTCON_MECHANICAL, .name = "MECHANICAL", }, - + EMISC(EXTCON_HV_PREPARE, "High Voltage Prepare"), + EMISC(EXTCON_HV_TA,"High Voltage TA"), + EMISC(EXTCON_HV_TA_ERR, "Error HV TA"), + EMISC(EXTCON_DESKDOCK, "Desk-dock"), + EMISC(EXTCON_DESKDOCK_VB, "Desk-dock-VB"), + EMISC(EXTCON_AUDIODOCK, "Audio-dock"), + EMISC(EXTCON_SMARTDOCK, "Smart-dock"), + EMISC(EXTCON_SMARTDOCK_TA, "Smart-dock-TA"), + EMISC(EXTCON_SMARTDOCK_USB, "Smart-dock-USB"), + EMISC(EXTCON_MULTIMEDIADOCK, "Multimedia-dock"), + EMISC(EXTCON_JIG_UARTOFF, "JIG-UART-OFF"), + EMISC(EXTCON_JIG_UARTOFF_VB, "JIG-UART-OFF-VB"), + EMISC(EXTCON_JIG_UARTON, "JIG-UART-ON"), + EMISC(EXTCON_JIG_USBOFF, "JIG-USB-OFF"), + EMISC(EXTCON_JIG_USBON, "JIG-USB-ON"), + EMISC(EXTCON_INCOMPATIBLE, "Incompatible-TA"), + EMISC(EXTCON_CHARGING_CABLE, "Charging-Cable"), + EMISC(EXTCON_HMT, "HMT"), + EMISC(EXTCON_HV_TA_1A, "High Voltage 1A Type Cable"), { /* sentinel */ } }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 12d417a4d4a854..09ab72f2ea0198 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -321,7 +321,6 @@ config GPIO_MVEBU config GPIO_MXC def_bool y - depends on ARCH_MXC select GPIO_GENERIC select GENERIC_IRQ_CHIP @@ -443,6 +442,12 @@ config GPIO_VF610 help Say yes here to support Vybrid vf610 GPIOs. +config GPIO_IMX_RPMSG + bool "NXP i.MX7ULP RPMSG GPIO support" + depends on ARCH_MXC && RPMSG && GPIOLIB + help + This driver support i.MX7ULP RPMSG virtual GPIOs. + config GPIO_VR41XX tristate "NEC VR4100 series General-purpose I/O Uint support" depends on CPU_VR41XX diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d074c2299393dc..95f52f4a97ce48 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -124,6 +124,7 @@ obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o +obj-$(CONFIG_GPIO_IMX_RPMSG) += gpio-imx-rpmsg.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index a6607faf2fdf82..fbca09c926868f 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -138,6 +138,9 @@ static int gen_74x164_probe(struct spi_device *spi) chip->registers = nregs; chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; + of_property_read_u8_array(spi->dev.of_node, "registers-default", + chip->buffer, chip->registers); + chip->gpio_chip.can_sleep = true; chip->gpio_chip.parent = &spi->dev; chip->gpio_chip.owner = THIS_MODULE; diff --git a/drivers/gpio/gpio-imx-rpmsg.c b/drivers/gpio/gpio-imx-rpmsg.c new file mode 100644 index 00000000000000..9bfd1880fc57b3 --- /dev/null +++ b/drivers/gpio/gpio-imx-rpmsg.c @@ -0,0 +1,322 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_RPMSG_GPIO_PER_PORT 32 +#define RPMSG_TIMEOUT 1000 + +enum gpio_input_trigger_type { + GPIO_RPMSG_TRI_IGNORE, + GPIO_RPMSG_TRI_RISING, + GPIO_RPMSG_TRI_FALLING, + GPIO_RPMSG_TRI_BOTH_EDGE, + GPIO_RPMSG_TRI_LOW_LEVEL, + GPIO_RPMSG_TRI_HIGH_LEVEL, +}; + +enum gpio_rpmsg_header_type { + GPIO_RPMSG_SETUP, + GPIO_RPMSG_REPLY, + GPIO_RPMSG_NOTIFY, +}; + +enum gpio_rpmsg_header_cmd { + GPIO_RPMSG_INPUT_INIT, + GPIO_RPMSG_OUTPUT_INIT, + GPIO_RPMSG_INPUT_GET, +}; + +struct gpio_rpmsg_data { + struct imx_rpmsg_head header; + u8 pin_idx; + u8 port_idx; + union { + u8 event; + u8 retcode; + u8 value; + } out; + union { + u8 wakeup; + u8 value; + } in; +} __packed __aligned(8); + +struct imx_rpmsg_gpio_port { + struct gpio_chip gc; + struct gpio_rpmsg_data msg; + int idx; +}; + +struct imx_gpio_rpmsg_info { + struct rpmsg_device *rpdev; + struct gpio_rpmsg_data *notify_msg; + struct gpio_rpmsg_data *reply_msg; + struct pm_qos_request pm_qos_req; + struct completion cmd_complete; + struct mutex lock; +}; + +static struct imx_gpio_rpmsg_info gpio_rpmsg; + +static int gpio_send_message(struct imx_rpmsg_gpio_port *port, + struct gpio_rpmsg_data *msg, struct imx_gpio_rpmsg_info *info) +{ + int err; + + if (!info->rpdev) { + dev_dbg(&info->rpdev->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + pm_qos_add_request(&info->pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct gpio_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->reply_msg->out.retcode != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->reply_msg->out.retcode); + err = -EINVAL; + goto err_out; + } + + /* copy the reply message */ + memcpy(&port->msg, info->reply_msg, sizeof(*info->reply_msg)); + + err = 0; + +err_out: + pm_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int gpio_rpmsg_cb(struct rpmsg_device *rpdev, + void *data, int len, void *priv, u32 src) +{ + struct gpio_rpmsg_data *msg = (struct gpio_rpmsg_data *)data; + + if (msg->header.type == GPIO_RPMSG_REPLY) { + gpio_rpmsg.reply_msg = msg; + complete(&gpio_rpmsg.cmd_complete); + } else if (msg->header.type == GPIO_RPMSG_NOTIFY) { + gpio_rpmsg.notify_msg = msg; + /* TBD for interrupt handler */ + } else + dev_err(&gpio_rpmsg.rpdev->dev, "wrong command type!\n"); + + return 0; +} + +static int imx_rpmsg_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + int ret; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + msg.header.cate = IMX_RPMSG_GPIO; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = GPIO_RPMSG_SETUP; + msg.header.cmd = GPIO_RPMSG_INPUT_GET; + msg.pin_idx = gpio; + msg.port_idx = port->idx; + + ret = gpio_send_message(port, &msg, &gpio_rpmsg); + if (!ret) + return !!port->msg.in.value; + + return ret; +} + +static int imx_rpmsg_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + msg.header.cate = IMX_RPMSG_GPIO; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = GPIO_RPMSG_SETUP; + msg.header.cmd = GPIO_RPMSG_INPUT_INIT; + msg.pin_idx = gpio; + msg.port_idx = port->idx; + + /* TBD: get event trigger and wakeup from GPIO descriptor */ + msg.out.event = GPIO_RPMSG_TRI_IGNORE; + msg.in.wakeup = 0; + + return gpio_send_message(port, &msg, &gpio_rpmsg); +} + +static inline void imx_rpmsg_gpio_direction_output_init(struct gpio_chip *gc, + unsigned int gpio, int val, struct gpio_rpmsg_data *msg) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_OUTPUT_INIT; + msg->pin_idx = gpio; + msg->port_idx = port->idx; + msg->out.value = val; +} + +static void imx_rpmsg_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, &msg); + gpio_send_message(port, &msg, &gpio_rpmsg); +} + +static int imx_rpmsg_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data msg; + + memset(&msg, 0, sizeof(struct gpio_rpmsg_data)); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, &msg); + return gpio_send_message(port, &msg, &gpio_rpmsg); +} + +static int gpio_rpmsg_probe(struct rpmsg_device *rpdev) +{ + gpio_rpmsg.rpdev = rpdev; + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&gpio_rpmsg.cmd_complete); + mutex_init(&gpio_rpmsg.lock); + + return 0; +} + +static struct rpmsg_device_id gpio_rpmsg_id_table[] = { + { .name = "rpmsg-io-channel" }, + {}, +}; + +static struct rpmsg_driver gpio_rpmsg_driver = { + .drv.name = "gpio_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = gpio_rpmsg_id_table, + .probe = gpio_rpmsg_probe, + .callback = gpio_rpmsg_cb, +}; + +static int imx_rpmsg_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct imx_rpmsg_gpio_port *port; + struct gpio_chip *gc; + int ret; + + port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + ret = of_property_read_u32(np, "port_idx", &port->idx); + if (ret) + return ret; + + gc = &port->gc; + gc->of_node = np; + gc->parent = dev; + gc->label = "imx-rpmsg-gpio"; + gc->ngpio = IMX_RPMSG_GPIO_PER_PORT; + gc->base = of_alias_get_id(np, "gpio") * IMX_RPMSG_GPIO_PER_PORT; + + gc->direction_input = imx_rpmsg_gpio_direction_input; + gc->direction_output = imx_rpmsg_gpio_direction_output; + gc->get = imx_rpmsg_gpio_get; + gc->set = imx_rpmsg_gpio_set; + + platform_set_drvdata(pdev, port); + + ret = devm_gpiochip_add_data(dev, gc, port); + if (ret < 0) + return ret; + + return 0; +} + +static const struct of_device_id imx_rpmsg_gpio_dt_ids[] = { + { .compatible = "fsl,imx-rpmsg-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver imx_rpmsg_gpio_driver = { + .driver = { + .name = "gpio-imx-rpmsg", + .of_match_table = imx_rpmsg_gpio_dt_ids, + }, + .probe = imx_rpmsg_gpio_probe, +}; + +static int __init gpio_imx_rpmsg_init(void) +{ + int ret; + + ret = register_rpmsg_driver(&gpio_rpmsg_driver); + if (ret) + return ret; + + return platform_driver_register(&imx_rpmsg_gpio_driver); +} +device_initcall(gpio_imx_rpmsg_init); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("NXP i.MX7ULP rpmsg gpio driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index fe731f09425712..f645dbd11e521f 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -813,6 +814,10 @@ static int pca953x_probe(struct i2c_client *client, lockdep_set_subclass(&chip->i2c_lock, i2c_adapter_depth(client->adapter)); + ret = device_reset(&client->dev); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* initialize cached registers from their original values. * we can't share this chip with another i2c master. */ diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c index 3edb09cb9ee080..68567cabcdee4c 100644 --- a/drivers/gpio/gpio-vf610.c +++ b/drivers/gpio/gpio-vf610.c @@ -43,6 +43,7 @@ struct vf610_gpio_port { #define GPIO_PCOR 0x08 #define GPIO_PTOR 0x0c #define GPIO_PDIR 0x10 +#define GPIO_PDDR 0x14 #define PORT_PCR(n) ((n) * 0x4) #define PORT_PCR_IRQC_OFFSET 16 @@ -79,8 +80,16 @@ static inline u32 vf610_gpio_readl(void __iomem *reg) static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) { struct vf610_gpio_port *port = gpiochip_get_data(gc); + unsigned long mask = BIT(gpio); + + mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); - return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) & BIT(gpio)); + if (mask) + return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDOR) + & BIT(gpio)); + else + return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) + & BIT(gpio)); } static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) @@ -88,6 +97,8 @@ static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) struct vf610_gpio_port *port = gpiochip_get_data(gc); unsigned long mask = BIT(gpio); + vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR); + if (val) vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR); else @@ -96,6 +107,13 @@ static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { + struct vf610_gpio_port *port = gpiochip_get_data(chip); + unsigned long mask = BIT(gpio); + u32 val; + + val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); + val &= ~mask; + vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); return pinctrl_gpio_direction_input(chip->base + gpio); } @@ -262,6 +280,14 @@ static int vf610_gpio_probe(struct platform_device *pdev) /* Clear the interrupt status register for all GPIO's */ vf610_gpio_writel(~0, port->base + PORT_ISFR); + /* + * At imx7ulp, any interrupts can wake system up from "standby" mode, + * so, mask interrupt at suspend mode by default, and the user + * can still enable wakeup through /sys entry. + */ + if (of_machine_is_compatible("fsl,imx7ulp")) + vf610_gpio_irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; + ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0, handle_edge_irq, IRQ_TYPE_NONE); if (ret) { diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 483059a22b1b71..3409a59d1fdb05 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -160,6 +160,12 @@ config DRM_VGEM as used by Mesa's software renderer for enhanced performance. If M is selected the module will be called vgem. +config DRM_VIVANTE + tristate "Vivante GCCore" + depends on DRM + help + Choose this option if you have a Vivante graphics card. + If M is selected, the module will be called vivante. source "drivers/gpu/drm/exynos/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 25c720454017e6..e9682a2fc9ad3c 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_DRM) += drm.o obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o obj-$(CONFIG_DRM_ARM) += arm/ obj-$(CONFIG_DRM_TTM) += ttm/ +obj-$(CONFIG_DRM_VIVANTE) += vivante/ obj-$(CONFIG_DRM_TDFX) += tdfx/ obj-$(CONFIG_DRM_R128) += r128/ obj-$(CONFIG_HSA_AMD) += amd/amdkfd/ diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig index 2cde7a5442fb3f..566ed6deb9b4f5 100644 --- a/drivers/gpu/drm/etnaviv/Kconfig +++ b/drivers/gpu/drm/etnaviv/Kconfig @@ -3,6 +3,7 @@ config DRM_ETNAVIV tristate "ETNAVIV (DRM support for Vivante GPU IP cores)" depends on DRM depends on ARCH_MXC || ARCH_DOVE + depends on !MXC_USE_VENDOR_DRIVERS select SHMEM select TMPFS select IOMMU_API diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c index 3ce391c239b02a..6c764a9a10b954 100644 --- a/drivers/gpu/drm/imx/imx-ldb.c +++ b/drivers/gpu/drm/imx/imx-ldb.c @@ -247,8 +247,9 @@ static void imx_ldb_encoder_enable(struct drm_encoder *encoder) else if (imx_ldb_ch == &ldb->channel[1]) lvds_mux = &ldb->lvds_mux[1]; - regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, - mux << lvds_mux->shift); + if (lvds_mux) + regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, + mux << lvds_mux->shift); } regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); @@ -270,6 +271,12 @@ imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder, int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); u32 bus_format = imx_ldb_ch->bus_format; + if (mux < 0) { + dev_warn(ldb->dev, + "%s: cannot get valid mux id\n", __func__); + return; + } + if (mode->clock > 170000) { dev_warn(ldb->dev, "%s: mode exceeds 170 MHz pixel clock\n", __func__); @@ -436,7 +443,7 @@ static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) { char clkname[16]; - snprintf(clkname, sizeof(clkname), "di%d", chno); + snprintf(clkname, sizeof(clkname), "ldb_di%d", chno); ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); if (IS_ERR(ldb->clk[chno])) return PTR_ERR(ldb->clk[chno]); diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 62aba976e744c1..5dc2106da2bc0d 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -7,6 +7,16 @@ config DRM_PANEL menu "Display Panels" depends on DRM && DRM_PANEL +config DRM_PANEL_LVDS + tristate "Generic LVDS panel driver" + depends on OF + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + This driver supports LVDS panels that don't require device-specific + handling of power supplies or control signals. It implements automatic + backlight handling if the panel is attached to a backlight controller. + config DRM_PANEL_SIMPLE tristate "support for simple panels" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index a5c7ec0236e017..20b5060d1f47cb 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o diff --git a/drivers/gpu/drm/panel/panel-lvds.c b/drivers/gpu/drm/panel/panel-lvds.c new file mode 100644 index 00000000000000..3216aa9a88d6c2 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-lvds.c @@ -0,0 +1,286 @@ +/* + * rcar_du_crtc.c -- R-Car Display Unit CRTCs + * + * Copyright (C) 2016 Laurent Pinchart + * Copyright (C) 2016 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include