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XiangShan

XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此。

Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.

Copyright 2020-2022 by Peng Cheng Laboratory.

Docs and slides

XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.

Follow us

Wechat/微信：香山开源处理器

Zhihu/知乎：香山开源处理器

Weibo/微博：香山开源处理器

You can contact us through our mail list. All mails from this list will be archived to here.

Architecture

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this branch, which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the main branch. Present version of Nanhu is V3.

The micro-architecture overview of Nanhu-V3 (南湖V3) is shown below.

xs-arch-nanhu

Sub-directories Overview

Some of the key directories are shown below.

.
├── src
│   └── main/scala         # design files
│       ├── device         # virtual device for simulation
│       ├── system         # SoC wrapper
│       ├── top            # top module
│       ├── utils          # utilization code
│       ├── xiangshan      # main design code
│       └── xstransforms   # some useful firrtl transforms
├── scripts                # scripts for agile development
├── fudian                 # floating unit submodule of XiangShan
├── huancun                # L2/L3 cache submodule of XiangShan
├── difftest               # difftest co-simulation framework
└── ready-to-run           # pre-built simulation images

IDE Support

bsp

make bsp

IDEA

make idea

Generate Verilog

  • Run make verilog to generate verilog code. The output file is build/XSTop.v.
  • Refer to Makefile for more information.

Run Programs by Simulation

Prepare environment

  • Set environment variable NEMU_HOME to the absolute path of the NEMU project.
  • Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
  • Set environment variable AM_HOME to the absolute path of the AM project.
  • Install mill. Refer to the Manual section in this guide.
  • Clone this project and run make init to initialize submodules.

Run with simulator

  • Install Verilator, the open-source Verilog simulator.
  • Run make emu_rtl to build the C++ simulator ./sim/emu/comp/emu with Verilator.
  • Refer to ./sim/emu/comp/emu --help for run-time arguments of the simulator.
  • Refer to Makefile and verilator.mk for more information.

Example:

make emu_rtl -j32
make emu_rtl-run RUN_BIN=coremark-3-iteration.bin

Troubleshooting Guide

Troubleshooting Guide

Acknowledgement

In the development of XiangShan, some components from the open-source community are employed. All relevant usage is listed below.

Sub-module Source Detail
L2 Cache/LLC Sifive block-inclusivecache Our new L2/L3 design are inspired by Sifive's block-inclusivecache.
Diplomacy/TileLink Rocket-chip We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus.
Vector Function Unit riscv-vector We reused vector function units in Intel's VPU

We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.