diff --git a/drivers/dma/dma_silabs_siwx917.c b/drivers/dma/dma_silabs_siwx917.c index 9b27d87..5f4d8dc 100644 --- a/drivers/dma/dma_silabs_siwx917.c +++ b/drivers/dma/dma_silabs_siwx917.c @@ -32,19 +32,19 @@ LOG_MODULE_REGISTER(si91x_dma, CONFIG_DMA_LOG_LEVEL); -static RSI_UDMA_HANDLE_T siwx917_udma_handle[2]; // Structure to store udma handles for UDMA0 and - // UDMA1(ULP_UDMA) +static RSI_UDMA_HANDLE_T siwx917_udma_handle[2]; /* Structure to store udma handles for UDMA0 and + UDMA1(ULP_UDMA) */ struct dma_siwx917_config { - UDMA0_Type *reg; // UDMA register base address - uint8_t channels; // UDMA channel count - void (*irq_configure)(void); // IRQ configure function + UDMA0_Type *reg; /* UDMA register base address */ + uint8_t channels; /* UDMA channel count */ + void (*irq_configure)(void); /* IRQ configure function */ }; struct dma_siwx917_data { - UDMA_Channel_Info siwx917_udma_channel_info; // UDMA channel info - dma_callback_t dma_callback; // User callback - void *cb_data; // User callback data + UDMA_Channel_Info siwx917_udma_channel_info; /* UDMA channel info */ + dma_callback_t dma_callback; /* User callback */ + void *cb_data; /* User callback data */ }; /*Function to validate and convert channel priority for sl layer usage*/ @@ -68,11 +68,11 @@ static inline int siwx917_dma_transfer_direction(uint32_t dir) { switch (dir) { case 0: - return PERIPHERAL_REQUEST_DISABLE; // Memory to Memory transfer + return PERIPHERAL_REQUEST_DISABLE; /* Memory to Memory transfer */ case 1: - return PERIPHERAL_REQUEST_ENABLE; // Memory to Peripheral transfer + return PERIPHERAL_REQUEST_ENABLE; /* Memory to Peripheral transfer */ case 2: - return PERIPHERAL_REQUEST_ENABLE; // Peripheral to Memory transfer + return PERIPHERAL_REQUEST_ENABLE; /* Peripheral to Memory transfer */ default: printf("Invalid Transfer direction - must be,\n \ memory-memory (0)\n \ @@ -88,11 +88,11 @@ static inline int siwx917_dma_data_width(uint32_t data_width) { switch (data_width) { case 1: - return SL_TRANSFER_SIZE_8; // 8-bit width + return SL_TRANSFER_SIZE_8; /* 8-bit width */ case 2: - return SL_TRANSFER_SIZE_16; // 16-bit width + return SL_TRANSFER_SIZE_16; /* 16-bit width */ case 4: - return SL_TRANSFER_SIZE_32; // 32-bit width + return SL_TRANSFER_SIZE_32; /* 32-bit width */ default: printf("Invalid Source/Destination data size - must be,\n \ 8-bit (1)\n \ @@ -123,9 +123,9 @@ static inline int siwx917_dma_addr_adjustment(uint32_t adjustment) { switch (adjustment) { case 0: - break; // Addr Increment + break; /* Addr Increment */ case 2: - return UDMA_ADDR_INC_NONE; // No Address increment + return UDMA_ADDR_INC_NONE; /* No Address increment */ default: printf("Invalid Source/Destination Addr adjustment - must be,\n \ Increment (0)\n \ @@ -140,28 +140,28 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, struct dma_config *config) { - // Fetch DMA config and data structures from device. + /* Fetch DMA config and data structures from device. */ const struct dma_siwx917_config *cfg = dev->config; struct dma_siwx917_data *data = dev->data; uint32_t dma_instance; sl_status_t status = SL_STATUS_OK; UDMA_RESOURCES UDMA_Resources; - static UDMA_Channel_Info channel_info[32]; // channel info structure to temporarily hold the - // channel data. + static UDMA_Channel_Info channel_info[32]; /* channel info structure to temporarily hold the + channel data. */ uint32_t rsi_channel = channel - 1; if (cfg->reg == UDMA0) { - dma_instance = UDMA0_INSTANCE; // udma0 - // Expecting a fixed channel number between 1-32 + dma_instance = UDMA0_INSTANCE; /* udma0 */ + /* Expecting a fixed channel number between 1-32 */ if ((channel > CHANNEL_32) || (channel == 0)) { return -EINVAL; } else { UDMA_Resources.udma_irq_num = UDMA0_IRQn; } } else if (cfg->reg == UDMA1) { - dma_instance = ULP_UDMA_INSTANCE; // ulp_udma - // Expecting a fixed channel number between 1-12 + dma_instance = ULP_UDMA_INSTANCE; /* ulp_udma */ + /* Expecting a fixed channel number between 1-12 */ if ((channel > CHANNEL_12) || (channel == 0)) { return -EINVAL; } else { @@ -171,26 +171,26 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, return -EINVAL; } - UDMA_Resources.reg = cfg->reg; // UDMA register base address + UDMA_Resources.reg = cfg->reg; /* UDMA register base address */ UDMA_Resources.desc = (RSI_UDMA_DESC_T *) - cfg->reg->CTRL_BASE_PTR; // SRAM address where UDMA descriptor is stored + cfg->reg->CTRL_BASE_PTR; /* SRAM address where UDMA descriptor is stored */ - // Disable the channel before configuring + /* Disable the channel before configuring */ if (sl_si91x_dma_channel_disable(dma_instance, channel) != SL_STATUS_OK) { return -EINVAL; } - // Validate the priority + /* Validate the priority */ if (siwx917_dma_priority(config->channel_priority) < 0) { return -EINVAL; } - // Allocate the channel for transfer + /* Allocate the channel for transfer */ status = sl_si91x_dma_allocate_channel(dma_instance, &channel, siwx917_dma_priority(config->channel_priority)); if ((status != SL_STATUS_OK) && (status != SL_STATUS_DMA_CHANNEL_ALLOCATED)) { - // Channel is not available for transfer + /* Channel is not available for transfer */ return -ECANCELED; } @@ -209,32 +209,32 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, channel_config.burstReq = BURST_REQUEST_DISABLE; if (channel_config.periphReq) { - // Arbitration power for peripheral<->memory transfers + /* Arbitration power for peripheral<->memory transfers */ channel_control.rPower = ARBSIZE_1; } else { - // Arbitration power for mem-mem transfers + /* Arbitration power for mem-mem transfers */ channel_control.rPower = ARBSIZE_1024; } channel_control.transferType = SL_DMA_BASIC_MODE; channel_control.nextBurst = NEXT_BURST_DISABLE; channel_control.srcProtCtrl = SOURCE_PROTECT_CONTROL_DISABLE; channel_control.dstProtCtrl = DESTINATION_PROTECT_CONTROL_DISABLE; - // Obtain the number of transfers + /* Obtain the number of transfers */ config->head_block->block_size /= config->source_data_size; if (config->head_block->block_size >= DMA_MAX_TRANSFER_COUNT) { - // Maximum number of transfers is 1024 + /* Maximum number of transfers is 1024 */ channel_control.totalNumOfDMATrans = (DMA_MAX_TRANSFER_COUNT - 1); } else { channel_control.totalNumOfDMATrans = config->head_block->block_size; } - // Validate source and data sizes + /* Validate source and data sizes */ if ((siwx917_dma_data_width(config->source_data_size) < 0) || (siwx917_dma_data_width(config->dest_data_size) < 0)) { return -EINVAL; } - // Validate burst length + /* Validate burst length */ if ((siwx917_dma_burst_length(config->source_burst_length >> 3) < 0) || (siwx917_dma_burst_length(config->dest_burst_length >> 3) < 0)) { return -EINVAL; @@ -243,12 +243,12 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, channel_control.srcSize = siwx917_dma_data_width(config->source_data_size); channel_control.dstSize = siwx917_dma_data_width(config->dest_data_size); - // Validate the addr increment value + /* Validate the addr increment value */ if ((siwx917_dma_addr_adjustment(config->head_block->source_addr_adj) < 0) || (siwx917_dma_addr_adjustment(config->head_block->dest_addr_adj) < 0)) { return -EINVAL; } - // Update source and destination addr increment values + /* Update source and destination addr increment values */ if (siwx917_dma_addr_adjustment(config->head_block->source_addr_adj) == 0) { channel_control.srcInc = channel_control.srcSize; } else { @@ -260,7 +260,7 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, channel_control.dstInc = UDMA_DST_INC_NONE; } - // Configure dma channel for transfer + /* Configure dma channel for transfer */ status = (sl_status_t)UDMAx_ChannelConfigure( &UDMA_Resources, (uint8_t)rsi_channel, (uint32_t)(config->head_block->source_address), @@ -268,7 +268,7 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, channel_control, &channel_config, NULL, channel_info, siwx917_udma_handle[dma_instance]); - // Now store the channel info data to dev->data structure. + /* Now store the channel info data to dev->data structure. */ data[rsi_channel].dma_callback = config->dma_callback; data[rsi_channel].cb_data = config->user_data; data[rsi_channel].siwx917_udma_channel_info.Cnt = channel_info[rsi_channel].Cnt; @@ -282,7 +282,7 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst, size_t size) { - // Fetch DMA config and data structures from device. + /* Fetch DMA config and data structures from device. */ const struct dma_siwx917_config *cfg = dev->config; struct dma_siwx917_data *data = dev->data; @@ -293,14 +293,14 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 RSI_UDMA_DESC_T *UDMA_Table; if (cfg->reg == UDMA0) { - // Expecting a fixed channel number between 1-32 + /* Expecting a fixed channel number between 1-32 */ if ((channel > CHANNEL_32) || (channel == 0)) { return -EINVAL; } else { dma_instance = UDMA0_INSTANCE; } } else if (cfg->reg == UDMA1) { - // Expecting a fixed channel number between 1-12 + /* Expecting a fixed channel number between 1-12 */ if ((channel > CHANNEL_12) || (channel == 0)) { return -EINVAL; } else { @@ -310,27 +310,27 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 return -EINVAL; } - UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); // Fetch the SRAM address where - // UDMA descriptor is stored + UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); /* Fetch the SRAM address where + UDMA descriptor is stored */ - // Check if the channel is already allocated (this fucntion is not used for - // configuring new channels) + /* Check if the channel is already allocated (this fucntion is not used for + configuring new channels) */ if (sl_si91x_dma_channel_status_get(dma_instance, channel) != SL_STATUS_DMA_CHANNEL_ALLOCATED) { return -ECANCELED; } - // Disable the channel before reloading transfer + /* Disable the channel before reloading transfer */ if (sl_si91x_dma_channel_disable(dma_instance, channel) != SL_STATUS_OK) { return -ECANCELED; } - // Update new channel info to dev->data structure + /* Update new channel info to dev->data structure */ data[rsi_channel].siwx917_udma_channel_info.SrcAddr = src; data[rsi_channel].siwx917_udma_channel_info.DestAddr = dst; data[rsi_channel].siwx917_udma_channel_info.Size = size; - // Update new transfer size to dev->data structure + /* Update new transfer size to dev->data structure */ if (size >= DMA_MAX_TRANSFER_COUNT) { data[rsi_channel].siwx917_udma_channel_info.Cnt = (DMA_MAX_TRANSFER_COUNT - 1); } else { @@ -338,7 +338,7 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 } uint32_t length; - // Program the DMA descriptors with new transfer data information. + /* Program the DMA descriptors with new transfer data information. */ if (UDMA_Table[rsi_channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) { length = (data[rsi_channel].siwx917_udma_channel_info.Cnt) << UDMA_Table[rsi_channel].vsUDMAChaConfigData1.srcInc; @@ -361,28 +361,28 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 /*Function to start a DMA transfer*/ static int dma_siwx917_start(const struct device *dev, uint32_t channel) { - // Fetch DMA config structure from device. + /* Fetch DMA config structure from device. */ const struct dma_siwx917_config *cfg = dev->config; uint32_t rsi_channel = channel - 1; RSI_UDMA_DESC_T *UDMA_Table; if (cfg->reg == UDMA0) { - // Expecting a fixed channel number between 1-32 + /* Expecting a fixed channel number between 1-32 */ if ((channel > CHANNEL_32) || (channel == 0)) { return -EINVAL; } else { - // Enable UDMA0 channel + /* Enable UDMA0 channel */ if (sl_si91x_dma_channel_enable(UDMA0_INSTANCE, channel) != SL_STATUS_OK) { return -EINVAL; } } } else if (cfg->reg == UDMA1) { - // Expecting a fixed channel number between 1-12 + /* Expecting a fixed channel number between 1-12 */ if ((channel > 12) || (channel == 0)) { return -EINVAL; } else { - // Enable ULP_DMA/UDMA1 channel + /* Enable ULP_DMA/UDMA1 channel */ if (sl_si91x_dma_channel_enable(ULP_UDMA_INSTANCE, channel) != SL_STATUS_OK) { return -EINVAL; @@ -392,13 +392,13 @@ static int dma_siwx917_start(const struct device *dev, uint32_t channel) return -EINVAL; } - UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); // Fetch the SRAM address where - // UDMA descriptor is stored + UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); /* Fetch the SRAM address where + UDMA descriptor is stored */ - // Check if the transfer type is memory-memory + /* Check if the transfer type is memory-memory */ if ((UDMA_Table[rsi_channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) && (UDMA_Table[rsi_channel].vsUDMAChaConfigData1.dstInc != UDMA_DST_INC_NONE)) { - // Apply software trigger to start transfer + /* Apply software trigger to start transfer */ cfg->reg->CHNL_SW_REQUEST |= SET_BIT(rsi_channel); } return 0; @@ -407,25 +407,25 @@ static int dma_siwx917_start(const struct device *dev, uint32_t channel) /*Function to stop a DMA transfer*/ static int dma_siwx917_stop(const struct device *dev, uint32_t channel) { - // Fetch DMA config structure from device. + /* Fetch DMA config structure from device. */ const struct dma_siwx917_config *cfg = dev->config; if (cfg->reg == UDMA0) { - // Expecting a fixed channel number between 1-32 + /* Expecting a fixed channel number between 1-32 */ if ((channel > CHANNEL_32) || (channel == 0)) { return -EINVAL; } else { - // Disable UDMA0 channel + /* Disable UDMA0 channel */ if (sl_si91x_dma_channel_disable(UDMA0_INSTANCE, channel) != SL_STATUS_OK) { return -EINVAL; } } } else if (cfg->reg == UDMA1) { - // Expecting a fixed channel number between 1-12 + /* Expecting a fixed channel number between 1-12 */ if ((channel > CHANNEL_12) || (channel == 0)) { return -EINVAL; } else { - // Disable ULP_DMA/UDMA1 channel + /* Disable ULP_DMA/UDMA1 channel */ if (sl_si91x_dma_channel_disable(ULP_UDMA_INSTANCE, channel) != SL_STATUS_OK) { return -EINVAL; @@ -442,18 +442,18 @@ static int dma_siwx917_stop(const struct device *dev, uint32_t channel) static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, struct dma_status *stat) { - // Fetch DMA config structure from device. + /* Fetch DMA config structure from device. */ const struct dma_siwx917_config *cfg = dev->config; uint32_t rsi_channel = channel - 1; RSI_UDMA_DESC_T *UDMA_Table; if (cfg->reg == UDMA0) { - // Expecting a fixed channel number between 1-32 + /* Expecting a fixed channel number between 1-32 */ if ((channel > CHANNEL_32) || (channel == 0)) { return -EINVAL; } else { - // UDMA0 channel status + /* UDMA0 channel status */ if (sl_si91x_dma_channel_status_get(UDMA0_INSTANCE, channel) == SL_STATUS_BUSY) { stat->busy = 1; @@ -462,11 +462,11 @@ static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, } } } else if (cfg->reg == UDMA1) { - // Expecting a fixed channel number between 1-12 + /* Expecting a fixed channel number between 1-12 */ if ((channel > CHANNEL_12) || (channel == 0)) { return -EINVAL; } else { - // ULP_DMA/UDMA1 channel status + /* ULP_DMA/UDMA1 channel status */ if (sl_si91x_dma_channel_status_get(ULP_UDMA_INSTANCE, channel) == SL_STATUS_BUSY) { stat->busy = 1; @@ -478,10 +478,10 @@ static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, return -EINVAL; } - UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); // Fetch the SRAM address where - // UDMA descriptor is stored + UDMA_Table = (RSI_UDMA_DESC_T *)(cfg->reg->CTRL_BASE_PTR); /* Fetch the SRAM address where + UDMA descriptor is stored */ - // Obtain the transfer direction from channel descriptors + /* Obtain the transfer direction from channel descriptors */ if (UDMA_Table[rsi_channel].vsUDMAChaConfigData1.srcInc == UDMA_SRC_INC_NONE) { stat->dir = PERIPHERAL_TO_MEMORY; } else if (UDMA_Table[rsi_channel].vsUDMAChaConfigData1.dstInc == UDMA_DST_INC_NONE) { @@ -495,7 +495,7 @@ static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, /*Function to initialize DMA peripheral*/ static int dma_siwx917_init(const struct device *dev) { - // Fetch DMA config structure from device. + /* Fetch DMA config structure from device. */ const struct dma_siwx917_config *cfg = dev->config; sl_dma_init_t dma_init; @@ -509,18 +509,18 @@ static int dma_siwx917_init(const struct device *dev) return -EINVAL; } - // Initialize DMA peripheral. + /* Initialize DMA peripheral. */ status = sl_si91x_dma_init(&dma_init); if (status != SL_STATUS_OK) { return -ECANCELED; } - // Store the UDMA handle + /* Store the UDMA handle */ siwx917_udma_handle[dma_init.dma_number] = dma_init.udma_handle; - // Connect the DMA interrupt + /* Connect the DMA interrupt */ cfg->irq_configure(); - // Enable UDMA instance + /* Enable UDMA instance */ if (sl_si91x_dma_enable(dma_init.dma_number) != SL_STATUS_OK) { return -EBUSY; } @@ -529,7 +529,7 @@ static int dma_siwx917_init(const struct device *dev) static void dma_siwx917_isr(const struct device *dev) { - // Fetch DMA config and data structures from device. + /* Fetch DMA config and data structures from device. */ const struct dma_siwx917_config *cfg = dev->config; struct dma_siwx917_data *data = dev->data; uint32_t irq_number; @@ -539,23 +539,23 @@ static void dma_siwx917_isr(const struct device *dev) } else { irq_number = UDMA0_IRQn; } - // Disable IRQ + /* Disable IRQ */ irq_disable(irq_number); uint8_t channel; uint32_t int_status; uint8_t soft_trig_flag = 0; uint8_t transfer_complete = 0; - int_status = cfg->reg->UDMA_DONE_STATUS_REG; // Read the interrupt status - // Initialize UDMA Resources + int_status = cfg->reg->UDMA_DONE_STATUS_REG; /* Read the interrupt status */ + /* Initialize UDMA Resources */ UDMA_RESOURCES UDMA_Siwx917_Resources = { cfg->reg, irq_number, - (RSI_UDMA_DESC_T *)cfg->reg->CTRL_BASE_PTR // SRAM base address + (RSI_UDMA_DESC_T *)cfg->reg->CTRL_BASE_PTR /* SRAM base address */ }; - // Identify the interrupt channel + /* Identify the interrupt channel */ for (channel = 0; channel < cfg->channels; channel++) { if (int_status & (1U << channel)) { - // Copy channel info to channel_info[]. + /* Copy channel info to channel_info[]. */ channel_info[channel].Cnt = data[channel].siwx917_udma_channel_info.Cnt; channel_info[channel].DestAddr = data[channel].siwx917_udma_channel_info.DestAddr; @@ -563,17 +563,17 @@ static void dma_siwx917_isr(const struct device *dev) channel_info[channel].SrcAddr = data[channel].siwx917_udma_channel_info.SrcAddr; if (channel_info[channel].Cnt != channel_info[channel].Size) { - // Check if the transfer type is memory-memory + /* Check if the transfer type is memory-memory */ if ((UDMA_Siwx917_Resources.desc[channel] .vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) && (UDMA_Siwx917_Resources.desc[channel] .vsUDMAChaConfigData1.dstInc != UDMA_DST_INC_NONE)) { - // Need to apply a software trigger later + /* Need to apply a software trigger later */ soft_trig_flag = 1; } if ((channel_info[channel].Size - channel_info[channel].Cnt) > DMA_MAX_TRANSFER_COUNT) { - // Update dev->data with latest transfer count. + /* Update dev->data with latest transfer count. */ data[channel].siwx917_udma_channel_info.Cnt += DMA_MAX_TRANSFER_COUNT; } else { @@ -587,23 +587,23 @@ static void dma_siwx917_isr(const struct device *dev) break; } } - // Call UDMA ROM IRQ handler. + /* Call UDMA ROM IRQ handler. */ ROMAPI_UDMA_WRAPPER_API->uDMAx_IRQHandler(&UDMA_Siwx917_Resources, UDMA_Siwx917_Resources.desc, channel_info); if (soft_trig_flag) { - // Set the software trigger bit for starting next transfer + /* Set the software trigger bit for starting next transfer */ cfg->reg->CHNL_SW_REQUEST |= (1U << channel); } if ((data[channel].dma_callback != NULL) && transfer_complete) { - // Transfer complete, call user callback + /* Transfer complete, call user callback */ data[channel].dma_callback(dev, data[channel].cb_data, channel + 1, 0); } - // Enable IRQ + /* Enable IRQ */ irq_enable(irq_number); } -// Store the Si91x DMA APIs +/* Store the Si91x DMA APIs */ static const struct dma_driver_api siwx917_dma_driver_api = { .config = dma_siwx917_configure, .reload = dma_siwx917_reload, diff --git a/tests/drivers/dma/udma_tests/src/main.c b/tests/drivers/dma/udma_tests/src/main.c index 52eefa4..1b8af29 100644 --- a/tests/drivers/dma/udma_tests/src/main.c +++ b/tests/drivers/dma/udma_tests/src/main.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include