diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h b/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h deleted file mode 100644 index 8bd20f97e9..0000000000 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_ulp_uart_config.h - * @brief SL ULP UART Config. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_ULP_UART_CONFIG_H -#define SL_SI91X_ULP_UART_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_si91x_usart.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// ULP UART UC Configuration -// Enable: Peripheral configuration is taken straight from the configuration set in the universal configuration (UC). -// Disable: If the application demands it to be modified during runtime, use the sl_si91x_uart_set_configuration API to modify the peripheral configuration. -// Default: 1 -#define ULP_UART_UC 1 -#define ULPUART_MODULE 2 - -// UART Configuration -#define ENABLE 1 -#define DISABLE 0 - -#if (ULP_UART_UC) -// Baud Rate (Baud/Second) <300-7372800> -// Default: 115200 -#define SL_ULP_UART_BAUDRATE 115200 - -// Parity -// No Parity -// Even -// Odd -// Default: SL_USART_NO_PARITY -#define SL_ULP_UART_PARITY SL_USART_NO_PARITY - -// Stop Bits -// 1 -// 1.5 -// 2 -// Default: USART_STOP_BITS_1 -#define SL_ULP_UART_STOP_BITS SL_USART_STOP_BITS_1 - -// Data Width -// 5 -// 6 -// 7 -// 8 -// Default: USART_DATA_BITS_8 -#define SL_ULP_UART_DATA_BITS SL_USART_DATA_BITS_8 - -// Flow control -// None -// Default: USART_FLOW_CONTROL_NONE -#define SL_ULP_UART_FLOW_CONTROL_TYPE SL_USART_FLOW_CONTROL_NONE -#endif - -// ULP_UART Configuration -// - -#ifdef __cplusplus -} -#endif -// <<< end of configuration section >>> - -#if (ULP_UART_UC) -sl_si91x_usart_control_config_t ulp_uart_configuration = { .baudrate = SL_ULP_UART_BAUDRATE, - .mode = SL_USART_MODE_ASYNCHRONOUS, - .parity = SL_ULP_UART_PARITY, - .stopbits = SL_ULP_UART_STOP_BITS, - .hwflowcontrol = SL_ULP_UART_FLOW_CONTROL_TYPE, - .databits = SL_ULP_UART_DATA_BITS, - .usart_module = ULPUART_MODULE }; - -#endif //ULP_UART_UC -#endif //SL_SI91X_UART_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_config.h b/matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_config.h deleted file mode 100644 index 8bd20f97e9..0000000000 --- a/matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_ulp_uart_config.h - * @brief SL ULP UART Config. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_ULP_UART_CONFIG_H -#define SL_SI91X_ULP_UART_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_si91x_usart.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// ULP UART UC Configuration -// Enable: Peripheral configuration is taken straight from the configuration set in the universal configuration (UC). -// Disable: If the application demands it to be modified during runtime, use the sl_si91x_uart_set_configuration API to modify the peripheral configuration. -// Default: 1 -#define ULP_UART_UC 1 -#define ULPUART_MODULE 2 - -// UART Configuration -#define ENABLE 1 -#define DISABLE 0 - -#if (ULP_UART_UC) -// Baud Rate (Baud/Second) <300-7372800> -// Default: 115200 -#define SL_ULP_UART_BAUDRATE 115200 - -// Parity -// No Parity -// Even -// Odd -// Default: SL_USART_NO_PARITY -#define SL_ULP_UART_PARITY SL_USART_NO_PARITY - -// Stop Bits -// 1 -// 1.5 -// 2 -// Default: USART_STOP_BITS_1 -#define SL_ULP_UART_STOP_BITS SL_USART_STOP_BITS_1 - -// Data Width -// 5 -// 6 -// 7 -// 8 -// Default: USART_DATA_BITS_8 -#define SL_ULP_UART_DATA_BITS SL_USART_DATA_BITS_8 - -// Flow control -// None -// Default: USART_FLOW_CONTROL_NONE -#define SL_ULP_UART_FLOW_CONTROL_TYPE SL_USART_FLOW_CONTROL_NONE -#endif - -// ULP_UART Configuration -// - -#ifdef __cplusplus -} -#endif -// <<< end of configuration section >>> - -#if (ULP_UART_UC) -sl_si91x_usart_control_config_t ulp_uart_configuration = { .baudrate = SL_ULP_UART_BAUDRATE, - .mode = SL_USART_MODE_ASYNCHRONOUS, - .parity = SL_ULP_UART_PARITY, - .stopbits = SL_ULP_UART_STOP_BITS, - .hwflowcontrol = SL_ULP_UART_FLOW_CONTROL_TYPE, - .databits = SL_ULP_UART_DATA_BITS, - .usart_module = ULPUART_MODULE }; - -#endif //ULP_UART_UC -#endif //SL_SI91X_UART_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/RTE_Components.h b/matter/si91x/siwx917/BRD4343A/autogen/RTE_Components.h new file mode 100644 index 0000000000..4412235e51 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/RTE_Components.h @@ -0,0 +1,33 @@ +// This file is autogenerated by Simplicity Configuration Tools. +// The contents of this file will be replaced in their entirety upon +// regeneration. +// +// Source template file: RTE_Components.h.jinja + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + +#define RTE_RTOS_FreeRTOS_CORE + +#define RTE_RTOS_FreeRTOS_CONFIG_RTOS2 + +#define RTE_RTOS_FreeRTOS_COROUTINE + +#define RTE_RTOS_FreeRTOS_EVENTGROUPS + +#define RTE_RTOS_FreeRTOS_TIMERS + +#define RTE_RTOS_FreeRTOS_HEAP_3 + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Simplicity Configuration Tools. */ +/* The contents of this file will be replaced in their entirety upon + * regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_component_catalog.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_component_catalog.h new file mode 100644 index 0000000000..d5ff2c9163 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_component_catalog.h @@ -0,0 +1,35 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_BTN0_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN0_PRESENT +#define SL_CATALOG_BTN1_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT +#define SL_CATALOG_LED0_PRESENT +#define SL_CATALOG_SIMPLE_LED_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT +#define SL_CATALOG_LED1_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED1_PRESENT +#define SL_CATALOG_ULP_TIMER_PRESENT +#define SL_CATALOG_ULP_TIMER_TIMER0_PRESENT +#define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_FREERTOS_KERNEL_PRESENT +#define SL_CATALOG_KERNEL_PRESENT +#define SL_CATALOG_IOSTREAM_PRESENT +#define SL_CATALOG_MEMORY_MANAGER_PRESENT +#define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_SEGGER_RTT_PRESENT +#if defined(DISPLAY_ENABLED) || defined(SL_ICD_ENABLED) +#define SL_CATALOG_SLEEPTIMER_PRESENT +#ifdef DISPLAY_ENABLED +#define SL_CATALOG_DMD_MEMLCD_PRESENT +#define SL_CATALOG_GLIB_PRESENT +#endif // DISPLAY_ENABLED +#endif // DISPLAY_ENABLED || SL_ICD_ENABLED + +#endif // SL_COMPONENT_CATALOG_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.c new file mode 100644 index 0000000000..9d46be388e --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.c @@ -0,0 +1,70 @@ +#include "sl_event_handler.h" + +#include "system_si91x.h" +#include "rsi_nvic_priorities_config.h" +#include "sli_siwx917_soc.h" +#include "rsi_board.h" +#include "rsi_debug.h" +#if SL_ICD_ENABLED +#include "sl_si91x_power_manager.h" +#include "rsi_wisemcu_hardware_setup.h" +#include "sl_si91x_power_manager_init.h" +#endif // SL_ICD_ENABLED +#include "SEGGER_RTT.h" +#include "sl_sleeptimer.h" +#include "sl_si91x_button_instances.h" +#include "sl_si91x_led_instances.h" +#include "sl_ulp_timer_instances.h" +#include "sl_iostream_rtt.h" +#include "cmsis_os2.h" +#include "sl_iostream_init_instances.h" + +void sl_platform_init(void) +{ + SystemCoreClockUpdate(); + sl_si91x_device_init_nvic(); + sli_si91x_platform_init(); + RSI_Board_Init(); + DEBUGINIT(); +#if SL_ICD_ENABLED + sl_si91x_hardware_setup(); +#endif // SL_ICD_ENABLED + osKernelInitialize(); +} + +void sl_kernel_start(void) +{ + osKernelStart(); +} + +void sl_driver_init(void) +{ + button_init_instances(); + led_init_instances(); +} + +void sl_service_init(void) +{ +#if SL_ICD_ENABLED + sl_si91x_power_manager_init(); + sli_si91x_power_manager_configure_ram_and_peripheral(); +#endif // SL_ICD_ENABLED +#if defined(DISPLAY_ENABLED) || defined(SL_ICD_ENABLED) + sl_sleeptimer_init(); +#endif // DISPLAY_ENABLED || SL_ICD_ENABLED + sl_iostream_init_instances(); +} + +void sl_stack_init(void) +{ +} + +void sl_internal_app_init(void) +{ +} + +void sl_iostream_init_instances(void) +{ + sl_iostream_rtt_init(); +} + diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.h new file mode 100644 index 0000000000..ef8751b80f --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_event_handler.h @@ -0,0 +1,12 @@ +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_kernel_start(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_iostream_init_instances(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.c new file mode 100644 index 0000000000..064e882d0e --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.c @@ -0,0 +1,27 @@ +#include "sl_iostream.h" +#include "sl_iostream_handles.h" +#include "string.h" + +const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { + + &sl_iostream_instance_rtt_info, + +}; + +const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); + +/***************************************************************************//** + * Get iostream instance handle for a given name + * + * @return Instance handle if it exist, NULL otherwise. + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_handle(char *name) +{ + for (uint32_t i = 0; i < sl_iostream_instances_count; i++) { + if (strcmp(sl_iostream_instances_info[i]->name, name) == 0) { + return sl_iostream_instances_info[i]->handle; + } + } + + return NULL; +} \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.h new file mode 100644 index 0000000000..e7aab8e58b --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_handles.h @@ -0,0 +1,20 @@ +#ifndef SL_IOSTREAM_HANDLES_H +#define SL_IOSTREAM_HANDLES_H +#include "sl_iostream.h" +#include "sl_iostream_rtt.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +extern const sl_iostream_instance_info_t *sl_iostream_instances_info[]; +extern const uint32_t sl_iostream_instances_count; + +sl_iostream_t *sl_iostream_get_handle(char *name); + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_HANDLES_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_init_instances.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_init_instances.h new file mode 100644 index 0000000000..c092c37eec --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_iostream_init_instances.h @@ -0,0 +1,16 @@ +#ifndef SL_IOSTREAM_INIT_INSTANCES_H +#define SL_IOSTREAM_INIT_INSTANCES_H + +#include "sl_iostream.h" +#ifdef __cplusplus +extern "C" { +#endif + +// Initialize iostream component(s) / instance(s) +void sl_iostream_init_instances(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_INIT_INSTANCES_H \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.c new file mode 100644 index 0000000000..99c7014855 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.c @@ -0,0 +1,57 @@ +/***************************************************************************/ /** + * @file sl_si91x_button_instances.c.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_button_pin_config.h" +#include "sl_si91x_button_instances.h" + +sl_button_t const button_btn0 = { + .port = SL_BUTTON_BTN0_PORT, + .pin = SL_BUTTON_BTN0_PIN, + .button_number = SL_BUTTON_BTN0_NUMBER, + #ifdef SL_BUTTON_BTN0_PAD + .pad = SL_BUTTON_BTN0_PAD, + #endif + .interrupt_config = SL_BUTTON_CONFIG_BTN0_INTR +}; +sl_button_t const button_btn1 = { + .port = SL_BUTTON_BTN1_PORT, + .pin = SL_BUTTON_BTN1_PIN, + .button_number = SL_BUTTON_BTN1_NUMBER, + #ifdef SL_BUTTON_BTN1_PAD + .pad = SL_BUTTON_BTN1_PAD, + #endif + .interrupt_config = SL_BUTTON_CONFIG_BTN1_INTR +}; + +void button_init_instances(void) +{ + sl_si91x_button_init(&button_btn0); + sl_si91x_button_init(&button_btn1); +} diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.h new file mode 100644 index 0000000000..7a7aa92365 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_button_instances.h @@ -0,0 +1,45 @@ +/***************************************************************************/ /** + * @file sl_si91x_button_instances.h.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_BUTTON_INSTANCES_H +#define SL_SI91X_BUTTON_INSTANCES_H + +#include "sl_si91x_button.h" +#include "sl_si91x_button_init_btn0_config.h" +#include "sl_si91x_button_init_btn1_config.h" + +extern const sl_button_t button_btn0; +extern const sl_button_t button_btn1; + + +void button_init_instances(void); +void sl_simple_button_init_instances(void); + +#endif // BUTTON_INSTANCES_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.c new file mode 100644 index 0000000000..04ce6657e2 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.c @@ -0,0 +1,49 @@ +/***************************************************************************/ /** + * @file sl_si91x_led_instances.c.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_led.h" +#include "sl_si91x_led_config.h" +#include "sl_si91x_led_instances.h" +sl_led_t const led_led0 = { + .port = SL_LED_LED0_PORT, + .pin = SL_LED_LED0_PIN, + .led_number = SL_LED_LED0_NUMBER, +}; +sl_led_t const led_led1 = { + .port = SL_LED_LED1_PORT, + .pin = SL_LED_LED1_PIN, + .led_number = SL_LED_LED1_NUMBER, +}; + +void led_init_instances(void) +{ + sl_si91x_led_init(&led_led0); + sl_si91x_led_init(&led_led1); +} diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.h new file mode 100644 index 0000000000..8856d06512 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_led_instances.h @@ -0,0 +1,51 @@ +/***************************************************************************/ /** + * @file sl_si91x_led_instances.h.jinja + * @brief Button Driver Instances + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91x_LED_INSTANCES_H +#define SL_SI91x_LED_INSTANCES_H + +#include +#include "sl_si91x_led_init_led0_config.h" +#include "sl_si91x_led_init_led1_config.h" + + +typedef struct { + uint8_t pin; ///< Pin number of the LED. + uint8_t port; ///< Port number of the LED. + uint8_t led_number; ///< LED number for identification. +} sl_led_t; + +extern const sl_led_t led_led0; +extern const sl_led_t led_led1; + + +void led_init_instances(void); + +#endif // SL_SI91x_LED_INSTANCES_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_handler.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_handler.c new file mode 100644 index 0000000000..6b5d512cb7 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_handler.c @@ -0,0 +1,96 @@ +/***************************************************************************//** + * @file sl_si91x_power_manager_handler.c.jinja + * @brief Power Manager Service Handler + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_power_manager.h" + +/***************************************************************************//** + * Check if the MCU can sleep at that time. This function is called when the system + * is about to go sleeping, with the interrupts disabled. It allows the software to + * cancel going to sleep in case of a last-minute event occurred (window between the + * function call and interrupt disable). + * + * @return True, if the system can go to sleep. + * False, otherwise. + * + * @note This function is called with the interrupt disabled and it MUST NOT be + * re-enabled. + ******************************************************************************/ +__WEAK boolean_t app_is_ok_to_sleep(void) +{ + return true; +} + +/***************************************************************************//** + * Check if the MCU can sleep after an interrupt. This function is called after an + * interrupt occured and was processed. It allows the power manger to know if it must + * go back to sleep or wakeup. + * + * @return SL_SI91X_POWER_MANAGER_IGNORE, if the module did not trigger an ISR and it + * won't to contribute to the decision. + * + * SL_SI91X_POWER_MANAGER_SLEEP, The module was the one that caused the system + * wakeup and the system SHOULD go back to sleep. + * + * SL_SI91X_POWER_MANAGER_WAKEUP, The module was the one that caused the system + * wakeup and the system MUST NOT go back to sleep. + * + * @note This function must not have any side effects. It is not guaranteed to be + * called for every ISR. If a prior hook function requires to wakeup, such + * as a wireless stack, the application hook function won't be called. + ******************************************************************************/ +__WEAK sl_si91x_power_manager_on_isr_exit_t app_sleep_on_isr_exit(void) +{ + return SL_SI91X_POWER_MANAGER_ISR_IGNORE; +} +/***************************************************************************//** + * Mandatory callback that must validate if the MCU can sleep after having + * processed an interrupt when the system was sleeping. + ******************************************************************************/ +boolean_t sl_si91x_power_manager_sleep_on_isr_exit(void) +{ + sl_si91x_power_manager_on_isr_exit_t answer; + boolean_t sleep = false; + boolean_t force_wakeup = false; + + + // Application hook + answer = app_sleep_on_isr_exit(); + if (answer == SL_SI91X_POWER_MANAGER_ISR_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_SI91X_POWER_MANAGER_ISR_SLEEP) { + sleep = true; + } + + if (force_wakeup) { + sleep = false; + } + + return sleep; +} diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_init.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_init.h new file mode 100644 index 0000000000..46c4fd1bb5 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_init.h @@ -0,0 +1,51 @@ +/***************************************************************************//** + * @file sl_si91x_power_manager_init.h.jinja + * @brief Power Manager Service Initialization + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_POWER_MANAGER_INIT_H +#define SL_SI91X_POWER_MANAGER_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_power_manager_config_3.h" + + +__STATIC_INLINE void sli_si91x_power_manager_configure_ram_and_peripheral(void) +{ + sl_si91x_power_manager_remove_peripheral_requirement(&peripheral_config); + sl_si91x_power_manager_configure_ram_retention(&ram_configuration); +} + +#ifdef __cplusplus +} +#endif + +#endif // SL_SI91X_POWER_MANAGER_INIT_H \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.c new file mode 100644 index 0000000000..b75675c5f0 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.c @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file sl_si91x_power_manager_wakeup_handler.c.jinja + * @brief Power Manager Service Wakeup Handler APIs + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_power_manager_wakeup_handler.h" + +sl_status_t sl_si91x_power_manager_wakeup_init(void) +{ + sl_status_t status = SL_STATUS_OK; + + status = sli_si91x_power_manager_gpio_init(); + if (status != SL_STATUS_OK) { + return status; + } + + return status; +} \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.h new file mode 100644 index 0000000000..416492cdbc --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_si91x_power_manager_wakeup_handler.h @@ -0,0 +1,43 @@ +/***************************************************************************/ /** + * @file sl_si91x_power_manager_wakeup_handler.h.jinja + * @brief Power Manager Service Wakeup Handler APIs + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_POWER_MANAGER_WAKEUP_HANDLER_H +#define SL_SI91X_POWER_MANAGER_WAKEUP_HANDLER_H + +#include "sl_status.h" + +#include "sl_si91x_driver_gpio.h" + +#include "sl_si91x_power_manager_wakeup_source_config.h" + +sl_status_t sl_si91x_power_manager_wakeup_init(void); + +sl_status_t sli_si91x_power_manager_gpio_init(void); + +#endif // SL_SI91X_POWER_MANAGER_WAKEUP_HANDLER_H \ No newline at end of file diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_init.c b/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_init.c new file mode 100644 index 0000000000..91a8a01f21 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_init.c @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file sl_ulp_timer_init.c.jinja + * @brief ULP timer Instance Initialization + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_ulp_timer.h" + +#include "sl_si91x_ulp_timer_init_timer0_config.h" + + +#include "sl_ulp_timer_instances.h" + + + +ulp_timer_config_t sl_timer_handle_timer0 = { + .timer_num = SL_ULP_TIMER_TIMER0, + .timer_mode = SL_ULP_TIMER_TIMER0_MODE, + .timer_type = SL_ULP_TIMER_TIMER0_TYPE, + .timer_match_value = SL_TIMER_MATCH_VALUE_DEFAULT, + .timer_direction = SL_ULP_TIMER_TIMER0_DIRECTION, +}; + + + diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_instances.h b/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_instances.h new file mode 100644 index 0000000000..1eb1e971e0 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sl_ulp_timer_instances.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file sl_ulp_timer_instances.h.jinja + * @brief ULP Timer Instance + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_ULP_TIMER_INSTANCES_H +#define SL_ULP_TIMER_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +#define SL_ULP_TIMER_TIMER0 0 +#define SL_ULP_TIMER_TIMER1 1 +#define SL_ULP_TIMER_TIMER2 2 +#define SL_ULP_TIMER_TIMER3 3 + + +extern ulp_timer_config_t sl_timer_handle_timer0 ; + + + +#ifdef __cplusplus +} +#endif + +#endif // SL_ULP_TIMER_INSTANCES_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_autogen.h b/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_autogen.h new file mode 100644 index 0000000000..a900af14a9 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_autogen.h @@ -0,0 +1,49 @@ +// This is an autogenerated config file, any changes to this file will be +// overwritten + +#ifndef SLI_MBEDTLS_CONFIG_AUTOGEN_H +#define SLI_MBEDTLS_CONFIG_AUTOGEN_H + +#define MBEDTLS_MPI_MAX_SIZE 32 + +#define MBEDTLS_NO_PLATFORM_ENTROPY +#define MBEDTLS_AES_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#define MBEDTLS_BASE64_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CMAC_C +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_MD_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PEM_PARSE_C +#define MBEDTLS_PEM_WRITE_C +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_PLATFORM_C +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_ENTROPY_FORCE_SHA256 +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SHA224_C +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CREATE_C +#define MBEDTLS_X509_CRT_PARSE_C +#define MBEDTLS_X509_CRT_WRITE_C +#define MBEDTLS_X509_CRL_PARSE_C +#define MBEDTLS_X509_CSR_PARSE_C +#define MBEDTLS_X509_CSR_WRITE_C +#ifndef SL_MBEDTLS_USE_TINYCRYPT +#define MBEDTLS_PSA_CRYPTO_C +#define MBEDTLS_USE_PSA_CRYPTO +#define MBEDTLS_PSA_CRYPTO_CONFIG +#define MBEDTLS_PSA_CRYPTO_STORAGE_C +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#endif // SL_MBEDTLS_USE_TINYCRYPT +#endif // SLI_MBEDTLS_CONFIG_AUTOGEN_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_transform_autogen.h b/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_transform_autogen.h new file mode 100644 index 0000000000..0ea1e1ea11 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sli_mbedtls_config_transform_autogen.h @@ -0,0 +1,51 @@ +// This is an autogenerated config file, any changes to this file will be +// overwritten + +#ifndef SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H +#define SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H + +// Convert CMSIS Markup config defines to mbedTLS specific config defines + +#if SL_MBEDTLS_RSA_NO_CRT +#define MBEDTLS_RSA_NO_CRT +#endif + +// Allow undefining the specified cipher suites +#if defined(SLI_MBEDTLS_AUTODETECT_CIPHERSUITES) +#undef MBEDTLS_SSL_CIPHERSUITES +#endif + +#if SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#endif +#if SL_MBEDTLS_SSL_EXPORT_KEYS +#define MBEDTLS_SSL_EXPORT_KEYS +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING +#define MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING +#endif + +#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) +#define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN +#endif + +#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) +#define MBEDTLS_SSL_OUT_CONTENT_LEN SL_MBEDTLS_SSL_OUT_CONTENT_LEN +#endif + +#endif // SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_builtin_config_autogen.h b/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_builtin_config_autogen.h new file mode 100644 index 0000000000..9852d41080 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_builtin_config_autogen.h @@ -0,0 +1,16 @@ +// This is an autogenerated config file, any changes to this file will be +// overwritten + +#ifndef SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H +#define SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H + +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 + +#endif // SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H diff --git a/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_config_autogen.h b/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_config_autogen.h new file mode 100644 index 0000000000..8dc02c0ce4 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/autogen/sli_psa_config_autogen.h @@ -0,0 +1,32 @@ +// This is an autogenerated config file, any changes to this file will be +// overwritten + +#ifndef SLI_PSA_CONFIG_AUTOGEN_H +#define SLI_PSA_CONFIG_AUTOGEN_H + +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG +#define PSA_WANT_KEY_TYPE_AES 1 +#define PSA_WANT_ALG_CCM 1 +#define PSA_WANT_ALG_CMAC 1 +#define PSA_WANT_ALG_SHA_224 1 +#define PSA_WANT_ALG_SHA_256 1 +#define PSA_WANT_ALG_ECB_NO_PADDING 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_ECC_SECP_R1_256 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define PSA_WANT_ALG_ECDH 1 +#define PSA_WANT_ALG_ECDSA 1 +#define PSA_WANT_ALG_HKDF 1 +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_KEY_TYPE_HMAC 1 + +#define MBEDTLS_PSA_KEY_SLOT_COUNT (1 + SL_PSA_KEY_USER_SLOT_COUNT) +#ifndef SL_PSA_ITS_MAX_FILES +#define SL_PSA_ITS_MAX_FILES (1 + SL_PSA_ITS_USER_MAX_FILES) +#endif + +#endif // SLI_PSA_CONFIG_AUTOGEN_H diff --git a/matter/si91x/siwx917/BRD4343A/config/RTE_Device_917.h b/matter/si91x/siwx917/BRD4343A/config/RTE_Device_917.h new file mode 100644 index 0000000000..1f58279f9d --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/RTE_Device_917.h @@ -0,0 +1,4557 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgement in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 1. December 2016 + * $Revision: V2.4.4 + * + * Project: RTE Device Configuration for Si917 ACx Module BRD4343A + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H +#include "rsi_ccp_user_config.h" + +#define GPIO_PORT_0 0 // GPIO port 0 +#define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 +#define HOST_PAD_GPIO_MIN 25 // GPIO host pad minimum pin number +#define HOST_PAD_GPIO_MAX 30 // GPIO host pad maximum pin number +#define GPIO_MAX_PIN 64 // GPIO maximum pin number + +#define BUTTON_0_GPIO_PIN 2 + +#define RTE_BUTTON0_PORT 0 +#define RTE_BUTTON0_NUMBER 0 +#define RTE_BUTTON0_PIN (2U) + +#define RTE_BUTTON1_PORT 0 +#define RTE_BUTTON1_NUMBER 1 +#define RTE_BUTTON1_PIN (11U) +#define RTE_BUTTON1_PAD 6 + +#define RTE_LED0_PORT 4 +#define RTE_LED0_NUMBER 0 +#define RTE_LED0_PIN (0U) + +#define RTE_LED1_PORT 0 +#define RTE_LED1_NUMBER 1 +#define RTE_LED1_PIN (10U) +#define BOARD_ACTIVITY_LED (0U) // LED0 +#define RTE_LED1_PAD 5 + +// USART0 [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_ENABLE_FIFO 1 + +#define RTE_USART0 1 + +#define RTE_USART0_CLK_SRC USART_ULPREFCLK +#define RTE_USART0_CLK_DIV_FACT 1 +#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_USART_MODE 0 //!Usart mode macros +#define RTE_CONTINUOUS_CLOCK_MODE 0 + +#define RTE_USART0_LOOPBACK 0 +#define RTE_USART0_DTR_EANBLE 0 + +#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode + +#define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_USART0_DMA_TX_LEN_PER_DES 1024 +#define RTE_USART0_DMA_RX_LEN_PER_DES 1024 + +#define RTE_USART0_CHNL_UDMA_TX_CH 25 + +#define RTE_USART0_CHNL_UDMA_RX_CH 24 + +// USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 +// CLK of USART0 +#ifndef USART0_CLK_LOC +#define RTE_USART0_CLK_PORT_ID 0 + +#if (RTE_USART0_CLK_PORT_ID == 0) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 8 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#elif (RTE_USART0_CLK_PORT_ID == 1) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 25 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#elif (RTE_USART0_CLK_PORT_ID == 2) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 52 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#else +#error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT 0 +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif + +// USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 +// TX for USART0 +#ifndef USART0_TX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_TX_PORT_ID 1 +#else +#define RTE_USART0_TX_PORT_ID 0 +#endif + +#if (RTE_USART0_TX_PORT_ID == 0) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 15 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#elif (RTE_USART0_TX_PORT_ID == 1) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 30 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#elif (RTE_USART0_TX_PORT_ID == 2) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 54 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#elif (RTE_USART0_TX_PORT_ID == 3) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 71 +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#else +#error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_TX_PORT 0 +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif + +// USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 +// RX for USART0 +#ifndef USART0_RX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_RX_PORT_ID 1 +#else +#define RTE_USART0_RX_PORT_ID 0 +#endif + +#if (RTE_USART0_RX_PORT_ID == 0) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 10 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#elif (RTE_USART0_RX_PORT_ID == 1) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 29 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#elif (RTE_USART0_RX_PORT_ID == 2) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 55 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#elif (RTE_USART0_RX_PORT_ID == 3) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 65 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#elif (RTE_USART0_RX_PORT_ID == 4) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 70 +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#else +#error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RX_PORT 0 +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif + +// USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 +// CTS for USART0 +#ifndef USART0_CTS_LOC +#define RTE_USART0_CTS_PORT_ID 0 + +#if (RTE_USART0_CTS_PORT_ID == 0) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 6 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#elif (RTE_USART0_CTS_PORT_ID == 1) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 26 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#elif (RTE_USART0_CTS_PORT_ID == 2) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 56 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#elif (RTE_USART0_CTS_PORT_ID == 3) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 70 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#else +#error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT 0 +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif + +// USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 +// RTS for USART0 +#ifndef USART0_RTS_LOC +#define RTE_USART0_RTS_PORT_ID 0 + +#if (RTE_USART0_RTS_PORT_ID == 0) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 9 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#elif (RTE_USART0_RTS_PORT_ID == 1) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 28 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#elif (RTE_USART0_RTS_PORT_ID == 2) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 53 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#else +#error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT 0 +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif + +// USART0_IR_TX <0=>P0_48 <1=>P0_72 +// IR TX for USART0 +#ifndef USART0_IRTX_LOC +#define RTE_IR_TX_PORT_ID 0 +#if ((RTE_IR_TX_PORT_ID == 2)) +#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif + +#if (RTE_IR_TX_PORT_ID == 0) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 48 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#elif (RTE_IR_TX_PORT_ID == 1) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 72 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#elif (RTE_IR_TX_PORT_ID == 2) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 26 +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#else +#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT 0 +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif + +// USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 +// IR RX for USART0 +#ifndef USART0_IRRX_LOC +#define RTE_IR_RX_PORT_ID 0 +#if ((RTE_IR_RX_PORT_ID == 2)) +#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif + +#if (RTE_IR_RX_PORT_ID == 0) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 47 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#elif (RTE_IR_RX_PORT_ID == 1) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 71 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#elif (RTE_IR_RX_PORT_ID == 2) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 25 +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#else +#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT 0 +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif + +// USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 +// RI for USART0 +#ifndef USART0_RI_LOC +#define RTE_RI_PORT_ID 0 + +#if (RTE_RI_PORT_ID == 0) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 27 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#elif (RTE_RI_PORT_ID == 1) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 46 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#else +#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RI_PORT 0 +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif + +// USART0_DSR <0=>P0_11 <1=>P0_57 +// DSR for USART0 +#ifndef USART0_DSR_LOC +#define RTE_DSR_PORT_ID 0 + +#if (RTE_DSR_PORT_ID == 0) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 11 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#elif (RTE_DSR_PORT_ID == 1) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 57 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#else +#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + +// USART0_DCD <0=>P0_12 <1=>P0_29 +// DCD for USART0 +#ifndef USART0_DCD_LOC +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 12 +#else +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif + +// USART0_DTR <0=>P0_7 +// DTR for USART0 +#ifndef USART0_DTR_LOC +#define RTE_USART0_DTR_PORT 0 +#define RTE_USART0_DTR_PIN 7 +#else +#define RTE_USART0_DTR_PORT 0 +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 +// + +// UART1 [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART +#define RTE_UART1 1 + +#define RTE_UART1_CLK_SRC USART_ULPREFCLK +#define RTE_UART1_CLK_DIV_FACT 1 +#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_UART1_LOOPBACK 0 +#define RTE_UART1_DMA_MODE1_EN 0 + +#define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_UART1_DMA_TX_LEN_PER_DES 1024 +#define RTE_UART1_DMA_RX_LEN_PER_DES 1024 + +#define RTE_UART1_CHNL_UDMA_TX_CH 27 + +#define RTE_UART1_CHNL_UDMA_RX_CH 26 + +/*UART1 PINS*/ +// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_69 <3=>P0_73 <4=>P0_75 <5=>P0_34 +// TX of UART1 +#ifndef UART1_TX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_TX_PORT_ID 0 +#else +#define RTE_UART1_TX_PORT_ID 0 + +#if ((RTE_UART1_TX_PORT_ID == 6)) +#error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif + +#if (RTE_UART1_TX_PORT_ID == 0) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 7 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#elif (RTE_UART1_TX_PORT_ID == 1) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 30 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#elif (RTE_UART1_TX_PORT_ID == 2) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 73 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#elif (RTE_UART1_TX_PORT_ID == 3) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 75 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#else +#error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_TX_PORT 0 +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif + +// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_72 +// RX of UART1 +#ifndef UART1_RX_LOC +#define RTE_UART1_RX_PORT_ID 0 + +#if (RTE_UART1_RX_PORT_ID == 0) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 6 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#elif (RTE_UART1_RX_PORT_ID == 1) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 29 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#elif (RTE_UART1_RX_PORT_ID == 2) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 66 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 24 +#elif (RTE_UART1_RX_PORT_ID == 3) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 72 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#else +#error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_RX_PORT 0 +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif + +// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 +// CTS of UART1 +#ifndef UART1_CTS_LOC +#define RTE_UART1_CTS_PORT_ID 0 + +#if (RTE_UART1_CTS_PORT_ID == 0) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 11 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#elif (RTE_UART1_CTS_PORT_ID == 1) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 28 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#elif (RTE_UART1_CTS_PORT_ID == 2) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 51 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#elif (RTE_UART1_CTS_PORT_ID == 3) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 65 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#elif (RTE_UART1_CTS_PORT_ID == 4) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 71 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#else +#error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT 0 +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif + +// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 +// RTS of UART1 +#ifndef UART1_RTS_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_RTS_PORT_ID 0 +#else +#define RTE_UART1_RTS_PORT_ID 0 +#endif + +#if (RTE_UART1_RTS_PORT_ID == 0) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 10 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#elif (RTE_UART1_RTS_PORT_ID == 1) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 27 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#elif (RTE_UART1_RTS_PORT_ID == 2) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 50 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#elif (RTE_UART1_RTS_PORT_ID == 3) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 70 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#elif (RTE_UART1_RTS_PORT_ID == 4) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 72 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#else +#error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT 0 +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + +// + +// ULP_UART [Driver_ULP_UART] +// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART +#define RTE_ULP_UART 1 + +#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK +#define RTE_ULP_UART_CLK_DIV_FACT 0 +#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_ULP_UART_LOOPBACK 0 +#define RTE_ULP_UART_DMA_MODE1_EN 0 + +#define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 +#define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 + +#define RTE_ULPUART_CHNL_UDMA_TX_CH 1 + +#define RTE_ULPUART_CHNL_UDMA_RX_CH 0 + +/*ULPSS UART PINS*/ +// UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 +// TX of ULPSS UART +#ifndef ULP_UART_TX_LOC +#define RTE_ULP_UART_TX_PORT_ID 1 +#if (RTE_ULP_UART_TX_PORT_ID == 0) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 7 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 1) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 11 +#define RTE_ULP_UART_TX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif + +// UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 +// RX of ULPSS UART +#ifndef ULP_UART_RX_LOC +#define RTE_ULP_UART_RX_PORT_ID 2 +#if (RTE_ULP_UART_RX_PORT_ID == 0) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 2 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 1) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 6 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 2) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 9 +#define RTE_ULP_UART_RX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif + +// UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 +// CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC +#define RTE_ULP_UART_CTS_PORT_ID 0 +#if (RTE_ULP_UART_CTS_PORT_ID == 0) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 1 +#define RTE_ULP_UART_CTS_MUX 3 +#elif (RTE_ULP_UART_CTS_PORT_ID == 1) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 8 +#define RTE_ULP_UART_CTS_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif + +// UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 +// RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC +#define RTE_ULP_UART_RTS_PORT_ID 0 +#if (RTE_ULP_UART_RTS_PORT_ID == 0) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 10 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" +#endif +#else +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + +// + +// SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] +// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_MASTER 1 + +// SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 +#ifndef SSI_MASTER_DATA1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_MASTER_MISO_PORT_ID 1 +#else +#define RTE_SSI_MASTER_MISO_PORT_ID 0 +#endif + +#if (RTE_SSI_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 12 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 27 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 57 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#else +#error "Invalid SSI_MASTER_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif + +// SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC +#define RTE_SSI_MASTER_MOSI_PORT_ID 1 + +#if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 11 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 26 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 56 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#else +#error "Invalid SSI_MASTER_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif + +// SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC +#define RTE_SSI_MASTER_SCK_PORT_ID 1 + +#if (RTE_SSI_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 8 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 25 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 52 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#else +#error "Invalid SSI_MASTER_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif + +#define M4_SSI_CS0 1 +#define M4_SSI_CS1 0 +#define M4_SSI_CS2 0 +#define M4_SSI_CS3 0 + +// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC +#define RTE_SSI_MASTER_CS0_PORT_ID 1 + +#if (RTE_SSI_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 9 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 28 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 53 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#else +#error "Invalid SSI_MASTER_CS0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif + +//CS1 +#ifndef SSI_MASTER_CS1_LOC +#define RTE_SSI_MASTER_CS1_PORT_ID 0 +#if (RTE_SSI_MASTER_CS1_PORT_ID == 0) +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 +#else +#error "Invalid SSI_MASTER_CS1 Pin Configuration!" +#endif +#else +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 + +//CS2 +#ifndef SSI_MASTER_CS2_LOC +#define RTE_SSI_MASTER_CS2_PORT_ID 1 +#if (RTE_SSI_MASTER_CS2_PORT_ID == 0) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 15 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 50 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#else +#error "Invalid SSI_MASTER_CS2 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif + +//CS3 +#ifndef SSI_MASTER_CS3_LOC +#define RTE_SSI_MASTER_CS3_PORT_ID 0 +#if (RTE_SSI_MASTER_CS3_PORT_ID == 0) +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 +#else +#error "Invalid SSI_MASTER_CS3 Pin Configuration!" +#endif +#else +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 + +// DMA Rx +// Channel <28=>28 +// Selects DMA Channel (only Channel 28 can be used) +// +#define RTE_SSI_MASTER_UDMA_RX_CH 28 + +// DMA Tx +// Channel <29=>29 +// Selects DMA Channel (only Channel 29 can be used) +// +#define RTE_SSI_MASTER_UDMA_TX_CH 29 +// + +// SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] +// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI +#define RTE_SSI_SLAVE 1 + +#define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK + +// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC +#define RTE_SSI_SLAVE_MISO_PORT_ID 2 + +#if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) +#define RTE_SSI_SLAVE_MISO 0 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 11 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 28 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 49 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 57 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#else +#error "Invalid SSI_SLAVE_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif + +// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 +#ifndef SSI_SLAVE_MOSI_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#else +#define RTE_SSI_SLAVE_MOSI_PORT_ID 1 +#endif + +#if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) +#define RTE_SSI_SLAVE_MOSI 0 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 10 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 27 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 48 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 56 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#else +#error "Invalid SSI_SLAVE_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif + +// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC +#define RTE_SSI_SLAVE_SCK_PORT_ID 2 + +#if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) +#define RTE_SSI_SLAVE_SCK 0 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 8 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 26 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 47 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 52 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#else +#error "Invalid SSI_SLAVE_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif + +// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC +#define RTE_SSI_SLAVE_CS_PORT_ID 2 + +#if (RTE_SSI_SLAVE_CS_PORT_ID == 0) +#define RTE_SSI_SLAVE_CS 0 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 9 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 25 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 46 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 53 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#else +#error "Invalid SSI_SLAVE_CS Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif + +// DMA Rx +// Channel <22=>22 +// Selects DMA Channel (only Channel 22 can be used) +// +#define RTE_SSI_SLAVE_UDMA_RX_CH 22 +#define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 + +// DMA Tx +// Channel <23=>23 +// Selects DMA Channel (only Channel 23 can be used) +// +#define RTE_SSI_SLAVE_UDMA_TX_CH 23 +#define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 + +// + +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_ULP_MASTER 1 + +// Enable multiple CSN lines +#define ULP_SSI_CS0 0 +#define ULP_SSI_CS1 1 +#define ULP_SSI_CS2 0 + +// SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#if !defined(ULP_SPI_MISO_LOC) && !defined(ULP_SSI_MISO_LOC) +#define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 2 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 9 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else +#error "Invalid SSI_ULP_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SSI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif + +// SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#if !defined(ULP_SPI_MOSI_LOC) && !defined(ULP_SSI_MOSI_LOC) +#define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else +#error "Invalid SSI_ULP_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SSI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif + +// SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#if !defined(ULP_SPI_SCK_LOC) && !defined(ULP_SSI_SCK_LOC) +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#else +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#endif +#if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_SCK 0 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 0 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 8 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#else +#error "Invalid SSI_ULP_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SSI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif + +// CS0 +#if !defined(ULP_SPI_CS0_LOC) && !defined(ULP_SSI_CS0_LOC) +#define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 +#if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 3 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 10 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#else +#error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SSI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif + +// CS1 +#if !defined(ULP_SPI_CS1_LOC) || !defined(ULP_SSI_CS1_LOC) +#define RTE_SSI_ULP_MASTER_CS1_PORT 0 +#define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT 0 +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SSI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#define RTE_SSI_ULP_MASTER_CS1_MODE 1 + +// CS2 +#if !defined(ULP_SPI_CS2_LOC) && !defined(ULP_SSI_CS2_LOC) +#define RTE_SSI_ULP_MASTER_CS2_PORT 0 +#define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT 0 +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SSI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#define RTE_SSI_ULP_MASTER_CS2_MODE 1 + +// DMA Rx +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// +#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 +#define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 + +// DMA Tx +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// +#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 +#define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 + +// +/*=================================================================== + UDMA Defines +====================================================================*/ +// UDMA [Driver_UDMA] +#define DESC_MAX_LEN 0x400 +#define RTE_UDMA0 1 +#define UDMA0_IRQHandler IRQ033_Handler +#define CHNL_MASK_REQ0 0 +#define CHNL_PRIORITY0 0 +#define DMA_PERI_ACK0 0 +#define BURST_REQ0_EN 1 +#define UDMA0_CHNL_PRIO_LVL 1 +#define UDMA0_SRAM_BASE 0x1FC00 + +#define RTE_UDMA1 1 +#define UDMA1_IRQHandler IRQ010_Handler +#define CHNL_MASK_REQ1 0 +#define CHNL_PRIORITY1 0 +#define BURST_REQ1_EN 1 +#define CHNL_HIGH_PRIO_EN1 1 +#define UDMA1_CHNL_PRIO_LVL 1 +#define ULP_SRAM_START_ADDR 0x24060000 +#define ULP_SRAM_END_ADDR 0x24063E00 +// RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 +#define RTE_UDMA1_BASE_MEM 0 +#if (RTE_UDMA1_BASE_MEM == 0) +#define UDMA1_SRAM_BASE 0x24061C00 +#elif (RTE_UDMA1_BASE_MEM == 1) +#define UDMA1_SRAM_BASE 0x1CC00 +#else +#error "Invalid UDMA1 Control Base Address!" +#endif +// + +// I2S0 [Driver_I2S0] +// Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S + +#define RTE_I2S0 1 +#define I2S0_IRQHandler IRQ064_Handler +/*I2S0 PINS*/ + +// I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// SCLK of I2S0 +#ifndef I2S0_SCLK_LOC +#define RTE_I2S0_SCLK_PORT_ID 1 + +#if (RTE_I2S0_SCLK_PORT_ID == 0) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 8 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 3 +#elif (RTE_I2S0_SCLK_PORT_ID == 1) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 25 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 0 //no pad +#elif (RTE_I2S0_SCLK_PORT_ID == 2) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 46 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 10 +#elif (RTE_I2S0_SCLK_PORT_ID == 3) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 52 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 16 +#else +#error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif + +// I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 +// WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC +#define RTE_I2S0_WSCLK_PORT_ID 1 + +#if (RTE_I2S0_WSCLK_PORT_ID == 0) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 9 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 4 +#elif (RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 26 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 0 //no pad +#elif (RTE_I2S0_WSCLK_PORT_ID == 2) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 47 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 11 +#elif (RTE_I2S0_WSCLK_PORT_ID == 3) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 53 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 17 +#else +#error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif + +// I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 +// DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC +#define RTE_I2S0_DOUT0_PORT_ID 1 + +#if (RTE_I2S0_DOUT0_PORT_ID == 0) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 11 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 6 +#elif (RTE_I2S0_DOUT0_PORT_ID == 1) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 28 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 0 // no pad +#elif (RTE_I2S0_DOUT0_PORT_ID == 2) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 49 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 13 +#elif (RTE_I2S0_DOUT0_PORT_ID == 3) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 57 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 21 +#else +#error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif + +// I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 +// DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC +#define RTE_I2S0_DIN0_PORT_ID 1 + +#if (RTE_I2S0_DIN0_PORT_ID == 0) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 10 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 5 +#elif (RTE_I2S0_DIN0_PORT_ID == 1) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 27 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 0 // no pad +#elif (RTE_I2S0_DIN0_PORT_ID == 2) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 48 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 12 +#elif (RTE_I2S0_DIN0_PORT_ID == 3) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 56 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 20 +#else +#error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S0_DOUT1_PORT_ID 1 +#else +#define RTE_I2S0_DOUT1_PORT_ID 0 +#endif + +#if (RTE_I2S0_DOUT1_PORT_ID == 0) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 7 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 2 +#elif (RTE_I2S0_DOUT1_PORT_ID == 1) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 30 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 0 //no pad +#elif (RTE_I2S0_DOUT1_PORT_ID == 2) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 51 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 15 +#elif (RTE_I2S0_DOUT1_PORT_ID == 3) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 55 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 19 +#else +#error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif + +// I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC +#define RTE_I2S0_DIN1_PORT_ID 0 + +#if (RTE_I2S0_DIN1_PORT_ID == 0) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 6 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 1 +#elif (RTE_I2S0_DIN1_PORT_ID == 1) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 29 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 0 //no pad +#elif (RTE_I2S0_DIN1_PORT_ID == 2) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 50 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 14 +#elif (RTE_I2S0_DIN1_PORT_ID == 3) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 54 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 18 +#else +#error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) +#define I2S0_RX_FIFO_LEVEL (2U) + +// I2S0_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_TX_RES 1 +#if (RTE_I2S0_TX_RES == 0) +#define I2S0_TX_RES RES_12_BIT +#elif (RTE_I2S0_TX_RES == 1) +#define I2S0_TX_RES RES_16_BIT +#elif (RTE_I2S0_TX_RES == 2) +#define I2S0_TX_RES RES_20_BIT +#elif (RTE_I2S0_TX_RES == 3) +#define I2S0_TX_RES RES_24_BIT +#else +#error "Invalid I2S0 TX channel resolution!" +#endif + +// I2S0_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_RX_RES 1 +#if (RTE_I2S0_RX_RES == 0) +#define I2S0_RX_RES RES_12_BIT +#elif (RTE_I2S0_RX_RES == 1) +#define I2S0_RX_RES RES_16_BIT +#elif (RTE_I2S0_RX_RES == 2) +#define I2S0_RX_RES RES_20_BIT +#elif (RTE_I2S0_RX_RES == 3) +#define I2S0_RX_RES RES_24_BIT +#else +#error "Invalid I2S0 RX channel resolution!" +#endif + +#define RTE_I2S0_CHNL_UDMA_TX_EN 1 +#define RTE_I2S0_CHNL_UDMA_TX_CH 15 + +#define RTE_I2S0_CHNL_UDMA_RX_EN 1 +#define RTE_I2S0_CHNL_UDMA_RX_CH 14 + +#define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 + +// + +// ULP I2S [Driver_I2S1] +// Configuration settings for Driver_I2S1 in component ::Drivers:I2S +#define RTE_I2S1 1 +#define I2S1_IRQHandler IRQ014_Handler + +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 +/*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S1_SCLK_PORT_ID 0 +#else +#define RTE_I2S1_SCLK_PORT_ID 2 +#endif +#if (RTE_I2S1_SCLK_PORT_ID == 0) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 3 +#define RTE_I2S1_SCLK_MUX 2 +#elif (RTE_I2S1_SCLK_PORT_ID == 1) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 7 +#define RTE_I2S1_SCLK_MUX 2 +#elif (RTE_I2S1_SCLK_PORT_ID == 2) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 8 +#define RTE_I2S1_SCLK_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif + +// I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC +#define RTE_I2S1_WSCLK_PORT_ID 0 +#if (RTE_I2S1_WSCLK_PORT_ID == 0) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 2 +#define RTE_I2S1_WSCLK_MUX 2 +#elif (RTE_I2S1_WSCLK_PORT_ID == 1) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 10 +#define RTE_I2S1_WSCLK_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif + +// I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC +#define RTE_I2S1_DOUT0_PORT_ID 0 +#if (RTE_I2S1_DOUT0_PORT_ID == 0) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 1 +#define RTE_I2S1_DOUT0_MUX 2 +#elif (RTE_I2S1_DOUT0_PORT_ID == 1) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 11 +#define RTE_I2S1_DOUT0_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif + +// I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC +#define RTE_I2S1_DIN0_PORT_ID 1 +#if (RTE_I2S1_DIN0_PORT_ID == 0) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 0 +#define RTE_I2S1_DIN0_MUX 2 +#elif (RTE_I2S1_DIN0_PORT_ID == 1) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 6 +#define RTE_I2S1_DIN0_MUX 2 +#elif (RTE_I2S1_DIN0_PORT_ID == 2) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 9 +#define RTE_I2S1_DIN0_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif + +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) +#define I2S1_RX_FIFO_LEVEL (2U) + +// I2S1_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_TX_RES 1 +#if (RTE_I2S1_TX_RES == 0) +#define I2S1_TX_RES RES_12_BIT +#elif (RTE_I2S1_TX_RES == 1) +#define I2S1_TX_RES RES_16_BIT +#elif (RTE_I2S1_TX_RES == 2) +#define I2S1_TX_RES RES_20_BIT +#elif (RTE_I2S1_TX_RES == 3) +#define I2S1_TX_RES RES_24_BIT +#else +#error "Invalid I2S1 TX channel resolution!" +#endif + +// I2S1_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_RX_RES 1 +#if (RTE_I2S1_RX_RES == 0) +#define I2S1_RX_RES RES_12_BIT +#elif (RTE_I2S1_RX_RES == 1) +#define I2S1_RX_RES RES_16_BIT +#elif (RTE_I2S1_RX_RES == 2) +#define I2S1_RX_RES RES_20_BIT +#elif (RTE_I2S1_RX_RES == 3) +#define I2S1_RX_RES RES_24_BIT +#else +#error "Invalid I2S1 RX channel resolution!" +#endif + +#define RTE_I2S1_CHNL_UDMA_TX_EN 1 +#define RTE_I2S1_CHNL_UDMA_TX_CH 7 + +#define RTE_I2S1_CHNL_UDMA_RX_EN 1 +#define RTE_I2S1_CHNL_UDMA_RX_CH 6 + +#define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 + +// I2S1 [Driver_I2S1] + +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C + +#define RTE_I2C0 1 +#define I2C0_IRQHandler IRQ042_Handler + +// I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 +#ifndef I2C0_SCL_LOC +#define RTE_I2C0_SCL_PORT_ID 1 + +#if (RTE_I2C0_SCL_PORT_ID == 0) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 7 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#elif (RTE_I2C0_SCL_PORT_ID == 1) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 65 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#elif (RTE_I2C0_SCL_PORT_ID == 2) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 66 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 24 +#define RTE_I2C0_SCL_I2C_REN 2 +#elif (RTE_I2C0_SCL_PORT_ID == 3) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 75 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#else +#error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT 0 +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif + +// I2C0_SCL Pin <0=>P0_6 +#ifndef I2C0_SDA_LOC +#define RTE_I2C0_SDA_PORT_ID 0 + +#if (RTE_I2C0_SDA_PORT_ID == 0) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 6 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#else +#error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT 0 +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define I2C_DMA 0 +#if (I2C_DMA == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif +// I2C1 [Driver_I2C0] + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#define I2C1_IRQHandler IRQ061_Handler +// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC +#define RTE_I2C1_SCL_PORT_ID 2 + +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 6 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 29 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#elif (RTE_I2C1_SCL_PORT_ID == 2) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 50 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#elif (RTE_I2C1_SCL_PORT_ID == 3) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 54 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#elif (RTE_I2C1_SCL_PORT_ID == 5) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 66 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_REN 2 +#elif (RTE_I2C1_SCL_PORT_ID == 6) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 70 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT 0 +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif + +// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <5=>P0_71 <6=>P0_34 +#ifndef I2C1_SDA_LOC +#define RTE_I2C1_SDA_PORT_ID 2 + +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 7 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 30 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#elif (RTE_I2C1_SDA_PORT_ID == 2) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 51 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#elif (RTE_I2C1_SDA_PORT_ID == 3) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 55 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#elif (RTE_I2C1_SDA_PORT_ID == 4) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 65 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#elif (RTE_I2C1_SDA_PORT_ID == 5) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 71 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT 0 +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C1 [Driver_I2C1] + +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 1 +#define I2C2_IRQHandler IRQ013_Handler + +// I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C2_SCL_PORT_ID 0 +#else +#define RTE_I2C2_SCL_PORT_ID 0 +#endif +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 7 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 7 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 8 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 8 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif + +// I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 6 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 6 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 11 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 11 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C2 [Driver_I2C2] + +// GSPI (Generic SPI master) [Driver_GSPI_MASTER] +// Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI +#define RTE_GSPI_MASTER 1 + +// GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 + +#if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 8 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 3 +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 1) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 25 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 2) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 46 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 10 +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 3) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 52 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 16 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS0 +// <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 +// CS0 of GSPI0 +// +#ifndef GSPI_MASTER_CS0_LOC +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 + +#if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 9 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 4 +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 28 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 49 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 13 +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 53 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 17 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS1 +// <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// CS1 of GSPI0 +// +#ifndef GSPI_MASTER_CS1_LOC +#define RTE_GSPI_MASTER_CS1_PORT_ID 1 +#if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 10 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 5 +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 29 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 50 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 14 +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 54 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 18 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS2 +// <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// CS2 of GSPI0 +// +#ifndef GSPI_MASTER_CS2_LOC +#define RTE_GSPI_MASTER_CS2_PORT_ID 1 +#if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 15 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 8 +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 30 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 51 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 15 +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 55 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 19 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif + +// GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 +// MOSI of GSPI0 +#ifndef GSPI_MASTER_MOSI_LOC +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 + +#if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 12 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 7 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 1) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 27 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 2) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 48 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 3) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 57 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 4) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 6 +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif + +// GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 +// MISO of GSPI0 +#ifndef GSPI_MASTER_MISO_LOC +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 + +#if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 11 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 6 +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 1) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 26 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 2) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 47 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 11 +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 3) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 56 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 20 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif + +#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 3 +#define RTE_FIFO_AEMPTY_THRLD 7 + +#define TX_DMA_ARB_SIZE ARBSIZE_4 +#define RX_DMA_ARB_SIZE ARBSIZE_8 +#else +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 0 +#define RTE_FIFO_AEMPTY_THRLD 0 + +#define TX_DMA_ARB_SIZE ARBSIZE_1 +#define RX_DMA_ARB_SIZE ARBSIZE_1 +#endif + +// (Generic SPI master)[Driver_GSPI_MASTER] + +// (State Configurable Timer) Interface +#define SCT_CLOCK_SOURCE M4_SOCCLKFOROTHERCLKSCT +#define SCT_CLOCK_DIV_FACT 1 + +//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 + +#ifndef SCT_IN0_LOC +#define RTE_SCT_IN_0_PORT_ID 0 + +#if (RTE_SCT_IN_0_PORT_ID == 0) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT 0 +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif + +//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 +#ifndef SCT_IN1_LOC +#define RTE_SCT_IN_1_PORT_ID 1 + +#if (RTE_SCT_IN_1_PORT_ID == 0) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 26 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#elif (RTE_SCT_IN_1_PORT_ID == 1) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 65 +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#else +#error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT 0 +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif + +//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 +#ifndef SCT_IN2_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_2_PORT_ID 0 +#else +#define RTE_SCT_IN_2_PORT_ID 1 +#endif + +#if (RTE_SCT_IN_2_PORT_ID == 0) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 27 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#elif (RTE_SCT_IN_2_PORT_ID == 1) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 66 +#define RTE_SCT_IN_2_MUX 7 +#define RTE_SCT_IN_2_PAD 24 +#elif (RTE_SCT_IN_2_PORT_ID == 2) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 70 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT 0 +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif + +//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_71 +#ifndef SCT_IN3_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_3_PORT_ID 0 +#else +#define RTE_SCT_IN_3_PORT_ID 1 +#endif + +#if (RTE_SCT_IN_3_PORT_ID == 0) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 28 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#elif (RTE_SCT_IN_3_PORT_ID == 1) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 71 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT 0 +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif + +// SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC +#define RTE_SCT_OUT_0_PORT_ID 0 +#if (RTE_SCT_OUT_0_PORT_ID == 0) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT 0 +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif + +// SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC +#define RTE_SCT_OUT_1_PORT_ID 0 +#if (RTE_SCT_OUT_1_PORT_ID == 0) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT 0 +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data +#endif + +//Pintool data +#define RTE_SCT_OUT_2_PORT 0 +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_3_PORT 0 +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_4_PORT 0 +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_5_PORT 0 +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_6_PORT 0 +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_7_PORT 0 +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +//Pintool data + +// SIO // +//<> Serial Input Output +//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 +#ifndef SIO_0_LOC +#define RTE_SIO_0_PORT_ID 0 + +#if (RTE_SIO_0_PORT_ID == 0) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 6 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 1 +#elif (RTE_SIO_0_PORT_ID == 1) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 25 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 0 //no pad +#elif (RTE_SIO_0_PORT_ID == 2) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 72 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 30 +#else +#error "Invalid RTE_SIO_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif + +//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 +#ifndef SIO_1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_1_PORT_ID 1 +#else +#define RTE_SIO_1_PORT_ID 0 +#endif + +#if (RTE_SIO_1_PORT_ID == 0) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 7 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 2 +#elif (RTE_SIO_1_PORT_ID == 1) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 26 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 0 // no pad +#elif (RTE_SIO_1_PORT_ID == 2) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 65 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 23 +#elif (RTE_SIO_1_PORT_ID == 3) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 73 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 31 +#else +#error "Invalid RTE_SIO_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif + +// SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 +#ifndef SIO_2_LOC +#define RTE_SIO_2_PORT_ID 1 + +#if (RTE_SIO_2_PORT_ID == 0) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 8 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 3 +#elif (RTE_SIO_2_PORT_ID == 1) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 27 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 0 //no pad +#elif (RTE_SIO_2_PORT_ID == 2) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 66 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 24 +#else +#error "Invalid RTE_SIO_2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif + +//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_75 +#ifndef SIO_3_LOC +#define RTE_SIO_3_PORT_ID 1 + +#if (RTE_SIO_3_PORT_ID == 0) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 9 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 4 +#elif (RTE_SIO_3_PORT_ID == 1) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 28 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 0 //no pad +#elif (RTE_SIO_3_PORT_ID == 2) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 75 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 33 +#else +#error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif + +//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_4_PORT_ID 1 +#else +#define RTE_SIO_4_PORT_ID 0 +#endif +#if (RTE_SIO_4_PORT_ID == 0) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 10 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 5 +#elif (RTE_SIO_4_PORT_ID == 1) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 29 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 0 //NO PAD +#else +#error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif + +// SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC +#define RTE_SIO_5_PORT_ID 0 +#if (RTE_SIO_5_PORT_ID == 0) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 11 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 6 +#elif (RTE_SIO_5_PORT_ID == 1) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 30 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 0 //no pad +#else +#error "Invalid RTE_SIO_5_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif + +// SIO_6 GPIO_70 +#ifndef SIO_6_LOC +#define RTE_SIO_6_PORT 0 +#define RTE_SIO_6_PIN 70 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 + +// SIO_7 <0=>GPIO_15 <1=>GPIO_71 +#ifndef SIO_7_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_7_PORT_ID 1 +#else +#define RTE_SIO_7_PORT_ID 0 +#endif + +#if (RTE_SIO_7_PORT_ID == 0) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 15 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 8 +#elif (RTE_SIO_7_PORT_ID == 1) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 71 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 29 +#else +#error "Invalid RTE_SIO_7_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif + +//<> Pulse Width Modulation +//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 +#ifndef PWM_1H_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1H_PORT_ID 0 +#else +#define RTE_PWM_1H_PORT_ID 0 +#endif + +#if (RTE_PWM_1H_PORT_ID == 0) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 7 +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#elif (RTE_PWM_1H_PORT_ID == 1) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 65 +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#else +#error "Invalid RTE_PWM_1H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_1H_PORT 0 +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif + +// PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 +#ifndef PWM_1L_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1L_PORT_ID 0 +#else +#define RTE_PWM_1L_PORT_ID 1 +#endif + +#if (RTE_PWM_1L_PORT_ID == 0) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#else +#error "Invalid RTE_PWM_1L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_1L_PORT 0 +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif + +//PWM_2H <0=>GPIO_9 +#ifndef PWM_2H_LOC +#define RTE_PWM_2H_PORT_ID 0 +#if ((RTE_PWM_2H_PORT_ID == 2)) +#error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif + +#if (RTE_PWM_2H_PORT_ID == 0) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 9 +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#else +#error "Invalid RTE_PWM_2H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_2H_PORT 0 +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif + +// PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 +#ifndef PWM_2L_LOC +#define RTE_PWM_2L_PORT_ID 0 +#if ((RTE_PWM_2L_PORT_ID == 2)) +#error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif + +#if (RTE_PWM_2L_PORT_ID == 0) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 8 +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#elif (RTE_PWM_2L_PORT_ID == 1) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 66 +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#else +#error "Invalid RTE_PWM_2L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_2L_PORT 0 +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif + +// PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC +#define RTE_PWM_3H_PORT_ID 0 +#if (RTE_PWM_3H_PORT_ID == 0) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#else +#error "Invalid RTE_PWM_3H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_3H_PORT 0 +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif + +// PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC +#define RTE_PWM_3L_PORT_ID 0 + +#if (RTE_PWM_3L_PORT_ID == 0) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#else +#error "Invalid RTE_PWM_3L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_3L_PORT 0 +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif + +// PWM_4H <0=>GPIO_15 <1=>GPIO_71 +#ifndef PWM_4H_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4H_PORT_ID 1 +#else +#define RTE_PWM_4H_PORT_ID 0 +#endif + +#if (RTE_PWM_4H_PORT_ID == 0) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 15 +#define RTE_PWM_4H_MUX 10 +#define RTE_PWM_4H_PAD 8 +#elif (RTE_PWM_4H_PORT_ID == 1) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 71 +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +#else +#error "Invalid RTE_PWM_4H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif + +// PWM_4H <0=>GPIO_12 <1=>GPIO_70 +#ifndef PWM_4L_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4L_PORT_ID 1 +#else +#define RTE_PWM_4L_PORT_ID 0 +#endif + +#if (RTE_PWM_4L_PORT_ID == 0) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 12 +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#elif (RTE_PWM_4L_PORT_ID == 1) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 70 +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#else +#error "Invalid RTE_PWM_4L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_4L_PORT 0 +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif + +// PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC +#define RTE_PWM_FAULTA_PORT_ID 0 + +#if (RTE_PWM_FAULTA_PORT_ID == 0) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 25 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#elif (RTE_PWM_FAULTA_PORT_ID == 2) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 73 +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#else +#error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT 0 +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif + +// PWM_FAULTB <0=>GPIO_26 +#ifndef PWM_FAULTB_LOC +#define RTE_PWM_FAULTB_PORT_ID 0 + +#if (RTE_PWM_FAULTB_PORT_ID == 0) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 26 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#else +#error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT 0 +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + +//PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC +#define RTE_PWM_SLP_EVENT_TRIG_PORT 0 +#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT 0 +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 + +//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC +#define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 + +#if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#else +#error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC +#define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 + +#if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#else +#error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT 0 +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT 0 +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data + +//<> QEI (Quadrature Encode Interface) + +//QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_71 <4=>GPIO_73 <5=>GPIO_11 <6=>GPIO_34 + +#define RTE_QEI_DIR_PORT_ID 3 + +#if (RTE_QEI_DIR_PORT_ID == 0) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 28 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 0 //no pad +#elif (RTE_QEI_DIR_PORT_ID == 1) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 49 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 13 +#elif (RTE_QEI_DIR_PORT_ID == 2) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 57 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 21 +#elif (RTE_QEI_DIR_PORT_ID == 3) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 71 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 29 +#elif (RTE_QEI_DIR_PORT_ID == 4) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 73 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 31 +#else +#error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" +#endif + +//QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 + +#define RTE_QEI_IDX_PORT_ID 3 + +#if (RTE_QEI_IDX_PORT_ID == 0) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 25 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 0 //no pad +#elif (RTE_QEI_IDX_PORT_ID == 1) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 46 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 10 +#elif (RTE_QEI_IDX_PORT_ID == 2) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 52 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 16 +#elif (RTE_QEI_IDX_PORT_ID == 3) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 72 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 30 +#else +#error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" +#endif + +//QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHA_PORT_ID 3 +#else +#define RTE_QEI_PHA_PORT_ID 5 +#endif + +#if (RTE_QEI_PHA_PORT_ID == 0) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 26 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 0 //no pad +#elif (RTE_QEI_PHA_PORT_ID == 1) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 47 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 11 +#elif (RTE_QEI_PHA_PORT_ID == 2) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 53 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 17 +#elif (RTE_QEI_PHA_PORT_ID == 3) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 65 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 23 +#elif (RTE_QEI_PHA_PORT_ID == 4) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 73 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 31 +#else +#error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" +#endif + +//QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <2=>GPIO_56 <3=>GPIO_66 <4=>GPIO_70 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHB_PORT_ID 4 +#else +#define RTE_QEI_PHB_PORT_ID 3 +#endif + +#if (RTE_QEI_PHB_PORT_ID == 0) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 27 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 0 //no pad +#elif (RTE_QEI_PHB_PORT_ID == 1) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 48 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 12 +#elif (RTE_QEI_PHB_PORT_ID == 2) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 56 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 20 +#elif (RTE_QEI_PHB_PORT_ID == 3) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 66 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 24 +#elif (RTE_QEI_PHB_PORT_ID == 4) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 70 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 28 +#else +#error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" +#endif + +#endif +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + +#define RTE_GPIO_6_PORT 0 +#define RTE_GPIO_6_PAD 1 +#define RTE_GPIO_6_PIN 6 +#define RTE_GPIO_6_MODE 0 + +#define RTE_GPIO_7_PORT 0 +#define RTE_GPIO_7_PAD 2 +#define RTE_GPIO_7_PIN 7 +#define RTE_GPIO_7_MODE 0 + +#define RTE_GPIO_8_PORT 0 +#define RTE_GPIO_8_PAD 3 +#define RTE_GPIO_8_PIN 8 +#define RTE_GPIO_8_MODE 0 + +#define RTE_GPIO_9_PORT 0 +#define RTE_GPIO_9_PAD 4 +#define RTE_GPIO_9_PIN 9 +#define RTE_GPIO_9_MODE 0 + +#define RTE_GPIO_10_PORT 0 +#define RTE_GPIO_10_PAD 5 +#define RTE_GPIO_10_PIN 10 +#define RTE_GPIO_10_MODE 0 + +#define RTE_GPIO_11_PORT 0 +#define RTE_GPIO_11_PAD 6 +#define RTE_GPIO_11_PIN 11 +#define RTE_GPIO_11_MODE 0 + +#define RTE_GPIO_12_PORT 0 +#define RTE_GPIO_12_PAD 7 +#define RTE_GPIO_12_PIN 12 +#define RTE_GPIO_12_MODE 0 + +#define RTE_GPIO_15_PORT 0 +#define RTE_GPIO_15_PAD 8 +#define RTE_GPIO_15_PIN 15 +#define RTE_GPIO_15_MODE 0 + +#define RTE_GPIO_25_PORT 0 +#define RTE_GPIO_25_PIN 25 +#define RTE_GPIO_25_MODE 0 + +#define RTE_GPIO_26_PORT 0 +#define RTE_GPIO_26_PIN 26 +#define RTE_GPIO_26_MODE 0 + +#define RTE_GPIO_27_PORT 0 +#define RTE_GPIO_27_PIN 27 +#define RTE_GPIO_27_MODE 0 + +#define RTE_GPIO_28_PORT 0 +#define RTE_GPIO_28_PIN 28 +#define RTE_GPIO_28_MODE 0 + +#define RTE_GPIO_29_PORT 0 +#define RTE_GPIO_29_PIN 29 +#define RTE_GPIO_29_MODE 0 + +#define RTE_GPIO_30_PORT 0 +#define RTE_GPIO_30_PIN 30 +#define RTE_GPIO_30_MODE 0 + +#define RTE_GPIO_31_PORT 0 +#define RTE_GPIO_31_PAD 9 +#define RTE_GPIO_31_PIN 31 +#define RTE_GPIO_31_MODE 0 + +#define RTE_GPIO_32_PORT 0 +#define RTE_GPIO_32_PAD 9 +#define RTE_GPIO_32_PIN 32 +#define RTE_GPIO_32_MODE 0 + +#define RTE_GPIO_33_PORT 0 +#define RTE_GPIO_33_PAD 9 +#define RTE_GPIO_33_PIN 33 +#define RTE_GPIO_33_MODE 0 + +#define RTE_GPIO_34_PORT 0 +#define RTE_GPIO_34_PAD 9 +#define RTE_GPIO_34_PIN 34 +#define RTE_GPIO_34_MODE 0 + +#define RTE_GPIO_46_PORT 0 +#define RTE_GPIO_46_PAD 10 +#define RTE_GPIO_46_PIN 46 +#define RTE_GPIO_46_MODE 0 + +#define RTE_GPIO_47_PORT 0 +#define RTE_GPIO_47_PAD 11 +#define RTE_GPIO_47_PIN 47 +#define RTE_GPIO_47_MODE 0 + +#define RTE_GPIO_48_PORT 0 +#define RTE_GPIO_48_PAD 12 +#define RTE_GPIO_48_PIN 48 +#define RTE_GPIO_48_MODE 0 + +#define RTE_GPIO_49_PORT 0 +#define RTE_GPIO_49_PAD 13 +#define RTE_GPIO_49_PIN 49 +#define RTE_GPIO_49_MODE 0 + +#define RTE_GPIO_50_PORT 0 +#define RTE_GPIO_50_PAD 14 +#define RTE_GPIO_50_PIN 50 +#define RTE_GPIO_50_MODE 0 + +#define RTE_GPIO_51_PORT 0 +#define RTE_GPIO_51_PAD 15 +#define RTE_GPIO_51_PIN 51 +#define RTE_GPIO_51_MODE 0 + +#define RTE_GPIO_52_PORT 0 +#define RTE_GPIO_52_PAD 16 +#define RTE_GPIO_52_PIN 52 +#define RTE_GPIO_52_MODE 0 + +#define RTE_GPIO_53_PORT 0 +#define RTE_GPIO_53_PAD 17 +#define RTE_GPIO_53_PIN 53 +#define RTE_GPIO_53_MODE 0 + +#define RTE_GPIO_54_PORT 0 +#define RTE_GPIO_54_PAD 18 +#define RTE_GPIO_54_PIN 54 +#define RTE_GPIO_54_MODE 0 + +#define RTE_GPIO_55_PORT 0 +#define RTE_GPIO_55_PAD 19 +#define RTE_GPIO_55_PIN 55 +#define RTE_GPIO_55_MODE 0 + +#define RTE_GPIO_56_PORT 0 +#define RTE_GPIO_56_PAD 20 +#define RTE_GPIO_56_PIN 56 +#define RTE_GPIO_56_MODE 0 + +#define RTE_GPIO_57_PORT 0 +#define RTE_GPIO_57_PAD 21 +#define RTE_GPIO_57_PIN 57 +#define RTE_GPIO_57_MODE 0 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_0_PORT_ID 1 +#else +#define RTE_ULP_GPIO_0_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_0_PORT_ID == 0) +#define RTE_ULP_GPIO_0_PORT 0 +#define RTE_ULP_GPIO_0_PAD 22 +#define RTE_ULP_GPIO_0_PIN 64 +#define RTE_ULP_GPIO_0_MODE 0 +#elif (RTE_ULP_GPIO_0_PORT_ID == 1) +#define RTE_ULP_GPIO_0_PORT 4 +#define RTE_ULP_GPIO_0_PIN 0 +#define RTE_ULP_GPIO_0_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_0_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_1_PORT_ID 1 +#else +#define RTE_ULP_GPIO_1_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_1_PORT_ID == 0) +#define RTE_ULP_GPIO_1_PORT 0 +#define RTE_ULP_GPIO_1_PAD 23 +#define RTE_ULP_GPIO_1_PIN 65 +#define RTE_ULP_GPIO_1_MODE 0 +#elif (RTE_ULP_GPIO_1_PORT_ID == 1) +#define RTE_ULP_GPIO_1_PORT 4 +#define RTE_ULP_GPIO_1_PIN 1 +#define RTE_ULP_GPIO_1_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_1_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_2_PORT_ID 1 +#else +#define RTE_ULP_GPIO_2_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_2_PORT_ID == 0) +#define RTE_ULP_GPIO_2_PORT 0 +#define RTE_ULP_GPIO_2_PAD 24 +#define RTE_ULP_GPIO_2_PIN 66 +#define RTE_ULP_GPIO_2_MODE 0 +#elif (RTE_ULP_GPIO_2_PORT_ID == 1) +#define RTE_ULP_GPIO_2_PORT 4 +#define RTE_ULP_GPIO_2_PIN 2 +#define RTE_ULP_GPIO_2_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_2_PIN Pin Configuration!" +#endif + +#define RTE_ULP_GPIO_3_PORT_ID 1 + +#if (RTE_ULP_GPIO_3_PORT_ID == 1) +#define RTE_ULP_GPIO_3_PORT 4 +#define RTE_ULP_GPIO_3_PIN 3 +#define RTE_ULP_GPIO_3_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_3_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_4_PORT_ID 1 +#else +#define RTE_ULP_GPIO_4_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_4_PORT_ID == 0) +#define RTE_ULP_GPIO_4_PORT 0 +#define RTE_ULP_GPIO_4_PAD 26 +#define RTE_ULP_GPIO_4_PIN 68 +#define RTE_ULP_GPIO_4_MODE 0 +#elif (RTE_ULP_GPIO_4_PORT_ID == 1) +#define RTE_ULP_GPIO_4_PORT 4 +#define RTE_ULP_GPIO_4_PIN 4 +#define RTE_ULP_GPIO_4_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_4_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_5_PORT_ID 1 +#else +#define RTE_ULP_GPIO_5_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_5_PORT_ID == 0) +#define RTE_ULP_GPIO_5_PORT 4 +#define RTE_ULP_GPIO_5_PAD 27 +#define RTE_ULP_GPIO_5_PIN 69 +#define RTE_ULP_GPIO_5_MODE 0 +#elif (RTE_ULP_GPIO_5_PORT_ID == 1) +#define RTE_ULP_GPIO_5_PORT 4 +#define RTE_ULP_GPIO_5_PIN 5 +#define RTE_ULP_GPIO_5_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_5_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_6_PORT_ID 1 +#else +#define RTE_ULP_GPIO_6_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_6_PORT_ID == 0) +#define RTE_ULP_GPIO_6_PORT 4 +#define RTE_ULP_GPIO_6_PAD 28 +#define RTE_ULP_GPIO_6_PIN 70 +#define RTE_ULP_GPIO_6_MODE 0 +#elif (RTE_ULP_GPIO_6_PORT_ID == 1) +#define RTE_ULP_GPIO_6_PORT 4 +#define RTE_ULP_GPIO_6_PIN 6 +#define RTE_ULP_GPIO_6_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_6_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_7_PORT_ID 1 +#else +#define RTE_ULP_GPIO_7_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_7_PORT_ID == 0) +#define RTE_ULP_GPIO_7_PORT 4 +#define RTE_ULP_GPIO_7_PAD 29 +#define RTE_ULP_GPIO_7_PIN 71 +#define RTE_ULP_GPIO_7_MODE 0 +#elif (RTE_ULP_GPIO_7_PORT_ID == 1) +#define RTE_ULP_GPIO_7_PORT 4 +#define RTE_ULP_GPIO_7_PIN 7 +#define RTE_ULP_GPIO_7_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_7_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_8_PORT_ID 1 +#else +#define RTE_ULP_GPIO_8_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_8_PORT_ID == 0) +#define RTE_ULP_GPIO_8_PORT 4 +#define RTE_ULP_GPIO_8_PAD 30 +#define RTE_ULP_GPIO_8_PIN 72 +#define RTE_ULP_GPIO_8_MODE 0 +#elif (RTE_ULP_GPIO_8_PORT_ID == 1) +#define RTE_ULP_GPIO_8_PORT 4 +#define RTE_ULP_GPIO_8_PIN 8 +#define RTE_ULP_GPIO_8_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_8_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_9_PORT_ID 1 +#else +#define RTE_ULP_GPIO_9_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_9_PORT_ID == 0) +#define RTE_ULP_GPIO_9_PORT 4 +#define RTE_ULP_GPIO_9_PAD 31 +#define RTE_ULP_GPIO_9_PIN 73 +#define RTE_ULP_GPIO_9_MODE 0 +#elif (RTE_ULP_GPIO_9_PORT_ID == 1) +#define RTE_ULP_GPIO_9_PORT 4 +#define RTE_ULP_GPIO_9_PIN 9 +#define RTE_ULP_GPIO_9_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_9_PIN Pin Configuration!" +#endif + +#define RTE_ULP_GPIO_10_PORT_ID 0 + +#if (RTE_ULP_GPIO_10_PORT_ID == 0) +#define RTE_ULP_GPIO_10_PORT 4 +#define RTE_ULP_GPIO_10_PIN 10 +#define RTE_ULP_GPIO_10_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_10_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_11_PORT_ID 1 +#else +#define RTE_ULP_GPIO_11_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_11_PORT_ID == 0) +#define RTE_ULP_GPIO_11_PORT 4 +#define RTE_ULP_GPIO_11_PAD 33 +#define RTE_ULP_GPIO_11_PIN 75 +#define RTE_ULP_GPIO_11_MODE 0 +#elif (RTE_ULP_GPIO_11_PORT_ID == 1) +#define RTE_ULP_GPIO_11_PORT 4 +#define RTE_ULP_GPIO_11_PIN 11 +#define RTE_ULP_GPIO_11_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_11_PIN Pin Configuration!" +#endif + +// RTE_UULP_GPIO_x_PORT refers to port for UULP GPIO pin x +#define RTE_UULP_GPIO_0_PORT 5 +#define RTE_UULP_GPIO_0_PIN 0 +#define RTE_UULP_GPIO_0_MODE 0 + +#define RTE_UULP_GPIO_1_PORT 5 +#define RTE_UULP_GPIO_1_PIN 1 +#define RTE_UULP_GPIO_1_MODE 0 + +#define RTE_UULP_GPIO_2_PORT 5 +#define RTE_UULP_GPIO_2_PIN 2 +#define RTE_UULP_GPIO_2_MODE 0 + +#define RTE_UULP_GPIO_3_PORT 5 +#define RTE_UULP_GPIO_3_PIN 3 +#define RTE_UULP_GPIO_3_MODE 0 + +#define RTE_UULP_GPIO_4_PORT 5 +#define RTE_UULP_GPIO_4_PIN 4 +#define RTE_UULP_GPIO_4_MODE 0 + +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + +// ULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_ULP +#define SENSOR_ENABLE_GPIO_PORT RTE_ULP_GPIO_2_PORT +#define SENSOR_ENABLE_GPIO_PIN RTE_ULP_GPIO_2_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 4 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 5 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/matter/si91x/siwx917/BRD4343A/config/SEGGER_RTT_Conf.h b/matter/si91x/siwx917/BRD4343A/config/SEGGER_RTT_Conf.h new file mode 100644 index 0000000000..91283ff736 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/SEGGER_RTT_Conf.h @@ -0,0 +1,428 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2023 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.52 * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 24316 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +// +// Take in and set to correct values for Cortex-A systems with CPU cache +// +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// +// Most common case: +// Up-channel 0: RTT +// Up-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (9) // Max. number of up-buffers (T->H) available on this target (Default: 9) +#endif +// +// Most common case: +// Down-channel 0: RTT +// Down-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (9) // Max. number of down-buffers (H->T) available on this target (Default: 9) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RL78 +*/ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for CCRX +*/ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/matter/si91x/siwx917/BRD4343A/config/emlib_core_debug_config.h b/matter/si91x/siwx917/BRD4343A/config/emlib_core_debug_config.h new file mode 100644 index 0000000000..07ee9b9efb --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/emlib_core_debug_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/glib_config.h b/matter/si91x/siwx917/BRD4343A/config/glib_config.h new file mode 100644 index 0000000000..47c3291015 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/glib_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief GLIB Config. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_GLIB_CONFIG_H +#define SL_GLIB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Fonts configuration + +// Default font, 8x8 +// Include/exclude the font. +// Default: 1 +#define SL_GLIB_FONTNORMAL_8X8 1 + +// Narrow font, 6x8 +// Include/exclude the font. +// Default: 1 +#define SL_GLIB_FONTNARROW_6X8 1 + +// Number only font, 16x20 +// Include/exclude the font. +// Default: 1 +#define SL_GLIB_FONTNUMBER_16X20 1 + +// + +// <<< end of configuration section >>> + +#endif // SL_GLIB_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/nvm3_default_config.h b/matter/si91x/siwx917/BRD4343A/config/nvm3_default_config.h new file mode 100644 index 0000000000..7cd7f1f1e4 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/nvm3_default_config.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* @file nvm3_default_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef NVM3_DEFAULT_CONFIG_H +#define NVM3_DEFAULT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// NVM3 Default Instance Configuration + +#ifndef NVM3_DEFAULT_CACHE_SIZE +// NVM3 Default Instance Cache Size +// Number of NVM3 objects to cache. To reduce access times this number +// should be equal to or higher than the number of NVM3 objects in the +// default NVM3 instance. +// Default: 200 +#define NVM3_DEFAULT_CACHE_SIZE 200 +#endif + +#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE +// NVM3 Default Instance Max Object Size +// Max NVM3 object size that can be stored. +// Default: 254 +#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 +#endif + +#ifndef NVM3_DEFAULT_REPACK_HEADROOM +// NVM3 Default Instance User Repack Headroom +// Headroom determining how many bytes below the forced repack limit the user +// repack limit should be placed. The default is 0, which means the user and +// forced repack limits are equal. +// Default: 0 +#define NVM3_DEFAULT_REPACK_HEADROOM 0 +#endif + +#ifndef NVM3_DEFAULT_NVM_SIZE +// NVM3 Default Instance Size +// Size of the NVM3 storage region in flash. This size should be aligned with +// the flash page size of the device. +// Default: 36864 +#define NVM3_DEFAULT_NVM_SIZE 36864 +#endif + +// + +// <<< end of configuration section >>> + +#endif // NVM3_DEFAULT_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/pin_config.h b/matter/si91x/siwx917/BRD4343A/config/pin_config.h new file mode 100644 index 0000000000..2bbc8c59c3 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/psa_crypto_config.h b/matter/si91x/siwx917/BRD4343A/config/psa_crypto_config.h new file mode 100644 index 0000000000..7909932a54 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/psa_crypto_config.h @@ -0,0 +1,130 @@ +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// Key management configuration + +// PSA User Maximum Open Keys Count <0-128> +// Maximum amount of keys that the user application will have open +// simultaneously. In context of PSA Crypto, an open key means any key +// either stored in RAM (lifetime set to PSA_KEY_LIFETIME_VOLATILE), or +// used as part of a cryptographic operation. +// When using a key for a multi-part (setup/update/finish) operation, a key +// is considered to be open from the moment the operation is successfully +// setup, until it finishes or aborts. +// When an application tries to open more keys than this value accounts for, +// the PSA API may return PSA_ERROR_INSUFFICIENT_MEMORY. Keep in mind that +// other software included in the application (e.g. wireless protocol +// stacks) also can have a need to have open keys in PSA Crypto. This could +// lead to a race condition when the application key slot count is set too +// low for the actual usage of the application, as a software stack may not +// fail gracefully in case an application opens more than its declared +// amount of keys, thereby precluding the stack from functioning. +// Default: 4 +#define SL_PSA_KEY_USER_SLOT_COUNT (4) + +// PSA Maximum User Persistent Keys Count <0-1024> +// Maximum amount of keys (or other files) that can be stored persistently +// by the application through the PSA interface, when persistent storage +// support for PSA Crypto is included in the project. +// Due to caching logic, this setting does have an impact on static RAM +// usage. Note that this number is added to the potential requirements from +// other software components in the project, such that the total amount of +// keys which can be stored through the ITS backend can be higher than what +// is configured here. WARNING: When changing this setting on an +// application that is already deployed, and thus will get the change +// through an application upgrade, care should be taken to ensure that the +// setting is only ever increased, and never decreased. Decreasing this +// setting might cause previously stored keys/files to become inaccessible. +// +// It is not possible to change this setting when using V3 ITS Driver. +// The file-storage indexing is dependent on the maximum number of files, +// and if SL_PSA_ITS_USER_MAX_FILES is changed, ITS should be cleared and +// all files need to be stored again. +// Default: 128 +#define SL_PSA_ITS_USER_MAX_FILES (128) + +// Enable V1 Format Support For ITS Files <0-1> +// Devices that used PSA ITS together with gecko_sdk_3.1.x or earlier +// might have keys (or other files) stored in V1 format. +// If no v1 files are used, its support can be disabled for space +// optimization. +// Default: 0 +#define SL_PSA_ITS_SUPPORT_V1_DRIVER 0 + +// Enable V2 ITS Driver Support <0-1> +// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys +// (or other files) stored using different address range. Enabling this +// config option adds upgrade code which converts V2 (and V1 if +// supported) format ITS keys/files to the latest V3 format. Update is +// fully automatic, needs to be run once and require extra flash space of +// approximately the size of the largest key. +// V1 ITS driver support can be disabled if the device has never used ITS +// driver before in GSDK 4.1.x and earlier, or the keys has been already +// migrated. +// Default: 0 +#define SL_PSA_ITS_SUPPORT_V2_DRIVER 0 + +// Enable support for V3 ITS Driver <0-1> +// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys +// (or other files) stored using different address range. In rare case +// that those devices have full nvm3 and not enough space for the +// upgrade, (that requires an extra space to store largest key in memory +// twice), this config option can disable v3 driver and use v2 one. +// To upgrade the device, make space for the upgrade, and enable v3 driver +// again. WARNING: When using V3 driver, it is not possible to increase +// or decrease the value of SL_PSA_ITS_USER_MAX_FILES. If the change of +// SL_PSA_ITS_USER_MAX_FILES is required, ITS should be cleared and all +// files need to be stored again. Default: 1 +#define SL_PSA_ITS_SUPPORT_V3_DRIVER 1 + +// Built-in AES Key Mode of Operation +// CTR Mode +// CFB Mode +// OFB Mode +// ECB Mode +// CBC Mode (no padding) +// CBC Mode (PKCS#7 padding) +// PSA Crypto only allows one specific usage algorithm per built-in key ID. +// Default: PSA_ALG_CTR +#define SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG (PSA_ALG_CTR) + +#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG +// Built-in PUF Key Algorithm +// PBKDF2 (CMAC-AES-128-PRF) +// CMAC +// PSA Crypto only allows one specific usage algorithm per built-in key ID. +// It is recommended to only use the PUF key for deriving further key +// material. +// Default: PSA_ALG_PBKDF2_AES_CMAC_PRF_128 +#define SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG (PSA_ALG_PBKDF2_AES_CMAC_PRF_128) +#endif // SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Sub-files + +#if defined(SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE) +#include SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE +#else +#include "sli_psa_config_autogen.h" +#endif + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +#include "sli_psa_tfm_translation.h" +#endif + +#if SL_MBEDTLS_DRIVERS_ENABLED +#include "sli_psa_acceleration.h" +#endif + +#include "sli_psa_builtin_config_autogen.h" + +#endif // PSA_CRYPTO_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_board_configuration.h b/matter/si91x/siwx917/BRD4343A/config/sl_board_configuration.h new file mode 100644 index 0000000000..635fe5f8a2 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_board_configuration.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* @file sl_board_configuration.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include + +#define DEFAULT_UART NULL +#define DEFAULT_UART_PIN_CONFIG NULL diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_board_control.h b/matter/si91x/siwx917/BRD4343A/config/sl_board_control.h new file mode 100644 index 0000000000..8b85d7553a --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_board_control.h @@ -0,0 +1,22 @@ +/******************************************************************************* +* @file sl_board_control.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include "sl_status.h" + +sl_status_t sl_board_enable_vcom(void); diff --git a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_core_config.h similarity index 80% rename from matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h rename to matter/si91x/siwx917/BRD4343A/config/sl_core_config.h index 921e7a507c..27b173d2eb 100644 --- a/matter/si91x/siwx917/BRD4338A/config/sl_si91x_ulp_uart_common_config.h +++ b/matter/si91x/siwx917/BRD4343A/config/sl_core_config.h @@ -1,6 +1,6 @@ -/***************************************************************************/ /** - * @file sl_si91x_ulp_uart_common_config.h - * @brief SL SI91X ULP UART Common Config. +/***************************************************************************//** + * @file + * @brief sl_core Configuration ******************************************************************************* * # License * Copyright 2023 Silicon Laboratories Inc. www.silabs.com @@ -28,16 +28,17 @@ * ******************************************************************************/ -#ifndef SL_SI91X_ULP_UART_COMMON_CONFIG_H -#define SL_SI91X_ULP_UART_COMMON_CONFIG_H +#ifndef SL_CORE_CONFIG_H +#define SL_CORE_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// DMA Configuration -// ULP UART DMA -// Default: 1 -#define SL_ULPUART_DMA_CONFIG_ENABLE 0 +// Core Abstraction Configuration +// Enables measurement of interrupt masking time for debugging purposes. +// Default: 0 +#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0 // + // <<< end of configuration section >>> -#endif // SL_SI91X_ULP_UART_COMMON_CONFIG_H +#endif // SL_CORE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_config.h new file mode 100644 index 0000000000..bf38c462ff --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_config.h @@ -0,0 +1,118 @@ +#ifndef SL_MBEDTLS_CONFIG_H +#define SL_MBEDTLS_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// TLS/DTLS configuration + +// Complete list of ciphersuites to use, in order of preference. +// Default: MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 +// Complete list of ciphersuites to use, in order of preference. +// The value of this configuration should be updated for the application needs. +#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + +// Maximum TLS/DTLS fragment length in bytes (input). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when receiving data. +#define SL_MBEDTLS_SSL_IN_CONTENT_LEN 768 + +// Maximum TLS/DTLS fragment length in bytes (output). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when sending data. +#define SL_MBEDTLS_SSL_OUT_CONTENT_LEN 768 + +// Enable support for RFC 6066 max_fragment_length extension in SSL. +// Default: 1 +// Enable support for RFC 6066 max_fragment_length extension in SSL. +#define SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1 + +// Enable support for exporting key block and master secret. +// Default: 1 +// Enable support for exporting key block and master secret. +// This is required for certain users of TLS, e.g. EAP-TLS. +#define SL_MBEDTLS_SSL_EXPORT_KEYS 1 + +// Enable the PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED 0 + +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED 0 + +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED 0 + +// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED 0 + +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED 0 + +// Enable parsing of the compressed curves. +// Default: 0 +// Enable parsing of the compressed curves. +#define SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING 0 + +// + +// RSA configuration + +// Disable use of the Chinese Remainder Theorem for RSA. +// Default: 0 +// Disable use of the Chinese Remainder Theorem for RSA private key +// computations. +#define SL_MBEDTLS_RSA_NO_CRT 0 + +// + +// Miscellaneous configuration + +// Enable Silicon Labs' Mbed TLS- and PSA Crypto drivers. +// Default: 1 +// Enable drivers for hardware acceleration (Mbed TLS and PSA Crypto) and +// secure key handling (PSA Crypto). +#define SL_MBEDTLS_DRIVERS_ENABLED 1 + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Sub-files + +#if defined(SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE) +#include SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE +#else +#include "sli_mbedtls_config_autogen.h" +#endif + +#include "sli_mbedtls_omnipresent.h" + +#if SL_MBEDTLS_DRIVERS_ENABLED +#include "sli_mbedtls_acceleration.h" +#endif + +#include "sl_mbedtls_device_config.h" + +// Include transformation logic to apply CMSIS-config configuration options to +// the correct Mbed TLS / PSA Crypto options. +#include "sli_mbedtls_config_transform_autogen.h" + +// Included for backward compatibility reasons. +#include "mbedtls/build_info.h" + +#endif // SL_MBEDTLS_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_device_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_device_config.h new file mode 100644 index 0000000000..fd0858c964 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_mbedtls_device_config.h @@ -0,0 +1,70 @@ +#ifndef SL_MBEDTLS_DEVICE_CONFIG_H +#define SL_MBEDTLS_DEVICE_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// Secure Engine (SE) version configuration + +// Support SE firmware versions older +// than 1.2.2 <0-1> Enable software fallback for ECDH and ECC public key +// validation on xG21 devices running SE firmware versions lower than 1.2.2. +// +// Due to other stability concerns, it is strongly recommended to upgrade +// these devices to the latest firmware revision instead of turning on +// software fallback support. +// +// Not having fallback support will make ECDH operations, as well as PSA +// Crypto public key import, return an error code on affected devices. +// +// Default: 0 +#define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 0 + +// Assume an SE firmware version newer +// than 1.2.2 <0-1> For enhanced performance: if it is guaranteed that all +// devices on which this library will run are updated to at least SE +// FW 1.2.2, then turning on this option will remove certain fallback +// checks, thereby reducing the amount of processing required for ECDH and +// public key verification operations. Default: 0 +#define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 0 + +// Assume an SE firmware +// version that is unaffected by Ed25519 errata <0-1> For minimal code size +// and performance savings: if it is guaranteed that none of the devices +// running this library has SE FWs in the range [1.2.2, 1.2.8], then +// enabling this option will disable runtime version checks. Default: 0 +#define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 0 + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Additional SE version related logic (DO NOT MODIFY) + +// SL_SE_ASSUME_FW_AT_LEAST_1_2_10 is no longer in use, however, it is kept here +// for backwards compatibility. */ +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) +#undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 +#define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 +#undef SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA +#define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 1 +#endif + +// SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2 is no longer in use, however, it is kept +// here for backwards compatibility. */ +#if defined(SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2) +#undef SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 +#define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 1 +#endif + +// SLI_SE_ASSUME_FW_AT_LEAST_1_2_2 is no longer in use, however, it is kept +// here for backwards compatibility. */ +#if defined(SLI_SE_ASSUME_FW_AT_LEAST_1_2_2) +#undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 +#define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 +#endif + +#endif // SL_MBEDTLS_DEVICE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_config.h new file mode 100644 index 0000000000..7e4b056778 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap Allocator configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_CONFIG_H +#define SL_MEMORY_MANAGER_CONFIG_H + +// Memory Manager Configuration + +// Minimum block allocation size +// <32-128:8> +// Minimum block allocation size to avoid creating a block too small while splitting up an allocated block. +// Size expressed in bytes and can only be a multiple of 8 bytes for the proper data alignment management done by the dynamic allocator malloc() function. +// Default: 32 +#define SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE (32) + +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_region_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_region_config.h new file mode 100644 index 0000000000..ba02fdd8f3 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_memory_manager_region_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap and stack size configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_REGION_CONFIG_H +#define SL_MEMORY_MANAGER_REGION_CONFIG_H + +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE +#define SL_STACK_SIZE 4096 +#endif +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_REGION_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_net_default_values.h b/matter/si91x/siwx917/BRD4343A/config/sl_net_default_values.h new file mode 100644 index 0000000000..ffe3767f49 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_net_default_values.h @@ -0,0 +1,149 @@ +/******************************************************************************* +* @file sl_net_default_values.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include "sl_net_wifi_types.h" + +#if defined(__GNUC__) +// Ignore warning of unused variables. It is expected that some or all of these are unused +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +#ifdef SLI_SI91X_ENABLE_IPV6 +#define REQUIRED_IP_TYPE SL_IPV6 +#else +#define REQUIRED_IP_TYPE SL_IPV4 +#endif + +#ifndef DEFAULT_WIFI_CLIENT_PROFILE_SSID +#define DEFAULT_WIFI_CLIENT_PROFILE_SSID "YOUR_AP_SSID" +#endif + +#ifndef DEFAULT_WIFI_CLIENT_CREDENTIAL +#define DEFAULT_WIFI_CLIENT_CREDENTIAL "YOUR_AP_PASSPHRASE" +#endif + +#ifndef DEFAULT_WIFI_AP_PROFILE_SSID +#define DEFAULT_WIFI_AP_PROFILE_SSID "MY_AP_SSID" +#endif + +#ifndef DEFAULT_WIFI_AP_CREDENTIAL +#define DEFAULT_WIFI_AP_CREDENTIAL "MY_AP_PASSPHRASE" +#endif + +#ifndef DEFAULT_WIFI_CLIENT_SECURITY_TYPE +#define DEFAULT_WIFI_CLIENT_SECURITY_TYPE SL_WIFI_WPA2 +#endif + +#ifndef DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE +#define DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE SL_WIFI_DEFAULT_ENCRYPTION +#endif + +//! IP address of the module +//! E.g: 0x0A0AA8C0 == 192.168.10.10 +#ifndef DEFAULT_WIFI_MODULE_IP_ADDRESS +#define DEFAULT_WIFI_MODULE_IP_ADDRESS 0x0A0AA8C0 +#endif + +//! IP address of netmask +//! E.g: 0x00FFFFFF == 255.255.255.0 +#ifndef DEFAULT_WIFI_SN_MASK_ADDRESS +#define DEFAULT_WIFI_SN_MASK_ADDRESS 0x00FFFFFF +#endif + +//! IP address of Gateway +//! E.g: 0x0A0AA8C0 == 192.168.10.10 +#ifndef DEFAULT_WIFI_GATEWAY_ADDRESS +#define DEFAULT_WIFI_GATEWAY_ADDRESS 0x0A0AA8C0 +#endif + +#define DEFAULT_WIFI_CLIENT_PROFILE \ + (sl_net_wifi_client_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_CLIENT_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_CLIENT_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .channel_bitmap.channel_bitmap_2_4 = SL_WIFI_DEFAULT_CHANNEL_BITMAP, \ + .bssid = {{0}}, \ + .bss_type = SL_WIFI_BSS_TYPE_INFRASTRUCTURE, \ + .security = DEFAULT_WIFI_CLIENT_SECURITY_TYPE, \ + .encryption = DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE, \ + .client_options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_DHCP, \ + .type = REQUIRED_IP_TYPE, \ + .host_name = NULL, \ + .ip = {{{0}}}, \ + } \ + } + +#define DEFAULT_WIFI_ACCESS_POINT_PROFILE \ + (sl_net_wifi_ap_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_AP_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_AP_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .security = SL_WIFI_WPA2, \ + .encryption = SL_WIFI_CCMP_ENCRYPTION, \ + .rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO, \ + .options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, \ + .keepalive_type = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE, \ + .beacon_interval = 100, \ + .client_idle_timeout = 0xFF, \ + .dtim_beacon_count = 3, \ + .maximum_clients = 3, \ + .beacon_stop = 0, \ + .tdi_flags =SL_WIFI_TDI_NONE, \ + .is_11n_enabled = 1, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_STATIC_IP, \ + .type = SL_IPV4, \ + .host_name = NULL, \ + .ip = { \ + .v4.ip_address.value = DEFAULT_WIFI_MODULE_IP_ADDRESS, \ + .v4.gateway.value = DEFAULT_WIFI_GATEWAY_ADDRESS, \ + .v4.netmask.value = DEFAULT_WIFI_SN_MASK_ADDRESS \ + }, \ + } \ + } + +static sl_net_wifi_psk_credential_entry_t default_wifi_client_credential = { + .type = SL_NET_WIFI_PSK, + .data_length = sizeof(DEFAULT_WIFI_CLIENT_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_CLIENT_CREDENTIAL +}; + +static sl_net_wifi_psk_credential_entry_t default_wifi_ap_credential = { .type = SL_NET_WIFI_PSK, + .data_length = + sizeof(DEFAULT_WIFI_AP_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_AP_CREDENTIAL }; +#if defined(__GNUC__) +// Restore GCC diagnostics +#pragma GCC diagnostic pop +#endif diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn0_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn0_config.h new file mode 100644 index 0000000000..e08670e8f1 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn0_config.h @@ -0,0 +1,42 @@ +/***************************************************************************/ /** + * @file sl_si91x_button_init_btn0_config.h + * @brief Button Driver Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_BUTTON_INIT_BTN0_CONFIG_H +#define SL_SI91X_BUTTON_INIT_BTN0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Button Interrupt Configuration +// High level interrupt +// Low level interrupt +// High level and low level interrupt +// Rise edge interrupt +// Fall edge interrupt +// Rise edge and fall edge interrupt +// Default: RISE_EDGE_AND_FALL_EDGE_INTERRUPT +#define SL_BUTTON_CONFIG_BTN0_INTR RISE_EDGE_AND_FALL_EDGE_INTERRUPT + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SI91X_BUTTON_0 +// $[GPIO_SL_SI91X_BUTTON_0] +#ifndef SL_SI91X_BUTTON_0_PORT +#define SL_SI91X_BUTTON_0_PORT UULP_VBAT +#endif +#ifndef SL_SI91X_BUTTON_0_PIN +#define SL_SI91X_BUTTON_0_PIN 2 +#endif +// [GPIO_SL_SI91X_BUTTON_0]$ +// <<< sl:end pin_tool >>> + +#define SL_BUTTON_BTN0_PIN SL_SI91X_BUTTON_0_PIN +#define SL_BUTTON_BTN0_PORT RTE_BUTTON0_PORT +#define SL_BUTTON_BTN0_NUMBER RTE_BUTTON0_NUMBER + +#endif // SL_SI91X_BUTTON_INIT_BTN0_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn1_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn1_config.h new file mode 100644 index 0000000000..f422b07001 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_init_btn1_config.h @@ -0,0 +1,43 @@ +/***************************************************************************/ /** + * @file sl_si91x_button_init_btn1_config.h + * @brief Button Driver Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_BUTTON_INIT_BTN1_CONFIG_H +#define SL_SI91X_BUTTON_INIT_BTN1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Button Interrupt Configuration +// High level interrupt +// Low level interrupt +// High level and low level interrupt +// Rise edge interrupt +// Fall edge interrupt +// Rise edge and fall edge interrupt +// Default: RISE_EDGE_AND_FALL_EDGE_INTERRUPT +#define SL_BUTTON_CONFIG_BTN1_INTR RISE_EDGE_AND_FALL_EDGE_INTERRUPT + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SI91X_BUTTON_1 +// $[GPIO_SL_SI91X_BUTTON_1] +#ifndef SL_SI91X_BUTTON_1_PORT +#define SL_SI91X_BUTTON_1_PORT HP +#endif +#ifndef SL_SI91X_BUTTON_1_PIN +#define SL_SI91X_BUTTON_1_PIN 11 +#endif +// [GPIO_SL_SI91X_BUTTON_1]$ +// <<< sl:end pin_tool >>> + +#define SL_BUTTON_BTN1_PIN SL_SI91X_BUTTON_1_PIN +#define SL_BUTTON_BTN1_PORT RTE_BUTTON1_PORT +#define SL_BUTTON_BTN1_NUMBER RTE_BUTTON1_NUMBER +#define SL_BUTTON_BTN1_PAD RTE_BUTTON1_PAD + +#endif // SL_SI91X_BUTTON_INIT_BTN1_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_pin_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_pin_config.h new file mode 100644 index 0000000000..adda54dcbc --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_button_pin_config.h @@ -0,0 +1,30 @@ +/***************************************************************************/ /** + * @file sl_si91x_button_config.h + * @brief Button Driver Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_BUTTON_PIN_CONFIG_H +#define SL_SI91X_BUTTON_PIN_CONFIG_H + +#include "RTE_Device_917.h" +#include "sl_si91x_button_instances.h" + +#define SL_SI91x_BUTTON_COUNT (2) + +#ifndef SL_SI91X_BUTTON_0_PORT +#define SL_BUTTON_BTN0_PIN RTE_BUTTON0_PIN +#define SL_BUTTON_BTN0_PORT RTE_BUTTON0_PORT +#define SL_BUTTON_BTN0_NUMBER RTE_BUTTON0_NUMBER +#endif + +#ifndef SL_SI91X_BUTTON_1_PORT +#define SL_BUTTON_BTN1_PIN RTE_BUTTON1_PIN +#define SL_BUTTON_BTN1_PORT RTE_BUTTON1_PORT +#define SL_BUTTON_BTN1_NUMBER RTE_BUTTON1_NUMBER +#define SL_BUTTON_BTN1_PAD RTE_BUTTON1_PAD +#endif + +#endif // SL_SI91X_BUTTON_PIN_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_common_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_dma_config.h similarity index 77% rename from matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_common_config.h rename to matter/si91x/siwx917/BRD4343A/config/sl_si91x_dma_config.h index 921e7a507c..109df2599c 100644 --- a/matter/si91x/siwx917/BRD4342A/config/sl_si91x_ulp_uart_common_config.h +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_dma_config.h @@ -1,6 +1,6 @@ /***************************************************************************/ /** - * @file sl_si91x_ulp_uart_common_config.h - * @brief SL SI91X ULP UART Common Config. + * @file + * @brief SL USART Config. ******************************************************************************* * # License * Copyright 2023 Silicon Laboratories Inc. www.silabs.com @@ -28,16 +28,25 @@ * ******************************************************************************/ -#ifndef SL_SI91X_ULP_UART_COMMON_CONFIG_H -#define SL_SI91X_ULP_UART_COMMON_CONFIG_H +#ifndef SL_SI91X_DMA_CONFIG_H +#define SL_SI91X_DMA_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> -// DMA Configuration +#ifdef __cplusplus +extern "C" { +#endif -// ULP UART DMA -// Default: 1 -#define SL_ULPUART_DMA_CONFIG_ENABLE 0 +// DMA instance 0 channel count <1-32> +// Default: 32 +#define SL_DMA0_CHANNEL_COUNT 32 + +// ULP DMA instance channel count <1-12> +// Default: 12 +#define SL_ULP_DMA_CHANNEL_COUNT 12 -// // <<< end of configuration section >>> -#endif // SL_SI91X_ULP_UART_COMMON_CONFIG_H + +#ifdef __cplusplus +} +#endif +#endif //SL_SI91X_DMA_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_config.h new file mode 100644 index 0000000000..acc70d318d --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_config.h @@ -0,0 +1,30 @@ +/***************************************************************************/ /** + * @file RTE_led_config.h + * @brief Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_LED_CONFIG_H +#define SL_SI91X_LED_CONFIG_H + +#include "RTE_Device_917.h" +#include "sl_si91x_led_instances.h" + +#define SL_SI91x_LED_COUNT 2 + +#ifndef SL_SI91X_LED_0_PORT +#define SL_LED_LED0_PIN RTE_LED0_PIN +#define SL_LED_LED0_PORT RTE_LED0_PORT +#define SL_LED_LED0_NUMBER RTE_LED0_NUMBER +#endif + +#ifndef SL_SI91X_LED_1_PORT +#define SL_LED_LED1_PIN RTE_LED1_PIN +#define SL_LED_LED1_PORT RTE_LED1_PORT +#define SL_LED_LED1_NUMBER RTE_LED1_NUMBER +#define SL_LED_LED1_PAD RTE_LED1_PAD +#endif + +#endif // SL_SI91X_LED_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led0_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led0_config.h new file mode 100644 index 0000000000..28169b6c2c --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led0_config.h @@ -0,0 +1,28 @@ +/***************************************************************************/ /** + * @file sl_si91x_led_init_led0_config.h + * @brief Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_LED_INIT_LED0_CONFIG_H +#define SL_SI91X_LED_INIT_LED0_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_SI91X_LED_0 +// $[GPIO_SL_SI91X_LED_0] +#ifndef SL_SI91X_LED_0_PORT +#define SL_SI91X_LED_0_PORT ULP +#endif +#ifndef SL_SI91X_LED_0_PIN +#define SL_SI91X_LED_0_PIN 0 +#endif +// [GPIO_SL_SI91X_LED_0]$ +// <<< sl:end pin_tool >>> + +#define SL_LED_LED0_PIN SL_SI91X_LED_0_PIN +#define SL_LED_LED0_PORT RTE_LED0_PORT +#define SL_LED_LED0_NUMBER RTE_LED0_NUMBER + +#endif // SL_SI91X_LED_INIT_LED0_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led1_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led1_config.h new file mode 100644 index 0000000000..14093b027a --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_led_init_led1_config.h @@ -0,0 +1,28 @@ +/***************************************************************************/ /** + * @file sl_si91x_led_init_led1_config.h + * @brief Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + *******************************************************************************/ + +#ifndef SL_SI91X_LED_INIT_LED1_CONFIG_H +#define SL_SI91X_LED_INIT_LED1_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_SI91X_LED_1 +// $[GPIO_SL_SI91X_LED_1] +#ifndef SL_SI91X_LED_1_PORT +#define SL_SI91X_LED_1_PORT HP +#endif +#ifndef SL_SI91X_LED_1_PIN +#define SL_SI91X_LED_1_PIN 10 +#endif +// [GPIO_SL_SI91X_LED_1]$ +// <<< sl:end pin_tool >>> + +#define SL_LED_LED1_PIN SL_SI91X_LED_1_PIN +#define SL_LED_LED1_PORT RTE_LED1_PORT +#define SL_LED_LED1_NUMBER RTE_LED1_NUMBER + +#endif // SL_SI91X_LED_INIT_LED1_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_config_3.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_config_3.h new file mode 100644 index 0000000000..3becf17434 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_config_3.h @@ -0,0 +1,358 @@ +/***************************************************************************/ /** + * @file sl_si91x_power_manager_config_3.h + * @brief Power Manager Configuration NWP Basic and MCU Advance RAM Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_POWER_MANAGER_CONFIG_3_H +#define SL_SI91X_POWER_MANAGER_CONFIG_3_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_power_manager.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Peripheral Configuration + +// High Power Peripherals +// M4 DEBUG +// Default: 1 +#define SL_HP_M4_DEBUG_PERIPHERAL 1 + +// QSPI +// Default: 1 +#define SL_HP_QSPI_PERIPHERAL 1 + +// RPDMA +// Default: 1 +#define SL_HP_RPDMA_PERIPHERAL 1 + +// SDIO SPI +// Default: 1 +#define SL_HP_SDIO_SPI_PERIPHERAL 1 +// + +// Low Power Peripherals +// ULP AUX +// Default: 1 +#define SL_ULP_AUX_PERIPHERAL 1 + +// ULP CAPACITIVE TOUCH +// Default: 1 +#define SL_ULP_CAP_PERIPHERAL 1 + +// ULP FIM +// Default: 1 +#define SL_ULP_FIM_PERIPHERAL 1 + +// ULP I2C +// Default: 1 +#define SL_ULP_I2C_PERIPHERAL 1 + +// ULP I2S +// Default: 1 +#define SL_ULP_I2S_PERIPHERAL 1 + +// ULP IR +// Default: 1 +#define SL_ULP_IR_PERIPHERAL 1 + +// ULP SSI +// Default: 1 +#define SL_ULP_SSI_PERIPHERAL 1 + +// ULP UART +// Default: 1 +#define SL_ULP_UART_PERIPHERAL 1 + +// ULP UDMA +// Default: 1 +#define SL_ULP_UDMA_PERIPHERAL 1 +// + +// Ultra Low Power Peripherals +// MCU STORE 1 +// Default: 1 +#define SL_UULP_MCU_STORE1_PERIPHERAL 1 + +// MCU STORE 2 +// Default: 1 +#define SL_UULP_MCU_STORE2_PERIPHERAL 1 + +// MCU STORE 3 +// Default: 1 +#define SL_UULP_MCU_STORE3_PERIPHERAL 1 + +// RTC (CALENDAR) +// Default: 1 +#define SL_UULP_RTC_PERIPHERAL 1 + +// TIME PERIOD +// Default: 1 +#define SL_UULP_TIME_PERIOD_PERIPHERAL 1 + +// UPS +// Default: 1 +#define SL_UULP_UPS_PERIPHERAL 1 + +// UTS +// Default: 1 +#define SL_UULP_UTS_PERIPHERAL 1 + +// WATCHDOG TIMER +// Default: 1 +#define SL_UULP_WDT_PERIPHERAL 1 +// + +// + +// RAM Configuration + +// Configure RAM Banks using Size +#define SL_RAM_RETENTION_USING_SIZE 1 + +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_1 4 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_2 8 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_3 12 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_4 16 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_5 32 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_6 64 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_7 128 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_8 192 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_9 256 +#define SL_LP_RAM_RETENTION_USING_SIZE_BANK_10 320 +// Low Power Ram Retention Size (in KB) +// 4 KB +// 8 KB +// 12 KB +// 16 KB +// 32 KB +// 64 KB +// 128 KB +// 192 KB +// 256 KB +// 320 KB +// Selection of LP RAM Retention Size +#define SL_LP_RAM_RETENTION_SIZE SL_LP_RAM_RETENTION_USING_SIZE_BANK_10 + +#define SL_ULP_RAM_RETENTION_USING_SIZE_BANK_1 2 +#define SL_ULP_RAM_RETENTION_USING_SIZE_BANK_2 4 +// Ultra Low Power Ram Retention Size (in KB) +// 2 KB +// 4 KB +// Selection of ULP RAM Retention Size +#define SL_ULP_RAM_RETENTION_SIZE SL_ULP_RAM_RETENTION_USING_SIZE_BANK_2 +// + +// Configure RAM Banks using Bank Number +#define SL_RAM_RETENTION_USING_NUMBER 0 +// LOW POWER RAM BANK 1 +// Default: 1 +#define SL_LP_RAM_BANK1 1 + +// LOW POWER RAM BANK 2 +// Default: 1 +#define SL_LP_RAM_BANK2 1 + +// LOW POWER RAM BANK 3 +// Default: 1 +#define SL_LP_RAM_BANK3 1 + +// LOW POWER RAM BANK 4 +// Default: 1 +#define SL_LP_RAM_BANK4 1 + +// LOW POWER RAM BANK 5 +// Default: 1 +#define SL_LP_RAM_BANK5 1 + +// LOW POWER RAM BANK 6 +// Default: 1 +#define SL_LP_RAM_BANK6 1 + +// LOW POWER RAM BANK 7 +// Default: 1 +#define SL_LP_RAM_BANK7 1 + +// LOW POWER RAM BANK 8 +// Default: 1 +#define SL_LP_RAM_BANK8 1 + +// LOW POWER RAM BANK 9 +// Default: 1 +#define SL_LP_RAM_BANK9 1 + +// LOW POWER RAM BANK 10 +// Default: 1 +#define SL_LP_RAM_BANK10 1 + +// ULTRA LOW POWER RAM BANK 2 +// Default: 1 +#define SL_ULP_RAM_BANK2 1 + +// ULTRA LOW POWER RAM BANK 3 +// Default: 1 +#define SL_ULP_RAM_BANK3 1 +// + +// + +// <<< end of configuration section >>> + +sl_power_peripheral_t peripheral_config = { + .m4ss_peripheral = (0 +#if (SL_HP_M4_DEBUG_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_M4SS_PG_M4_DEBUG +#endif +#if (SL_HP_RPDMA_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_M4SS_PG_RPDMA +#endif +#if (SL_HP_QSPI_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_M4SS_PG_QSPI +#endif +#if (SL_HP_SDIO_SPI_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_M4SS_PG_SDIO_SPI +#endif + ), + .ulpss_peripheral = (0 +#if (SL_ULP_AUX_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_AUX +#endif +#if (SL_ULP_CAP_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_CAP +#endif +#if (SL_ULP_FIM_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_FIM +#endif +#if (SL_ULP_I2C_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_I2C +#endif +#if (SL_ULP_I2S_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_I2S +#endif +#if (SL_ULP_IR_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_IR +#endif +#if (SL_ULP_SSI_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_SSI +#endif +#if (SL_ULP_UART_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_UART +#endif +#if (SL_ULP_UDMA_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_PG_UDMA +#endif + ), + .npss_peripheral = (0 +#if (SL_UULP_MCU_STORE1_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUSTORE1 +#endif +#if (SL_UULP_MCU_STORE2_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUSTORE2 +#endif +#if (SL_UULP_MCU_STORE3_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUSTORE3 +#endif +#if (SL_UULP_RTC_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCURTC +#endif +#if (SL_UULP_TIME_PERIOD_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_TIMEPERIOD +#endif +#if (SL_UULP_UPS_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUPS +#endif +#if (SL_UULP_UTS_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUTS +#endif +#if (SL_UULP_WDT_PERIPHERAL == 0) + | SL_SI91X_POWER_MANAGER_NPSS_PG_MCUWDT +#endif + ), +}; + +sl_power_ram_retention_config_t ram_configuration = { +#if (SL_RAM_RETENTION_USING_SIZE == 1) + .configure_ram_banks = false, + .m4ss_ram_size_kb = SL_LP_RAM_RETENTION_SIZE, + .ulpss_ram_size_kb = SL_ULP_RAM_RETENTION_SIZE, +#else + .configure_ram_banks = true, + .m4ss_ram_banks = (0 +#if (SL_LP_RAM_BANK1 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_1 +#endif +#if (SL_LP_RAM_BANK2 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_2 +#endif +#if (SL_LP_RAM_BANK3 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_3 +#endif +#if (SL_LP_RAM_BANK3 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_3 +#endif +#if (SL_LP_RAM_BANK4 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_4 +#endif +#if (SL_LP_RAM_BANK5 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_5 +#endif +#if (SL_LP_RAM_BANK6 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_6 +#endif +#if (SL_LP_RAM_BANK7 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_7 +#endif +#if (SL_LP_RAM_BANK8 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_8 +#endif +#if (SL_LP_RAM_BANK9 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_9 +#endif +#if (SL_LP_RAM_BANK10 == 0) + | SL_SI91X_POWER_MANAGER_M4SS_RAM_BANK_10 +#endif + ), + .ulpss_ram_banks = (0 +#if (SL_ULP_RAM_BANK2 == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_RAM_BANK_2 +#endif +#if (SL_ULP_RAM_BANK3 == 0) + | SL_SI91X_POWER_MANAGER_ULPSS_RAM_BANK_3 +#endif + ), +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif // SL_SI91X_POWER_MANAGER_CONFIG_3_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_wakeup_source_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_wakeup_source_config.h new file mode 100644 index 0000000000..1fb5bed4ac --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_power_manager_wakeup_source_config.h @@ -0,0 +1,104 @@ +/***************************************************************************/ /** + * @file sl_si91x_power_manager_wakeup_source_config.h + * @brief Power Manager Wakeup Source Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_POWER_MANAGER_WAKEUP_SOURCE_CONFIG_H +#define SL_SI91X_POWER_MANAGER_WAKEUP_SOURCE_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Calendar Wakeup +#define SL_ENABLE_CALENDAR_WAKEUP_SOURCE 0 + +// Enable Second Wakeup Source +// Default: 0 +#define ENABLE_SECOND 0 + +// Enable Alarm Wakeup Source +// Default: 1 +#define ENABLE_ALARM 0 + +// Enable Milli Second Wakeup Source +// Default: 0 +#define ENABLE_MSEC 0 + +// Alarm Time (in milliseconds) +// Default: 5000 +#define ALARM_TIME_MSEC 5000 + +// + +// GPIO Wakeup +#define SL_ENABLE_GPIO_WAKEUP_SOURCE 1 + +// Enable NPSS GPIO 0 +// Default: 0 +#define ENABLE_NPSS_GPIO_0 0 + +// Enable NPSS GPIO 1 +// Default: 0 +#define ENABLE_NPSS_GPIO_1 0 + +// Enable NPSS GPIO 2 +// Default: 0 +#define ENABLE_NPSS_GPIO_2 1 + +// Enable NPSS GPIO 3 +// Default: 0 +#define ENABLE_NPSS_GPIO_3 0 +// + +// WDT Wakeup +#define SL_ENABLE_WDT_WAKEUP_SOURCE 0 +// + +// Deep Sleep Timer Wakeup +#define SL_ENABLE_DST_WAKEUP_SOURCE 0 + +// Sleep Time (in microseconds) +// Default: 500 +#define DST_WAKEUP_TIME 500 + +// + +// Wireless Wakeup +#define SL_ENABLE_WIRELESS_WAKEUP_SOURCE 0 +// + +// <<< end of configuration section >>> + +#ifdef __cplusplus +} +#endif + +#endif // SL_SI91X_POWER_MANAGER_WAKEUP_SOURCE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_stack_size_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_stack_size_config.h new file mode 100644 index 0000000000..c369cf7a7a --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_stack_size_config.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* @file sl_si91x_stack_size_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __SL_SI91X_STACK_SIZE_CONFIG_H_ +#define __SL_SI91X_STACK_SIZE_CONFIG_H_ + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 12288 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE +#define SL_STACK_SIZE 12288 +#endif + +// +// <<< end of configuration section >>> + +#endif // __SL_SI91X_STACK_SIZE_CONFIG_H_ diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_common_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_common_config.h new file mode 100644 index 0000000000..761d50ed93 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_common_config.h @@ -0,0 +1,84 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_timer_common_config.h + * @brief ULP Timer common configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_TIMER_COMMON_CONFIG_H +#define SL_SI91X_ULP_TIMER_COMMON_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +/******************************************************************************/ +/******************** ADC Peripheral CommonConfiguration **********************/ + +// <<< Use Configuration Wizard in Context Menu >>> +// ULP Timer Clock Configuration + +// Clock Type +// Static (auto select) +// Dynamic +// Selection of the Timer CLK Type. +#define SL_ULP_TIMER_CLK_TYPE SL_ULP_TIMER_CLK_TYPE_STATIC + +// Sync to ULPSS PCLK +// Enable or disable sync to ULPSS pclock. +// Default: 0 +#define SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK 0 + +// Wait for switching timer clock +// 1 : Enable waiting for switching timer clk & 0 : Skip waiting for switching timer clk. +// Default: 0 +#define SL_ULP_TIMER_SKIP_SWITCH_TIME 0 + +// clock source +// Ref clock +// 32KHZ_RO +// 32KHZ_RC +// 32KHZ_XTAL +// 32MHZ_RC (auto select) +// 20MHZ_RO +// Selection of the Clock source +#define SL_ULP_TIMER_CLK_INPUT_SOURCE ULP_TIMER_32MHZ_RC_CLK_SRC //default timer clock input source is ref clock + +// +// <<< end of configuration section >>> + +ulp_timer_clk_src_config_t sl_timer_clk_handle = { + .ulp_timer_clk_type = SL_ULP_TIMER_CLK_TYPE, + .ulp_timer_sync_to_ulpss_pclk = SL_ULP_TIMER_SYNC_TO_ULPSS_PCLK, + .ulp_timer_clk_input_src = SL_ULP_TIMER_CLK_INPUT_SOURCE, + .ulp_timer_skip_switch_time = SL_ULP_TIMER_SKIP_SWITCH_TIME, +}; + +#ifdef __cplusplus +} +#endif // SL_ULP_TIMER +#endif /* SL_SI91X_ULP_TIMER_COMMON_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_init_timer0_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_init_timer0_config.h new file mode 100644 index 0000000000..09d1badb50 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_si91x_ulp_timer_init_timer0_config.h @@ -0,0 +1,67 @@ +/***************************************************************************/ /** + * @file sl_si91x_ulp_timer_init_timer0_config.h + * @brief ULP Timer timer0 configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H +#define SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_si91x_ulp_timer.h" +/******************************************************************************/ +/******************************* ULP-Timer clock Configuration **************************/ +// timer0 Configuration + +// Timer type +// Down Counter (auto select) +// 1 Micro-Sec +// 256-Micro-Sec +// Selection of the Timer type +#define SL_ULP_TIMER_TIMER0_TYPE ULP_TIMER_TYP_DEFAULT + +// Timer mode +// One-shot +// Periodic (auto select) +// Selection of the Timer mode +#define SL_ULP_TIMER_TIMER0_MODE ULP_TIMER_MODE_PERIODIC + +// Timer direction +// Down (auto select) +// Up +// Selection of the Timer direction +#define SL_ULP_TIMER_TIMER0_DIRECTION DOWN_COUNTER + +// End timer0 Configuration +/******************************************************************************/ +// <<< end of configuration section >>> + +#endif /* SL_SI91X_ULP_TIMER_TIMER0_CONFIG_H */ diff --git a/matter/si91x/siwx917/BRD4343A/config/sl_sleeptimer_config.h b/matter/si91x/siwx917/BRD4343A/config/sl_sleeptimer_config.h new file mode 100644 index 0000000000..8344ef5f11 --- /dev/null +++ b/matter/si91x/siwx917/BRD4343A/config/sl_sleeptimer_config.h @@ -0,0 +1,82 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 +#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 +#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// WTIMER +// TIMER +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) +// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. +// Default: 0 +#define SL_SLEEPTIMER_TIMER_INSTANCE 0 + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider (not applicable for WTIMER/TIMER) +// WTIMER/TIMER peripherals are always prescaled to 1024. +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>>