From d1a3714755e4328ca96d5f1a5752d3e79402716b Mon Sep 17 00:00:00 2001 From: Mason Tran Date: Thu, 1 Sep 2022 15:32:41 -0400 Subject: [PATCH] Create an eero version of the openthread-efr32-[soc/rcp] CMake libs --- CMakeLists.txt | 4 +- script/build | 60 +-- .../openthread-efr32-rcp-eero/CMakeLists.txt | 255 +++++++++++ .../autogen/.crc_config.crc | 21 + .../autogen/RTE_Components.h | 22 + .../autogen/linkerfile.ld | 221 ++++++++++ .../autogen/mbedtls_config_autogen.h | 104 +++++ .../autogen/psa_crypto_config_autogen.h | 109 +++++ .../autogen/sl_board_default_init.c | 36 ++ .../autogen/sl_component_catalog.h | 16 + .../autogen/sl_device_init_clocks.c | 49 ++ .../autogen/sl_event_handler.c | 84 ++++ .../autogen/sl_event_handler.h | 14 + .../sl_mbedtls_config_transform_autogen.h | 62 +++ .../autogen/sl_ot_init.c | 5 + .../autogen/sl_ot_init.h | 27 ++ .../autogen/sl_uartdrv_init.c | 91 ++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../config/SEGGER_RTT_Conf.h | 417 ++++++++++++++++++ .../config/dmadrv_config.h | 26 ++ .../config/emlib_core_debug_config.h | 46 ++ .../config/mbedtls_config.h | 72 +++ .../config/nvm3_default_config.h | 45 ++ .../config/psa_crypto_config.h | 47 ++ .../config/sl_board_control_config.h | 76 ++++ .../config/sl_debug_swo_config.h | 100 +++++ .../config/sl_device_init_dcdc_config.h | 58 +++ .../config/sl_device_init_emu_config.h | 68 +++ .../config/sl_device_init_hfxo_config.h | 68 +++ .../config/sl_device_init_lfxo_config.h | 67 +++ .../config/sl_memory_config.h | 28 ++ .../sl_mx25_flash_shutdown_usart_config.h | 54 +++ .../config/sl_rail_util_pa_config.h | 80 ++++ .../config/sl_rail_util_pti_config.h | 75 ++++ .../config/sl_rail_util_rssi_config.h | 44 ++ .../config/sl_sleeptimer_config.h | 72 +++ .../config/sl_uartdrv_usart_vcom_config.h | 103 +++++ .../config/uartdrv_config.h | 114 +++++ .../openthread-efr32-rcp-sdk.cmake | 406 +++++++++++++++++ .../openthread-efr32-soc-eero/CMakeLists.txt | 239 ++++++++++ .../autogen/.crc_config.crc | 21 + .../autogen/RTE_Components.h | 22 + .../autogen/linkerfile.ld | 221 ++++++++++ .../autogen/mbedtls_config_autogen.h | 108 +++++ .../autogen/psa_crypto_config_autogen.h | 121 +++++ .../autogen/sl_board_default_init.c | 36 ++ .../autogen/sl_component_catalog.h | 17 + .../autogen/sl_device_init_clocks.c | 49 ++ .../autogen/sl_event_handler.c | 86 ++++ .../autogen/sl_event_handler.h | 14 + .../sl_mbedtls_config_transform_autogen.h | 62 +++ .../autogen/sl_ot_init.c | 5 + .../autogen/sl_ot_init.h | 27 ++ .../autogen/sl_uartdrv_init.c | 91 ++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../config/SEGGER_RTT_Conf.h | 417 ++++++++++++++++++ .../config/dmadrv_config.h | 26 ++ .../config/emlib_core_debug_config.h | 46 ++ .../config/mbedtls_config.h | 72 +++ .../config/nvm3_default_config.h | 45 ++ .../config/psa_crypto_config.h | 47 ++ .../config/sl_board_control_config.h | 76 ++++ .../config/sl_debug_swo_config.h | 100 +++++ .../config/sl_device_init_dcdc_config.h | 58 +++ .../config/sl_device_init_emu_config.h | 68 +++ .../config/sl_device_init_hfxo_config.h | 68 +++ .../config/sl_device_init_lfxo_config.h | 67 +++ .../config/sl_memory_config.h | 28 ++ .../sl_mx25_flash_shutdown_usart_config.h | 54 +++ .../config/sl_rail_util_pa_config.h | 80 ++++ .../config/sl_rail_util_pti_config.h | 75 ++++ .../config/sl_rail_util_rssi_config.h | 44 ++ .../config/sl_sleeptimer_config.h | 72 +++ .../config/sl_uartdrv_usart_vcom_config.h | 103 +++++ .../config/uartdrv_config.h | 114 +++++ .../openthread-efr32-soc-sdk.cmake | 409 +++++++++++++++++ 76 files changed, 6472 insertions(+), 32 deletions(-) create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/CMakeLists.txt create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/.crc_config.crc create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/RTE_Components.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/linkerfile.ld create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/mbedtls_config_autogen.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/psa_crypto_config_autogen.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_board_default_init.c create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_component_catalog.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_device_init_clocks.c create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.c create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_mbedtls_config_transform_autogen.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.c create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_init.c create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_instances.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/SEGGER_RTT_Conf.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/dmadrv_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/emlib_core_debug_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/mbedtls_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/nvm3_default_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/psa_crypto_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_board_control_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_debug_swo_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_dcdc_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_emu_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_hfxo_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_lfxo_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_memory_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_mx25_flash_shutdown_usart_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pa_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pti_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_rssi_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_sleeptimer_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/sl_uartdrv_usart_vcom_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/config/uartdrv_config.h create mode 100644 src/platform_libs/openthread-efr32-rcp-eero/openthread-efr32-rcp-sdk.cmake create mode 100644 src/platform_libs/openthread-efr32-soc-eero/CMakeLists.txt create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/.crc_config.crc create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/RTE_Components.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/linkerfile.ld create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/mbedtls_config_autogen.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/psa_crypto_config_autogen.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_board_default_init.c create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_component_catalog.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_device_init_clocks.c create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.c create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_mbedtls_config_transform_autogen.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.c create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_init.c create mode 100644 src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_instances.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/SEGGER_RTT_Conf.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/dmadrv_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/emlib_core_debug_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/mbedtls_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/nvm3_default_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/psa_crypto_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_board_control_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_debug_swo_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_dcdc_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_emu_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_hfxo_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_lfxo_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_memory_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_mx25_flash_shutdown_usart_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pa_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pti_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_rssi_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_sleeptimer_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/sl_uartdrv_usart_vcom_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/config/uartdrv_config.h create mode 100644 src/platform_libs/openthread-efr32-soc-eero/openthread-efr32-soc-sdk.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index 6a2c0cb5..13ea477a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -80,10 +80,10 @@ target_compile_options(ot-config INTERFACE # Generated platform projects # ============================================================================== set(slc_generated_projects - ${PROJECT_SOURCE_DIR}/build/${BOARD_LOWERCASE}/slc/soc/platform ${PROJECT_SOURCE_DIR}/build/${BOARD_LOWERCASE}/slc/soc/mbedtls - ${PROJECT_SOURCE_DIR}/build/${BOARD_LOWERCASE}/slc/rcp/platform ${PROJECT_SOURCE_DIR}/build/${BOARD_LOWERCASE}/slc/rcp/mbedtls + ${PROJECT_SOURCE_DIR}/src/platform_libs/openthread-efr32-soc-eero + ${PROJECT_SOURCE_DIR}/src/platform_libs/openthread-efr32-rcp-eero ) foreach(slc_project IN LISTS slc_generated_projects) diff --git a/script/build b/script/build index 378a5d26..b90f1f24 100755 --- a/script/build +++ b/script/build @@ -78,21 +78,21 @@ build() # ============================================================================================================== # Generate openthread-efr32-soc and openthread-efr32-soc-sdk libs # ============================================================================================================== - current_project_export_dir="${slc_generated_projects_dir}/soc/platform" - - run_slc -v 1 generate \ - --sdk="${sdk_dir}" \ - --clear-cache \ - --project-file="${repo_dir}/src/platform_projects/openthread-efr32-soc.slcp" \ - --output-type=makefile \ - --no-copy \ - --export-templates="${repo_dir}"/third_party/silabs/slc/exporter_templates/platform_library \ - --export-destination="${current_project_export_dir}" \ - --with "${board}" - - # TODO: Remove this when slc supports generic jinja template generation - mv "${current_project_export_dir}/openthread-efr32-soc.Makefile" "${current_project_export_dir}/CMakeLists.txt" - mv "${current_project_export_dir}/openthread-efr32-soc.project.mak" "${current_project_export_dir}/openthread-efr32-soc-sdk.cmake" + # current_project_export_dir="${slc_generated_projects_dir}/soc/platform" + + # run_slc -v 1 generate \ + # --sdk="${sdk_dir}" \ + # --clear-cache \ + # --project-file="${repo_dir}/src/platform_projects/openthread-efr32-soc.slcp" \ + # --output-type=makefile \ + # --no-copy \ + # --export-templates="${repo_dir}"/third_party/silabs/slc/exporter_templates/platform_library \ + # --export-destination="${current_project_export_dir}" \ + # --with "${board}" + + # # TODO: Remove this when slc supports generic jinja template generation + # mv "${current_project_export_dir}/openthread-efr32-soc.Makefile" "${current_project_export_dir}/CMakeLists.txt" + # mv "${current_project_export_dir}/openthread-efr32-soc.project.mak" "${current_project_export_dir}/openthread-efr32-soc-sdk.cmake" # ============================================================================================================== # Generate openthread-efr32-soc-mbedtls lib @@ -117,21 +117,21 @@ build() # ============================================================================================================== # Generate openthread-efr32-rcp and openthread-efr32-rcp-sdk libs # ============================================================================================================== - current_project_export_dir="${slc_generated_projects_dir}/rcp/platform" - - run_slc -v 1 generate \ - --sdk="${sdk_dir}" \ - --clear-cache \ - --project-file="${repo_dir}/src/platform_projects/openthread-efr32-rcp.slcp" \ - --output-type=makefile \ - --no-copy \ - --export-templates="${repo_dir}"/third_party/silabs/slc/exporter_templates/platform_library \ - --export-destination="${current_project_export_dir}" \ - --with "${board}" - - # TODO: Remove this when slc supports generic jinja template generation - mv "${current_project_export_dir}/openthread-efr32-rcp.Makefile" "${current_project_export_dir}/CMakeLists.txt" - mv "${current_project_export_dir}/openthread-efr32-rcp.project.mak" "${current_project_export_dir}/openthread-efr32-rcp-sdk.cmake" + # current_project_export_dir="${slc_generated_projects_dir}/rcp/platform" + + # run_slc -v 1 generate \ + # --sdk="${sdk_dir}" \ + # --clear-cache \ + # --project-file="${repo_dir}/src/platform_projects/openthread-efr32-rcp.slcp" \ + # --output-type=makefile \ + # --no-copy \ + # --export-templates="${repo_dir}"/third_party/silabs/slc/exporter_templates/platform_library \ + # --export-destination="${current_project_export_dir}" \ + # --with "${board}" + + # # TODO: Remove this when slc supports generic jinja template generation + # mv "${current_project_export_dir}/openthread-efr32-rcp.Makefile" "${current_project_export_dir}/CMakeLists.txt" + # mv "${current_project_export_dir}/openthread-efr32-rcp.project.mak" "${current_project_export_dir}/openthread-efr32-rcp-sdk.cmake" # ============================================================================================================== # Generate openthread-efr32-rcp-mbedtls lib diff --git a/src/platform_libs/openthread-efr32-rcp-eero/CMakeLists.txt b/src/platform_libs/openthread-efr32-rcp-eero/CMakeLists.txt new file mode 100644 index 00000000..8c2edd85 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/CMakeLists.txt @@ -0,0 +1,255 @@ +#################################################################### +# Automatically-generated file. Do not edit! # +# CMake Version 1 # +#################################################################### +# +# Copyright (c) 2022, The OpenThread Authors. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +include(${PROJECT_SOURCE_DIR}/third_party/silabs/cmake/utility.cmake) +include(openthread-efr32-rcp-sdk.cmake) + +# ============================================================================== +# Platform library +# ============================================================================== +add_library(openthread-efr32-rcp + $ +) + +# Interface lib for sharing efr32 config to relevant targets +add_library(openthread-efr32-rcp-config INTERFACE) + +# Define RCP specific libraries +set(OT_PLATFORM_LIB_RCP openthread-efr32-rcp) +set(OT_MBEDTLS_RCP silabs-mbedtls-rcp) + +set_target_properties(openthread-efr32-rcp + PROPERTIES + C_STANDARD 99 + CXX_STANDARD 11 +) + +# ============================================================================== +# Includes +# ============================================================================== +target_include_directories(ot-config INTERFACE + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include + ${SILABS_GSDK_DIR}/platform/common/inc + ${SILABS_GSDK_DIR}/hardware/board/inc + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc + ${SILABS_GSDK_DIR}/platform/driver/debug/inc + ${SILABS_GSDK_DIR}/platform/service/device_init/inc + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc + ${SILABS_GSDK_DIR}/platform/emlib/inc + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/include + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/library + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc + ${SILABS_GSDK_DIR}/platform/service/mpu/inc + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms/utils + ${PROJECT_SOURCE_DIR}/src/src + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154 + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc + ${SILABS_GSDK_DIR}/platform/service/system/inc + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc + ${SILABS_GSDK_DIR}/platform/service/udelay/inc +) + +target_include_directories(openthread-efr32-rcp-config INTERFACE + autogen + config +) + +target_link_libraries(openthread-radio PUBLIC openthread-efr32-rcp-config) + +target_include_directories(openthread-efr32-rcp PRIVATE + ${OT_PUBLIC_INCLUDES} +) + +# ============================================================================== +# Sources +# ============================================================================== +target_sources(openthread-efr32-rcp PRIVATE + ${PROJECT_SOURCE_DIR}/src/src/alarm.c + ${PROJECT_SOURCE_DIR}/src/src/board_config.h + ${PROJECT_SOURCE_DIR}/src/src/crypto.c + ${PROJECT_SOURCE_DIR}/src/src/diag.c + ${PROJECT_SOURCE_DIR}/src/src/entropy.c + ${PROJECT_SOURCE_DIR}/src/src/flash.c + ${PROJECT_SOURCE_DIR}/src/src/ieee802154-packet-utils.cpp + ${PROJECT_SOURCE_DIR}/src/src/ieee802154-packet-utils.hpp + ${PROJECT_SOURCE_DIR}/src/src/ieee802154mac.h + ${PROJECT_SOURCE_DIR}/src/src/logging.c + ${PROJECT_SOURCE_DIR}/src/src/memory.c + ${PROJECT_SOURCE_DIR}/src/src/misc.c + ${PROJECT_SOURCE_DIR}/src/src/openthread-core-efr32-config-check.h + ${PROJECT_SOURCE_DIR}/src/src/openthread-core-efr32-config.h + ${PROJECT_SOURCE_DIR}/src/src/platform-band.h + ${PROJECT_SOURCE_DIR}/src/src/platform-efr32.h + ${PROJECT_SOURCE_DIR}/src/src/radio.c + ${PROJECT_SOURCE_DIR}/src/src/rail_config.h + ${PROJECT_SOURCE_DIR}/src/src/security_manager.c + ${PROJECT_SOURCE_DIR}/src/src/security_manager.h + ${PROJECT_SOURCE_DIR}/src/src/sl_openthread.h + ${PROJECT_SOURCE_DIR}/src/src/sl_packet_utils.h + ${PROJECT_SOURCE_DIR}/src/src/startup-gcc.c + ${PROJECT_SOURCE_DIR}/src/src/system.c + ${PROJECT_SOURCE_DIR}/src/src/uartdrv_uart.c +) + +# ============================================================================== +# Compile definitions +# ============================================================================== +target_compile_definitions(ot-config INTERFACE + EFR32MG12P432F1024GL125=1 + SL_BOARD_NAME="BRD4161A" + SL_BOARD_REV="A03" + SL_COMPONENT_CATALOG_PRESENT=1 + MBEDTLS_CONFIG_FILE= + OPENTHREAD_CONFIG_ENABLE_BUILTIN_MBEDTLS=0 + OPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE="openthread-core-efr32-config-check.h" + OPENTHREAD_PROJECT_CORE_CONFIG_FILE="openthread-core-efr32-config.h" + BUFFER_SIZE_DOWN=0 + BUFFER_SIZE_UP=768 + MBEDTLS_PSA_CRYPTO_CONFIG_FILE= + SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT=0 + SL_RAIL_UTIL_PA_CONFIG_HEADER= + RTT_USE_ASM=0 + SEGGER_RTT_SECTION="SEGGER_RTT" +) + +target_compile_definitions(openthread-efr32-rcp-config INTERFACE + MBEDTLS_PSA_CRYPTO_CLIENT=1 +) + +target_compile_definitions(openthread-efr32-rcp PUBLIC + OPENTHREAD_COPROCESSOR=1 + OPENTHREAD_RADIO=1 +) + +target_compile_definitions(openthread-efr32-rcp-sdk PRIVATE + OPENTHREAD_COPROCESSOR=1 + OPENTHREAD_RADIO=1 +) + +target_compile_options(openthread-efr32-rcp PRIVATE + # GNU C flags + $<$: + "SHELL:-mcpu=cortex-m4" + "SHELL:-mthumb" + "SHELL:-mfpu=fpv4-sp-d16" + "SHELL:-mfloat-abi=softfp" + "SHELL:-std=c99" + "SHELL:-Wall" + "SHELL:-Wextra" + "SHELL:-Os" + "SHELL:-fdata-sections" + "SHELL:-ffunction-sections" + "SHELL:-fomit-frame-pointer" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:--specs=nano.specs" + "SHELL:-g" + > +) + +# ============================================================================== +# Linking +# ============================================================================== +set(LD_FILE "${CMAKE_CURRENT_SOURCE_DIR}/autogen/linkerfile.ld") +set(openthread-efr32-rcp-sdk_location $) + +target_link_libraries(openthread-efr32-rcp + PUBLIC + -lstdc++ + -lgcc + -lc + -lm + -lnosys + openthread-efr32-rcp-config + + PRIVATE + -T${LD_FILE} + -Wl,--gc-sections + + # The --whole-archive flags are necessary to resolve all symbols from the GSDK + -Wl,--whole-archive ${openthread-efr32-rcp-sdk_location} -Wl,--no-whole-archive + ot-config +) + +target_link_options(openthread-efr32-rcp PRIVATE + -mcpu=cortex-m4 + -mthumb + -mfpu=fpv4-sp-d16 + -mfloat-abi=softfp + -Wl,--gc-sections +) + +# ============================================================================== +# Static libraries from GSDK +# ============================================================================== +set(GSDK_LIBS + "${SILABS_GSDK_DIR}/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a" + "${SILABS_GSDK_DIR}/protocol/openthread/libs/libsl_openthread_efr32mg1x_gcc.a" + "${SILABS_GSDK_DIR}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg12_gcc_release.a" +) + +# Import GSDK static libs and set a dependency on the GSDK library +# This will ensure proper linking order +foreach(lib_file ${GSDK_LIBS}) + # Parse lib name, stripping .a extension + get_filename_component(lib_name ${lib_file} NAME_WE) + set(imported_lib_name "silabs-${lib_name}") + + # Add as an IMPORTED lib + add_library(${imported_lib_name} STATIC IMPORTED) + set_target_properties(${imported_lib_name} + PROPERTIES + IMPORTED_LOCATION "${lib_file}" + IMPORTED_LINK_INTERFACE_LIBRARIES openthread-efr32-rcp-sdk + ) + target_link_libraries(openthread-efr32-rcp PUBLIC ${imported_lib_name}) +endforeach() diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/.crc_config.crc b/src/platform_libs/openthread-efr32-rcp-eero/autogen/.crc_config.crc new file mode 100644 index 00000000..814c4965 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/.crc_config.crc @@ -0,0 +1,21 @@ +#CRC Codes for initially generated config files -- do not modify! +SEGGER_RTT_Conf.h=-674599354 +dmadrv_config.h=-894158991 +emlib_core_debug_config.h=171843933 +mbedtls_config.h=-1710232477 +nvm3_default_config.h=1109545002 +psa_crypto_config.h=-715200899 +sl_board_control_config.h=-858618493 +sl_debug_swo_config.h=848473986 +sl_device_init_dcdc_config.h=-1223674373 +sl_device_init_emu_config.h=1414330218 +sl_device_init_hfxo_config.h=349146444 +sl_device_init_lfxo_config.h=239925891 +sl_memory_config.h=-995392215 +sl_mx25_flash_shutdown_usart_config.h=330822538 +sl_rail_util_pa_config.h=1112608945 +sl_rail_util_pti_config.h=1157262329 +sl_rail_util_rssi_config.h=-1255858871 +sl_sleeptimer_config.h=-1074849105 +sl_uartdrv_usart_vcom_config.h=108701171 +uartdrv_config.h=-1381003705 \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/RTE_Components.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/RTE_Components.h new file mode 100644 index 00000000..3b6ea30c --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/RTE_Components.h @@ -0,0 +1,22 @@ +// This file is autogenerated by Silicon Labs SLC. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Silicon Labs SLC. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/linkerfile.ld b/src/platform_libs/openthread-efr32-rcp-eero/autogen/linkerfile.ld new file mode 100644 index 00000000..62217d8a --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/linkerfile.ld @@ -0,0 +1,221 @@ +/***************************************************************************//** + * GCC Linker script for Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + MEMORY + { + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 + } + +ENTRY(Reset_Handler) + +SECTIONS +{ + + .text : + { + linker_vectors_begin = .; + KEEP(*(.vectors)) + linker_vectors_end = .; + + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + + linker_code_begin = .; + *(.text*) + linker_code_end = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + *(.eh_frame*) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + __etext = .; + + /* Start placing output sections which are loaded into RAM */ + . = ORIGIN(RAM); + + .stack ALIGN(8) (NOLOAD): + { + __StackLimit = .; + KEEP(*(.stack*)) + . = ALIGN(4); + __StackTop = .; + PROVIDE(__stack = __StackTop); + } > RAM + + + .noinit . (NOLOAD): + { + *(.noinit*); + } > RAM + + .data . : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + + PROVIDE(__ram_func_section_start = .); + *(.ram) + PROVIDE(__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss . : + { + . = ALIGN(4); + __bss_start__ = .; + *(SEGGER_RTT) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM); + __HeapLimit = .; + } > RAM + + __heap_size = __HeapLimit - __HeapBase; + __main_flash_end__ = 0x0 + 0x100000; + + /* This is where we handle flash storage blocks. We use dummy sections for finding the configured + * block sizes and then "place" them at the end of flash when the size is known. */ + .internal_storage (DSECT) : { + KEEP(*(.internal_storage*)) + } > FLASH + + + .nvm (DSECT) : { + KEEP(*(.simee*)) + } > FLASH + + linker_nvm_end = __main_flash_end__; + linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); + linker_nvm_size = SIZEOF(.nvm); + linker_storage_end = linker_nvm_begin; + __nvm3Base = linker_nvm_begin; + + linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); + linker_storage_size = SIZEOF(.internal_storage); + ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") + + +} diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/mbedtls_config_autogen.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/mbedtls_config_autogen.h new file mode 100644 index 00000000..3a090a23 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/mbedtls_config_autogen.h @@ -0,0 +1,104 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef MBEDTLS_CONFIG_AUTOGEN_H +#define MBEDTLS_CONFIG_AUTOGEN_H + + +#define MBEDTLS_MPI_MAX_SIZE 32 + + +#define MBEDTLS_AES_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#define MBEDTLS_BASE64_C +#define MBEDTLS_CCM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_CMAC_C +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_HMAC_DRBG_C +#define MBEDTLS_ENTROPY_HARDWARE_ALT +#define MBEDTLS_ENTROPY_RAIL_PRESENT +#define MBEDTLS_MD_C +#define MBEDTLS_ECJPAKE_C +#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_PEM_PARSE_C +#define MBEDTLS_PEM_WRITE_C +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_ENTROPY_FORCE_SHA256 +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 +#define MBEDTLS_NO_PLATFORM_ENTROPY +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SHA224_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CREATE_C +#define MBEDTLS_X509_CRT_PARSE_C +#define MBEDTLS_X509_CRT_WRITE_C +#define MBEDTLS_X509_CRL_PARSE_C +#define MBEDTLS_X509_CSR_PARSE_C +#define MBEDTLS_X509_CSR_WRITE_C +#define MBEDTLS_OID_C +#define MBEDTLS_PSA_CRYPTO_CONFIG +#define MBEDTLS_PSA_CRYPTO_DRIVERS + + +#include "config-device-acceleration.h" + +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) || defined(SL_SE_ASSUME_FW_AT_LEAST_2_1_7) + #undef MBEDTLS_ECP_DP_CURVE25519_ENABLED + #if !(defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED)) + #undef MBEDTLS_ECDH_C + #undef MBEDTLS_ECP_C + #undef MBEDTLS_BIGNUM_C + #endif /* !MBEDTLS_ECP_DP_SECPxR1_ENABLED */ +#endif /* SL_SE_ASSUME_FW_AT_LEAST_x */ + +#if !defined(TEST_SUITE_MEMORY_BUFFER_ALLOC) +#if !defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#if defined(CONFIG_MBEDTLS_USE_FREERTOS_PVCALLOC) + /* In FreeRTOS, use pvCalloc (and vPortFree) for dynamic memory allocation. + E.g. Amazon FreeRTOS implements pvCalloc for dynamic memory allocation. */ + #include + + extern void * pvCalloc( size_t xNumElements, + size_t xSize ) ; + extern void vPortFree( void *pv ); + #define MBEDTLS_PLATFORM_CALLOC_MACRO pvCalloc + #define MBEDTLS_PLATFORM_FREE_MACRO vPortFree +#else + /* No memory allocator override, supply the default for SL platforms */ + #include "sl_malloc.h" + + #define MBEDTLS_PLATFORM_FREE_MACRO sl_free + #define MBEDTLS_PLATFORM_CALLOC_MACRO sl_calloc +#endif +#endif /* No specific memory allocator override */ +#endif /* Not under test */ + +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_C + + + +#endif diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/psa_crypto_config_autogen.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/psa_crypto_config_autogen.h new file mode 100644 index 00000000..454444ef --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/psa_crypto_config_autogen.h @@ -0,0 +1,109 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef PSA_CRYPTO_CONFIG_AUTOGEN_H +#define PSA_CRYPTO_CONFIG_AUTOGEN_H + +#define PSA_WANT_ALG_SHA_224 +#define PSA_WANT_ALG_SHA_256 +#define PSA_WANT_ALG_CCM +#define PSA_WANT_ALG_CMAC +#define PSA_WANT_ALG_CBC_NO_PADDING +#define PSA_WANT_ALG_ECB_NO_PADDING +#define PSA_WANT_ALG_ECDSA +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY +#define PSA_WANT_KEY_TYPE_AES +#define PSA_WANT_ECC_SECP_R1_256 +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG +#define MBEDTLS_PSA_ACCEL_ALG_SHA_1 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_224 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_256 +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_AES +#define MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7 +#define MBEDTLS_PSA_ACCEL_ALG_CTR +#define MBEDTLS_PSA_ACCEL_ALG_CFB +#define MBEDTLS_PSA_ACCEL_ALG_OFB +#define MBEDTLS_PSA_ACCEL_ALG_GCM +#define MBEDTLS_PSA_ACCEL_ALG_CCM +#define MBEDTLS_PSA_ACCEL_ALG_CMAC + +#define MBEDTLS_PSA_KEY_SLOT_COUNT ( + SL_PSA_KEY_USER_SLOT_COUNT) +#define SL_PSA_ITS_MAX_FILES ( + SL_PSA_ITS_USER_MAX_FILES) + +#include "config-device-acceleration.h" +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) || defined(SL_SE_ASSUME_FW_AT_LEAST_2_1_7) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 + #undef MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 + #if !(defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED)) + #undef MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR + #undef MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY + #undef MBEDTLS_PSA_BUILTIN_ALG_ECDH + #endif /* !MBEDTLS_ECP_DP_SECPxR1_ENABLED */ +#endif /* SL_SE_ASSUME_FW_AT_LEAST_x */ + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// Asymmetric Crypt module (RSA is not supported) +#define TFM_CRYPTO_ASYM_ENCRYPT_MODULE_DISABLED + +// HASH module +#if !defined(PSA_WANT_ALG_SHA_1) \ + && !defined(PSA_WANT_ALG_SHA_224) \ + && !defined(PSA_WANT_ALG_SHA_256) \ + && !defined(PSA_WANT_ALG_SHA_384) \ + && !defined(PSA_WANT_ALG_SHA_512) \ + && !defined(PSA_WANT_ALG_MD5) +#define TFM_CRYPTO_HASH_MODULE_DISABLED +#endif + +// AEAD module +#if !defined(PSA_WANT_ALG_CCM) \ + && !defined(PSA_WANT_ALG_GCM) \ + && !defined(PSA_WANT_ALG_CHACHA20_POLY1305) +#define TFM_CRYPTO_AEAD_MODULE_DISABLED +#endif + +// Asymmetric Sign module +#if !defined(PSA_WANT_ALG_ECDSA) \ + && !defined(PSA_WANT_ALG_EDDSA) \ + && !defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) +#define TFM_CRYPTO_ASYM_SIGN_MODULE_DISABLED +#endif + +// Cipher module +#if !defined(PSA_WANT_ALG_CFB) \ + && !defined(PSA_WANT_ALG_CTR) \ + && !defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + && !defined(PSA_WANT_ALG_CBC_PKCS7) \ + && !defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + && !defined(PSA_WANT_ALG_XTS) \ + && !defined(PSA_WANT_ALG_OFB) \ + && !defined(PSA_WANT_ALG_STREAM_CIPHER) +#define TFM_CRYPTO_CIPHER_MODULE_DISABLED +#endif + +// MAC module +#if !defined(PSA_WANT_ALG_HMAC) \ + && !defined(PSA_WANT_ALG_CMAC) \ + && !defined(PSA_WANT_ALG_CBC_MAC) +#define TFM_CRYPTO_MAC_MODULE_DISABLED +#endif + +// Key derivation module +#if !defined(PSA_WANT_ALG_PBKDF2_HMAC) \ + && !defined(PSA_WANT_ALG_HKDF) \ + && !defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) \ + && !defined(PSA_WANT_ALG_TLS12_PRF) \ + && !defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) \ + && !defined(PSA_WANT_ALG_ECDH) +#define TFM_CRYPTO_KEY_DERIVATION_MODULE_DISABLED +#endif + +#endif // TFM_CONFIG_SL_SECURE_LIBRARY + +#endif diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_board_default_init.c b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_board_default_init.c new file mode 100644 index 00000000..bd43db36 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_component_catalog.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_component_catalog.h new file mode 100644 index 00000000..7e787c7e --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_component_catalog.h @@ -0,0 +1,16 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_MPU_PRESENT +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT +#define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_RAIL_LIB_PRESENT +#define SL_CATALOG_RAIL_UTIL_PTI_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT +#define SL_CATALOG_UARTDRV_USART_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_device_init_clocks.c b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_device_init_clocks.c new file mode 100644 index 00000000..9349ba24 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_device_init_clocks.c @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.c b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.c new file mode 100644 index 00000000..69a0e75d --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.c @@ -0,0 +1,84 @@ +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "pa_conversions_efr32.h" +#include "sl_rail_util_pti.h" +#include "sl_rail_util_rssi.h" +#include "sl_board_control.h" +#include "platform-efr32.h" +#include "sl_sleeptimer.h" +#include "sl_debug_swo.h" +#include "gpiointerrupt.h" +#include "sl_mbedtls.h" +#include "sl_mpu.h" +#include "nvm3_default.h" +#include "sl_ot_init.h" +#include "sl_uartdrv_instances.h" +#include "sl_cos.h" + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_lfxo(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + nvm3_initDefault(); +} + +void sl_driver_init(void) +{ + sl_debug_swo_init(); + GPIOINT_Init(); + sl_uartdrv_init_instances(); + sl_cos_send_config(); +} + +void sl_service_init(void) +{ + sl_board_configure_vcom(); + sl_sleeptimer_init(); + sl_mbedtls_init(); + sl_mpu_disable_execute_from_ram(); +} + +void sl_stack_init(void) +{ + sl_rail_util_pa_init(); + sl_rail_util_pti_init(); + sl_rail_util_rssi_init(); + sl_ot_sys_init(); +} + +void sl_internal_app_init(void) +{ + sl_ot_init(); +} + +void sl_platform_process_action(void) +{ +} + +void sl_service_process_action(void) +{ +} + +void sl_stack_process_action(void) +{ +} + +void sl_internal_app_process_action(void) +{ +} + diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.h new file mode 100644 index 00000000..89299544 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_event_handler.h @@ -0,0 +1,14 @@ +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_platform_process_action(void); +void sl_service_process_action(void); +void sl_stack_process_action(void); +void sl_internal_app_process_action(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_mbedtls_config_transform_autogen.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_mbedtls_config_transform_autogen.h new file mode 100644 index 00000000..c787ba5b --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_mbedtls_config_transform_autogen.h @@ -0,0 +1,62 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H +#define SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H + +// Convert CMSIS Markup config defines to mbedTLS specific config defines + +// Allow undefining the specified cipher suites +#if defined(SLI_MBEDTLS_AUTODETECT_CIPHERSUITES) +#undef MBEDTLS_SSL_CIPHERSUITES +#endif + +#if SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#endif +#if SL_MBEDTLS_SSL_EXPORT_KEYS + #define MBEDTLS_SSL_EXPORT_KEYS +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#endif + +#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) + #define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN +#endif + +#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) + #define MBEDTLS_SSL_OUT_CONTENT_LEN SL_MBEDTLS_SSL_OUT_CONTENT_LEN +#endif + + +#define SLI_SSL_IN_CONTENT_LEN_REQUIREMENT 900 + +// If the SDK requires a certain SSL buffer size, configure Mbed TLS +// to size the buffer to the highest of the user/default or SDK setting. +#if MBEDTLS_SSL_IN_CONTENT_LEN < SLI_SSL_IN_CONTENT_LEN_REQUIREMENT + #undef MBEDTLS_SSL_IN_CONTENT_LEN + #define MBEDTLS_SSL_IN_CONTENT_LEN SLI_SSL_IN_CONTENT_LEN_REQUIREMENT +#endif + + + +#define SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT 900 + +// If the SDK requires a certain SSL buffer size, configure Mbed TLS +// to size the buffer to the highest of the user/default or SDK setting. +#if MBEDTLS_SSL_OUT_CONTENT_LEN < SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT + #undef MBEDTLS_SSL_OUT_CONTENT_LEN + #define MBEDTLS_SSL_OUT_CONTENT_LEN SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT +#endif + + +#endif // SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.c b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.c new file mode 100644 index 00000000..df8c81f3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.c @@ -0,0 +1,5 @@ +#include "sl_ot_init.h" + +void sl_ot_init(void) +{ +} \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.h new file mode 100644 index 00000000..0e73d3b3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_ot_init.h @@ -0,0 +1,27 @@ +/***************************************************************************/ +/** + * @file + * @brief This generated header includes declaration of all functions required + * during initialization that must be defined by the OpenThread application. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * + * https://www.silabs.com/about-us/legal/master-software-license-agreement + * + * This software is distributed to you in Source Code format and is governed by + * the sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_OT_INIT_H +#define SL_OT_INIT_H + +void sl_ot_init(void); + +#endif // SL_OT_INIT_H \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_init.c b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_init.c new file mode 100644 index 00000000..ab0bb51b --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_instances.h b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_instances.h new file mode 100644 index 00000000..894c73f8 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/SEGGER_RTT_Conf.h b/src/platform_libs/openthread-efr32-rcp-eero/config/SEGGER_RTT_Conf.h new file mode 100644 index 00000000..ca8df42d --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/SEGGER_RTT_Conf.h @@ -0,0 +1,417 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.30 * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 21386 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* + * + * Defines, configurable + * + ********************************************************************** + */ +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* + * + * RTT memcpy configuration + * + * memcpy() is good for large amounts of data, + * but the overhead is big for small amounts, which are usually stored via RTT. + * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. + * + * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. + * This is may be required with memory access restrictions, + * such as on Cortex-A devices with MMU. + */ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* + * + * RTT lock configuration for SEGGER Embedded Studio, + * Rowley CrossStudio and GCC + */ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i" (SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif defined(__ARM_ARCH_7A__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR EWARM + */ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RX + */ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RL78 + */ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for KEIL ARM + */ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm("basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for TI ARM + */ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for CCRX + */ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for embOS Simulation on Windows + * (Can also be used for generic RTT locking with embOS) + */ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration fallback + */ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +/********************************************************************* + * + * RTT control block configuration + */ +#define SEGGER_RTT_ALIGNMENT 1024 + +#endif +/*************************** End of file ****************************/ diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/dmadrv_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/dmadrv_config.h new file mode 100644 index 00000000..9aa48db5 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/dmadrv_config.h @@ -0,0 +1,26 @@ +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-7> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 4 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 + +// Number of available channels <1-8> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 8 +#define EMDRV_DMADRV_DMA_CH_COUNT 8 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/emlib_core_debug_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/emlib_core_debug_config.h new file mode 100644 index 00000000..50dbbed9 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/emlib_core_debug_config.h @@ -0,0 +1,46 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +// If Enabled, either cycle_counter or systemview component must be added to project. +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/mbedtls_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/mbedtls_config.h new file mode 100644 index 00000000..44ce8ed5 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/mbedtls_config.h @@ -0,0 +1,72 @@ +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +// Include the autogenerated mbedtls configuration file +#include "mbedtls_config_autogen.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// TLS/DTLS configuration + +// Complete list of ciphersuites to use, in order of preference. +// Default: MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 +// Complete list of ciphersuites to use, in order of preference. +// The value of this configuration should be updated for the application needs. +#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + +// Maximum TLS/DTLS fragment length in bytes (input). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when receiving data. +#define SL_MBEDTLS_SSL_IN_CONTENT_LEN 768 + +// Maximum TLS/DTLS fragment length in bytes (output). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when sending data. +#define SL_MBEDTLS_SSL_OUT_CONTENT_LEN 768 + +// Enable support for RFC 6066 max_fragment_length extension in SSL. +// Default: 1 +// Enable support for RFC 6066 max_fragment_length extension in SSL. +#define SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1 + +// Enable support for exporting key block and master secret. +// Default: 1 +// Enable support for exporting key block and master secret. +// This is required for certain users of TLS, e.g. EAP-TLS. +#define SL_MBEDTLS_SSL_EXPORT_KEYS 1 + +// Enable the PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED 0 + +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED 0 + +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED 0 + +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED 0 + +// +// <<< end of configuration section >>> + +// Include transformation logic to apply CMSIS-config configuration options to +// the correct Mbed TLS / PSA Crypto options. +#include "sl_mbedtls_config_transform_autogen.h" + +// Custom defines can be placed here before check_config.h is included. + +#include "mbedtls/config_psa.h" + +#include "mbedtls/check_config.h" + +#endif diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/nvm3_default_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/nvm3_default_config.h new file mode 100644 index 00000000..ba2982c2 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/nvm3_default_config.h @@ -0,0 +1,45 @@ +#ifndef NVM3_DEFAULT_CONFIG_H +#define NVM3_DEFAULT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// NVM3 Default Instance Configuration + +#ifndef NVM3_DEFAULT_CACHE_SIZE +// NVM3 Default Instance Cache Size +// Number of NVM3 objects to cache. To reduce access times this number +// should be equal to or higher than the number of NVM3 objects in the +// default NVM3 instance. +// Default: 200 +#define NVM3_DEFAULT_CACHE_SIZE 200 +#endif + +#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE +// NVM3 Default Instance Max Object Size +// Max NVM3 object size that can be stored. +// Default: 254 +#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 +#endif + +#ifndef NVM3_DEFAULT_REPACK_HEADROOM +// NVM3 Default Instance User Repack Headroom +// Headroom determining how many bytes below the forced repack limit the user +// repack limit should be placed. The default is 0, which means the user and +// forced repack limits are equal. +// Default: 0 +#define NVM3_DEFAULT_REPACK_HEADROOM 0 +#endif + +#ifndef NVM3_DEFAULT_NVM_SIZE +// NVM3 Default Instance Size +// Size of the NVM3 storage region in flash. This size should be aligned with +// the flash page size of the device. +// Default: 36864 +#define NVM3_DEFAULT_NVM_SIZE 36864 +#endif + +// + +// <<< end of configuration section >>> + +#endif // NVM3_DEFAULT_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/psa_crypto_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/psa_crypto_config.h new file mode 100644 index 00000000..557606d1 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/psa_crypto_config.h @@ -0,0 +1,47 @@ +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PSA User Maximum Open Keys Count <0-128> +// Maximum amount of keys that the user application will have open +// simultaneously. In context of PSA Crypto, an open key means any key +// either stored in RAM (lifetime set to PSA_KEY_LIFETIME_VOLATILE), or +// used as part of a cryptographic operation. +// When using a key for a multi-part (setup/update/finish) operation, a key +// is considered to be open from the moment the operation is successfully +// setup, until it finishes or aborts. +// When an application tries to open more keys than this value accounts for, +// the PSA API may return PSA_ERROR_INSUFFICIENT_MEMORY. Keep in mind that +// other software included in the application (e.g. wireless protocol stacks) +// also can have a need to have open keys in PSA Crypto. This could lead to +// a race condition when the application key slot count is set too low for +// the actual usage of the application, as a software stack may not fail +// gracefully in case an application opens more than its declared amount of +// keys, thereby precluding the stack from functioning. +// Default: 4 +#define SL_PSA_KEY_USER_SLOT_COUNT (4) + +// PSA Maximum User Persistent Keys Count <0-1024> +// Maximum amount of keys (or other files) that can be stored persistently +// by the application through the PSA interface, when persistent storage +// support for PSA Crypto is included in the project. +// Due to caching logic, this setting does have an impact on static RAM usage. +// Note that this number is added to the potential requirements from other +// software components in the project, such that the total amount of keys +// which can be stored through the ITS backend can be higher than what is +// configured here. +// +// WARNING: When changing this setting on an application that is already +// deployed, and thus will get the change through an application upgrade, +// care should be taken to ensure that the setting is only ever increased, +// and never decreased. Decreasing this setting might cause previously +// stored keys/files to become inaccessible. +// Default: 128 +#define SL_PSA_ITS_USER_MAX_FILES (128) +// <<< end of configuration section >>> + +// Include the autogenerated PSA Crypto configuration file +#include "psa_crypto_config_autogen.h" + +#endif // PSA_CRYPTO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_board_control_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_board_control_config.h new file mode 100644 index 00000000..e75b074f --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortA +#define SL_BOARD_ENABLE_VCOM_PIN 5 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortD +#define SL_BOARD_ENABLE_DISPLAY_PIN 15 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_debug_swo_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_debug_swo_config.h new file mode 100644 index 00000000..bd2964af --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_debug_swo_config.h @@ -0,0 +1,100 @@ +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[DBG_SL_DEBUG] +#define SL_DEBUG_PERIPHERAL DBG + +#define SL_DEBUG_SWV_PORT gpioPortF +#define SL_DEBUG_SWV_PIN 2 +#define SL_DEBUG_SWV_LOC 0 +// [DBG_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_dcdc_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_dcdc_config.h new file mode 100644 index 00000000..734aed36 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 0 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL DCDC_PFMXCTRL_IPKVAL_DEFAULT + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_emu_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_emu_config.h new file mode 100644 index 00000000..387abf94 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_emu_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_EMU Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_EMU_CONFIG_H +#define SL_DEVICE_INIT_EMU_CONFIG_H + +#include "em_emu.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// EM4H Voltage scaling level +// Fast-wakeup voltage level +// Low-power optimized voltage level +// Default: emuVScaleEM4H_LowPower +#define SL_DEVICE_INIT_EMU_EM4_VSCALE emuVScaleEM4H_LowPower + +// Retain LFXO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFXO 0 + +// Retain LFRCO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFRCO 0 + +// Retain ULFRCO in EM4S +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_ULFRCO 0 + +// Hibernate or shutoff EM4 state +// EM4 Shutoff +// EM4 Hibernate +// Default: emuEM4Shutoff +#define SL_DEVICE_INIT_EMU_EM4_STATE emuEM4Shutoff + +// EM4 pin retention mode +// No Retention: Pads enter reset state when entering EM4. +// Retention through EM4: Pads enter reset state when exiting EM4. +// Retention through EM4 and wakeup. +// Default: emuPinRetentionDisable +#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_EMU_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_hfxo_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_hfxo_config.h new file mode 100644 index 00000000..ccd1c239 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_hfxo_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 327 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_lfxo_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_lfxo_config.h new file mode 100644 index 00000000..d4b79b3d --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_device_init_lfxo_config.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 32 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_memory_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_memory_config.h new file mode 100644 index 00000000..b43ebcba --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_memory_config.h @@ -0,0 +1,28 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 4096 +#endif + +// Minimum heap size for the application. +// Default: 2048 +// Note that this value will configure the c heap which is normally used by +// malloc() and free() from the c library. The value defines a minimum heap +// size that is guaranteed to be available. The available heap may be larger +// to make use of any memory that would otherwise remain unused. +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 2048 +#endif + +// +// <<< end of configuration section >>> + +#endif diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_mx25_flash_shutdown_usart_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 00000000..742762a3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,54 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// USART1 TX on PC6 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 6 +#define SL_MX25_FLASH_SHUTDOWN_TX_LOC 11 + +// USART1 RX on PC7 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 7 +#define SL_MX25_FLASH_SHUTDOWN_RX_LOC 11 + +// USART1 CLK on PC8 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 8 +#define SL_MX25_FLASH_SHUTDOWN_CLK_LOC 11 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pa_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pa_config.h new file mode 100644 index 00000000..09a4e6f0 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pa_config.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 +// 2.4 GHz PA Selection +// High Power +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HP +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HP +// Sub-1 GHz PA Selection +// Enable +// Disable +// Default: RAIL_TX_POWER_MODE_SUBGIG +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pti_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pti_config.h new file mode 100644 index 00000000..e5ea09f6 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_pti_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PB12 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DOUT_PIN 12 +#define SL_RAIL_UTIL_PTI_DOUT_LOC 6 + +// PTI DFRAME on PB13 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 13 +#define SL_RAIL_UTIL_PTI_DFRAME_LOC 6 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_rssi_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_rssi_config.h new file mode 100644 index 00000000..3c60beb8 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: -8 +#define SL_RAIL_UTIL_RSSI_OFFSET -8 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_sleeptimer_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_sleeptimer_config.h new file mode 100644 index 00000000..846d37d6 --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_sleeptimer_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/sl_uartdrv_usart_vcom_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 00000000..29b7f57d --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 0 +#define SL_UARTDRV_USART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 1 +#define SL_UARTDRV_USART_VCOM_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 2 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 3 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 30 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-rcp-eero/config/uartdrv_config.h b/src/platform_libs/openthread-efr32-rcp-eero/config/uartdrv_config.h new file mode 100644 index 00000000..e1d0a85d --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/src/platform_libs/openthread-efr32-rcp-eero/openthread-efr32-rcp-sdk.cmake b/src/platform_libs/openthread-efr32-rcp-eero/openthread-efr32-rcp-sdk.cmake new file mode 100644 index 00000000..ac3ac70c --- /dev/null +++ b/src/platform_libs/openthread-efr32-rcp-eero/openthread-efr32-rcp-sdk.cmake @@ -0,0 +1,406 @@ +#################################################################### +# Automatically-generated file. Do not edit! # +# CMake Version 1 # +#################################################################### +# +# Copyright (c) 2022, The OpenThread Authors. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +include(${PROJECT_SOURCE_DIR}/third_party/silabs/cmake/utility.cmake) + +# ============================================================================== +# Library of platform dependencies from GSDK and generated config files +# ============================================================================== +add_library(openthread-efr32-rcp-sdk) + +set_target_properties(openthread-efr32-rcp-sdk + PROPERTIES + C_STANDARD 99 + CXX_STANDARD 11 +) + +# ============================================================================== +# Includes +# ============================================================================== +target_include_directories(openthread-efr32-rcp-sdk PUBLIC + config + autogen + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include + ${SILABS_GSDK_DIR}/platform/common/inc + ${SILABS_GSDK_DIR}/hardware/board/inc + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc + ${SILABS_GSDK_DIR}/platform/driver/debug/inc + ${SILABS_GSDK_DIR}/platform/service/device_init/inc + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc + ${SILABS_GSDK_DIR}/platform/emlib/inc + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/include + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/library + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc + ${SILABS_GSDK_DIR}/platform/service/mpu/inc + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms/utils + ${PROJECT_SOURCE_DIR}/src/src + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154 + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc + ${SILABS_GSDK_DIR}/platform/service/system/inc + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc + ${SILABS_GSDK_DIR}/platform/service/udelay/inc +) + +target_include_directories(openthread-efr32-rcp-sdk PRIVATE + ${OT_PUBLIC_INCLUDES} +) + +# ============================================================================== +# Sources +# ============================================================================== +target_sources(openthread-efr32-rcp-sdk PRIVATE + ${SILABS_GSDK_DIR}/hardware/board/inc/sl_board_control.h + ${SILABS_GSDK_DIR}/hardware/board/inc/sl_board_init.h + ${SILABS_GSDK_DIR}/hardware/board/src/sl_board_control_gpio.c + ${SILABS_GSDK_DIR}/hardware/board/src/sl_board_init.c + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc/sl_cos.h + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/src/sl_cos.c + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_compiler.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_gcc.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_version.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/core_cm4.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/mpu_armv7.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/tz_context.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_assert.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_atomic.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_common.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_enum.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_status.h + ${SILABS_GSDK_DIR}/platform/common/src/sl_assert.c + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_gcc_preinclude.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_memory.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_memory_region.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/src/sl_memory.c + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p432f1024gl125.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_acmp.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_adc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_pins.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_ports.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cmu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cryotimer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_crypto.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_csen.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_devinfo.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dma_descriptor.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dmareq.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_emu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_etm.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_fpueh.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpcrc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio_p.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_i2c.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_idac.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_buf.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_st.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_letimer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_leuart.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_msc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_pcnt.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_signals.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rmu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_romtable.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_cc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_ret.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_smu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer_cc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_trng.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_usart.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac_opa.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog_pch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/em_device.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/system_efr32mg12p.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Source/startup_efr32mg12p.c + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Source/system_efr32mg12p.c + ${SILABS_GSDK_DIR}/platform/driver/debug/inc/sl_debug_swo.h + ${SILABS_GSDK_DIR}/platform/driver/debug/src/sl_debug_swo.c + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc/ecode.h + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc/dmadrv.h + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/src/dmadrv.c + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_default.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_hal.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_hal_flash.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_lock.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_default_common_linker.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_hal_flash.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_lock.c + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc/uartdrv.h + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/src/uartdrv.c + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_assert.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_bus.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_chip.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_cmu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_cmu_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_common.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_core.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_crypto.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_crypto_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_emu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_gpio.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_ldma.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_leuart.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_msc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_msc_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_prs.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_ramfunc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_rmu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_rtcc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_system.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_usart.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_version.h + ${SILABS_GSDK_DIR}/platform/emlib/src/em_cmu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_core.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_crypto.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_emu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_gpio.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_ldma.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_leuart.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_msc.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_prs.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_rmu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_rtcc.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_system.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_usart.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_assert_error_codes.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_features.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_mfm.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_types.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x/sl_rail_util_pa_curves.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble/rail_ble.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave/rail_zwave.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_clocks.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_dcdc.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_emu.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_hfxo.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_lfxo.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_nvic.h + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_dcdc_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_emu_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_hfxo_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_lfxo_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_nvic.c + ${SILABS_GSDK_DIR}/platform/service/mpu/inc/sl_mpu.h + ${SILABS_GSDK_DIR}/platform/service/mpu/src/sl_mpu.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc/sl_sleeptimer.h + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc/sli_sleeptimer.h + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sl_sleeptimer.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sli_sleeptimer_hal.h + ${SILABS_GSDK_DIR}/platform/service/system/inc/sl_system_init.h + ${SILABS_GSDK_DIR}/platform/service/system/inc/sl_system_process_action.h + ${SILABS_GSDK_DIR}/platform/service/system/src/sl_system_init.c + ${SILABS_GSDK_DIR}/platform/service/system/src/sl_system_process_action.c + ${SILABS_GSDK_DIR}/platform/service/udelay/inc/sl_udelay.h + ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay.c + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-sl-crypto-all-acceleration.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/aes_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/ccm_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/cmac_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/gcm_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha1_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha256_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha512_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/threading_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/crypto_aes.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/crypto_ecp.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_sha.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_mbedtls.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_crypto.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/crypto_management.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public/sl_psa_values.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_transparent_functions.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_transparent_types.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_trng_driver.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/crypto_management.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_cipher.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_hash.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_mac.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_trng_driver.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_driver_common.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_driver_init.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_trng.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER.h + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h + autogen/mbedtls_config_autogen.h + autogen/psa_crypto_config_autogen.h + autogen/RTE_Components.h + autogen/sl_board_default_init.c + autogen/sl_component_catalog.h + autogen/sl_device_init_clocks.c + autogen/sl_event_handler.c + autogen/sl_event_handler.h + autogen/sl_mbedtls_config_transform_autogen.h + autogen/sl_ot_init.c + autogen/sl_ot_init.h + autogen/sl_uartdrv_init.c + autogen/sl_uartdrv_instances.h + config/dmadrv_config.h + config/emlib_core_debug_config.h + config/mbedtls_config.h + config/nvm3_default_config.h + config/psa_crypto_config.h + config/SEGGER_RTT_Conf.h + config/sl_board_control_config.h + config/sl_debug_swo_config.h + config/sl_device_init_dcdc_config.h + config/sl_device_init_emu_config.h + config/sl_device_init_hfxo_config.h + config/sl_device_init_lfxo_config.h + config/sl_memory_config.h + config/sl_mx25_flash_shutdown_usart_config.h + config/sl_rail_util_pa_config.h + config/sl_rail_util_pti_config.h + config/sl_rail_util_rssi_config.h + config/sl_sleeptimer_config.h + config/sl_uartdrv_usart_vcom_config.h + config/uartdrv_config.h +) + +target_sources(openthread-efr32-rcp-sdk PRIVATE ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S) +set_property(SOURCE ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S PROPERTY LANGUAGE C) + +# ============================================================================== +# Compile Options +# ============================================================================== +target_compile_options(openthread-efr32-rcp-sdk PRIVATE + -Wno-unused-parameter + -Wno-missing-field-initializers + + # GNU C flags + $<$: + "SHELL:-mcpu=cortex-m4" + "SHELL:-mthumb" + "SHELL:-mfpu=fpv4-sp-d16" + "SHELL:-mfloat-abi=softfp" + "SHELL:-std=c99" + "SHELL:-Wall" + "SHELL:-Wextra" + "SHELL:-Os" + "SHELL:-fdata-sections" + "SHELL:-ffunction-sections" + "SHELL:-fomit-frame-pointer" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:--specs=nano.specs" + "SHELL:-g" + > +) + +# ============================================================================== +# Linking +# ============================================================================== +target_link_libraries(openthread-efr32-rcp-sdk + PUBLIC + openthread-efr32-rcp-mbedtls + PRIVATE + -lstdc++ + -lgcc + -lc + -lm + -lnosys + "${SILABS_GSDK_DIR}/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a" + "${SILABS_GSDK_DIR}/protocol/openthread/libs/libsl_openthread_efr32mg1x_gcc.a" + "${SILABS_GSDK_DIR}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg12_gcc_release.a" + openthread-efr32-rcp-config + ot-config +) + +# ============================================================================== +# Linker Flags +# ============================================================================== +target_link_options(openthread-efr32-rcp-sdk PRIVATE + -mcpu=cortex-m4 + -mthumb + -mfpu=fpv4-sp-d16 + -mfloat-abi=softfp + -Wl,--gc-sections +) diff --git a/src/platform_libs/openthread-efr32-soc-eero/CMakeLists.txt b/src/platform_libs/openthread-efr32-soc-eero/CMakeLists.txt new file mode 100644 index 00000000..b57c30a6 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/CMakeLists.txt @@ -0,0 +1,239 @@ +#################################################################### +# Automatically-generated file. Do not edit! # +# CMake Version 1 # +#################################################################### +# +# Copyright (c) 2022, The OpenThread Authors. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +include(${PROJECT_SOURCE_DIR}/third_party/silabs/cmake/utility.cmake) +include(openthread-efr32-soc-sdk.cmake) + +# ============================================================================== +# Platform library +# ============================================================================== +add_library(openthread-efr32-soc + $ +) + +# Interface lib for sharing efr32 config to relevant targets +add_library(openthread-efr32-soc-config INTERFACE) + +set_target_properties(openthread-efr32-soc + PROPERTIES + C_STANDARD 99 + CXX_STANDARD 11 +) + +# ============================================================================== +# Includes +# ============================================================================== +target_include_directories(ot-config INTERFACE + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include + ${SILABS_GSDK_DIR}/platform/common/inc + ${SILABS_GSDK_DIR}/hardware/board/inc + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc + ${SILABS_GSDK_DIR}/platform/driver/debug/inc + ${SILABS_GSDK_DIR}/platform/service/device_init/inc + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc + ${SILABS_GSDK_DIR}/platform/emlib/inc + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/include + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/library + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc + ${SILABS_GSDK_DIR}/platform/service/mpu/inc + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms/utils + ${PROJECT_SOURCE_DIR}/src/src + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154 + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc + ${SILABS_GSDK_DIR}/platform/service/system/inc + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc + ${SILABS_GSDK_DIR}/platform/service/udelay/inc +) + +target_include_directories(openthread-efr32-soc-config INTERFACE + autogen + config +) + +target_link_libraries(openthread-ftd PUBLIC openthread-efr32-soc-config) +target_link_libraries(openthread-mtd PUBLIC openthread-efr32-soc-config) + +target_include_directories(openthread-efr32-soc PRIVATE + ${OT_PUBLIC_INCLUDES} +) + +# ============================================================================== +# Sources +# ============================================================================== +target_sources(openthread-efr32-soc PRIVATE + ${PROJECT_SOURCE_DIR}/src/src/alarm.c + ${PROJECT_SOURCE_DIR}/src/src/board_config.h + ${PROJECT_SOURCE_DIR}/src/src/crypto.c + ${PROJECT_SOURCE_DIR}/src/src/diag.c + ${PROJECT_SOURCE_DIR}/src/src/entropy.c + ${PROJECT_SOURCE_DIR}/src/src/flash.c + ${PROJECT_SOURCE_DIR}/src/src/ieee802154-packet-utils.cpp + ${PROJECT_SOURCE_DIR}/src/src/ieee802154-packet-utils.hpp + ${PROJECT_SOURCE_DIR}/src/src/ieee802154mac.h + ${PROJECT_SOURCE_DIR}/src/src/logging.c + ${PROJECT_SOURCE_DIR}/src/src/memory.c + ${PROJECT_SOURCE_DIR}/src/src/misc.c + ${PROJECT_SOURCE_DIR}/src/src/openthread-core-efr32-config-check.h + ${PROJECT_SOURCE_DIR}/src/src/openthread-core-efr32-config.h + ${PROJECT_SOURCE_DIR}/src/src/platform-band.h + ${PROJECT_SOURCE_DIR}/src/src/platform-efr32.h + ${PROJECT_SOURCE_DIR}/src/src/radio.c + ${PROJECT_SOURCE_DIR}/src/src/rail_config.h + ${PROJECT_SOURCE_DIR}/src/src/security_manager.c + ${PROJECT_SOURCE_DIR}/src/src/security_manager.h + ${PROJECT_SOURCE_DIR}/src/src/sl_openthread.h + ${PROJECT_SOURCE_DIR}/src/src/sl_packet_utils.h + ${PROJECT_SOURCE_DIR}/src/src/startup-gcc.c + ${PROJECT_SOURCE_DIR}/src/src/system.c + ${PROJECT_SOURCE_DIR}/src/src/uartdrv_uart.c +) + +# ============================================================================== +# Compile definitions +# ============================================================================== +target_compile_definitions(ot-config INTERFACE + EFR32MG12P432F1024GL125=1 + SL_BOARD_NAME="BRD4161A" + SL_BOARD_REV="A03" + SL_COMPONENT_CATALOG_PRESENT=1 + MBEDTLS_CONFIG_FILE= + OPENTHREAD_CONFIG_ENABLE_BUILTIN_MBEDTLS=0 + OPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE="openthread-core-efr32-config-check.h" + OPENTHREAD_PROJECT_CORE_CONFIG_FILE="openthread-core-efr32-config.h" + PSA_WANT_ALG_TLS12_PRF=1 + BUFFER_SIZE_DOWN=0 + BUFFER_SIZE_UP=768 + MBEDTLS_PSA_CRYPTO_CONFIG_FILE= + SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT=0 + SL_RAIL_UTIL_PA_CONFIG_HEADER= + RTT_USE_ASM=0 + SEGGER_RTT_SECTION="SEGGER_RTT" +) + +target_compile_options(openthread-efr32-soc PRIVATE + # GNU C flags + $<$: + "SHELL:-mcpu=cortex-m4" + "SHELL:-mthumb" + "SHELL:-mfpu=fpv4-sp-d16" + "SHELL:-mfloat-abi=softfp" + "SHELL:-std=c99" + "SHELL:-Wall" + "SHELL:-Wextra" + "SHELL:-Os" + "SHELL:-fdata-sections" + "SHELL:-ffunction-sections" + "SHELL:-fomit-frame-pointer" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:--specs=nano.specs" + "SHELL:-g" + > +) + +# ============================================================================== +# Linking +# ============================================================================== +set(LD_FILE "${CMAKE_CURRENT_SOURCE_DIR}/autogen/linkerfile.ld") +set(openthread-efr32-soc-sdk_location $) + +target_link_libraries(openthread-efr32-soc + PUBLIC + -lstdc++ + -lgcc + -lc + -lm + -lnosys + openthread-efr32-soc-config + + PRIVATE + -T${LD_FILE} + -Wl,--gc-sections + + # The --whole-archive flags are necessary to resolve all symbols from the GSDK + -Wl,--whole-archive ${openthread-efr32-soc-sdk_location} -Wl,--no-whole-archive + ot-config +) + +target_link_options(openthread-efr32-soc PRIVATE + -mcpu=cortex-m4 + -mthumb + -mfpu=fpv4-sp-d16 + -mfloat-abi=softfp + -Wl,--gc-sections +) + +# ============================================================================== +# Static libraries from GSDK +# ============================================================================== +set(GSDK_LIBS + "${SILABS_GSDK_DIR}/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a" + "${SILABS_GSDK_DIR}/protocol/openthread/libs/libsl_openthread_efr32mg1x_gcc.a" + "${SILABS_GSDK_DIR}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg12_gcc_release.a" +) + +# Import GSDK static libs and set a dependency on the GSDK library +# This will ensure proper linking order +foreach(lib_file ${GSDK_LIBS}) + # Parse lib name, stripping .a extension + get_filename_component(lib_name ${lib_file} NAME_WE) + set(imported_lib_name "silabs-${lib_name}") + + # Add as an IMPORTED lib + add_library(${imported_lib_name} STATIC IMPORTED) + set_target_properties(${imported_lib_name} + PROPERTIES + IMPORTED_LOCATION "${lib_file}" + IMPORTED_LINK_INTERFACE_LIBRARIES openthread-efr32-soc-sdk + ) + target_link_libraries(openthread-efr32-soc PUBLIC ${imported_lib_name}) +endforeach() diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/.crc_config.crc b/src/platform_libs/openthread-efr32-soc-eero/autogen/.crc_config.crc new file mode 100644 index 00000000..ae029726 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/.crc_config.crc @@ -0,0 +1,21 @@ +#CRC Codes for initially generated config files -- do not modify! +SEGGER_RTT_Conf.h=-674599354 +dmadrv_config.h=-894158991 +emlib_core_debug_config.h=171843933 +mbedtls_config.h=-1681532838 +nvm3_default_config.h=1109545002 +psa_crypto_config.h=-715200899 +sl_board_control_config.h=-858618493 +sl_debug_swo_config.h=848473986 +sl_device_init_dcdc_config.h=-1223674373 +sl_device_init_emu_config.h=1414330218 +sl_device_init_hfxo_config.h=349146444 +sl_device_init_lfxo_config.h=239925891 +sl_memory_config.h=1344294468 +sl_mx25_flash_shutdown_usart_config.h=330822538 +sl_rail_util_pa_config.h=1112608945 +sl_rail_util_pti_config.h=1157262329 +sl_rail_util_rssi_config.h=-1255858871 +sl_sleeptimer_config.h=-1074849105 +sl_uartdrv_usart_vcom_config.h=108701171 +uartdrv_config.h=-1381003705 \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/RTE_Components.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/RTE_Components.h new file mode 100644 index 00000000..3b6ea30c --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/RTE_Components.h @@ -0,0 +1,22 @@ +// This file is autogenerated by Silicon Labs SLC. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Silicon Labs SLC. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/linkerfile.ld b/src/platform_libs/openthread-efr32-soc-eero/autogen/linkerfile.ld new file mode 100644 index 00000000..62217d8a --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/linkerfile.ld @@ -0,0 +1,221 @@ +/***************************************************************************//** + * GCC Linker script for Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + MEMORY + { + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 + } + +ENTRY(Reset_Handler) + +SECTIONS +{ + + .text : + { + linker_vectors_begin = .; + KEEP(*(.vectors)) + linker_vectors_end = .; + + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + + linker_code_begin = .; + *(.text*) + linker_code_end = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + *(.eh_frame*) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + __etext = .; + + /* Start placing output sections which are loaded into RAM */ + . = ORIGIN(RAM); + + .stack ALIGN(8) (NOLOAD): + { + __StackLimit = .; + KEEP(*(.stack*)) + . = ALIGN(4); + __StackTop = .; + PROVIDE(__stack = __StackTop); + } > RAM + + + .noinit . (NOLOAD): + { + *(.noinit*); + } > RAM + + .data . : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + + PROVIDE(__ram_func_section_start = .); + *(.ram) + PROVIDE(__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss . : + { + . = ALIGN(4); + __bss_start__ = .; + *(SEGGER_RTT) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM); + __HeapLimit = .; + } > RAM + + __heap_size = __HeapLimit - __HeapBase; + __main_flash_end__ = 0x0 + 0x100000; + + /* This is where we handle flash storage blocks. We use dummy sections for finding the configured + * block sizes and then "place" them at the end of flash when the size is known. */ + .internal_storage (DSECT) : { + KEEP(*(.internal_storage*)) + } > FLASH + + + .nvm (DSECT) : { + KEEP(*(.simee*)) + } > FLASH + + linker_nvm_end = __main_flash_end__; + linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); + linker_nvm_size = SIZEOF(.nvm); + linker_storage_end = linker_nvm_begin; + __nvm3Base = linker_nvm_begin; + + linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); + linker_storage_size = SIZEOF(.internal_storage); + ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") + + +} diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/mbedtls_config_autogen.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/mbedtls_config_autogen.h new file mode 100644 index 00000000..51821bab --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/mbedtls_config_autogen.h @@ -0,0 +1,108 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef MBEDTLS_CONFIG_AUTOGEN_H +#define MBEDTLS_CONFIG_AUTOGEN_H + + +#define MBEDTLS_MPI_MAX_SIZE 32 + + +#define MBEDTLS_AES_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#define MBEDTLS_BASE64_C +#define MBEDTLS_CCM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_CMAC_C +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECDH_C +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_HMAC_DRBG_C +#define MBEDTLS_ENTROPY_HARDWARE_ALT +#define MBEDTLS_ENTROPY_RAIL_PRESENT +#define MBEDTLS_MD_C +#define MBEDTLS_ECJPAKE_C +#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_PEM_PARSE_C +#define MBEDTLS_PEM_WRITE_C +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_ENTROPY_FORCE_SHA256 +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 +#define MBEDTLS_NO_PLATFORM_ENTROPY +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SHA224_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CREATE_C +#define MBEDTLS_X509_CRT_PARSE_C +#define MBEDTLS_X509_CRT_WRITE_C +#define MBEDTLS_X509_CRL_PARSE_C +#define MBEDTLS_X509_CSR_PARSE_C +#define MBEDTLS_X509_CSR_WRITE_C +#define MBEDTLS_OID_C +#define MBEDTLS_USE_PSA_CRYPTO +#define MBEDTLS_PSA_CRYPTO_C +#define MBEDTLS_PSA_CRYPTO_CONFIG +#define MBEDTLS_PSA_CRYPTO_DRIVERS +#define MBEDTLS_PSA_CRYPTO_STORAGE_C + + +#include "config-device-acceleration.h" + +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) || defined(SL_SE_ASSUME_FW_AT_LEAST_2_1_7) + #undef MBEDTLS_ECP_DP_CURVE25519_ENABLED + #if !(defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED)) + #undef MBEDTLS_ECDH_C + #undef MBEDTLS_ECP_C + #undef MBEDTLS_BIGNUM_C + #endif /* !MBEDTLS_ECP_DP_SECPxR1_ENABLED */ +#endif /* SL_SE_ASSUME_FW_AT_LEAST_x */ + +#if !defined(TEST_SUITE_MEMORY_BUFFER_ALLOC) +#if !defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#if defined(CONFIG_MBEDTLS_USE_FREERTOS_PVCALLOC) + /* In FreeRTOS, use pvCalloc (and vPortFree) for dynamic memory allocation. + E.g. Amazon FreeRTOS implements pvCalloc for dynamic memory allocation. */ + #include + + extern void * pvCalloc( size_t xNumElements, + size_t xSize ) ; + extern void vPortFree( void *pv ); + #define MBEDTLS_PLATFORM_CALLOC_MACRO pvCalloc + #define MBEDTLS_PLATFORM_FREE_MACRO vPortFree +#else + /* No memory allocator override, supply the default for SL platforms */ + #include "sl_malloc.h" + + #define MBEDTLS_PLATFORM_FREE_MACRO sl_free + #define MBEDTLS_PLATFORM_CALLOC_MACRO sl_calloc +#endif +#endif /* No specific memory allocator override */ +#endif /* Not under test */ + +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_C + + + +#endif diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/psa_crypto_config_autogen.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/psa_crypto_config_autogen.h new file mode 100644 index 00000000..c80b3a77 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/psa_crypto_config_autogen.h @@ -0,0 +1,121 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef PSA_CRYPTO_CONFIG_AUTOGEN_H +#define PSA_CRYPTO_CONFIG_AUTOGEN_H + +#define PSA_WANT_KEY_TYPE_AES +#define PSA_WANT_ALG_CMAC +#define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1 +#define PSA_WANT_ALG_SHA_224 +#define PSA_WANT_ALG_SHA_256 +#define PSA_WANT_ALG_CCM +#define PSA_WANT_ALG_CBC_NO_PADDING +#define PSA_WANT_ALG_ECB_NO_PADDING +#define PSA_WANT_ALG_ECDSA +#define PSA_WANT_ALG_ECDH +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY +#define PSA_WANT_ECC_SECP_R1_256 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR 1 +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 +#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 +#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_HKDF +#define PSA_WANT_ALG_HMAC +#define PSA_WANT_KEY_TYPE_HMAC +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG +#define MBEDTLS_PSA_ACCEL_ALG_SHA_1 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_224 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_256 +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_AES +#define MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7 +#define MBEDTLS_PSA_ACCEL_ALG_CTR +#define MBEDTLS_PSA_ACCEL_ALG_CFB +#define MBEDTLS_PSA_ACCEL_ALG_OFB +#define MBEDTLS_PSA_ACCEL_ALG_GCM +#define MBEDTLS_PSA_ACCEL_ALG_CCM +#define MBEDTLS_PSA_ACCEL_ALG_CMAC + +#define MBEDTLS_PSA_KEY_SLOT_COUNT (15 + 1 + SL_PSA_KEY_USER_SLOT_COUNT) +#define SL_PSA_ITS_MAX_FILES (1 + SL_PSA_ITS_USER_MAX_FILES) + +#include "config-device-acceleration.h" +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) || defined(SL_SE_ASSUME_FW_AT_LEAST_2_1_7) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 + #undef MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 + #if !(defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED)) + #undef MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR + #undef MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY + #undef MBEDTLS_PSA_BUILTIN_ALG_ECDH + #endif /* !MBEDTLS_ECP_DP_SECPxR1_ENABLED */ +#endif /* SL_SE_ASSUME_FW_AT_LEAST_x */ + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// Asymmetric Crypt module (RSA is not supported) +#define TFM_CRYPTO_ASYM_ENCRYPT_MODULE_DISABLED + +// HASH module +#if !defined(PSA_WANT_ALG_SHA_1) \ + && !defined(PSA_WANT_ALG_SHA_224) \ + && !defined(PSA_WANT_ALG_SHA_256) \ + && !defined(PSA_WANT_ALG_SHA_384) \ + && !defined(PSA_WANT_ALG_SHA_512) \ + && !defined(PSA_WANT_ALG_MD5) +#define TFM_CRYPTO_HASH_MODULE_DISABLED +#endif + +// AEAD module +#if !defined(PSA_WANT_ALG_CCM) \ + && !defined(PSA_WANT_ALG_GCM) \ + && !defined(PSA_WANT_ALG_CHACHA20_POLY1305) +#define TFM_CRYPTO_AEAD_MODULE_DISABLED +#endif + +// Asymmetric Sign module +#if !defined(PSA_WANT_ALG_ECDSA) \ + && !defined(PSA_WANT_ALG_EDDSA) \ + && !defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) +#define TFM_CRYPTO_ASYM_SIGN_MODULE_DISABLED +#endif + +// Cipher module +#if !defined(PSA_WANT_ALG_CFB) \ + && !defined(PSA_WANT_ALG_CTR) \ + && !defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + && !defined(PSA_WANT_ALG_CBC_PKCS7) \ + && !defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + && !defined(PSA_WANT_ALG_XTS) \ + && !defined(PSA_WANT_ALG_OFB) \ + && !defined(PSA_WANT_ALG_STREAM_CIPHER) +#define TFM_CRYPTO_CIPHER_MODULE_DISABLED +#endif + +// MAC module +#if !defined(PSA_WANT_ALG_HMAC) \ + && !defined(PSA_WANT_ALG_CMAC) \ + && !defined(PSA_WANT_ALG_CBC_MAC) +#define TFM_CRYPTO_MAC_MODULE_DISABLED +#endif + +// Key derivation module +#if !defined(PSA_WANT_ALG_PBKDF2_HMAC) \ + && !defined(PSA_WANT_ALG_HKDF) \ + && !defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) \ + && !defined(PSA_WANT_ALG_TLS12_PRF) \ + && !defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) \ + && !defined(PSA_WANT_ALG_ECDH) +#define TFM_CRYPTO_KEY_DERIVATION_MODULE_DISABLED +#endif + +#endif // TFM_CONFIG_SL_SECURE_LIBRARY + +#endif diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_board_default_init.c b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_board_default_init.c new file mode 100644 index 00000000..bd43db36 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_board_default_init.c @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_component_catalog.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_component_catalog.h new file mode 100644 index 00000000..742c8123 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_component_catalog.h @@ -0,0 +1,17 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_MPU_PRESENT +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT +#define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_PSA_CRYPTO_PRESENT +#define SL_CATALOG_RAIL_LIB_PRESENT +#define SL_CATALOG_RAIL_UTIL_PTI_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT +#define SL_CATALOG_UARTDRV_USART_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_device_init_clocks.c b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_device_init_clocks.c new file mode 100644 index 00000000..9349ba24 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_device_init_clocks.c @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.c b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.c new file mode 100644 index 00000000..b1566c5c --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.c @@ -0,0 +1,86 @@ +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "pa_conversions_efr32.h" +#include "sl_rail_util_pti.h" +#include "sl_rail_util_rssi.h" +#include "sl_board_control.h" +#include "platform-efr32.h" +#include "sl_sleeptimer.h" +#include "sl_debug_swo.h" +#include "gpiointerrupt.h" +#include "sl_mbedtls.h" +#include "sl_mpu.h" +#include "nvm3_default.h" +#include "sl_ot_init.h" +#include "sl_uartdrv_instances.h" +#include "psa/crypto.h" +#include "sl_cos.h" + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_lfxo(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + nvm3_initDefault(); +} + +void sl_driver_init(void) +{ + sl_debug_swo_init(); + GPIOINT_Init(); + sl_uartdrv_init_instances(); + sl_cos_send_config(); +} + +void sl_service_init(void) +{ + sl_board_configure_vcom(); + sl_sleeptimer_init(); + sl_mbedtls_init(); + sl_mpu_disable_execute_from_ram(); + psa_crypto_init(); +} + +void sl_stack_init(void) +{ + sl_rail_util_pa_init(); + sl_rail_util_pti_init(); + sl_rail_util_rssi_init(); + sl_ot_sys_init(); +} + +void sl_internal_app_init(void) +{ + sl_ot_init(); +} + +void sl_platform_process_action(void) +{ +} + +void sl_service_process_action(void) +{ +} + +void sl_stack_process_action(void) +{ +} + +void sl_internal_app_process_action(void) +{ +} + diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.h new file mode 100644 index 00000000..89299544 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_event_handler.h @@ -0,0 +1,14 @@ +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_platform_process_action(void); +void sl_service_process_action(void); +void sl_stack_process_action(void); +void sl_internal_app_process_action(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_mbedtls_config_transform_autogen.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_mbedtls_config_transform_autogen.h new file mode 100644 index 00000000..c787ba5b --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_mbedtls_config_transform_autogen.h @@ -0,0 +1,62 @@ +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H +#define SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H + +// Convert CMSIS Markup config defines to mbedTLS specific config defines + +// Allow undefining the specified cipher suites +#if defined(SLI_MBEDTLS_AUTODETECT_CIPHERSUITES) +#undef MBEDTLS_SSL_CIPHERSUITES +#endif + +#if SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#endif +#if SL_MBEDTLS_SSL_EXPORT_KEYS + #define MBEDTLS_SSL_EXPORT_KEYS +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#endif + +#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) + #define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN +#endif + +#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) + #define MBEDTLS_SSL_OUT_CONTENT_LEN SL_MBEDTLS_SSL_OUT_CONTENT_LEN +#endif + + +#define SLI_SSL_IN_CONTENT_LEN_REQUIREMENT 900 + +// If the SDK requires a certain SSL buffer size, configure Mbed TLS +// to size the buffer to the highest of the user/default or SDK setting. +#if MBEDTLS_SSL_IN_CONTENT_LEN < SLI_SSL_IN_CONTENT_LEN_REQUIREMENT + #undef MBEDTLS_SSL_IN_CONTENT_LEN + #define MBEDTLS_SSL_IN_CONTENT_LEN SLI_SSL_IN_CONTENT_LEN_REQUIREMENT +#endif + + + +#define SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT 900 + +// If the SDK requires a certain SSL buffer size, configure Mbed TLS +// to size the buffer to the highest of the user/default or SDK setting. +#if MBEDTLS_SSL_OUT_CONTENT_LEN < SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT + #undef MBEDTLS_SSL_OUT_CONTENT_LEN + #define MBEDTLS_SSL_OUT_CONTENT_LEN SLI_SSL_OUT_CONTENT_LEN_REQUIREMENT +#endif + + +#endif // SL_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.c b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.c new file mode 100644 index 00000000..df8c81f3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.c @@ -0,0 +1,5 @@ +#include "sl_ot_init.h" + +void sl_ot_init(void) +{ +} \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.h new file mode 100644 index 00000000..0e73d3b3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_ot_init.h @@ -0,0 +1,27 @@ +/***************************************************************************/ +/** + * @file + * @brief This generated header includes declaration of all functions required + * during initialization that must be defined by the OpenThread application. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * + * https://www.silabs.com/about-us/legal/master-software-license-agreement + * + * This software is distributed to you in Source Code format and is governed by + * the sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_OT_INIT_H +#define SL_OT_INIT_H + +void sl_ot_init(void); + +#endif // SL_OT_INIT_H \ No newline at end of file diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_init.c b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_init.c new file mode 100644 index 00000000..ab0bb51b --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_instances.h b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_instances.h new file mode 100644 index 00000000..894c73f8 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/SEGGER_RTT_Conf.h b/src/platform_libs/openthread-efr32-soc-eero/config/SEGGER_RTT_Conf.h new file mode 100644 index 00000000..ca8df42d --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/SEGGER_RTT_Conf.h @@ -0,0 +1,417 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.30 * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 21386 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* + * + * Defines, configurable + * + ********************************************************************** + */ +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* + * + * RTT memcpy configuration + * + * memcpy() is good for large amounts of data, + * but the overhead is big for small amounts, which are usually stored via RTT. + * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. + * + * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. + * This is may be required with memory access restrictions, + * such as on Cortex-A devices with MMU. + */ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* + * + * RTT lock configuration for SEGGER Embedded Studio, + * Rowley CrossStudio and GCC + */ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i" (SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif defined(__ARM_ARCH_7A__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR EWARM + */ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RX + */ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RL78 + */ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for KEIL ARM + */ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm("basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for TI ARM + */ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for CCRX + */ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for embOS Simulation on Windows + * (Can also be used for generic RTT locking with embOS) + */ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration fallback + */ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +/********************************************************************* + * + * RTT control block configuration + */ +#define SEGGER_RTT_ALIGNMENT 1024 + +#endif +/*************************** End of file ****************************/ diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/dmadrv_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/dmadrv_config.h new file mode 100644 index 00000000..9aa48db5 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/dmadrv_config.h @@ -0,0 +1,26 @@ +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-7> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 4 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 + +// Number of available channels <1-8> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 8 +#define EMDRV_DMADRV_DMA_CH_COUNT 8 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/emlib_core_debug_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/emlib_core_debug_config.h new file mode 100644 index 00000000..50dbbed9 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/emlib_core_debug_config.h @@ -0,0 +1,46 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +// If Enabled, either cycle_counter or systemview component must be added to project. +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/mbedtls_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/mbedtls_config.h new file mode 100644 index 00000000..9608a1af --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/mbedtls_config.h @@ -0,0 +1,72 @@ +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +// Include the autogenerated mbedtls configuration file +#include "mbedtls_config_autogen.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// TLS/DTLS configuration + +// Complete list of ciphersuites to use, in order of preference. +// Default: MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 +// Complete list of ciphersuites to use, in order of preference. +// The value of this configuration should be updated for the application needs. +#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + +// Maximum TLS/DTLS fragment length in bytes (input). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when receiving data. +#define SL_MBEDTLS_SSL_IN_CONTENT_LEN 768 + +// Maximum TLS/DTLS fragment length in bytes (output). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when sending data. +#define SL_MBEDTLS_SSL_OUT_CONTENT_LEN 768 + +// Enable support for RFC 6066 max_fragment_length extension in SSL. +// Default: 1 +// Enable support for RFC 6066 max_fragment_length extension in SSL. +#define SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1 + +// Enable support for exporting key block and master secret. +// Default: 1 +// Enable support for exporting key block and master secret. +// This is required for certain users of TLS, e.g. EAP-TLS. +#define SL_MBEDTLS_SSL_EXPORT_KEYS 1 + +// Enable the PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED 1 + +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED 0 + +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED 1 + +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED 0 + +// +// <<< end of configuration section >>> + +// Include transformation logic to apply CMSIS-config configuration options to +// the correct Mbed TLS / PSA Crypto options. +#include "sl_mbedtls_config_transform_autogen.h" + +// Custom defines can be placed here before check_config.h is included. + +#include "mbedtls/config_psa.h" + +#include "mbedtls/check_config.h" + +#endif diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/nvm3_default_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/nvm3_default_config.h new file mode 100644 index 00000000..ba2982c2 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/nvm3_default_config.h @@ -0,0 +1,45 @@ +#ifndef NVM3_DEFAULT_CONFIG_H +#define NVM3_DEFAULT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// NVM3 Default Instance Configuration + +#ifndef NVM3_DEFAULT_CACHE_SIZE +// NVM3 Default Instance Cache Size +// Number of NVM3 objects to cache. To reduce access times this number +// should be equal to or higher than the number of NVM3 objects in the +// default NVM3 instance. +// Default: 200 +#define NVM3_DEFAULT_CACHE_SIZE 200 +#endif + +#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE +// NVM3 Default Instance Max Object Size +// Max NVM3 object size that can be stored. +// Default: 254 +#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 +#endif + +#ifndef NVM3_DEFAULT_REPACK_HEADROOM +// NVM3 Default Instance User Repack Headroom +// Headroom determining how many bytes below the forced repack limit the user +// repack limit should be placed. The default is 0, which means the user and +// forced repack limits are equal. +// Default: 0 +#define NVM3_DEFAULT_REPACK_HEADROOM 0 +#endif + +#ifndef NVM3_DEFAULT_NVM_SIZE +// NVM3 Default Instance Size +// Size of the NVM3 storage region in flash. This size should be aligned with +// the flash page size of the device. +// Default: 36864 +#define NVM3_DEFAULT_NVM_SIZE 36864 +#endif + +// + +// <<< end of configuration section >>> + +#endif // NVM3_DEFAULT_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/psa_crypto_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/psa_crypto_config.h new file mode 100644 index 00000000..557606d1 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/psa_crypto_config.h @@ -0,0 +1,47 @@ +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PSA User Maximum Open Keys Count <0-128> +// Maximum amount of keys that the user application will have open +// simultaneously. In context of PSA Crypto, an open key means any key +// either stored in RAM (lifetime set to PSA_KEY_LIFETIME_VOLATILE), or +// used as part of a cryptographic operation. +// When using a key for a multi-part (setup/update/finish) operation, a key +// is considered to be open from the moment the operation is successfully +// setup, until it finishes or aborts. +// When an application tries to open more keys than this value accounts for, +// the PSA API may return PSA_ERROR_INSUFFICIENT_MEMORY. Keep in mind that +// other software included in the application (e.g. wireless protocol stacks) +// also can have a need to have open keys in PSA Crypto. This could lead to +// a race condition when the application key slot count is set too low for +// the actual usage of the application, as a software stack may not fail +// gracefully in case an application opens more than its declared amount of +// keys, thereby precluding the stack from functioning. +// Default: 4 +#define SL_PSA_KEY_USER_SLOT_COUNT (4) + +// PSA Maximum User Persistent Keys Count <0-1024> +// Maximum amount of keys (or other files) that can be stored persistently +// by the application through the PSA interface, when persistent storage +// support for PSA Crypto is included in the project. +// Due to caching logic, this setting does have an impact on static RAM usage. +// Note that this number is added to the potential requirements from other +// software components in the project, such that the total amount of keys +// which can be stored through the ITS backend can be higher than what is +// configured here. +// +// WARNING: When changing this setting on an application that is already +// deployed, and thus will get the change through an application upgrade, +// care should be taken to ensure that the setting is only ever increased, +// and never decreased. Decreasing this setting might cause previously +// stored keys/files to become inaccessible. +// Default: 128 +#define SL_PSA_ITS_USER_MAX_FILES (128) +// <<< end of configuration section >>> + +// Include the autogenerated PSA Crypto configuration file +#include "psa_crypto_config_autogen.h" + +#endif // PSA_CRYPTO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_board_control_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_board_control_config.h new file mode 100644 index 00000000..e75b074f --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortA +#define SL_BOARD_ENABLE_VCOM_PIN 5 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortD +#define SL_BOARD_ENABLE_DISPLAY_PIN 15 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 10 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_debug_swo_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_debug_swo_config.h new file mode 100644 index 00000000..bd2964af --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_debug_swo_config.h @@ -0,0 +1,100 @@ +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[DBG_SL_DEBUG] +#define SL_DEBUG_PERIPHERAL DBG + +#define SL_DEBUG_SWV_PORT gpioPortF +#define SL_DEBUG_SWV_PIN 2 +#define SL_DEBUG_SWV_LOC 0 +// [DBG_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_dcdc_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_dcdc_config.h new file mode 100644 index 00000000..734aed36 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 0 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL DCDC_PFMXCTRL_IPKVAL_DEFAULT + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_emu_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_emu_config.h new file mode 100644 index 00000000..387abf94 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_emu_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_EMU Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_EMU_CONFIG_H +#define SL_DEVICE_INIT_EMU_CONFIG_H + +#include "em_emu.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// EM4H Voltage scaling level +// Fast-wakeup voltage level +// Low-power optimized voltage level +// Default: emuVScaleEM4H_LowPower +#define SL_DEVICE_INIT_EMU_EM4_VSCALE emuVScaleEM4H_LowPower + +// Retain LFXO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFXO 0 + +// Retain LFRCO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFRCO 0 + +// Retain ULFRCO in EM4S +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_ULFRCO 0 + +// Hibernate or shutoff EM4 state +// EM4 Shutoff +// EM4 Hibernate +// Default: emuEM4Shutoff +#define SL_DEVICE_INIT_EMU_EM4_STATE emuEM4Shutoff + +// EM4 pin retention mode +// No Retention: Pads enter reset state when entering EM4. +// Retention through EM4: Pads enter reset state when exiting EM4. +// Retention through EM4 and wakeup. +// Default: emuPinRetentionDisable +#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_EMU_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_hfxo_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_hfxo_config.h new file mode 100644 index 00000000..ccd1c239 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_hfxo_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 327 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_lfxo_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_lfxo_config.h new file mode 100644 index 00000000..d4b79b3d --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_device_init_lfxo_config.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 32 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_memory_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_memory_config.h new file mode 100644 index 00000000..8a9d0bc4 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_memory_config.h @@ -0,0 +1,28 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 4608 +#endif + +// Minimum heap size for the application. +// Default: 2048 +// Note that this value will configure the c heap which is normally used by +// malloc() and free() from the c library. The value defines a minimum heap +// size that is guaranteed to be available. The available heap may be larger +// to make use of any memory that would otherwise remain unused. +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 2048 +#endif + +// +// <<< end of configuration section >>> + +#endif diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_mx25_flash_shutdown_usart_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 00000000..742762a3 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,54 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// USART1 TX on PC6 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 6 +#define SL_MX25_FLASH_SHUTDOWN_TX_LOC 11 + +// USART1 RX on PC7 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 7 +#define SL_MX25_FLASH_SHUTDOWN_RX_LOC 11 + +// USART1 CLK on PC8 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 8 +#define SL_MX25_FLASH_SHUTDOWN_CLK_LOC 11 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pa_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pa_config.h new file mode 100644 index 00000000..09a4e6f0 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pa_config.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 +// 2.4 GHz PA Selection +// High Power +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HP +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HP +// Sub-1 GHz PA Selection +// Enable +// Disable +// Default: RAIL_TX_POWER_MODE_SUBGIG +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pti_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pti_config.h new file mode 100644 index 00000000..e5ea09f6 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_pti_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PB12 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DOUT_PIN 12 +#define SL_RAIL_UTIL_PTI_DOUT_LOC 6 + +// PTI DFRAME on PB13 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 13 +#define SL_RAIL_UTIL_PTI_DFRAME_LOC 6 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_rssi_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_rssi_config.h new file mode 100644 index 00000000..3c60beb8 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_rail_util_rssi_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief RSSI configuration header file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_RSSI_CONFIG_H +#define SL_RAIL_UTIL_RSSI_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RSSI Offset Configuration + +// Software RSSI offset value +// Default: -8 +#define SL_RAIL_UTIL_RSSI_OFFSET -8 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_RSSI_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_sleeptimer_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_sleeptimer_config.h new file mode 100644 index 00000000..846d37d6 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_sleeptimer_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/sl_uartdrv_usart_vcom_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 00000000..29b7f57d --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 0 +#define SL_UARTDRV_USART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 1 +#define SL_UARTDRV_USART_VCOM_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 2 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 3 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 30 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/src/platform_libs/openthread-efr32-soc-eero/config/uartdrv_config.h b/src/platform_libs/openthread-efr32-soc-eero/config/uartdrv_config.h new file mode 100644 index 00000000..e1d0a85d --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/src/platform_libs/openthread-efr32-soc-eero/openthread-efr32-soc-sdk.cmake b/src/platform_libs/openthread-efr32-soc-eero/openthread-efr32-soc-sdk.cmake new file mode 100644 index 00000000..9f942ea7 --- /dev/null +++ b/src/platform_libs/openthread-efr32-soc-eero/openthread-efr32-soc-sdk.cmake @@ -0,0 +1,409 @@ +#################################################################### +# Automatically-generated file. Do not edit! # +# CMake Version 1 # +#################################################################### +# +# Copyright (c) 2022, The OpenThread Authors. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +include(${PROJECT_SOURCE_DIR}/third_party/silabs/cmake/utility.cmake) + +# ============================================================================== +# Library of platform dependencies from GSDK and generated config files +# ============================================================================== +add_library(openthread-efr32-soc-sdk) + +set_target_properties(openthread-efr32-soc-sdk + PROPERTIES + C_STANDARD 99 + CXX_STANDARD 11 +) + +# ============================================================================== +# Includes +# ============================================================================== +target_include_directories(openthread-efr32-soc-sdk PUBLIC + config + autogen + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include + ${SILABS_GSDK_DIR}/platform/common/inc + ${SILABS_GSDK_DIR}/hardware/board/inc + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc + ${SILABS_GSDK_DIR}/platform/driver/debug/inc + ${SILABS_GSDK_DIR}/platform/service/device_init/inc + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc + ${SILABS_GSDK_DIR}/platform/emlib/inc + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/include + ${SILABS_GSDK_DIR}/util/third_party/crypto/mbedtls/library + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc + ${SILABS_GSDK_DIR}/platform/service/mpu/inc + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms + ${PROJECT_SOURCE_DIR}/openthread/examples/platforms/utils + ${PROJECT_SOURCE_DIR}/src/src + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154 + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc + ${SILABS_GSDK_DIR}/platform/service/system/inc + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc + ${SILABS_GSDK_DIR}/platform/service/udelay/inc +) + +target_include_directories(openthread-efr32-soc-sdk PRIVATE + ${OT_PUBLIC_INCLUDES} +) + +# ============================================================================== +# Sources +# ============================================================================== +target_sources(openthread-efr32-soc-sdk PRIVATE + ${SILABS_GSDK_DIR}/hardware/board/inc/sl_board_control.h + ${SILABS_GSDK_DIR}/hardware/board/inc/sl_board_init.h + ${SILABS_GSDK_DIR}/hardware/board/src/sl_board_control_gpio.c + ${SILABS_GSDK_DIR}/hardware/board/src/sl_board_init.c + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/inc/sl_cos.h + ${SILABS_GSDK_DIR}/hardware/driver/configuration_over_swo/src/sl_cos.c + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h + ${SILABS_GSDK_DIR}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_compiler.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_gcc.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/cmsis_version.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/core_cm4.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/mpu_armv7.h + ${SILABS_GSDK_DIR}/platform/CMSIS/Core/Include/tz_context.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_assert.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_atomic.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_common.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_enum.h + ${SILABS_GSDK_DIR}/platform/common/inc/sl_status.h + ${SILABS_GSDK_DIR}/platform/common/src/sl_assert.c + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_gcc_preinclude.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_memory.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/inc/sl_memory_region.h + ${SILABS_GSDK_DIR}/platform/common/toolchain/src/sl_memory.c + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p432f1024gl125.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_acmp.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_adc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_pins.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_af_ports.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cmu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_cryotimer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_crypto.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_csen.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_devinfo.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dma_descriptor.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_dmareq.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_emu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_etm.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_fpueh.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpcrc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_gpio_p.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_i2c.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_idac.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_ldma_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_buf.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_lesense_st.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_letimer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_leuart.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_msc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_pcnt.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_ch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_prs_signals.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rmu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_romtable.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_cc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_rtcc_ret.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_smu.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_timer_cc.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_trng.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_usart.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_vdac_opa.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/efr32mg12p_wdog_pch.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/em_device.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Include/system_efr32mg12p.h + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Source/startup_efr32mg12p.c + ${SILABS_GSDK_DIR}/platform/Device/SiliconLabs/EFR32MG12P/Source/system_efr32mg12p.c + ${SILABS_GSDK_DIR}/platform/driver/debug/inc/sl_debug_swo.h + ${SILABS_GSDK_DIR}/platform/driver/debug/src/sl_debug_swo.c + ${SILABS_GSDK_DIR}/platform/emdrv/common/inc/ecode.h + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/inc/dmadrv.h + ${SILABS_GSDK_DIR}/platform/emdrv/dmadrv/src/dmadrv.c + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h + ${SILABS_GSDK_DIR}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_default.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_hal.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_hal_flash.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/inc/nvm3_lock.h + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_default_common_linker.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_hal_flash.c + ${SILABS_GSDK_DIR}/platform/emdrv/nvm3/src/nvm3_lock.c + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/inc/uartdrv.h + ${SILABS_GSDK_DIR}/platform/emdrv/uartdrv/src/uartdrv.c + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_assert.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_bus.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_chip.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_cmu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_cmu_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_common.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_core.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_crypto.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_crypto_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_emu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_gpio.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_ldma.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_leuart.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_msc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_msc_compat.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_prs.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_ramfunc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_rmu.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_rtcc.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_system.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_usart.h + ${SILABS_GSDK_DIR}/platform/emlib/inc/em_version.h + ${SILABS_GSDK_DIR}/platform/emlib/src/em_cmu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_core.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_crypto.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_emu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_gpio.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_ldma.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_leuart.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_msc.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_prs.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_rmu.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_rtcc.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_system.c + ${SILABS_GSDK_DIR}/platform/emlib/src/em_usart.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_assert_error_codes.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_features.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_mfm.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/common/rail_types.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg1x/sl_rail_util_pa_curves.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.c + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ble/rail_ble.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h + ${SILABS_GSDK_DIR}/platform/radio/rail_lib/protocol/zwave/rail_zwave.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_clocks.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_dcdc.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_emu.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_hfxo.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_lfxo.h + ${SILABS_GSDK_DIR}/platform/service/device_init/inc/sl_device_init_nvic.h + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_dcdc_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_emu_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_hfxo_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_lfxo_s1.c + ${SILABS_GSDK_DIR}/platform/service/device_init/src/sl_device_init_nvic.c + ${SILABS_GSDK_DIR}/platform/service/mpu/inc/sl_mpu.h + ${SILABS_GSDK_DIR}/platform/service/mpu/src/sl_mpu.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc/sl_sleeptimer.h + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/inc/sli_sleeptimer.h + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sl_sleeptimer.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c + ${SILABS_GSDK_DIR}/platform/service/sleeptimer/src/sli_sleeptimer_hal.h + ${SILABS_GSDK_DIR}/platform/service/system/inc/sl_system_init.h + ${SILABS_GSDK_DIR}/platform/service/system/inc/sl_system_process_action.h + ${SILABS_GSDK_DIR}/platform/service/system/src/sl_system_init.c + ${SILABS_GSDK_DIR}/platform/service/system/src/sl_system_process_action.c + ${SILABS_GSDK_DIR}/platform/service/udelay/inc/sl_udelay.h + ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay.c + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c + ${SILABS_GSDK_DIR}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-sl-crypto-all-acceleration.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/aes_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/ccm_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/cmac_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/gcm_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha1_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha256_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sha512_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/inc/threading_alt.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/crypto_aes.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/crypto_ecp.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/mbedtls_sha.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_mbedtls.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_crypto.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/crypto_management.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/psa/error.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/psa/internal_trusted_storage.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/public/sl_psa_values.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_transparent_functions.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_transparent_types.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_crypto_trng_driver.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/crypto_management.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_cipher.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_hash.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_mac.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_trng_driver.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_driver_common.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_driver_init.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_psa_trng.c + ${SILABS_GSDK_DIR}/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER.h + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c + ${SILABS_GSDK_DIR}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h + autogen/mbedtls_config_autogen.h + autogen/psa_crypto_config_autogen.h + autogen/RTE_Components.h + autogen/sl_board_default_init.c + autogen/sl_component_catalog.h + autogen/sl_device_init_clocks.c + autogen/sl_event_handler.c + autogen/sl_event_handler.h + autogen/sl_mbedtls_config_transform_autogen.h + autogen/sl_ot_init.c + autogen/sl_ot_init.h + autogen/sl_uartdrv_init.c + autogen/sl_uartdrv_instances.h + config/dmadrv_config.h + config/emlib_core_debug_config.h + config/mbedtls_config.h + config/nvm3_default_config.h + config/psa_crypto_config.h + config/SEGGER_RTT_Conf.h + config/sl_board_control_config.h + config/sl_debug_swo_config.h + config/sl_device_init_dcdc_config.h + config/sl_device_init_emu_config.h + config/sl_device_init_hfxo_config.h + config/sl_device_init_lfxo_config.h + config/sl_memory_config.h + config/sl_mx25_flash_shutdown_usart_config.h + config/sl_rail_util_pa_config.h + config/sl_rail_util_pti_config.h + config/sl_rail_util_rssi_config.h + config/sl_sleeptimer_config.h + config/sl_uartdrv_usart_vcom_config.h + config/uartdrv_config.h +) + +target_sources(openthread-efr32-soc-sdk PRIVATE ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S) +set_property(SOURCE ${SILABS_GSDK_DIR}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S PROPERTY LANGUAGE C) + +# ============================================================================== +# Compile Options +# ============================================================================== +target_compile_options(openthread-efr32-soc-sdk PRIVATE + -Wno-unused-parameter + -Wno-missing-field-initializers + + # GNU C flags + $<$: + "SHELL:-mcpu=cortex-m4" + "SHELL:-mthumb" + "SHELL:-mfpu=fpv4-sp-d16" + "SHELL:-mfloat-abi=softfp" + "SHELL:-std=c99" + "SHELL:-Wall" + "SHELL:-Wextra" + "SHELL:-Os" + "SHELL:-fdata-sections" + "SHELL:-ffunction-sections" + "SHELL:-fomit-frame-pointer" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:-imacros sl_gcc_preinclude.h" + "SHELL:--specs=nano.specs" + "SHELL:-g" + > +) + +# ============================================================================== +# Linking +# ============================================================================== +target_link_libraries(openthread-efr32-soc-sdk + PUBLIC + openthread-efr32-soc-mbedtls + PRIVATE + -lstdc++ + -lgcc + -lc + -lm + -lnosys + "${SILABS_GSDK_DIR}/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a" + "${SILABS_GSDK_DIR}/protocol/openthread/libs/libsl_openthread_efr32mg1x_gcc.a" + "${SILABS_GSDK_DIR}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg12_gcc_release.a" + openthread-efr32-soc-config + ot-config +) + +# ============================================================================== +# Linker Flags +# ============================================================================== +target_link_options(openthread-efr32-soc-sdk PRIVATE + -mcpu=cortex-m4 + -mthumb + -mfpu=fpv4-sp-d16 + -mfloat-abi=softfp + -Wl,--gc-sections +)