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RTL8100.cpp
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RTL8100.cpp
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/*
* RTL8100.cpp - Hardware methods for RealTek RTL8100 family chips
* RealtekR1000SL
*
* Created by Chuck Fry on 10/8/09.
* Copyright 2009 Chuck Fry. All rights reserved.
*
* This software incorporates code from Realtek's open source Linux drivers
* and the open source Mac OS X project RealtekR1000 by Dmitri Arekhta,
* as modified by PSYSTAR Corporation.
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
* copyright PSYSTAR Corporation, 2008
* 2006 (c) Dmitri Arekhta ([email protected])
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "RealtekR1000SL.h"
#include "impl_defs.h"
/*** Static Initialization ***/
const u16 RealtekR1000::rtl8101_intr_mask =
SYSErr | LinkChg | RxDescUnavail | TxErr | TxOK | RxErr | RxOK;
const u16 RealtekR1000::rtl8101_napi_event =
RxOK | RxDescUnavail | RxFIFOOver | TxOK | TxErr;
const uint32_t RealtekR1000::rtl8101_rx_config =
(Reserved2_data << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
//rtl8101_hw_start
void RealtekR1000::RTL8100HwStart()
{
RTL8100NicReset();
// TODO rtl8101_set_rxbufsize(tp, dev);
WriteMMIO8(Cfg9346, Cfg9346_Unlock);
/* Set DMA burst size and Interframe Gap Time */
WriteMMIO32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
// Chip specific initializations
u16 cplus_cmd = 0;
if ((mcfg >= MCFG_8102E_1 && mcfg <= MCFG_8103E_3) || mcfg == MCFG_8401_1) {
RTL8100HwStart1Gen();
} else if (mcfg == MCFG_8105E_1) {
RTL8105EHwStart1();
cplus_cmd &= 0x2063;
} else if (mcfg >= MCFG_8105E_2 && mcfg <= MCFG_8105E_4) {
RTL8105EHwStart();
cplus_cmd &= 0x2063;
} else if (mcfg == MCFG_8402_1) {
RTL8402HwStart();
} else if ((mcfg >= MCFG_8106E_1) && (mcfg <= MCFG_8106EUS)) {
RTL8106HwStart();
}
WriteMMIO8(ETThReg, ETTh);
// I'm a little dubious that this needs to be done
WriteMMIO16(CPlusCmd, cplus_cmd);
/* Undocumented corner */
WriteMMIO16(IntrMitigate, 0x0000);
WriteMMIO32(TxDescStartAddr, static_cast<UInt32>(txdesc_phy_dma_addr));
#if defined(__LP64__)
WriteMMIO32(TxDescStartAddr + 4, static_cast<UInt32>(txdesc_phy_dma_addr >> 32));
#endif
WriteMMIO32(RxDescStartAddr, static_cast<UInt32>(rxdesc_phy_dma_addr));
#if defined(__LP64__)
WriteMMIO32(RxDescStartAddr + 4, static_cast<UInt32>(rxdesc_phy_dma_addr >> 32));
#endif
// Set Rx Config register
WriteMMIO32(RxConfig,
~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
AcceptMyPhys | AcceptAllPhys) & (rx_config_base |
(ReadMMIO32(RxConfig) & rx_config_mask)));
// Clear interrupt register
WriteMMIO16(IntrStatus, 0xFFFF);
if (mcfg >= MCFG_8101E_1 && mcfg <= MCFG_8101E_3) {
tx_tcp_csum_cmd = TxIPCS | TxTCPCS;
tx_udp_csum_cmd = TxIPCS | TxUDPCS;
tx_ip_csum_cmd = TxIPCS;
} else {
tx_tcp_csum_cmd = TxIPCS_C | TxTCPCS_C;
tx_udp_csum_cmd = TxIPCS_C | TxUDPCS_C;
tx_ip_csum_cmd = TxIPCS_C;
}
// Enable all known interrupts
WriteMMIO16(IntrMask, rtl8101_intr_mask);
WriteMMIO8(Cfg9346, Cfg9346_Lock);
RTL8100DSM(DSM_MAC_INIT);
u8 options1 = ReadMMIO8(Config3);
u8 options2 = ReadMMIO8(Config5);
if ((options1 & LinkUp) || (options1 & MagicPacket) ||
(options2 & UWF) || (options2 & BWF) || ( options2 & MWF)) {
wol_enabled = WOL_ENABLED;
} else {
wol_enabled = WOL_DISABLED;
}
if (eee_enable == 1) {
RTL8100EnableEEE();
} else {
RTL8100DisableEEE();
}
}
void RealtekR1000::RTL8100HwStart1Gen()
{
u8 link_control, device_control;
if (mcfg == MCFG_8102E_1) {
/* set PCI configuration space ossfet 0x70F to 0x17 */
u32 csi_tmp = ReadCSI32(0x70C);
WriteCSI32(0x70C, csi_tmp | 0x17000000);
}
link_control = pciDev->configRead8(0x81);
if (link_control == 1) {
pciDev->configWrite8(0x81, 0);
WriteMMIO8(DBG_reg, 0x98);
WriteMMIO8(Config2, ReadMMIO8(Config2) | BIT_7);
WriteMMIO8(Config4, ReadMMIO8(Config4) | BIT_2);
if (mcfg == MCFG_8103E_3) {
WriteMMIO8(0xF4, ReadMMIO8(0xF4) | BIT_3);
WriteMMIO8(0xF5, ReadMMIO8(0xF5) | BIT_2);
}
pciDev->configWrite8(0x81, 1);
if (mcfg == MCFG_8103E_3) {
if (ReadEPHY16(0x10) == 0x0008) {
WriteEPHY16(0x10, 0x000C);
}
}
}
if (mcfg == MCFG_8103E_3) {
link_control = pciDev->configRead8(0x80);
if (link_control & 3) {
WriteEPHY16(0x02, 0x011F);
}
}
// Set PCI COnfig offset to 0x70 to 0x50
/* Increase Tx performance */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
if (mcfg == MCFG_8102E_1 || mcfg == MCFG_8102E_2) {
WriteMMIO8(Config1, 0x0F);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
} else if (mcfg == MCFG_8103E_1 || mcfg == MCFG_8103E_2 ||
mcfg == MCFG_8401_1) {
WriteMMIO8(0xF4, 0x01);
} else if (mcfg == MCFG_8103E_3) {
WriteMMIO8(0xF4, ReadMMIO8(0xF4) | BIT_0);
}
// In the original source, there's a lot of bit shifts to get 0xDF9{8,C}
if (mcfg == MCFG_8102E_1 || mcfg == MCFG_8102E_2 ||
mcfg == MCFG_8103E_1) {
WriteMMIO16(CPlusCmd, ReadMMIO8(CPlusCmd) & ~0xDF98);
} else if(mcfg == MCFG_8103E_2 || mcfg == MCFG_8103E_3 ||
mcfg == MCFG_8401_1) {
WriteMMIO16(CPlusCmd, ReadMMIO8(CPlusCmd) & ~0xDF9C);
}
if (mcfg == MCFG_8103E_1 || mcfg == MCFG_8103E_2 || mcfg == MCFG_8103E_3 ||
mcfg == MCFG_8401_1) {
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
}
//E-PHY config
switch (mcfg){
case MCFG_8102E_1:
WriteEPHY16(0x03, 0xC2F9);
break;
case MCFG_8102E_2:
WriteEPHY16(0x01, 0x6FE5);
WriteEPHY16(0x03, 0xD7D9);
break;
case MCFG_8103E_1:
WriteEPHY16(0x06, 0xAF35);
break;
case MCFG_8103E_2:
WriteMMIO8(0xF5, ReadMMIO8(0xF5) | BIT_2);
WriteEPHY16(0x19, 0xEC90);
WriteEPHY16(0x01, 0x6FE5);
WriteEPHY16(0x03, 0x05D9);
WriteEPHY16(0x06, 0xAF35);
break;
case MCFG_8103E_3:
WriteEPHY16(0x01, 0x6FE5);
WriteEPHY16(0x03, 0x05D9);
WriteEPHY16(0x06, 0xAF35);
WriteEPHY16(0x19, 0xECFA);
break;
case MCFG_8401_1:
WriteEPHY16(0x06, 0xAF25);
WriteEPHY16(0x07, 0x8E68);
break;
default:
break;
}
}
void RealtekR1000::RTL8105EHwStart1()
{
/* Set PCI configuration space offset 0x70F to 0x27 */
u32 csi_tmp = ReadCSI32(0x70C) & 0x00FFFFFF;
WriteCSI32(0x70C, csi_tmp | 0x27000000);
WriteMMIO8(ETThReg, 0x0C);
/* Set CPI config offset 0x79 to 0x50 */
pciDev->configWrite8(0x79, 0x50);
/* TODO Enable tx checksum offload */
WriteMMIO8(0xF3, ReadMMIO8(0xF3) | BIT_5);
WriteMMIO8(0xF3, ReadMMIO8(0xF3) & ~BIT_5);
WriteMMIO8(0xD0, ReadMMIO8(0xD0) | 0xC0);
// WriteMMIO8(0xD0, ReadMMIO8(0xD0) | 0xC6);
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_2 | BIT_1);
WriteMMIO8(Config5, (ReadMMIO8(Config5) & ~0x08) | BIT_0);
WriteMMIO8(Config2, ReadMMIO8(Config2) | BIT_7);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
/* Set EPHY registers */
u16 data16;
data16 = ReadEPHY16(0x00) & ~ 0x0200;
data16 |= 0x100;
WriteEPHY16(0x00, data16);
data16 = ReadEPHY16(0x00);
data16 |= 0x0004;
WriteEPHY16(0x00, data16);
data16 = ReadEPHY16(0x06) & ~0x0002;
data16 |= 0x0001;
WriteEPHY16(0x06, data16);
data16 = ReadEPHY16(0x06);
data16 |= 0x0030;
WriteEPHY16(0x06, data16);
data16 = ReadEPHY16(0x07);
data16 |= 0x2000;
WriteEPHY16(0x07, data16);
data16 = ReadEPHY16(0x00);
data16 |= 0x0020;
WriteEPHY16(0x00, data16);
data16 = ReadEPHY16(0x03) & ~0x5800;
data16 |= 0x2000;
WriteEPHY16(0x03, data16);
data16 = ReadEPHY16(0x03);
data16 |= 0x0001;
WriteEPHY16(0x03, data16);
data16 = ReadEPHY16(0x01) & ~0x0800;
data16 |= 0x1000;
WriteEPHY16(0x01, data16);
data16 = ReadEPHY16(0x07);
data16 |= 0x4000;
WriteEPHY16(0x07, data16);
data16 = ReadEPHY16(0x1E);
data16 |= 0x2000;
WriteEPHY16(0x1E, data16);
WriteEPHY16(0x19, 0xFE6C);
data16 = ReadEPHY16(0x0A);
data16 |= 0x0040;
WriteEPHY16(0x0A, data16);
}
void RealtekR1000::RTL8105EHwStart()
{
u8 pci_config;
/* TODO enable chesksum offload */
pci_config = pciDev->configRead8(0x80);
if (pci_config & 0x03)
{
WriteMMIO8(Config5, ReadMMIO8(Config5) | BIT_0);
WriteMMIO8(0xF2, ReadMMIO8(0xF2) | BIT_7);
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_7);
WriteMMIO8(Config2, ReadMMIO8(Config2) | BIT_7);
}
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_5 | BIT_3);
WriteMMIO8(0xF2, ReadMMIO8(0xF2) & ~BIT_0);
WriteMMIO8(0xD3, ReadMMIO8(0xD3) | BIT_3 | BIT_2);
WriteMMIO8(0xD0, ReadMMIO8(0xD0) | BIT_6);
WriteMMIO16(0xE0, ReadMMIO16(0xE0) & ~0xDF9C);
u16 data16;
data16 = ReadEPHY16(0x07);
data16 |= 0x4000;
WriteEPHY16(0x07, data16);
data16 = ReadEPHY16(0x19);
data16 |= 0x0200;
WriteEPHY16(0x19, data16);
data16 = ReadEPHY16(0x19);
data16 |= 0x0020;
WriteEPHY16(0x19, data16);
data16 = ReadEPHY16(0x1E);
data16 |= 0x2000;
WriteEPHY16(0x1E, data16);
data16 = ReadEPHY16(0x03);
data16 |= 0x0001;
WriteEPHY16(0x03, data16);
data16 = ReadEPHY16(0x19);
data16 |= 0x0100;
WriteEPHY16(0x19, data16);
data16 = ReadEPHY16(0x19);
data16 |= 0x0004;
WriteEPHY16(0x19, data16);
data16 = ReadEPHY16(0x0A);
data16 |= 0x0020;
WriteEPHY16(0x0A, data16);
if (mcfg == MCFG_8105E_2) {
WriteMMIO8(Config5, ReadMMIO8(Config5) & ~BIT_0);
} else if (mcfg == MCFG_8105E_3 || mcfg == MCFG_8105E_4) {
data16 = ReadEPHY16(0x1E);
data16 |= 0x8000;
WriteEPHY16(0x1E, data16);
}
if (mcfg == MCFG_8105E_4) {
if ((ReadMMIO8(0x8C) & BIT_28) && !(ReadMMIO8(0xEF) & BIT_2)) {
WriteGMII16(0x1F, 0x0005);
data16 = ReadGMII16(0x1A);
data16 &= ~(BIT_8 | BIT_0);
WriteGMII16(0x0A, data16);
WriteGMII16(0x1F, 0x0000);
} else if (ReadMMIO8(0xEF) & BIT_2) {
WriteGMII16(0x1F, 0x0001);
data16 = ReadGMII16(0x1B) | BIT_2;
WriteGMII16(0x1B, data16);
WriteGMII16(0x1F, 0x0000);
}
}
}
void RealtekR1000::RTL8402HwStart()
{
u8 device_control;
u32 csi_tmp = ReadCSI32(0x70C) & 0x00FFFFFF;
WriteCSI32(0x70C, csi_tmp | 0x17000000);
/* Set PCI config space offset 0x70 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
WriteERI(0xC8, 4, 0x00000002, ERIAR_ExGMAC);
WriteERI(0xE8, 4, 0x00000006, ERIAR_ExGMAC);
WriteMMIO32(TxConfig, ReadMMIO32(TxConfig) | BIT_7);
WriteMMIO8(0xD3, ReadMMIO8(0xD3) & ~BIT_7);
csi_tmp = ReadERI(0xDC, 1, ERIAR_ExGMAC);
csi_tmp &= ~BIT_0;
WriteERI(0xDC, 1, csi_tmp, ERIAR_ExGMAC);
csi_tmp |= BIT_0;
WriteERI(0xDC, 1, csi_tmp, ERIAR_ExGMAC);
WriteEPHY16(0x19, 0xFF64);
WriteMMIO8(Config5, ReadMMIO8(Config5) | BIT_0);
WriteMMIO8(Config2, ReadMMIO8(Config2) | BIT_7);
WriteERI(0xC0, 2, 0x00000000, ERIAR_ExGMAC);
WriteERI(0xB8, 2, 0x00000000, ERIAR_ExGMAC);
WriteERI(0xD5, 1, 0x0000000E, ERIAR_ExGMAC);
}
void RealtekR1000::RTL8106HwStart()
{
WriteMMIO8(Config5, ReadMMIO8(Config5) & ~BIT_0);
WriteMMIO8(Config2, ReadMMIO8(Config2) & ~BIT_7);
WriteMMIO8(0xF1, ReadMMIO8(0xF1) & ~BIT_7);
if (mcfg == MCFG_8106E_1 || mcfg == MCFG_8106E_2) {
u8 pci_config;
cp_cmd &= 0x2063;
/* tx checksum offload enable */
features |= NETIF_F_IP_CSUM;
pci_config = pciDev->configRead8(0x80);
if (pci_config & 0x03) {
WriteMMIO8(Config5, ReadMMIO8(Config5) | BIT_0);
WriteMMIO8(0xF2, ReadMMIO8(0xF2) | BIT_7);
if (aspm)
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_7);
WriteMMIO8(Config2, ReadMMIO8(Config2) | BIT_7);
}
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_5 | BIT_3);
WriteMMIO8(0xF2, ReadMMIO8(0xF2) & ~BIT_0);
WriteMMIO8(0xD3, ReadMMIO8(0xD3) | BIT_3 | BIT_2);
WriteMMIO8(0xD0, ReadMMIO8(0xD0) & ~BIT_6);
WriteMMIO16(0xE0, ReadMMIO16(0xE0) & ~0xDF9C);
} else if (mcfg == MCFG_8106EUS) {
u8 data8;
u8 device_control;
u32 csi_tmp;
// set_offset70F(tp, 0x27);
// set_offset79(tp, 0x50);
/*set PCI configuration space offset 0x70F to 0x37*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70C) & 0x00ffffff;
WriteCSI32(0x70C, csi_tmp | 0x17000000);
/* Set PCI configuration space offset 0x79 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
WriteERI(0xC8, 4, 0x00080002, ERIAR_ExGMAC);
WriteERI(0xCC, 1, 0x38, ERIAR_ExGMAC);
WriteERI(0xD0, 1, 0x48, ERIAR_ExGMAC);
WriteERI(0xE8, 4, 0x00100006, ERIAR_ExGMAC);
WriteMMIO32(TxConfig, ReadMMIO32(TxConfig) | BIT_7);
csi_tmp = ReadERI(0xDC, 1, ERIAR_ExGMAC);
csi_tmp &= ~BIT_0;
WriteERI(0xDC, 1, csi_tmp, ERIAR_ExGMAC);
csi_tmp |= BIT_0;
WriteERI(0xDC, 1, csi_tmp, ERIAR_ExGMAC);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
cp_cmd = ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup |
Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable |
Macdbgo_sel);
WriteMMIO8(0x1B, ReadMMIO8(0x1B) & ~0x07);
WriteMMIO8(TDFNR, 0x4);
if (aspm)
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_7);
/* tx checksum offload enable */
features |= NETIF_F_IP_CSUM;
WriteMMIO8(0xD0, ReadMMIO8(0xD0) | BIT_6);
WriteMMIO8(0xF2, ReadMMIO8(0xF2) | BIT_6);
WriteMMIO8(0xD0, ReadMMIO8(0xD0) | BIT_7);
WriteERI(0xC0, 2, 0x0000, ERIAR_ExGMAC);
WriteERI(0xB8, 4, 0x00000000, ERIAR_ExGMAC);
WriteERI(0x5F0, 2, 0x4f87, ERIAR_ExGMAC);
csi_tmp = ReadERI(0xD4, 4, ERIAR_ExGMAC);
csi_tmp |= ( BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 );
WriteERI(0xD4, 4, csi_tmp, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x1B0, 4, ERIAR_ExGMAC);
csi_tmp &= ~BIT_12;
WriteERI(0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x2FC, 1, ERIAR_ExGMAC);
csi_tmp &= ~(BIT_0 | BIT_1 | BIT_2);
csi_tmp |= BIT_0;
WriteERI(0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x1D0, 1, ERIAR_ExGMAC);
csi_tmp |= BIT_1;
WriteERI(0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
if (aspm) {
csi_tmp = ReadERI(0x3F2, 2, ERIAR_ExGMAC);
csi_tmp &= ~( BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 | BIT_13 | BIT_14 | BIT_15 );
csi_tmp |= ( BIT_9 | BIT_10 | BIT_13 | BIT_14 | BIT_15 );
WriteERI(0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x3F5, 1, ERIAR_ExGMAC);
csi_tmp |= BIT_6 | BIT_7;
WriteERI(0x3F5, 1, csi_tmp, ERIAR_ExGMAC);
mac_ocp_write(0xE02C, 0x1880);
mac_ocp_write(0xE02E, 0x4880);
WriteERI(0x2E8, 2, 0x9003, ERIAR_ExGMAC);
WriteERI(0x2EA, 2, 0x9003, ERIAR_ExGMAC);
WriteERI(0x2EC, 2, 0x9003, ERIAR_ExGMAC);
WriteERI(0x2E2, 2, 0x883C, ERIAR_ExGMAC);
WriteERI(0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
WriteERI(0x2E6, 2, 0x9003, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x3FA, 2, ERIAR_ExGMAC);
csi_tmp |= BIT_14;
WriteERI(0x3FA, 2, csi_tmp, ERIAR_ExGMAC);
csi_tmp = ReadERI(0x3F2, 2, ERIAR_ExGMAC);
csi_tmp &= ~(BIT_0 | BIT_1);
csi_tmp |= BIT_0;
data8 = pciDev->configRead8(0x99);
if (!(data8 & (BIT_5 | BIT_6)))
csi_tmp &= ~(BIT_1);
if (!(data8 & BIT_2))
csi_tmp &= ~(BIT_0 );
WriteERI(0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
data8 = pciDev->configRead8(0x180);
if (data8 & (BIT_0|BIT_1)) {
csi_tmp = ReadERI(0x1E2, 1, ERIAR_ExGMAC);
csi_tmp |= BIT_2;
WriteERI(0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
} else {
csi_tmp = ReadERI(0x1E2, 1, ERIAR_ExGMAC);
csi_tmp &= ~BIT_2;
WriteERI(0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
}
}
}
}
void RealtekR1000::RTL8100HwPhyConfig()
{
switch (mcfg)
{
case MCFG_8102E_1:
case MCFG_8102E_2:
case MCFG_8103E_1:
RTL8102EHwPhyConfig();
break;
case MCFG_8401_1:
RTL8401PhyHwConfig();
break;
case MCFG_8105E_1:
RTL8105E1HwPhyConfig();
break;
case MCFG_8105E_2:
case MCFG_8105E_3:
case MCFG_8105E_4:
RTL8105EHwPhyConfig();
break;
case MCFG_8402_1:
RTL8402HwPhyConfig();
break;
case MCFG_8106E_1:
case MCFG_8106E_2:
case MCFG_8106EUS:
RTL8106EHwPhyConfig();
default:
break;
}
}
void RealtekR1000::RTL8102EHwPhyConfig()
{
WriteGMII16(0x1F, 0x0000);
WriteGMII16(0x11, ReadGMII16(0x11) | 0x1000);
WriteGMII16(0x19, ReadGMII16(0x19) | 0x2000);
WriteGMII16(0x10, ReadGMII16(0x10) | 0x8000);
WriteGMII16(0x1F, 0x0003);
WriteGMII16(0x08, 0x441D);
if (mcfg != MCFG_8103E_1)
{
WriteGMII16(0x01, 0x9100);
}
WriteGMII16(0x1F, 0x0000);
}
void RealtekR1000::RTL8401PhyHwConfig()
{
WriteGMII16(0x1F, 0x0000);
WriteGMII16(0x11, ReadGMII16(0x11) | BIT_12);
WriteGMII16(0x1F, 0x0002);
WriteGMII16(0x0F, ReadGMII16(0x0F) | BIT_0 | BIT_1);
WriteGMII16(0x1F, 0x0000);
RTL8100WritePhyIO(0x0E, 0x0068);
RTL8100WritePhyIO(0x0E, 0x0069);
RTL8100WritePhyIO(0x0E, 0x006A);
RTL8100WritePhyIO(0x0E, 0x006B);
RTL8100WritePhyIO(0x0E, 0x006C);
}
void RealtekR1000::RTL8105E1HwPhyConfig()
{
u32 gphy_val;
WriteMMIO8(0xF3, ReadMMIO8(0xF3) | BIT_2);
WriteGMII16(0x1f, 0x0000);
WriteGMII16(0x00, 0x1800);
WriteGMII16(0x1f, 0x0007);
WriteGMII16(0x1e, 0x0023);
WriteGMII16(0x17, 0x0117);
WriteGMII16(0x1f, 0x0007);
WriteGMII16(0x1E, 0x002C);
WriteGMII16(0x1B, 0x5000);
WriteGMII16(0x1f, 0x0000);
WriteGMII16(0x16, 0x4104);
for (int i = 0; i < 200; i++) {
IODelay(100);
gphy_val = ReadGMII16(0x1E);
gphy_val &= 0x03FF;
if (gphy_val==0x000C)
break;
}
WriteGMII16(0x1f, 0x0005);
for (int i = 0; i < 200; i++) {
IODelay(100);
gphy_val = ReadGMII16(0x07);
if ((gphy_val & BIT_5)==0)
break;
}
gphy_val = ReadGMII16(0x07);
if (gphy_val & BIT_5) {
WriteGMII16(0x1f, 0x0007);
WriteGMII16(0x1e, 0x00a1);
WriteGMII16(0x17, 0x1000);
WriteGMII16(0x17, 0x0000);
WriteGMII16(0x17, 0x2000);
WriteGMII16(0x1e, 0x002f);
WriteGMII16(0x18, 0x9bfb);
WriteGMII16(0x1f, 0x0005);
WriteGMII16(0x07, 0x0000);
WriteGMII16(0x1f, 0x0000);
}
WriteGMII16(0x1f, 0x0005);
WriteGMII16(0x05, 0xfff6);
WriteGMII16(0x06, 0x0080);
gphy_val = ReadGMII16(0x00);
gphy_val &= ~(BIT_7);
WriteGMII16(0x00, gphy_val);
WriteGMII16(0x1f, 0x0002);
gphy_val = ReadGMII16(0x08);
gphy_val &= ~(BIT_7);
WriteGMII16(0x08, gphy_val);
WriteGMII16(0x1f, 0x0000);
WriteGMII16(0x1f, 0x0007);
WriteGMII16(0x1e, 0x0023);
WriteGMII16(0x16, 0x0306);
WriteGMII16(0x16, 0x0307);
WriteGMII16(0x15, 0x000e);
WriteGMII16(0x19, 0x000a);
WriteGMII16(0x15, 0x0010);
WriteGMII16(0x19, 0x0008);
WriteGMII16(0x15, 0x0018);
WriteGMII16(0x19, 0x4801);
WriteGMII16(0x15, 0x0019);
WriteGMII16(0x19, 0x6801);
WriteGMII16(0x15, 0x001a);
WriteGMII16(0x19, 0x66a1);
WriteGMII16(0x15, 0x001f);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0020);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0021);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0022);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0023);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0024);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0025);
WriteGMII16(0x19, 0x64a1);
WriteGMII16(0x15, 0x0026);
WriteGMII16(0x19, 0x40ea);
WriteGMII16(0x15, 0x0027);
WriteGMII16(0x19, 0x4503);
WriteGMII16(0x15, 0x0028);
WriteGMII16(0x19, 0x9f00);
WriteGMII16(0x15, 0x0029);
WriteGMII16(0x19, 0xa631);
WriteGMII16(0x15, 0x002a);
WriteGMII16(0x19, 0x9717);
WriteGMII16(0x15, 0x002b);
WriteGMII16(0x19, 0x302c);
WriteGMII16(0x15, 0x002c);
WriteGMII16(0x19, 0x4802);
WriteGMII16(0x15, 0x002d);
WriteGMII16(0x19, 0x58da);
WriteGMII16(0x15, 0x002e);
WriteGMII16(0x19, 0x400d);
WriteGMII16(0x15, 0x002f);
WriteGMII16(0x19, 0x4488);
WriteGMII16(0x15, 0x0030);
WriteGMII16(0x19, 0x9e00);
WriteGMII16(0x15, 0x0031);
WriteGMII16(0x19, 0x63c8);
WriteGMII16(0x15, 0x0032);
WriteGMII16(0x19, 0x6481);
WriteGMII16(0x15, 0x0033);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0034);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0035);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0036);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0037);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0038);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0039);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x003a);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x003b);
WriteGMII16(0x19, 0x63e8);
WriteGMII16(0x15, 0x003c);
WriteGMII16(0x19, 0x7d00);
WriteGMII16(0x15, 0x003d);
WriteGMII16(0x19, 0x59d4);
WriteGMII16(0x15, 0x003e);
WriteGMII16(0x19, 0x63f8);
WriteGMII16(0x15, 0x0040);
WriteGMII16(0x19, 0x64a1);
WriteGMII16(0x15, 0x0041);
WriteGMII16(0x19, 0x30de);
WriteGMII16(0x15, 0x0044);
WriteGMII16(0x19, 0x480f);
WriteGMII16(0x15, 0x0045);
WriteGMII16(0x19, 0x6800);
WriteGMII16(0x15, 0x0046);
WriteGMII16(0x19, 0x6680);
WriteGMII16(0x15, 0x0047);
WriteGMII16(0x19, 0x7c10);
WriteGMII16(0x15, 0x0048);
WriteGMII16(0x19, 0x63c8);
WriteGMII16(0x15, 0x0049);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004a);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004b);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004c);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004d);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004e);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x004f);
WriteGMII16(0x19, 0x40ea);
WriteGMII16(0x15, 0x0050);
WriteGMII16(0x19, 0x4503);
WriteGMII16(0x15, 0x0051);
WriteGMII16(0x19, 0x58ca);
WriteGMII16(0x15, 0x0052);
WriteGMII16(0x19, 0x63c8);
WriteGMII16(0x15, 0x0053);
WriteGMII16(0x19, 0x63d8);
WriteGMII16(0x15, 0x0054);
WriteGMII16(0x19, 0x66a0);
WriteGMII16(0x15, 0x0055);
WriteGMII16(0x19, 0x9f00);
WriteGMII16(0x15, 0x0056);
WriteGMII16(0x19, 0x3000);
WriteGMII16(0x15, 0x006E);
WriteGMII16(0x19, 0x9afa);
WriteGMII16(0x15, 0x00a1);
WriteGMII16(0x19, 0x3044);
WriteGMII16(0x15, 0x00ab);
WriteGMII16(0x19, 0x5820);
WriteGMII16(0x15, 0x00ac);
WriteGMII16(0x19, 0x5e04);
WriteGMII16(0x15, 0x00ad);
WriteGMII16(0x19, 0xb60c);
WriteGMII16(0x15, 0x00af);
WriteGMII16(0x19, 0x000a);
WriteGMII16(0x15, 0x00b2);
WriteGMII16(0x19, 0x30b9);
WriteGMII16(0x15, 0x00b9);
WriteGMII16(0x19, 0x4408);
WriteGMII16(0x15, 0x00ba);
WriteGMII16(0x19, 0x480b);
WriteGMII16(0x15, 0x00bb);
WriteGMII16(0x19, 0x5e00);
WriteGMII16(0x15, 0x00bc);
WriteGMII16(0x19, 0x405f);
WriteGMII16(0x15, 0x00bd);
WriteGMII16(0x19, 0x4448);
WriteGMII16(0x15, 0x00be);
WriteGMII16(0x19, 0x4020);
WriteGMII16(0x15, 0x00bf);
WriteGMII16(0x19, 0x4468);
WriteGMII16(0x15, 0x00c0);
WriteGMII16(0x19, 0x9c02);
WriteGMII16(0x15, 0x00c1);
WriteGMII16(0x19, 0x58a0);
WriteGMII16(0x15, 0x00c2);
WriteGMII16(0x19, 0xb605);
WriteGMII16(0x15, 0x00c3);
WriteGMII16(0x19, 0xc0d3);
WriteGMII16(0x15, 0x00c4);
WriteGMII16(0x19, 0x00e6);
WriteGMII16(0x15, 0x00c5);
WriteGMII16(0x19, 0xdaec);
WriteGMII16(0x15, 0x00c6);
WriteGMII16(0x19, 0x00fa);
WriteGMII16(0x15, 0x00c7);
WriteGMII16(0x19, 0x9df9);
WriteGMII16(0x15, 0x00c8);
WriteGMII16(0x19, 0x307a);
WriteGMII16(0x15, 0x0112);
WriteGMII16(0x19, 0x6421);
WriteGMII16(0x15, 0x0113);
WriteGMII16(0x19, 0x7c08);
WriteGMII16(0x15, 0x0114);
WriteGMII16(0x19, 0x63f0);
WriteGMII16(0x15, 0x0115);
WriteGMII16(0x19, 0x4003);
WriteGMII16(0x15, 0x0116);
WriteGMII16(0x19, 0x4418);
WriteGMII16(0x15, 0x0117);
WriteGMII16(0x19, 0x9b00);
WriteGMII16(0x15, 0x0118);
WriteGMII16(0x19, 0x6461);
WriteGMII16(0x15, 0x0119);
WriteGMII16(0x19, 0x64e1);
WriteGMII16(0x15, 0x011a);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x0150);
WriteGMII16(0x19, 0x6461);
WriteGMII16(0x15, 0x0151);
WriteGMII16(0x19, 0x4003);
WriteGMII16(0x15, 0x0152);
WriteGMII16(0x19, 0x4540);
WriteGMII16(0x15, 0x0153);
WriteGMII16(0x19, 0x9f00);
WriteGMII16(0x15, 0x0155);
WriteGMII16(0x19, 0x6421);
WriteGMII16(0x15, 0x0156);
WriteGMII16(0x19, 0x64a1);
WriteGMII16(0x15, 0x021e);
WriteGMII16(0x19, 0x5410);
WriteGMII16(0x15, 0x0225);
WriteGMII16(0x19, 0x5400);
WriteGMII16(0x15, 0x023D);
WriteGMII16(0x19, 0x4050);
WriteGMII16(0x15, 0x0295);
WriteGMII16(0x19, 0x6c08);
WriteGMII16(0x15, 0x02bd);
WriteGMII16(0x19, 0xa523);
WriteGMII16(0x15, 0x02be);
WriteGMII16(0x19, 0x32ca);
WriteGMII16(0x15, 0x02ca);
WriteGMII16(0x19, 0x48b3);
WriteGMII16(0x15, 0x02cb);
WriteGMII16(0x19, 0x4020);
WriteGMII16(0x15, 0x02cc);
WriteGMII16(0x19, 0x4823);
WriteGMII16(0x15, 0x02cd);
WriteGMII16(0x19, 0x4510);
WriteGMII16(0x15, 0x02ce);
WriteGMII16(0x19, 0xb63a);
WriteGMII16(0x15, 0x02cf);
WriteGMII16(0x19, 0x7dc8);
WriteGMII16(0x15, 0x02d6);
WriteGMII16(0x19, 0x9bf8);
WriteGMII16(0x15, 0x02d8);
WriteGMII16(0x19, 0x85f6);
WriteGMII16(0x15, 0x02d9);
WriteGMII16(0x19, 0x32e0);
WriteGMII16(0x15, 0x02e0);
WriteGMII16(0x19, 0x4834);
WriteGMII16(0x15, 0x02e1);
WriteGMII16(0x19, 0x6c08);
WriteGMII16(0x15, 0x02e2);
WriteGMII16(0x19, 0x4020);
WriteGMII16(0x15, 0x02e3);
WriteGMII16(0x19, 0x4824);
WriteGMII16(0x15, 0x02e4);
WriteGMII16(0x19, 0x4520);
WriteGMII16(0x15, 0x02e5);
WriteGMII16(0x19, 0x4008);
WriteGMII16(0x15, 0x02e6);
WriteGMII16(0x19, 0x4560);
WriteGMII16(0x15, 0x02e7);
WriteGMII16(0x19, 0x9d04);
WriteGMII16(0x15, 0x02e8);
WriteGMII16(0x19, 0x48c4);
WriteGMII16(0x15, 0x02e9);
WriteGMII16(0x19, 0x0000);
WriteGMII16(0x15, 0x02ea);
WriteGMII16(0x19, 0x4844);
WriteGMII16(0x15, 0x02eb);
WriteGMII16(0x19, 0x7dc8);
WriteGMII16(0x15, 0x02f0);
WriteGMII16(0x19, 0x9cf7);
WriteGMII16(0x15, 0x02f1);
WriteGMII16(0x19, 0xdf94);
WriteGMII16(0x15, 0x02f2);
WriteGMII16(0x19, 0x0002);
WriteGMII16(0x15, 0x02f3);
WriteGMII16(0x19, 0x6810);
WriteGMII16(0x15, 0x02f4);
WriteGMII16(0x19, 0xb614);
WriteGMII16(0x15, 0x02f5);
WriteGMII16(0x19, 0xc42b);
WriteGMII16(0x15, 0x02f6);
WriteGMII16(0x19, 0x00d4);
WriteGMII16(0x15, 0x02f7);
WriteGMII16(0x19, 0xc455);
WriteGMII16(0x15, 0x02f8);
WriteGMII16(0x19, 0x0093);
WriteGMII16(0x15, 0x02f9);
WriteGMII16(0x19, 0x92ee);
WriteGMII16(0x15, 0x02fa);
WriteGMII16(0x19, 0xefed);
WriteGMII16(0x15, 0x02fb);
WriteGMII16(0x19, 0x3312);
WriteGMII16(0x15, 0x0312);
WriteGMII16(0x19, 0x49b5);
WriteGMII16(0x15, 0x0313);
WriteGMII16(0x19, 0x7d00);
WriteGMII16(0x15, 0x0314);
WriteGMII16(0x19, 0x4d00);
WriteGMII16(0x15, 0x0315);
WriteGMII16(0x19, 0x6810);
WriteGMII16(0x15, 0x031e);
WriteGMII16(0x19, 0x404f);
WriteGMII16(0x15, 0x031f);
WriteGMII16(0x19, 0x44c8);
WriteGMII16(0x15, 0x0320);
WriteGMII16(0x19, 0xd64f);
WriteGMII16(0x15, 0x0321);
WriteGMII16(0x19, 0x00e7);
WriteGMII16(0x15, 0x0322);
WriteGMII16(0x19, 0x7c08);
WriteGMII16(0x15, 0x0323);
WriteGMII16(0x19, 0x8203);
WriteGMII16(0x15, 0x0324);
WriteGMII16(0x19, 0x4d48);
WriteGMII16(0x15, 0x0325);
WriteGMII16(0x19, 0x3327);
WriteGMII16(0x15, 0x0326);
WriteGMII16(0x19, 0x4d40);
WriteGMII16(0x15, 0x0327);
WriteGMII16(0x19, 0xc8d7);
WriteGMII16(0x15, 0x0328);
WriteGMII16(0x19, 0x0003);
WriteGMII16(0x15, 0x0329);
WriteGMII16(0x19, 0x7c20);
WriteGMII16(0x15, 0x032a);
WriteGMII16(0x19, 0x4c20);
WriteGMII16(0x15, 0x032b);
WriteGMII16(0x19, 0xc8ed);
WriteGMII16(0x15, 0x032c);
WriteGMII16(0x19, 0x00f4);
WriteGMII16(0x15, 0x032d);