From ad7d3f5589e52be43e06bfcd02f1b6da01e0fee9 Mon Sep 17 00:00:00 2001 From: Seemebadnekai <51400137+SagarDevAchar@users.noreply.github.com> Date: Wed, 4 Sep 2024 22:27:35 +0530 Subject: [PATCH] Just some more tidying up --- docs/info.md | 1 - info.yaml | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/info.md b/docs/info.md index f6d27f9..d673577 100644 --- a/docs/info.md +++ b/docs/info.md @@ -37,7 +37,6 @@ The `audio_engine` drives the `freq_synth` to produce a ~28 second looping sound ## External hardware - [TinyVGA Pmod](https://github.com/mole99/tiny-vga) connected to OUTPUT terminal (`uo_out`) - - VGA Display connected to the HD15 female connector of the Pmod - [TT Audio Pmod](https://github.com/MichaelBell/tt-audio-pmod) connected to BIDIR terminal (`uio_out`) - Some switches to the INPUT terminal (`ui_in`) diff --git a/info.yaml b/info.yaml index 3e433a9..6f894eb 100644 --- a/info.yaml +++ b/info.yaml @@ -3,7 +3,7 @@ project: title: "DemoSiine" # Project title author: "SagarDevAchar" # Your name discord: "seemebadnekai" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "A Wavy and Rainbowy Submission to the TT08 Demoscene Challenge" # One line description of what your project does + description: "A Wavy and Rainbowy TT08 Demoscene Submission" # One line description of what your project does language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 25000000 # Clock frequency in Hz (or 0 if not applicable)