diff --git a/src/audio_engine.v b/src/audio_engine.v
index 514ecbb..7b5b557 100644
--- a/src/audio_engine.v
+++ b/src/audio_engine.v
@@ -97,7 +97,7 @@ module audio_engine(
     wire [6:0] seq_hp;
     
     reg [17:0] counter;
-    always @(posedge clk or negedge rst_n) begin
+    always @(posedge clk) begin
         if (~rst_n)
           counter <= 18'd0;
         else
@@ -107,7 +107,7 @@ module audio_engine(
     assign synth_clk = counter[10]; 
     assign seq_clk = counter[17];
     
-    always @(posedge seq_clk or negedge rst_n) begin
+    always @(posedge seq_clk) begin
         if (~rst_n) begin
             seq_ctr <= 5'd0;
             seq_time <= 7'd0;
diff --git a/src/freq_synth.v b/src/freq_synth.v
index 62d8f53..75612f2 100644
--- a/src/freq_synth.v
+++ b/src/freq_synth.v
@@ -9,13 +9,13 @@ module freq_synth(
     
     reg audio_reg;
     reg [6:0] hp_ctr;
-    always @ (posedge synth_clk or negedge rst_n) begin
+    always @ (posedge synth_clk) begin
         if (~active | ~rst_n) begin
             audio_reg <= 1'd0;  
             hp_ctr <= 7'd1;
         end else begin
             if (hp_ctr == hp) begin
-                hp_ctr <= 1'd1;
+                hp_ctr <= 7'd1;
                 audio_reg <= ~audio_reg;
             end else
                 hp_ctr <= hp_ctr + 1'd1;