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bb_proc.v
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/*
* Baseband Processor
*
* Must read EPC Gen2 UHF RFID protocols
*
* All of the input and output signals depend on your whole RFID Tag design
* In this case, we use the delayed PIE code to clock the received PIE code. So we should input PIE code (pie_code) and delayed PIE code (clk_dpie)
* we use the clock signal in 200 KHz generated by Multivinrator to generate the clock signal in BLF. (clk_200K)
* rst is generated by POR circuit in our analog front-end circuit to reset the baseband processor. (rst)
* output the backscattered data after processing and computing to control the Backscatter circuit in our analog front-end circuit. (bs_data)
*
* Output signals package_complete and crc_check_pass are not necessary for our RFID Tag design
* it's just for test
*/
`timescale 1us / 1ns
module bb_proc
(
output bs_data,
output package_complete,
output crc_check_pass,
input clk_200K,
input pie_code,
input clk_dpie,
input rst
);
wire clk_crc5;
wire clk_crc16;
wire clk_blf;
wire clk_cp;
wire clk_prng;
wire clk_frm;
wire clk_fm0;
wire clk_mil;
wire clk_mem;
wire rst_n;
wire rst_for_new_package;
wire rst_crc16;
wire start_working;
wire dr;
wire [1:0]m;
wire en_crc5;
wire en_crc16;
wire en_2nd_clk_cp;
wire en_prng_idol;
wire en_prng_act;
wire en_tx;
wire en_if;
wire packet_complete_sync;
wire en_crc16_for_rpy;
wire reply_complete;
wire rd_complete;
wire bs_complete;
wire [7:0]cmd;
wire [51:0]param;
wire [15:0]crc_16;
wire reply_data;
wire trext;
wire [18:0]addr;
wire [15:0]prn;
wire rd_data;
wire pre_p_complete;
wire p_complete;
wire [5:0]A;
wire [15:0]Q;
wire CEN;
// --- Clock/Reset Generator ---
crg crg_1
(
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.clk_blf(clk_blf),
.clk_cp(clk_cp),
.clk_prng(clk_prng),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.clk_if(clk_mem),
.rst_n(rst_n),
.clk_200K(clk_200K),
.clk_dpie(clk_dpie),
.pie_code(pie_code),
.rst(rst),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.start_working(start_working),
.dr(dr),
.m(m),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_tx(en_tx),
.en_if(en_if),
.packet_complete_sync(packet_complete_sync),
.en_crc16_for_rpy(en_crc16_for_rpy),
.reply_complete(reply_complete),
.rd_complete(rd_complete),
.bs_complete(bs_complete)
);
// --- RX (including Frame-Sync Detector, CRC-5, CRC-16 and Command Buffer) ---
rx rx_1
(
.cmd(cmd),
.param(param),
.package_complete(package_complete),
.crc_check_pass(crc_check_pass),
.crc_16(crc_16),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.pie_code(pie_code),
.clk_dpie(clk_dpie),
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.reply_data(reply_data),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
// --- Synchronizer (convential two flip-flop) ---
two_dff_sync two_dff_sync_1
(
.data_out(packet_complete_sync),
.clk_ad(clk_dpie),
.clk_bd(clk_blf),
.rst_n(rst_n),
.data_in(package_complete)
);
// --- Command Processor ---
cmd_proc cmd_proc_1
(
.reply_data(reply_data),
.reply_complete(reply_complete),
.dr(dr),
.m(m),
.trext(trext),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_tx(en_tx),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_crc16_for_rpy(en_crc16_for_rpy),
.en_if(en_if),
.addr(addr),
.clk_cp(clk_cp),
.clk_frm(clk_frm),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.cmd(cmd),
.param(param),
.prn(prn),
.crc_check_pass(crc_check_pass),
.rd_data(rd_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.rd_complete(rd_complete)
);
// --- Pseudo Ramdon Number Generator ---
prng prng_1
(
.prn(prn),
.clk_prng(clk_prng),
.rst_n(rst_n)
);
// --- Memory Interface ---
mem_if mem_if_1
(
.rd_data(rd_data),
.rd_complete(rd_complete),
.A(A),
.CEN(CEN),
.addr(addr),
.Q(Q),
.clk_if(clk_mem),
.rst_for_new_package(rst_for_new_package)
);
// --- ROM (64 words, 16 bits per word) ---
rom_64x16 rom_64x16_1
(
.Q(Q),
.CLK(clk_mem),
.CEN(CEN),
.A(A)
);
// --- TX (including Frame Generator, FM0 Encoder, Miller Encoder) ---
tx tx_1
(
.bs_data(bs_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.bs_complete(bs_complete),
.clk_blf(clk_blf),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.rst_for_new_package(rst_for_new_package),
.reply_data(reply_data),
.crc_16(crc_16),
.m(m),
.trext(trext),
.reply_complete(reply_complete),
.en_crc16_for_rpy(en_crc16_for_rpy),
.start_working(start_working)
);
endmodule