From b0f76bf4b7dddd59badd67f462e50ed8c9be484c Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Tue, 29 Nov 2022 11:30:47 -0500
Subject: [PATCH] Modified the DEF and verilog readers to better support
 DEF2Verilog for converting DEF files generated by magic into structural
 verilog netlists.

---
 VERSION           |  2 +-
 src/DEF2Verilog.c | 29 +++++++++++++++++++++++++++--
 src/readverilog.c | 16 ++++++++++++++++
 3 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/VERSION b/VERSION
index a423214..c47deb0 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.4.99
+1.4.100
diff --git a/src/DEF2Verilog.c b/src/DEF2Verilog.c
index 7a711ea..c256a8c 100644
--- a/src/DEF2Verilog.c
+++ b/src/DEF2Verilog.c
@@ -151,6 +151,30 @@ struct nlist *hash_nets(struct hashlist *p, void *cptr)
 	    if (bptr != NULL) *bptr = ' ';
 	}
     }
+    else if (aidx != -1) {
+	/* If a net name is not backslashed but contains illegal	*/
+	/* characters, then make this a backslashed name in verilog.	*/
+	char *s;
+	char illegal = 0;
+	s = net->netname;
+	if ((*s != '_') && !(isalpha(*s))) illegal = 1;
+	else {
+	    for (++s; *s; s++) {
+		if ((*s != '_') && (*s != '$') && !(isalnum(*s))) {
+		    illegal = 1;
+		    break;
+		}
+	    }
+	}
+ 	if (illegal == 1) {
+	    char *newname;
+	    newname = (char *)malloc(strlen(net->netname) + 3);
+	    sprintf(newname, "\\%s ", net->netname);
+	    free(net->netname);
+	    net->netname = newname;
+	}
+    }
+
 
     /* Check if record already exists */
     bdata = HashLookup(net->netname, NetHash);  
@@ -415,7 +439,7 @@ void write_output(struct cellrec *topcell, char *vlogoutname)
     fprintf(outfptr, "/* Verilog module written by DEF2Verilog (qflow) */\n");
     fprintf(outfptr, "module %s (\n", topcell->name);
 
-    /* Output the verilog netlist verbatim through the	list of ports.	*/
+    /* Output the verilog netlist verbatim through the list of ports. */
 
     for (port = topcell->portlist; port; port = port->next) {
 	if (port->name == NULL) continue;
@@ -471,13 +495,14 @@ void helpmessage(FILE *outf)
     fprintf(outf, "DEF2Verilog [-options] <netlist>\n");
     fprintf(outf, "\n");
     fprintf(outf, "DEF2Verilog converts a DEF file to a verilog structural\n");
-    fprintf(outf, "netlist. Output on stdout.\n");
+    fprintf(outf, "netlist. Output is on stdout if -o option is not provided.\n");
     fprintf(outf, "\n");
     fprintf(outf, "options:\n");
     fprintf(outf, "  -v <path>  Path to verilog file (for I/O list)\n");
     fprintf(outf, "  -l <path>  Path to standard cell LEF file (for macro list)\n");
     fprintf(outf, "  -p <name>  Name of power net\n");
     fprintf(outf, "  -g <name>  Name of ground net\n");
+    fprintf(outf, "  -o <name>  Name of output file\n");
     fprintf(outf, "\n");
     fprintf(outf, "  -h         Print this message\n");    
 
diff --git a/src/readverilog.c b/src/readverilog.c
index 87719d0..11e2d41 100644
--- a/src/readverilog.c
+++ b/src/readverilog.c
@@ -1419,6 +1419,22 @@ void ReadVerilogFile(char *fname, struct cellstack **CellStackPtr,
 	    while (strcmp(nexttok, ";")) SkipTok("X///**/X,;");
 	    continue;
 	}
+	else if (!strcmp(nexttok, "genvar")) {
+	    fprintf(stdout, "Ignoring '%s' in module '%s' (line %d)\n",
+		    nexttok, top->name, vlinenum);
+	    while (strcmp(nexttok, ";")) SkipTok("X///**/X,;");
+	    continue;
+	}
+	else if (!strcmp(nexttok, "generate")) {
+	    // Generate blocks should definitely not be ignored!
+	    // Work to do. . . 
+	    fprintf(stdout, "Warning:  Ignoring generate block in module"
+			" '%s' (line %d)\n",
+			top->name, vlinenum);
+	    while (strcmp(nexttok, "endgenerate"))
+		SkipTokComments(VLOG_DELIMITERS);
+	    continue;
+	}
 	else if (!strcmp(nexttok, "wire") ||
 		 !strcmp(nexttok, "assign")) {	/* wire = node */
 	    struct netrec wb, *nb = NULL;