Merge branch 'master' into qflow-1.4

RTimothyEdwards · Sep 24, 2021 · d749899 · d749899
2 parents a8d0ae3 + e1f692f
commit d749899
Show file tree

Hide file tree

Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/VERSION b/VERSION
@@ -1 +1 @@
-1.4.97
+1.4.98
diff --git a/src/readverilog.c b/src/readverilog.c
@@ -1421,7 +1421,7 @@ void ReadVerilogFile(char *fname, struct cellstack **CellStackPtr,
 	}
 	else if (!strcmp(nexttok, "wire") ||
 		 !strcmp(nexttok, "assign")) {	/* wire = node */
-	    struct netrec wb, *nb;
+	    struct netrec wb, *nb = NULL;
 	    char *eptr, *wirename;
 	    char is_assignment = FALSE;
 	    char is_lhs_bundle = FALSE, is_rhs_bundle = FALSE;
@@ -1474,7 +1474,7 @@ void ReadVerilogFile(char *fname, struct cellstack **CellStackPtr,
 			/* until this tool handles bus joining.  If the	    */
 			/* assignment is made on an undeclared wire, then   */
 			/* adjust the wire bounds.			    */
-			if (nb && nb->start == -1) {
+			if (nb && (nb->start == -1)) {
 			    nb->start = wb.start;
 			    nb->end = wb.end;
 			}