From a67574f86dc944797c17229e94fd8fc9d6fbf949 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 10 Dec 2024 18:03:05 -0500 Subject: [PATCH] Updated the custom additions to sky130_fd_sc_hd with a size-2 fill and decap cells with graded amounts of poly which can be used to hit a specific overall target poly density. --- VERSION | 2 +- sky130/custom/sky130_fd_sc_hd/Readme.txt | 2 + .../gds/sky130_ef_sc_hd__decap_20_12.gds | Bin 0 -> 4108 bytes .../gds/sky130_ef_sc_hd__decap_40_12.gds | Bin 0 -> 4108 bytes .../gds/sky130_ef_sc_hd__decap_60_12.gds | Bin 0 -> 3996 bytes .../gds/sky130_ef_sc_hd__decap_80_12.gds | Bin 0 -> 3996 bytes .../gds/sky130_ef_sc_hd__fill_12.gds | Bin 3996 -> 3474 bytes .../gds/sky130_ef_sc_hd__fill_2.gds | Bin 0 -> 1630 bytes .../gds/sky130_ef_sc_hd__newfill_12.gds | Bin 3458 -> 0 bytes ...2.lef => sky130_ef_sc_hd__decap_20_12.lef} | 6 +- .../lef/sky130_ef_sc_hd__decap_40_12.lef | 79 ++++++++++++++ .../lef/sky130_ef_sc_hd__decap_60_12.lef | 79 ++++++++++++++ .../lef/sky130_ef_sc_hd__decap_80_12.lef | 79 ++++++++++++++ .../lef/sky130_ef_sc_hd__fill_12.lef | 12 +-- .../verilog/sky130_ef_sc_hd__decap_20_12.v | 98 ++++++++++++++++++ .../verilog/sky130_ef_sc_hd__decap_40_12.v | 98 ++++++++++++++++++ .../verilog/sky130_ef_sc_hd__decap_60_12.v | 98 ++++++++++++++++++ .../verilog/sky130_ef_sc_hd__decap_80_12.v | 98 ++++++++++++++++++ ...newfill_12.v => sky130_ef_sc_hd__fill_2.v} | 20 ++-- 19 files changed, 652 insertions(+), 19 deletions(-) create mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_20_12.gds create mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_40_12.gds create mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_60_12.gds create mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_80_12.gds create mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fill_2.gds delete mode 100644 sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__newfill_12.gds rename sky130/custom/sky130_fd_sc_hd/lef/{sky130_ef_sc_hd__newfill_12.lef => sky130_ef_sc_hd__decap_20_12.lef} (94%) create mode 100644 sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_40_12.lef create mode 100644 sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_60_12.lef create mode 100644 sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_80_12.lef create mode 100644 sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_20_12.v create mode 100644 sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_40_12.v create mode 100644 sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_60_12.v create mode 100644 sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_80_12.v rename sky130/custom/sky130_fd_sc_hd/verilog/{sky130_ef_sc_hd__newfill_12.v => sky130_ef_sc_hd__fill_2.v} (79%) diff --git a/VERSION b/VERSION index 0236e72b..57f7ead7 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.0.504 +1.0.505 diff --git a/sky130/custom/sky130_fd_sc_hd/Readme.txt b/sky130/custom/sky130_fd_sc_hd/Readme.txt index c794b92c..fffbdf8f 100644 --- a/sky130/custom/sky130_fd_sc_hd/Readme.txt +++ b/sky130/custom/sky130_fd_sc_hd/Readme.txt @@ -3,3 +3,5 @@ These decap cells were redesigned to cut back on its use of the LI layer because The fill cells were redesigned to add tap diffusion in the middle because otherwise the spacing of the nwells and the height of the cells prevents FOM fill, resulting in a different density error. Cell "newfill_12" was added to satisfy the change in the poly density rule to 38%; this cell is effectively the decap_12 cell with the poly removed, rendering it a fill cell. Its use is to replace some percentage of decap_12 cells until the maximum poly density rule is satisfied. + +12/10/2024: Cell "newfill_12" was removed and replace with (a modified version of) "fill_12", which serves the same purpose but avoids the error in "newfill_12" where the nwell did not extend to the edge and would cause nwell spacing violations. Because SkyWater imposed stricter limits on poly density, cells "decap_20_12", "decap_40_12", "decap_60_12", and "decap_80_12" have been added to allow selection of poly densities in the decap (relative to the original cell) to meet an overall target poly density in a design. diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_20_12.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_20_12.gds new file mode 100644 index 0000000000000000000000000000000000000000..1f8fa114fab3692717ccebf2550d0907c4231dcc GIT binary patch literal 4108 zcmbW4ONbm*6oyY%S5#`bdg11Ad^HABp}H+ATlyOqb4vZLNaQ|Mi>ah zy~->C$wt&5MmH|9aN{GJfI)DjxNsrp#s`R?i)0a8xETNcoI2B0X>VmF1>Ilwx%a>S zeVn>=OHzrVmu0pQwf>Z@q|(9nu>4!vQTo)A3nE!FdF;sg!KH6Lx%uegwLMoZAAdn+ zld$fgG+jG;e((PIeD#%l?Nt8S={!HZdg|os`M&vl?>>p!B55y@za{NQA~H8<;=6QB zToIYMDB>&?#nZB>e?#?yLVsyvW8*4nUc%?7NaK*xxuc?8Ob3@?{7#V=>rY4)O|2HJbaJW`_k2Q{sU2TXPCaY zjNBU6LwPqn@`Czj?$BdC;lBla;s3<)V#R;UdiQ_nIn#G+{I;H%qz^Nz+f!JT#xIh2 zc6&C1I_j;dI9a?GaFy5Wab5d4%l*y;%dyS{)I#oa-Hjd}%e{(z@|fkG61m?+&zbv5 z8||~^uY`Y59vpw`hWW4_eW^2gyxyOA&+#ka&-`cpDm`8^{>fwJ!#t-i^WNz3 zdjH-o^H;*R_r3Wm;a`*o$KTs!KCDMy>Wm(*_wU~_e zf9#pRnSbditIti3gJu7G2gc-U>%Y_EU|Dbbr}iKF{h)8-CpqrHwGlb~ zqCD9D$!|?hQr|@mI;k(pRbRa8Jg@H>bN~02Gn*_N$6D~RHy-;v7^dZy;L2G?I)DvJnD8+^ftY zkl;oQVssNB3pXlmvIv4Zap6ukK0pLrB#YoeWc>eg>P%Oqy_FdYy1(vo?|=XMICblm zWD-R$%6ubg{w_Vqq>bEBfSpwM5~+}yl^niudnD$+RU^tiIDKUCGjZ^iVTo2K8Q$5*7RU#{xi z$9q^Ilr8=@kuVfOqga%)l# zfTkEzx1a0P)}d#j2^G|Z(cKhCE946 zHh(4ji}K+3o7c>T_2^5T(c|_0%zKVs34h)9oF1}|J{FU&ZzG(hR_!s3t|EU}1!+P|k&gk)a|G`!B zSHhpq3hp0D_!s3t|G`!BVLkd%XY_cz|LlhOE8%;`KJ!(Q4wqsQz0 zb7+`~x|yJ8Yf3ct+sWJz>uqr^mta z{H>LrKO*QK9>%=lzf5oRxU#IrSpjFioc*^t>Ci~uU8~j)(&Oo{;=fw;$Da9%`Inxu z`rPz5SoR-{{Y@8tXiUGh{yRMmmi4xOYX7lczKv(h8^-i=>~}w)-vvDm2K98-=O>B$ z(X+1;`NIq4VLfuD^&TpLY-jGFF+C23^<2LzYNKuFc>`_Do%gshsPBJ*b^j9k7D&Ho zH0AU-7}T@h{^5MF|4xsCWxbtQi}R0s20!kZVEZgiUD(H+9tVT^9Oq@$BdN=O9@FEu z(>IU<)JKb^cX}KQ`uB0qBseWAu?|xo+kfq&tLJb^Q^vWEd1A7&V0Ib9BaYL-gxZyV3?I(f-AFmxUw6)gOzv+ hBCw5BnQM>faj-m^3BCMb`gq3lPLG4CZ(`vS`4@sUF`EDY literal 0 HcmV?d00001 diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_60_12.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_60_12.gds new file mode 100644 index 0000000000000000000000000000000000000000..1c95028f7ddc79e76564b1dcedd0cd6b15b318eb GIT binary patch literal 3996 zcmbW4KZqSw6voe+H#6`5?%OyUdAfxbL4pfz3?xWIl6663WsQFlO<*%fvPMZG1ccaG zs4Nmluu+2;Ewo5slZZ`Wm&z?EAXYWG3_G*6iWd7QzJU_K|@|8F8eGB=XM-74Be@p(3{fp|)nD%1&3n0$k5%S8HFZKt=FIqJ}+tJUQ z(d+f&7w<^xQ>xOyQj$Y=BUa$9a-t+vG@N@oi{wlp*bN;U;@cak6%)@r{GH3L9y?^Sa`IYcbUoyWE{$hX7KXubQ zY)3D1Mz7cVhu6)ogn#C=`IYb&`-A@Bb@Q+tz04WCUhm(rZhj^F_v|&l68>U;(7$8d zJZwiVb4IV%`!i%X|CI1&8|GJfy=MMpN6f=Kz04WCKH+~(pa1b)ucb~DYl+RZ7}pBi zdME6C3M{`$q)*!^@ak^B>C_y{;_hu~xuZFk}C%O)@glyK}|*L3%wIRs1Ve zKc1PtnZNXw)%T{?!LmOe`z_b}#F%_*{damDEa&b0qy5M8@?E@R-ZUmx@x1#9{VwQr zFqo%V-=8GrkFJHCm_OXGKb*&$X@7`DAdfSRpV>tHa?e*1^x#r`|J4wmz_b}iOF@)dl1W`dn_Sasn!?({ks%x8FC zupP-<_Uo8lzg@n8Ilz3hV0ow4!JvPDdnU$eS&8c~^%?$mdc6_O^StRH>E-!5y2)yJ{~n&(94C_F*T?hQ>Gitt>wIDTC)w}r;W63&V!!%}-x@FI zT7Ulker3!hi^nk*-0T;JeIJg}@{iKW*&M1o4c@~@Jc|(6!Klo3#`HQ^9*v2-{Au~- PjOCqP2Q}Zqz{m0*P#`6+ literal 0 HcmV?d00001 diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_80_12.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_80_12.gds new file mode 100644 index 0000000000000000000000000000000000000000..70637edb14b749320832cf63438802dfbaed76c0 GIT binary patch literal 3996 zcmbW4Ply~v6vp55bob2c&g{&_-pJ@4;vvYwLN-Q>5|LzG5LsFOMonPTNV5JR7a<_T zyUHSg1TSg`iC#o<@S>uJ9D?9YJmh9B(SrzjFo)p5!{+$lULu{ygp%>HIy)z@Fu ztJl>vl1dc4DzlBK^@nsNl@9(sT>dWYD1GMXMUkwTJaK4!|MHJt{QcO{cY7|KKl+l) zCSl#KG(C0l^xl07`P%FGspI*ZC-VHn+VR)k&L3UK_dXn)q9~ zCN7E0oE34Fn&N5M)W56xL7_jlv9WO(J2YOQf3T{D-?Hf^Zkc|Q9$%KS zeyOT=ANO^7e9Zq2{kHuV)jyNRnZL$|NX(jXV!ufL2i&h<@)N!zCrA&I2-HE_r7{mH@MC%itDuCDv< zh>Em_>B}pqwQ)U^chjRzsDJJbJ@O0xE$9pXr&g9K{#(|&|0^$;zGL&Z_01%GfK}e^ zbCqsL=GE@i4eG47red=AY~U)d-IH1i^Y$!s&RETL&Y&08opoUJ_*gAg^pi)d7L{24 zE=JC0L5XLfXb<`ep22NCOBH|F{}|Z{FU(UpErLc{EPOW|I|(M zVL$p(XY_cz|KN)GE8#!=hWRVuU$h7P2UpC8{pd@b(c|_0JJ!u#3IBWcnZFYLMSIYH z$GZ8jAAPAadc590gNF5|gnzbS{z{M6)L(Yke5j`{bw-bm`9H7wfBe7CQpbw3#O7Iy zX9Zr9$LxLM^f*|~-)i~&BZBeaWz4JjkLisbSC;iSE8r}cas1XN85-%kbH&C%dOR6c z{8y^}*fW1K|I%Al-%l`Su-*n9j#sudmzHgl#2g`cfKXv@rFW<*I<{e}5HTJt- zpfBigFsP@qzCTISkDi5{s2^Tv59?7g?T^t3_uzhIK1e%~9><6v<7ee74v6UqDyz8ulxb@@yBHhz-hPQD+J<1gCPzxb{3 zqMr5V|La%AY_fP1x!`5LIPCjin3jK(R%UakvKxGWOgsw_*g;liIwN`dQCttC)no)9YZ-Khrfo)a)I;@Zq{g?{w&Ou;|aLzlHm! zWqaqZ>M!$+URM_V{ayZ3k-qnk!TN$oEnWmGBz4=IJZphxX|FLqE+|!W+JCz7l?DkNVBm<}2ZkTr^(^KeR{v zHH+pe;jf)EUkN|7NB!2E`AYb$W%HHrLwnShyWu)P&UxK1|3*ap!jrC*B=`r_4ub2Dv+t!acr^nnIyZktxZ7#pvb9P#~{O{_^>V4eW(^P%~ D5q0m` literal 3996 zcmbuCO=ule7>3W>`MLl3X{XB7xa^`3ur*+isw8R9MI`>#(qc16oBoi3LRQtaN{~Xu zl?G{cF0yb{&_x$T(3KSF(v7%qqk>%o7cS!ae&6{r=hn_#(%z6fH{Ut$dCr+RGk31b zT*Jj~Dr&fwT!bIKqM`Rwjck4G>am%l#p;D({akVBd{JDueC0}U>=~EG>5KClvr9jG z{r7W=-#)#ydFCxQmDY@vRgaaloXh$R_ovIo8koiOL@cwBKZmaCd$O~o?~V8`nZ&Qp zFG_yG=RZULB`oQ9z#Sx5H!juXcXxNUnKvSPQu9iwhyJ-o^nWm%H?MJ|e_ryrU;igK zsIOwJ^CjCiF$U^Jw1@NmU*7$pd1H)&&AbtH$@ld9;rKt+aH-24kNEcq?y26B>D=H8 zzP@xlIj_HC%q`a%WN*KA>WzoXV_fE6US8CEd(V&kle^Y9_D}Sy%WWTVzxe$l^BvV6 z<4b=aT;JS&*SGMX{PEGp2VSmk+46pWzb@xDdFbn7S@P3mKKV`8X|(Igh0Gy_kVx5FORwI@BT29Z=A(-fcsP242b)Z)Q!XUr~C5ikDErU9rq{Zl~S)-mHU4x*z1a<;dYPx+w^#a`x7FKP z3y7@LjWzz}ZS}U+jOt~ce&1f{Z(mbyXEq?bQa9H4+t<|FnKi1HdHQ{OrN4Vxy*=D3 zc^-uDO5IrF@19m~kJs|H=ILc#DfLQ!|FC-dcLKsIbz_ace^|Z!J4W>~Prq-k^pD+B z@Azgwc%^Qv@sHh8@A#%sz0A|^+bjJOx70g%F(ABBH`e$kZmD3W{RcMG zdvGQoyizyT_z!HT_u!0Cz0A|^+bjJ!`f%Uny8+>qy0ONepHy!SaQ|@}dYM;BJ@ha5 z&yVN%T+n_2UR-<8rzMkB+_(P4uO~lO*w2Xmwc|0%zQ*`-9pC6K>v%@=3&+#@d+y%h z{N%Y8Yw4`(ddT<`#vd=47TRXyy5%L*<07BWI6i*7TAw@@V}L#4{BTU3Co*fp|6R!h zPk5Y{k^SU3%eXVNzQP~>S8RRhysl@D-^=V>>KWtSK;Is}((z+Y ze1!Xvv3(Weqi#gKGT(j=Sv;F`1|=Iukwx8z_S!tX%p2)t-Z;vi{j7Oo^Fz%WQLprK zoy>9lM&?*Ij>>cW%p19G=8bjhkAA_vxQV_WmE=BU-H7(e`EyS(pKO<8j&);QK6^_0 zW=qpKKX7zYyL1zD zaCKM2$-h8B9K_K@oFqQyeec_xTWuN-T%P2~`Q7*9yg6`)qT6VeqN(qw!J&d_#NlU@ zBX{}I5>SuR^NWwqbl$)Cakl;D_||6c2Ab*aT+_M1{f8${pUCd6WrI7}z11vRTi@8o zP60_7aMKYU!OcXNLu)Pu@On5LzVpiG98fx9YQAW)f5a~od7#=;zWRxLi{DMn?;+&d z1^y-X56FA{Kz=4r^9SR2=J!!~9Lw_;HD6TX*R+1-e;~p<+`$r3xI-nl!X^)vnid>;Q|w_S)oF>mp2T~ofI^=tp@a7QB_ zVU|-+`hvPtO@kETr=n8zWE4T6DB)ROkh5;(v-X5AHUbrs*%htbcgl4+r?=rvicF@n& thRZM4uxE>fGu!0Ww|uDa1J20rk(y5(%cq<*&sRPxZ)!eOc#dO|;16*I)UW^m literal 0 HcmV?d00001 diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__newfill_12.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__newfill_12.gds deleted file mode 100644 index afafbee2599501d74b7db7f0c4cb91dd4275c05c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3458 zcmbuBziSj*6vxlb&dly6*<_;|B|Zxqi-6!SP(+ZZ0g*_aPt1ENBwP3!#YRx{4^UDF z+6fkljfI64DmE52c4A@oIxR$auh1e`#_#u>d)(R8J0!S}{cO&?pE>v5Id|qtE=h7s z)>o3+XKBcYjLL+J6@N=T$qyaeC(^EFd-g8uoPP7@%dV-Hn;+aeaa7i4ac@JOU%qf{ z>-H_3(`P!DPj=3o>U1uhzIx{T#fzP-+eFg3NZw3jQu5(M+OnxtU0PZ~qHNqaI4`nh zM#SmyY+TaOuD`eIi^xq}^iN~sxyV>U#OZOc)R+IvuObP3r^msfKi`udYW5ai_;B1~ zx4ZN>SoG)A-^BUTvbpnD^_%%dk1LD*z8?RHNc|mTuyIYKa=c5AgHgY|(|nSC`$L!X zLwnR`-pUQjpKP)GPLG38pVwzUk{KWT}%w$9x>W z)8k;=XZ=0KHTc1`SieS(D}VOAe(%_N3Au=Sxw}BFzqLpGWX^mg{A$g7CH&AH_0tLS zmGIN|<}2Zc_Nbr1;eA))cYfb|rN@6&KVkm0*XAqX*Dsi_gdf_Y`5U*)S8^=a2V6%b z{Lmit2eIEdekHsiJX7c^Jzg^Y=0@|C@S523^p)^Kdo=&>SM!zdM(&xfgdf_Ye(RO_ zO8BE^%~!$??NNW#g854LtGAo4gdf_YetXt@CH(f1`AYbqJ?hJyuuo9u+&8R$qsPnl zPcmoySm*Ru_ePJG`{{)BW1Z7u-5Wh#?q`eEFT>pFvF?o?FZXM&tsm>09_!xd@p8X$ z%lfg->9OvO9xwL?k6S<1KRwpH(c|TQbEEZRozr988$Dj`4}Z0OtaEy-d!xt8{njh% z$2zCSx;J{f++Vd|{aEMpSocPcm;3Em>&H5$$GSIq{3m~^|NYx|3J0G-ygTXQ=pX*)$S=m<3g@?#?|+;B58s|Y!uRB2`TH}Be{#9=_wnP1U0i?oIDh|c z{@u%7|Czr0*L(A8eF^8!x?9Hcb4GnXe?Ut=+MUOIwf>wQ2aEInOa0W(-{$h$J!iM2 P$Nyh_S-Fo#dz#93DL?5> diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__newfill_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_20_12.lef similarity index 94% rename from sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__newfill_12.lef rename to sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_20_12.lef index e291180e..2092dc39 100644 --- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__newfill_12.lef +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_20_12.lef @@ -2,9 +2,9 @@ VERSION 5.7 ; NOWIREEXTENSIONATPIN ON ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; -MACRO sky130_ef_sc_hd__newfill_12 +MACRO sky130_ef_sc_hd__decap_20_12 CLASS CORE SPACER ; - FOREIGN sky130_ef_sc_hd__newfill_12 ; + FOREIGN sky130_ef_sc_hd__decap_20_12 ; ORIGIN 0.000 0.000 ; SIZE 5.520 BY 2.720 ; SYMMETRY X Y R90 ; @@ -74,6 +74,6 @@ MACRO sky130_ef_sc_hd__newfill_12 RECT 4.745 -0.085 4.915 0.085 ; RECT 5.205 -0.085 5.375 0.085 ; END -END sky130_ef_sc_hd__newfill_12 +END sky130_ef_sc_hd__decap_20_12 END LIBRARY diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_40_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_40_12.lef new file mode 100644 index 00000000..06174917 --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_40_12.lef @@ -0,0 +1,79 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sky130_ef_sc_hd__decap_40_12 + CLASS CORE SPACER ; + FOREIGN sky130_ef_sc_hd__decap_40_12 ; + ORIGIN 0.000 0.000 ; + SIZE 5.520 BY 2.720 ; + SYMMETRY X Y R90 ; + SITE unithd ; + PIN VPWR + USE POWER ; + PORT + LAYER met1 ; + RECT 0.000 2.480 5.520 2.960 ; + END + END VPWR + PIN VGND + USE GROUND ; + PORT + LAYER met1 ; + RECT 0.000 -0.240 5.520 0.240 ; + END + END VGND + PIN VPB + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER nwell ; + RECT -0.190 1.305 5.710 2.910 ; + END + END VPB + PIN VNB + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER pwell ; + RECT 0.005 0.105 5.515 0.915 ; + RECT 0.145 -0.085 0.315 0.105 ; + END + END VNB + OBS + LAYER li1 ; + RECT 0.000 2.635 5.520 2.805 ; + RECT 0.085 2.200 5.430 2.635 ; + RECT 1.670 0.630 2.010 1.460 ; + RECT 3.490 0.950 3.840 2.200 ; + RECT 0.085 0.085 5.430 0.630 ; + RECT 0.000 -0.085 5.520 0.085 ; + LAYER mcon ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 1.065 2.635 1.235 2.805 ; + RECT 1.525 2.635 1.695 2.805 ; + RECT 1.985 2.635 2.155 2.805 ; + RECT 2.445 2.635 2.615 2.805 ; + RECT 2.905 2.635 3.075 2.805 ; + RECT 3.365 2.635 3.535 2.805 ; + RECT 3.825 2.635 3.995 2.805 ; + RECT 4.285 2.635 4.455 2.805 ; + RECT 4.745 2.635 4.915 2.805 ; + RECT 5.205 2.635 5.375 2.805 ; + RECT 0.145 -0.085 0.315 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + END +END sky130_ef_sc_hd__decap_40_12 +END LIBRARY + diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_60_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_60_12.lef new file mode 100644 index 00000000..3d308ff5 --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_60_12.lef @@ -0,0 +1,79 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sky130_ef_sc_hd__decap_60_12 + CLASS CORE SPACER ; + FOREIGN sky130_ef_sc_hd__decap_60_12 ; + ORIGIN 0.000 0.000 ; + SIZE 5.520 BY 2.720 ; + SYMMETRY X Y R90 ; + SITE unithd ; + PIN VPWR + USE POWER ; + PORT + LAYER met1 ; + RECT 0.000 2.480 5.520 2.960 ; + END + END VPWR + PIN VGND + USE GROUND ; + PORT + LAYER met1 ; + RECT 0.000 -0.240 5.520 0.240 ; + END + END VGND + PIN VPB + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER nwell ; + RECT -0.190 1.305 5.710 2.910 ; + END + END VPB + PIN VNB + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER pwell ; + RECT 0.005 0.105 5.515 0.915 ; + RECT 0.145 -0.085 0.315 0.105 ; + END + END VNB + OBS + LAYER li1 ; + RECT 0.000 2.635 5.520 2.805 ; + RECT 0.085 2.200 5.430 2.635 ; + RECT 1.670 0.630 2.010 1.460 ; + RECT 3.490 0.950 3.840 2.200 ; + RECT 0.085 0.085 5.430 0.630 ; + RECT 0.000 -0.085 5.520 0.085 ; + LAYER mcon ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 1.065 2.635 1.235 2.805 ; + RECT 1.525 2.635 1.695 2.805 ; + RECT 1.985 2.635 2.155 2.805 ; + RECT 2.445 2.635 2.615 2.805 ; + RECT 2.905 2.635 3.075 2.805 ; + RECT 3.365 2.635 3.535 2.805 ; + RECT 3.825 2.635 3.995 2.805 ; + RECT 4.285 2.635 4.455 2.805 ; + RECT 4.745 2.635 4.915 2.805 ; + RECT 5.205 2.635 5.375 2.805 ; + RECT 0.145 -0.085 0.315 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + END +END sky130_ef_sc_hd__decap_60_12 +END LIBRARY + diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_80_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_80_12.lef new file mode 100644 index 00000000..c1cc0a89 --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_80_12.lef @@ -0,0 +1,79 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sky130_ef_sc_hd__decap_80_12 + CLASS CORE SPACER ; + FOREIGN sky130_ef_sc_hd__decap_80_12 ; + ORIGIN 0.000 0.000 ; + SIZE 5.520 BY 2.720 ; + SYMMETRY X Y R90 ; + SITE unithd ; + PIN VPWR + USE POWER ; + PORT + LAYER met1 ; + RECT 0.000 2.480 5.520 2.960 ; + END + END VPWR + PIN VGND + USE GROUND ; + PORT + LAYER met1 ; + RECT 0.000 -0.240 5.520 0.240 ; + END + END VGND + PIN VPB + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER nwell ; + RECT -0.190 1.305 5.710 2.910 ; + END + END VPB + PIN VNB + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER pwell ; + RECT 0.005 0.105 5.515 0.915 ; + RECT 0.145 -0.085 0.315 0.105 ; + END + END VNB + OBS + LAYER li1 ; + RECT 0.000 2.635 5.520 2.805 ; + RECT 0.085 2.200 5.430 2.635 ; + RECT 1.670 0.630 2.010 1.460 ; + RECT 3.490 0.950 3.840 2.200 ; + RECT 0.085 0.085 5.430 0.630 ; + RECT 0.000 -0.085 5.520 0.085 ; + LAYER mcon ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 1.065 2.635 1.235 2.805 ; + RECT 1.525 2.635 1.695 2.805 ; + RECT 1.985 2.635 2.155 2.805 ; + RECT 2.445 2.635 2.615 2.805 ; + RECT 2.905 2.635 3.075 2.805 ; + RECT 3.365 2.635 3.535 2.805 ; + RECT 3.825 2.635 3.995 2.805 ; + RECT 4.285 2.635 4.455 2.805 ; + RECT 4.745 2.635 4.915 2.805 ; + RECT 5.205 2.635 5.375 2.805 ; + RECT 0.145 -0.085 0.315 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + END +END sky130_ef_sc_hd__decap_80_12 +END LIBRARY + diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef index e171847d..6be9b48c 100644 --- a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef @@ -28,7 +28,7 @@ MACRO sky130_ef_sc_hd__fill_12 USE POWER ; PORT LAYER nwell ; - RECT -0.190 1.305 2.950 2.910 ; + RECT -0.190 1.305 5.710 2.910 ; END END VPB PIN VNB @@ -36,17 +36,17 @@ MACRO sky130_ef_sc_hd__fill_12 USE GROUND ; PORT LAYER pwell ; - RECT 0.005 0.105 2.755 0.915 ; + RECT 0.005 0.105 5.515 0.915 ; RECT 0.145 -0.085 0.315 0.105 ; END END VNB OBS LAYER li1 ; RECT 0.000 2.635 5.520 2.805 ; - RECT 0.085 1.545 2.675 2.635 ; - RECT 0.085 0.855 1.295 1.375 ; - RECT 1.465 1.025 2.675 1.545 ; - RECT 0.085 0.085 2.675 0.855 ; + RECT 0.085 2.200 5.430 2.635 ; + RECT 1.670 0.630 2.010 1.460 ; + RECT 3.490 0.950 3.840 2.200 ; + RECT 0.085 0.085 5.430 0.630 ; RECT 0.000 -0.085 5.520 0.085 ; LAYER mcon ; RECT 0.145 2.635 0.315 2.805 ; diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_20_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_20_12.v new file mode 100644 index 00000000..2c8af53d --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_20_12.v @@ -0,0 +1,98 @@ +/** + * Copyright 2020 The SkyWater PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +`ifndef SKY130_EF_SC_HD__DECAP_20_12_V +`define SKY130_EF_SC_HD__DECAP_20_12_V + +/** + * decap: Decoupling capacitance filler. + * + * Verilog wrapper for decap with size of 12 units. + * This cell has been modified from sky130_fd_sc_hd__decap_12 + * to remove excess LI, so that when used extensively in a + * padded region of a digital layout, it does not cause the + * LI layer to exceed critical density. Additionally, this + * cell was modified from sky130_ef_sc_hd__decap_12 to remove + * excess poly, so that when used extensively in a padded + * region of a digital layout, it does not cause the POLY + * layer to exceed critical density. A combination of + * cells _20_12, _40_12, _60_12, and _80_12 (representing + * 20, 40, 60, and 80 percent of the original amount of poly) + * can be used to achieve a target poly density. + * + * WARNING: This file is autogenerated, do not modify directly! + */ + +`timescale 1ns / 1ps +`default_nettype none + +`ifdef USE_POWER_PINS +/*********************************************************/ + +`celldefine +module sky130_ef_sc_hd__decap_20_12 ( + VPWR, + VGND, + VPB , + VNB +); + + // Module ports + input VPWR; + input VGND; + input VPB ; + input VNB ; + // No contents. +endmodule +`endcelldefine + +/*********************************************************/ +`else // If not USE_POWER_PINS +/*********************************************************/ + +`ifdef FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_20_12 (); + // No contents. +endmodule +`endcelldefine + +`else // If not FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_20_12 (); + + // Voltage supply signals + supply1 VPWR; + supply0 VGND; + supply1 VPB ; + supply0 VNB ; + // No contents. +endmodule +`endcelldefine + +`endif // If not FUNCTIONAL + +/*********************************************************/ +`endif // If not USE_POWER_PINS + +`default_nettype wire +`endif // SKY130_EF_SC_HD__DECAP_20_12_V + + diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_40_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_40_12.v new file mode 100644 index 00000000..0df86cbf --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_40_12.v @@ -0,0 +1,98 @@ +/** + * Copyright 2020 The SkyWater PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +`ifndef SKY130_EF_SC_HD__DECAP_40_12_V +`define SKY130_EF_SC_HD__DECAP_40_12_V + +/** + * decap: Decoupling capacitance filler. + * + * Verilog wrapper for decap with size of 12 units. + * This cell has been modified from sky130_fd_sc_hd__decap_12 + * to remove excess LI, so that when used extensively in a + * padded region of a digital layout, it does not cause the + * LI layer to exceed critical density. Additionally, this + * cell was modified from sky130_ef_sc_hd__decap_12 to remove + * excess poly, so that when used extensively in a padded + * region of a digital layout, it does not cause the POLY + * layer to exceed critical density. A combination of + * cells _20_12, _40_12, _60_12, and _80_12 (representing + * 20, 40, 60, and 80 percent of the original amount of poly) + * can be used to achieve a target poly density. + * + * WARNING: This file is autogenerated, do not modify directly! + */ + +`timescale 1ns / 1ps +`default_nettype none + +`ifdef USE_POWER_PINS +/*********************************************************/ + +`celldefine +module sky130_ef_sc_hd__decap_40_12 ( + VPWR, + VGND, + VPB , + VNB +); + + // Module ports + input VPWR; + input VGND; + input VPB ; + input VNB ; + // No contents. +endmodule +`endcelldefine + +/*********************************************************/ +`else // If not USE_POWER_PINS +/*********************************************************/ + +`ifdef FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_40_12 (); + // No contents. +endmodule +`endcelldefine + +`else // If not FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_40_12 (); + + // Voltage supply signals + supply1 VPWR; + supply0 VGND; + supply1 VPB ; + supply0 VNB ; + // No contents. +endmodule +`endcelldefine + +`endif // If not FUNCTIONAL + +/*********************************************************/ +`endif // If not USE_POWER_PINS + +`default_nettype wire +`endif // SKY130_EF_SC_HD__DECAP_40_12_V + + diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_60_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_60_12.v new file mode 100644 index 00000000..e15678a7 --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_60_12.v @@ -0,0 +1,98 @@ +/** + * Copyright 2020 The SkyWater PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +`ifndef SKY130_EF_SC_HD__DECAP_60_12_V +`define SKY130_EF_SC_HD__DECAP_60_12_V + +/** + * decap: Decoupling capacitance filler. + * + * Verilog wrapper for decap with size of 12 units. + * This cell has been modified from sky130_fd_sc_hd__decap_12 + * to remove excess LI, so that when used extensively in a + * padded region of a digital layout, it does not cause the + * LI layer to exceed critical density. Additionally, this + * cell was modified from sky130_ef_sc_hd__decap_12 to remove + * excess poly, so that when used extensively in a padded + * region of a digital layout, it does not cause the POLY + * layer to exceed critical density. A combination of + * cells _20_12, _40_12, _60_12, and _80_12 (representing + * 20, 40, 60, and 80 percent of the original amount of poly) + * can be used to achieve a target poly density. + * + * WARNING: This file is autogenerated, do not modify directly! + */ + +`timescale 1ns / 1ps +`default_nettype none + +`ifdef USE_POWER_PINS +/*********************************************************/ + +`celldefine +module sky130_ef_sc_hd__decap_60_12 ( + VPWR, + VGND, + VPB , + VNB +); + + // Module ports + input VPWR; + input VGND; + input VPB ; + input VNB ; + // No contents. +endmodule +`endcelldefine + +/*********************************************************/ +`else // If not USE_POWER_PINS +/*********************************************************/ + +`ifdef FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_60_12 (); + // No contents. +endmodule +`endcelldefine + +`else // If not FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_60_12 (); + + // Voltage supply signals + supply1 VPWR; + supply0 VGND; + supply1 VPB ; + supply0 VNB ; + // No contents. +endmodule +`endcelldefine + +`endif // If not FUNCTIONAL + +/*********************************************************/ +`endif // If not USE_POWER_PINS + +`default_nettype wire +`endif // SKY130_EF_SC_HD__DECAP_60_12_V + + diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_80_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_80_12.v new file mode 100644 index 00000000..16c9712b --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_80_12.v @@ -0,0 +1,98 @@ +/** + * Copyright 2020 The SkyWater PDK Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +`ifndef SKY130_EF_SC_HD__DECAP_80_12_V +`define SKY130_EF_SC_HD__DECAP_80_12_V + +/** + * decap: Decoupling capacitance filler. + * + * Verilog wrapper for decap with size of 12 units. + * This cell has been modified from sky130_fd_sc_hd__decap_12 + * to remove excess LI, so that when used extensively in a + * padded region of a digital layout, it does not cause the + * LI layer to exceed critical density. Additionally, this + * cell was modified from sky130_ef_sc_hd__decap_12 to remove + * excess poly, so that when used extensively in a padded + * region of a digital layout, it does not cause the POLY + * layer to exceed critical density. A combination of + * cells _20_12, _40_12, _60_12, and _80_12 (representing + * 20, 40, 60, and 80 percent of the original amount of poly) + * can be used to achieve a target poly density. + * + * WARNING: This file is autogenerated, do not modify directly! + */ + +`timescale 1ns / 1ps +`default_nettype none + +`ifdef USE_POWER_PINS +/*********************************************************/ + +`celldefine +module sky130_ef_sc_hd__decap_80_12 ( + VPWR, + VGND, + VPB , + VNB +); + + // Module ports + input VPWR; + input VGND; + input VPB ; + input VNB ; + // No contents. +endmodule +`endcelldefine + +/*********************************************************/ +`else // If not USE_POWER_PINS +/*********************************************************/ + +`ifdef FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_80_12 (); + // No contents. +endmodule +`endcelldefine + +`else // If not FUNCTIONAL + +`celldefine +module sky130_ef_sc_hd__decap_80_12 (); + + // Voltage supply signals + supply1 VPWR; + supply0 VGND; + supply1 VPB ; + supply0 VNB ; + // No contents. +endmodule +`endcelldefine + +`endif // If not FUNCTIONAL + +/*********************************************************/ +`endif // If not USE_POWER_PINS + +`default_nettype wire +`endif // SKY130_EF_SC_HD__DECAP_80_12_V + + diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__newfill_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_2.v similarity index 79% rename from sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__newfill_12.v rename to sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_2.v index b33927ad..430a77c0 100644 --- a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__newfill_12.v +++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_2.v @@ -16,30 +16,32 @@ * SPDX-License-Identifier: Apache-2.0 */ -`ifndef SKY130_EF_SC_HD__NEWFILL_12_V -`define SKY130_EF_SC_HD__NEWFILL_12_V +`ifndef SKY130_EF_SC_HD__FILL_2_V +`define SKY130_EF_SC_HD__FILL_2_V /** - * newfill_12: Designed to replace the decap_12 cell while reducing - * the amount of local interconnect and satisfying the more restrictive - * poly density rule of 38%. + * fill: Fill cell. + * + * Verilog wrapper for fill with size of 4 units. + * + * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none - `ifdef USE_POWER_PINS /*********************************************************/ `celldefine -module sky130_ef_sc_hd__newfill_12 ( +module sky130_ef_sc_hd__fill_2 ( VPWR, VGND, VPB , VNB ); + // Module ports input VPWR; input VGND; input VPB ; @@ -53,7 +55,7 @@ endmodule /*********************************************************/ `celldefine -module sky130_ef_sc_hd__newfill_12 (); +module sky130_ef_sc_hd__fill_2 (); // Voltage supply signals supply1 VPWR; @@ -68,4 +70,4 @@ endmodule `endif // USE_POWER_PINS `default_nettype wire -`endif // SKY130_EF_SC_HD__NEWFILL_12_V +`endif // SKY130_EF_SC_HD__FILL_2_V