Port Model on Non Intel Architectures

Port Model on Non-Intel Architectures

This is an overview on the applicability of the port model to non-intel architectures

AMD

ARM Cortex A8

Interesting documents:

• [ti] http://processors.wiki.ti.com/index.php/Cortex-A8_Architecture
• [a8] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf

Two pipelines (pipe0 and pipe1), both take the same instructions, but only pipe0 can handle MUL instructions (as well as 'Load/store multiple and other multi-cycle instructions', what are they?). Only one load/store instruction can be issued per cycle. Decoding and register file allocation seem to handle two instructions per cycle.

Source and destination register's (required) availability in execution stages is documented in [a8 16-4ff].

Load and stores with 64-bit offsets take an additional iteration.

Two 32-bit loads and/or stores can be scheduled per cycle [a8 16.2.9].

Power8