diff --git a/osaca/data/m1.yml b/osaca/data/m1.yml index 229737b..a2667a1 100644 --- a/osaca/data/m1.yml +++ b/osaca/data/m1.yml @@ -24,7 +24,7 @@ port_model_scheme: | | 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 | +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ 0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5 - \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ | ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ @@ -37,15 +37,15 @@ port_model_scheme: | +------+ +------+ +------+ +------+ +------+ +------+ | FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA | +------+ +------+ +------+ +------+ +------+ +------+ - +------+ +------+ - | 2INT | | 2INT | - +------+ +------+ - +------+ - | RCP | - +------+ - +------+ - | SHA | - +------+ + +------+ +------+ + | 2INT | | 2INT | + +------+ +------+ + +------+ + | RCP | + +------+ + +------+ + | SHA | + +------+ instruction_forms: - name: [adc, adcs] operands: @@ -105,7 +105,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: register @@ -116,7 +116,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: immediate @@ -127,7 +127,7 @@ instruction_forms: - name: adr operands: - class: register - prefix: '*' + prefix: '*' - class: identifier throughput: 0.5 latency: ~ # 1*p89 @@ -1521,7 +1521,7 @@ instruction_forms: throughput: 0.16666666 latency: ~ # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1532,7 +1532,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1543,7 +1543,7 @@ instruction_forms: throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1554,7 +1554,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1596,8 +1596,8 @@ instruction_forms: latency: ~ port_pressure: [] - name: ret - operands: - - class: identifier + operands: + - class: identifier throughput: 0.0 latency: ~ port_pressure: [] @@ -1650,7 +1650,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w throughput: 0.33333333 @@ -1659,7 +1659,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x throughput: 0.33333333 @@ -1668,7 +1668,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x - class: immediate @@ -1679,7 +1679,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w - class: immediate @@ -2831,9 +2831,9 @@ instruction_forms: prefix: "*" - class: register prefix: "*" - - class: immediate + - class: immediate imd: int - - class: immediate + - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 @@ -2912,7 +2912,7 @@ instruction_forms: prefix: s - class: immediate imd: int - - class: condition + - class: condition ccode: "*" throughput: 1.0 latency: 1.0 # 1*p3 @@ -3617,7 +3617,7 @@ instruction_forms: width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 - port_pressure: [[1, '0123']] + port_pressure: [[1, '0123']] - name: [fmla, fmls] operands: - class: register diff --git a/osaca/data/spr.yml b/osaca/data/spr.yml index 9b8ff68..c95540f 100644 --- a/osaca/data/spr.yml +++ b/osaca/data/spr.yml @@ -2,9 +2,9 @@ osaca_version: 0.5.3 micro_architecture: Sapphire Rapids arch_code: SPR isa: x86 -ROB_size: ~ +ROB_size: ~ retired_uOps_per_cycle: ~ -scheduler_size: ~ +scheduler_size: ~ hidden_loads: false load_latency: {gpr: 5.0, mm: 5.0, xmm: 5.0, ymm: 5.0, zmm: 5.0} load_throughput: @@ -13,7 +13,7 @@ load_throughput: - {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} - {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} load_throughput_default: [[1, ['2', '3', '11']]] -store_throughput: +store_throughput: - {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '4'], [1, '9']]} - {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} - {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} @@ -2946,7 +2946,7 @@ instruction_forms: name: xmm # ibench - class: register # ibench name: xmm # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -2959,7 +2959,7 @@ instruction_forms: - class: register # ibench name: xmm # ibench mask: True # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -3338,7 +3338,7 @@ instruction_forms: port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3353,7 +3353,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench throughput: 1.0 # ibench uops: 9 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3368,7 +3368,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench throughput: 2.0 # ibench uops: 16 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -3383,7 +3383,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench throughput: 3.0 # ibench uops: 31 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3397,7 +3397,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench throughput: 1.0 # ibench uops: 9 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3411,7 +3411,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench throughput: 2.0 # ibench uops: 16 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3520,7 +3520,7 @@ instruction_forms: name: xmm # ibench - class: register # ibench name: xmm # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -3712,7 +3712,7 @@ instruction_forms: port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3724,7 +3724,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3736,7 +3736,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -3748,7 +3748,7 @@ instruction_forms: port_pressure: [[1, '05']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3761,7 +3761,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3774,7 +3774,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -4079,6 +4079,15 @@ instruction_forms: port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 uops: 1 +- name: vcvtdq2pd # uops.info + operands: # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: zmm # uops.info + latency: 7 # uops.info + port_pressure: [[1, '0'], [1, '5']] # uops.info + throughput: 1 # uops.info - name: vcvtss2si # uops.info operands: # uops.info - class: register # uops.info @@ -4258,7 +4267,7 @@ instruction_forms: throughput: 0.5 # uops.info uops: 1 # uops.info ############## || ################# -############## \/ assumed from ICX ################# +############## \/ assumed from ICX ################# - name: vinsertf128 operands: - class: immediate @@ -4413,6 +4422,28 @@ instruction_forms: port_pressure: [[1, '5']] throughput: 1.0 uops: 1 +- name: vcvtsi2sd + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: vcvtdq2pd + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 + uops: 2 - name: vcvtsi2ss operands: - class: register @@ -4421,9 +4452,9 @@ instruction_forms: name: xmm - class: register name: xmm - latency: 2 - port_pressure: [[1, '01'], [2, '5']] - throughput: 2.0 + latency: 4 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 uops: 3 - name: [vextractf128, vextracti128] operands: @@ -4599,6 +4630,20 @@ instruction_forms: port_pressure: [[1, '5']] # uops.info throughput: 1.0 # uops.info uops: 1 # uops.info +- name: vpinsrd # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: gpr # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '15'], [1, '1']] # asmbench + throughput: 1.0 # asmbench + uops: 2 # asmbench - name: vpalignr # asmbench operands: # asmbench - class: immediate # asmbench @@ -4725,7 +4770,7 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench -- name: vpermd # asmbench +- name: [vpermd, vpermt2q] # asmbench operands: # asmbench - class: register # asmbench name: zmm # asmbench @@ -4737,7 +4782,7 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench -- name: vpermd # asmbench +- name: [vpermd, vpermt2q] # asmbench operands: # asmbench - class: register # asmbench name: zmm # asmbench @@ -4800,6 +4845,156 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench - name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench operands: # asmbench - class: register # asmbench @@ -5002,450 +5197,460 @@ instruction_forms: port_pressure: [[1, '05']] # uops.info throughput: 0.5 # uops.info uops: 1 # uops.info -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: vpunpckhqdq +- name: VCMPPS operands: + - class: immediate + imd: int - class: register name: xmm - class: register name: xmm - class: register name: xmm - latency: 1 - port_pressure: [[1, '15']] + latency: 4 + port_pressure: [[1, '01']] throughput: 0.5 uops: 1 -- name: vpunpckhqdq +- name: VCMPPS operands: + - class: immediate + imd: int - class: register name: ymm - class: register name: ymm - class: register name: ymm - latency: 1 - port_pressure: [[1, '15']] + latency: 4 + port_pressure: [[1, '01']] throughput: 0.5 uops: 1 -- name: vpunpckhqdq - operands: - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: zmm - latency: 1 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 - -########### /\ ########## -########### || assumed from ICX ########## -- name: AND - operands: - - class: immediate - imd: int - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: RET - operands: [] - latency: 0 - port_pressure: [[1, '49'], [1, '78']] - throughput: 0.5 - uops: 2 -- name: CALL - operands: - - class: identifier - latency: 0 - port_pressure: [[1, '49'], [1, '78']] - throughput: 0.5 - uops: 2 -- name: TEST - operands: - - class: immediate - imd: int - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: TEST - operands: - - class: register - name: gpr - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: PTEST - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 -- name: VPTEST - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 -- name: VPTEST - operands: - - class: register - name: ymm - - class: register - name: ymm - latency: 6 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 -- name: [VTESTPD, VTESTPS] - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 3 - port_pressure: [[1, '0']] - throughput: 1.0 - uops: 1 -- name: [VTESTPD, VTESTPS] - operands: - - class: register - name: ymm - - class: register - name: ymm - latency: 5 - port_pressure: [[1, '0']] - throughput: 1.0 - uops: 1 -- name: VXORPD - operands: - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: VXORPD - operands: - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: VXORPS - operands: - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: VXORPS - operands: - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: VBROADCASTSS - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: register - name: xmm - - class: register - name: ymm - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: register - name: xmm - - class: register - name: zmm - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: memory - base: "*" - offset: "*" - index: "*" - scale: "*" - - class: register - name: ymm - latency: 5 - port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: memory - base: "*" - offset: "*" - index: "*" - scale: "*" - - class: register - name: zmm - latency: 5 - port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] - throughput: 1.0 - uops: 1 -- name: vandpd +- name: VCMPPD operands: + - class: immediate + imd: int - class: register name: xmm - class: register name: xmm - class: register name: xmm - latency: 1 - port_pressure: [[1, '015']] - throughput: 0.33333 + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 uops: 1 -- name: vandpd +- name: VCMPPD operands: + - class: immediate + imd: int - class: register name: ymm - class: register name: ymm - class: register name: ymm - latency: 1 - port_pressure: [[1, '015']] - throughput: 0.33333 + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 uops: 1 -- name: vandpd +- name: VCMPPS operands: + - class: immediate + imd: int - class: register name: zmm - class: register name: zmm - class: register - name: zmm - latency: 1 - port_pressure: [[1, '05']] + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 + +########### /\ ########## +########### || assumed from ICX ########## +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: RET + operands: [] + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: CALL + operands: + - class: identifier + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: [VTESTPD, VTESTPS] + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: [VTESTPD, VTESTPS] + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 +- name: vandpd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.33333 + uops: 1 +- name: vandpd + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.33333 + uops: 1 +- name: vandpd + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] throughput: 0.5 uops: 1 - name: vshuff64x2 @@ -5462,3 +5667,71 @@ instruction_forms: port_pressure: [[1, '5']] throughput: 1.0 uops: 1 +- name: vmovd + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] + throughput: 0.2 + uops: 1.0 +- name: vmov + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] + throughput: 0.2 + uops: 1.0 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333 + uops: 1 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333 + uops: 1 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: [kxorb, kxorw, kxord, kxorq, kxnorb, kxnorw, kxnord, kxnorq] + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 diff --git a/osaca/data/v2.yml b/osaca/data/v2.yml index f7e8352..82e0c7d 100644 --- a/osaca/data/v2.yml +++ b/osaca/data/v2.yml @@ -9,11 +9,17 @@ hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 7.0, s: 6.0, d: 6.0, q: 6.0, v: 6.0, z: 6.0} p_index_latency: 1 load_throughput: +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]} +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} load_throughput_default: [[1, ['12', '13', '14']]] store_throughput: +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]} +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} @@ -25,18 +31,18 @@ port_model_scheme: | +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 0 |BR0 1 |BR1 2 |ISC0 3 |ISC1 4 |ISC2 5 |ISC3 6 |IMC0 7 |IMC1 8 |FP0 9 |FP1 10 |FP2 11 |FP3 12 |LDST 13 |LDST 14 |LD 15 |ST 16 |ST \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ - +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ +-------+ +----+ +-------+ +-------+ +----+ +-------+ +-----+ +-----+ +-----+ +-----+ +-----+ - | BR | | BR | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | | DV | |SIMD/FP| |FPDV| |SIMD/FP| |SIMD/FP| |FPDV| |SIMD/FP| | LD | | LD | | LD | | ST | | ST | - +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ | ALU | +----+ | ALU | | ALU | +----+ | ALU | +-----+ +-----+ +-----+ +-----+ +-----+ - silly silly +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-----+ +-----+ - | MUL | | MUL | +-------+ +-------+ +-------+ +-------+ | AGU | | AGU | - +------+ +------+ |SIMD/FP| |SIMD/FP| |SIMD/FP| |SIMD/FP| +-----+ +-----+ - +------+ +------+ | MISC | | MISC | | MISC | | MISC | - | CRC | | CRC | +-------+ +-------+ +-------+ +-------+ - +------+ +------+ +-------+ +-------+ +-------+ +-------+ - +------+ +------+ | SIMD | | SIMD | | SIMD | | SIMD | - | SHIFT| | SHIFT| |INT MUL| | SHIFT| |INT MUL| | SHIFT| - +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ +-------+ +----+ +-------+ +-------+ +----+ +-------+ +-----+ +-----+ +-----+ +-----+ +-----+ + | BR | | BR | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | | DV | |SIMD/FP| |FPDV| |SIMD/FP| |SIMD/FP| |FPDV| |SIMD/FP| | LD | | LD | | LD | | ST | | ST | + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ | ALU | +----+ | ALU | | ALU | +----+ | ALU | +-----+ +-----+ +-----+ +-----+ +-----+ + silly silly +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-----+ +-----+ + | MUL | | MUL | +-------+ +-------+ +-------+ +-------+ | AGU | | AGU | + +------+ +------+ |SIMD/FP| |SIMD/FP| |SIMD/FP| |SIMD/FP| +-----+ +-----+ + +------+ +------+ | MISC | | MISC | | MISC | | MISC | + | CRC | | CRC | +-------+ +-------+ +-------+ +-------+ + +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +------+ +------+ | SIMD | | SIMD | | SIMD | | SIMD | + | SHIFT| | SHIFT| |INT MUL| | SHIFT| |INT MUL| | SHIFT| + +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | FPconv| | ST | | FPconv| +-------+ +-------+ +-------+ @@ -116,7 +122,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: register @@ -127,7 +133,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: immediate @@ -138,7 +144,7 @@ instruction_forms: - name: adr operands: - class: register - prefix: '*' + prefix: '*' - class: identifier throughput: 0.25 latency: ~ # 1*p67 @@ -1520,7 +1526,7 @@ instruction_forms: throughput: 0.0 latency: 0 # 0*p port_pressure: [] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1531,7 +1537,7 @@ instruction_forms: throughput: 0.1666666 latency: 1.0 # 1*234567 port_pressure: [[1, '234567']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1542,7 +1548,7 @@ instruction_forms: throughput: 0.25 latency: 1.0 # 1*p2367 port_pressure: [[1, '2367']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1553,7 +1559,7 @@ instruction_forms: throughput: 0.1666666 latency: 1.0 # 1*p234567 port_pressure: [[1, '234567']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1595,8 +1601,8 @@ instruction_forms: latency: ~ port_pressure: [] - name: ret - operands: - - class: identifier + operands: + - class: identifier throughput: 0.0 latency: ~ port_pressure: [] @@ -1662,7 +1668,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w throughput: 1.0 @@ -1671,7 +1677,16 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d + - class: register + prefix: w + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d - class: register prefix: x throughput: 1.0 @@ -1680,7 +1695,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x - class: immediate @@ -1691,7 +1706,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w - class: immediate @@ -1719,6 +1734,8 @@ instruction_forms: - class: register prefix: w throughput: 5.0 + latency: 5.0 # 2*p67DV + port_pressure: [[1, '67'], [10, ['6DV', '7DV']]] - name: [smaddl, smsubl, umaddl, umsubl] operands: - class: register @@ -1778,7 +1795,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1792,7 +1809,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1806,7 +1823,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1820,7 +1837,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1834,7 +1851,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1848,7 +1865,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1864,7 +1881,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1880,7 +1897,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1896,7 +1913,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1912,7 +1929,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1928,7 +1945,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1944,7 +1961,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1960,7 +1977,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1976,7 +1993,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1992,7 +2009,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2008,7 +2025,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2024,7 +2041,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2040,7 +2057,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2056,7 +2073,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2072,7 +2089,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2088,7 +2105,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2104,7 +2121,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2120,7 +2137,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2136,7 +2153,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2152,7 +2169,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2168,7 +2185,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2184,7 +2201,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2200,7 +2217,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2216,7 +2233,7 @@ instruction_forms: pre-indexed: true throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2232,7 +2249,7 @@ instruction_forms: pre-indexed: true throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2248,7 +2265,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2264,7 +2281,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2280,7 +2297,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2296,7 +2313,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2312,7 +2329,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2322,7 +2339,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2332,7 +2349,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2342,7 +2359,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2352,7 +2369,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2362,7 +2379,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2372,7 +2389,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2384,7 +2401,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2396,7 +2413,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2408,7 +2425,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2420,7 +2437,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2432,7 +2449,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2444,7 +2461,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2456,7 +2473,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2468,7 +2485,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2480,7 +2497,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2492,7 +2509,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2504,7 +2521,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2516,7 +2533,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2528,7 +2545,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2540,7 +2557,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2552,7 +2569,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2564,7 +2581,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2576,7 +2593,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2588,7 +2605,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2600,7 +2617,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2612,7 +2629,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2624,7 +2641,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2636,7 +2653,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2648,7 +2665,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2660,7 +2677,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2676,7 +2693,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: sub operands: - class: register @@ -2780,9 +2797,9 @@ instruction_forms: prefix: "*" - class: register prefix: "*" - - class: immediate + - class: immediate imd: int - - class: immediate + - class: immediate imd: int throughput: 0.25 latency: 1.0 # 1*p2367 @@ -2823,7 +2840,22 @@ instruction_forms: shape: '*' width: '*' - class: immediate - imd: int + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fadd + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: immediate + imd: '*' throughput: 0.25 latency: 2.0 # 1*p8,9,10,11 port_pressure: [[1, ['8', '9', '10', '11']]] @@ -2860,8 +2892,8 @@ instruction_forms: - class: register prefix: s - class: immediate - imd: int - - class: condition + imd: '*' + - class: condition ccode: "*" throughput: 1.0 latency: 1.0 # 1*p8 @@ -2928,7 +2960,7 @@ instruction_forms: shape: d width: '*' throughput: 5.0 - latency: 12.0 # 1*p67 + latency: 12.0 # 1*p8,10 port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]] - name: fdiv operands: @@ -4162,7 +4194,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[3, ['12', '13', '14']]] + port_pressure: [[1, ['12', '13', '14']]] - name: [ld1d, ld1sw, ld1sh, ld1sb] operands: - class: register @@ -4180,7 +4212,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1sw, ld1sh, ld1sb] operands: - class: register @@ -4198,7 +4230,7 @@ instruction_forms: post-indexed: true throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4216,7 +4248,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4234,7 +4266,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4252,15 +4284,15 @@ instruction_forms: post-indexed: true throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4277,11 +4309,11 @@ instruction_forms: - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4298,11 +4330,11 @@ instruction_forms: - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4319,11 +4351,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4340,11 +4372,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4361,11 +4393,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4486,15 +4518,15 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[2, '89'], [1, ['12','13']]] + port_pressure: [[2, ['15','16']], [1, ['12','13']]] - name: [st2d, st2w, st2b, st2h] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4507,15 +4539,15 @@ instruction_forms: post-indexed: false throughput: 2.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[2, '89'], [1, ['12','13']]] + port_pressure: [[2, ['15','16']], [1, ['12','13']]] - name: [st3d, st3w, st3b, st3h] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4528,7 +4560,7 @@ instruction_forms: post-indexed: false throughput: 2.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[4, '89'], [1, ['12','13']]] + port_pressure: [[4, ['15','16']], [1, ['12','13']]] - name: tbl operands: - class: register @@ -4572,7 +4604,7 @@ instruction_forms: throughput: 0.25 latency: 2.0 # 2*p89,10,11 port_pressure: [[1, ['8','9','10','11']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4585,7 +4617,7 @@ instruction_forms: throughput: 1.0 latency: 4.0 port_pressure: [[2, ['8','10']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4598,7 +4630,7 @@ instruction_forms: throughput: 2.0 latency: 6.0 port_pressure: [[4, ['8','10']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4611,3 +4643,103 @@ instruction_forms: throughput: 0.5 latency: 3.0 port_pressure: [[1, ['8','10']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + - class: register + prefix: z + shape: s + throughput: 0.5 + latency: 3.0 + port_pressure: [[1, ['8','10']]] +- name: [fdiv, fdivr] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 3.0 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [6, ['8DV','10DV']]] +- name: fadd + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fadd + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: '*' + width: '*' + - class: immediate + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: add + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + - class: immediate + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: add + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]]