From f61786abbec16d724ed217cb7358914dd396c8d4 Mon Sep 17 00:00:00 2001 From: tojauch Date: Thu, 11 Jul 2024 16:05:42 +0200 Subject: [PATCH] fixed typo in file name --- src/main/scala/Verilog_Generator.scala | 13 ++++++++++++ src/main/scala/Veriolog_Generator.scala | 28 ------------------------- 2 files changed, 13 insertions(+), 28 deletions(-) create mode 100755 src/main/scala/Verilog_Generator.scala delete mode 100755 src/main/scala/Veriolog_Generator.scala diff --git a/src/main/scala/Verilog_Generator.scala b/src/main/scala/Verilog_Generator.scala new file mode 100755 index 0000000..a24bb51 --- /dev/null +++ b/src/main/scala/Verilog_Generator.scala @@ -0,0 +1,13 @@ +package main.scala + +import chisel3._ +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec + + +import RISCV_TOP._ + +object VerilogGen extends App +{ + emitVerilog(new RISCV_TOP(), Array("--target-dir", "generated-src")) +} diff --git a/src/main/scala/Veriolog_Generator.scala b/src/main/scala/Veriolog_Generator.scala deleted file mode 100755 index b47235f..0000000 --- a/src/main/scala/Veriolog_Generator.scala +++ /dev/null @@ -1,28 +0,0 @@ -package main.scala - -import chisel3._ -import chiseltest._ -import org.scalatest.flatspec.AnyFlatSpec - - -import RISCV_TOP._ - -object VerilogGen extends App -{ - emitVerilog(new RISCV_TOP(), Array("--target-dir", "generated-src")) - //emitVerilog(new top_MC.top_MC("src/test/programs/beq_test", "src/main/scala/DataMemory/dataMemVals"), Array("--target-dir", "generated-src")) - //(new chisel3.stage.ChiselStage).emitVerilog(new RISCV_TOP) - // (new chisel3.stage.ChiselStage).emitVerilog(new bool()) - // - // (new chisel3.stage.ChiselStage).emitVerilog(new Control()) - // (new chisel3.stage.ChiselStage).emitVerilog(new DataMemory()) - // - // (new chisel3.stage.ChiselStage).emitVerilog(new DataPath()) - // (new chisel3.stage.ChiselStage).emitVerilog(new ExtenionUnit()) - // (new chisel3.stage.ChiselStage).emitVerilog(new registerFile()) - // (new chisel3.stage.ChiselStage).emitVerilog(new InstructionMemory()) - // (new chisel3.stage.ChiselStage).emitVerilog(new PC()) - // (new chisel3.stage.ChiselStage).emitVerilog(new DataMemory()) - //emitVerilog(new MDU.MDU, Array("--target-dir", "generated-src")) - -}